diff --git a/Cargo.lock b/Cargo.lock index 686b98cf6128..3b56dd6bd9ce 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -649,11 +649,11 @@ checksum = "a1d728cc89cf3aee9ff92b05e62b19ee65a02b5702cff7d5a377e32c6ae29d8d" [[package]] name = "clippy" -version = "0.1.96" +version = "0.1.97" dependencies = [ "anstream", "askama", - "cargo_metadata 0.18.1", + "cargo_metadata 0.23.1", "clippy_config", "clippy_lints", "clippy_lints_internal", @@ -676,7 +676,7 @@ dependencies = [ [[package]] name = "clippy_config" -version = "0.1.96" +version = "0.1.97" dependencies = [ "clippy_utils", "itertools", @@ -700,10 +700,10 @@ dependencies = [ [[package]] name = "clippy_lints" -version = "0.1.96" +version = "0.1.97" dependencies = [ "arrayvec", - "cargo_metadata 0.18.1", + "cargo_metadata 0.23.1", "clippy_config", "clippy_utils", "declare_clippy_lint", @@ -732,7 +732,7 @@ dependencies = [ [[package]] name = "clippy_utils" -version = "0.1.96" +version = "0.1.97" dependencies = [ "arrayvec", "itertools", @@ -1136,7 +1136,7 @@ dependencies = [ [[package]] name = "declare_clippy_lint" -version = "0.1.96" +version = "0.1.97" [[package]] name = "derive-where" @@ -1677,6 +1677,15 @@ dependencies = [ "serde_core", ] +[[package]] +name = "hashbrown" +version = "0.17.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4f467dd6dccf739c208452f8014c75c18bb8301b050ad1cfb27153803edb0f51" +dependencies = [ + "foldhash 0.2.0", +] + [[package]] name = "heck" version = "0.4.1" @@ -1953,12 +1962,12 @@ checksum = "964de6e86d545b246d84badc0fef527924ace5134f30641c203ef52ba83f58d5" [[package]] name = "indexmap" -version = "2.13.0" +version = "2.14.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017" +checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" dependencies = [ "equivalent", - "hashbrown 0.16.1", + "hashbrown 0.17.0", "serde", "serde_core", ] @@ -3505,6 +3514,7 @@ dependencies = [ "rand_xoshiro", "rustc_data_structures", "rustc_error_messages", + "rustc_errors", "rustc_hashes", "rustc_index", "rustc_macros", @@ -3805,7 +3815,7 @@ dependencies = [ "either", "elsa", "ena", - "hashbrown 0.16.1", + "hashbrown 0.17.0", "indexmap", "jobserver", "libc", @@ -3909,7 +3919,6 @@ dependencies = [ "anstream", "anstyle", "derive_setters", - "rustc_abi", "rustc_ast", "rustc_data_structures", "rustc_error_codes", @@ -3995,6 +4004,7 @@ dependencies = [ "rustc_ast_pretty", "rustc_data_structures", "rustc_error_messages", + "rustc_errors", "rustc_hashes", "rustc_hir_id", "rustc_index", @@ -4224,6 +4234,7 @@ dependencies = [ name = "rustc_lint_defs" version = "0.0.0" dependencies = [ + "rustc_ast", "rustc_data_structures", "rustc_error_messages", "rustc_hir_id", @@ -4568,7 +4579,6 @@ name = "rustc_query_impl" version = "0.0.0" dependencies = [ "measureme", - "rustc_abi", "rustc_data_structures", "rustc_errors", "rustc_hir", @@ -4691,7 +4701,6 @@ dependencies = [ "rustc-demangle", "rustc_abi", "rustc_data_structures", - "rustc_errors", "rustc_hashes", "rustc_hir", "rustc_middle", @@ -5540,9 +5549,9 @@ dependencies = [ [[package]] name = "thin-vec" -version = "0.2.14" +version = "0.2.15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "144f754d318415ac792f9d69fc87abbbfc043ce2ef041c60f16ad828f638717d" +checksum = "da322882471314edc77fa5232c587bcb87c9df52bfd0d7d4826f8868ead61899" [[package]] name = "thiserror" diff --git a/RELEASES.md b/RELEASES.md index c396cd8069d6..87768b2f74e7 100644 --- a/RELEASES.md +++ b/RELEASES.md @@ -1,3 +1,140 @@ +Version 1.95.0 (2026-04-16) +=========================== + + + +Language +-------- +- [Stabilize `if let` guards on match arms](https://github.com/rust-lang/rust/pull/141295) +- [`irrefutable_let_patterns` lint no longer lints on let chains](https://github.com/rust-lang/rust/pull/146832) +- [Support importing path-segment keywords with renaming](https://github.com/rust-lang/rust/pull/146972) +- [Stabilize inline assembly for PowerPC and PowerPC64](https://github.com/rust-lang/rust/pull/147996) +- [const-eval: be more consistent in the behavior of padding during typed copies](https://github.com/rust-lang/rust/pull/148967) +- [Const blocks are no longer evaluated to determine if expressions involving fallible operations can implicitly be constant-promoted.](https://github.com/rust-lang/rust/pull/150557). Expressions whose ability to implicitly be promoted would depend on the result of a const block are no longer implicitly promoted. +- [Make operational semantics of pattern matching independent of crate and module](https://github.com/rust-lang/rust/pull/150681) + + + + +Compiler +-------- + +- [Stabilize `--remap-path-scope` for controlling the scoping of how paths get remapped in the resulting binary](https://github.com/rust-lang/rust/pull/147611) +- [Apply patches for CVE-2026-6042 and CVE-2026-40200 to vendored musl](https://github.com/rust-lang/rust/pull/155171) + + + +Platform Support +---------------- +- [Promote `powerpc64-unknown-linux-musl` to Tier 2 with host tools](https://github.com/rust-lang/rust/pull/149962) +- [Promote `aarch64-apple-tvos` to Tier 2](https://github.com/rust-lang/rust/pull/152021) +- [Promote `aarch64-apple-tvos-sim` to Tier 2](https://github.com/rust-lang/rust/pull/152021) +- [Promote `aarch64-apple-watchos` to Tier 2](https://github.com/rust-lang/rust/pull/152021) +- [Promote `aarch64-apple-watchos-sim` to Tier 2](https://github.com/rust-lang/rust/pull/152021) +- [Promote `aarch64-apple-visionos` to Tier 2](https://github.com/rust-lang/rust/pull/152021) +- [Promote `aarch64-apple-visionos-sim` to Tier 2](https://github.com/rust-lang/rust/pull/152021) + + +Refer to Rust's [platform support page][platform-support-doc] +for more information on Rust's tiered platform support. + +[platform-support-doc]: https://doc.rust-lang.org/rustc/platform-support.html + + + +Libraries +--------- +- [`thread::scope`: document how join interacts with TLS destructors](https://github.com/rust-lang/rust/pull/149482) +- [Speed up `str::contains` on aarch64 targets with `neon` target feature enabled by default](https://github.com/rust-lang/rust/pull/152176) + + + + +Stabilized APIs +--------------- + +- [`MaybeUninit<[T; N]>: From<[MaybeUninit; N]>`](https://doc.rust-lang.org/stable/std/mem/union.MaybeUninit.html#impl-From%3CMaybeUninit%3C%5BT;+N%5D%3E%3E-for-%5BMaybeUninit%3CT%3E;+N%5D) +- [`MaybeUninit<[T; N]>: AsRef<[MaybeUninit; N]>`](https://doc.rust-lang.org/stable/std/mem/union.MaybeUninit.html#impl-AsRef%3C%5BMaybeUninit%3CT%3E;+N%5D%3E-for-MaybeUninit%3C%5BT;+N%5D%3E) +- [`MaybeUninit<[T; N]>: AsRef<[MaybeUninit]>`](https://doc.rust-lang.org/stable/std/mem/union.MaybeUninit.html#impl-AsRef%3C%5BMaybeUninit%3CT%3E%5D%3E-for-MaybeUninit%3C%5BT;+N%5D%3E) +- [`MaybeUninit<[T; N]>: AsMut<[MaybeUninit; N]>`](https://doc.rust-lang.org/beta/std/mem/union.MaybeUninit.html#impl-AsMut%3C%5BMaybeUninit%3CT%3E;+N%5D%3E-for-MaybeUninit%3C%5BT;+N%5D%3E) +- [`MaybeUninit<[T; N]>: AsMut<[MaybeUninit]>`](https://doc.rust-lang.org/stable/std/mem/union.MaybeUninit.html#impl-AsMut%3C%5BMaybeUninit%3CT%3E%5D%3E-for-MaybeUninit%3C%5BT;+N%5D%3E) +- [`[MaybeUninit; N]: From>`](https://doc.rust-lang.org/stable/std/mem/union.MaybeUninit.html#impl-From%3C%5BMaybeUninit%3CT%3E;+N%5D%3E-for-MaybeUninit%3C%5BT;+N%5D%3E) +- [`Cell<[T; N]>: AsRef<[Cell; N]>`](https://doc.rust-lang.org/stable/std/cell/struct.Cell.html#impl-AsRef%3C%5BCell%3CT%3E;+N%5D%3E-for-Cell%3C%5BT;+N%5D%3E) +- [`Cell<[T; N]>: AsRef<[Cell]>`](https://doc.rust-lang.org/stable/std/cell/struct.Cell.html#impl-AsRef%3C%5BCell%3CT%3E%5D%3E-for-Cell%3C%5BT;+N%5D%3E) +- [`Cell<[T]>: AsRef<[Cell]>`](https://doc.rust-lang.org/stable/std/cell/struct.Cell.html#impl-AsRef%3C%5BCell%3CT%3E%5D%3E-for-Cell%3C%5BT%5D%3E) +- [`bool: TryFrom<{integer}>`](https://doc.rust-lang.org/stable/std/primitive.bool.html#impl-TryFrom%3Cu128%3E-for-bool) +- [`AtomicPtr::update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicPtr.html#method.update) +- [`AtomicPtr::try_update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicPtr.html#method.try_update) +- [`AtomicBool::update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicBool.html#method.update) +- [`AtomicBool::try_update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicBool.html#method.try_update) +- [`AtomicIn::update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicIsize.html#method.update) +- [`AtomicIn::try_update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicIsize.html#method.try_update) +- [`AtomicUn::update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicUsize.html#method.update) +- [`AtomicUn::try_update`](https://doc.rust-lang.org/stable/std/sync/atomic/struct.AtomicUsize.html#method.try_update) +- [`cfg_select!`](https://doc.rust-lang.org/stable/std/macro.cfg_select.html) +- [`mod core::range`](https://doc.rust-lang.org/stable/core/range/index.html) +- [`core::range::RangeInclusive`](https://doc.rust-lang.org/stable/core/range/struct.RangeInclusive.html) +- [`core::range::RangeInclusiveIter`](https://doc.rust-lang.org/stable/core/range/struct.RangeInclusiveIter.html) +- [`core::hint::cold_path`](https://doc.rust-lang.org/stable/core/hint/fn.cold_path.html) +- [`<*const T>::as_ref_unchecked`](https://doc.rust-lang.org/stable/std/primitive.pointer.html#method.as_ref_unchecked) +- [`<*mut T>::as_ref_unchecked`](https://doc.rust-lang.org/stable/std/primitive.pointer.html#method.as_ref_unchecked-1) +- [`<*mut T>::as_mut_unchecked`](https://doc.rust-lang.org/stable/std/primitive.pointer.html#method.as_mut_unchecked) +- [`Vec::push_mut`](https://doc.rust-lang.org/stable/std/vec/struct.Vec.html#method.push_mut) +- [`Vec::insert_mut`](https://doc.rust-lang.org/stable/std/vec/struct.Vec.html#method.insert_mut) +- [`VecDeque::push_front_mut`](https://doc.rust-lang.org/stable/std/collections/struct.VecDeque.html#method.push_front_mut) +- [`VecDeque::push_back_mut`](https://doc.rust-lang.org/stable/std/collections/struct.VecDeque.html#method.push_back_mut) +- [`VecDeque::insert_mut`](https://doc.rust-lang.org/stable/std/collections/struct.VecDeque.html#method.insert_mut) +- [`LinkedList::push_front_mut`](https://doc.rust-lang.org/stable/std/collections/struct.LinkedList.html#method.push_front_mut) +- [`LinkedList::push_back_mut`](https://doc.rust-lang.org/stable/std/collections/struct.LinkedList.html#method.push_back_mut) +- [`Layout::dangling_ptr`](https://doc.rust-lang.org/stable/std/alloc/struct.Layout.html#method.dangling_ptr) +- [`Layout::repeat`](https://doc.rust-lang.org/stable/std/alloc/struct.Layout.html#method.repeat) +- [`Layout::repeat_packed`](https://doc.rust-lang.org/stable/std/alloc/struct.Layout.html#method.repeat_packed) +- [`Layout::extend_packed`](https://doc.rust-lang.org/stable/std/alloc/struct.Layout.html#method.extend_packed) + +These previously stable APIs are now stable in const contexts: + +- [`fmt::from_fn`](https://doc.rust-lang.org/stable/std/fmt/fn.from_fn.html) +- [`ControlFlow::is_break`](https://doc.rust-lang.org/stable/core/ops/enum.ControlFlow.html#method.is_break) +- [`ControlFlow::is_continue`](https://doc.rust-lang.org/stable/core/ops/enum.ControlFlow.html#method.is_continue) + + + +Rustdoc +----- +- [In search results, rank unstable items lower](https://github.com/rust-lang/rust/pull/149460) +- [Add new "hide deprecated items" setting in rustdoc](https://github.com/rust-lang/rust/pull/151091) + + + +Compatibility Notes +------------------- +- [Array coercions may now result in less inference constraints than before](https://github.com/rust-lang/rust/pull/140283) +- Importing `$crate` without renaming, i.e. `use $crate::{self};`, is now no longer permitted due to stricter error checking for `self` imports. +- [const-eval: be more consistent in the behavior of padding during typed copies.](https://github.com/rust-lang/rust/pull/148967) + In very rare cases, this may cause compilation errors due to bytes from parts of a pointer ending up in the padding bytes of a `const` or `static`. +- [A future-incompatibility warning lint `ambiguous_glob_imported_traits` is now reported when using an ambiguously glob imported trait](https://github.com/rust-lang/rust/pull/149058) +- [Check lifetime bounds of types mentioning only type parameters](https://github.com/rust-lang/rust/pull/149389) +- [Report more visibility-related ambiguous import errors](https://github.com/rust-lang/rust/pull/149596) +- [Deprecate `Eq::assert_receiver_is_total_eq` and emit future compatibility warnings on manual impls](https://github.com/rust-lang/rust/pull/149978) +- [powerpc64: Use the ELF ABI version set in target spec instead of guessing](https://github.com/rust-lang/rust/pull/150468) (fixes the ELF ABI used by the OpenBSD target) +- Matching on a `#[non_exhaustive]` enum [now reads the discriminant, even if the enum has only one variant](https://github.com/rust-lang/rust/pull/150681). This can cause closures to capture values that they previously wouldn't. +- `mut ref` and `mut ref mut` patterns, part of the unstable [Match Ergonomics 2024 RFC](https://github.com/rust-lang/rust/issues/123076), were accidentally allowed on stable within struct pattern field shorthand. These patterns are now correctly feature-gated as unstable in this position. +- [Add future-compatibility warning for derive helper attributes which conflict with built-in attributes](https://github.com/rust-lang/rust/pull/151152) +- [JSON target specs](https://doc.rust-lang.org/rustc/targets/custom.html) have been destabilized and now require `-Z unstable-options` to use. Previously, they could not be used without the standard library, which has no stable build mechanism. In preparation for the `build-std` project adding that support, JSON target specs are being proactively gated to ensure they remain unstable even if `build-std` is stabilized. Cargo now includes the `-Z json-target-spec` CLI flag to automatically pass `-Z unstable-options` to the compiler when needed. See [#150151](https://github.com/rust-lang/rust/pull/150151), [#151534](https://github.com/rust-lang/rust/pull/150151), and [rust-lang/cargo#16557](https://github.com/rust-lang/cargo/pull/16557). +- [The arguments of `#[feature]` attributes on invalid targets are now checked](https://github.com/rust-lang/rust/issues/153764) + + + +Internal Changes +---------------- + +These changes do not affect any public interfaces of Rust, but they represent +significant improvements to the performance or internals of rustc and related +tools. + +- [Update to LLVM 22](https://github.com/rust-lang/rust/pull/150722) + + Version 1.94.1 (2026-03-26) =========================== diff --git a/compiler/rustc_abi/Cargo.toml b/compiler/rustc_abi/Cargo.toml index 83d96d8d04da..13e0bd8703d9 100644 --- a/compiler/rustc_abi/Cargo.toml +++ b/compiler/rustc_abi/Cargo.toml @@ -10,6 +10,7 @@ rand = { version = "0.9.0", default-features = false, optional = true } rand_xoshiro = { version = "0.7.0", optional = true } rustc_data_structures = { path = "../rustc_data_structures", optional = true } rustc_error_messages = { path = "../rustc_error_messages", optional = true } +rustc_errors = { path = "../rustc_errors", optional = true } rustc_hashes = { path = "../rustc_hashes" } rustc_index = { path = "../rustc_index", default-features = false } rustc_macros = { path = "../rustc_macros", optional = true } @@ -21,11 +22,12 @@ tracing = "0.1" [features] # tidy-alphabetical-start default = ["nightly", "randomize"] -# rust-analyzer depends on this crate and we therefore require it to built on a stable toolchain -# without depending on rustc_data_structures, rustc_macros and rustc_serialize +# rust-analyzer depends on this crate and we therefore require it to build on a stable toolchain +# without depending on the rustc_* crates in the following list. nightly = [ "dep:rustc_data_structures", "dep:rustc_error_messages", + "dep:rustc_errors", "dep:rustc_macros", "dep:rustc_serialize", "dep:rustc_span", diff --git a/compiler/rustc_abi/src/callconv.rs b/compiler/rustc_abi/src/callconv.rs index 7ad7088b3089..d6594e277f00 100644 --- a/compiler/rustc_abi/src/callconv.rs +++ b/compiler/rustc_abi/src/callconv.rs @@ -75,10 +75,11 @@ pub fn homogeneous_aggregate(&self, cx: &C) -> Result { + BackendRepr::SimdVector { element, count: _ } => { assert!(!self.is_zst()); + Ok(HomogeneousAggregate::Homogeneous(Reg { - kind: RegKind::Vector, + kind: RegKind::Vector { hint_vector_elem: element.primitive() }, size: self.size, })) } diff --git a/compiler/rustc_abi/src/callconv/reg.rs b/compiler/rustc_abi/src/callconv/reg.rs index 66d4dca00726..c30425fb703a 100644 --- a/compiler/rustc_abi/src/callconv/reg.rs +++ b/compiler/rustc_abi/src/callconv/reg.rs @@ -1,14 +1,19 @@ #[cfg(feature = "nightly")] use rustc_macros::HashStable_Generic; -use crate::{Align, HasDataLayout, Size}; +use crate::{Align, HasDataLayout, Integer, Primitive, Size}; #[cfg_attr(feature = "nightly", derive(HashStable_Generic))] #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] pub enum RegKind { Integer, Float, - Vector, + Vector { + /// The `hint_vector_elem` is strictly for optimization purposes. E.g. it can be used by + /// a codegen backend to prevent extra bitcasts that obscure a pattern. Alternatively, + /// it can be safely ignored by always picking i8. + hint_vector_elem: Primitive, + }, } #[cfg_attr(feature = "nightly", derive(HashStable_Generic))] @@ -36,6 +41,12 @@ impl Reg { reg_ctor!(f32, Float, 32); reg_ctor!(f64, Float, 64); reg_ctor!(f128, Float, 128); + + /// A vector of the given size with an unknown (and irrelevant) element type. + pub fn opaque_vector(size: Size) -> Reg { + // Default to an i8 vector of the given size. + Reg { kind: RegKind::Vector { hint_vector_elem: Primitive::Int(Integer::I8, true) }, size } + } } impl Reg { @@ -58,7 +69,7 @@ pub fn align(&self, cx: &C) -> Align { 128 => dl.f128_align, _ => panic!("unsupported float: {self:?}"), }, - RegKind::Vector => dl.llvmlike_vector_align(self.size), + RegKind::Vector { .. } => dl.llvmlike_vector_align(self.size), } } } diff --git a/compiler/rustc_abi/src/extern_abi.rs b/compiler/rustc_abi/src/extern_abi.rs index 9173245d8aa4..95ba2ee3b78f 100644 --- a/compiler/rustc_abi/src/extern_abi.rs +++ b/compiler/rustc_abi/src/extern_abi.rs @@ -131,6 +131,29 @@ pub const fn as_str(&self) -> &'static str { $($e_name::$variant $( { unwind: $uw } )* => $tok,)* } } + // FIXME(FnSigKind): when PartialEq is stably const, use it instead + const fn internal_const_eq(&self, other: &Self) -> bool { + match (self, other) { + $( ( $e_name::$variant $( { unwind: $uw } )* , $e_name::$variant $( { unwind: $uw } )* ) => true,)* + _ => false, + } + } + // ALL_VARIANTS.iter().position(|v| v == self), but const + pub const fn as_packed(&self) -> u8 { + let mut index = 0; + while index < $e_name::ALL_VARIANTS.len() { + if self.internal_const_eq(&$e_name::ALL_VARIANTS[index]) { + return index as u8; + } + index += 1; + } + panic!("unreachable: invalid ExternAbi variant"); + } + pub const fn from_packed(index: u8) -> Self { + let index = index as usize; + assert!(index < $e_name::ALL_VARIANTS.len(), "invalid ExternAbi index"); + $e_name::ALL_VARIANTS[index] + } } impl ::core::str::FromStr for $e_name { diff --git a/compiler/rustc_abi/src/lib.rs b/compiler/rustc_abi/src/lib.rs index f148b776852a..450a93ee8481 100644 --- a/compiler/rustc_abi/src/lib.rs +++ b/compiler/rustc_abi/src/lib.rs @@ -46,10 +46,16 @@ use bitflags::bitflags; #[cfg(feature = "nightly")] use rustc_data_structures::stable_hasher::StableOrd; +#[cfg(feature = "nightly")] +use rustc_error_messages::{DiagArgValue, IntoDiagArg}; +#[cfg(feature = "nightly")] +use rustc_errors::{Diag, DiagCtxtHandle, Diagnostic, EmissionGuarantee, Level, msg}; use rustc_hashes::Hash64; use rustc_index::{Idx, IndexSlice, IndexVec}; #[cfg(feature = "nightly")] use rustc_macros::{Decodable_NoContext, Encodable_NoContext, HashStable_Generic}; +#[cfg(feature = "nightly")] +use rustc_span::{Symbol, sym}; mod callconv; mod canon_abi; @@ -332,7 +338,7 @@ fn default() -> TargetDataLayout { } } -pub enum TargetDataLayoutErrors<'a> { +pub enum TargetDataLayoutError<'a> { InvalidAddressSpace { addr_space: &'a str, cause: &'a str, err: ParseIntError }, InvalidBits { kind: &'a str, bit: &'a str, cause: &'a str, err: ParseIntError }, MissingAlignment { cause: &'a str }, @@ -343,6 +349,51 @@ pub enum TargetDataLayoutErrors<'a> { UnknownPointerSpecification { err: String }, } +#[cfg(feature = "nightly")] +impl Diagnostic<'_, G> for TargetDataLayoutError<'_> { + fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { + match self { + TargetDataLayoutError::InvalidAddressSpace { addr_space, err, cause } => { + Diag::new(dcx, level, msg!("invalid address space `{$addr_space}` for `{$cause}` in \"data-layout\": {$err}")) + .with_arg("addr_space", addr_space) + .with_arg("cause", cause) + .with_arg("err", err) + } + TargetDataLayoutError::InvalidBits { kind, bit, cause, err } => { + Diag::new(dcx, level, msg!("invalid {$kind} `{$bit}` for `{$cause}` in \"data-layout\": {$err}")) + .with_arg("kind", kind) + .with_arg("bit", bit) + .with_arg("cause", cause) + .with_arg("err", err) + } + TargetDataLayoutError::MissingAlignment { cause } => { + Diag::new(dcx, level, msg!("missing alignment for `{$cause}` in \"data-layout\"")) + .with_arg("cause", cause) + } + TargetDataLayoutError::InvalidAlignment { cause, err } => { + Diag::new(dcx, level, msg!("invalid alignment for `{$cause}` in \"data-layout\": {$err}")) + .with_arg("cause", cause) + .with_arg("err", err.to_string()) + } + TargetDataLayoutError::InconsistentTargetArchitecture { dl, target } => { + Diag::new(dcx, level, msg!("inconsistent target specification: \"data-layout\" claims architecture is {$dl}-endian, while \"target-endian\" is `{$target}`")) + .with_arg("dl", dl).with_arg("target", target) + } + TargetDataLayoutError::InconsistentTargetPointerWidth { pointer_size, target } => { + Diag::new(dcx, level, msg!("inconsistent target specification: \"data-layout\" claims pointers are {$pointer_size}-bit, while \"target-pointer-width\" is `{$target}`")) + .with_arg("pointer_size", pointer_size).with_arg("target", target) + } + TargetDataLayoutError::InvalidBitsSize { err } => { + Diag::new(dcx, level, msg!("{$err}")).with_arg("err", err) + } + TargetDataLayoutError::UnknownPointerSpecification { err } => { + Diag::new(dcx, level, msg!("unknown pointer specification `{$err}` in datalayout string")) + .with_arg("err", err) + } + } + } +} + impl TargetDataLayout { /// Parse data layout from an /// [llvm data layout string](https://llvm.org/docs/LangRef.html#data-layout) @@ -352,17 +403,17 @@ impl TargetDataLayout { pub fn parse_from_llvm_datalayout_string<'a>( input: &'a str, default_address_space: AddressSpace, - ) -> Result> { + ) -> Result> { // Parse an address space index from a string. let parse_address_space = |s: &'a str, cause: &'a str| { s.parse::().map(AddressSpace).map_err(|err| { - TargetDataLayoutErrors::InvalidAddressSpace { addr_space: s, cause, err } + TargetDataLayoutError::InvalidAddressSpace { addr_space: s, cause, err } }) }; // Parse a bit count from a string. let parse_bits = |s: &'a str, kind: &'a str, cause: &'a str| { - s.parse::().map_err(|err| TargetDataLayoutErrors::InvalidBits { + s.parse::().map_err(|err| TargetDataLayoutError::InvalidBits { kind, bit: s, cause, @@ -378,7 +429,7 @@ pub fn parse_from_llvm_datalayout_string<'a>( let parse_align_str = |s: &'a str, cause: &'a str| { let align_from_bits = |bits| { Align::from_bits(bits) - .map_err(|err| TargetDataLayoutErrors::InvalidAlignment { cause, err }) + .map_err(|err| TargetDataLayoutError::InvalidAlignment { cause, err }) }; let abi = parse_bits(s, "alignment", cause)?; Ok(align_from_bits(abi)?) @@ -388,7 +439,7 @@ pub fn parse_from_llvm_datalayout_string<'a>( // ignoring the secondary alignment specifications. let parse_align_seq = |s: &[&'a str], cause: &'a str| { if s.is_empty() { - return Err(TargetDataLayoutErrors::MissingAlignment { cause }); + return Err(TargetDataLayoutError::MissingAlignment { cause }); } parse_align_str(s[0], cause) }; @@ -426,7 +477,7 @@ pub fn parse_from_llvm_datalayout_string<'a>( // However, we currently don't take into account further specifications: // an error is emitted instead. if p.starts_with(char::is_alphabetic) { - return Err(TargetDataLayoutErrors::UnknownPointerSpecification { + return Err(TargetDataLayoutError::UnknownPointerSpecification { err: p.to_string(), }); } @@ -471,7 +522,7 @@ pub fn parse_from_llvm_datalayout_string<'a>( // However, we currently don't take into account further specifications: // an error is emitted instead. if p.starts_with(char::is_alphabetic) { - return Err(TargetDataLayoutErrors::UnknownPointerSpecification { + return Err(TargetDataLayoutError::UnknownPointerSpecification { err: p.to_string(), }); } @@ -723,6 +774,14 @@ pub fn as_str(&self) -> &'static str { Self::Big => "big", } } + + #[cfg(feature = "nightly")] + pub fn desc_symbol(&self) -> Symbol { + match self { + Self::Little => sym::little, + Self::Big => sym::big, + } + } } impl fmt::Debug for Endian { @@ -1718,6 +1777,24 @@ pub fn from_field_count(count: usize) -> Option { } } +#[cfg(feature = "nightly")] +impl IntoDiagArg for NumScalableVectors { + fn into_diag_arg(self, _: &mut Option) -> DiagArgValue { + DiagArgValue::Str(std::borrow::Cow::Borrowed(match self.0 { + 0 => panic!("`NumScalableVectors(0)` is illformed"), + 1 => "one", + 2 => "two", + 3 => "three", + 4 => "four", + 5 => "five", + 6 => "six", + 7 => "seven", + 8 => "eight", + _ => panic!("`NumScalableVectors(N)` for N>8 is illformed"), + })) + } +} + /// The way we represent values to the backend /// /// Previously this was conflated with the "ABI" a type is given, as in the platform-specific ABI. diff --git a/compiler/rustc_arena/src/lib.rs b/compiler/rustc_arena/src/lib.rs index 97dd21db07e7..24ade7300c33 100644 --- a/compiler/rustc_arena/src/lib.rs +++ b/compiler/rustc_arena/src/lib.rs @@ -140,25 +140,19 @@ impl TypedArena { /// Allocates an object in the `TypedArena`, returning a reference to it. #[inline] pub fn alloc(&self, object: T) -> &mut T { + assert!(size_of::() != 0); + if self.ptr == self.end { self.grow(1) } unsafe { - if size_of::() == 0 { - self.ptr.set(self.ptr.get().wrapping_byte_add(1)); - let ptr = ptr::NonNull::::dangling().as_ptr(); - // Don't drop the object. This `write` is equivalent to `forget`. - ptr::write(ptr, object); - &mut *ptr - } else { - let ptr = self.ptr.get(); - // Advance the pointer. - self.ptr.set(self.ptr.get().add(1)); - // Write into uninitialized memory. - ptr::write(ptr, object); - &mut *ptr - } + let ptr = self.ptr.get(); + // Advance the pointer. + self.ptr.set(self.ptr.get().add(1)); + // Write into uninitialized memory. + ptr::write(ptr, object); + &mut *ptr } } @@ -287,10 +281,9 @@ fn grow(&self, additional: usize) { // Also ensure that this chunk can fit `additional`. new_cap = cmp::max(additional, new_cap); - let mut chunk = ArenaChunk::::new(new_cap); + let chunk = chunks.push_mut(ArenaChunk::::new(new_cap)); self.ptr.set(chunk.start()); self.end.set(chunk.end()); - chunks.push(chunk); } } @@ -303,16 +296,10 @@ fn clear_last_chunk(&self, last_chunk: &mut ArenaChunk) { let end = self.ptr.get().addr(); // We then calculate the number of elements to be dropped in the last chunk, // which is the filled area's length. - let diff = if size_of::() == 0 { - // `T` is ZST. It can't have a drop flag, so the value here doesn't matter. We get - // the number of zero-sized values in the last and only chunk, just out of caution. - // Recall that `end` was incremented for each allocated value. - end - start - } else { - // FIXME: this should *likely* use `offset_from`, but more - // investigation is needed (including running tests in miri). - (end - start) / size_of::() - }; + assert_ne!(size_of::(), 0); + // FIXME: this should *likely* use `offset_from`, but more + // investigation is needed (including running tests in miri). + let diff = (end - start) / size_of::(); // Pass that to the `destroy` method. unsafe { last_chunk.destroy(diff); @@ -419,7 +406,7 @@ fn grow(&self, layout: Layout) { // Also ensure that this chunk can fit `additional`. new_cap = cmp::max(additional, new_cap); - let mut chunk = ArenaChunk::new(align_up(new_cap, PAGE)); + let chunk = chunks.push_mut(ArenaChunk::new(align_up(new_cap, PAGE))); self.start.set(chunk.start()); // Align the end to DROPLESS_ALIGNMENT. @@ -430,8 +417,6 @@ fn grow(&self, layout: Layout) { debug_assert!(chunk.start().addr() <= end); self.end.set(chunk.end().with_addr(end)); - - chunks.push(chunk); } } diff --git a/compiler/rustc_arena/src/tests.rs b/compiler/rustc_arena/src/tests.rs index eb9406d691b1..751ddd80408a 100644 --- a/compiler/rustc_arena/src/tests.rs +++ b/compiler/rustc_arena/src/tests.rs @@ -22,7 +22,6 @@ fn clear(&mut self) { if let Some(last_chunk) = chunks_borrow.last_mut() { self.clear_last_chunk(last_chunk); let len = chunks_borrow.len(); - // If `T` is ZST, code below has no effect. for mut chunk in chunks_borrow.drain(..len - 1) { chunk.destroy(chunk.entries); } @@ -117,18 +116,6 @@ fn test_noncopy() { } } -#[test] -fn test_typed_arena_zero_sized() { - let arena = TypedArena::default(); - #[cfg(not(miri))] - const N: usize = 100000; - #[cfg(miri)] - const N: usize = 1000; - for _ in 0..N { - arena.alloc(()); - } -} - #[test] fn test_typed_arena_clear() { let mut arena = TypedArena::default(); @@ -207,7 +194,8 @@ fn test_typed_arena_drop_on_clear() { static DROP_COUNTER: Cell = Cell::new(0) } -struct SmallDroppable; +#[allow(unused)] +struct SmallDroppable(u8); impl Drop for SmallDroppable { fn drop(&mut self) { @@ -222,7 +210,7 @@ fn test_typed_arena_drop_small_count() { let arena: TypedArena = TypedArena::default(); for _ in 0..100 { // Allocate something with drop glue to make sure it doesn't leak. - arena.alloc(SmallDroppable); + arena.alloc(SmallDroppable(0)); } // dropping }; diff --git a/compiler/rustc_ast/Cargo.toml b/compiler/rustc_ast/Cargo.toml index 471a6bf1df13..97256963118f 100644 --- a/compiler/rustc_ast/Cargo.toml +++ b/compiler/rustc_ast/Cargo.toml @@ -15,6 +15,6 @@ rustc_macros = { path = "../rustc_macros" } rustc_serialize = { path = "../rustc_serialize" } rustc_span = { path = "../rustc_span" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_ast/src/ast.rs b/compiler/rustc_ast/src/ast.rs index ae4989fcbc6c..b2c573c23f89 100644 --- a/compiler/rustc_ast/src/ast.rs +++ b/compiler/rustc_ast/src/ast.rs @@ -3901,12 +3901,17 @@ pub struct Delegation { pub from_glob: bool, } +#[derive(Clone, Encodable, Decodable, Debug, Walkable)] +pub enum DelegationSuffixes { + List(ThinVec<(Ident, Option)>), + Glob(Span), +} + #[derive(Clone, Encodable, Decodable, Debug, Walkable)] pub struct DelegationMac { pub qself: Option>, pub prefix: Path, - // Some for list delegation, and None for glob delegation. - pub suffixes: Option)>>, + pub suffixes: DelegationSuffixes, pub body: Option>, } @@ -3918,6 +3923,13 @@ pub struct StaticItem { pub mutability: Mutability, pub expr: Option>, pub define_opaque: Option>, + + /// This static is an implementation of an externally implementable item (EII). + /// This means, there was an EII declared somewhere and this static is the + /// implementation that should be used for the declaration. + /// + /// For statics, there may be at most one `EiiImpl`, but this is a `ThinVec` to make usages of this field nicer. + pub eii_impls: ThinVec, } #[derive(Clone, Encodable, Decodable, Debug, Walkable)] diff --git a/compiler/rustc_ast/src/visit.rs b/compiler/rustc_ast/src/visit.rs index 6aa8d5f38ad2..ee4b1d135430 100644 --- a/compiler/rustc_ast/src/visit.rs +++ b/compiler/rustc_ast/src/visit.rs @@ -430,6 +430,7 @@ pub fn ctxt(&self) -> Option { Defaultness, Delegation, DelegationMac, + DelegationSuffixes, DelimArgs, DelimSpan, EnumDef, diff --git a/compiler/rustc_ast_lowering/Cargo.toml b/compiler/rustc_ast_lowering/Cargo.toml index c00bac5d3c5a..42befe958633 100644 --- a/compiler/rustc_ast_lowering/Cargo.toml +++ b/compiler/rustc_ast_lowering/Cargo.toml @@ -23,6 +23,6 @@ rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } rustc_target = { path = "../rustc_target" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_ast_lowering/src/delegation.rs b/compiler/rustc_ast_lowering/src/delegation.rs index ee4a52fb3863..01382a69f2ec 100644 --- a/compiler/rustc_ast_lowering/src/delegation.rs +++ b/compiler/rustc_ast_lowering/src/delegation.rs @@ -46,9 +46,9 @@ use rustc_ast::*; use rustc_data_structures::fx::FxHashSet; use rustc_errors::ErrorGuaranteed; -use rustc_hir as hir; use rustc_hir::attrs::{AttributeKind, InlineAttr}; use rustc_hir::def_id::DefId; +use rustc_hir::{self as hir, FnDeclFlags}; use rustc_middle::span_bug; use rustc_middle::ty::Asyncness; use rustc_span::symbol::kw; @@ -271,7 +271,7 @@ fn get_resolution_id(&self, node_id: NodeId) -> Option { // Function parameter count, including C variadic `...` if present. fn param_count(&self, def_id: DefId) -> (usize, bool /*c_variadic*/) { let sig = self.tcx.fn_sig(def_id).skip_binder().skip_binder(); - (sig.inputs().len() + usize::from(sig.c_variadic), sig.c_variadic) + (sig.inputs().len() + usize::from(sig.c_variadic()), sig.c_variadic()) } fn lower_delegation_decl( @@ -309,9 +309,9 @@ fn lower_delegation_decl( self.arena.alloc(hir::FnDecl { inputs, output: hir::FnRetTy::Return(output), - c_variadic, - lifetime_elision_allowed: true, - implicit_self: hir::ImplicitSelfKind::None, + fn_decl_kind: FnDeclFlags::default() + .set_lifetime_elision_allowed(true) + .set_c_variadic(c_variadic), }) } @@ -331,11 +331,11 @@ fn lower_delegation_sig( safety: if self.tcx.codegen_fn_attrs(sig_id).safe_target_features { hir::HeaderSafety::SafeTargetFeatures } else { - hir::HeaderSafety::Normal(sig.safety) + hir::HeaderSafety::Normal(sig.safety()) }, constness: self.tcx.constness(sig_id), asyncness, - abi: sig.abi, + abi: sig.abi(), }; hir::FnSig { decl, header, span } @@ -603,13 +603,7 @@ fn generate_delegation_error( span: Span, delegation: &Delegation, ) -> DelegationResults<'hir> { - let decl = self.arena.alloc(hir::FnDecl { - inputs: &[], - output: hir::FnRetTy::DefaultReturn(span), - c_variadic: false, - lifetime_elision_allowed: true, - implicit_self: hir::ImplicitSelfKind::None, - }); + let decl = self.arena.alloc(hir::FnDecl::dummy(span)); let header = self.generate_header_error(); let sig = hir::FnSig { decl, header, span }; diff --git a/compiler/rustc_ast_lowering/src/delegation/generics.rs b/compiler/rustc_ast_lowering/src/delegation/generics.rs index 4e960e3b9290..01b17438bc7f 100644 --- a/compiler/rustc_ast_lowering/src/delegation/generics.rs +++ b/compiler/rustc_ast_lowering/src/delegation/generics.rs @@ -10,18 +10,38 @@ use crate::{LoweringContext, ResolverAstLoweringExt}; -pub(super) enum DelegationGenerics { +#[derive(Clone, Copy)] +pub(super) enum DelegationGenericsKind { /// User-specified args are present: `reuse foo::;`. UserSpecified, /// The default case when no user-specified args are present: `reuse Trait::foo;`. - Default(T), + Default, /// In free-to-trait reuse, when user specified args for trait `reuse Trait::::foo;` /// in this case we need to both generate `Self` and process user args. - SelfAndUserSpecified(T), + SelfAndUserSpecified, /// In delegations from trait impl to other entities like free functions or trait functions, /// we want to generate a function whose generics matches generics of signature function /// in trait. - TraitImpl(T, bool /* Has user-specified args */), + TraitImpl(bool /* Has user-specified args */), +} + +pub(super) struct DelegationGenerics { + generics: T, + kind: DelegationGenericsKind, +} + +impl<'hir> DelegationGenerics<&'hir [ty::GenericParamDef]> { + fn default(generics: &'hir [ty::GenericParamDef]) -> Self { + DelegationGenerics { generics, kind: DelegationGenericsKind::Default } + } + + fn user_specified(generics: &'hir [ty::GenericParamDef]) -> Self { + DelegationGenerics { generics, kind: DelegationGenericsKind::UserSpecified } + } + + fn trait_impl(generics: &'hir [ty::GenericParamDef], user_specified: bool) -> Self { + DelegationGenerics { generics, kind: DelegationGenericsKind::TraitImpl(user_specified) } + } } /// Used for storing either ty generics or their uplifted HIR version. First we obtain @@ -54,20 +74,19 @@ pub(super) struct GenericArgsPropagationDetails { pub(super) use_args_in_sig_inheritance: bool, } -impl DelegationGenerics { - fn args_propagation_details(&self) -> GenericArgsPropagationDetails { +impl DelegationGenericsKind { + fn args_propagation_details(self) -> GenericArgsPropagationDetails { match self { - DelegationGenerics::UserSpecified | DelegationGenerics::SelfAndUserSpecified { .. } => { - GenericArgsPropagationDetails { - should_propagate: false, - use_args_in_sig_inheritance: true, - } - } - DelegationGenerics::TraitImpl(_, user_specified) => GenericArgsPropagationDetails { - should_propagate: !*user_specified, + DelegationGenericsKind::UserSpecified + | DelegationGenericsKind::SelfAndUserSpecified => GenericArgsPropagationDetails { + should_propagate: false, + use_args_in_sig_inheritance: true, + }, + DelegationGenericsKind::TraitImpl(user_specified) => GenericArgsPropagationDetails { + should_propagate: !user_specified, use_args_in_sig_inheritance: false, }, - DelegationGenerics::Default(_) => GenericArgsPropagationDetails { + DelegationGenericsKind::Default => GenericArgsPropagationDetails { should_propagate: true, use_args_in_sig_inheritance: false, }, @@ -81,25 +100,9 @@ pub(super) fn into_hir_generics( ctx: &mut LoweringContext<'_, 'hir, impl ResolverAstLoweringExt<'hir>>, span: Span, ) -> &mut HirOrTyGenerics<'hir> { - if let HirOrTyGenerics::Ty(params) = self { - let mut uplift_params = |generics: &'hir [ty::GenericParamDef]| { - ctx.uplift_delegation_generic_params(span, generics) - }; - - let hir_generics = match params { - DelegationGenerics::UserSpecified => DelegationGenerics::UserSpecified, - DelegationGenerics::Default(params) => { - DelegationGenerics::Default(uplift_params(params)) - } - DelegationGenerics::SelfAndUserSpecified(params) => { - DelegationGenerics::SelfAndUserSpecified(uplift_params(params)) - } - DelegationGenerics::TraitImpl(params, user_specified) => { - DelegationGenerics::TraitImpl(uplift_params(params), *user_specified) - } - }; - - *self = HirOrTyGenerics::Hir(hir_generics); + if let HirOrTyGenerics::Ty(ty) = self { + let params = ctx.uplift_delegation_generic_params(span, ty.generics); + *self = HirOrTyGenerics::Hir(DelegationGenerics { generics: params, kind: ty.kind }); } self @@ -108,12 +111,7 @@ pub(super) fn into_hir_generics( fn hir_generics_or_empty(&self) -> &'hir hir::Generics<'hir> { match self { HirOrTyGenerics::Ty(_) => hir::Generics::empty(), - HirOrTyGenerics::Hir(hir_generics) => match hir_generics { - DelegationGenerics::UserSpecified => hir::Generics::empty(), - DelegationGenerics::Default(generics) - | DelegationGenerics::SelfAndUserSpecified(generics) - | DelegationGenerics::TraitImpl(generics, _) => generics, - }, + HirOrTyGenerics::Hir(hir) => hir.generics, } } @@ -127,21 +125,16 @@ pub(super) fn into_generic_args( HirOrTyGenerics::Ty(_) => { bug!("Attempting to get generic args before uplifting to HIR") } - HirOrTyGenerics::Hir(hir_generics) => match hir_generics { - DelegationGenerics::UserSpecified => hir::GenericArgs::NONE, - DelegationGenerics::Default(generics) - | DelegationGenerics::SelfAndUserSpecified(generics) - | DelegationGenerics::TraitImpl(generics, _) => { - ctx.create_generics_args_from_params(generics.params, add_lifetimes, span) - } - }, + HirOrTyGenerics::Hir(hir) => { + ctx.create_generics_args_from_params(hir.generics.params, add_lifetimes, span) + } } } pub(super) fn args_propagation_details(&self) -> GenericArgsPropagationDetails { match self { - HirOrTyGenerics::Ty(ty_generics) => ty_generics.args_propagation_details(), - HirOrTyGenerics::Hir(hir_generics) => hir_generics.args_propagation_details(), + HirOrTyGenerics::Ty(ty) => ty.kind.args_propagation_details(), + HirOrTyGenerics::Hir(hir) => hir.kind.args_propagation_details(), } } } @@ -231,9 +224,10 @@ pub(super) fn uplift_delegation_generics( if matches!(delegation_parent_kind, DefKind::Impl { of_trait: true }) { // Considering parent generics, during signature inheritance // we will take those args that are in trait impl header trait ref. - let parent = GenericsGenerationResult::new(DelegationGenerics::TraitImpl(&[], true)); + let parent = DelegationGenerics::trait_impl(&[], true); + let parent = GenericsGenerationResult::new(parent); - let child = DelegationGenerics::TraitImpl(sig_params, child_user_specified); + let child = DelegationGenerics::trait_impl(sig_params, child_user_specified); let child = GenericsGenerationResult::new(child); return GenericsGenerationResults { parent, child }; @@ -257,22 +251,28 @@ pub(super) fn uplift_delegation_generics( if segments[len - 2].args.is_some() { if generate_self { // Take only first Self parameter, it is trait so Self must be present. - DelegationGenerics::SelfAndUserSpecified(&sig_parent_params[..1]) + DelegationGenerics { + kind: DelegationGenericsKind::SelfAndUserSpecified, + generics: &sig_parent_params[..1], + } } else { - DelegationGenerics::UserSpecified + DelegationGenerics::user_specified(&[]) } } else { let skip_self = usize::from(!generate_self); - DelegationGenerics::Default(&sig_parent_params[skip_self..]) + DelegationGenerics::default(&sig_parent_params[skip_self..]) } } else { - DelegationGenerics::<&'hir [ty::GenericParamDef]>::Default(&[]) + DelegationGenerics::default(&[]) }; let child_generics = if child_user_specified { - DelegationGenerics::UserSpecified + let synth_params_index = + sig_params.iter().position(|p| p.kind.is_synthetic()).unwrap_or(sig_params.len()); + + DelegationGenerics::user_specified(&sig_params[synth_params_index..]) } else { - DelegationGenerics::Default(sig_params) + DelegationGenerics::default(sig_params) }; GenericsGenerationResults { @@ -295,10 +295,9 @@ fn uplift_delegation_generic_params( let param_ident = Ident::new(p.name, span); let def_name = Some(param_ident.name); - let path_data = def_kind.def_path_data(def_name); let node_id = self.next_node_id(); - let def_id = self.create_def(node_id, def_name, def_kind, path_data, span); + let def_id = self.create_def(node_id, def_name, def_kind, span); let kind = match p.kind { GenericParamDefKind::Lifetime => { diff --git a/compiler/rustc_ast_lowering/src/expr.rs b/compiler/rustc_ast_lowering/src/expr.rs index b6bc122051cb..aad838e9a172 100644 --- a/compiler/rustc_ast_lowering/src/expr.rs +++ b/compiler/rustc_ast_lowering/src/expr.rs @@ -8,7 +8,6 @@ use rustc_errors::msg; use rustc_hir as hir; use rustc_hir::def::{DefKind, Res}; -use rustc_hir::definitions::DefPathData; use rustc_hir::{HirId, Target, find_attr}; use rustc_middle::span_bug; use rustc_middle::ty::TyCtxt; @@ -29,7 +28,7 @@ use crate::errors::{InvalidLegacyConstGenericArg, UseConstGenericArg, YieldInClosure}; use crate::{AllowReturnTypeNotation, FnDeclKind, ImplTraitPosition, TryBlockScope}; -struct WillCreateDefIdsVisitor {} +pub(super) struct WillCreateDefIdsVisitor; impl<'v> rustc_ast::visit::Visitor<'v> for WillCreateDefIdsVisitor { type Result = ControlFlow; @@ -472,25 +471,19 @@ fn lower_legacy_const_generics( for (idx, arg) in args.iter().cloned().enumerate() { if legacy_args_idx.contains(&idx) { let node_id = self.next_node_id(); - self.create_def( - node_id, - None, - DefKind::AnonConst, - DefPathData::LateAnonConst, - f.span, - ); - let mut visitor = WillCreateDefIdsVisitor {}; - let const_value = if let ControlFlow::Break(span) = visitor.visit_expr(&arg) { - Box::new(Expr { - id: self.next_node_id(), - kind: ExprKind::Err(invalid_expr_error(self.tcx, span)), - span: f.span, - attrs: [].into(), - tokens: None, - }) - } else { - arg - }; + self.create_def(node_id, None, DefKind::AnonConst, f.span); + let const_value = + if let ControlFlow::Break(span) = WillCreateDefIdsVisitor.visit_expr(&arg) { + Box::new(Expr { + id: self.next_node_id(), + kind: ExprKind::Err(invalid_expr_error(self.tcx, span)), + span: f.span, + attrs: [].into(), + tokens: None, + }) + } else { + arg + }; let anon_const = AnonConst { id: node_id, @@ -762,9 +755,7 @@ pub(super) fn make_desugared_coroutine_expr( let fn_decl = self.arena.alloc(hir::FnDecl { inputs, output, - c_variadic: false, - implicit_self: hir::ImplicitSelfKind::None, - lifetime_elision_allowed: false, + fn_decl_kind: hir::FnDeclFlags::default(), }); let body = self.lower_body(move |this| { diff --git a/compiler/rustc_ast_lowering/src/item.rs b/compiler/rustc_ast_lowering/src/item.rs index 1c80c56f2693..239daecd3d1f 100644 --- a/compiler/rustc_ast_lowering/src/item.rs +++ b/compiler/rustc_ast_lowering/src/item.rs @@ -24,8 +24,8 @@ use super::errors::{InvalidAbi, InvalidAbiSuggestion, TupleStructWithDefault, UnionWithDefault}; use super::stability::{enabled_names, gate_unstable_abi}; use super::{ - AstOwner, FnDeclKind, ImplTraitContext, ImplTraitPosition, LoweringContext, ParamMode, - RelaxedBoundForbiddenReason, RelaxedBoundPolicy, ResolverAstLoweringExt, + AstOwner, FnDeclKind, GenericArgsMode, ImplTraitContext, ImplTraitPosition, LoweringContext, + ParamMode, RelaxedBoundForbiddenReason, RelaxedBoundPolicy, ResolverAstLoweringExt, }; /// Wraps either IndexVec (during `hir_crate`), which acts like a primary @@ -213,8 +213,14 @@ fn generate_extra_attrs_for_item_kind( i: &ItemKind, ) -> Vec { match i { - ItemKind::Fn(box Fn { eii_impls, .. }) if eii_impls.is_empty() => Vec::new(), - ItemKind::Fn(box Fn { eii_impls, .. }) => { + ItemKind::Fn(box Fn { eii_impls, .. }) + | ItemKind::Static(box StaticItem { eii_impls, .. }) + if eii_impls.is_empty() => + { + Vec::new() + } + ItemKind::Fn(box Fn { eii_impls, .. }) + | ItemKind::Static(box StaticItem { eii_impls, .. }) => { vec![hir::Attribute::Parsed(AttributeKind::EiiImpls( eii_impls.iter().map(|i| self.lower_eii_impl(i)).collect(), ))] @@ -226,7 +232,6 @@ fn generate_extra_attrs_for_item_kind( ItemKind::ExternCrate(..) | ItemKind::Use(..) - | ItemKind::Static(..) | ItemKind::Const(..) | ItemKind::ConstBlock(..) | ItemKind::Mod(..) @@ -302,6 +307,7 @@ fn lower_item_kind( mutability: m, expr: e, define_opaque, + eii_impls: _, }) => { let ident = self.lower_ident(*ident); let ty = self @@ -540,14 +546,14 @@ fn lower_item_kind( constness, is_auto, safety, - // FIXME(impl_restrictions): lower to HIR - impl_restriction: _, + impl_restriction, ident, generics, bounds, items, }) => { let constness = self.lower_constness(*constness); + let impl_restriction = self.lower_impl_restriction(impl_restriction); let ident = self.lower_ident(*ident); let (generics, (safety, items, bounds)) = self.lower_generics( generics, @@ -566,7 +572,16 @@ fn lower_item_kind( (safety, items, bounds) }, ); - hir::ItemKind::Trait(constness, *is_auto, safety, ident, generics, bounds, items) + hir::ItemKind::Trait( + constness, + *is_auto, + safety, + impl_restriction, + ident, + generics, + bounds, + items, + ) } ItemKind::TraitAlias(box TraitAlias { constness, ident, generics, bounds }) => { let constness = self.lower_constness(*constness); @@ -817,6 +832,7 @@ fn lower_foreign_item(&mut self, i: &ForeignItem) -> &'hir hir::ForeignItem<'hir expr: _, safety, define_opaque, + eii_impls: _, }) => { let ty = self .lower_ty_alloc(ty, ImplTraitContext::Disallowed(ImplTraitPosition::StaticTy)); @@ -1831,6 +1847,38 @@ pub(super) fn lower_safety(&self, s: Safety, default: hir::Safety) -> hir::Safet } } + pub(super) fn lower_impl_restriction( + &mut self, + r: &ImplRestriction, + ) -> &'hir hir::ImplRestriction<'hir> { + let kind = match &r.kind { + RestrictionKind::Unrestricted => hir::RestrictionKind::Unrestricted, + RestrictionKind::Restricted { path, id, shorthand: _ } => { + let res = self.resolver.get_partial_res(*id); + if let Some(did) = res.and_then(|res| res.expect_full_res().opt_def_id()) { + hir::RestrictionKind::Restricted(self.arena.alloc(hir::Path { + res: did, + segments: self.arena.alloc_from_iter(path.segments.iter().map(|segment| { + self.lower_path_segment( + path.span, + segment, + ParamMode::Explicit, + GenericArgsMode::Err, + ImplTraitContext::Disallowed(ImplTraitPosition::Path), + None, + ) + })), + span: self.lower_span(path.span), + })) + } else { + self.dcx().span_delayed_bug(path.span, "should have errored in resolve"); + hir::RestrictionKind::Unrestricted + } + } + }; + self.arena.alloc(hir::ImplRestriction { kind, span: self.lower_span(r.span) }) + } + /// Return the pair of the lowered `generics` as `hir::Generics` and the evaluation of `f` with /// the carried impl trait definitions and bounds. #[instrument(level = "debug", skip(self, f))] diff --git a/compiler/rustc_ast_lowering/src/lib.rs b/compiler/rustc_ast_lowering/src/lib.rs index 0561490344d2..2ffb9c123b5f 100644 --- a/compiler/rustc_ast_lowering/src/lib.rs +++ b/compiler/rustc_ast_lowering/src/lib.rs @@ -39,8 +39,9 @@ use std::sync::Arc; use rustc_ast::node_id::NodeMap; +use rustc_ast::visit::Visitor; use rustc_ast::{self as ast, *}; -use rustc_attr_parsing::{AttributeParser, Late, OmitDoc}; +use rustc_attr_parsing::{AttributeParser, EmitAttribute, Late, OmitDoc}; use rustc_data_structures::fingerprint::Fingerprint; use rustc_data_structures::fx::FxIndexSet; use rustc_data_structures::sorted_map::SortedMap; @@ -50,8 +51,8 @@ use rustc_errors::{DiagArgFromDisplay, DiagCtxtHandle}; use rustc_hir::def::{DefKind, LifetimeRes, Namespace, PartialRes, PerNS, Res}; use rustc_hir::def_id::{CRATE_DEF_ID, LOCAL_CRATE, LocalDefId}; -use rustc_hir::definitions::{DefPathData, DisambiguatorState}; -use rustc_hir::lints::{AttributeLint, DelayedLint}; +use rustc_hir::definitions::PerParentDisambiguatorState; +use rustc_hir::lints::{AttributeLint, DelayedLint, DynAttribute}; use rustc_hir::{ self as hir, AngleBrackets, ConstArg, GenericArg, HirId, ItemLocalMap, LifetimeSource, LifetimeSyntax, ParamName, Target, TraitCandidate, find_attr, @@ -93,7 +94,7 @@ macro_rules! arena_vec { struct LoweringContext<'a, 'hir, R> { tcx: TyCtxt<'hir>, resolver: &'a mut R, - disambiguator: DisambiguatorState, + disambiguator: PerParentDisambiguatorState, /// Used to allocate HIR nodes. arena: &'hir hir::Arena<'hir>, @@ -154,11 +155,11 @@ struct LoweringContext<'a, 'hir, R> { impl<'a, 'hir, R: ResolverAstLoweringExt<'hir>> LoweringContext<'a, 'hir, R> { fn new(tcx: TyCtxt<'hir>, resolver: &'a mut R) -> Self { - let registered_tools = tcx.registered_tools(()); + let registered_tools = tcx.registered_tools(()).iter().map(|x| x.name).collect(); Self { tcx, resolver, - disambiguator: DisambiguatorState::new(), + disambiguator: Default::default(), arena: tcx.hir_arena, // HirId handling. @@ -301,6 +302,10 @@ fn trait_candidates(&self, node_id: NodeId) -> Option<&'tcx [hir::TraitCandidate fn next_node_id(&mut self) -> NodeId { next_node_id(&mut self.next_node_id) } + + fn steal_or_create_disambiguator(&self, parent: LocalDefId) -> PerParentDisambiguatorState { + self.base.steal_or_create_disambiguator(parent) + } } fn next_node_id(current_id: &mut NodeId) -> NodeId { @@ -403,6 +408,10 @@ fn trait_candidates(&self, node_id: NodeId) -> Option<&'tcx [hir::TraitCandidate fn next_node_id(&mut self) -> NodeId { next_node_id(&mut self.next_node_id) } + + fn steal_or_create_disambiguator(&self, parent: LocalDefId) -> PerParentDisambiguatorState { + self.per_parent_disambiguators.get(&parent).map(|s| s.steal()).unwrap_or_default() + } } /// How relaxed bounds `?Trait` should be treated. @@ -716,7 +725,6 @@ fn create_def( node_id: ast::NodeId, name: Option, def_kind: DefKind, - def_path_data: DefPathData, span: Span, ) -> LocalDefId { let parent = self.current_hir_id_owner.def_id; @@ -732,7 +740,7 @@ fn create_def( let def_id = self .tcx .at(span) - .create_def(parent, name, def_kind, Some(def_path_data), &mut self.disambiguator) + .create_def(parent, name, def_kind, None, &mut self.disambiguator) .def_id(); debug!("create_def: def_id_to_node_id[{:?}] <-> {:?}", def_id, node_id); @@ -773,6 +781,8 @@ fn with_hir_id_owner( ) { let owner_id = self.owner_id(owner); + let new_disambig = self.resolver.steal_or_create_disambiguator(owner_id.def_id); + let disambiguator = std::mem::replace(&mut self.disambiguator, new_disambig); let current_attrs = std::mem::take(&mut self.attrs); let current_bodies = std::mem::take(&mut self.bodies); let current_define_opaque = std::mem::take(&mut self.define_opaque); @@ -807,6 +817,7 @@ fn with_hir_id_owner( assert!(self.impl_trait_bounds.is_empty()); let info = self.make_owner_info(item); + self.disambiguator = disambiguator; self.attrs = current_attrs; self.bodies = current_bodies; self.define_opaque = current_define_opaque; @@ -846,14 +857,12 @@ fn make_owner_info(&mut self, node: hir::OwnerNode<'hir>) -> &'hir hir::OwnerInf let bodies = SortedMap::from_presorted_elements(bodies); // Don't hash unless necessary, because it's expensive. - let rustc_middle::hir::Hashes { opt_hash_including_bodies, attrs_hash, delayed_lints_hash } = - self.tcx.hash_owner_nodes(node, &bodies, &attrs, &delayed_lints, define_opaque); + let rustc_middle::hir::Hashes { opt_hash_including_bodies, attrs_hash } = + self.tcx.hash_owner_nodes(node, &bodies, &attrs, define_opaque); let num_nodes = self.item_local_id_counter.as_usize(); let (nodes, parenting) = index::index_hir(self.tcx, node, &bodies, num_nodes); let nodes = hir::OwnerNodes { opt_hash_including_bodies, nodes, bodies }; let attrs = hir::AttributeMap { map: attrs, opt_hash: attrs_hash, define_opaque }; - let delayed_lints = - hir::lints::DelayedLints { lints: delayed_lints, opt_hash: delayed_lints_hash }; self.arena.alloc(hir::OwnerInfo { nodes, parenting, attrs, trait_map, delayed_lints }) } @@ -1014,7 +1023,6 @@ fn lifetime_res_to_generic_param( param, Some(kw::UnderscoreLifetime), DefKind::LifetimeParam, - DefPathData::DesugaredAnonymousLifetime, ident.span, ); debug!(?_def_id); @@ -1166,13 +1174,23 @@ fn lower_attrs_vec( target, OmitDoc::Lower, |s| l.lower(s), - |lint_id, span, kind| { - self.delayed_lints.push(DelayedLint::AttributeParsing(AttributeLint { - lint_id, - id: target_hir_id, - span, - kind, - })); + |lint_id, span, kind| match kind { + EmitAttribute::Static(attr_kind) => { + self.delayed_lints.push(DelayedLint::AttributeParsing(AttributeLint { + lint_id, + id: target_hir_id, + span, + kind: attr_kind, + })); + } + EmitAttribute::Dynamic(callback) => { + self.delayed_lints.push(DelayedLint::Dynamic(DynAttribute { + lint_id, + id: target_hir_id, + span, + callback, + })); + } }, ) } @@ -1831,7 +1849,7 @@ fn lower_fn_decl( // as they are not explicit in HIR/Ty function signatures. // (instead, the `c_variadic` flag is set to `true`) let mut inputs = &decl.inputs[..]; - if c_variadic { + if decl.c_variadic() { inputs = &inputs[..inputs.len() - 1]; } let inputs = self.arena.alloc_from_iter(inputs.iter().map(|param| { @@ -1894,12 +1912,8 @@ fn lower_fn_decl( }, }; - self.arena.alloc(hir::FnDecl { - inputs, - output, - c_variadic, - lifetime_elision_allowed: self.resolver.lifetime_elision_allowed(fn_node_id), - implicit_self: decl.inputs.get(0).map_or(hir::ImplicitSelfKind::None, |arg| { + let fn_decl_kind = hir::FnDeclFlags::default() + .set_implicit_self(decl.inputs.get(0).map_or(hir::ImplicitSelfKind::None, |arg| { let is_mutable_pat = matches!( arg.pat.kind, PatKind::Ident(hir::BindingMode(_, Mutability::Mut), ..) @@ -1921,8 +1935,11 @@ fn lower_fn_decl( } _ => hir::ImplicitSelfKind::None, } - }), - }) + })) + .set_lifetime_elision_allowed(self.resolver.lifetime_elision_allowed(fn_node_id)) + .set_c_variadic(c_variadic); + + self.arena.alloc(hir::FnDecl { inputs, output, fn_decl_kind }) } // Transforms `-> T` for `async fn` into `-> OpaqueTy { .. }` @@ -2219,14 +2236,22 @@ fn lower_generic_param_kind( // since later compiler stages cannot handle them (and shouldn't need to be able to). let default = default .as_ref() - .filter(|_| match source { + .filter(|anon_const| match source { hir::GenericParamSource::Generics => true, hir::GenericParamSource::Binder => { - self.dcx().emit_err(errors::GenericParamDefaultInBinder { - span: param.span(), - }); - - false + let err = errors::GenericParamDefaultInBinder { span: param.span() }; + if expr::WillCreateDefIdsVisitor + .visit_expr(&anon_const.value) + .is_break() + { + // FIXME(mgca): make this non-fatal once we have a better way + // to handle nested items in anno const from binder + // Issue: https://github.com/rust-lang/rust/issues/123629 + self.dcx().emit_fatal(err) + } else { + self.dcx().emit_err(err); + false + } } }) .map(|def| self.lower_anon_const_to_const_arg_and_alloc(def)); @@ -2495,13 +2520,7 @@ fn lower_const_path_to_const_arg( // We're lowering a const argument that was originally thought to be a type argument, // so the def collector didn't create the def ahead of time. That's why we have to do // it here. - let def_id = self.create_def( - node_id, - None, - DefKind::AnonConst, - DefPathData::LateAnonConst, - span, - ); + let def_id = self.create_def(node_id, None, DefKind::AnonConst, span); let hir_id = self.lower_node_id(node_id); let path_expr = Expr { @@ -2563,12 +2582,17 @@ fn lower_expr_to_const_arg_direct(&mut self, expr: &Expr) -> hir::ConstArg<'hir> let span = self.lower_span(expr.span); let overly_complex_const = |this: &mut Self| { - let e = this.dcx().struct_span_err( - expr.span, - "complex const arguments must be placed inside of a `const` block", - ); + let msg = "complex const arguments must be placed inside of a `const` block"; + let e = if expr::WillCreateDefIdsVisitor.visit_expr(expr).is_break() { + // FIXME(mgca): make this non-fatal once we have a better way to handle + // nested items in const args + // Issue: https://github.com/rust-lang/rust/issues/154539 + this.dcx().struct_span_fatal(expr.span, msg).emit() + } else { + this.dcx().struct_span_err(expr.span, msg).emit() + }; - ConstArg { hir_id: this.next_id(), kind: hir::ConstArgKind::Error(e.emit()), span } + ConstArg { hir_id: this.next_id(), kind: hir::ConstArgKind::Error(e), span } }; match &expr.kind { diff --git a/compiler/rustc_ast_lowering/src/pat.rs b/compiler/rustc_ast_lowering/src/pat.rs index 40d42ffb5f4f..88f038f11d3c 100644 --- a/compiler/rustc_ast_lowering/src/pat.rs +++ b/compiler/rustc_ast_lowering/src/pat.rs @@ -3,7 +3,6 @@ use rustc_ast::*; use rustc_data_structures::stack::ensure_sufficient_stack; use rustc_hir::def::{DefKind, Res}; -use rustc_hir::definitions::DefPathData; use rustc_hir::{self as hir, LangItem, Target}; use rustc_middle::span_bug; use rustc_span::{DesugaringKind, Ident, Span, Spanned, respan}; @@ -421,7 +420,11 @@ fn lower_expr_within_pat( } _ => { let is_const_block = matches!(expr.kind, ExprKind::ConstBlock(_)); - let pattern_from_macro = expr.is_approximately_pattern(); + let pattern_from_macro = expr.is_approximately_pattern() + || matches!( + expr.peel_parens().kind, + ExprKind::Binary(Spanned { node: BinOpKind::BitOr, .. }, ..) + ); let guar = self.dcx().emit_err(ArbitraryExpressionInPattern { span, pattern_from_macro_note: pattern_from_macro, @@ -534,8 +537,7 @@ fn lower_ty_pat_range_end( // We're generating a range end that didn't exist in the AST, // so the def collector didn't create the def ahead of time. That's why we have to do // it here. - let def_id = - self.create_def(node_id, None, DefKind::AnonConst, DefPathData::LateAnonConst, span); + let def_id = self.create_def(node_id, None, DefKind::AnonConst, span); let hir_id = self.lower_node_id(node_id); let unstable_span = self.mark_span_with_reason( diff --git a/compiler/rustc_ast_passes/Cargo.toml b/compiler/rustc_ast_passes/Cargo.toml index c9def6246d1b..42cbd7b3d362 100644 --- a/compiler/rustc_ast_passes/Cargo.toml +++ b/compiler/rustc_ast_passes/Cargo.toml @@ -18,5 +18,5 @@ rustc_macros = { path = "../rustc_macros" } rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } rustc_target = { path = "../rustc_target" } -thin-vec = "0.2.12" +thin-vec = "0.2.15" # tidy-alphabetical-end diff --git a/compiler/rustc_ast_passes/src/feature_gate.rs b/compiler/rustc_ast_passes/src/feature_gate.rs index 1b615b611258..5831636a81b2 100644 --- a/compiler/rustc_ast_passes/src/feature_gate.rs +++ b/compiler/rustc_ast_passes/src/feature_gate.rs @@ -7,7 +7,7 @@ use rustc_hir::attrs::AttributeKind; use rustc_session::Session; use rustc_session::parse::{feature_err, feature_warn}; -use rustc_span::{DUMMY_SP, Span, Spanned, Symbol, sym}; +use rustc_span::{Span, Spanned, Symbol, sym}; use thin_vec::ThinVec; use crate::errors; @@ -646,14 +646,7 @@ fn maybe_stage_features(sess: &Session, features: &Features, krate: &ast::Crate) let mut errored = false; if let Some(Attribute::Parsed(AttributeKind::Feature(feature_idents, first_span))) = - AttributeParser::parse_limited( - sess, - &krate.attrs, - sym::feature, - DUMMY_SP, - krate.id, - Some(&features), - ) + AttributeParser::parse_limited(sess, &krate.attrs, &[sym::feature]) { // `feature(...)` used on non-nightly. This is definitely an error. let mut err = errors::FeatureOnNonNightly { diff --git a/compiler/rustc_ast_pretty/Cargo.toml b/compiler/rustc_ast_pretty/Cargo.toml index b704040be961..957fc1297c58 100644 --- a/compiler/rustc_ast_pretty/Cargo.toml +++ b/compiler/rustc_ast_pretty/Cargo.toml @@ -13,5 +13,5 @@ rustc_span = { path = "../rustc_span" } [dev-dependencies] # tidy-alphabetical-start -thin-vec = "0.2.12" +thin-vec = "0.2.15" # tidy-alphabetical-end diff --git a/compiler/rustc_ast_pretty/src/helpers.rs b/compiler/rustc_ast_pretty/src/helpers.rs deleted file mode 100644 index 34641ea2f5ae..000000000000 --- a/compiler/rustc_ast_pretty/src/helpers.rs +++ /dev/null @@ -1,49 +0,0 @@ -use std::borrow::Cow; - -use crate::pp::Printer; - -impl Printer { - pub fn word_space>>(&mut self, w: W) { - self.word(w); - self.space(); - } - - pub fn popen(&mut self) { - self.word("("); - } - - pub fn pclose(&mut self) { - self.word(")"); - } - - pub fn hardbreak_if_not_bol(&mut self) { - if !self.is_beginning_of_line() { - self.hardbreak() - } - } - - pub fn space_if_not_bol(&mut self) { - if !self.is_beginning_of_line() { - self.space(); - } - } - - pub fn nbsp(&mut self) { - self.word(" ") - } - - pub fn word_nbsp>>(&mut self, w: S) { - self.word(w); - self.nbsp() - } - - /// Synthesizes a comment that was not textually present in the original - /// source file. - pub fn synth_comment(&mut self, text: impl Into>) { - self.word("/*"); - self.space(); - self.word(text); - self.space(); - self.word("*/") - } -} diff --git a/compiler/rustc_ast_pretty/src/lib.rs b/compiler/rustc_ast_pretty/src/lib.rs index a7d9f89fb3df..bfc1d387b700 100644 --- a/compiler/rustc_ast_pretty/src/lib.rs +++ b/compiler/rustc_ast_pretty/src/lib.rs @@ -3,6 +3,5 @@ #![feature(negative_impls)] // tidy-alphabetical-end -mod helpers; pub mod pp; pub mod pprust; diff --git a/compiler/rustc_ast_pretty/src/pp.rs b/compiler/rustc_ast_pretty/src/pp.rs index 4108671a3629..c7a38d981b89 100644 --- a/compiler/rustc_ast_pretty/src/pp.rs +++ b/compiler/rustc_ast_pretty/src/pp.rs @@ -132,7 +132,6 @@ //! methods called `Printer::scan_*`, and the 'PRINT' process is the //! method called `Printer::print`. -mod convenience; mod ring; use std::borrow::Cow; @@ -188,6 +187,12 @@ pub(crate) enum Token { End, } +impl Token { + pub(crate) fn is_hardbreak_tok(&self) -> bool { + *self == Printer::hardbreak_tok_offset(0) + } +} + #[derive(Copy, Clone)] enum PrintFrame { Fits, @@ -479,4 +484,132 @@ fn print_string(&mut self, string: &str) { self.out.push_str(string); self.space -= string.len() as isize; } + + /// Synthesizes a comment that was not textually present in the original + /// source file. + pub fn synth_comment(&mut self, text: impl Into>) { + self.word("/*"); + self.space(); + self.word(text); + self.space(); + self.word("*/") + } + + /// "raw box" + pub fn rbox(&mut self, indent: isize, breaks: Breaks) -> BoxMarker { + self.scan_begin(BeginToken { indent: IndentStyle::Block { offset: indent }, breaks }) + } + + /// Inconsistent breaking box + pub fn ibox(&mut self, indent: isize) -> BoxMarker { + self.rbox(indent, Breaks::Inconsistent) + } + + /// Consistent breaking box + pub fn cbox(&mut self, indent: isize) -> BoxMarker { + self.rbox(indent, Breaks::Consistent) + } + + pub fn visual_align(&mut self) -> BoxMarker { + self.scan_begin(BeginToken { indent: IndentStyle::Visual, breaks: Breaks::Consistent }) + } + + pub fn break_offset(&mut self, n: usize, off: isize) { + self.scan_break(BreakToken { + offset: off, + blank_space: n as isize, + ..BreakToken::default() + }); + } + + pub fn end(&mut self, b: BoxMarker) { + self.scan_end(b) + } + + pub fn eof(mut self) -> String { + self.scan_eof(); + self.out + } + + pub fn word>>(&mut self, wrd: S) { + let string = wrd.into(); + self.scan_string(string) + } + + pub fn word_space>>(&mut self, w: W) { + self.word(w); + self.space(); + } + + pub fn nbsp(&mut self) { + self.word(" ") + } + + pub fn word_nbsp>>(&mut self, w: S) { + self.word(w); + self.nbsp() + } + + fn spaces(&mut self, n: usize) { + self.break_offset(n, 0) + } + + pub fn zerobreak(&mut self) { + self.spaces(0) + } + + pub fn space(&mut self) { + self.spaces(1) + } + + pub fn popen(&mut self) { + self.word("("); + } + + pub fn pclose(&mut self) { + self.word(")"); + } + + pub fn hardbreak(&mut self) { + self.spaces(SIZE_INFINITY as usize) + } + + pub fn is_beginning_of_line(&self) -> bool { + match self.last_token() { + Some(last_token) => last_token.is_hardbreak_tok(), + None => true, + } + } + + pub fn hardbreak_if_not_bol(&mut self) { + if !self.is_beginning_of_line() { + self.hardbreak() + } + } + + pub fn space_if_not_bol(&mut self) { + if !self.is_beginning_of_line() { + self.space(); + } + } + + pub(crate) fn hardbreak_tok_offset(off: isize) -> Token { + Token::Break(BreakToken { + offset: off, + blank_space: SIZE_INFINITY, + ..BreakToken::default() + }) + } + + pub fn trailing_comma(&mut self) { + self.scan_break(BreakToken { pre_break: Some(','), ..BreakToken::default() }); + } + + pub fn trailing_comma_or_space(&mut self) { + self.scan_break(BreakToken { + blank_space: 1, + pre_break: Some(','), + ..BreakToken::default() + }); + } } diff --git a/compiler/rustc_ast_pretty/src/pp/convenience.rs b/compiler/rustc_ast_pretty/src/pp/convenience.rs deleted file mode 100644 index 9b902b38122c..000000000000 --- a/compiler/rustc_ast_pretty/src/pp/convenience.rs +++ /dev/null @@ -1,97 +0,0 @@ -use std::borrow::Cow; - -use crate::pp::{ - BeginToken, BoxMarker, BreakToken, Breaks, IndentStyle, Printer, SIZE_INFINITY, Token, -}; - -impl Printer { - /// "raw box" - pub fn rbox(&mut self, indent: isize, breaks: Breaks) -> BoxMarker { - self.scan_begin(BeginToken { indent: IndentStyle::Block { offset: indent }, breaks }) - } - - /// Inconsistent breaking box - pub fn ibox(&mut self, indent: isize) -> BoxMarker { - self.rbox(indent, Breaks::Inconsistent) - } - - /// Consistent breaking box - pub fn cbox(&mut self, indent: isize) -> BoxMarker { - self.rbox(indent, Breaks::Consistent) - } - - pub fn visual_align(&mut self) -> BoxMarker { - self.scan_begin(BeginToken { indent: IndentStyle::Visual, breaks: Breaks::Consistent }) - } - - pub fn break_offset(&mut self, n: usize, off: isize) { - self.scan_break(BreakToken { - offset: off, - blank_space: n as isize, - ..BreakToken::default() - }); - } - - pub fn end(&mut self, b: BoxMarker) { - self.scan_end(b) - } - - pub fn eof(mut self) -> String { - self.scan_eof(); - self.out - } - - pub fn word>>(&mut self, wrd: S) { - let string = wrd.into(); - self.scan_string(string) - } - - fn spaces(&mut self, n: usize) { - self.break_offset(n, 0) - } - - pub fn zerobreak(&mut self) { - self.spaces(0) - } - - pub fn space(&mut self) { - self.spaces(1) - } - - pub fn hardbreak(&mut self) { - self.spaces(SIZE_INFINITY as usize) - } - - pub fn is_beginning_of_line(&self) -> bool { - match self.last_token() { - Some(last_token) => last_token.is_hardbreak_tok(), - None => true, - } - } - - pub(crate) fn hardbreak_tok_offset(off: isize) -> Token { - Token::Break(BreakToken { - offset: off, - blank_space: SIZE_INFINITY, - ..BreakToken::default() - }) - } - - pub fn trailing_comma(&mut self) { - self.scan_break(BreakToken { pre_break: Some(','), ..BreakToken::default() }); - } - - pub fn trailing_comma_or_space(&mut self) { - self.scan_break(BreakToken { - blank_space: 1, - pre_break: Some(','), - ..BreakToken::default() - }); - } -} - -impl Token { - pub(crate) fn is_hardbreak_tok(&self) -> bool { - *self == Printer::hardbreak_tok_offset(0) - } -} diff --git a/compiler/rustc_ast_pretty/src/pprust/state/item.rs b/compiler/rustc_ast_pretty/src/pprust/state/item.rs index 3e9c59614834..cb9bbf014e01 100644 --- a/compiler/rustc_ast_pretty/src/pprust/state/item.rs +++ b/compiler/rustc_ast_pretty/src/pprust/state/item.rs @@ -43,6 +43,7 @@ pub(crate) fn print_foreign_item(&mut self, item: &ast::ForeignItem) { expr, safety, define_opaque, + eii_impls, }) => self.print_item_const( *ident, Some(*mutability), @@ -53,6 +54,7 @@ pub(crate) fn print_foreign_item(&mut self, item: &ast::ForeignItem) { *safety, ast::Defaultness::Implicit, define_opaque.as_deref(), + eii_impls, ), ast::ForeignItemKind::TyAlias(box ast::TyAlias { defaultness, @@ -93,8 +95,12 @@ fn print_item_const( safety: ast::Safety, defaultness: ast::Defaultness, define_opaque: Option<&[(ast::NodeId, ast::Path)]>, + eii_impls: &[EiiImpl], ) { self.print_define_opaques(define_opaque); + for eii_impl in eii_impls { + self.print_eii_impl(eii_impl); + } let (cb, ib) = self.head(""); self.print_visibility(vis); self.print_safety(safety); @@ -191,6 +197,7 @@ pub(crate) fn print_item(&mut self, item: &ast::Item) { mutability: mutbl, expr: body, define_opaque, + eii_impls, }) => { self.print_safety(*safety); self.print_item_const( @@ -203,6 +210,7 @@ pub(crate) fn print_item(&mut self, item: &ast::Item) { ast::Safety::Default, ast::Defaultness::Implicit, define_opaque.as_deref(), + eii_impls, ); } ast::ItemKind::ConstBlock(ast::ConstBlockItem { id: _, span: _, block }) => { @@ -234,6 +242,7 @@ pub(crate) fn print_item(&mut self, item: &ast::Item) { ast::Safety::Default, *defaultness, define_opaque.as_deref(), + &[], ); } ast::ItemKind::Fn(func) => { @@ -435,7 +444,10 @@ pub(crate) fn print_item(&mut self, item: &ast::Item) { &item.vis, &deleg.qself, &deleg.prefix, - deleg.suffixes.as_ref().map_or(DelegationKind::Glob, |s| DelegationKind::List(s)), + match &deleg.suffixes { + ast::DelegationSuffixes::List(s) => DelegationKind::List(s), + ast::DelegationSuffixes::Glob(_) => DelegationKind::Glob, + }, &deleg.body, ), } @@ -602,6 +614,7 @@ pub(crate) fn print_assoc_item(&mut self, item: &ast::AssocItem) { ast::Safety::Default, *defaultness, define_opaque.as_deref(), + &[], ); } ast::AssocItemKind::Type(box ast::TyAlias { @@ -641,7 +654,10 @@ pub(crate) fn print_assoc_item(&mut self, item: &ast::AssocItem) { vis, &deleg.qself, &deleg.prefix, - deleg.suffixes.as_ref().map_or(DelegationKind::Glob, |s| DelegationKind::List(s)), + match &deleg.suffixes { + ast::DelegationSuffixes::List(s) => DelegationKind::List(s), + ast::DelegationSuffixes::Glob(_) => DelegationKind::Glob, + }, &deleg.body, ), } @@ -703,18 +719,8 @@ fn print_fn_full(&mut self, vis: &ast::Visibility, attrs: &[ast::Attribute], fun self.print_define_opaques(define_opaque.as_deref()); - for EiiImpl { eii_macro_path, impl_safety, .. } in eii_impls { - self.word("#["); - if let Safety::Unsafe(..) = impl_safety { - self.word("unsafe"); - self.popen(); - } - self.print_path(eii_macro_path, false, 0); - if let Safety::Unsafe(..) = impl_safety { - self.pclose(); - } - self.word("]"); - self.hardbreak(); + for eii_impl in eii_impls { + self.print_eii_impl(eii_impl); } let body_cb_ib = body.as_ref().map(|body| (body, self.head(""))); @@ -741,6 +747,20 @@ fn print_fn_full(&mut self, vis: &ast::Visibility, attrs: &[ast::Attribute], fun } } + fn print_eii_impl(&mut self, eii: &ast::EiiImpl) { + self.word("#["); + if let Safety::Unsafe(..) = eii.impl_safety { + self.word("unsafe"); + self.popen(); + } + self.print_path(&eii.eii_macro_path, false, 0); + if let Safety::Unsafe(..) = eii.impl_safety { + self.pclose(); + } + self.word("]"); + self.hardbreak(); + } + fn print_define_opaques(&mut self, define_opaque: Option<&[(ast::NodeId, ast::Path)]>) { if let Some(define_opaque) = define_opaque { self.word("#[define_opaque("); diff --git a/compiler/rustc_attr_parsing/Cargo.toml b/compiler/rustc_attr_parsing/Cargo.toml index 886df58e8d6f..fc83c3b6e9bc 100644 --- a/compiler/rustc_attr_parsing/Cargo.toml +++ b/compiler/rustc_attr_parsing/Cargo.toml @@ -19,5 +19,5 @@ rustc_parse_format = { path = "../rustc_parse_format" } rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } rustc_target = { path = "../rustc_target" } -thin-vec = "0.2.12" +thin-vec = "0.2.15" # tidy-alphabetical-end diff --git a/compiler/rustc_attr_parsing/src/attributes/autodiff.rs b/compiler/rustc_attr_parsing/src/attributes/autodiff.rs index 31e79e118bfa..1f8c5fe3d3e5 100644 --- a/compiler/rustc_attr_parsing/src/attributes/autodiff.rs +++ b/compiler/rustc_attr_parsing/src/attributes/autodiff.rs @@ -8,8 +8,8 @@ use rustc_span::{Symbol, sym}; use thin_vec::ThinVec; +use crate::attributes::SingleAttributeParser; use crate::attributes::prelude::Allow; -use crate::attributes::{OnDuplicate, SingleAttributeParser}; use crate::context::{AcceptContext, Stage}; use crate::parser::{ArgParser, MetaItemOrLitParser}; use crate::target_checking::AllowedTargets; @@ -18,7 +18,6 @@ impl SingleAttributeParser for RustcAutodiffParser { const PATH: &[Symbol] = &[sym::rustc_autodiff]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), diff --git a/compiler/rustc_attr_parsing/src/attributes/body.rs b/compiler/rustc_attr_parsing/src/attributes/body.rs index a1492d761946..46285c2323b8 100644 --- a/compiler/rustc_attr_parsing/src/attributes/body.rs +++ b/compiler/rustc_attr_parsing/src/attributes/body.rs @@ -6,7 +6,6 @@ impl NoArgsAttributeParser for CoroutineParser { const PATH: &[Symbol] = &[sym::coroutine]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Closure)]); const CREATE: fn(rustc_span::Span) -> AttributeKind = |span| AttributeKind::Coroutine(span); } diff --git a/compiler/rustc_attr_parsing/src/attributes/cfg.rs b/compiler/rustc_attr_parsing/src/attributes/cfg.rs index ccc4a1a64c56..84c83be8b4a5 100644 --- a/compiler/rustc_attr_parsing/src/attributes/cfg.rs +++ b/compiler/rustc_attr_parsing/src/attributes/cfg.rs @@ -2,7 +2,7 @@ use rustc_ast::token::Delimiter; use rustc_ast::tokenstream::DelimSpan; -use rustc_ast::{AttrItem, Attribute, CRATE_NODE_ID, LitKind, ast, token}; +use rustc_ast::{AttrItem, Attribute, LitKind, ast, token}; use rustc_errors::{Applicability, PResult, msg}; use rustc_feature::{ AttrSuggestionStyle, AttributeTemplate, Features, GatedCfg, find_gated_cfg, template, @@ -19,6 +19,7 @@ use rustc_span::{ErrorGuaranteed, Span, Symbol, sym}; use thin_vec::ThinVec; +use crate::attributes::AttributeSafety; use crate::context::{AcceptContext, ShouldEmit, Stage}; use crate::parser::{ AllowExprMetavar, ArgParser, MetaItemListParser, MetaItemOrLitParser, NameValueParser, @@ -78,7 +79,7 @@ pub fn parse_cfg( } } - adcx.expected_single_argument(list.span); + adcx.expected_single_argument(list.span, list.len()); return None; }; parse_cfg_entry(cx, single).ok() @@ -93,7 +94,7 @@ pub fn parse_cfg_entry( ArgParser::List(list) => match meta.path().word_sym() { Some(sym::not) => { let Some(single) = list.single() else { - return Err(cx.adcx().expected_single_argument(list.span)); + return Err(cx.adcx().expected_single_argument(list.span, list.len())); }; CfgEntry::Not(Box::new(parse_cfg_entry(cx, single)?), list.span) } @@ -324,12 +325,13 @@ pub fn parse_cfg_attr( cfg_attr: &Attribute, sess: &Session, features: Option<&Features>, + lint_node_id: ast::NodeId, ) -> Option<(CfgEntry, Vec<(AttrItem, Span)>)> { match cfg_attr.get_normal_item().args.unparsed_ref().unwrap() { ast::AttrArgs::Delimited(ast::DelimArgs { dspan, delim, tokens }) if !tokens.is_empty() => { check_cfg_attr_bad_delim(&sess.psess, *dspan, *delim); match parse_in(&sess.psess, tokens.clone(), "`cfg_attr` input", |p| { - parse_cfg_attr_internal(p, sess, features, cfg_attr) + parse_cfg_attr_internal(p, sess, features, lint_node_id, cfg_attr) }) { Ok(r) => return Some(r), Err(e) => { @@ -390,6 +392,7 @@ fn parse_cfg_attr_internal<'a>( parser: &mut Parser<'a>, sess: &'a Session, features: Option<&Features>, + lint_node_id: ast::NodeId, attribute: &Attribute, ) -> PResult<'a, (CfgEntry, Vec<(ast::AttrItem, Span)>)> { // Parse cfg predicate @@ -408,9 +411,10 @@ fn parse_cfg_attr_internal<'a>( attribute.style, AttrPath { segments: attribute.path().into_boxed_slice(), span: attribute.span }, Some(attribute.get_normal_item().unsafety), + AttributeSafety::Normal, ParsedDescription::Attribute, pred_span, - CRATE_NODE_ID, + lint_node_id, Target::Crate, features, ShouldEmit::ErrorsAndLints { recovery: Recovery::Allowed }, diff --git a/compiler/rustc_attr_parsing/src/attributes/cfg_select.rs b/compiler/rustc_attr_parsing/src/attributes/cfg_select.rs index 4ff224006ca8..918fd0a4582b 100644 --- a/compiler/rustc_attr_parsing/src/attributes/cfg_select.rs +++ b/compiler/rustc_attr_parsing/src/attributes/cfg_select.rs @@ -12,6 +12,7 @@ use rustc_session::lint::builtin::UNREACHABLE_CFG_SELECT_PREDICATES; use rustc_span::{ErrorGuaranteed, Span, Symbol, sym}; +use crate::attributes::AttributeSafety; use crate::parser::{AllowExprMetavar, MetaItemOrLitParser}; use crate::{AttributeParser, ParsedDescription, ShouldEmit, errors, parse_cfg_entry}; @@ -105,6 +106,7 @@ pub fn parse_cfg_select( AttrStyle::Inner, AttrPath { segments: vec![sym::cfg_select].into_boxed_slice(), span: cfg_span }, None, + AttributeSafety::Normal, ParsedDescription::Macro, cfg_span, lint_node_id, diff --git a/compiler/rustc_attr_parsing/src/attributes/cfi_encoding.rs b/compiler/rustc_attr_parsing/src/attributes/cfi_encoding.rs index 81d5c8f99f45..32ea506211c9 100644 --- a/compiler/rustc_attr_parsing/src/attributes/cfi_encoding.rs +++ b/compiler/rustc_attr_parsing/src/attributes/cfi_encoding.rs @@ -8,7 +8,6 @@ impl SingleAttributeParser for CfiEncodingParser { Allow(Target::Enum), Allow(Target::Union), ]); - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const TEMPLATE: AttributeTemplate = template!(NameValueStr: "encoding"); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { diff --git a/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs index 93664aff4915..357be2f48f85 100644 --- a/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs @@ -1,7 +1,9 @@ use rustc_hir::attrs::{CoverageAttrKind, OptimizeAttr, RtsanSetting, SanitizerSet, UsedBy}; use rustc_session::parse::feature_err; +use rustc_span::edition::Edition::Edition2024; use super::prelude::*; +use crate::attributes::AttributeSafety; use crate::session_diagnostics::{ NakedFunctionIncompatibleAttribute, NullOnExport, NullOnObjcClass, NullOnObjcSelector, ObjcClassExpectedStringLiteral, ObjcSelectorExpectedStringLiteral, @@ -12,7 +14,6 @@ impl SingleAttributeParser for OptimizeParser { const PATH: &[Symbol] = &[sym::optimize]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::WarnButFutureError; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Closure), @@ -23,16 +24,7 @@ impl SingleAttributeParser for OptimizeParser { const TEMPLATE: AttributeTemplate = template!(List: &["size", "speed", "none"]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(list) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - - let Some(single) = list.single() else { - cx.adcx().expected_single_argument(list.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let res = match single.meta_item().and_then(|i| i.path().word().map(|i| i.name)) { Some(sym::size) => OptimizeAttr::Size, @@ -69,7 +61,6 @@ impl NoArgsAttributeParser for ColdParser { impl SingleAttributeParser for CoverageParser { const PATH: &[Symbol] = &[sym::coverage]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Closure), @@ -84,22 +75,13 @@ impl SingleAttributeParser for CoverageParser { const TEMPLATE: AttributeTemplate = template!(OneOf: &[sym::off, sym::on]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(args) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_specific_argument_and_list(attr_span, &[sym::on, sym::off]); - return None; - }; - - let Some(arg) = args.single() else { - cx.adcx().expected_single_argument(args.span); - return None; - }; + let arg = cx.single_element_list(args, cx.attr_span)?; let mut fail_incorrect_argument = |span| cx.adcx().expected_specific_argument(span, &[sym::on, sym::off]); let Some(arg) = arg.meta_item() else { - fail_incorrect_argument(args.span); + fail_incorrect_argument(arg.span()); return None; }; @@ -121,6 +103,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for ExportNameParser { const PATH: &[rustc_span::Symbol] = &[sym::export_name]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::WarnButFutureError; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: Some(Edition2024) }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Static), Allow(Target::Fn), @@ -158,7 +141,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcObjcClassParser { const PATH: &[rustc_span::Symbol] = &[sym::rustc_objc_class]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::ForeignStatic)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "ClassName"); @@ -190,7 +172,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcObjcSelectorParser { const PATH: &[rustc_span::Symbol] = &[sym::rustc_objc_selector]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::ForeignStatic)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "methodName"); @@ -238,6 +219,7 @@ impl AttributeParser for NakedParser { this.span = Some(cx.attr_span); } })]; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: None }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -295,15 +277,10 @@ fn finalize(self, cx: &FinalizeContext<'_, '_, S>) -> Option { let span = self.span?; - let Some(tools) = cx.tools else { - unreachable!("tools required while parsing attributes"); - }; - - let tools = tools.iter().map(|tool| tool.name).collect::>(); // only if we found a naked attribute do we do the somewhat expensive check 'outer: for other_attr in cx.all_attrs { for allowed_attr in ALLOW_LIST { - if other_attr.segments().next().is_some_and(|i| tools.contains(&i.name)) { + if other_attr.segments().next().is_some_and(|i| cx.tools.contains(&i.name)) { // effectively skips the error message being emitted below // if it's a tool attribute continue 'outer; @@ -363,6 +340,7 @@ impl NoArgsAttributeParser for TrackCallerParser { impl NoArgsAttributeParser for NoMangleParser { const PATH: &[Symbol] = &[sym::no_mangle]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: Some(Edition2024) }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowListWarnRest(&[ Allow(Target::Fn), Allow(Target::Static), @@ -394,7 +372,7 @@ impl AttributeParser for UsedParser { ArgParser::NoArgs => UsedBy::Default, ArgParser::List(list) => { let Some(l) = list.single() else { - cx.adcx().expected_single_argument(list.span); + cx.adcx().expected_single_argument(list.span, list.len()); return; }; @@ -565,6 +543,7 @@ fn extend( impl CombineAttributeParser for ForceTargetFeatureParser { type Item = (Symbol, Span); const PATH: &[Symbol] = &[sym::force_target_feature]; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: None }; const CONVERT: ConvertFn = |items, span| AttributeKind::TargetFeature { features: items, attr_span: span, @@ -608,8 +587,6 @@ impl SingleAttributeParser for SanitizeParser { r#"realtime = "nonblocking|blocking|caller""#, ]); - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { let Some(list) = args.list() else { let attr_span = cx.attr_span; @@ -712,7 +689,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for ThreadLocalParser { const PATH: &[Symbol] = &[sym::thread_local]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::WarnButFutureError; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Static), Allow(Target::ForeignStatic)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::ThreadLocal; @@ -722,7 +698,6 @@ impl NoArgsAttributeParser for ThreadLocalParser { impl NoArgsAttributeParser for RustcPassIndirectlyInNonRusticAbisParser { const PATH: &[Symbol] = &[sym::rustc_pass_indirectly_in_non_rustic_abis]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcPassIndirectlyInNonRusticAbis; } @@ -731,8 +706,8 @@ impl NoArgsAttributeParser for RustcPassIndirectlyInNonRusticAbisPa impl NoArgsAttributeParser for RustcEiiForeignItemParser { const PATH: &[Symbol] = &[sym::rustc_eii_foreign_item]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::ForeignFn)]); + const ALLOWED_TARGETS: AllowedTargets = + AllowedTargets::AllowList(&[Allow(Target::ForeignFn), Allow(Target::ForeignStatic)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcEiiForeignItem; } @@ -740,7 +715,6 @@ impl NoArgsAttributeParser for RustcEiiForeignItemParser { impl SingleAttributeParser for PatchableFunctionEntryParser { const PATH: &[Symbol] = &[sym::patchable_function_entry]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const TEMPLATE: AttributeTemplate = template!(List: &["prefix_nops = m, entry_nops = n"]); @@ -755,7 +729,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option) -> Option { return None; } - Some(AttributeKind::RustcConfusables { - symbols: self.confusables, - first_span: self.first_span.unwrap(), - }) + Some(AttributeKind::RustcConfusables { confusables: self.confusables }) } } diff --git a/compiler/rustc_attr_parsing/src/attributes/crate_level.rs b/compiler/rustc_attr_parsing/src/attributes/crate_level.rs index 774fd0805a7a..fed4ca7e76ab 100644 --- a/compiler/rustc_attr_parsing/src/attributes/crate_level.rs +++ b/compiler/rustc_attr_parsing/src/attributes/crate_level.rs @@ -108,7 +108,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for MoveSizeLimitParser { const PATH: &[Symbol] = &[sym::move_size_limit]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const TEMPLATE: AttributeTemplate = template!(NameValueStr: "N"); const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); @@ -154,7 +153,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for PatternComplexityLimitParser { const PATH: &[Symbol] = &[sym::pattern_complexity_limit]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const TEMPLATE: AttributeTemplate = template!(NameValueStr: "N"); const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); @@ -177,7 +175,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for NoCoreParser { const PATH: &[Symbol] = &[sym::no_core]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::NoCore; } @@ -204,7 +201,6 @@ impl NoArgsAttributeParser for NoMainParser { impl NoArgsAttributeParser for RustcCoherenceIsCoreParser { const PATH: &[Symbol] = &[sym::rustc_coherence_is_core]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcCoherenceIsCore; } @@ -247,7 +243,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for PanicRuntimeParser { const PATH: &[Symbol] = &[sym::panic_runtime]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::PanicRuntime; } @@ -256,7 +251,6 @@ impl NoArgsAttributeParser for PanicRuntimeParser { impl NoArgsAttributeParser for NeedsPanicRuntimeParser { const PATH: &[Symbol] = &[sym::needs_panic_runtime]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::NeedsPanicRuntime; } @@ -265,7 +259,6 @@ impl NoArgsAttributeParser for NeedsPanicRuntimeParser { impl NoArgsAttributeParser for ProfilerRuntimeParser { const PATH: &[Symbol] = &[sym::profiler_runtime]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::ProfilerRuntime; } @@ -283,7 +276,6 @@ impl NoArgsAttributeParser for NoBuiltinsParser { impl NoArgsAttributeParser for RustcPreserveUbChecksParser { const PATH: &[Symbol] = &[sym::rustc_preserve_ub_checks]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcPreserveUbChecks; } @@ -292,7 +284,6 @@ impl NoArgsAttributeParser for RustcPreserveUbChecksParser { impl NoArgsAttributeParser for RustcNoImplicitBoundsParser { const PATH: &[Symbol] = &[sym::rustc_no_implicit_bounds]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcNoImplicitBounds; } @@ -301,7 +292,6 @@ impl NoArgsAttributeParser for RustcNoImplicitBoundsParser { impl NoArgsAttributeParser for DefaultLibAllocatorParser { const PATH: &[Symbol] = &[sym::default_lib_allocator]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::DefaultLibAllocator; } diff --git a/compiler/rustc_attr_parsing/src/attributes/debugger.rs b/compiler/rustc_attr_parsing/src/attributes/debugger.rs index 3bde4949bce0..65e9b968e946 100644 --- a/compiler/rustc_attr_parsing/src/attributes/debugger.rs +++ b/compiler/rustc_attr_parsing/src/attributes/debugger.rs @@ -20,15 +20,7 @@ fn extend( cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser, ) -> impl IntoIterator { - let Some(l) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - let Some(single) = l.single() else { - cx.adcx().expected_single_argument(l.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let Some(mi) = single.meta_item() else { cx.adcx().expected_name_value(single.span(), None); return None; diff --git a/compiler/rustc_attr_parsing/src/attributes/deprecation.rs b/compiler/rustc_attr_parsing/src/attributes/deprecation.rs index 35996904e8c7..e948d120fafb 100644 --- a/compiler/rustc_attr_parsing/src/attributes/deprecation.rs +++ b/compiler/rustc_attr_parsing/src/attributes/deprecation.rs @@ -34,7 +34,6 @@ fn get( pub(crate) struct DeprecatedParser; impl SingleAttributeParser for DeprecatedParser { const PATH: &[Symbol] = &[sym::deprecated]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowListWarnRest(&[ Allow(Target::Fn), Allow(Target::Mod), diff --git a/compiler/rustc_attr_parsing/src/attributes/diagnostic/mod.rs b/compiler/rustc_attr_parsing/src/attributes/diagnostic/mod.rs index e63baf77c085..ea5e81c3db81 100644 --- a/compiler/rustc_attr_parsing/src/attributes/diagnostic/mod.rs +++ b/compiler/rustc_attr_parsing/src/attributes/diagnostic/mod.rs @@ -24,6 +24,7 @@ pub(crate) mod on_const; pub(crate) mod on_move; pub(crate) mod on_unimplemented; +pub(crate) mod on_unknown; #[derive(Copy, Clone)] pub(crate) enum Mode { @@ -35,6 +36,47 @@ pub(crate) enum Mode { DiagnosticOnConst, /// `#[diagnostic::on_move]` DiagnosticOnMove, + /// `#[diagnostic::on_unknown]` + DiagnosticOnUnknown, +} + +impl Mode { + fn as_str(&self) -> &'static str { + match self { + Self::RustcOnUnimplemented => "rustc_on_unimplemented", + Self::DiagnosticOnUnimplemented => "diagnostic::on_unimplemented", + Self::DiagnosticOnConst => "diagnostic::on_const", + Self::DiagnosticOnMove => "diagnostic::on_move", + Self::DiagnosticOnUnknown => "diagnostic::on_unknown", + } + } + + fn expected_options(&self) -> &'static str { + const DEFAULT: &str = + "at least one of the `message`, `note` and `label` options are expected"; + match self { + Self::RustcOnUnimplemented => { + "see " + } + Self::DiagnosticOnUnimplemented => DEFAULT, + Self::DiagnosticOnConst => DEFAULT, + Self::DiagnosticOnMove => DEFAULT, + Self::DiagnosticOnUnknown => DEFAULT, + } + } + + fn allowed_options(&self) -> &'static str { + const DEFAULT: &str = "only `message`, `note` and `label` are allowed as options"; + match self { + Self::RustcOnUnimplemented => { + "see " + } + Self::DiagnosticOnUnimplemented => DEFAULT, + Self::DiagnosticOnConst => DEFAULT, + Self::DiagnosticOnMove => DEFAULT, + Self::DiagnosticOnUnknown => DEFAULT, + } + } } fn merge_directives( @@ -80,6 +122,49 @@ fn merge( } } +fn parse_list<'p, S: Stage>( + cx: &mut AcceptContext<'_, '_, S>, + args: &'p ArgParser, + mode: Mode, +) -> Option<&'p MetaItemListParser> { + let span = cx.attr_span; + match args { + ArgParser::List(items) if items.len() != 0 => return Some(items), + ArgParser::List(list) => { + // We're dealing with `#[diagnostic::attr()]`. + // This can be because that is what the user typed, but that's also what we'd see + // if the user used non-metaitem syntax. See `ArgParser::from_attr_args`. + cx.emit_lint( + MALFORMED_DIAGNOSTIC_ATTRIBUTES, + AttributeLintKind::NonMetaItemDiagnosticAttribute, + list.span, + ); + } + ArgParser::NoArgs => { + cx.emit_lint( + MALFORMED_DIAGNOSTIC_ATTRIBUTES, + AttributeLintKind::MissingOptionsForDiagnosticAttribute { + attribute: mode.as_str(), + options: mode.expected_options(), + }, + span, + ); + } + ArgParser::NameValue(_) => { + cx.emit_lint( + MALFORMED_DIAGNOSTIC_ATTRIBUTES, + AttributeLintKind::MalFormedDiagnosticAttribute { + attribute: mode.as_str(), + options: mode.allowed_options(), + span, + }, + span, + ); + } + } + None +} + fn parse_directive_items<'p, S: Stage>( cx: &mut AcceptContext<'_, '_, S>, mode: Mode, @@ -97,32 +182,15 @@ fn parse_directive_items<'p, S: Stage>( let span = item.span(); macro malformed() {{ - match mode { - Mode::RustcOnUnimplemented => { - cx.emit_err(NoValueInOnUnimplemented { span: item.span() }); - } - Mode::DiagnosticOnUnimplemented => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MalformedOnUnimplementedAttr { span }, - span, - ); - } - Mode::DiagnosticOnConst => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MalformedOnConstAttr { span }, - span, - ); - } - Mode::DiagnosticOnMove => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MalformedOnMoveAttr { span }, - span, - ); - } - } + cx.emit_lint( + MALFORMED_DIAGNOSTIC_ATTRIBUTES, + AttributeLintKind::MalFormedDiagnosticAttribute { + attribute: mode.as_str(), + options: mode.allowed_options(), + span, + }, + span, + ); continue; }} @@ -136,22 +204,15 @@ fn parse_directive_items<'p, S: Stage>( }} macro duplicate($name: ident, $($first_span:tt)*) {{ - match mode { - Mode::RustcOnUnimplemented => { - cx.emit_err(NoValueInOnUnimplemented { span: item.span() }); - } - Mode::DiagnosticOnUnimplemented |Mode::DiagnosticOnConst | Mode::DiagnosticOnMove => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::IgnoredDiagnosticOption { - first_span: $($first_span)*, - later_span: span, - option_name: $name, - }, - span, - ); - } - } + cx.emit_lint( + MALFORMED_DIAGNOSTIC_ATTRIBUTES, + AttributeLintKind::IgnoredDiagnosticOption { + first_span: $($first_span)*, + later_span: span, + option_name: $name, + }, + span, + ); }} let item: &MetaItemParser = or_malformed!(item.meta_item()?); @@ -176,7 +237,8 @@ fn parse_directive_items<'p, S: Stage>( Ok((f, warnings)) => { for warning in warnings { let (FormatWarning::InvalidSpecifier { span, .. } - | FormatWarning::PositionalArgument { span, .. }) = warning; + | FormatWarning::PositionalArgument { span, .. } + | FormatWarning::DisallowedPlaceholder { span }) = warning; cx.emit_lint( MALFORMED_DIAGNOSTIC_FORMAT_LITERALS, AttributeLintKind::MalformedDiagnosticFormat { warning }, @@ -326,6 +388,10 @@ fn parse_arg( is_source_literal: bool, ) -> FormatArg { let span = slice_span(input_span, arg.position_span.clone(), is_source_literal); + if matches!(mode, Mode::DiagnosticOnUnknown) { + warnings.push(FormatWarning::DisallowedPlaceholder { span }); + return FormatArg::AsIs(sym::empty_braces); + } match arg.position { // Something like "hello {name}" @@ -525,15 +591,6 @@ pub(crate) enum InvalidOnClause { }, } -#[derive(Diagnostic)] -#[diag("this attribute must have a value", code = E0232)] -#[note("e.g. `#[rustc_on_unimplemented(message=\"foo\")]`")] -pub(crate) struct NoValueInOnUnimplemented { - #[primary_span] - #[label("expected value here")] - pub span: Span, -} - #[derive(Diagnostic)] #[diag( "using multiple `rustc_on_unimplemented` (or mixing it with `diagnostic::on_unimplemented`) is not supported" diff --git a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_const.rs b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_const.rs index def4069f6b47..1e62c03fc3b6 100644 --- a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_const.rs +++ b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_const.rs @@ -1,6 +1,4 @@ use rustc_hir::attrs::diagnostic::Directive; -use rustc_hir::lints::AttributeLintKind; -use rustc_session::lint::builtin::MALFORMED_DIAGNOSTIC_ATTRIBUTES; use crate::attributes::diagnostic::*; use crate::attributes::prelude::*; @@ -17,35 +15,17 @@ impl AttributeParser for OnConstParser { template!(List: &[r#"/*opt*/ message = "...", /*opt*/ label = "...", /*opt*/ note = "...""#]), |this, cx, args| { if !cx.features().diagnostic_on_const() { + // `UnknownDiagnosticAttribute` is emitted in rustc_resolve/macros.rs return; } let span = cx.attr_span; this.span = Some(span); + let mode = Mode::DiagnosticOnConst; - let items = match args { - ArgParser::List(items) if items.len() != 0 => items, - ArgParser::NoArgs | ArgParser::List(_) => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MissingOptionsForOnConst, - span, - ); - return; - } - ArgParser::NameValue(_) => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MalformedOnConstAttr { span }, - span, - ); - return; - } - }; + let Some(items) = parse_list(cx, args, mode) else { return }; - let Some(directive) = - parse_directive_items(cx, Mode::DiagnosticOnConst, items.mixed(), true) - else { + let Some(directive) = parse_directive_items(cx, mode, items.mixed(), true) else { return; }; merge_directives(cx, &mut this.directive, (span, directive)); diff --git a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_move.rs b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_move.rs index 006b3b66658e..2b62ab7f3d11 100644 --- a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_move.rs +++ b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_move.rs @@ -1,7 +1,5 @@ use rustc_feature::template; use rustc_hir::attrs::AttributeKind; -use rustc_hir::lints::AttributeLintKind; -use rustc_session::lint::builtin::MALFORMED_DIAGNOSTIC_ATTRIBUTES; use rustc_span::sym; use crate::attributes::diagnostic::*; @@ -24,30 +22,16 @@ fn parse<'sess, S: Stage>( mode: Mode, ) { if !cx.features().diagnostic_on_move() { + // `UnknownDiagnosticAttribute` is emitted in rustc_resolve/macros.rs return; } let span = cx.attr_span; self.span = Some(span); - let Some(list) = args.list() else { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MissingOptionsForOnMove, - span, - ); - return; - }; - if list.is_empty() { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::OnMoveMalformedAttrExpectedLiteralOrDelimiter, - list.span, - ); - return; - } + let Some(items) = parse_list(cx, args, mode) else { return }; - if let Some(directive) = parse_directive_items(cx, mode, list.mixed(), true) { + if let Some(directive) = parse_directive_items(cx, mode, items.mixed(), true) { merge_directives(cx, &mut self.directive, (span, directive)); } } diff --git a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unimplemented.rs b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unimplemented.rs index 12028059b7d4..dce3226670a1 100644 --- a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unimplemented.rs +++ b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unimplemented.rs @@ -1,6 +1,4 @@ use rustc_hir::attrs::diagnostic::Directive; -use rustc_hir::lints::AttributeLintKind; -use rustc_session::lint::builtin::MALFORMED_DIAGNOSTIC_ATTRIBUTES; use crate::attributes::diagnostic::*; use crate::attributes::prelude::*; @@ -29,25 +27,7 @@ fn parse<'sess, S: Stage>( return; } - let items = match args { - ArgParser::List(items) if items.len() != 0 => items, - ArgParser::NoArgs | ArgParser::List(_) => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MissingOptionsForOnUnimplemented, - span, - ); - return; - } - ArgParser::NameValue(_) => { - cx.emit_lint( - MALFORMED_DIAGNOSTIC_ATTRIBUTES, - AttributeLintKind::MalformedOnUnimplementedAttr { span }, - span, - ); - return; - } - }; + let Some(items) = parse_list(cx, args, mode) else { return }; if let Some(directive) = parse_directive_items(cx, mode, items.mixed(), true) { merge_directives(cx, &mut self.directive, (span, directive)); diff --git a/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unknown.rs b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unknown.rs new file mode 100644 index 000000000000..a5364f968b21 --- /dev/null +++ b/compiler/rustc_attr_parsing/src/attributes/diagnostic/on_unknown.rs @@ -0,0 +1,57 @@ +use rustc_hir::attrs::diagnostic::Directive; + +use crate::attributes::diagnostic::*; +use crate::attributes::prelude::*; + +#[derive(Default)] +pub(crate) struct OnUnknownParser { + span: Option, + directive: Option<(Span, Directive)>, +} + +impl OnUnknownParser { + fn parse<'sess, S: Stage>( + &mut self, + cx: &mut AcceptContext<'_, 'sess, S>, + args: &ArgParser, + mode: Mode, + ) { + if let Some(features) = cx.features + && !features.diagnostic_on_unknown() + { + // `UnknownDiagnosticAttribute` is emitted in rustc_resolve/macros.rs + return; + } + let span = cx.attr_span; + self.span = Some(span); + + let Some(items) = parse_list(cx, args, mode) else { return }; + + if let Some(directive) = parse_directive_items(cx, mode, items.mixed(), true) { + merge_directives(cx, &mut self.directive, (span, directive)); + }; + } +} + +impl AttributeParser for OnUnknownParser { + const ATTRIBUTES: AcceptMapping = &[( + &[sym::diagnostic, sym::on_unknown], + template!(List: &[r#"/*opt*/ message = "...", /*opt*/ label = "...", /*opt*/ note = "...""#]), + |this, cx, args| { + this.parse(cx, args, Mode::DiagnosticOnUnknown); + }, + )]; + //FIXME attribute is not parsed for non-use statements but diagnostics are issued in `check_attr.rs` + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); + + fn finalize(self, _cx: &FinalizeContext<'_, '_, S>) -> Option { + if let Some(span) = self.span { + Some(AttributeKind::OnUnknown { + span, + directive: self.directive.map(|d| Box::new(d.1)), + }) + } else { + None + } + } +} diff --git a/compiler/rustc_attr_parsing/src/attributes/doc.rs b/compiler/rustc_attr_parsing/src/attributes/doc.rs index 99f856684abd..a5b8c0ebe25e 100644 --- a/compiler/rustc_attr_parsing/src/attributes/doc.rs +++ b/compiler/rustc_attr_parsing/src/attributes/doc.rs @@ -1,5 +1,5 @@ use rustc_ast::ast::{AttrStyle, LitKind, MetaItemLit}; -use rustc_errors::msg; +use rustc_errors::{Diagnostic, msg}; use rustc_feature::template; use rustc_hir::Target; use rustc_hir::attrs::{ @@ -171,12 +171,15 @@ fn parse_single_test_doc_attr_item( if let Some(used_span) = self.attribute.no_crate_inject { let unused_span = path.span(); - cx.emit_lint( + cx.emit_dyn_lint( rustc_session::lint::builtin::INVALID_DOC_ATTRIBUTES, - AttributeLintKind::UnusedDuplicate { - this: unused_span, - other: used_span, - warning: true, + move |dcx, level| { + rustc_errors::lints::UnusedDuplicate { + this: unused_span, + other: used_span, + warning: true, + } + .into_diag(dcx, level) }, unused_span, ); diff --git a/compiler/rustc_attr_parsing/src/attributes/inline.rs b/compiler/rustc_attr_parsing/src/attributes/inline.rs index f34a776d9ae8..32f995753bad 100644 --- a/compiler/rustc_attr_parsing/src/attributes/inline.rs +++ b/compiler/rustc_attr_parsing/src/attributes/inline.rs @@ -38,7 +38,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option Some(AttributeKind::Inline(InlineAttr::Hint, cx.attr_span)), ArgParser::List(list) => { let Some(l) = list.single() else { - cx.adcx().expected_single_argument(list.span); + cx.adcx().expected_single_argument(list.span, list.len()); return None; }; @@ -67,7 +67,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcForceInlineParser { const PATH: &[Symbol] = &[sym::rustc_force_inline]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::WarnButFutureError; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -80,7 +79,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option None, ArgParser::List(list) => { let Some(l) = list.single() else { - cx.adcx().expected_single_argument(list.span); + cx.adcx().expected_single_argument(list.span, list.len()); return None; }; diff --git a/compiler/rustc_attr_parsing/src/attributes/instruction_set.rs b/compiler/rustc_attr_parsing/src/attributes/instruction_set.rs index 00e2241f2e70..36e45a763e17 100644 --- a/compiler/rustc_attr_parsing/src/attributes/instruction_set.rs +++ b/compiler/rustc_attr_parsing/src/attributes/instruction_set.rs @@ -15,16 +15,11 @@ impl SingleAttributeParser for InstructionSetParser { Allow(Target::Method(MethodKind::Trait { body: true })), ]); const TEMPLATE: AttributeTemplate = template!(List: &["set"], "https://doc.rust-lang.org/reference/attributes/codegen.html#the-instruction_set-attribute"); - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { const POSSIBLE_SYMBOLS: &[Symbol] = &[sym::arm_a32, sym::arm_t32]; const POSSIBLE_ARM_SYMBOLS: &[Symbol] = &[sym::a32, sym::t32]; - let Some(maybe_meta_item) = args.list().and_then(MetaItemListParser::single) else { - let attr_span = cx.attr_span; - cx.adcx().expected_specific_argument(attr_span, POSSIBLE_SYMBOLS); - return None; - }; + let maybe_meta_item = cx.single_element_list(args, cx.attr_span)?; let Some(meta_item) = maybe_meta_item.meta_item() else { cx.adcx().expected_specific_argument(maybe_meta_item.span(), POSSIBLE_SYMBOLS); diff --git a/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs index 6ae4e31af9df..9f48f7f8ab55 100644 --- a/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs @@ -5,11 +5,13 @@ use rustc_session::Session; use rustc_session::lint::builtin::ILL_FORMED_ATTRIBUTE_INPUT; use rustc_session::parse::feature_err; +use rustc_span::edition::Edition::Edition2024; use rustc_span::kw; use rustc_target::spec::{Arch, BinaryFormat}; use super::prelude::*; use super::util::parse_single_integer; +use crate::attributes::AttributeSafety; use crate::attributes::cfg::parse_cfg_entry; use crate::session_diagnostics::{ AsNeededCompatibility, BundleNeedsStatic, EmptyLinkName, ExportSymbolsNeedsStatic, @@ -388,12 +390,7 @@ fn parse_link_cfg( cx.adcx().duplicate_key(item.span(), sym::cfg); return true; } - let Some(link_cfg) = item.args().list() else { - cx.adcx().expected_list(item.span(), item.args()); - return true; - }; - let Some(link_cfg) = link_cfg.single() else { - cx.adcx().expected_single_argument(item.span()); + let Some(link_cfg) = cx.single_element_list(item.args(), item.span()) else { return true; }; if !features.link_cfg() { @@ -468,6 +465,7 @@ fn parse_link_import_name_type( impl SingleAttributeParser for LinkSectionParser { const PATH: &[Symbol] = &[sym::link_section]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::WarnButFutureError; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: Some(Edition2024) }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowListWarnRest(&[ Allow(Target::Static), Allow(Target::Fn), @@ -504,7 +502,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for ExportStableParser { const PATH: &[Symbol] = &[sym::export_stable]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); //FIXME Still checked fully in `check_attr.rs` const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::ExportStable; } @@ -512,7 +509,7 @@ impl NoArgsAttributeParser for ExportStableParser { pub(crate) struct FfiConstParser; impl NoArgsAttributeParser for FfiConstParser { const PATH: &[Symbol] = &[sym::ffi_const]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: None }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::FfiConst; } @@ -520,7 +517,7 @@ impl NoArgsAttributeParser for FfiConstParser { pub(crate) struct FfiPureParser; impl NoArgsAttributeParser for FfiPureParser { const PATH: &[Symbol] = &[sym::ffi_pure]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; + const SAFETY: AttributeSafety = AttributeSafety::Unsafe { unsafe_since: None }; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::FfiPure; } @@ -528,7 +525,6 @@ impl NoArgsAttributeParser for FfiPureParser { pub(crate) struct RustcStdInternalSymbolParser; impl NoArgsAttributeParser for RustcStdInternalSymbolParser { const PATH: &[Symbol] = &[sym::rustc_std_internal_symbol]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::ForeignFn), @@ -542,7 +538,6 @@ impl NoArgsAttributeParser for RustcStdInternalSymbolParser { impl SingleAttributeParser for LinkOrdinalParser { const PATH: &[Symbol] = &[sym::link_ordinal]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::ForeignFn), Allow(Target::ForeignStatic), @@ -583,7 +578,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for LinkageParser { const PATH: &[Symbol] = &[sym::linkage]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -666,7 +660,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for NeedsAllocatorParser { const PATH: &[Symbol] = &[sym::needs_allocator]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::NeedsAllocator; } @@ -675,7 +668,6 @@ impl NoArgsAttributeParser for NeedsAllocatorParser { impl NoArgsAttributeParser for CompilerBuiltinsParser { const PATH: &[Symbol] = &[sym::compiler_builtins]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::CompilerBuiltins; } diff --git a/compiler/rustc_attr_parsing/src/attributes/lint.rs b/compiler/rustc_attr_parsing/src/attributes/lint.rs deleted file mode 100644 index f9c8ff6e6874..000000000000 --- a/compiler/rustc_attr_parsing/src/attributes/lint.rs +++ /dev/null @@ -1,371 +0,0 @@ -use rustc_ast::LitKind; -use rustc_hir::HashIgnoredAttrId; -use rustc_hir::attrs::{LintAttribute, LintAttributeKind, LintInstance}; -use rustc_hir::lints::AttributeLintKind; -use rustc_hir::target::GenericParamKind; -use rustc_session::DynLintStore; -use rustc_session::lint::builtin::{RENAMED_AND_REMOVED_LINTS, UNKNOWN_LINTS, UNUSED_ATTRIBUTES}; -use rustc_session::lint::{CheckLintNameResult, LintId}; - -use super::prelude::*; -use crate::attributes::AcceptFn; -use crate::session_diagnostics::UnknownToolInScopedLint; - -pub(crate) trait Lint { - const KIND: LintAttributeKind; - const ATTR_SYMBOL: Symbol = Self::KIND.symbol(); -} - -pub(crate) struct Allow; - -impl Lint for Allow { - const KIND: LintAttributeKind = LintAttributeKind::Allow; -} -pub(crate) struct Deny; - -impl Lint for Deny { - const KIND: LintAttributeKind = LintAttributeKind::Deny; -} -pub(crate) struct Expect; - -impl Lint for Expect { - const KIND: LintAttributeKind = LintAttributeKind::Expect; -} -pub(crate) struct Forbid; - -impl Lint for Forbid { - const KIND: LintAttributeKind = LintAttributeKind::Forbid; -} -pub(crate) struct Warn; - -impl Lint for Warn { - const KIND: LintAttributeKind = LintAttributeKind::Warn; -} - -#[derive(Default)] -pub(crate) struct LintParser { - lint_attrs: ThinVec, -} - -trait Mapping { - const MAPPING: (&'static [Symbol], AttributeTemplate, AcceptFn); -} -impl Mapping for T { - const MAPPING: (&'static [Symbol], AttributeTemplate, AcceptFn) = ( - &[T::ATTR_SYMBOL], - template!( - List: &["lint1", "lint1, lint2, ...", r#"lint1, lint2, lint3, reason = "...""#], - "https://doc.rust-lang.org/reference/attributes/diagnostics.html#lint-check-attributes" - ), - |this, cx, args| { - if let Some(lint_attr) = validate_lint_attr::(cx, args) { - this.lint_attrs.push(lint_attr); - } - }, - ); -} - -impl AttributeParser for LintParser { - const ATTRIBUTES: AcceptMapping = - &[Allow::MAPPING, Deny::MAPPING, Expect::MAPPING, Forbid::MAPPING, Warn::MAPPING]; - - const ALLOWED_TARGETS: AllowedTargets = { - use super::prelude::{Allow, Warn}; - AllowedTargets::AllowList(&[ - Allow(Target::ExternCrate), - Allow(Target::Use), - Allow(Target::Static), - Allow(Target::Const), - Allow(Target::Fn), - Allow(Target::Closure), - Allow(Target::Mod), - Allow(Target::ForeignMod), - Allow(Target::GlobalAsm), - Allow(Target::TyAlias), - Allow(Target::Enum), - Allow(Target::Variant), - Allow(Target::Struct), - Allow(Target::Field), - Allow(Target::Union), - Allow(Target::Trait), - Allow(Target::TraitAlias), - Allow(Target::Impl { of_trait: false }), - Allow(Target::Impl { of_trait: true }), - Allow(Target::Expression), - Allow(Target::Statement), - Allow(Target::Arm), - Allow(Target::AssocConst), - Allow(Target::Method(MethodKind::Inherent)), - Allow(Target::Method(MethodKind::Trait { body: false })), - Allow(Target::Method(MethodKind::Trait { body: true })), - Allow(Target::Method(MethodKind::TraitImpl)), - Allow(Target::AssocTy), - Allow(Target::ForeignFn), - Allow(Target::ForeignStatic), - Allow(Target::ForeignTy), - Allow(Target::MacroDef), - Allow(Target::Param), - Allow(Target::PatField), - Allow(Target::ExprField), - Allow(Target::Crate), - Allow(Target::Delegation { mac: false }), - Allow(Target::Delegation { mac: true }), - Allow(Target::GenericParam { kind: GenericParamKind::Type, has_default: false }), - Allow(Target::GenericParam { kind: GenericParamKind::Lifetime, has_default: false }), - Allow(Target::GenericParam { kind: GenericParamKind::Const, has_default: false }), - Allow(Target::GenericParam { kind: GenericParamKind::Type, has_default: true }), - Allow(Target::GenericParam { kind: GenericParamKind::Lifetime, has_default: true }), - Allow(Target::GenericParam { kind: GenericParamKind::Const, has_default: true }), - Warn(Target::MacroCall), - ]) - }; - - fn finalize(mut self, _cx: &FinalizeContext<'_, '_, S>) -> Option { - if !self.lint_attrs.is_empty() { - // Sort to ensure correct order operations later - self.lint_attrs.sort_by(|a, b| a.attr_span.cmp(&b.attr_span)); - Some(AttributeKind::LintAttributes(self.lint_attrs)) - } else { - None - } - } -} - -#[inline(always)] -fn validate_lint_attr( - cx: &mut AcceptContext<'_, '_, S>, - args: &ArgParser, -) -> Option { - let Some(lint_store) = cx.sess.lint_store.as_ref().map(|store| store.to_owned()) else { - unreachable!("lint_store required while parsing attributes"); - }; - let lint_store = lint_store.as_ref(); - let Some(list) = args.list() else { - let span = cx.inner_span; - cx.adcx().expected_list(span, args); - return None; - }; - let mut list = list.mixed().peekable(); - - let mut skip_unused_check = false; - let mut errored = false; - let mut reason = None; - let mut lint_instances = ThinVec::new(); - let mut lint_index = 0; - let targeting_crate = matches!(cx.target, Target::Crate); - while let Some(item) = list.next() { - let Some(meta_item) = item.meta_item() else { - cx.adcx().expected_identifier(item.span()); - errored = true; - continue; - }; - - match meta_item.args() { - ArgParser::NameValue(nv_parser) if meta_item.path().word_is(sym::reason) => { - //FIXME replace this with duplicate check? - if list.peek().is_some() { - cx.adcx().expected_nv_as_last_argument(meta_item.span(), sym::reason); - errored = true; - continue; - } - - let val_lit = nv_parser.value_as_lit(); - let LitKind::Str(reason_sym, _) = val_lit.kind else { - cx.adcx().expected_string_literal(nv_parser.value_span, Some(val_lit)); - errored = true; - continue; - }; - reason = Some(reason_sym); - } - ArgParser::NameValue(_) => { - cx.adcx().expected_specific_argument(meta_item.span(), &[sym::reason]); - errored = true; - } - ArgParser::List(list) => { - cx.adcx().expected_no_args(list.span); - errored = true; - } - ArgParser::NoArgs => { - skip_unused_check = true; - let mut segments = meta_item.path().segments(); - - let Some(tool_or_name) = segments.next() else { - unreachable!("first segment should always exist"); - }; - - let rest = segments.collect::>(); - let (tool_name, tool_span, name): (Option, Option, _) = - if rest.is_empty() { - let name = tool_or_name.name; - (None, None, name.to_string()) - } else { - let tool = tool_or_name; - let name = rest - .into_iter() - .map(|ident| ident.to_string()) - .collect::>() - .join("::"); - (Some(tool.name), Some(tool.span), name) - }; - - let meta_item_span = meta_item.span(); - let original_name = Symbol::intern(&name); - let mut full_name = tool_name - .map(|tool| Symbol::intern(&format!("{tool}::{}", original_name))) - .unwrap_or(original_name); - - if let Some(ids) = check_lint( - cx, - lint_store, - original_name, - &mut full_name, - tool_name, - tool_span, - meta_item_span, - ) { - if !targeting_crate && ids.iter().any(|lint_id| lint_id.lint.crate_level_only) { - cx.emit_lint( - UNUSED_ATTRIBUTES, - AttributeLintKind::IgnoredUnlessCrateSpecified { - level: T::ATTR_SYMBOL, - name: original_name, - }, - meta_item_span, - ); - } - lint_instances.extend(ids.into_iter().map(|id| { - LintInstance::new(full_name, id.to_string(), meta_item_span, lint_index) - })); - } - lint_index += 1; - } - } - } - if !skip_unused_check && !errored && lint_instances.is_empty() { - let span = cx.attr_span; - cx.adcx().warn_empty_attribute(span); - } - - (!errored).then_some(LintAttribute { - reason, - lint_instances, - attr_span: cx.attr_span, - attr_style: cx.attr_style, - attr_id: HashIgnoredAttrId { attr_id: cx.attr_id }, - kind: T::KIND, - }) -} - -fn check_lint<'a, S: Stage>( - cx: &mut AcceptContext<'_, '_, S>, - lint_store: &'a dyn DynLintStore, - original_name: Symbol, - full_name: &mut Symbol, - tool_name: Option, - tool_span: Option, - span: Span, -) -> Option<&'a [LintId]> { - let Some(tools) = cx.tools else { - unreachable!("tools required while parsing attributes"); - }; - if tools.is_empty() { - unreachable!("tools should never be empty") - } - - match lint_store.check_lint_name(original_name.as_str(), tool_name, tools) { - CheckLintNameResult::Ok(ids) => Some(ids), - CheckLintNameResult::Tool(ids, new_lint_name) => { - let _name = match new_lint_name { - None => original_name, - Some(new_lint_name) => { - let new_lint_name = Symbol::intern(&new_lint_name); - cx.emit_lint( - RENAMED_AND_REMOVED_LINTS, - AttributeLintKind::DeprecatedLintName { - name: *full_name, - suggestion: span, - replace: new_lint_name, - }, - span, - ); - new_lint_name - } - }; - Some(ids) - } - - CheckLintNameResult::MissingTool => { - // If `MissingTool` is returned, then either the lint does not - // exist in the tool or the code was not compiled with the tool and - // therefore the lint was never added to the `LintStore`. To detect - // this is the responsibility of the lint tool. - None - } - - CheckLintNameResult::NoTool => { - cx.emit_err(UnknownToolInScopedLint { - span: tool_span, - tool_name: tool_name.unwrap(), - full_lint_name: *full_name, - is_nightly_build: cx.sess.is_nightly_build(), - }); - None - } - - CheckLintNameResult::Renamed(replace) => { - cx.emit_lint( - RENAMED_AND_REMOVED_LINTS, - AttributeLintKind::RenamedLint { name: *full_name, replace, suggestion: span }, - span, - ); - - // Since it was renamed, and we have emitted the warning - // we replace the "full_name", to ensure we don't get notes with: - // `#[allow(NEW_NAME)]` implied by `#[allow(OLD_NAME)]` - // Other lints still have access to the original name as the user wrote it, - // through `original_name` - *full_name = replace; - - // If this lint was renamed, apply the new lint instead of ignoring the - // attribute. Ignore any errors or warnings that happen because the new - // name is inaccurate. - // NOTE: `new_name` already includes the tool name, so we don't - // have to add it again. - match lint_store.check_lint_name(replace.as_str(), None, tools) { - CheckLintNameResult::Ok(ids) => Some(ids), - _ => panic!("renamed lint does not exist: {replace}"), - } - } - - CheckLintNameResult::RenamedToolLint(new_name) => { - cx.emit_lint( - RENAMED_AND_REMOVED_LINTS, - AttributeLintKind::RenamedLint { - name: *full_name, - replace: new_name, - suggestion: span, - }, - span, - ); - None - } - - CheckLintNameResult::Removed(reason) => { - cx.emit_lint( - RENAMED_AND_REMOVED_LINTS, - AttributeLintKind::RemovedLint { name: *full_name, reason }, - span, - ); - None - } - - CheckLintNameResult::NoLint(suggestion) => { - cx.emit_lint( - UNKNOWN_LINTS, - AttributeLintKind::UnknownLint { name: *full_name, suggestion, span }, - span, - ); - None - } - } -} diff --git a/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs b/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs index 76bddacd20bf..db29f193802e 100644 --- a/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs +++ b/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs @@ -3,7 +3,6 @@ pub(crate) struct RustcAsPtrParser; impl NoArgsAttributeParser for RustcAsPtrParser { const PATH: &[Symbol] = &[sym::rustc_as_ptr]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -17,7 +16,6 @@ impl NoArgsAttributeParser for RustcAsPtrParser { pub(crate) struct RustcPubTransparentParser; impl NoArgsAttributeParser for RustcPubTransparentParser { const PATH: &[Symbol] = &[sym::rustc_pub_transparent]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Struct), Allow(Target::Enum), @@ -29,7 +27,6 @@ impl NoArgsAttributeParser for RustcPubTransparentParser { pub(crate) struct RustcPassByValueParser; impl NoArgsAttributeParser for RustcPassByValueParser { const PATH: &[Symbol] = &[sym::rustc_pass_by_value]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Struct), Allow(Target::Enum), @@ -41,7 +38,6 @@ impl NoArgsAttributeParser for RustcPassByValueParser { pub(crate) struct RustcShouldNotBeCalledOnConstItemsParser; impl NoArgsAttributeParser for RustcShouldNotBeCalledOnConstItemsParser { const PATH: &[Symbol] = &[sym::rustc_should_not_be_called_on_const_items]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Method(MethodKind::Inherent)), Allow(Target::Method(MethodKind::TraitImpl)), diff --git a/compiler/rustc_attr_parsing/src/attributes/loop_match.rs b/compiler/rustc_attr_parsing/src/attributes/loop_match.rs index 528090b8673d..1ad34baeeb88 100644 --- a/compiler/rustc_attr_parsing/src/attributes/loop_match.rs +++ b/compiler/rustc_attr_parsing/src/attributes/loop_match.rs @@ -3,7 +3,6 @@ pub(crate) struct LoopMatchParser; impl NoArgsAttributeParser for LoopMatchParser { const PATH: &[Symbol] = &[sym::loop_match]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Expression)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::LoopMatch; } @@ -11,7 +10,6 @@ impl NoArgsAttributeParser for LoopMatchParser { pub(crate) struct ConstContinueParser; impl NoArgsAttributeParser for ConstContinueParser { const PATH: &[Symbol] = &[sym::const_continue]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Expression)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::ConstContinue; } diff --git a/compiler/rustc_attr_parsing/src/attributes/macro_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/macro_attrs.rs index 3467d5712e1a..7dcf1b3eb064 100644 --- a/compiler/rustc_attr_parsing/src/attributes/macro_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/macro_attrs.rs @@ -167,7 +167,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for CollapseDebugInfoParser { const PATH: &[Symbol] = &[sym::collapse_debuginfo]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const TEMPLATE: AttributeTemplate = template!( List: &["no", "external", "yes"], "https://doc.rust-lang.org/reference/attributes/debugger.html#the-collapse_debuginfo-attribute" @@ -175,15 +174,7 @@ impl SingleAttributeParser for CollapseDebugInfoParser { const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::MacroDef)]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(list) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - let Some(single) = list.single() else { - cx.adcx().expected_single_argument(list.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let Some(mi) = single.meta_item() else { cx.adcx().expected_not_literal(single.span()); return None; @@ -211,7 +202,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcProcMacroDeclsParser { const PATH: &[Symbol] = &[sym::rustc_proc_macro_decls]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Static)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcProcMacroDecls; } diff --git a/compiler/rustc_attr_parsing/src/attributes/mod.rs b/compiler/rustc_attr_parsing/src/attributes/mod.rs index 66f452040954..ba2e2b54e25b 100644 --- a/compiler/rustc_attr_parsing/src/attributes/mod.rs +++ b/compiler/rustc_attr_parsing/src/attributes/mod.rs @@ -18,6 +18,7 @@ use rustc_feature::{AttributeTemplate, template}; use rustc_hir::attrs::AttributeKind; +use rustc_span::edition::Edition; use rustc_span::{Span, Symbol}; use thin_vec::ThinVec; @@ -46,7 +47,6 @@ pub(crate) mod inline; pub(crate) mod instruction_set; pub(crate) mod link_attrs; -pub(crate) mod lint; pub(crate) mod lint_helpers; pub(crate) mod loop_match; pub(crate) mod macro_attrs; @@ -98,6 +98,7 @@ pub(crate) trait AttributeParser: Default + 'static { /// If an attribute has this symbol, the `accept` function will be called on it. const ATTRIBUTES: AcceptMapping; const ALLOWED_TARGETS: AllowedTargets; + const SAFETY: AttributeSafety = AttributeSafety::Normal; /// The parser has gotten a chance to accept the attributes on an item, /// here it can produce an attribute. @@ -127,7 +128,8 @@ pub(crate) trait SingleAttributeParser: 'static { /// Configures what to do when when the same attribute is /// applied more than once on the same syntax node. - const ON_DUPLICATE: OnDuplicate; + const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; + const SAFETY: AttributeSafety = AttributeSafety::Normal; const ALLOWED_TARGETS: AllowedTargets; @@ -159,13 +161,14 @@ impl, S: Stage> AttributeParser for Single if let Some(pa) = T::convert(cx, args) { if let Some((_, used)) = group.1 { T::ON_DUPLICATE.exec::(cx, used, cx.attr_span); + } else { + group.1 = Some((pa, cx.attr_span)); } - - group.1 = Some((pa, cx.attr_span)); } }, )]; const ALLOWED_TARGETS: AllowedTargets = T::ALLOWED_TARGETS; + const SAFETY: AttributeSafety = T::SAFETY; fn finalize(self, _cx: &FinalizeContext<'_, '_, S>) -> Option { Some(self.1?.0) @@ -218,6 +221,18 @@ fn exec>( } } +#[derive(Copy, Clone, PartialEq, Debug)] +pub enum AttributeSafety { + /// Normal attribute that does not need `#[unsafe(...)]` + Normal, + /// Unsafe attribute that requires safety obligations to be discharged. + /// + /// An error is emitted when `#[unsafe(...)]` is omitted, except when the attribute's edition + /// is less than the one stored in `unsafe_since`. This handles attributes that were safe in + /// earlier editions, but become unsafe in later ones. + Unsafe { unsafe_since: Option }, +} + /// An even simpler version of [`SingleAttributeParser`]: /// now automatically check that there are no arguments provided to the attribute. /// @@ -225,8 +240,9 @@ fn exec>( // pub(crate) trait NoArgsAttributeParser: 'static { const PATH: &[Symbol]; - const ON_DUPLICATE: OnDuplicate; + const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets; + const SAFETY: AttributeSafety = AttributeSafety::Normal; /// Create the [`AttributeKind`] given attribute's [`Span`]. const CREATE: fn(Span) -> AttributeKind; @@ -243,6 +259,7 @@ fn default() -> Self { impl, S: Stage> SingleAttributeParser for WithoutArgs { const PATH: &[Symbol] = T::PATH; const ON_DUPLICATE: OnDuplicate = T::ON_DUPLICATE; + const SAFETY: AttributeSafety = T::SAFETY; const ALLOWED_TARGETS: AllowedTargets = T::ALLOWED_TARGETS; const TEMPLATE: AttributeTemplate = template!(Word); @@ -272,6 +289,7 @@ pub(crate) trait CombineAttributeParser: 'static { /// For example, individual representations from `#[repr(...)]` attributes into an `AttributeKind::Repr(x)`, /// where `x` is a vec of these individual reprs. const CONVERT: ConvertFn; + const SAFETY: AttributeSafety = AttributeSafety::Normal; const ALLOWED_TARGETS: AllowedTargets; @@ -313,6 +331,7 @@ impl, S: Stage> AttributeParser for Combine) -> Option { if let Some(first_span) = self.first_span { diff --git a/compiler/rustc_attr_parsing/src/attributes/must_not_suspend.rs b/compiler/rustc_attr_parsing/src/attributes/must_not_suspend.rs index a95151812958..5ff637cdb056 100644 --- a/compiler/rustc_attr_parsing/src/attributes/must_not_suspend.rs +++ b/compiler/rustc_attr_parsing/src/attributes/must_not_suspend.rs @@ -4,7 +4,6 @@ impl SingleAttributeParser for MustNotSuspendParser { const PATH: &[rustc_span::Symbol] = &[sym::must_not_suspend]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Struct), Allow(Target::Enum), diff --git a/compiler/rustc_attr_parsing/src/attributes/pin_v2.rs b/compiler/rustc_attr_parsing/src/attributes/pin_v2.rs index 597a9515b004..52c380fbb78d 100644 --- a/compiler/rustc_attr_parsing/src/attributes/pin_v2.rs +++ b/compiler/rustc_attr_parsing/src/attributes/pin_v2.rs @@ -2,7 +2,7 @@ use rustc_hir::attrs::AttributeKind; use rustc_span::{Span, Symbol, sym}; -use crate::attributes::{NoArgsAttributeParser, OnDuplicate}; +use crate::attributes::NoArgsAttributeParser; use crate::context::Stage; use crate::target_checking::AllowedTargets; use crate::target_checking::Policy::Allow; @@ -11,7 +11,6 @@ impl NoArgsAttributeParser for PinV2Parser { const PATH: &[Symbol] = &[sym::pin_v2]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Enum), Allow(Target::Struct), diff --git a/compiler/rustc_attr_parsing/src/attributes/proc_macro_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/proc_macro_attrs.rs index c5bf8737fffb..7cb59856b8a2 100644 --- a/compiler/rustc_attr_parsing/src/attributes/proc_macro_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/proc_macro_attrs.rs @@ -9,7 +9,6 @@ pub(crate) struct ProcMacroParser; impl NoArgsAttributeParser for ProcMacroParser { const PATH: &[Symbol] = &[sym::proc_macro]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = PROC_MACRO_ALLOWED_TARGETS; const CREATE: fn(Span) -> AttributeKind = AttributeKind::ProcMacro; } @@ -17,7 +16,6 @@ impl NoArgsAttributeParser for ProcMacroParser { pub(crate) struct ProcMacroAttributeParser; impl NoArgsAttributeParser for ProcMacroAttributeParser { const PATH: &[Symbol] = &[sym::proc_macro_attribute]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = PROC_MACRO_ALLOWED_TARGETS; const CREATE: fn(Span) -> AttributeKind = AttributeKind::ProcMacroAttribute; } @@ -25,7 +23,6 @@ impl NoArgsAttributeParser for ProcMacroAttributeParser { pub(crate) struct ProcMacroDeriveParser; impl SingleAttributeParser for ProcMacroDeriveParser { const PATH: &[Symbol] = &[sym::proc_macro_derive]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = PROC_MACRO_ALLOWED_TARGETS; const TEMPLATE: AttributeTemplate = template!( List: &["TraitName", "TraitName, attributes(name1, name2, ...)"], @@ -45,7 +42,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcBuiltinMacroParser { const PATH: &[Symbol] = &[sym::rustc_builtin_macro]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::MacroDef)]); const TEMPLATE: AttributeTemplate = template!(List: &["TraitName", "TraitName, attributes(name1, name2, ...)"]); diff --git a/compiler/rustc_attr_parsing/src/attributes/prototype.rs b/compiler/rustc_attr_parsing/src/attributes/prototype.rs index 37d690983446..b6110f627a8c 100644 --- a/compiler/rustc_attr_parsing/src/attributes/prototype.rs +++ b/compiler/rustc_attr_parsing/src/attributes/prototype.rs @@ -5,7 +5,6 @@ use rustc_hir::attrs::{AttributeKind, MirDialect, MirPhase}; use rustc_span::{Span, Symbol, sym}; -use super::OnDuplicate; use crate::attributes::SingleAttributeParser; use crate::context::{AcceptContext, Stage}; use crate::parser::ArgParser; @@ -18,8 +17,6 @@ impl SingleAttributeParser for CustomMirParser { const PATH: &[rustc_span::Symbol] = &[sym::custom_mir]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const TEMPLATE: AttributeTemplate = template!(List: &[r#"dialect = "...", phase = "...""#]); @@ -82,7 +79,7 @@ fn extract_value( } let Some(val) = arg.name_value() else { - cx.adcx().expected_single_argument(arg.span().unwrap_or(span)); + cx.adcx().expected_name_value(span, Some(key)); *failed = true; return; }; diff --git a/compiler/rustc_attr_parsing/src/attributes/repr.rs b/compiler/rustc_attr_parsing/src/attributes/repr.rs index ebb9d90eb152..71a41384d213 100644 --- a/compiler/rustc_attr_parsing/src/attributes/repr.rs +++ b/compiler/rustc_attr_parsing/src/attributes/repr.rs @@ -297,7 +297,7 @@ fn parse(&mut self, cx: &mut AcceptContext<'_, '_, S>, args: &ArgParse } ArgParser::List(list) => { let Some(align) = list.single() else { - cx.adcx().expected_single_argument(list.span); + cx.adcx().expected_single_argument(list.span, list.len()); return; }; diff --git a/compiler/rustc_attr_parsing/src/attributes/rustc_allocator.rs b/compiler/rustc_attr_parsing/src/attributes/rustc_allocator.rs index cf4f8eab3246..9590a23ae934 100644 --- a/compiler/rustc_attr_parsing/src/attributes/rustc_allocator.rs +++ b/compiler/rustc_attr_parsing/src/attributes/rustc_allocator.rs @@ -4,7 +4,6 @@ impl NoArgsAttributeParser for RustcAllocatorParser { const PATH: &[Symbol] = &[sym::rustc_allocator]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn), Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcAllocator; @@ -14,7 +13,6 @@ impl NoArgsAttributeParser for RustcAllocatorParser { impl NoArgsAttributeParser for RustcAllocatorZeroedParser { const PATH: &[Symbol] = &[sym::rustc_allocator_zeroed]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn), Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcAllocatorZeroed; @@ -24,7 +22,6 @@ impl NoArgsAttributeParser for RustcAllocatorZeroedParser { impl SingleAttributeParser for RustcAllocatorZeroedVariantParser { const PATH: &[Symbol] = &[sym::rustc_allocator_zeroed_variant]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn), Allow(Target::ForeignFn)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "function"); @@ -43,7 +40,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcDeallocatorParser { const PATH: &[Symbol] = &[sym::rustc_deallocator]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn), Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDeallocator; @@ -53,7 +49,6 @@ impl NoArgsAttributeParser for RustcDeallocatorParser { impl NoArgsAttributeParser for RustcReallocatorParser { const PATH: &[Symbol] = &[sym::rustc_reallocator]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn), Allow(Target::ForeignFn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcReallocator; diff --git a/compiler/rustc_attr_parsing/src/attributes/rustc_dump.rs b/compiler/rustc_attr_parsing/src/attributes/rustc_dump.rs index 7c771a71bf63..e6f97683c612 100644 --- a/compiler/rustc_attr_parsing/src/attributes/rustc_dump.rs +++ b/compiler/rustc_attr_parsing/src/attributes/rustc_dump.rs @@ -1,9 +1,8 @@ -use rustc_hir::attrs::AttributeKind; +use rustc_hir::attrs::{AttributeKind, RustcDumpLayoutKind}; use rustc_hir::{MethodKind, Target}; use rustc_span::{Span, Symbol, sym}; -use crate::attributes::prelude::Allow; -use crate::attributes::{NoArgsAttributeParser, OnDuplicate}; +use super::prelude::*; use crate::context::Stage; use crate::target_checking::AllowedTargets; @@ -11,7 +10,6 @@ impl NoArgsAttributeParser for RustcDumpUserArgsParser { const PATH: &[Symbol] = &[sym::rustc_dump_user_args]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpUserArgs; } @@ -20,16 +18,45 @@ impl NoArgsAttributeParser for RustcDumpUserArgsParser { impl NoArgsAttributeParser for RustcDumpDefParentsParser { const PATH: &[Symbol] = &[sym::rustc_dump_def_parents]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpDefParents; } +pub(crate) struct RustcDumpDefPathParser; + +impl SingleAttributeParser for RustcDumpDefPathParser { + const PATH: &[Symbol] = &[sym::rustc_dump_def_path]; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ + Allow(Target::Fn), + Allow(Target::Method(MethodKind::TraitImpl)), + Allow(Target::Method(MethodKind::Inherent)), + Allow(Target::Method(MethodKind::Trait { body: true })), + Allow(Target::ForeignFn), + Allow(Target::ForeignStatic), + Allow(Target::Impl { of_trait: false }), + ]); + const TEMPLATE: AttributeTemplate = template!(Word); + fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { + if let Err(span) = args.no_args() { + cx.adcx().expected_no_args(span); + return None; + } + Some(AttributeKind::RustcDumpDefPath(cx.attr_span)) + } +} + +pub(crate) struct RustcDumpHiddenTypeOfOpaquesParser; + +impl NoArgsAttributeParser for RustcDumpHiddenTypeOfOpaquesParser { + const PATH: &[Symbol] = &[sym::rustc_dump_hidden_type_of_opaques]; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); + const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpHiddenTypeOfOpaques; +} + pub(crate) struct RustcDumpInferredOutlivesParser; impl NoArgsAttributeParser for RustcDumpInferredOutlivesParser { const PATH: &[Symbol] = &[sym::rustc_dump_inferred_outlives]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Struct), Allow(Target::Enum), @@ -43,16 +70,78 @@ impl NoArgsAttributeParser for RustcDumpInferredOutlivesParser { impl NoArgsAttributeParser for RustcDumpItemBoundsParser { const PATH: &[Symbol] = &[sym::rustc_dump_item_bounds]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::AssocTy)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpItemBounds; } +pub(crate) struct RustcDumpLayoutParser; + +impl CombineAttributeParser for RustcDumpLayoutParser { + const PATH: &[Symbol] = &[sym::rustc_dump_layout]; + + type Item = RustcDumpLayoutKind; + + const CONVERT: ConvertFn = |items, _| AttributeKind::RustcDumpLayout(items); + + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ + Allow(Target::Struct), + Allow(Target::Enum), + Allow(Target::Union), + Allow(Target::TyAlias), + ]); + + const TEMPLATE: AttributeTemplate = + template!(List: &["abi", "align", "size", "homogenous_aggregate", "debug"]); + fn extend( + cx: &mut AcceptContext<'_, '_, S>, + args: &ArgParser, + ) -> impl IntoIterator { + let ArgParser::List(items) = args else { + let attr_span = cx.attr_span; + cx.adcx().expected_list(attr_span, args); + return vec![]; + }; + + let mut result = Vec::new(); + for item in items.mixed() { + let Some(arg) = item.meta_item() else { + cx.adcx().expected_not_literal(item.span()); + continue; + }; + let Some(ident) = arg.ident() else { + cx.adcx().expected_identifier(arg.span()); + return vec![]; + }; + let kind = match ident.name { + sym::align => RustcDumpLayoutKind::Align, + sym::backend_repr => RustcDumpLayoutKind::BackendRepr, + sym::debug => RustcDumpLayoutKind::Debug, + sym::homogeneous_aggregate => RustcDumpLayoutKind::HomogenousAggregate, + sym::size => RustcDumpLayoutKind::Size, + _ => { + cx.adcx().expected_specific_argument( + ident.span, + &[ + sym::align, + sym::backend_repr, + sym::debug, + sym::homogeneous_aggregate, + sym::size, + ], + ); + continue; + } + }; + result.push(kind); + } + result + } +} + pub(crate) struct RustcDumpObjectLifetimeDefaultsParser; impl NoArgsAttributeParser for RustcDumpObjectLifetimeDefaultsParser { const PATH: &[Symbol] = &[sym::rustc_dump_object_lifetime_defaults]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::AssocConst), Allow(Target::AssocTy), @@ -79,7 +168,6 @@ impl NoArgsAttributeParser for RustcDumpObjectLifetimeDefaultsParse impl NoArgsAttributeParser for RustcDumpPredicatesParser { const PATH: &[Symbol] = &[sym::rustc_dump_predicates]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::AssocConst), Allow(Target::AssocTy), @@ -103,11 +191,33 @@ impl NoArgsAttributeParser for RustcDumpPredicatesParser { const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpPredicates; } +pub(crate) struct RustcDumpSymbolNameParser; + +impl SingleAttributeParser for RustcDumpSymbolNameParser { + const PATH: &[Symbol] = &[sym::rustc_dump_symbol_name]; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ + Allow(Target::Fn), + Allow(Target::Method(MethodKind::TraitImpl)), + Allow(Target::Method(MethodKind::Inherent)), + Allow(Target::Method(MethodKind::Trait { body: true })), + Allow(Target::ForeignFn), + Allow(Target::ForeignStatic), + Allow(Target::Impl { of_trait: false }), + ]); + const TEMPLATE: AttributeTemplate = template!(Word); + fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { + if let Err(span) = args.no_args() { + cx.adcx().expected_no_args(span); + return None; + } + Some(AttributeKind::RustcDumpSymbolName(cx.attr_span)) + } +} + pub(crate) struct RustcDumpVariancesParser; impl NoArgsAttributeParser for RustcDumpVariancesParser { const PATH: &[Symbol] = &[sym::rustc_dump_variances]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Enum), Allow(Target::Fn), @@ -125,7 +235,6 @@ impl NoArgsAttributeParser for RustcDumpVariancesParser { impl NoArgsAttributeParser for RustcDumpVariancesOfOpaquesParser { const PATH: &[Symbol] = &[sym::rustc_dump_variances_of_opaques]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDumpVariancesOfOpaques; } @@ -134,7 +243,6 @@ impl NoArgsAttributeParser for RustcDumpVariancesOfOpaquesParser { impl NoArgsAttributeParser for RustcDumpVtableParser { const PATH: &[Symbol] = &[sym::rustc_dump_vtable]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Impl { of_trait: true }), Allow(Target::TyAlias), diff --git a/compiler/rustc_attr_parsing/src/attributes/rustc_internal.rs b/compiler/rustc_attr_parsing/src/attributes/rustc_internal.rs index d77c804af697..3f4049366f40 100644 --- a/compiler/rustc_attr_parsing/src/attributes/rustc_internal.rs +++ b/compiler/rustc_attr_parsing/src/attributes/rustc_internal.rs @@ -4,14 +4,13 @@ use rustc_hir::LangItem; use rustc_hir::attrs::{ BorrowckGraphvizFormatKind, CguFields, CguKind, DivergingBlockBehavior, - DivergingFallbackBehavior, RustcCleanAttribute, RustcCleanQueries, RustcLayoutType, - RustcMirKind, + DivergingFallbackBehavior, RustcCleanAttribute, RustcCleanQueries, RustcMirKind, }; -use rustc_session::errors; use rustc_span::Symbol; use super::prelude::*; use super::util::parse_single_integer; +use crate::errors; use crate::session_diagnostics::{ AttributeRequiresOpt, CguFieldsMissing, RustcScalableVectorCountOutOfRange, UnknownLangItem, }; @@ -20,7 +19,6 @@ impl NoArgsAttributeParser for RustcMainParser { const PATH: &[Symbol] = &[sym::rustc_main]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcMain; } @@ -29,7 +27,6 @@ impl NoArgsAttributeParser for RustcMainParser { impl SingleAttributeParser for RustcMustImplementOneOfParser { const PATH: &[Symbol] = &[sym::rustc_must_implement_one_of]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const TEMPLATE: AttributeTemplate = template!(List: &["function1, function2, ..."]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { @@ -75,7 +72,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcNeverReturnsNullPtrParser { const PATH: &[Symbol] = &[sym::rustc_never_returns_null_ptr]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -89,7 +85,6 @@ impl NoArgsAttributeParser for RustcNeverReturnsNullPtrParser { impl NoArgsAttributeParser for RustcNoImplicitAutorefsParser { const PATH: &[Symbol] = &[sym::rustc_no_implicit_autorefs]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -105,7 +100,6 @@ impl NoArgsAttributeParser for RustcNoImplicitAutorefsParser { impl SingleAttributeParser for RustcLayoutScalarValidRangeStartParser { const PATH: &[Symbol] = &[sym::rustc_layout_scalar_valid_range_start]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const TEMPLATE: AttributeTemplate = template!(List: &["start"]); @@ -119,7 +113,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcLayoutScalarValidRangeEndParser { const PATH: &[Symbol] = &[sym::rustc_layout_scalar_valid_range_end]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const TEMPLATE: AttributeTemplate = template!(List: &["end"]); @@ -133,7 +126,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcLegacyConstGenericsParser { const PATH: &[Symbol] = &[sym::rustc_legacy_const_generics]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const TEMPLATE: AttributeTemplate = template!(List: &["N"]); @@ -177,7 +169,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcInheritOverflowChecksParser { const PATH: &[Symbol] = &[sym::rustc_inherit_overflow_checks]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -191,15 +182,10 @@ impl NoArgsAttributeParser for RustcInheritOverflowChecksParser { impl SingleAttributeParser for RustcLintOptDenyFieldAccessParser { const PATH: &[Symbol] = &[sym::rustc_lint_opt_deny_field_access]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Field)]); const TEMPLATE: AttributeTemplate = template!(Word); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(arg) = args.list().and_then(MetaItemListParser::single) else { - let attr_span = cx.attr_span; - cx.adcx().expected_single_argument(attr_span); - return None; - }; + let arg = cx.single_element_list(args, cx.attr_span)?; let MetaItemOrLitParser::Lit(MetaItemLit { kind: LitKind::Str(lint_message, _), .. }) = arg else { @@ -215,7 +201,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcLintOptTyParser { const PATH: &[Symbol] = &[sym::rustc_lint_opt_ty]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcLintOptTy; } @@ -364,7 +349,6 @@ fn finalize(self, _cx: &FinalizeContext<'_, '_, S>) -> Option { impl SingleAttributeParser for RustcDeprecatedSafe2024Parser { const PATH: &[Symbol] = &[sym::rustc_deprecated_safe_2024]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -375,19 +359,10 @@ impl SingleAttributeParser for RustcDeprecatedSafe2024Parser { const TEMPLATE: AttributeTemplate = template!(List: &[r#"audit_that = "...""#]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(args) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - - let Some(single) = args.single() else { - cx.adcx().expected_single_argument(args.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let Some(arg) = single.meta_item() else { - cx.adcx().expected_name_value(args.span, None); + cx.adcx().expected_name_value(single.span(), None); return None; }; @@ -414,7 +389,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcConversionSuggestionParser { const PATH: &[Symbol] = &[sym::rustc_conversion_suggestion]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -429,7 +403,6 @@ impl NoArgsAttributeParser for RustcConversionSuggestionParser { impl NoArgsAttributeParser for RustcCaptureAnalysisParser { const PATH: &[Symbol] = &[sym::rustc_capture_analysis]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Closure)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcCaptureAnalysis; } @@ -438,7 +411,6 @@ impl NoArgsAttributeParser for RustcCaptureAnalysisParser { impl SingleAttributeParser for RustcNeverTypeOptionsParser { const PATH: &[Symbol] = &[sym::rustc_never_type_options]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const TEMPLATE: AttributeTemplate = template!(List: &[ r#"fallback = "unit", "never", "no""#, @@ -521,7 +493,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcTrivialFieldReadsParser { const PATH: &[Symbol] = &[sym::rustc_trivial_field_reads]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcTrivialFieldReads; } @@ -530,7 +501,6 @@ impl NoArgsAttributeParser for RustcTrivialFieldReadsParser { impl NoArgsAttributeParser for RustcNoMirInlineParser { const PATH: &[Symbol] = &[sym::rustc_no_mir_inline]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -541,11 +511,25 @@ impl NoArgsAttributeParser for RustcNoMirInlineParser { const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcNoMirInline; } +pub(crate) struct RustcNoWritableParser; + +impl NoArgsAttributeParser for RustcNoWritableParser { + const PATH: &[Symbol] = &[sym::rustc_no_writable]; + const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ + Allow(Target::Fn), + Allow(Target::Closure), + Allow(Target::Method(MethodKind::Inherent)), + Allow(Target::Method(MethodKind::TraitImpl)), + Allow(Target::Method(MethodKind::Trait { body: true })), + ]); + const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcNoWritable; +} + pub(crate) struct RustcLintQueryInstabilityParser; impl NoArgsAttributeParser for RustcLintQueryInstabilityParser { const PATH: &[Symbol] = &[sym::rustc_lint_query_instability]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -560,7 +544,6 @@ impl NoArgsAttributeParser for RustcLintQueryInstabilityParser { impl NoArgsAttributeParser for RustcRegionsParser { const PATH: &[Symbol] = &[sym::rustc_regions]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -576,7 +559,6 @@ impl NoArgsAttributeParser for RustcRegionsParser { impl NoArgsAttributeParser for RustcLintUntrackedQueryInformationParser { const PATH: &[Symbol] = &[sym::rustc_lint_untracked_query_information]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -592,7 +574,6 @@ impl NoArgsAttributeParser for RustcLintUntrackedQueryInformationPa impl SingleAttributeParser for RustcSimdMonomorphizeLaneLimitParser { const PATH: &[Symbol] = &[sym::rustc_simd_monomorphize_lane_limit]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "N"); @@ -610,7 +591,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcScalableVectorParser { const PATH: &[Symbol] = &[sym::rustc_scalable_vector]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const TEMPLATE: AttributeTemplate = template!(Word, List: &["count"]); @@ -635,7 +615,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for LangParser { const PATH: &[Symbol] = &[sym::lang]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); // Targets are checked per lang item in `rustc_passes` const TEMPLATE: AttributeTemplate = template!(NameValueStr: "name"); @@ -661,7 +640,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcHasIncoherentInherentImplsParser { const PATH: &[Symbol] = &[sym::rustc_has_incoherent_inherent_impls]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Trait), Allow(Target::Struct), @@ -676,24 +654,14 @@ impl NoArgsAttributeParser for RustcHasIncoherentInherentImplsParse impl NoArgsAttributeParser for PanicHandlerParser { const PATH: &[Symbol] = &[sym::panic_handler]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); // Targets are checked per lang item in `rustc_passes` const CREATE: fn(Span) -> AttributeKind = |span| AttributeKind::Lang(LangItem::PanicImpl, span); } -pub(crate) struct RustcHiddenTypeOfOpaquesParser; - -impl NoArgsAttributeParser for RustcHiddenTypeOfOpaquesParser { - const PATH: &[Symbol] = &[sym::rustc_hidden_type_of_opaques]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); - const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcHiddenTypeOfOpaques; -} pub(crate) struct RustcNounwindParser; impl NoArgsAttributeParser for RustcNounwindParser { const PATH: &[Symbol] = &[sym::rustc_nounwind]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::ForeignFn), @@ -708,69 +676,10 @@ impl NoArgsAttributeParser for RustcNounwindParser { impl NoArgsAttributeParser for RustcOffloadKernelParser { const PATH: &[Symbol] = &[sym::rustc_offload_kernel]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcOffloadKernel; } -pub(crate) struct RustcLayoutParser; - -impl CombineAttributeParser for RustcLayoutParser { - const PATH: &[Symbol] = &[sym::rustc_layout]; - - type Item = RustcLayoutType; - - const CONVERT: ConvertFn = |items, _| AttributeKind::RustcLayout(items); - - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ - Allow(Target::Struct), - Allow(Target::Enum), - Allow(Target::Union), - Allow(Target::TyAlias), - ]); - - const TEMPLATE: AttributeTemplate = - template!(List: &["abi", "align", "size", "homogenous_aggregate", "debug"]); - fn extend( - cx: &mut AcceptContext<'_, '_, S>, - args: &ArgParser, - ) -> impl IntoIterator { - let ArgParser::List(items) = args else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return vec![]; - }; - - let mut result = Vec::new(); - for item in items.mixed() { - let Some(arg) = item.meta_item() else { - cx.adcx().expected_not_literal(item.span()); - continue; - }; - let Some(ident) = arg.ident() else { - cx.adcx().expected_identifier(arg.span()); - return vec![]; - }; - let ty = match ident.name { - sym::abi => RustcLayoutType::Abi, - sym::align => RustcLayoutType::Align, - sym::size => RustcLayoutType::Size, - sym::homogeneous_aggregate => RustcLayoutType::HomogenousAggregate, - sym::debug => RustcLayoutType::Debug, - _ => { - cx.adcx().expected_specific_argument( - ident.span, - &[sym::abi, sym::align, sym::size, sym::homogeneous_aggregate, sym::debug], - ); - continue; - } - }; - result.push(ty); - } - result - } -} - pub(crate) struct RustcMirParser; impl CombineAttributeParser for RustcMirParser { @@ -865,7 +774,6 @@ fn extend( impl NoArgsAttributeParser for RustcNonConstTraitMethodParser { const PATH: &[Symbol] = &[sym::rustc_non_const_trait_method]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Method(MethodKind::Trait { body: true })), Allow(Target::Method(MethodKind::Trait { body: false })), @@ -984,8 +892,6 @@ fn extend( impl SingleAttributeParser for RustcIfThisChangedParser { const PATH: &[Symbol] = &[sym::rustc_if_this_changed]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ // tidy-alphabetical-start Allow(Target::AssocConst), @@ -1022,7 +928,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { let Some(item) = list.single() else { let attr_span = cx.attr_span; - cx.adcx().expected_single_argument(attr_span); + cx.adcx().expected_single_argument(attr_span, list.len()); return None; }; let Some(ident) = item.meta_item().and_then(|item| item.ident()) else { @@ -1082,11 +988,7 @@ fn extend( if !cx.cx.sess.opts.unstable_opts.query_dep_graph { cx.emit_err(AttributeRequiresOpt { span: cx.attr_span, opt: "-Z query-dep-graph" }); } - let Some(item) = args.list().and_then(|l| l.single()) else { - let inner_span = cx.inner_span; - cx.adcx().expected_single_argument(inner_span); - return None; - }; + let item = cx.single_element_list(args, cx.attr_span)?; let Some(ident) = item.meta_item().and_then(|item| item.ident()) else { cx.adcx().expected_identifier(item.span()); return None; @@ -1099,7 +1001,6 @@ fn extend( impl NoArgsAttributeParser for RustcInsignificantDtorParser { const PATH: &[Symbol] = &[sym::rustc_insignificant_dtor]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Enum), Allow(Target::Struct), @@ -1112,7 +1013,6 @@ impl NoArgsAttributeParser for RustcInsignificantDtorParser { impl NoArgsAttributeParser for RustcEffectiveVisibilityParser { const PATH: &[Symbol] = &[sym::rustc_effective_visibility]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Use), Allow(Target::Static), @@ -1151,7 +1051,6 @@ impl NoArgsAttributeParser for RustcEffectiveVisibilityParser { impl SingleAttributeParser for RustcDiagnosticItemParser { const PATH: &[Symbol] = &[sym::rustc_diagnostic_item]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Trait), Allow(Target::Struct), @@ -1190,7 +1089,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcDoNotConstCheckParser { const PATH: &[Symbol] = &[sym::rustc_do_not_const_check]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -1205,64 +1103,14 @@ impl NoArgsAttributeParser for RustcDoNotConstCheckParser { impl NoArgsAttributeParser for RustcNonnullOptimizationGuaranteedParser { const PATH: &[Symbol] = &[sym::rustc_nonnull_optimization_guaranteed]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcNonnullOptimizationGuaranteed; } -pub(crate) struct RustcSymbolNameParser; - -impl SingleAttributeParser for RustcSymbolNameParser { - const PATH: &[Symbol] = &[sym::rustc_symbol_name]; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ - Allow(Target::Fn), - Allow(Target::Method(MethodKind::TraitImpl)), - Allow(Target::Method(MethodKind::Inherent)), - Allow(Target::Method(MethodKind::Trait { body: true })), - Allow(Target::ForeignFn), - Allow(Target::ForeignStatic), - Allow(Target::Impl { of_trait: false }), - ]); - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const TEMPLATE: AttributeTemplate = template!(Word); - fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - if let Err(span) = args.no_args() { - cx.adcx().expected_no_args(span); - return None; - } - Some(AttributeKind::RustcSymbolName(cx.attr_span)) - } -} - -pub(crate) struct RustcDefPathParser; - -impl SingleAttributeParser for RustcDefPathParser { - const PATH: &[Symbol] = &[sym::rustc_def_path]; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ - Allow(Target::Fn), - Allow(Target::Method(MethodKind::TraitImpl)), - Allow(Target::Method(MethodKind::Inherent)), - Allow(Target::Method(MethodKind::Trait { body: true })), - Allow(Target::ForeignFn), - Allow(Target::ForeignStatic), - Allow(Target::Impl { of_trait: false }), - ]); - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const TEMPLATE: AttributeTemplate = template!(Word); - fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - if let Err(span) = args.no_args() { - cx.adcx().expected_no_args(span); - return None; - } - Some(AttributeKind::RustcDefPath(cx.attr_span)) - } -} - pub(crate) struct RustcStrictCoherenceParser; impl NoArgsAttributeParser for RustcStrictCoherenceParser { const PATH: &[Symbol] = &[sym::rustc_strict_coherence]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Trait), Allow(Target::Struct), @@ -1277,7 +1125,6 @@ impl NoArgsAttributeParser for RustcStrictCoherenceParser { impl SingleAttributeParser for RustcReservationImplParser { const PATH: &[Symbol] = &[sym::rustc_reservation_impl]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Impl { of_trait: true })]); @@ -1303,7 +1150,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for PreludeImportParser { const PATH: &[Symbol] = &[sym::prelude_import]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Use)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::PreludeImport; } @@ -1312,7 +1158,6 @@ impl NoArgsAttributeParser for PreludeImportParser { impl SingleAttributeParser for RustcDocPrimitiveParser { const PATH: &[Symbol] = &[sym::rustc_doc_primitive]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Mod)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "primitive name"); @@ -1336,7 +1181,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcIntrinsicParser { const PATH: &[Symbol] = &[sym::rustc_intrinsic]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcIntrinsic; } @@ -1345,7 +1189,14 @@ impl NoArgsAttributeParser for RustcIntrinsicParser { impl NoArgsAttributeParser for RustcIntrinsicConstStableIndirectParser { const PATH: &'static [Symbol] = &[sym::rustc_intrinsic_const_stable_indirect]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcIntrinsicConstStableIndirect; } + +pub(crate) struct RustcExhaustiveParser; + +impl NoArgsAttributeParser for RustcExhaustiveParser { + const PATH: &'static [Symbol] = &[sym::rustc_must_match_exhaustively]; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Enum)]); + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcMustMatchExhaustively; +} diff --git a/compiler/rustc_attr_parsing/src/attributes/semantics.rs b/compiler/rustc_attr_parsing/src/attributes/semantics.rs index d7f624832971..28091d711a3d 100644 --- a/compiler/rustc_attr_parsing/src/attributes/semantics.rs +++ b/compiler/rustc_attr_parsing/src/attributes/semantics.rs @@ -3,7 +3,6 @@ pub(crate) struct MayDangleParser; impl NoArgsAttributeParser for MayDangleParser { const PATH: &[Symbol] = &[sym::may_dangle]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); //FIXME Still checked fully in `check_attr.rs` const CREATE: fn(span: Span) -> AttributeKind = AttributeKind::MayDangle; } diff --git a/compiler/rustc_attr_parsing/src/attributes/stability.rs b/compiler/rustc_attr_parsing/src/attributes/stability.rs index 866b53e4c0d9..0559469bc369 100644 --- a/compiler/rustc_attr_parsing/src/attributes/stability.rs +++ b/compiler/rustc_attr_parsing/src/attributes/stability.rs @@ -2,6 +2,7 @@ use rustc_errors::ErrorGuaranteed; use rustc_feature::ACCEPTED_LANG_FEATURES; +use rustc_hir::attrs::UnstableRemovedFeature; use rustc_hir::target::GenericParamKind; use rustc_hir::{ DefaultBodyStability, MethodKind, PartialConstStability, Stability, StabilityLevel, @@ -476,3 +477,89 @@ pub(crate) fn parse_unstability( (Err(ErrorGuaranteed { .. }), _) | (_, Err(ErrorGuaranteed { .. })) => None, } } + +pub(crate) struct UnstableRemovedParser; + +impl CombineAttributeParser for UnstableRemovedParser { + type Item = UnstableRemovedFeature; + const PATH: &[Symbol] = &[sym::unstable_removed]; + const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); + const TEMPLATE: AttributeTemplate = + template!(List: &[r#"feature = "name", reason = "...", link = "...", since = "version""#]); + + const CONVERT: ConvertFn = |items, _| AttributeKind::UnstableRemoved(items); + + fn extend( + cx: &mut AcceptContext<'_, '_, S>, + args: &ArgParser, + ) -> impl IntoIterator { + let mut feature = None; + let mut reason = None; + let mut link = None; + let mut since = None; + + if !cx.features().staged_api() { + cx.emit_err(session_diagnostics::StabilityOutsideStd { span: cx.attr_span }); + return None; + } + + let ArgParser::List(list) = args else { + let attr_span = cx.attr_span; + cx.adcx().expected_list(attr_span, args); + return None; + }; + + for param in list.mixed() { + let Some(param) = param.meta_item() else { + cx.adcx().expected_not_literal(param.span()); + return None; + }; + + let Some(word) = param.path().word() else { + cx.adcx().expected_specific_argument( + param.span(), + &[sym::feature, sym::reason, sym::link, sym::since], + ); + return None; + }; + match word.name { + sym::feature => insert_value_into_option_or_error(cx, ¶m, &mut feature, word)?, + sym::since => insert_value_into_option_or_error(cx, ¶m, &mut since, word)?, + sym::reason => insert_value_into_option_or_error(cx, ¶m, &mut reason, word)?, + sym::link => insert_value_into_option_or_error(cx, ¶m, &mut link, word)?, + _ => { + cx.adcx().expected_specific_argument( + param.span(), + &[sym::feature, sym::reason, sym::link, sym::since], + ); + return None; + } + } + } + + // Check all the arguments are present + let Some(feature) = feature else { + cx.adcx().missing_name_value(list.span, sym::feature); + return None; + }; + let Some(reason) = reason else { + cx.adcx().missing_name_value(list.span, sym::reason); + return None; + }; + let Some(link) = link else { + cx.adcx().missing_name_value(list.span, sym::link); + return None; + }; + let Some(since) = since else { + cx.adcx().missing_name_value(list.span, sym::since); + return None; + }; + + let Some(version) = parse_version(since) else { + cx.emit_err(session_diagnostics::InvalidSince { span: cx.attr_span }); + return None; + }; + + Some(UnstableRemovedFeature { feature, reason, link, since: version }) + } +} diff --git a/compiler/rustc_attr_parsing/src/attributes/test_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/test_attrs.rs index 0f7baa941702..06087c8a4baa 100644 --- a/compiler/rustc_attr_parsing/src/attributes/test_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/test_attrs.rs @@ -72,7 +72,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { let Some(single) = list.single() else { - cx.adcx().expected_single_argument(list.span); + cx.adcx().expected_single_argument(list.span, list.len()); return None; }; let Some(single) = single.meta_item() else { @@ -102,7 +102,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for ReexportTestHarnessMainParser { const PATH: &[Symbol] = &[sym::reexport_test_harness_main]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const TEMPLATE: AttributeTemplate = template!(NameValueStr: "name"); @@ -129,7 +128,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcAbiParser { const PATH: &[Symbol] = &[sym::rustc_abi]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const TEMPLATE: AttributeTemplate = template!(OneOf: &[sym::debug, sym::assert_eq]); const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::TyAlias), @@ -150,7 +148,7 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option, args: &ArgParser) -> Option NoArgsAttributeParser for RustcDelayedBugFromInsideQueryParser { const PATH: &[Symbol] = &[sym::rustc_delayed_bug_from_inside_query]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Fn)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcDelayedBugFromInsideQuery; } @@ -188,7 +185,6 @@ impl NoArgsAttributeParser for RustcDelayedBugFromInsideQueryParser impl NoArgsAttributeParser for RustcEvaluateWhereClausesParser { const PATH: &[Symbol] = &[sym::rustc_evaluate_where_clauses]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), @@ -203,21 +199,11 @@ impl NoArgsAttributeParser for RustcEvaluateWhereClausesParser { impl SingleAttributeParser for TestRunnerParser { const PATH: &[Symbol] = &[sym::test_runner]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Crate)]); const TEMPLATE: AttributeTemplate = template!(List: &["path"]); fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option { - let Some(list) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - - let Some(single) = list.single() else { - cx.adcx().expected_single_argument(list.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let Some(meta) = single.meta_item() else { cx.adcx().expected_not_literal(single.span()); @@ -232,7 +218,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option SingleAttributeParser for RustcTestMarkerParser { const PATH: &[Symbol] = &[sym::rustc_test_marker]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Const), Allow(Target::Fn), diff --git a/compiler/rustc_attr_parsing/src/attributes/traits.rs b/compiler/rustc_attr_parsing/src/attributes/traits.rs index 54a95ffd0ea3..b2a9addfeab3 100644 --- a/compiler/rustc_attr_parsing/src/attributes/traits.rs +++ b/compiler/rustc_attr_parsing/src/attributes/traits.rs @@ -1,16 +1,15 @@ use std::mem; use super::prelude::*; -use crate::attributes::{NoArgsAttributeParser, OnDuplicate, SingleAttributeParser}; +use crate::attributes::{NoArgsAttributeParser, SingleAttributeParser}; use crate::context::{AcceptContext, Stage}; use crate::parser::ArgParser; +use crate::target_checking::AllowedTargets; use crate::target_checking::Policy::{Allow, Warn}; -use crate::target_checking::{ALL_TARGETS, AllowedTargets}; pub(crate) struct RustcSkipDuringMethodDispatchParser; impl SingleAttributeParser for RustcSkipDuringMethodDispatchParser { const PATH: &[Symbol] = &[sym::rustc_skip_during_method_dispatch]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const TEMPLATE: AttributeTemplate = template!(List: &["array, boxed_slice"]); @@ -60,7 +59,6 @@ fn convert(cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser) -> Option NoArgsAttributeParser for RustcParenSugarParser { const PATH: &[Symbol] = &[sym::rustc_paren_sugar]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcParenSugar; } @@ -70,7 +68,6 @@ impl NoArgsAttributeParser for RustcParenSugarParser { pub(crate) struct MarkerParser; impl NoArgsAttributeParser for MarkerParser { const PATH: &[Symbol] = &[sym::marker]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Warn; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Trait), Warn(Target::Field), @@ -83,7 +80,6 @@ impl NoArgsAttributeParser for MarkerParser { pub(crate) struct RustcDenyExplicitImplParser; impl NoArgsAttributeParser for RustcDenyExplicitImplParser { const PATH: &[Symbol] = &[sym::rustc_deny_explicit_impl]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcDenyExplicitImpl; } @@ -91,7 +87,6 @@ impl NoArgsAttributeParser for RustcDenyExplicitImplParser { pub(crate) struct RustcDynIncompatibleTraitParser; impl NoArgsAttributeParser for RustcDynIncompatibleTraitParser { const PATH: &[Symbol] = &[sym::rustc_dyn_incompatible_trait]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcDynIncompatibleTrait; } @@ -101,7 +96,6 @@ impl NoArgsAttributeParser for RustcDynIncompatibleTraitParser { pub(crate) struct RustcSpecializationTraitParser; impl NoArgsAttributeParser for RustcSpecializationTraitParser { const PATH: &[Symbol] = &[sym::rustc_specialization_trait]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcSpecializationTrait; } @@ -109,7 +103,6 @@ impl NoArgsAttributeParser for RustcSpecializationTraitParser { pub(crate) struct RustcUnsafeSpecializationMarkerParser; impl NoArgsAttributeParser for RustcUnsafeSpecializationMarkerParser { const PATH: &[Symbol] = &[sym::rustc_unsafe_specialization_marker]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcUnsafeSpecializationMarker; } @@ -119,7 +112,6 @@ impl NoArgsAttributeParser for RustcUnsafeSpecializationMarkerParse pub(crate) struct RustcCoinductiveParser; impl NoArgsAttributeParser for RustcCoinductiveParser { const PATH: &[Symbol] = &[sym::rustc_coinductive]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcCoinductive; } @@ -127,7 +119,6 @@ impl NoArgsAttributeParser for RustcCoinductiveParser { pub(crate) struct RustcAllowIncoherentImplParser; impl NoArgsAttributeParser for RustcAllowIncoherentImplParser { const PATH: &[Symbol] = &[sym::rustc_allow_incoherent_impl]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Method(MethodKind::Inherent))]); const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcAllowIncoherentImpl; @@ -136,16 +127,7 @@ impl NoArgsAttributeParser for RustcAllowIncoherentImplParser { pub(crate) struct FundamentalParser; impl NoArgsAttributeParser for FundamentalParser { const PATH: &[Symbol] = &[sym::fundamental]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Struct), Allow(Target::Trait)]); const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::Fundamental; } - -pub(crate) struct PointeeParser; -impl NoArgsAttributeParser for PointeeParser { - const PATH: &[Symbol] = &[sym::pointee]; - const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; - const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(ALL_TARGETS); //FIXME Still checked fully in `check_attr.rs` - const CREATE: fn(Span) -> AttributeKind = AttributeKind::Pointee; -} diff --git a/compiler/rustc_attr_parsing/src/attributes/util.rs b/compiler/rustc_attr_parsing/src/attributes/util.rs index 4bd9b2b963e9..98f8cc23b500 100644 --- a/compiler/rustc_attr_parsing/src/attributes/util.rs +++ b/compiler/rustc_attr_parsing/src/attributes/util.rs @@ -41,15 +41,7 @@ pub(crate) fn parse_single_integer( cx: &mut AcceptContext<'_, '_, S>, args: &ArgParser, ) -> Option { - let Some(list) = args.list() else { - let attr_span = cx.attr_span; - cx.adcx().expected_list(attr_span, args); - return None; - }; - let Some(single) = list.single() else { - cx.adcx().expected_single_argument(list.span); - return None; - }; + let single = cx.single_element_list(args, cx.attr_span)?; let Some(lit) = single.lit() else { cx.adcx().expected_integer_literal(single.span()); return None; diff --git a/compiler/rustc_attr_parsing/src/context.rs b/compiler/rustc_attr_parsing/src/context.rs index 0be1b9b45b22..aa9284e54d36 100644 --- a/compiler/rustc_attr_parsing/src/context.rs +++ b/compiler/rustc_attr_parsing/src/context.rs @@ -7,7 +7,8 @@ use private::Sealed; use rustc_ast::{AttrStyle, MetaItemLit, NodeId}; -use rustc_errors::{Diag, Diagnostic, Level}; +use rustc_data_structures::sync::{DynSend, DynSync}; +use rustc_errors::{Diag, DiagCtxtHandle, Diagnostic, Level, MultiSpan}; use rustc_feature::{AttrSuggestionStyle, AttributeTemplate}; use rustc_hir::attrs::AttributeKind; use rustc_hir::lints::AttributeLintKind; @@ -15,9 +16,8 @@ use rustc_parse::parser::Recovery; use rustc_session::Session; use rustc_session::lint::{Lint, LintId}; -use rustc_span::{AttrId, ErrorGuaranteed, Span, Symbol}; +use rustc_span::{ErrorGuaranteed, Span, Symbol}; -use crate::AttributeParser; // Glob imports to avoid big, bitrotty import lists use crate::attributes::allow_unstable::*; use crate::attributes::autodiff::*; @@ -32,12 +32,12 @@ use crate::attributes::diagnostic::on_const::*; use crate::attributes::diagnostic::on_move::*; use crate::attributes::diagnostic::on_unimplemented::*; +use crate::attributes::diagnostic::on_unknown::*; use crate::attributes::doc::*; use crate::attributes::dummy::*; use crate::attributes::inline::*; use crate::attributes::instruction_set::*; use crate::attributes::link_attrs::*; -use crate::attributes::lint::*; use crate::attributes::lint_helpers::*; use crate::attributes::loop_match::*; use crate::attributes::macro_attrs::*; @@ -59,13 +59,14 @@ use crate::attributes::test_attrs::*; use crate::attributes::traits::*; use crate::attributes::transparency::*; -use crate::attributes::{AttributeParser as _, Combine, Single, WithoutArgs}; -use crate::parser::{ArgParser, RefPathParser}; +use crate::attributes::{AttributeParser as _, AttributeSafety, Combine, Single, WithoutArgs}; +use crate::parser::{ArgParser, MetaItemOrLitParser, RefPathParser}; use crate::session_diagnostics::{ AttributeParseError, AttributeParseErrorReason, AttributeParseErrorSuggestions, ParsedDescription, }; use crate::target_checking::AllowedTargets; +use crate::{AttributeParser, EmitAttribute}; type GroupType = LazyLock>; pub(super) struct GroupTypeInner { @@ -76,6 +77,7 @@ pub(super) struct GroupTypeInnerAccept { pub(super) template: AttributeTemplate, pub(super) accept_fn: AcceptFn, pub(super) allowed_targets: AllowedTargets, + pub(super) safety: AttributeSafety, pub(super) finalizer: FinalizeFn, } @@ -126,6 +128,7 @@ mod late { accept_fn(s, cx, args) }) }), + safety: <$names as crate::attributes::AttributeParser<$stage>>::SAFETY, allowed_targets: <$names as crate::attributes::AttributeParser<$stage>>::ALLOWED_TARGETS, finalizer: Box::new(|cx| { let state = STATE_OBJECT.take(); @@ -150,12 +153,12 @@ mod late { ConfusablesParser, ConstStabilityParser, DocParser, - LintParser, MacroUseParser, NakedParser, OnConstParser, OnMoveParser, OnUnimplementedParser, + OnUnknownParser, RustcAlignParser, RustcAlignStaticParser, RustcCguTestAttributeParser, @@ -174,11 +177,12 @@ mod late { Combine, Combine, Combine, - Combine, + Combine, Combine, Combine, Combine, Combine, + Combine, // tidy-alphabetical-end // tidy-alphabetical-start @@ -213,11 +217,12 @@ mod late { Single, Single, Single, - Single, Single, Single, Single, Single, + Single, + Single, Single, Single, Single, @@ -233,7 +238,6 @@ mod late { Single, Single, Single, - Single, Single, Single, Single, @@ -268,7 +272,6 @@ mod late { Single>, Single>, Single>, - Single>, Single>, Single>, Single>, @@ -287,6 +290,7 @@ mod late { Single>, Single>, Single>, + Single>, Single>, Single>, Single>, @@ -299,8 +303,8 @@ mod late { Single>, Single>, Single>, + Single>, Single>, - Single>, Single>, Single>, Single>, @@ -313,6 +317,7 @@ mod late { Single>, Single>, Single>, + Single>, Single>, Single>, Single>, @@ -447,8 +452,6 @@ pub struct AcceptContext<'f, 'sess, S: Stage> { /// The name of the attribute we're currently accepting. pub(crate) attr_path: AttrPath, - - pub(crate) attr_id: AttrId, } impl<'f, 'sess: 'f, S: Stage> SharedContext<'f, 'sess, S> { @@ -459,23 +462,54 @@ pub(crate) fn emit_err(&self, diag: impl for<'x> Diagnostic<'x>) -> ErrorGuarant /// Emit a lint. This method is somewhat special, since lints emitted during attribute parsing /// must be delayed until after HIR is built. This method will take care of the details of /// that. - pub(crate) fn emit_lint(&mut self, lint: &'static Lint, kind: AttributeLintKind, span: Span) { + pub(crate) fn emit_lint( + &mut self, + lint: &'static Lint, + kind: AttributeLintKind, + span: impl Into, + ) { + self.emit_lint_inner(lint, EmitAttribute::Static(kind), span); + } + + /// Emit a lint. This method is somewhat special, since lints emitted during attribute parsing + /// must be delayed until after HIR is built. This method will take care of the details of + /// that. + pub(crate) fn emit_dyn_lint< + F: for<'a> Fn(DiagCtxtHandle<'a>, Level) -> Diag<'a, ()> + DynSend + DynSync + 'static, + >( + &mut self, + lint: &'static Lint, + callback: F, + span: impl Into, + ) { + self.emit_lint_inner(lint, EmitAttribute::Dynamic(Box::new(callback)), span); + } + + fn emit_lint_inner( + &mut self, + lint: &'static Lint, + kind: EmitAttribute, + span: impl Into, + ) { if !matches!( self.stage.should_emit(), ShouldEmit::ErrorsAndLints { .. } | ShouldEmit::EarlyFatal { also_emit_lints: true } ) { return; } - (self.emit_lint)(LintId::of(lint), span, kind); + (self.emit_lint)(LintId::of(lint), span.into(), kind); } pub(crate) fn warn_unused_duplicate(&mut self, used_span: Span, unused_span: Span) { - self.emit_lint( + self.emit_dyn_lint( rustc_session::lint::builtin::UNUSED_ATTRIBUTES, - AttributeLintKind::UnusedDuplicate { - this: unused_span, - other: used_span, - warning: false, + move |dcx, level| { + rustc_errors::lints::UnusedDuplicate { + this: unused_span, + other: used_span, + warning: false, + } + .into_diag(dcx, level) }, unused_span, ) @@ -486,12 +520,15 @@ pub(crate) fn warn_unused_duplicate_future_error( used_span: Span, unused_span: Span, ) { - self.emit_lint( + self.emit_dyn_lint( rustc_session::lint::builtin::UNUSED_ATTRIBUTES, - AttributeLintKind::UnusedDuplicate { - this: unused_span, - other: used_span, - warning: true, + move |dcx, level| { + rustc_errors::lints::UnusedDuplicate { + this: unused_span, + other: used_span, + warning: true, + } + .into_diag(dcx, level) }, unused_span, ) @@ -502,6 +539,36 @@ impl<'f, 'sess: 'f, S: Stage> AcceptContext<'f, 'sess, S> { pub(crate) fn adcx(&mut self) -> AttributeDiagnosticContext<'_, 'f, 'sess, S> { AttributeDiagnosticContext { ctx: self, custom_suggestions: Vec::new() } } + + /// Asserts that this MetaItem is a list that contains a single element. Emits an error and + /// returns `None` if it is not the case. + /// + /// Some examples: + /// + /// - In `#[allow(warnings)]`, `warnings` is returned + /// - In `#[cfg_attr(docsrs, doc = "foo")]`, `None` is returned, "expected a single argument + /// here" is emitted. + /// - In `#[cfg()]`, `None` is returned, "expected an argument here" is emitted. + /// + /// The provided span is used as a fallback for diagnostic generation in case `arg` does not + /// contain any. It should be the span of the node that contains `arg`. + pub(crate) fn single_element_list<'arg>( + &mut self, + arg: &'arg ArgParser, + span: Span, + ) -> Option<&'arg MetaItemOrLitParser> { + let ArgParser::List(l) = arg else { + self.adcx().expected_list(span, arg); + return None; + }; + + let Some(single) = l.single() else { + self.adcx().expected_single_argument(l.span, l.len()); + return None; + }; + + Some(single) + } } impl<'f, 'sess, S: Stage> Deref for AcceptContext<'f, 'sess, S> { @@ -532,7 +599,7 @@ pub struct SharedContext<'p, 'sess, S: Stage> { /// The second argument of the closure is a [`NodeId`] if `S` is `Early` and a [`HirId`] if `S` /// is `Late` and is the ID of the syntactical component this attribute was applied to. - pub(crate) emit_lint: &'p mut dyn FnMut(LintId, Span, AttributeLintKind), + pub(crate) emit_lint: &'p mut dyn FnMut(LintId, MultiSpan, EmitAttribute), } /// Context given to every attribute parser during finalization. @@ -689,6 +756,8 @@ pub(crate) fn expected_integer_literal_in_range( ) } + /// The provided span is used as a fallback in case `args` does not contain any. It should be + /// the span of the node that contains `args`. pub(crate) fn expected_list(&mut self, span: Span, args: &ArgParser) -> ErrorGuaranteed { let span = match args { ArgParser::NoArgs => span, @@ -740,19 +809,38 @@ pub(crate) fn expected_name_value( self.emit_parse_error(span, AttributeParseErrorReason::ExpectedNameValue(name)) } + /// Emit an error that a `name = value` argument is missing in a list of name-value pairs. + pub(crate) fn missing_name_value(&mut self, span: Span, name: Symbol) -> ErrorGuaranteed { + self.emit_parse_error(span, AttributeParseErrorReason::MissingNameValue(name)) + } + /// Emit an error that a `name = value` pair was found where that name was already seen. pub(crate) fn duplicate_key(&mut self, span: Span, key: Symbol) -> ErrorGuaranteed { self.emit_parse_error(span, AttributeParseErrorReason::DuplicateKey(key)) } - /// An error that should be emitted when a [`MetaItemOrLitParser`](crate::parser::MetaItemOrLitParser) + /// An error that should be emitted when a [`MetaItemOrLitParser`] /// was expected *not* to be a literal, but instead a meta item. pub(crate) fn expected_not_literal(&mut self, span: Span) -> ErrorGuaranteed { self.emit_parse_error(span, AttributeParseErrorReason::ExpectedNotLiteral) } - pub(crate) fn expected_single_argument(&mut self, span: Span) -> ErrorGuaranteed { - self.emit_parse_error(span, AttributeParseErrorReason::ExpectedSingleArgument) + /// Signals that we expected exactly one argument and that we got either zero or two or more. + /// The `provided_arguments` argument allows distinguishing between "expected an argument here" + /// (when zero arguments are provided) and "expect a single argument here" (when two or more + /// arguments are provided). + pub(crate) fn expected_single_argument( + &mut self, + span: Span, + provided_arguments: usize, + ) -> ErrorGuaranteed { + let reason = if provided_arguments == 0 { + AttributeParseErrorReason::ExpectedArgument + } else { + AttributeParseErrorReason::ExpectedSingleArgument + }; + + self.emit_parse_error(span, reason) } pub(crate) fn expected_at_least_one_argument(&mut self, span: Span) -> ErrorGuaranteed { @@ -808,17 +896,6 @@ pub(crate) fn expected_specific_argument_strings( ) } - pub(crate) fn expected_nv_as_last_argument( - &mut self, - span: Span, - name_value_key: Symbol, - ) -> ErrorGuaranteed { - self.emit_parse_error( - span, - AttributeParseErrorReason::ExpectedNameValueAsLastArgument { span, name_value_key }, - ) - } - pub(crate) fn warn_empty_attribute(&mut self, span: Span) { let attr_path = self.attr_path.clone().to_string(); let valid_without_list = self.template.word; diff --git a/compiler/rustc_attr_parsing/src/errors.rs b/compiler/rustc_attr_parsing/src/errors.rs index d4236416dd6a..7049ffae89ab 100644 --- a/compiler/rustc_attr_parsing/src/errors.rs +++ b/compiler/rustc_attr_parsing/src/errors.rs @@ -50,3 +50,19 @@ pub(crate) struct UnreachableCfgSelectPredicateWildcard { #[label("always matches")] pub wildcard_span: Span, } + +#[derive(Diagnostic)] +#[diag("must be a name of an associated function")] +pub(crate) struct MustBeNameOfAssociatedFunction { + #[primary_span] + pub span: Span, +} + +#[derive(Diagnostic)] +#[diag("unsafe attribute used without unsafe")] +pub(crate) struct UnsafeAttrOutsideUnsafeLint { + #[label("usage of unsafe attribute")] + pub span: Span, + #[subdiagnostic] + pub suggestion: Option, +} diff --git a/compiler/rustc_attr_parsing/src/interface.rs b/compiler/rustc_attr_parsing/src/interface.rs index 902f2419c46d..0dfa67951e62 100644 --- a/compiler/rustc_attr_parsing/src/interface.rs +++ b/compiler/rustc_attr_parsing/src/interface.rs @@ -2,27 +2,37 @@ use rustc_ast as ast; use rustc_ast::token::DocFragmentKind; -use rustc_ast::{AttrItemKind, AttrStyle, NodeId, Safety}; -use rustc_data_structures::fx::FxIndexSet; -use rustc_errors::DiagCtxtHandle; +use rustc_ast::{AttrItemKind, AttrStyle, CRATE_NODE_ID, NodeId, Safety}; +use rustc_data_structures::sync::{DynSend, DynSync}; +use rustc_errors::{Diag, DiagCtxtHandle, Level, MultiSpan}; use rustc_feature::{AttributeTemplate, Features}; use rustc_hir::attrs::AttributeKind; use rustc_hir::lints::AttributeLintKind; use rustc_hir::{AttrArgs, AttrItem, AttrPath, Attribute, HashIgnoredAttrId, Target}; use rustc_session::Session; use rustc_session::lint::LintId; -use rustc_span::{DUMMY_SP, Ident, Span, Symbol, sym}; +use rustc_span::{DUMMY_SP, Span, Symbol, sym}; +use crate::attributes::AttributeSafety; use crate::context::{AcceptContext, FinalizeContext, FinalizeFn, SharedContext, Stage}; use crate::early_parsed::{EARLY_PARSED_ATTRIBUTES, EarlyParsedState}; use crate::parser::{AllowExprMetavar, ArgParser, PathParser, RefPathParser}; use crate::session_diagnostics::ParsedDescription; use crate::{Early, Late, OmitDoc, ShouldEmit}; +pub enum EmitAttribute { + Static(AttributeLintKind), + Dynamic( + Box< + dyn for<'a> Fn(DiagCtxtHandle<'a>, Level) -> Diag<'a, ()> + DynSend + DynSync + 'static, + >, + ), +} + /// Context created once, for example as part of the ast lowering /// context, through which all attributes can be lowered. pub struct AttributeParser<'sess, S: Stage = Late> { - pub(crate) tools: Option<&'sess FxIndexSet>, + pub(crate) tools: Vec, pub(crate) features: Option<&'sess Features>, pub(crate) sess: &'sess Session, pub(crate) stage: S, @@ -30,7 +40,7 @@ pub struct AttributeParser<'sess, S: Stage = Late> { /// *Only* parse attributes with this symbol. /// /// Used in cases where we want the lowering infrastructure for parse just a single attribute. - parse_only: Option, + parse_only: Option<&'static [Symbol]>, } impl<'sess> AttributeParser<'sess, Early> { @@ -48,36 +58,30 @@ impl<'sess> AttributeParser<'sess, Early> { /// No diagnostics will be emitted when parsing limited. Lints are not emitted at all, while /// errors will be emitted as a delayed bugs. in other words, we *expect* attributes parsed /// with `parse_limited` to be reparsed later during ast lowering where we *do* emit the errors - /// - /// Due to this function not taking in RegisteredTools (`FxIndexSet`), *do not* use this for parsing any lint attributes pub fn parse_limited( sess: &'sess Session, attrs: &[ast::Attribute], - sym: Symbol, - target_span: Span, - target_node_id: NodeId, - features: Option<&'sess Features>, + sym: &'static [Symbol], ) -> Option { Self::parse_limited_should_emit( sess, attrs, sym, - target_span, - target_node_id, - Target::Crate, // Does not matter, we're not going to emit errors anyways - features, + // Because we're not emitting warnings/errors, the target should not matter + DUMMY_SP, + CRATE_NODE_ID, + Target::Crate, + None, ShouldEmit::Nothing, ) } /// This does the same as `parse_limited`, except it has a `should_emit` parameter which allows it to emit errors. /// Usually you want `parse_limited`, which emits no errors. - /// - /// Due to this function not taking in RegisteredTools (`FxIndexSet`), *do not* use this for parsing any lint attributes pub fn parse_limited_should_emit( sess: &'sess Session, attrs: &[ast::Attribute], - sym: Symbol, + sym: &'static [Symbol], target_span: Span, target_node_id: NodeId, target: Target, @@ -93,7 +97,6 @@ pub fn parse_limited_should_emit( target_node_id, features, should_emit, - None, ); assert!(parsed.len() <= 1); parsed.pop() @@ -106,51 +109,32 @@ pub fn parse_limited_should_emit( /// `rustc_ast_lowering`. Some attributes require access to features to parse, which would /// crash if you tried to do so through [`parse_limited_all`](Self::parse_limited_all). /// Therefore, if `parse_only` is None, then features *must* be provided. - pub fn parse_limited_all<'a>( + pub fn parse_limited_all( sess: &'sess Session, - attrs: impl IntoIterator, - parse_only: Option, + attrs: &[ast::Attribute], + parse_only: Option<&'static [Symbol]>, target: Target, target_span: Span, target_node_id: NodeId, features: Option<&'sess Features>, emit_errors: ShouldEmit, - tools: Option<&'sess FxIndexSet>, ) -> Vec { - let mut p = Self { features, tools, parse_only, sess, stage: Early { emit_errors } }; + let mut p = + Self { features, tools: Vec::new(), parse_only, sess, stage: Early { emit_errors } }; p.parse_attribute_list( attrs, target_span, target, OmitDoc::Skip, std::convert::identity, - |lint_id, span, kind| sess.psess.buffer_lint(lint_id.lint, span, target_node_id, kind), - ) - } - - /// This method provides the same functionality as [`parse_limited_all`](Self::parse_limited_all) except filtered, - /// making sure that only allow-listed symbols are parsed - pub fn parse_limited_all_filtered<'a>( - sess: &'sess Session, - attrs: impl IntoIterator, - filter: &[Symbol], - target: Target, - target_span: Span, - target_node_id: NodeId, - features: Option<&'sess Features>, - emit_errors: ShouldEmit, - tools: &'sess FxIndexSet, - ) -> Vec { - Self::parse_limited_all( - sess, - attrs.into_iter().filter(|attr| attr.has_any_name(filter)), - None, - target, - target_span, - target_node_id, - features, - emit_errors, - Some(tools), + |lint_id, span, kind| match kind { + EmitAttribute::Static(kind) => { + sess.psess.buffer_lint(lint_id.lint, span, target_node_id, kind) + } + EmitAttribute::Dynamic(callback) => { + sess.psess.dyn_buffer_lint(lint_id.lint, span, target_node_id, callback) + } + }, ) } @@ -167,6 +151,7 @@ pub fn parse_single( parse_fn: fn(cx: &mut AcceptContext<'_, '_, Early>, item: &ArgParser) -> Option, template: &AttributeTemplate, allow_expr_metavar: AllowExprMetavar, + expected_safety: AttributeSafety, ) -> Option { let ast::AttrKind::Normal(normal_attr) = &attr.kind else { panic!("parse_single called on a doc attr") @@ -189,6 +174,7 @@ pub fn parse_single( attr.style, path, Some(normal_attr.item.unsafety), + expected_safety, ParsedDescription::Attribute, target_span, target_node_id, @@ -210,6 +196,7 @@ pub fn parse_single_args( attr_style: AttrStyle, attr_path: AttrPath, attr_safety: Option, + expected_safety: AttributeSafety, parsed_description: ParsedDescription, target_span: Span, target_node_id: NodeId, @@ -220,15 +207,30 @@ pub fn parse_single_args( parse_fn: fn(cx: &mut AcceptContext<'_, '_, Early>, item: &I) -> T, template: &AttributeTemplate, ) -> T { - let mut parser = - Self { features, tools: None, parse_only: None, sess, stage: Early { emit_errors } }; - let mut emit_lint = |lint_id: LintId, span: Span, kind: AttributeLintKind| { - sess.psess.buffer_lint(lint_id.lint, span, target_node_id, kind) + let mut parser = Self { + features, + tools: Vec::new(), + parse_only: None, + sess, + stage: Early { emit_errors }, + }; + let mut emit_lint = |lint_id: LintId, span: MultiSpan, kind: EmitAttribute| match kind { + EmitAttribute::Static(kind) => { + sess.psess.buffer_lint(lint_id.lint, span, target_node_id, kind) + } + EmitAttribute::Dynamic(callback) => { + sess.psess.dyn_buffer_lint(lint_id.lint, span, target_node_id, callback) + } }; if let Some(safety) = attr_safety { - parser.check_attribute_safety(&attr_path, inner_span, safety, &mut emit_lint) + parser.check_attribute_safety( + &attr_path, + inner_span, + safety, + expected_safety, + &mut emit_lint, + ); } - let attr_id = sess.psess.attr_id_generator.mk_attr_id(); let mut cx: AcceptContext<'_, 'sess, Early> = AcceptContext { shared: SharedContext { cx: &mut parser, @@ -242,7 +244,6 @@ pub fn parse_single_args( parsed_description, template, attr_path, - attr_id, }; parse_fn(&mut cx, args) } @@ -252,10 +253,10 @@ impl<'sess, S: Stage> AttributeParser<'sess, S> { pub fn new( sess: &'sess Session, features: &'sess Features, - tools: &'sess FxIndexSet, + tools: Vec, stage: S, ) -> Self { - Self { features: Some(features), tools: Some(tools), parse_only: None, sess, stage } + Self { features: Some(features), tools, parse_only: None, sess, stage } } pub(crate) fn sess(&self) -> &'sess Session { @@ -278,14 +279,14 @@ pub(crate) fn dcx(&self) -> DiagCtxtHandle<'sess> { /// /// `target_span` is the span of the thing this list of attributes is applied to, /// and when `omit_doc` is set, doc attributes are filtered out. - pub fn parse_attribute_list<'a>( + pub fn parse_attribute_list( &mut self, - attrs: impl IntoIterator, + attrs: &[ast::Attribute], target_span: Span, target: Target, omit_doc: OmitDoc, lower_span: impl Copy + Fn(Span) -> Span, - mut emit_lint: impl FnMut(LintId, Span, AttributeLintKind), + mut emit_lint: impl FnMut(LintId, MultiSpan, EmitAttribute), ) -> Vec { let mut attributes = Vec::new(); // We store the attributes we intend to discard at the end of this function in order to @@ -296,12 +297,12 @@ pub fn parse_attribute_list<'a>( let mut attr_paths: Vec> = Vec::new(); let mut early_parsed_state = EarlyParsedState::default(); - let mut finalizers: Vec<&FinalizeFn> = Vec::new(); + let mut finalizers: Vec<&FinalizeFn> = Vec::with_capacity(attrs.len()); - for attr in attrs.into_iter() { + for attr in attrs { // If we're only looking for a single attribute, skip all the ones we don't care about. if let Some(expected) = self.parse_only { - if !attr.has_name(expected) { + if !attr.path_matches(expected) { continue; } } @@ -343,17 +344,18 @@ pub fn parse_attribute_list<'a>( } }; - self.check_attribute_safety( - &attr_path, - lower_span(n.item.span()), - n.item.unsafety, - &mut emit_lint, - ); - let parts = n.item.path.segments.iter().map(|seg| seg.ident.name).collect::>(); if let Some(accept) = S::parsers().accepters.get(parts.as_slice()) { + self.check_attribute_safety( + &attr_path, + lower_span(n.item.span()), + n.item.unsafety, + accept.safety, + &mut emit_lint, + ); + let Some(args) = ArgParser::from_attr_args( args, &parts, @@ -408,7 +410,6 @@ pub fn parse_attribute_list<'a>( parsed_description: ParsedDescription::Attribute, template: &accept.template, attr_path: attr_path.clone(), - attr_id: attr.id, }; (accept.accept_fn)(&mut cx, &args); @@ -427,6 +428,14 @@ pub fn parse_attribute_list<'a>( span: attr_span, }; + self.check_attribute_safety( + &attr_path, + lower_span(n.item.span()), + n.item.unsafety, + AttributeSafety::Normal, + &mut emit_lint, + ); + if !matches!(self.stage.should_emit(), ShouldEmit::Nothing) && target == Target::Crate { @@ -435,9 +444,11 @@ pub fn parse_attribute_list<'a>( let attr = Attribute::Unparsed(Box::new(attr)); - if self - .tools - .is_some_and(|tools| tools.iter().any(|tool| tool.name == parts[0])) + if self.tools.contains(&parts[0]) + // FIXME: this can be removed once #152369 has been merged. + // https://github.com/rust-lang/rust/pull/152369 + || [sym::allow, sym::deny, sym::expect, sym::forbid, sym::warn] + .contains(&parts[0]) { attributes.push(attr); } else { diff --git a/compiler/rustc_attr_parsing/src/lib.rs b/compiler/rustc_attr_parsing/src/lib.rs index 93eb5a0c3ab7..73618dbfbf30 100644 --- a/compiler/rustc_attr_parsing/src/lib.rs +++ b/compiler/rustc_attr_parsing/src/lib.rs @@ -106,11 +106,12 @@ mod target_checking; pub mod validate_attr; +pub use attributes::AttributeSafety; pub use attributes::cfg::{ CFG_TEMPLATE, EvalConfigResult, eval_config_entry, parse_cfg, parse_cfg_attr, parse_cfg_entry, }; pub use attributes::cfg_select::*; pub use attributes::util::{is_builtin_attr, parse_version}; pub use context::{Early, Late, OmitDoc, ShouldEmit}; -pub use interface::AttributeParser; +pub use interface::{AttributeParser, EmitAttribute}; pub use session_diagnostics::ParsedDescription; diff --git a/compiler/rustc_attr_parsing/src/safety.rs b/compiler/rustc_attr_parsing/src/safety.rs index 4cc703c5d0cc..6566aaa55705 100644 --- a/compiler/rustc_attr_parsing/src/safety.rs +++ b/compiler/rustc_attr_parsing/src/safety.rs @@ -1,13 +1,13 @@ use rustc_ast::Safety; -use rustc_feature::{AttributeSafety, BUILTIN_ATTRIBUTE_MAP}; +use rustc_errors::{Diagnostic, MultiSpan}; use rustc_hir::AttrPath; -use rustc_hir::lints::AttributeLintKind; use rustc_session::lint::LintId; use rustc_session::lint::builtin::UNSAFE_ATTR_OUTSIDE_UNSAFE; use rustc_span::Span; +use crate::attributes::AttributeSafety; use crate::context::Stage; -use crate::{AttributeParser, ShouldEmit}; +use crate::{AttributeParser, EmitAttribute, ShouldEmit, errors}; impl<'sess, S: Stage> AttributeParser<'sess, S> { pub fn check_attribute_safety( @@ -15,28 +15,23 @@ pub fn check_attribute_safety( attr_path: &AttrPath, attr_span: Span, attr_safety: Safety, - emit_lint: &mut impl FnMut(LintId, Span, AttributeLintKind), + expected_safety: AttributeSafety, + emit_lint: &mut impl FnMut(LintId, MultiSpan, EmitAttribute), ) { if matches!(self.stage.should_emit(), ShouldEmit::Nothing) { return; } - let name = (attr_path.segments.len() == 1).then_some(attr_path.segments[0]); - - // FIXME: We should retrieve this information from the attribute parsers instead of from `BUILTIN_ATTRIBUTE_MAP` - let builtin_attr_info = name.and_then(|name| BUILTIN_ATTRIBUTE_MAP.get(&name)); - let builtin_attr_safety = builtin_attr_info.map(|x| x.safety); - - match (builtin_attr_safety, attr_safety) { + match (expected_safety, attr_safety) { // - Unsafe builtin attribute // - User wrote `#[unsafe(..)]`, which is permitted on any edition - (Some(AttributeSafety::Unsafe { .. }), Safety::Unsafe(..)) => { + (AttributeSafety::Unsafe { .. }, Safety::Unsafe(..)) => { // OK } // - Unsafe builtin attribute // - User did not write `#[unsafe(..)]` - (Some(AttributeSafety::Unsafe { unsafe_since }), Safety::Default) => { + (AttributeSafety::Unsafe { unsafe_since }, Safety::Default) => { let path_span = attr_path.span; // If the `attr_item`'s span is not from a macro, then just suggest @@ -83,19 +78,25 @@ pub fn check_attribute_safety( } else { emit_lint( LintId::of(UNSAFE_ATTR_OUTSIDE_UNSAFE), - path_span, - AttributeLintKind::UnsafeAttrOutsideUnsafe { - attribute_name_span: path_span, - sugg_spans: not_from_proc_macro - .then(|| (diag_span.shrink_to_lo(), diag_span.shrink_to_hi())), - }, + path_span.into(), + EmitAttribute::Dynamic(Box::new(move |dcx, level| { + errors::UnsafeAttrOutsideUnsafeLint { + span: path_span, + suggestion: not_from_proc_macro + .then(|| (diag_span.shrink_to_lo(), diag_span.shrink_to_hi())) + .map(|(left, right)| { + crate::session_diagnostics::UnsafeAttrOutsideUnsafeSuggestion { left, right } + }), + } + .into_diag(dcx, level) + })), ) } } // - Normal builtin attribute // - Writing `#[unsafe(..)]` is not permitted on normal builtin attributes - (None | Some(AttributeSafety::Normal), Safety::Unsafe(unsafe_span)) => { + (AttributeSafety::Normal, Safety::Unsafe(unsafe_span)) => { self.stage.emit_err( self.sess, crate::session_diagnostics::InvalidAttrUnsafe { @@ -107,14 +108,11 @@ pub fn check_attribute_safety( // - Normal builtin attribute // - No explicit `#[unsafe(..)]` written. - (None | Some(AttributeSafety::Normal), Safety::Default) => { + (AttributeSafety::Normal, Safety::Default) => { // OK } - ( - Some(AttributeSafety::Unsafe { .. } | AttributeSafety::Normal) | None, - Safety::Safe(..), - ) => { + (_, Safety::Safe(..)) => { self.sess.dcx().span_delayed_bug( attr_span, "`check_attribute_safety` does not expect `Safety::Safe` on attributes", diff --git a/compiler/rustc_attr_parsing/src/session_diagnostics.rs b/compiler/rustc_attr_parsing/src/session_diagnostics.rs index 5b198813dc43..203c7f8ebff1 100644 --- a/compiler/rustc_attr_parsing/src/session_diagnostics.rs +++ b/compiler/rustc_attr_parsing/src/session_diagnostics.rs @@ -557,6 +557,7 @@ pub(crate) enum AttributeParseErrorReason<'a> { upper_bound: isize, }, ExpectedAtLeastOneArgument, + ExpectedArgument, ExpectedSingleArgument, ExpectedList, ExpectedListOrNoArgs, @@ -567,6 +568,7 @@ pub(crate) enum AttributeParseErrorReason<'a> { ExpectedNonEmptyStringLiteral, ExpectedNotLiteral, ExpectedNameValue(Option), + MissingNameValue(Symbol), DuplicateKey(Symbol), ExpectedSpecificArgument { possibilities: &'a [Symbol], @@ -575,10 +577,6 @@ pub(crate) enum AttributeParseErrorReason<'a> { list: bool, }, ExpectedIdentifier, - ExpectedNameValueAsLastArgument { - span: Span, - name_value_key: Symbol, - }, } /// A description of a thing that can be parsed using an attribute parser. @@ -777,6 +775,10 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, G> { diag.span_label(self.span, "expected a single argument here"); diag.code(E0805); } + AttributeParseErrorReason::ExpectedArgument => { + diag.span_label(self.span, "expected an argument here"); + diag.code(E0805); + } AttributeParseErrorReason::ExpectedAtLeastOneArgument => { diag.span_label(self.span, "expected at least 1 argument here"); } @@ -822,6 +824,9 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, G> { format!("expected this to be of the form `{name} = \"...\"`"), ); } + AttributeParseErrorReason::MissingNameValue(name) => { + diag.span_label(self.span, format!("missing argument `{name} = \"...\"`")); + } AttributeParseErrorReason::ExpectedSpecificArgument { possibilities, strings, @@ -839,12 +844,6 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, G> { AttributeParseErrorReason::ExpectedIdentifier => { diag.span_label(self.span, "expected a valid identifier here"); } - AttributeParseErrorReason::ExpectedNameValueAsLastArgument { span, name_value_key } => { - diag.span_label( - *span, - format!("expected {name_value_key} = \"...\" to be the last argument"), - ); - } } if let Some(link) = self.template.docs { @@ -1138,14 +1137,3 @@ pub(crate) struct UnstableAttrForAlreadyStableFeature { #[label("the stability attribute annotates this item")] pub item_span: Span, } - -#[derive(Diagnostic)] -#[diag("unknown tool name `{$tool_name}` found in scoped lint: `{$full_lint_name}`", code = E0710)] -pub(crate) struct UnknownToolInScopedLint { - #[primary_span] - pub span: Option, - pub tool_name: Symbol, - pub full_lint_name: Symbol, - #[help("add `#![register_tool({$tool_name})]` to the crate root")] - pub is_nightly_build: bool, -} diff --git a/compiler/rustc_attr_parsing/src/validate_attr.rs b/compiler/rustc_attr_parsing/src/validate_attr.rs index f5ff312f3ade..06ff674f2538 100644 --- a/compiler/rustc_attr_parsing/src/validate_attr.rs +++ b/compiler/rustc_attr_parsing/src/validate_attr.rs @@ -1,6 +1,7 @@ //! Meta-syntax validation logic of attributes for post-expansion. use std::convert::identity; +use std::slice; use rustc_ast::token::Delimiter; use rustc_ast::tokenstream::DelimSpan; @@ -8,7 +9,7 @@ self as ast, AttrArgs, Attribute, DelimArgs, MetaItem, MetaItemInner, MetaItemKind, Safety, }; use rustc_errors::{Applicability, PResult}; -use rustc_feature::{AttributeTemplate, BUILTIN_ATTRIBUTE_MAP}; +use rustc_feature::{AttributeTemplate, BUILTIN_ATTRIBUTE_MAP, BuiltinAttribute, template}; use rustc_hir::AttrPath; use rustc_hir::lints::AttributeLintKind; use rustc_parse::parse_in; @@ -17,23 +18,50 @@ use rustc_session::parse::ParseSess; use rustc_span::{Span, Symbol, sym}; -use crate::session_diagnostics as errors; +use crate::{AttributeParser, Late, session_diagnostics as errors}; pub fn check_attr(psess: &ParseSess, attr: &Attribute) { - // Built-in attributes are parsed in their respective attribute parsers, so can be ignored here - if attr.is_doc_comment() - || attr.name().is_some_and(|name| BUILTIN_ATTRIBUTE_MAP.contains_key(&name)) + if attr.is_doc_comment() || attr.has_name(sym::cfg_trace) || attr.has_name(sym::cfg_attr_trace) { return; } - let attr_item = attr.get_normal_item(); - if let AttrArgs::Eq { .. } = attr_item.args.unparsed_ref().unwrap() { - // All key-value attributes are restricted to meta-item syntax. - match parse_meta(psess, attr) { - Ok(_) => {} - Err(err) => { - err.emit(); + let builtin_attr_info = attr.name().and_then(|name| BUILTIN_ATTRIBUTE_MAP.get(&name)); + + // Check input tokens for built-in and key-value attributes. + match builtin_attr_info { + Some(BuiltinAttribute { name, .. }) => { + if AttributeParser::::is_parsed_attribute(slice::from_ref(&name)) { + return; + } + match parse_meta(psess, attr) { + // Don't check safety again, we just did that + Ok(meta) => { + // FIXME The only unparsed builtin attributes that are left are the lint attributes, so we can hardcode the template here + let lint_attrs = [sym::forbid, sym::allow, sym::warn, sym::deny, sym::expect]; + assert!(lint_attrs.contains(name)); + + let template = template!( + List: &["lint1", "lint1, lint2, ...", r#"lint1, lint2, lint3, reason = "...""#], + "https://doc.rust-lang.org/reference/attributes/diagnostics.html#lint-check-attributes" + ); + check_builtin_meta_item(psess, &meta, attr.style, *name, template, false) + } + Err(err) => { + err.emit(); + } + } + } + _ => { + let attr_item = attr.get_normal_item(); + if let AttrArgs::Eq { .. } = attr_item.args.unparsed_ref().unwrap() { + // All key-value attributes are restricted to meta-item syntax. + match parse_meta(psess, attr) { + Ok(_) => {} + Err(err) => { + err.emit(); + } + } } } } diff --git a/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs b/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs index a927c30fae32..13c705137e0e 100644 --- a/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs @@ -451,7 +451,7 @@ fn try_extract_error_from_region_constraints<'a, 'tcx>( (RePlaceholder(a_p), RePlaceholder(b_p)) => a_p.bound == b_p.bound, _ => a_region == b_region, }; - let mut check = |c: &Constraint<'tcx>, cause: &SubregionOrigin<'tcx>, exact| match c.kind { + let mut check = |c: Constraint<'tcx>, cause: &SubregionOrigin<'tcx>, exact| match c.kind { ConstraintKind::RegSubReg if ((exact && c.sup == placeholder_region) || (!exact && regions_the_same(c.sup, placeholder_region))) @@ -467,13 +467,23 @@ fn try_extract_error_from_region_constraints<'a, 'tcx>( { Some((c.sub, cause.clone())) } - _ => None, + ConstraintKind::VarSubVar + | ConstraintKind::RegSubVar + | ConstraintKind::VarSubReg + | ConstraintKind::RegSubReg => None, + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!() + } }; let mut find_culprit = |exact_match: bool| { region_constraints .constraints .iter() + .flat_map(|(constraint, cause)| { + constraint.iter_outlives().map(move |constraint| (constraint, cause)) + }) .find_map(|(constraint, cause)| check(constraint, cause, exact_match)) }; diff --git a/compiler/rustc_borrowck/src/diagnostics/conflict_errors.rs b/compiler/rustc_borrowck/src/diagnostics/conflict_errors.rs index b8eefa4dd071..2bbaf3e5c817 100644 --- a/compiler/rustc_borrowck/src/diagnostics/conflict_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/conflict_errors.rs @@ -3538,6 +3538,24 @@ fn try_report_cannot_return_reference_to_local( Applicability::MaybeIncorrect, ); } + + if let Some(cow_did) = tcx.get_diagnostic_item(sym::Cow) + && let ty::Adt(adt_def, _) = return_ty.kind() + && adt_def.did() == cow_did + { + if let Ok(snippet) = tcx.sess.source_map().span_to_snippet(return_span) { + if let Some(pos) = snippet.rfind(".to_owned") { + let byte_pos = BytePos(pos as u32 + 1u32); + let to_owned_span = return_span.with_hi(return_span.lo() + byte_pos); + err.span_suggestion_short( + to_owned_span.shrink_to_hi(), + "try using `.into_owned()` if you meant to convert a `Cow<'_, T>` to an owned `T`", + "in", + Applicability::MaybeIncorrect, + ); + } + } + } } Err(err) @@ -4022,23 +4040,74 @@ pub(crate) fn report_illegal_reassignment( if let Some(decl) = local_decl && decl.can_be_made_mutable() { - let is_for_loop = matches!( - decl.local_info(), - LocalInfo::User(BindingForm::Var(VarBindingForm { - opt_match_place: Some((_, match_span)), - .. - })) if matches!(match_span.desugaring_kind(), Some(DesugaringKind::ForLoop)) - ); - let message = if is_for_loop + let mut is_for_loop = false; + let mut is_ref_pattern = false; + if let LocalInfo::User(BindingForm::Var(VarBindingForm { + opt_match_place: Some((_, match_span)), + .. + })) = *decl.local_info() + { + if matches!(match_span.desugaring_kind(), Some(DesugaringKind::ForLoop)) { + is_for_loop = true; + + if let Some(body) = self.infcx.tcx.hir_maybe_body_owned_by(self.mir_def_id()) { + struct RefPatternFinder<'tcx> { + tcx: TyCtxt<'tcx>, + binding_span: Span, + is_ref_pattern: bool, + } + + impl<'tcx> Visitor<'tcx> for RefPatternFinder<'tcx> { + type NestedFilter = OnlyBodies; + + fn maybe_tcx(&mut self) -> Self::MaybeTyCtxt { + self.tcx + } + + fn visit_pat(&mut self, pat: &'tcx hir::Pat<'tcx>) { + if !self.is_ref_pattern + && let hir::PatKind::Binding(_, _, ident, _) = pat.kind + && ident.span == self.binding_span + { + self.is_ref_pattern = + self.tcx.hir_parent_iter(pat.hir_id).any(|(_, node)| { + matches!( + node, + hir::Node::Pat(hir::Pat { + kind: hir::PatKind::Ref(..), + .. + }) + ) + }); + } + hir::intravisit::walk_pat(self, pat); + } + } + + let mut finder = RefPatternFinder { + tcx: self.infcx.tcx, + binding_span: decl.source_info.span, + is_ref_pattern: false, + }; + + finder.visit_body(body); + is_ref_pattern = finder.is_ref_pattern; + } + } + } + + let (span, message) = if is_for_loop + && is_ref_pattern && let Ok(binding_name) = self.infcx.tcx.sess.source_map().span_to_snippet(decl.source_info.span) { - format!("(mut {}) ", binding_name) + (decl.source_info.span, format!("(mut {})", binding_name)) } else { - "mut ".to_string() + (decl.source_info.span.shrink_to_lo(), "mut ".to_string()) }; + err.span_suggestion_verbose( - decl.source_info.span.shrink_to_lo(), + span, "consider making this binding mutable", message, Applicability::MachineApplicable, diff --git a/compiler/rustc_borrowck/src/diagnostics/move_errors.rs b/compiler/rustc_borrowck/src/diagnostics/move_errors.rs index 89e008f06ebc..49a181731162 100644 --- a/compiler/rustc_borrowck/src/diagnostics/move_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/move_errors.rs @@ -678,7 +678,7 @@ fn closure_clause_kind( fn add_move_hints(&self, error: GroupedMoveError<'tcx>, err: &mut Diag<'_>, span: Span) { match error { GroupedMoveError::MovesFromPlace { mut binds_to, move_from, .. } => { - self.add_borrow_suggestions(err, span); + self.add_borrow_suggestions(err, span, !binds_to.is_empty()); if binds_to.is_empty() { let place_ty = move_from.ty(self.body, self.infcx.tcx).ty; let place_desc = match self.describe_place(move_from.as_ref()) { @@ -787,29 +787,67 @@ fn add_move_hints(&self, error: GroupedMoveError<'tcx>, err: &mut Diag<'_>, span } } - fn add_borrow_suggestions(&self, err: &mut Diag<'_>, span: Span) { + fn add_borrow_suggestions( + &self, + err: &mut Diag<'_>, + span: Span, + is_destructuring_pattern_move: bool, + ) { match self.infcx.tcx.sess.source_map().span_to_snippet(span) { Ok(snippet) if snippet.starts_with('*') => { let sp = span.with_lo(span.lo() + BytePos(1)); let inner = self.find_expr(sp); let mut is_raw_ptr = false; + let mut is_ref = false; + let mut is_destructuring_assignment = false; + let mut is_nested_deref = false; if let Some(inner) = inner { + is_nested_deref = + matches!(inner.kind, hir::ExprKind::Unary(hir::UnOp::Deref, _)); let typck_result = self.infcx.tcx.typeck(self.mir_def_id()); if let Some(inner_type) = typck_result.node_type_opt(inner.hir_id) { if matches!(inner_type.kind(), ty::RawPtr(..)) { is_raw_ptr = true; + } else if matches!(inner_type.kind(), ty::Ref(..)) { + is_ref = true; } } + is_destructuring_assignment = + self.infcx.tcx.hir_parent_iter(inner.hir_id).any(|(_, node)| { + matches!( + node, + hir::Node::LetStmt(&hir::LetStmt { + source: hir::LocalSource::AssignDesugar, + .. + }) + ) + }); } // If the `inner` is a raw pointer, do not suggest removing the "*", see #126863 // FIXME: need to check whether the assigned object can be a raw pointer, see `tests/ui/borrowck/issue-20801.rs`. - if !is_raw_ptr { + if is_raw_ptr { + return; + } + + if !is_destructuring_pattern_move || is_ref { err.span_suggestion_verbose( span.with_hi(span.lo() + BytePos(1)), "consider removing the dereference here", String::new(), Applicability::MaybeIncorrect, ); + } else if !is_destructuring_assignment && !is_nested_deref { + err.span_suggestion_verbose( + span.shrink_to_lo(), + "consider borrowing here", + '&', + Applicability::MaybeIncorrect, + ); + } else { + err.span_help( + span, + "destructuring assignment cannot borrow from this expression; consider using a `let` binding instead", + ); } } _ => { diff --git a/compiler/rustc_borrowck/src/diagnostics/mutability_errors.rs b/compiler/rustc_borrowck/src/diagnostics/mutability_errors.rs index a0e53248c904..4f59033e5671 100644 --- a/compiler/rustc_borrowck/src/diagnostics/mutability_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/mutability_errors.rs @@ -493,7 +493,7 @@ pub(crate) fn report_mutability_error( for (_, node) in self.infcx.tcx.hir_parent_iter(upvar_hir_id) { if let Some(fn_decl) = node.fn_decl() { if !matches!( - fn_decl.implicit_self, + fn_decl.implicit_self(), hir::ImplicitSelfKind::RefImm | hir::ImplicitSelfKind::RefMut ) { err.span_suggestion_verbose( @@ -810,7 +810,7 @@ fn is_error_in_trait(&self, local: Local) -> (bool, bool, Option) { && let Some(ty) = sig.decl.inputs.get(local.index() - 1) && let hir::TyKind::Ref(_, mut_ty) = ty.kind && let hir::Mutability::Not = mut_ty.mutbl - && sig.decl.implicit_self.has_implicit_self() + && sig.decl.implicit_self().has_implicit_self() { Some(ty.span) } else { @@ -1147,7 +1147,7 @@ fn expected_fn_found_fn_mut_call(&self, err: &mut Diag<'_>, sp: Span, act: &str) arg_pos .and_then(|pos| { sig.decl.inputs.get( - pos + if sig.decl.implicit_self.has_implicit_self() { + pos + if sig.decl.implicit_self().has_implicit_self() { 1 } else { 0 @@ -1410,9 +1410,20 @@ fn suggest_make_local_mut(&self, err: &mut Diag<'_>, local: Local, name: Symbol) (span, " mut".to_owned(), true) // If there is already a binding, we modify it to be `mut`. } else if binding_exists { - // Shrink the span to just after the `&` in `&variable`. - let span = span.with_lo(span.lo() + BytePos(1)).shrink_to_lo(); - (span, "mut ".to_owned(), true) + // Replace the sigil with the mutable version. We may be dealing + // with parser recovery here and cannot assume the user actually + // typed `&` or `*const`, so we compute the prefix from the snippet. + let Ok(src) = self.infcx.tcx.sess.source_map().span_to_snippet(span) else { + return; + }; + let (prefix_len, replacement) = if local_decl.ty.is_ref() { + (src.chars().next().map_or(0, char::len_utf8), "&mut ") + } else { + (src.find("const").map_or(1, |i| i + "const".len()), "*mut ") + }; + let ws_len = src[prefix_len..].len() - src[prefix_len..].trim_start().len(); + let span = span.with_hi(span.lo() + BytePos((prefix_len + ws_len) as u32)); + (span, replacement.to_owned(), true) } else { // Otherwise, suggest that the user annotates the binding; We provide the // type of the local. diff --git a/compiler/rustc_borrowck/src/diagnostics/opaque_types.rs b/compiler/rustc_borrowck/src/diagnostics/opaque_types.rs index 31890381fd5e..94767ebdd693 100644 --- a/compiler/rustc_borrowck/src/diagnostics/opaque_types.rs +++ b/compiler/rustc_borrowck/src/diagnostics/opaque_types.rs @@ -219,12 +219,12 @@ impl<'tcx> TypeVisitor> for FindOpaqueRegion<'_, 'tcx> { fn visit_ty(&mut self, ty: Ty<'tcx>) -> Self::Result { // If we find an opaque in a local ty, then for each of its captured regions, // try to find a path between that captured regions and our borrow region... - if let ty::Alias(opaque @ ty::AliasTy { kind: ty::Opaque { def_id }, .. }) = *ty.kind() + if let ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) = *ty.kind() && let hir::OpaqueTyOrigin::FnReturn { parent, in_trait_or_impl: None } = self.tcx.opaque_ty_origin(def_id) { let variances = self.tcx.variances_of(def_id); - for (idx, (arg, variance)) in std::iter::zip(opaque.args, variances).enumerate() { + for (idx, (arg, variance)) in std::iter::zip(args, variances).enumerate() { // Skip uncaptured args. if *variance == ty::Bivariant { continue; @@ -276,12 +276,12 @@ impl<'tcx> TypeVisitor> for CheckExplicitRegionMentionAndCollectGen fn visit_ty(&mut self, ty: Ty<'tcx>) -> Self::Result { match *ty.kind() { - ty::Alias(opaque @ ty::AliasTy { kind: ty::Opaque { def_id }, .. }) => { + ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) => { if self.seen_opaques.insert(def_id) { for (bound, _) in self .tcx .explicit_item_bounds(def_id) - .iter_instantiated_copied(self.tcx, opaque.args) + .iter_instantiated_copied(self.tcx, args) { bound.visit_with(self)?; } diff --git a/compiler/rustc_borrowck/src/diagnostics/region_errors.rs b/compiler/rustc_borrowck/src/diagnostics/region_errors.rs index f6a20e41742b..5f798c6c9030 100644 --- a/compiler/rustc_borrowck/src/diagnostics/region_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/region_errors.rs @@ -15,7 +15,8 @@ use rustc_middle::hir::place::PlaceBase; use rustc_middle::mir::{AnnotationSource, ConstraintCategory, ReturnConstraint}; use rustc_middle::ty::{ - self, GenericArgs, Region, RegionVid, Ty, TyCtxt, TypeFoldable, TypeVisitor, fold_regions, + self, FnSigKind, GenericArgs, Region, RegionVid, Ty, TyCtxt, TypeFoldable, TypeVisitor, + fold_regions, }; use rustc_span::{Ident, Span, kw}; use rustc_trait_selection::error_reporting::InferCtxtErrorExt; @@ -686,6 +687,8 @@ fn report_escaping_data_error(&self, errci: &ErrorConstraintInfo<'tcx>) -> Diag< || (*category == ConstraintCategory::Assignment && self.regioncx.universal_regions().defining_ty.is_fn_def()) || self.regioncx.universal_regions().defining_ty.is_const() + || (fr_name_and_span.is_none() + && self.regioncx.universal_regions().defining_ty.is_fn_def()) { return self.report_general_error(errci); } @@ -1081,14 +1084,14 @@ fn suggest_deref_closure_return(&self, diag: &mut Diag<'_>) { } // Build a new closure where the return type is an owned value, instead of a ref. + let fn_sig_kind = + FnSigKind::default().set_safe(true).set_c_variadic(liberated_sig.c_variadic()); let closure_sig_as_fn_ptr_ty = Ty::new_fn_ptr( tcx, ty::Binder::dummy(tcx.mk_fn_sig( liberated_sig.inputs().iter().copied(), peeled_ty, - liberated_sig.c_variadic, - hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, + fn_sig_kind, )), ); let closure_ty = Ty::new_closure( diff --git a/compiler/rustc_borrowck/src/type_check/constraint_conversion.rs b/compiler/rustc_borrowck/src/type_check/constraint_conversion.rs index 703223e2e54a..868c6f11b68d 100644 --- a/compiler/rustc_borrowck/src/type_check/constraint_conversion.rs +++ b/compiler/rustc_borrowck/src/type_check/constraint_conversion.rs @@ -70,12 +70,14 @@ pub(crate) fn new( #[instrument(skip(self), level = "debug")] pub(super) fn convert_all(&mut self, query_constraints: &QueryRegionConstraints<'tcx>) { - let QueryRegionConstraints { outlives, assumptions } = query_constraints; + let QueryRegionConstraints { constraints, assumptions } = query_constraints; let assumptions = elaborate::elaborate_outlives_assumptions(self.infcx.tcx, assumptions.iter().copied()); - for &(predicate, constraint_category) in outlives { - self.convert(predicate, constraint_category, &assumptions); + for &(constraint, constraint_category) in constraints { + constraint.iter_outlives().for_each(|predicate| { + self.convert(predicate, constraint_category, &assumptions); + }); } } @@ -292,8 +294,12 @@ fn normalize_and_add_type_outlives_constraints( ) { Ok(TypeOpOutput { output: ty, constraints, .. }) => { // FIXME(higher_ranked_auto): What should we do with the assumptions here? - if let Some(QueryRegionConstraints { outlives, assumptions: _ }) = constraints { - next_outlives_predicates.extend(outlives.iter().copied()); + if let Some(QueryRegionConstraints { constraints, assumptions: _ }) = constraints { + next_outlives_predicates.extend(constraints.iter().flat_map( + |(constraint, category)| { + constraint.iter_outlives().map(|outlives| (outlives, *category)) + }, + )); } ty } diff --git a/compiler/rustc_borrowck/src/type_check/input_output.rs b/compiler/rustc_borrowck/src/type_check/input_output.rs index 4e762b368496..2e6a2962b876 100644 --- a/compiler/rustc_borrowck/src/type_check/input_output.rs +++ b/compiler/rustc_borrowck/src/type_check/input_output.rs @@ -32,6 +32,15 @@ pub(super) fn check_signature_annotation(&mut self) { return; } + // If the MIR body was constructed via `construct_error` (because an + // earlier pass like match checking failed), its args may not match + // the user-provided signature (e.g. a coroutine with too many + // parameters). Bail out as this can cause panic, + // see . + if self.body.tainted_by_errors.is_some() { + return; + } + let user_provided_poly_sig = self.tcx().closure_user_provided_sig(mir_def_id); // Instantiate the canonicalized variables from user-provided signature @@ -94,9 +103,7 @@ pub(super) fn check_signature_annotation(&mut self) { user_provided_sig = self.tcx().mk_fn_sig( user_provided_sig.inputs().iter().copied(), output_ty, - user_provided_sig.c_variadic, - user_provided_sig.safety, - user_provided_sig.abi, + user_provided_sig.fn_sig_kind, ); } diff --git a/compiler/rustc_borrowck/src/type_check/mod.rs b/compiler/rustc_borrowck/src/type_check/mod.rs index 0b7b4e01e752..7cacbb1c06e6 100644 --- a/compiler/rustc_borrowck/src/type_check/mod.rs +++ b/compiler/rustc_borrowck/src/type_check/mod.rs @@ -1015,7 +1015,7 @@ fn visit_rvalue(&mut self, rvalue: &Rvalue<'tcx>, location: Location) { if let ty::FnDef(def_id, _) = *src_ty.kind() && let ty::FnPtr(_, target_hdr) = *ty.kind() && tcx.codegen_fn_attrs(def_id).safe_target_features - && target_hdr.safety.is_safe() + && target_hdr.safety().is_safe() && let Some(safe_sig) = tcx.adjust_target_feature_sig( def_id, src_sig, @@ -1971,7 +1971,8 @@ fn check_call_inputs( term_location: Location, call_source: CallSource, ) { - if args.len() < sig.inputs().len() || (args.len() > sig.inputs().len() && !sig.c_variadic) { + if args.len() < sig.inputs().len() || (args.len() > sig.inputs().len() && !sig.c_variadic()) + { span_mirbug!(self, term, "call to {:?} with wrong # of args", sig); } diff --git a/compiler/rustc_builtin_macros/Cargo.toml b/compiler/rustc_builtin_macros/Cargo.toml index dd84a2c1802d..ebf25d68314d 100644 --- a/compiler/rustc_builtin_macros/Cargo.toml +++ b/compiler/rustc_builtin_macros/Cargo.toml @@ -29,7 +29,7 @@ rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } rustc_target = { path = "../rustc_target" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_builtin_macros/src/cfg.rs b/compiler/rustc_builtin_macros/src/cfg.rs index c4a458089f2d..2872cff0fdc7 100644 --- a/compiler/rustc_builtin_macros/src/cfg.rs +++ b/compiler/rustc_builtin_macros/src/cfg.rs @@ -6,7 +6,8 @@ use rustc_ast::{AttrStyle, token}; use rustc_attr_parsing::parser::{AllowExprMetavar, MetaItemOrLitParser}; use rustc_attr_parsing::{ - self as attr, AttributeParser, CFG_TEMPLATE, ParsedDescription, ShouldEmit, parse_cfg_entry, + self as attr, AttributeParser, AttributeSafety, CFG_TEMPLATE, ParsedDescription, ShouldEmit, + parse_cfg_entry, }; use rustc_expand::base::{DummyResult, ExpandResult, ExtCtxt, MacEager, MacroExpanderResult}; use rustc_hir::attrs::CfgEntry; @@ -53,6 +54,7 @@ fn parse_cfg(cx: &ExtCtxt<'_>, span: Span, tts: TokenStream) -> Result { let is_packed = matches!( - AttributeParser::parse_limited(cx.sess, &item.attrs, sym::repr, item.span, item.id, None), + AttributeParser::parse_limited(cx.sess, &item.attrs, &[sym::repr]), Some(Attribute::Parsed(AttributeKind::Repr { reprs, .. })) if reprs.iter().any(|(x, _)| matches!(x, ReprPacked(..))) ); diff --git a/compiler/rustc_builtin_macros/src/eii.rs b/compiler/rustc_builtin_macros/src/eii.rs index 7b651ed84828..fd0ef8500c6c 100644 --- a/compiler/rustc_builtin_macros/src/eii.rs +++ b/compiler/rustc_builtin_macros/src/eii.rs @@ -1,7 +1,8 @@ use rustc_ast::token::{Delimiter, TokenKind}; use rustc_ast::tokenstream::{DelimSpacing, DelimSpan, Spacing, TokenStream, TokenTree}; use rustc_ast::{ - Attribute, DUMMY_NODE_ID, EiiDecl, EiiImpl, ItemKind, MetaItem, Path, StmtKind, Visibility, ast, + Attribute, DUMMY_NODE_ID, EiiDecl, EiiImpl, ItemKind, MetaItem, Mutability, Path, StmtKind, + Visibility, ast, }; use rustc_ast_pretty::pprust::path_to_string; use rustc_expand::base::{Annotatable, ExtCtxt}; @@ -10,8 +11,9 @@ use crate::errors::{ EiiExternTargetExpectedList, EiiExternTargetExpectedMacro, EiiExternTargetExpectedUnsafe, - EiiMacroExpectedMaxOneArgument, EiiOnlyOnce, EiiSharedMacroExpectedFunction, - EiiSharedMacroInStatementPosition, + EiiMacroExpectedMaxOneArgument, EiiOnlyOnce, EiiSharedMacroInStatementPosition, + EiiSharedMacroTarget, EiiStaticArgumentRequired, EiiStaticDefault, + EiiStaticMultipleImplementations, EiiStaticMutable, }; /// ```rust @@ -73,44 +75,72 @@ fn eii_( }); return vec![orig_item]; } else { - ecx.dcx().emit_err(EiiSharedMacroExpectedFunction { + ecx.dcx().emit_err(EiiSharedMacroTarget { span: eii_attr_span, name: path_to_string(&meta_item.path), }); return vec![orig_item]; }; - let ast::Item { attrs, id: _, span: _, vis, kind: ItemKind::Fn(func), tokens: _ } = - item.as_ref() - else { - ecx.dcx().emit_err(EiiSharedMacroExpectedFunction { - span: eii_attr_span, - name: path_to_string(&meta_item.path), - }); - return vec![Annotatable::Item(item)]; + let ast::Item { attrs, id: _, span: _, vis, kind, tokens: _ } = item.as_ref(); + let (item_span, foreign_item_name) = match kind { + ItemKind::Fn(func) => (func.sig.span, func.ident), + ItemKind::Static(stat) => { + // Statics with a default are not supported yet + if let Some(stat_body) = &stat.expr { + ecx.dcx().emit_err(EiiStaticDefault { + span: stat_body.span, + name: path_to_string(&meta_item.path), + }); + return vec![]; + } + // Statics must have an explicit name for the eii + if meta_item.is_word() { + ecx.dcx().emit_err(EiiStaticArgumentRequired { + span: eii_attr_span, + name: path_to_string(&meta_item.path), + }); + return vec![]; + } + + // Mut statics are currently not supported + if stat.mutability == Mutability::Mut { + ecx.dcx().emit_err(EiiStaticMutable { + span: eii_attr_span, + name: path_to_string(&meta_item.path), + }); + } + + (item.span, stat.ident) + } + _ => { + ecx.dcx().emit_err(EiiSharedMacroTarget { + span: eii_attr_span, + name: path_to_string(&meta_item.path), + }); + return vec![Annotatable::Item(item)]; + } }; + // only clone what we need let attrs = attrs.clone(); - let func = (**func).clone(); let vis = vis.clone(); let attrs_from_decl = filter_attrs_for_multiple_eii_attr(ecx, attrs, eii_attr_span, &meta_item.path); - let Ok(macro_name) = name_for_impl_macro(ecx, &func, &meta_item) else { + let Ok(macro_name) = name_for_impl_macro(ecx, foreign_item_name, &meta_item) else { // we don't need to wrap in Annotatable::Stmt conditionally since // EII can't be used on items in statement position return vec![Annotatable::Item(item)]; }; - // span of the declaring item without attributes - let item_span = func.sig.span; - let foreign_item_name = func.ident; - let mut module_items = Vec::new(); - if func.body.is_some() { - module_items.push(generate_default_impl( + if let ItemKind::Fn(func) = kind + && func.body.is_some() + { + module_items.push(generate_default_func_impl( ecx, &func, impl_unsafe, @@ -125,7 +155,7 @@ fn eii_( ecx, eii_attr_span, item_span, - func, + kind, vis, &attrs_from_decl, )); @@ -148,11 +178,11 @@ fn eii_( /// declaration of the EII. fn name_for_impl_macro( ecx: &mut ExtCtxt<'_>, - func: &ast::Fn, + item_ident: Ident, meta_item: &MetaItem, ) -> Result { if meta_item.is_word() { - Ok(func.ident) + Ok(item_ident) } else if let Some([first]) = meta_item.meta_item_list() && let Some(m) = first.meta_item() && m.path.segments.len() == 1 @@ -190,7 +220,7 @@ fn filter_attrs_for_multiple_eii_attr( .collect() } -fn generate_default_impl( +fn generate_default_func_impl( ecx: &mut ExtCtxt<'_>, func: &ast::Fn, impl_unsafe: bool, @@ -257,7 +287,7 @@ fn generate_foreign_item( ecx: &mut ExtCtxt<'_>, eii_attr_span: Span, item_span: Span, - mut func: ast::Fn, + item_kind: &ItemKind, vis: Visibility, attrs_from_decl: &[Attribute], ) -> Box { @@ -268,30 +298,21 @@ fn generate_foreign_item( // This attribute makes sure that we later know that this foreign item's symbol should not be. foreign_item_attrs.push(ecx.attr_word(sym::rustc_eii_foreign_item, eii_attr_span)); - let abi = match func.sig.header.ext { - // extern "X" fn => extern "X" {} - ast::Extern::Explicit(lit, _) => Some(lit), - // extern fn => extern {} - ast::Extern::Implicit(_) => None, - // fn => extern "Rust" {} - ast::Extern::None => Some(ast::StrLit { - symbol: sym::Rust, - suffix: None, - symbol_unescaped: sym::Rust, - style: ast::StrStyle::Cooked, - span: eii_attr_span, - }), + // We set the abi to the default "rust" abi, which can be overridden by `generate_foreign_func`, + // if a specific abi was specified on the EII function + let mut abi = Some(ast::StrLit { + symbol: sym::Rust, + suffix: None, + symbol_unescaped: sym::Rust, + style: ast::StrStyle::Cooked, + span: eii_attr_span, + }); + let foreign_kind = match item_kind { + ItemKind::Fn(func) => generate_foreign_func(func.clone(), &mut abi), + ItemKind::Static(stat) => generate_foreign_static(stat.clone()), + _ => unreachable!("Target was checked earlier"), }; - // ABI has been moved to the extern {} block, so we remove it from the fn item. - func.sig.header.ext = ast::Extern::None; - func.body = None; - - // And mark safe functions explicitly as `safe fn`. - if func.sig.header.safety == ast::Safety::Default { - func.sig.header.safety = ast::Safety::Safe(func.sig.span); - } - ecx.item( eii_attr_span, ThinVec::new(), @@ -304,13 +325,46 @@ fn generate_foreign_item( id: ast::DUMMY_NODE_ID, span: item_span, vis, - kind: ast::ForeignItemKind::Fn(Box::new(func.clone())), + kind: foreign_kind, tokens: None, })]), }), ) } +fn generate_foreign_func( + mut func: Box, + abi: &mut Option, +) -> ast::ForeignItemKind { + match func.sig.header.ext { + // extern "X" fn => extern "X" {} + ast::Extern::Explicit(lit, _) => *abi = Some(lit), + // extern fn => extern {} + ast::Extern::Implicit(_) => *abi = None, + // no abi was specified, so we keep the default + ast::Extern::None => {} + }; + + // ABI has been moved to the extern {} block, so we remove it from the fn item. + func.sig.header.ext = ast::Extern::None; + func.body = None; + + // And mark safe functions explicitly as `safe fn`. + if func.sig.header.safety == ast::Safety::Default { + func.sig.header.safety = ast::Safety::Safe(func.sig.span); + } + + ast::ForeignItemKind::Fn(func) +} + +fn generate_foreign_static(mut stat: Box) -> ast::ForeignItemKind { + if stat.safety == ast::Safety::Default { + stat.safety = ast::Safety::Safe(stat.ident.span); + } + + ast::ForeignItemKind::Static(stat) +} + /// Generate a stub macro (a bit like in core) that will roughly look like: /// /// ```rust, ignore, example @@ -453,19 +507,25 @@ pub(crate) fn eii_shared_macro( { item } else { - ecx.dcx().emit_err(EiiSharedMacroExpectedFunction { - span, - name: path_to_string(&meta_item.path), - }); + ecx.dcx().emit_err(EiiSharedMacroTarget { span, name: path_to_string(&meta_item.path) }); return vec![item]; }; - let ItemKind::Fn(f) = &mut i.kind else { - ecx.dcx().emit_err(EiiSharedMacroExpectedFunction { - span, - name: path_to_string(&meta_item.path), - }); - return vec![item]; + let eii_impls = match &mut i.kind { + ItemKind::Fn(func) => &mut func.eii_impls, + ItemKind::Static(stat) => { + if !stat.eii_impls.is_empty() { + // Reject multiple implementations on one static item + // because it might be unintuitive for libraries defining statics the defined statics may alias + ecx.dcx().emit_err(EiiStaticMultipleImplementations { span }); + } + &mut stat.eii_impls + } + _ => { + ecx.dcx() + .emit_err(EiiSharedMacroTarget { span, name: path_to_string(&meta_item.path) }); + return vec![item]; + } }; let is_default = if meta_item.is_word() { @@ -483,7 +543,7 @@ pub(crate) fn eii_shared_macro( return vec![item]; }; - f.eii_impls.push(EiiImpl { + eii_impls.push(EiiImpl { node_id: DUMMY_NODE_ID, inner_span: meta_item.path.span, eii_macro_path: meta_item.path.clone(), diff --git a/compiler/rustc_builtin_macros/src/errors.rs b/compiler/rustc_builtin_macros/src/errors.rs index 87f1ff960a82..ad641beb87d9 100644 --- a/compiler/rustc_builtin_macros/src/errors.rs +++ b/compiler/rustc_builtin_macros/src/errors.rs @@ -158,6 +158,16 @@ pub(crate) struct AllocMustStatics { pub(crate) span: Span, } +#[derive(Diagnostic)] +#[diag("allocators cannot be `#[thread_local]`")] +pub(crate) struct AllocCannotThreadLocal { + #[primary_span] + pub(crate) span: Span, + #[label("marked `#[thread_local]` here")] + #[suggestion("remove this attribute", code = "", applicability = "maybe-incorrect")] + pub(crate) attr: Span, +} + pub(crate) use autodiff::*; mod autodiff { @@ -1107,8 +1117,42 @@ pub(crate) struct EiiExternTargetExpectedUnsafe { } #[derive(Diagnostic)] -#[diag("`#[{$name}]` is only valid on functions")] -pub(crate) struct EiiSharedMacroExpectedFunction { +#[diag("`#[{$name}]` is only valid on functions and statics")] +pub(crate) struct EiiSharedMacroTarget { + #[primary_span] + pub span: Span, + pub name: String, +} + +#[derive(Diagnostic)] +#[diag("static cannot implement multiple EIIs")] +#[note( + "this is not allowed because multiple externally implementable statics that alias may be unintuitive" +)] +pub(crate) struct EiiStaticMultipleImplementations { + #[primary_span] + pub span: Span, +} + +#[derive(Diagnostic)] +#[diag("`#[{$name}]` cannot be used on statics with a value")] +pub(crate) struct EiiStaticDefault { + #[primary_span] + pub span: Span, + pub name: String, +} + +#[derive(Diagnostic)] +#[diag("`#[{$name}]` requires the name as an explicit argument when used on a static")] +pub(crate) struct EiiStaticArgumentRequired { + #[primary_span] + pub span: Span, + pub name: String, +} + +#[derive(Diagnostic)] +#[diag("`#[{$name}]` cannot be used on mutable statics")] +pub(crate) struct EiiStaticMutable { #[primary_span] pub span: Span, pub name: String, diff --git a/compiler/rustc_builtin_macros/src/global_allocator.rs b/compiler/rustc_builtin_macros/src/global_allocator.rs index 85ad8a63a54f..208562b8d0bc 100644 --- a/compiler/rustc_builtin_macros/src/global_allocator.rs +++ b/compiler/rustc_builtin_macros/src/global_allocator.rs @@ -38,6 +38,12 @@ pub(crate) fn expand( return vec![orig_item]; }; + // Forbid `#[thread_local]` attributes on the item + if let Some(attr) = item.attrs.iter().find(|x| x.has_name(sym::thread_local)) { + ecx.dcx().emit_err(errors::AllocCannotThreadLocal { span: item.span, attr: attr.span }); + return vec![orig_item]; + } + // Generate a bunch of new items using the AllocFnFactory let span = ecx.with_def_site_ctxt(item.span); let f = AllocFnFactory { span, ty_span, global: ident, cx: ecx }; diff --git a/compiler/rustc_builtin_macros/src/pattern_type.rs b/compiler/rustc_builtin_macros/src/pattern_type.rs index 4126547b0515..53ab3fcd9b34 100644 --- a/compiler/rustc_builtin_macros/src/pattern_type.rs +++ b/compiler/rustc_builtin_macros/src/pattern_type.rs @@ -80,6 +80,7 @@ fn pat_to_ty_pat(cx: &mut ExtCtxt<'_>, pat: ast::Pat) -> TyPat { TyPatKind::Or(variants.into_iter().map(|pat| pat_to_ty_pat(cx, pat)).collect()) } ast::PatKind::Err(guar) => TyPatKind::Err(guar), + ast::PatKind::Paren(p) => pat_to_ty_pat(cx, *p).kind, _ => TyPatKind::Err(cx.dcx().span_err(pat.span, "pattern not supported in pattern types")), }; ty_pat(kind, pat.span) diff --git a/compiler/rustc_builtin_macros/src/proc_macro_harness.rs b/compiler/rustc_builtin_macros/src/proc_macro_harness.rs index 24a5d79958c6..aa936b46eec2 100644 --- a/compiler/rustc_builtin_macros/src/proc_macro_harness.rs +++ b/compiler/rustc_builtin_macros/src/proc_macro_harness.rs @@ -1,7 +1,7 @@ use std::{mem, slice}; use rustc_ast::visit::{self, Visitor}; -use rustc_ast::{self as ast, HasNodeId, NodeId, attr}; +use rustc_ast::{self as ast, NodeId, attr}; use rustc_ast_pretty::pprust; use rustc_attr_parsing::AttributeParser; use rustc_errors::DiagCtxtHandle; @@ -108,10 +108,7 @@ fn collect_custom_derive( })) = AttributeParser::parse_limited( self.session, slice::from_ref(attr), - sym::proc_macro_derive, - item.span, - item.node_id(), - None, + &[sym::proc_macro_derive], ) else { return; diff --git a/compiler/rustc_builtin_macros/src/test.rs b/compiler/rustc_builtin_macros/src/test.rs index 5764dfc83927..1b761614f3e6 100644 --- a/compiler/rustc_builtin_macros/src/test.rs +++ b/compiler/rustc_builtin_macros/src/test.rs @@ -3,7 +3,7 @@ use std::{assert_matches, iter}; -use rustc_ast::{self as ast, GenericParamKind, HasNodeId, attr, join_path_idents}; +use rustc_ast::{self as ast, GenericParamKind, attr, join_path_idents}; use rustc_ast_pretty::pprust; use rustc_attr_parsing::AttributeParser; use rustc_errors::{Applicability, Diag, Level}; @@ -480,14 +480,7 @@ fn should_ignore_message(i: &ast::Item) -> Option { fn should_panic(cx: &ExtCtxt<'_>, i: &ast::Item) -> ShouldPanic { if let Some(Attribute::Parsed(AttributeKind::ShouldPanic { reason, .. })) = - AttributeParser::parse_limited( - cx.sess, - &i.attrs, - sym::should_panic, - i.span, - i.node_id(), - None, - ) + AttributeParser::parse_limited(cx.sess, &i.attrs, &[sym::should_panic]) { ShouldPanic::Yes(reason) } else { diff --git a/compiler/rustc_builtin_macros/src/test_harness.rs b/compiler/rustc_builtin_macros/src/test_harness.rs index 1bb6d8a6bfd0..adcf4086fb1e 100644 --- a/compiler/rustc_builtin_macros/src/test_harness.rs +++ b/compiler/rustc_builtin_macros/src/test_harness.rs @@ -61,7 +61,7 @@ pub fn inject( // Do this here so that the test_runner crate attribute gets marked as used // even in non-test builds - let test_runner = get_test_runner(sess, features, krate); + let test_runner = get_test_runner(sess, krate); if sess.is_test_crate() { let panic_strategy = match (panic_strategy, sess.opts.unstable_opts.panic_abort_tests) { @@ -387,15 +387,8 @@ fn get_test_name(i: &ast::Item) -> Option { attr::first_attr_value_str_by_name(&i.attrs, sym::rustc_test_marker) } -fn get_test_runner(sess: &Session, features: &Features, krate: &ast::Crate) -> Option { - match AttributeParser::parse_limited( - sess, - &krate.attrs, - sym::test_runner, - krate.spans.inner_span, - krate.id, - Some(features), - ) { +fn get_test_runner(sess: &Session, krate: &ast::Crate) -> Option { + match AttributeParser::parse_limited(sess, &krate.attrs, &[sym::test_runner]) { Some(rustc_hir::Attribute::Parsed(AttributeKind::TestRunner(path))) => Some(path), _ => None, } diff --git a/compiler/rustc_codegen_cranelift/example/mini_core.rs b/compiler/rustc_codegen_cranelift/example/mini_core.rs index 218050982e6d..ab9d2a743739 100644 --- a/compiler/rustc_codegen_cranelift/example/mini_core.rs +++ b/compiler/rustc_codegen_cranelift/example/mini_core.rs @@ -8,6 +8,7 @@ rustc_attrs, rustc_private, transparent_unions, + pattern_types, auto_traits, freeze_impls )] @@ -15,6 +16,30 @@ #![no_core] #![allow(dead_code, internal_features, ambiguous_wide_pointer_comparisons)] +#[lang = "pointee_trait"] +pub trait Pointee: PointeeSized { + #[lang = "metadata_type"] + // needed so that layout_of will return `TooGeneric` instead of `Unknown` + // when asked for the layout of `*const T`. Which is important for making + // transmutes between raw pointers (and especially pattern types of raw pointers) + // work. + type Metadata: Copy + Sync + Unpin + Freeze; +} + +#[lang = "dyn_metadata"] +pub struct DynMetadata { + _vtable_ptr: NonNull, + _phantom: PhantomData, +} + +unsafe extern "C" { + /// Opaque type for accessing vtables. + /// + /// Private implementation detail of `DynMetadata::size_of` etc. + /// There is conceptually not actually any Abstract Machine memory behind this pointer. + type VTable; +} + #[lang = "pointee_sized"] pub trait PointeeSized {} @@ -105,7 +130,7 @@ unsafe impl<'a, T: PointeeSized> Sync for &'a T {} unsafe impl Sync for [T; N] {} #[lang = "freeze"] -unsafe auto trait Freeze {} +pub unsafe auto trait Freeze {} unsafe impl Freeze for PhantomData {} unsafe impl Freeze for *const T {} @@ -570,10 +595,24 @@ pub trait Deref { fn deref(&self) -> &Self::Target; } +#[rustc_builtin_macro(pattern_type)] +#[macro_export] +macro_rules! pattern_type { + ($($arg:tt)*) => { + /* compiler built-in */ + }; +} + +impl CoerceUnsized for pattern_type!(*const T is !null) where + T: Unsize +{ +} + +impl, U> DispatchFromDyn for pattern_type!(T is !null) {} + #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] -pub struct NonNull(pub *const T); +pub struct NonNull(pub pattern_type!(*const T is !null)); impl CoerceUnsized> for NonNull where T: Unsize {} impl DispatchFromDyn> for NonNull where T: Unsize {} @@ -600,7 +639,16 @@ pub fn new(val: T) -> Box { let size = size_of::(); let ptr = libc::malloc(size); intrinsics::copy(&val as *const T as *const u8, ptr, size); - Box(Unique { pointer: NonNull(ptr as *const T), _marker: PhantomData }, Global) + Box( + Unique { + pointer: NonNull(intrinsics::transmute::< + *mut u8, + pattern_type!(*const T is !null), + >(ptr)), + _marker: PhantomData, + }, + Global, + ) } } } @@ -609,7 +657,9 @@ impl Drop for Box { fn drop(&mut self) { // inner value is dropped by compiler unsafe { - libc::free(self.0.pointer.0 as *mut u8); + libc::free(intrinsics::transmute::( + self.0.pointer.0, + ) as *mut u8); } } } diff --git a/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs b/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs index 6734d19fbb48..5e986201b385 100644 --- a/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs +++ b/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs @@ -1,4 +1,13 @@ -#![feature(no_core, lang_items, never_type, extern_types, thread_local, repr_simd, rustc_private)] +#![feature( + no_core, + lang_items, + never_type, + extern_types, + thread_local, + repr_simd, + pattern_types, + rustc_private +)] #![cfg_attr(not(any(jit, target_vendor = "apple", windows)), feature(linkage))] #![no_core] #![allow(dead_code, non_camel_case_types, internal_features)] @@ -153,7 +162,10 @@ extern "C" fn bool_struct_in_11(_arg0: bool_11) {} #[allow(unreachable_code)] // FIXME false positive fn main() { - take_unique(Unique { pointer: unsafe { NonNull(1 as *mut ()) }, _marker: PhantomData }); + take_unique(Unique { + pointer: unsafe { NonNull(intrinsics::transmute(1 as *mut ())) }, + _marker: PhantomData, + }); take_f32(0.1); call_return_u128_pair(); @@ -219,7 +231,12 @@ fn main() { let noisy_unsized_drop = const { intrinsics::needs_drop::() }; assert!(noisy_unsized_drop); - Unique { pointer: NonNull(1 as *mut &str), _marker: PhantomData } as Unique; + Unique { + pointer: NonNull(intrinsics::transmute::<_, pattern_type!(*const &str is !null)>( + 1 as *mut &str, + )), + _marker: PhantomData, + } as Unique; struct MyDst(T); diff --git a/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs b/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs index 44b63aa95f83..0283263cc604 100644 --- a/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs +++ b/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs @@ -26,7 +26,9 @@ fn reg_to_abi_param(reg: Reg) -> AbiParam { (RegKind::Float, 4) => types::F32, (RegKind::Float, 8) => types::F64, (RegKind::Float, 16) => types::F128, - (RegKind::Vector, size) => types::I8.by(u32::try_from(size).unwrap()).unwrap(), + (RegKind::Vector { hint_vector_elem: _ }, size) => { + types::I8.by(u32::try_from(size).unwrap()).unwrap() + } _ => unreachable!("{:?}", reg), }; AbiParam::new(clif_ty) diff --git a/compiler/rustc_codegen_cranelift/src/driver/aot.rs b/compiler/rustc_codegen_cranelift/src/driver/aot.rs index c74e0b9b1a66..4329c5d682cb 100644 --- a/compiler/rustc_codegen_cranelift/src/driver/aot.rs +++ b/compiler/rustc_codegen_cranelift/src/driver/aot.rs @@ -380,11 +380,9 @@ fn codegen_cgu_content( fn module_codegen( tcx: TyCtxt<'_>, - (global_asm_config, cgu_name, token): ( - Arc, - rustc_span::Symbol, - ConcurrencyLimiterToken, - ), + global_asm_config: Arc, + cgu_name: rustc_span::Symbol, + token: ConcurrencyLimiterToken, ) -> OngoingModuleCodegen { let mut module = make_module(tcx.sess, cgu_name.as_str().to_string()); @@ -513,8 +511,14 @@ pub(crate) fn run_aot(tcx: TyCtxt<'_>) -> Box { let (module, _) = tcx.dep_graph.with_task( dep_node, tcx, - (global_asm_config.clone(), cgu.name(), concurrency_limiter.acquire(tcx.dcx())), - module_codegen, + || { + module_codegen( + tcx, + global_asm_config.clone(), + cgu.name(), + concurrency_limiter.acquire(tcx.dcx()), + ) + }, Some(rustc_middle::dep_graph::hash_result), ); IntoDynSyncSend(module) diff --git a/compiler/rustc_codegen_cranelift/src/value_and_place.rs b/compiler/rustc_codegen_cranelift/src/value_and_place.rs index 5b76a4cb9779..67adbaf028eb 100644 --- a/compiler/rustc_codegen_cranelift/src/value_and_place.rs +++ b/compiler/rustc_codegen_cranelift/src/value_and_place.rs @@ -98,7 +98,7 @@ pub(crate) fn by_val_pair( /// Create an instance of a ZST /// - /// The is represented by a dangling pointer of suitable alignment. + /// The ZST is represented by a dangling pointer of suitable alignment. pub(crate) fn zst(layout: TyAndLayout<'tcx>) -> CValue<'tcx> { assert!(layout.is_zst()); CValue::by_ref(crate::Pointer::dangling(layout.align.abi), layout) @@ -870,20 +870,10 @@ pub(crate) fn assert_assignable<'tcx>( let from_sig = fx .tcx .normalize_erasing_late_bound_regions(fx.typing_env(), from_ty.fn_sig(fx.tcx)); - let FnSig { - inputs_and_output: types_from, - c_variadic: c_variadic_from, - safety: unsafety_from, - abi: abi_from, - } = from_sig; + let FnSig { inputs_and_output: types_from, fn_sig_kind: fn_sig_kind_from } = from_sig; let to_sig = fx.tcx.normalize_erasing_late_bound_regions(fx.typing_env(), to_ty.fn_sig(fx.tcx)); - let FnSig { - inputs_and_output: types_to, - c_variadic: c_variadic_to, - safety: unsafety_to, - abi: abi_to, - } = to_sig; + let FnSig { inputs_and_output: types_to, fn_sig_kind: fn_sig_kind_to } = to_sig; let mut types_from = types_from.iter(); let mut types_to = types_to.iter(); loop { @@ -894,17 +884,7 @@ pub(crate) fn assert_assignable<'tcx>( } } assert_eq!( - c_variadic_from, c_variadic_to, - "Can't write fn ptr with incompatible sig {:?} to place with sig {:?}\n\n{:#?}", - from_sig, to_sig, fx, - ); - assert_eq!( - unsafety_from, unsafety_to, - "Can't write fn ptr with incompatible sig {:?} to place with sig {:?}\n\n{:#?}", - from_sig, to_sig, fx, - ); - assert_eq!( - abi_from, abi_to, + fn_sig_kind_from, fn_sig_kind_to, "Can't write fn ptr with incompatible sig {:?} to place with sig {:?}\n\n{:#?}", from_sig, to_sig, fx, ); diff --git a/compiler/rustc_codegen_gcc/example/mini_core.rs b/compiler/rustc_codegen_gcc/example/mini_core.rs index 2e165cc3c129..87b059526ea0 100644 --- a/compiler/rustc_codegen_gcc/example/mini_core.rs +++ b/compiler/rustc_codegen_gcc/example/mini_core.rs @@ -9,6 +9,7 @@ transparent_unions, auto_traits, freeze_impls, + pattern_types, thread_local )] #![no_core] @@ -580,9 +581,16 @@ impl Allocator for () {} impl Allocator for Global {} #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] -pub struct NonNull(pub *const T); +pub struct NonNull(pub pattern_type!(*const T is !null)); + +#[rustc_builtin_macro(pattern_type)] +#[macro_export] +macro_rules! pattern_type { + ($($arg:tt)*) => { + /* compiler built-in */ + }; +} impl CoerceUnsized> for NonNull where T: Unsize {} impl DispatchFromDyn> for NonNull where T: Unsize {} diff --git a/compiler/rustc_codegen_gcc/src/abi.rs b/compiler/rustc_codegen_gcc/src/abi.rs index 4d1274a63d1f..8277231f16a5 100644 --- a/compiler/rustc_codegen_gcc/src/abi.rs +++ b/compiler/rustc_codegen_gcc/src/abi.rs @@ -90,7 +90,9 @@ fn gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, '_>) -> Type<'gcc> { 64 => cx.type_f64(), _ => bug!("unsupported float: {:?}", self), }, - RegKind::Vector => cx.type_vector(cx.type_i8(), self.size.bytes()), + RegKind::Vector { hint_vector_elem: _ } => { + cx.type_vector(cx.type_i8(), self.size.bytes()) + } } } } diff --git a/compiler/rustc_codegen_gcc/src/base.rs b/compiler/rustc_codegen_gcc/src/base.rs index 73b0723895b4..7d63f430af68 100644 --- a/compiler/rustc_codegen_gcc/src/base.rs +++ b/compiler/rustc_codegen_gcc/src/base.rs @@ -83,8 +83,7 @@ pub fn compile_codegen_unit( let (module, _) = tcx.dep_graph.with_task( dep_node, tcx, - (cgu_name, target_info, lto_supported), - module_codegen, + || module_codegen(tcx, cgu_name, target_info, lto_supported), Some(dep_graph::hash_result), ); let time_to_codegen = start_time.elapsed(); @@ -96,7 +95,9 @@ pub fn compile_codegen_unit( fn module_codegen( tcx: TyCtxt<'_>, - (cgu_name, target_info, lto_supported): (Symbol, LockedTargetInfo, bool), + cgu_name: Symbol, + target_info: LockedTargetInfo, + lto_supported: bool, ) -> ModuleCodegen { let cgu = tcx.codegen_unit(cgu_name); // Instantiate monomorphizations without filling out definitions yet... diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs index 83ac627d27c5..2a7c88afe17d 100644 --- a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs +++ b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs @@ -7,8 +7,6 @@ #[cfg(feature = "master")] use gccjit::Type; use gccjit::{ComparisonOp, Function, FunctionType, RValue, ToRValue, UnaryOp}; -#[cfg(feature = "master")] -use rustc_abi::ExternAbi; use rustc_abi::{BackendRepr, HasDataLayout, WrappingRange}; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::base::wants_msvc_seh; @@ -1483,32 +1481,26 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>( // `unsafe fn(*mut i8) -> ()` let try_fn_ty = Ty::new_fn_ptr( tcx, - ty::Binder::dummy(tcx.mk_fn_sig( + ty::Binder::dummy(tcx.mk_fn_sig_rust_abi( iter::once(i8p), tcx.types.unit, - false, rustc_hir::Safety::Unsafe, - ExternAbi::Rust, )), ); // `unsafe fn(*mut i8, *mut i8) -> ()` let catch_fn_ty = Ty::new_fn_ptr( tcx, - ty::Binder::dummy(tcx.mk_fn_sig( + ty::Binder::dummy(tcx.mk_fn_sig_rust_abi( [i8p, i8p].iter().cloned(), tcx.types.unit, - false, rustc_hir::Safety::Unsafe, - ExternAbi::Rust, )), ); // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32` - let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig( + let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig_rust_abi( [try_fn_ty, i8p, catch_fn_ty], tcx.types.i32, - false, rustc_hir::Safety::Unsafe, - ExternAbi::Rust, )); let rust_try = gen_fn(cx, "__rust_try", rust_fn_sig, codegen); cx.rust_try_fn.set(Some(rust_try)); diff --git a/compiler/rustc_codegen_llvm/src/abi.rs b/compiler/rustc_codegen_llvm/src/abi.rs index a6e841e440a2..dcde960258a5 100644 --- a/compiler/rustc_codegen_llvm/src/abi.rs +++ b/compiler/rustc_codegen_llvm/src/abi.rs @@ -2,8 +2,8 @@ use libc::c_uint; use rustc_abi::{ - ArmCall, BackendRepr, CanonAbi, HasDataLayout, InterruptKind, Primitive, Reg, RegKind, Size, - X86Call, + ArmCall, BackendRepr, CanonAbi, Float, HasDataLayout, Integer, InterruptKind, Primitive, Reg, + RegKind, Size, X86Call, }; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; @@ -38,11 +38,12 @@ fn apply_attrs_to_callsite( const ABI_AFFECTING_ATTRIBUTES: [(ArgAttribute, llvm::AttributeKind); 1] = [(ArgAttribute::InReg, llvm::AttributeKind::InReg)]; -const OPTIMIZATION_ATTRIBUTES: [(ArgAttribute, llvm::AttributeKind); 4] = [ +const OPTIMIZATION_ATTRIBUTES: [(ArgAttribute, llvm::AttributeKind); 5] = [ (ArgAttribute::NoAlias, llvm::AttributeKind::NoAlias), (ArgAttribute::NonNull, llvm::AttributeKind::NonNull), (ArgAttribute::ReadOnly, llvm::AttributeKind::ReadOnly), (ArgAttribute::NoUndef, llvm::AttributeKind::NoUndef), + (ArgAttribute::Writable, llvm::AttributeKind::Writable), ]; const CAPTURES_ATTRIBUTES: [(ArgAttribute, llvm::AttributeKind); 3] = [ @@ -137,7 +138,31 @@ fn llvm_type<'ll>(&self, cx: &CodegenCx<'ll, '_>) -> &'ll Type { 128 => cx.type_f128(), _ => bug!("unsupported float: {:?}", self), }, - RegKind::Vector => cx.type_vector(cx.type_i8(), self.size.bytes()), + RegKind::Vector { hint_vector_elem } => { + // NOTE: it is valid to ignore the element type hint (and always pick i8). + // But providing a more accurate type means fewer casts in LLVM IR, + // which helps with optimization. + let ty = match hint_vector_elem { + Primitive::Int(integer, _) => match integer { + Integer::I8 => cx.type_ix(8), + Integer::I16 => cx.type_ix(16), + Integer::I32 => cx.type_ix(32), + Integer::I64 => cx.type_ix(64), + Integer::I128 => cx.type_ix(128), + }, + Primitive::Float(float) => match float { + Float::F16 => cx.type_f16(), + Float::F32 => cx.type_f32(), + Float::F64 => cx.type_f64(), + Float::F128 => cx.type_f128(), + }, + Primitive::Pointer(_) => cx.type_ptr(), + }; + + assert!(self.size.bytes().is_multiple_of(hint_vector_elem.size(cx).bytes())); + let len = self.size.bytes() / hint_vector_elem.size(cx).bytes(); + cx.type_vector(ty, len) + } } } } diff --git a/compiler/rustc_codegen_llvm/src/base.rs b/compiler/rustc_codegen_llvm/src/base.rs index e1a678594263..a7dec13422f4 100644 --- a/compiler/rustc_codegen_llvm/src/base.rs +++ b/compiler/rustc_codegen_llvm/src/base.rs @@ -65,8 +65,7 @@ pub(crate) fn compile_codegen_unit( let (module, _) = tcx.dep_graph.with_task( dep_node, tcx, - cgu_name, - module_codegen, + || module_codegen(tcx, cgu_name), Some(dep_graph::hash_result), ); let time_to_codegen = start_time.elapsed(); diff --git a/compiler/rustc_codegen_llvm/src/errors.rs b/compiler/rustc_codegen_llvm/src/errors.rs index caec20db4c2d..8921395ab76c 100644 --- a/compiler/rustc_codegen_llvm/src/errors.rs +++ b/compiler/rustc_codegen_llvm/src/errors.rs @@ -211,3 +211,32 @@ pub(crate) struct FixedX18InvalidArch<'a> { "enabling both `-Zpacked-stack` and the `backchain` target feature is incompatible with the default s390x ABI. Switch to s390x-unknown-none-softfloat if you need both attributes" )] pub(crate) struct PackedStackBackchainNeedsSoftfloat; + +#[derive(Diagnostic)] +#[diag( + "intrinsic signature mismatch for `{$name}`: expected signature `{$llvm_fn_ty}`, found `{$rust_fn_ty}`" +)] +pub(crate) struct IntrinsicSignatureMismatch<'a> { + pub name: &'a str, + pub llvm_fn_ty: &'a str, + pub rust_fn_ty: &'a str, + #[primary_span] + pub span: Span, +} + +#[derive(Diagnostic)] +#[diag("unknown LLVM intrinsic `{$name}`")] +pub(crate) struct UnknownIntrinsic<'a> { + pub name: &'a str, + #[primary_span] + pub span: Span, +} + +#[derive(Diagnostic)] +#[diag("intrinsic `{$name}` cannot be used with target arch `{$target_arch}`")] +pub(crate) struct IntrinsicWrongArch<'a> { + pub name: &'a str, + pub target_arch: &'a str, + #[primary_span] + pub span: Span, +} diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs index 3e600914d6f4..b8be612fbe69 100644 --- a/compiler/rustc_codegen_llvm/src/intrinsic.rs +++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs @@ -1,10 +1,9 @@ use std::cmp::Ordering; use std::ffi::c_uint; -use std::{assert_matches, ptr}; +use std::{assert_matches, iter, ptr}; use rustc_abi::{ - Align, BackendRepr, ExternAbi, Float, HasDataLayout, NumScalableVectors, Primitive, Size, - WrappingRange, + Align, BackendRepr, Float, HasDataLayout, NumScalableVectors, Primitive, Size, WrappingRange, }; use rustc_codegen_ssa::base::{compare_simd_types, wants_msvc_seh, wants_wasm_eh}; use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; @@ -21,10 +20,11 @@ use rustc_middle::ty::{self, GenericArgsRef, Instance, SimdAlign, Ty, TyCtxt, TypingEnv}; use rustc_middle::{bug, span_bug}; use rustc_session::config::CrateType; +use rustc_session::lint::builtin::DEPRECATED_LLVM_INTRINSIC; use rustc_span::{Span, Symbol, sym}; use rustc_symbol_mangling::{mangle_internal_symbol, symbol_name_for_instance_in_crate}; use rustc_target::callconv::PassMode; -use rustc_target::spec::Os; +use rustc_target::spec::{Arch, Os}; use tracing::debug; use crate::abi::FnAbiLlvmExt; @@ -36,7 +36,8 @@ use crate::context::CodegenCx; use crate::declare::declare_raw_fn; use crate::errors::{ - AutoDiffWithoutEnable, AutoDiffWithoutLto, OffloadWithoutEnable, OffloadWithoutFatLTO, + AutoDiffWithoutEnable, AutoDiffWithoutLto, IntrinsicSignatureMismatch, IntrinsicWrongArch, + OffloadWithoutEnable, OffloadWithoutFatLTO, UnknownIntrinsic, }; use crate::llvm::{self, Type, Value}; use crate::type_of::LayoutLlvmExt; @@ -283,37 +284,47 @@ fn codegen_intrinsic_call( } sym::breakpoint => self.call_intrinsic("llvm.debugtrap", &[], &[]), sym::va_arg => { - match result.layout.backend_repr { - BackendRepr::Scalar(scalar) => { - match scalar.primitive() { - Primitive::Int(..) => { - if self.cx().size_of(result.layout.ty).bytes() < 4 { - // `va_arg` should not be called on an integer type - // less than 4 bytes in length. If it is, promote - // the integer to an `i32` and truncate the result - // back to the smaller type. - let promoted_result = emit_va_arg(self, args[0], tcx.types.i32); - self.trunc(promoted_result, result.layout.llvm_type(self)) - } else { - emit_va_arg(self, args[0], result.layout.ty) - } - } - Primitive::Float(Float::F16) => { - bug!("the va_arg intrinsic does not work with `f16`") - } - Primitive::Float(Float::F64) | Primitive::Pointer(_) => { - emit_va_arg(self, args[0], result.layout.ty) - } - // `va_arg` should never be used with the return type f32. - Primitive::Float(Float::F32) => { - bug!("the va_arg intrinsic does not work with `f32`") - } - Primitive::Float(Float::F128) => { - bug!("the va_arg intrinsic does not work with `f128`") - } + let BackendRepr::Scalar(scalar) = result.layout.backend_repr else { + bug!("the va_arg intrinsic does not support non-scalar types") + }; + + match scalar.primitive() { + Primitive::Pointer(_) => { + // Pointers are always OK. + emit_va_arg(self, args[0], result.layout.ty) + } + Primitive::Int(..) => { + let int_width = self.cx().size_of(result.layout.ty).bits(); + let target_c_int_width = self.cx().sess().target.options.c_int_width; + if int_width < u64::from(target_c_int_width) { + // Smaller integer types are automatically promototed and `va_arg` + // should not be called on them. + bug!( + "va_arg got i{} but needs at least c_int (an i{})", + int_width, + target_c_int_width + ); + } + emit_va_arg(self, args[0], result.layout.ty) + } + Primitive::Float(Float::F16) => { + bug!("the va_arg intrinsic does not support `f16`") + } + Primitive::Float(Float::F32) => { + if self.cx().sess().target.arch == Arch::Avr { + // c_double is actually f32 on avr. + emit_va_arg(self, args[0], result.layout.ty) + } else { + bug!("the va_arg intrinsic does not support `f32` on this target") } } - _ => bug!("the va_arg intrinsic does not work with non-scalar types"), + Primitive::Float(Float::F64) => { + // 64-bit floats are always OK. + emit_va_arg(self, args[0], result.layout.ty) + } + Primitive::Float(Float::F128) => { + bug!("the va_arg intrinsic does not support `f128`") + } } } @@ -606,27 +617,6 @@ fn codegen_intrinsic_call( self.pointercast(val, self.type_ptr()) } - sym::sve_cast => { - let Some((in_cnt, in_elem, in_num_vecs)) = - args[0].layout.ty.scalable_vector_parts(self.cx.tcx) - else { - bug!("input parameter to `sve_cast` was not scalable vector"); - }; - let out_layout = self.layout_of(fn_args.type_at(1)); - let Some((out_cnt, out_elem, out_num_vecs)) = - out_layout.ty.scalable_vector_parts(self.cx.tcx) - else { - bug!("output parameter to `sve_cast` was not scalable vector"); - }; - assert_eq!(in_cnt, out_cnt); - assert_eq!(in_num_vecs, out_num_vecs); - let out_llty = self.backend_type(out_layout); - match simd_cast(self, sym::simd_cast, args, out_llty, in_elem, out_elem) { - Some(val) => val, - _ => bug!("could not cast scalable vectors"), - } - } - sym::sve_tuple_create2 => { assert_matches!( self.layout_of(fn_args.type_at(0)).backend_repr, @@ -818,7 +808,7 @@ fn codegen_llvm_intrinsic_call( &mut self, instance: ty::Instance<'tcx>, args: &[OperandRef<'tcx, Self::Value>], - is_cleanup: bool, + _is_cleanup: bool, ) -> Self::Value { let tcx = self.tcx(); @@ -829,7 +819,7 @@ fn codegen_llvm_intrinsic_call( } _ => unreachable!(), }; - assert!(!fn_sig.c_variadic); + assert!(!fn_sig.c_variadic()); let ret_layout = self.layout_of(fn_sig.output()); let llreturn_ty = if ret_layout.is_zst() { @@ -847,42 +837,29 @@ fn codegen_llvm_intrinsic_call( llargument_tys.push(arg_layout.immediate_llvm_type(self)); } - let fn_ty = self.type_func(&llargument_tys, llreturn_ty); - let fn_ptr = if let Some(&llfn) = self.intrinsic_instances.borrow().get(&instance) { llfn } else { let sym = tcx.symbol_name(instance).name; - // FIXME use get_intrinsic let llfn = if let Some(llfn) = self.get_declared_value(sym) { llfn } else { - // Function addresses in Rust are never significant, allowing functions to - // be merged. - let llfn = declare_raw_fn( - self, - sym, - llvm::CCallConv, - llvm::UnnamedAddr::Global, - llvm::Visibility::Default, - fn_ty, - ); - - llfn + intrinsic_fn(self, sym, llreturn_ty, llargument_tys, instance) }; self.intrinsic_instances.borrow_mut().insert(instance, llfn); llfn }; + let fn_ty = self.get_type_of_global(fn_ptr); let mut llargs = vec![]; for arg in args { match arg.val { OperandValue::ZeroSized => {} - OperandValue::Immediate(_) => llargs.push(arg.immediate()), + OperandValue::Immediate(a) => llargs.push(a), OperandValue::Pair(a, b) => { llargs.push(a); llargs.push(b); @@ -908,24 +885,38 @@ fn codegen_llvm_intrinsic_call( } debug!("call intrinsic {:?} with args ({:?})", instance, llargs); - let args = self.check_call("call", fn_ty, fn_ptr, &llargs); + + for (dest_ty, arg) in iter::zip(self.func_params_types(fn_ty), &mut llargs) { + let src_ty = self.val_ty(arg); + assert!( + can_autocast(self, src_ty, dest_ty), + "Cannot match `{dest_ty:?}` (expected) with {src_ty:?} (found) in `{fn_ptr:?}" + ); + + *arg = autocast(self, arg, src_ty, dest_ty); + } + let llret = unsafe { llvm::LLVMBuildCallWithOperandBundles( self.llbuilder, fn_ty, fn_ptr, - args.as_ptr() as *const &llvm::Value, - args.len() as c_uint, + llargs.as_ptr(), + llargs.len() as c_uint, ptr::dangling(), 0, c"".as_ptr(), ) }; - if is_cleanup { - self.apply_attrs_to_cleanup_callsite(llret); - } - llret + let src_ty = self.val_ty(llret); + let dest_ty = llreturn_ty; + assert!( + can_autocast(self, dest_ty, src_ty), + "Cannot match `{src_ty:?}` (expected) with `{dest_ty:?}` (found) in `{fn_ptr:?}`" + ); + + autocast(self, llret, src_ty, dest_ty) } fn abort(&mut self) { @@ -976,6 +967,239 @@ fn va_end(&mut self, va_list: &'ll Value) -> &'ll Value { } } +fn llvm_arch_for(rust_arch: &Arch) -> Option<&'static str> { + Some(match rust_arch { + Arch::AArch64 | Arch::Arm64EC => "aarch64", + Arch::AmdGpu => "amdgcn", + Arch::Arm => "arm", + Arch::Bpf => "bpf", + Arch::Hexagon => "hexagon", + Arch::LoongArch32 | Arch::LoongArch64 => "loongarch", + Arch::Mips | Arch::Mips32r6 | Arch::Mips64 | Arch::Mips64r6 => "mips", + Arch::Nvptx64 => "nvvm", + Arch::PowerPC | Arch::PowerPC64 => "ppc", + Arch::RiscV32 | Arch::RiscV64 => "riscv", + Arch::S390x => "s390", + Arch::SpirV => "spv", + Arch::Wasm32 | Arch::Wasm64 => "wasm", + Arch::X86 | Arch::X86_64 => "x86", + _ => return None, // fallback for unknown archs + }) +} + +fn can_autocast<'ll>(cx: &CodegenCx<'ll, '_>, rust_ty: &'ll Type, llvm_ty: &'ll Type) -> bool { + if rust_ty == llvm_ty { + return true; + } + + match cx.type_kind(llvm_ty) { + // Some LLVM intrinsics return **non-packed** structs, but they can't be mimicked from Rust + // due to auto field-alignment in non-packed structs (packed structs are represented in LLVM + // as, well, packed structs, so they won't match with those either) + TypeKind::Struct if cx.type_kind(rust_ty) == TypeKind::Struct => { + let rust_element_tys = cx.struct_element_types(rust_ty); + let llvm_element_tys = cx.struct_element_types(llvm_ty); + + if rust_element_tys.len() != llvm_element_tys.len() { + return false; + } + + iter::zip(rust_element_tys, llvm_element_tys).all( + |(rust_element_ty, llvm_element_ty)| { + can_autocast(cx, rust_element_ty, llvm_element_ty) + }, + ) + } + TypeKind::Vector => { + let llvm_element_ty = cx.element_type(llvm_ty); + let element_count = cx.vector_length(llvm_ty) as u64; + + if llvm_element_ty == cx.type_bf16() { + rust_ty == cx.type_vector(cx.type_i16(), element_count) + } else if llvm_element_ty == cx.type_i1() { + let int_width = element_count.next_power_of_two().max(8); + rust_ty == cx.type_ix(int_width) + } else { + false + } + } + TypeKind::BFloat => rust_ty == cx.type_i16(), + _ => false, + } +} + +fn autocast<'ll>( + bx: &mut Builder<'_, 'll, '_>, + val: &'ll Value, + src_ty: &'ll Type, + dest_ty: &'ll Type, +) -> &'ll Value { + if src_ty == dest_ty { + return val; + } + match (bx.type_kind(src_ty), bx.type_kind(dest_ty)) { + // re-pack structs + (TypeKind::Struct, TypeKind::Struct) => { + let mut ret = bx.const_poison(dest_ty); + for (idx, (src_element_ty, dest_element_ty)) in + iter::zip(bx.struct_element_types(src_ty), bx.struct_element_types(dest_ty)) + .enumerate() + { + let elt = bx.extract_value(val, idx as u64); + let casted_elt = autocast(bx, elt, src_element_ty, dest_element_ty); + ret = bx.insert_value(ret, casted_elt, idx as u64); + } + ret + } + // cast from the i1xN vector type to the primitive type + (TypeKind::Vector, TypeKind::Integer) if bx.element_type(src_ty) == bx.type_i1() => { + let vector_length = bx.vector_length(src_ty) as u64; + let int_width = vector_length.next_power_of_two().max(8); + + let val = if vector_length == int_width { + val + } else { + // zero-extends vector + let shuffle_indices = match vector_length { + 0 => unreachable!("zero length vectors are not allowed"), + 1 => vec![0, 1, 1, 1, 1, 1, 1, 1], + 2 => vec![0, 1, 2, 2, 2, 2, 2, 2], + 3 => vec![0, 1, 2, 3, 3, 3, 3, 3], + 4.. => (0..int_width as i32).collect(), + }; + let shuffle_mask = + shuffle_indices.into_iter().map(|i| bx.const_i32(i)).collect::>(); + bx.shuffle_vector(val, bx.const_null(src_ty), bx.const_vector(&shuffle_mask)) + }; + bx.bitcast(val, dest_ty) + } + // cast from the primitive type to the i1xN vector type + (TypeKind::Integer, TypeKind::Vector) if bx.element_type(dest_ty) == bx.type_i1() => { + let vector_length = bx.vector_length(dest_ty) as u64; + let int_width = vector_length.next_power_of_two().max(8); + + let intermediate_ty = bx.type_vector(bx.type_i1(), int_width); + let intermediate = bx.bitcast(val, intermediate_ty); + + if vector_length == int_width { + intermediate + } else { + let shuffle_mask: Vec<_> = + (0..vector_length).map(|i| bx.const_i32(i as i32)).collect(); + bx.shuffle_vector( + intermediate, + bx.const_poison(intermediate_ty), + bx.const_vector(&shuffle_mask), + ) + } + } + _ => bx.bitcast(val, dest_ty), // for `bf16(xN)` <-> `u16(xN)` + } +} + +fn intrinsic_fn<'ll, 'tcx>( + bx: &Builder<'_, 'll, 'tcx>, + name: &str, + rust_return_ty: &'ll Type, + rust_argument_tys: Vec<&'ll Type>, + instance: ty::Instance<'tcx>, +) -> &'ll Value { + let tcx = bx.tcx; + + let rust_fn_ty = bx.type_func(&rust_argument_tys, rust_return_ty); + + let intrinsic = llvm::Intrinsic::lookup(name.as_bytes()); + + if let Some(intrinsic) = intrinsic + && intrinsic.is_target_specific() + { + let (llvm_arch, _) = name[5..].split_once('.').unwrap(); + let rust_arch = &tcx.sess.target.arch; + + if let Some(correct_llvm_arch) = llvm_arch_for(rust_arch) + && llvm_arch != correct_llvm_arch + { + tcx.dcx().emit_fatal(IntrinsicWrongArch { + name, + target_arch: rust_arch.desc(), + span: tcx.def_span(instance.def_id()), + }); + } + } + + if let Some(intrinsic) = intrinsic + && !intrinsic.is_overloaded() + { + // FIXME: also do this for overloaded intrinsics + let llfn = intrinsic.get_declaration(bx.llmod, &[]); + let llvm_fn_ty = bx.get_type_of_global(llfn); + + let llvm_return_ty = bx.get_return_type(llvm_fn_ty); + let llvm_argument_tys = bx.func_params_types(llvm_fn_ty); + let llvm_is_variadic = bx.func_is_variadic(llvm_fn_ty); + + let is_correct_signature = !llvm_is_variadic + && rust_argument_tys.len() == llvm_argument_tys.len() + && iter::once((rust_return_ty, llvm_return_ty)) + .chain(iter::zip(rust_argument_tys, llvm_argument_tys)) + .all(|(rust_ty, llvm_ty)| can_autocast(bx, rust_ty, llvm_ty)); + + if !is_correct_signature { + tcx.dcx().emit_fatal(IntrinsicSignatureMismatch { + name, + llvm_fn_ty: &format!("{llvm_fn_ty:?}"), + rust_fn_ty: &format!("{rust_fn_ty:?}"), + span: tcx.def_span(instance.def_id()), + }); + } + + return llfn; + } + + // Function addresses in Rust are never significant, allowing functions to be merged. + let llfn = declare_raw_fn( + bx, + name, + llvm::CCallConv, + llvm::UnnamedAddr::Global, + llvm::Visibility::Default, + rust_fn_ty, + ); + + if intrinsic.is_none() { + let mut new_llfn = None; + let can_upgrade = unsafe { llvm::LLVMRustUpgradeIntrinsicFunction(llfn, &mut new_llfn) }; + + if !can_upgrade { + // This is either plain wrong, or this can be caused by incompatible LLVM versions + tcx.dcx().emit_fatal(UnknownIntrinsic { name, span: tcx.def_span(instance.def_id()) }); + } else if let Some(def_id) = instance.def_id().as_local() { + // we can emit diagnostics only for local crates + let hir_id = tcx.local_def_id_to_hir_id(def_id); + + // not all intrinsics are upgraded to some other intrinsics, most are upgraded to instruction sequences + let msg = if let Some(new_llfn) = new_llfn { + format!( + "using deprecated intrinsic `{name}`, `{}` can be used instead", + str::from_utf8(&llvm::get_value_name(new_llfn)).unwrap() + ) + } else { + format!("using deprecated intrinsic `{name}`") + }; + + tcx.emit_node_lint( + DEPRECATED_LLVM_INTRINSIC, + hir_id, + rustc_errors::DiagDecorator(|d| { + d.primary_message(msg).span(tcx.hir_span(hir_id)); + }), + ); + } + } + + llfn +} + fn catch_unwind_intrinsic<'ll, 'tcx>( bx: &mut Builder<'_, 'll, 'tcx>, try_func: &'ll Value, @@ -1415,32 +1639,18 @@ fn get_rust_try_fn<'a, 'll, 'tcx>( // `unsafe fn(*mut i8) -> ()` let try_fn_ty = Ty::new_fn_ptr( tcx, - ty::Binder::dummy(tcx.mk_fn_sig( - [i8p], - tcx.types.unit, - false, - hir::Safety::Unsafe, - ExternAbi::Rust, - )), + ty::Binder::dummy(tcx.mk_fn_sig_rust_abi([i8p], tcx.types.unit, hir::Safety::Unsafe)), ); // `unsafe fn(*mut i8, *mut i8) -> ()` let catch_fn_ty = Ty::new_fn_ptr( tcx, - ty::Binder::dummy(tcx.mk_fn_sig( - [i8p, i8p], - tcx.types.unit, - false, - hir::Safety::Unsafe, - ExternAbi::Rust, - )), + ty::Binder::dummy(tcx.mk_fn_sig_rust_abi([i8p, i8p], tcx.types.unit, hir::Safety::Unsafe)), ); // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32` - let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig( + let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig_rust_abi( [try_fn_ty, i8p, catch_fn_ty], tcx.types.i32, - false, hir::Safety::Unsafe, - ExternAbi::Rust, )); let rust_try = gen_fn(cx, "__rust_try", rust_fn_sig, codegen); cx.rust_try_fn.set(Some(rust_try)); @@ -1668,6 +1878,23 @@ macro_rules! require_simd { }}; } + macro_rules! require_simd_or_scalable { + ($ty: expr, $variant:ident) => {{ + require!( + $ty.is_simd() || $ty.is_scalable_vector(), + InvalidMonomorphization::$variant { span, name, ty: $ty } + ); + if $ty.is_simd() { + let (len, ty) = $ty.simd_size_and_type(bx.tcx()); + (len, ty, None) + } else { + let (count, ty, num_vecs) = + $ty.scalable_vector_parts(bx.tcx()).expect("`is_scalable_vector` was wrong"); + (count as u64, ty, Some(num_vecs)) + } + }}; + } + /// Returns the bitwidth of the `$ty` argument if it is an `Int` or `Uint` type. macro_rules! require_int_or_uint_ty { ($ty: expr, $diag: expr) => { @@ -1787,8 +2014,19 @@ fn vector_mask_to_bitmask<'a, 'll, 'tcx>( return Ok(splat); } - // every intrinsic below takes a SIMD vector as its first argument - let (in_len, in_elem) = require_simd!(args[0].layout.ty, SimdInput); + let supports_scalable = match name { + sym::simd_cast | sym::simd_select => true, + _ => false, + }; + + // Every intrinsic below takes a SIMD vector as its first argument. Some intrinsics also accept + // scalable vectors. `require_simd_or_scalable` is used regardless as it'll do the right thing + // for non-scalable vectors, and an additional check to prohibit scalable vectors for those + // intrinsics that do not support them is added. + if !supports_scalable { + let _ = require_simd!(args[0].layout.ty, SimdInput); + } + let (in_len, in_elem, in_num_vecs) = require_simd_or_scalable!(args[0].layout.ty, SimdInput); let in_ty = args[0].layout.ty; let comparison = match name { @@ -1977,7 +2215,7 @@ fn vector_mask_to_bitmask<'a, 'll, 'tcx>( if name == sym::simd_select { let m_elem_ty = in_elem; let m_len = in_len; - let (v_len, _) = require_simd!(args[1].layout.ty, SimdArgument); + let (v_len, _, _) = require_simd_or_scalable!(args[1].layout.ty, SimdArgument); require!( m_len == v_len, InvalidMonomorphization::MismatchedLengths { span, name, m_len, v_len } @@ -2781,7 +3019,7 @@ macro_rules! bitwise_red { } if name == sym::simd_cast || name == sym::simd_as { - let (out_len, out_elem) = require_simd!(ret_ty, SimdReturn); + let (out_len, out_elem, out_num_vecs) = require_simd_or_scalable!(ret_ty, SimdReturn); require!( in_len == out_len, InvalidMonomorphization::ReturnLengthInputType { @@ -2793,9 +3031,99 @@ macro_rules! bitwise_red { out_len } ); - match simd_cast(bx, name, args, llret_ty, in_elem, out_elem) { - Some(val) => return Ok(val), - None => return_error!(InvalidMonomorphization::UnsupportedCast { + require!( + in_num_vecs == out_num_vecs, + InvalidMonomorphization::ReturnNumVecsInputType { + span, + name, + in_num_vecs: in_num_vecs.unwrap_or(NumScalableVectors(1)), + in_ty, + ret_ty, + out_num_vecs: out_num_vecs.unwrap_or(NumScalableVectors(1)) + } + ); + + // Casting cares about nominal type, not just structural type + if in_elem == out_elem { + return Ok(args[0].immediate()); + } + + #[derive(Copy, Clone)] + enum Sign { + Unsigned, + Signed, + } + use Sign::*; + + enum Style { + Float, + Int(Sign), + Unsupported, + } + + let (in_style, in_width) = match in_elem.kind() { + // vectors of pointer-sized integers should've been + // disallowed before here, so this unwrap is safe. + ty::Int(i) => ( + Style::Int(Signed), + i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Uint(u) => ( + Style::Int(Unsigned), + u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Float(f) => (Style::Float, f.bit_width()), + _ => (Style::Unsupported, 0), + }; + let (out_style, out_width) = match out_elem.kind() { + ty::Int(i) => ( + Style::Int(Signed), + i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Uint(u) => ( + Style::Int(Unsigned), + u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Float(f) => (Style::Float, f.bit_width()), + _ => (Style::Unsupported, 0), + }; + + match (in_style, out_style) { + (Style::Int(sign), Style::Int(_)) => { + return Ok(match in_width.cmp(&out_width) { + Ordering::Greater => bx.trunc(args[0].immediate(), llret_ty), + Ordering::Equal => args[0].immediate(), + Ordering::Less => match sign { + Sign::Signed => bx.sext(args[0].immediate(), llret_ty), + Sign::Unsigned => bx.zext(args[0].immediate(), llret_ty), + }, + }); + } + (Style::Int(Sign::Signed), Style::Float) => { + return Ok(bx.sitofp(args[0].immediate(), llret_ty)); + } + (Style::Int(Sign::Unsigned), Style::Float) => { + return Ok(bx.uitofp(args[0].immediate(), llret_ty)); + } + (Style::Float, Style::Int(sign)) => { + return Ok(match (sign, name == sym::simd_as) { + (Sign::Unsigned, false) => bx.fptoui(args[0].immediate(), llret_ty), + (Sign::Signed, false) => bx.fptosi(args[0].immediate(), llret_ty), + (_, true) => bx.cast_float_to_int( + matches!(sign, Sign::Signed), + args[0].immediate(), + llret_ty, + ), + }); + } + (Style::Float, Style::Float) => { + return Ok(match in_width.cmp(&out_width) { + Ordering::Greater => bx.fptrunc(args[0].immediate(), llret_ty), + Ordering::Equal => args[0].immediate(), + Ordering::Less => bx.fpext(args[0].immediate(), llret_ty), + }); + } + _ => return_error!(InvalidMonomorphization::UnsupportedCast { span, name, in_ty, @@ -2977,86 +3305,3 @@ macro_rules! arith_unary { span_bug!(span, "unknown SIMD intrinsic"); } - -/// Implementation of `core::intrinsics::simd_cast`, re-used by `core::scalable::sve_cast`. -fn simd_cast<'ll, 'tcx>( - bx: &mut Builder<'_, 'll, 'tcx>, - name: Symbol, - args: &[OperandRef<'tcx, &'ll Value>], - llret_ty: &'ll Type, - in_elem: Ty<'tcx>, - out_elem: Ty<'tcx>, -) -> Option<&'ll Value> { - // Casting cares about nominal type, not just structural type - if in_elem == out_elem { - return Some(args[0].immediate()); - } - - #[derive(Copy, Clone)] - enum Sign { - Unsigned, - Signed, - } - use Sign::*; - - enum Style { - Float, - Int(Sign), - Unsupported, - } - - let (in_style, in_width) = match in_elem.kind() { - // vectors of pointer-sized integers should've been - // disallowed before here, so this unwrap is safe. - ty::Int(i) => ( - Style::Int(Signed), - i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Uint(u) => ( - Style::Int(Unsigned), - u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Float(f) => (Style::Float, f.bit_width()), - _ => (Style::Unsupported, 0), - }; - let (out_style, out_width) = match out_elem.kind() { - ty::Int(i) => ( - Style::Int(Signed), - i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Uint(u) => ( - Style::Int(Unsigned), - u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Float(f) => (Style::Float, f.bit_width()), - _ => (Style::Unsupported, 0), - }; - - match (in_style, out_style) { - (Style::Int(sign), Style::Int(_)) => Some(match in_width.cmp(&out_width) { - Ordering::Greater => bx.trunc(args[0].immediate(), llret_ty), - Ordering::Equal => args[0].immediate(), - Ordering::Less => match sign { - Sign::Signed => bx.sext(args[0].immediate(), llret_ty), - Sign::Unsigned => bx.zext(args[0].immediate(), llret_ty), - }, - }), - (Style::Int(Sign::Signed), Style::Float) => Some(bx.sitofp(args[0].immediate(), llret_ty)), - (Style::Int(Sign::Unsigned), Style::Float) => { - Some(bx.uitofp(args[0].immediate(), llret_ty)) - } - (Style::Float, Style::Int(sign)) => Some(match (sign, name == sym::simd_as) { - (Sign::Unsigned, false) => bx.fptoui(args[0].immediate(), llret_ty), - (Sign::Signed, false) => bx.fptosi(args[0].immediate(), llret_ty), - (_, true) => { - bx.cast_float_to_int(matches!(sign, Sign::Signed), args[0].immediate(), llret_ty) - } - }), - (Style::Float, Style::Float) => Some(match in_width.cmp(&out_width) { - Ordering::Greater => bx.fptrunc(args[0].immediate(), llret_ty), - Ordering::Equal => args[0].immediate(), - Ordering::Less => bx.fpext(args[0].immediate(), llret_ty), - }), - _ => None, - } -} diff --git a/compiler/rustc_codegen_llvm/src/llvm/enzyme_ffi.rs b/compiler/rustc_codegen_llvm/src/llvm/enzyme_ffi.rs index 67fbc0f53adc..195e050a9b65 100644 --- a/compiler/rustc_codegen_llvm/src/llvm/enzyme_ffi.rs +++ b/compiler/rustc_codegen_llvm/src/llvm/enzyme_ffi.rs @@ -73,7 +73,6 @@ pub(crate) fn LLVMRustGetFunctionCall( pub(crate) fn LLVMDumpModule(M: &Module); pub(crate) fn LLVMDumpValue(V: &Value); pub(crate) fn LLVMGetFunctionCallConv(F: &Value) -> c_uint; - pub(crate) fn LLVMGetReturnType(T: &Type) -> &Type; pub(crate) fn LLVMGetParams(Fnc: &Value, params: *mut &Value); pub(crate) fn LLVMGetNamedFunction(M: &Module, Name: *const c_char) -> Option<&Value>; } diff --git a/compiler/rustc_codegen_llvm/src/llvm/ffi.rs b/compiler/rustc_codegen_llvm/src/llvm/ffi.rs index bc24f1692fcf..525d1dbe9d0d 100644 --- a/compiler/rustc_codegen_llvm/src/llvm/ffi.rs +++ b/compiler/rustc_codegen_llvm/src/llvm/ffi.rs @@ -921,6 +921,9 @@ pub(crate) fn LLVMGetInlineAsm<'ll>( pub(crate) fn LLVMDoubleTypeInContext(C: &Context) -> &Type; pub(crate) fn LLVMFP128TypeInContext(C: &Context) -> &Type; + // Operations on non-IEEE real types + pub(crate) fn LLVMBFloatTypeInContext(C: &Context) -> &Type; + // Operations on function types pub(crate) fn LLVMFunctionType<'a>( ReturnType: &'a Type, @@ -930,6 +933,8 @@ pub(crate) fn LLVMFunctionType<'a>( ) -> &'a Type; pub(crate) fn LLVMCountParamTypes(FunctionTy: &Type) -> c_uint; pub(crate) fn LLVMGetParamTypes<'a>(FunctionTy: &'a Type, Dest: *mut &'a Type); + pub(crate) fn LLVMGetReturnType(FunctionTy: &Type) -> &Type; + pub(crate) fn LLVMIsFunctionVarArg(FunctionTy: &Type) -> Bool; // Operations on struct types pub(crate) fn LLVMStructTypeInContext<'a>( @@ -1084,12 +1089,18 @@ pub(crate) fn LLVMAddFunction<'a>( // Operations about llvm intrinsics pub(crate) fn LLVMLookupIntrinsicID(Name: *const c_char, NameLen: size_t) -> c_uint; + pub(crate) fn LLVMIntrinsicIsOverloaded(ID: NonZero) -> Bool; pub(crate) fn LLVMGetIntrinsicDeclaration<'a>( Mod: &'a Module, ID: NonZero, ParamTypes: *const &'a Type, ParamCount: size_t, ) -> &'a Value; + pub(crate) fn LLVMRustUpgradeIntrinsicFunction<'a>( + Fn: &'a Value, + NewFn: &mut Option<&'a Value>, + ) -> bool; + pub(crate) fn LLVMRustIsTargetIntrinsic(ID: NonZero) -> bool; // Operations on parameters pub(crate) fn LLVMIsAArgument(Val: &Value) -> Option<&Value>; @@ -1605,6 +1616,9 @@ pub(crate) fn LLVMStructSetBody<'a>( Packed: Bool, ); + pub(crate) fn LLVMCountStructElementTypes(StructTy: &Type) -> c_uint; + pub(crate) fn LLVMGetStructElementTypes<'a>(StructTy: &'a Type, Dest: *mut &'a Type); + pub(crate) safe fn LLVMMetadataAsValue<'a>(C: &'a Context, MD: &'a Metadata) -> &'a Value; pub(crate) safe fn LLVMSetUnnamedAddress(Global: &Value, UnnamedAddr: UnnamedAddr); diff --git a/compiler/rustc_codegen_llvm/src/llvm/mod.rs b/compiler/rustc_codegen_llvm/src/llvm/mod.rs index 2871326b28b5..2ec19b1795b5 100644 --- a/compiler/rustc_codegen_llvm/src/llvm/mod.rs +++ b/compiler/rustc_codegen_llvm/src/llvm/mod.rs @@ -323,6 +323,14 @@ pub(crate) fn lookup(name: &[u8]) -> Option { NonZero::new(id).map(|id| Self { id }) } + pub(crate) fn is_overloaded(self) -> bool { + unsafe { LLVMIntrinsicIsOverloaded(self.id).is_true() } + } + + pub(crate) fn is_target_specific(self) -> bool { + unsafe { LLVMRustIsTargetIntrinsic(self.id) } + } + pub(crate) fn get_declaration<'ll>( self, llmod: &'ll Module, diff --git a/compiler/rustc_codegen_llvm/src/llvm_util.rs b/compiler/rustc_codegen_llvm/src/llvm_util.rs index 3e0a6efde025..180559d28d84 100644 --- a/compiler/rustc_codegen_llvm/src/llvm_util.rs +++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs @@ -630,6 +630,7 @@ fn llvm_features_by_flags(sess: &Session, features: &mut Vec) { } target_features::retpoline_features_by_flags(sess, features); + target_features::sanitizer_features_by_flags(sess, features); // -Zfixed-x18 if sess.opts.unstable_opts.fixed_x18 { diff --git a/compiler/rustc_codegen_llvm/src/mono_item.rs b/compiler/rustc_codegen_llvm/src/mono_item.rs index 0783282bc6e5..2c0a6ff01018 100644 --- a/compiler/rustc_codegen_llvm/src/mono_item.rs +++ b/compiler/rustc_codegen_llvm/src/mono_item.rs @@ -135,7 +135,8 @@ fn add_static_aliases(&self, aliasee: &llvm::Value, aliases: &[(DefId, Linkage, let ty = self.get_type_of_global(aliasee); for (alias, linkage, visibility) in aliases { - let symbol_name = self.tcx.symbol_name(Instance::mono(self.tcx, *alias)); + let instance = Instance::mono(self.tcx, *alias); + let symbol_name = self.tcx.symbol_name(instance); tracing::debug!("STATIC ALIAS: {alias:?} {linkage:?} {visibility:?}"); let lldecl = llvm::add_alias( @@ -145,6 +146,13 @@ fn add_static_aliases(&self, aliasee: &llvm::Value, aliases: &[(DefId, Linkage, aliasee, &CString::new(symbol_name.name).unwrap(), ); + // Add the alias name to the set of cached items, so there is no duplicate + // instance added to it during the normal `external static` codegen + let prev_entry = self.instances.borrow_mut().insert(instance, lldecl); + + // If there already was a previous entry, then `add_static_aliases` was called multiple times for the same `alias` + // which would result in incorrect codegen + assert!(prev_entry.is_none(), "An instance was already present for {instance:?}"); llvm::set_visibility(lldecl, base::visibility_to_llvm(*visibility)); llvm::set_linkage(lldecl, base::linkage_to_llvm(*linkage)); diff --git a/compiler/rustc_codegen_llvm/src/type_.rs b/compiler/rustc_codegen_llvm/src/type_.rs index 2026b06d104d..796f3d9ef60b 100644 --- a/compiler/rustc_codegen_llvm/src/type_.rs +++ b/compiler/rustc_codegen_llvm/src/type_.rs @@ -77,6 +77,10 @@ pub(crate) fn add_func(&self, name: &str, ty: &'ll Type) -> &'ll Value { unsafe { llvm::LLVMAddFunction(self.llmod(), name.as_ptr(), ty) } } + pub(crate) fn get_return_type(&self, ty: &'ll Type) -> &'ll Type { + unsafe { llvm::LLVMGetReturnType(ty) } + } + pub(crate) fn func_params_types(&self, ty: &'ll Type) -> Vec<&'ll Type> { unsafe { let n_args = llvm::LLVMCountParamTypes(ty) as usize; @@ -86,6 +90,20 @@ pub(crate) fn func_params_types(&self, ty: &'ll Type) -> Vec<&'ll Type> { args } } + + pub(crate) fn func_is_variadic(&self, ty: &'ll Type) -> bool { + unsafe { llvm::LLVMIsFunctionVarArg(ty).is_true() } + } + + pub(crate) fn struct_element_types(&self, ty: &'ll Type) -> Vec<&'ll Type> { + unsafe { + let n_args = llvm::LLVMCountStructElementTypes(ty) as usize; + let mut args = Vec::with_capacity(n_args); + llvm::LLVMGetStructElementTypes(ty, args.as_mut_ptr()); + args.set_len(n_args); + args + } + } } impl<'ll, 'tcx> CodegenCx<'ll, 'tcx> { pub(crate) fn type_bool(&self) -> &'ll Type { @@ -165,6 +183,10 @@ pub(crate) fn type_struct(&self, els: &[&'ll Type], packed: bool) -> &'ll Type { ) } } + + pub(crate) fn type_bf16(&self) -> &'ll Type { + unsafe { llvm::LLVMBFloatTypeInContext(self.llcx()) } + } } impl<'ll, CX: Borrow>> BaseTypeCodegenMethods for GenericCx<'ll, CX> { diff --git a/compiler/rustc_codegen_ssa/src/base.rs b/compiler/rustc_codegen_ssa/src/base.rs index f291aa846ecc..82e51dc9b0a6 100644 --- a/compiler/rustc_codegen_ssa/src/base.rs +++ b/compiler/rustc_codegen_ssa/src/base.rs @@ -27,7 +27,7 @@ use rustc_middle::mono::{CodegenUnit, CodegenUnitNameBuilder, MonoItem, MonoItemPartitions}; use rustc_middle::query::Providers; use rustc_middle::ty::layout::{HasTyCtxt, HasTypingEnv, LayoutOf, TyAndLayout}; -use rustc_middle::ty::{self, Instance, Ty, TyCtxt}; +use rustc_middle::ty::{self, Instance, PatternKind, Ty, TyCtxt}; use rustc_middle::{bug, span_bug}; use rustc_session::Session; use rustc_session::config::{self, CrateType, EntryFnType}; @@ -273,6 +273,13 @@ pub(crate) fn coerce_unsized_into<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>>( let src_ty = src.layout.ty; let dst_ty = dst.layout.ty; match (src_ty.kind(), dst_ty.kind()) { + (&ty::Pat(s, sp), &ty::Pat(d, dp)) + if let (PatternKind::NotNull, PatternKind::NotNull) = (*sp, *dp) => + { + let src = src.project_type(bx, s); + let dst = dst.project_type(bx, d); + coerce_unsized_into(bx, src, dst) + } (&ty::Ref(..), &ty::Ref(..) | &ty::RawPtr(..)) | (&ty::RawPtr(..), &ty::RawPtr(..)) => { let (base, info) = match bx.load_operand(src).val { OperandValue::Pair(base, info) => unsize_ptr(bx, base, src_ty, dst_ty, Some(info)), diff --git a/compiler/rustc_codegen_ssa/src/debuginfo/type_names.rs b/compiler/rustc_codegen_ssa/src/debuginfo/type_names.rs index d207cdca4d4b..17948e0a69e4 100644 --- a/compiler/rustc_codegen_ssa/src/debuginfo/type_names.rs +++ b/compiler/rustc_codegen_ssa/src/debuginfo/type_names.rs @@ -364,10 +364,10 @@ fn push_debuginfo_type_name<'tcx>( } output.push_str(" (*)("); } else { - output.push_str(sig.safety.prefix_str()); + output.push_str(sig.safety().prefix_str()); - if sig.abi != rustc_abi::ExternAbi::Rust { - let _ = write!(output, "extern {} ", sig.abi); + if sig.abi() != rustc_abi::ExternAbi::Rust { + let _ = write!(output, "extern {} ", sig.abi()); } output.push_str("fn("); @@ -381,7 +381,7 @@ fn push_debuginfo_type_name<'tcx>( pop_arg_separator(output); } - if sig.c_variadic { + if sig.c_variadic() { if !sig.inputs().is_empty() { output.push_str(", ..."); } else { diff --git a/compiler/rustc_codegen_ssa/src/errors.rs b/compiler/rustc_codegen_ssa/src/errors.rs index cec84f60a7b0..f1112510af0f 100644 --- a/compiler/rustc_codegen_ssa/src/errors.rs +++ b/compiler/rustc_codegen_ssa/src/errors.rs @@ -6,6 +6,7 @@ use std::path::{Path, PathBuf}; use std::process::ExitStatus; +use rustc_abi::NumScalableVectors; use rustc_errors::codes::*; use rustc_errors::{ Diag, DiagArgValue, DiagCtxtHandle, DiagSymbolList, Diagnostic, EmissionGuarantee, IntoDiagArg, @@ -809,6 +810,17 @@ pub enum InvalidMonomorphization<'tcx> { out_len: u64, }, + #[diag("invalid monomorphization of `{$name}` intrinsic: expected return type with {$in_num_vecs} vectors (same as input type `{$in_ty}`), found `{$ret_ty}` with length {$out_num_vecs}", code = E0511)] + ReturnNumVecsInputType { + #[primary_span] + span: Span, + name: Symbol, + in_num_vecs: NumScalableVectors, + in_ty: Ty<'tcx>, + ret_ty: Ty<'tcx>, + out_num_vecs: NumScalableVectors, + }, + #[diag("invalid monomorphization of `{$name}` intrinsic: expected second argument with length {$in_len} (same as input type `{$in_ty}`), found `{$arg_ty}` with length {$out_len}", code = E0511)] SecondArgumentLength { #[primary_span] @@ -1057,7 +1069,7 @@ pub(crate) struct TargetFeatureSafeTrait { #[derive(Diagnostic)] #[diag("target feature `{$feature}` cannot be enabled with `#[target_feature]`: {$reason}")] -pub struct ForbiddenTargetFeatureAttr<'a> { +pub(crate) struct ForbiddenTargetFeatureAttr<'a> { #[primary_span] pub span: Span, pub feature: &'a str, @@ -1199,7 +1211,7 @@ pub(crate) struct ForbiddenCTargetFeature<'a> { pub reason: &'a str, } -pub struct TargetFeatureDisableOrEnable<'a> { +pub(crate) struct TargetFeatureDisableOrEnable<'a> { pub features: &'a [&'a str], pub span: Option, pub missing_features: Option, @@ -1207,7 +1219,7 @@ pub struct TargetFeatureDisableOrEnable<'a> { #[derive(Subdiagnostic)] #[help("add the missing features in a `target_feature` attribute")] -pub struct MissingFeatures; +pub(crate) struct MissingFeatures; impl Diagnostic<'_, G> for TargetFeatureDisableOrEnable<'_> { fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { diff --git a/compiler/rustc_codegen_ssa/src/lib.rs b/compiler/rustc_codegen_ssa/src/lib.rs index ced4b59c4f0c..1c266382d027 100644 --- a/compiler/rustc_codegen_ssa/src/lib.rs +++ b/compiler/rustc_codegen_ssa/src/lib.rs @@ -256,7 +256,7 @@ pub struct CompiledModules { pub allocator_module: Option, } -pub enum CodegenErrors { +pub enum CodegenError { WrongFileType, EmptyVersionNumber, EncodingVersionMismatch { version_array: String, rlink_version: u32 }, @@ -317,32 +317,32 @@ pub fn serialize_rlink( pub fn deserialize_rlink( sess: &Session, data: Vec, - ) -> Result<(Self, CrateInfo, EncodedMetadata, OutputFilenames), CodegenErrors> { + ) -> Result<(Self, CrateInfo, EncodedMetadata, OutputFilenames), CodegenError> { // The Decodable machinery is not used here because it panics if the input data is invalid // and because its internal representation may change. if !data.starts_with(RLINK_MAGIC) { - return Err(CodegenErrors::WrongFileType); + return Err(CodegenError::WrongFileType); } let data = &data[RLINK_MAGIC.len()..]; if data.len() < 4 { - return Err(CodegenErrors::EmptyVersionNumber); + return Err(CodegenError::EmptyVersionNumber); } let mut version_array: [u8; 4] = Default::default(); version_array.copy_from_slice(&data[..4]); if u32::from_be_bytes(version_array) != RLINK_VERSION { - return Err(CodegenErrors::EncodingVersionMismatch { + return Err(CodegenError::EncodingVersionMismatch { version_array: String::from_utf8_lossy(&version_array).to_string(), rlink_version: RLINK_VERSION, }); } let Ok(mut decoder) = MemDecoder::new(&data[4..], 0) else { - return Err(CodegenErrors::CorruptFile); + return Err(CodegenError::CorruptFile); }; let rustc_version = decoder.read_str(); if rustc_version != sess.cfg_version { - return Err(CodegenErrors::RustcVersionMismatch { + return Err(CodegenError::RustcVersionMismatch { rustc_version: rustc_version.to_string(), }); } diff --git a/compiler/rustc_codegen_ssa/src/mir/naked_asm.rs b/compiler/rustc_codegen_ssa/src/mir/naked_asm.rs index 7af10dbd042c..bdefacefd20b 100644 --- a/compiler/rustc_codegen_ssa/src/mir/naked_asm.rs +++ b/compiler/rustc_codegen_ssa/src/mir/naked_asm.rs @@ -8,7 +8,7 @@ use rustc_middle::{bug, ty}; use rustc_span::sym; use rustc_target::callconv::{ArgAbi, FnAbi, PassMode}; -use rustc_target::spec::{Arch, BinaryFormat}; +use rustc_target::spec::{Arch, BinaryFormat, Env, Os}; use crate::common; use crate::mir::AsmCodegenMethods; @@ -128,6 +128,8 @@ fn prefix_and_suffix<'tcx>( let is_arm = tcx.sess.target.arch == Arch::Arm; let is_thumb = tcx.sess.unstable_target_features.contains(&sym::thumb_mode); + let function_sections = + tcx.sess.opts.unstable_opts.function_sections.unwrap_or(tcx.sess.target.function_sections); // If we're compiling the compiler-builtins crate, e.g., the equivalent of // compiler-rt, then we want to implicitly compile everything with hidden @@ -218,8 +220,6 @@ fn prefix_and_suffix<'tcx>( let mut end = String::new(); match asm_binary_format { BinaryFormat::Elf => { - let section = link_section.unwrap_or_else(|| format!(".text.{asm_name}")); - let progbits = match is_arm { true => "%progbits", false => "@progbits", @@ -230,7 +230,13 @@ fn prefix_and_suffix<'tcx>( false => "@function", }; - writeln!(begin, ".pushsection {section},\"ax\", {progbits}").unwrap(); + if let Some(section) = &link_section { + writeln!(begin, ".pushsection {section},\"ax\", {progbits}").unwrap(); + } else if function_sections { + writeln!(begin, ".pushsection .text.{asm_name},\"ax\", {progbits}").unwrap(); + } else { + writeln!(begin, ".text").unwrap(); + } writeln!(begin, ".balign {align_bytes}").unwrap(); write_linkage(&mut begin).unwrap(); match visibility { @@ -249,14 +255,22 @@ fn prefix_and_suffix<'tcx>( // pattern match on assembly generated by LLVM. writeln!(end, ".Lfunc_end_{asm_name}:").unwrap(); writeln!(end, ".size {asm_name}, . - {asm_name}").unwrap(); - writeln!(end, ".popsection").unwrap(); + if link_section.is_some() || function_sections { + writeln!(end, ".popsection").unwrap(); + } if !arch_suffix.is_empty() { writeln!(end, "{}", arch_suffix).unwrap(); } } BinaryFormat::MachO => { - let section = link_section.unwrap_or_else(|| "__TEXT,__text".to_string()); - writeln!(begin, ".pushsection {},regular,pure_instructions", section).unwrap(); + // NOTE: LLVM ignores `-Zfunction-sections` on macos. Instead the Mach-O symbol + // subsection splitting feature is used, which can be enabled with the + // `.subsections_via_symbols` global directive. LLVM already enables this directive. + if let Some(section) = &link_section { + writeln!(begin, ".pushsection {section},regular,pure_instructions").unwrap(); + } else { + writeln!(begin, ".section __TEXT,__text,regular,pure_instructions").unwrap(); + } writeln!(begin, ".balign {align_bytes}").unwrap(); write_linkage(&mut begin).unwrap(); match visibility { @@ -267,7 +281,9 @@ fn prefix_and_suffix<'tcx>( writeln!(end).unwrap(); writeln!(end, ".Lfunc_end_{asm_name}:").unwrap(); - writeln!(end, ".popsection").unwrap(); + if link_section.is_some() { + writeln!(end, ".popsection").unwrap(); + } if !arch_suffix.is_empty() { writeln!(end, "{}", arch_suffix).unwrap(); } @@ -278,8 +294,36 @@ fn prefix_and_suffix<'tcx>( writeln!(begin, ".type 32").unwrap(); writeln!(begin, ".endef").unwrap(); - let section = link_section.unwrap_or_else(|| format!(".text.{asm_name}")); - writeln!(begin, ".pushsection {},\"xr\"", section).unwrap(); + if let Some(section) = &link_section { + writeln!(begin, ".section {section},\"xr\"").unwrap() + } else if !function_sections { + // Function sections are enabled by default on MSVC and windows-gnullvm, + // but disabled by default on GNU. + writeln!(begin, ".text").unwrap(); + } else { + // LLVM uses an extension to the section directive to support defining multiple + // sections with the same name and comdat. It adds `unique,` at the end of the + // `.section` directive. We have no way of generating that unique ID here, so don't + // emit it. + // + // See https://llvm.org/docs/Extensions.html#id2. + match &tcx.sess.target.options.env { + Env::Gnu => { + writeln!(begin, ".section .text${asm_name},\"xr\",one_only,{asm_name}") + .unwrap(); + } + Env::Msvc => { + writeln!(begin, ".section .text,\"xr\",one_only,{asm_name}").unwrap(); + } + Env::Unspecified => match &tcx.sess.target.options.os { + Os::Uefi => { + writeln!(begin, ".section .text,\"xr\",one_only,{asm_name}").unwrap(); + } + _ => bug!("unexpected coff target {}", tcx.sess.target.llvm_target), + }, + other => bug!("unexpected coff env {other:?}"), + } + } write_linkage(&mut begin).unwrap(); writeln!(begin, ".balign {align_bytes}").unwrap(); writeln!(begin, "{asm_name}:").unwrap(); @@ -421,7 +465,7 @@ fn wasm_type<'tcx>(signature: &mut String, arg_abi: &ArgAbi<'_, Ty<'tcx>>, ptr_t ..=8 => "f64", _ => ptr_type, }, - RegKind::Vector => "v128", + RegKind::Vector { .. } => "v128", }; signature.push_str(wrapped_wasm_type); diff --git a/compiler/rustc_codegen_ssa/src/mir/rvalue.rs b/compiler/rustc_codegen_ssa/src/mir/rvalue.rs index 2cb96c4ec0f5..f9e4a6a352ba 100644 --- a/compiler/rustc_codegen_ssa/src/mir/rvalue.rs +++ b/compiler/rustc_codegen_ssa/src/mir/rvalue.rs @@ -302,6 +302,14 @@ fn vector_can_bitcast(x: abi::Scalar) -> bool { let to_backend_ty = bx.cx().immediate_backend_type(cast); OperandValue::Immediate(bx.bitcast(imm, to_backend_ty)) } + ( + OperandValue::Immediate(imm), + abi::BackendRepr::SimdScalableVector { element: from_scalar, .. }, + abi::BackendRepr::SimdScalableVector { element: to_scalar, .. }, + ) if vector_can_bitcast(from_scalar) && vector_can_bitcast(to_scalar) => { + let to_backend_ty = bx.cx().immediate_backend_type(cast); + OperandValue::Immediate(bx.bitcast(imm, to_backend_ty)) + } ( OperandValue::Pair(imm_a, imm_b), abi::BackendRepr::ScalarPair(in_a, in_b), diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index 8ac3f0555db2..24f731c01996 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -10,7 +10,7 @@ use rustc_session::lint::builtin::AARCH64_SOFTFLOAT_NEON; use rustc_session::parse::feature_err; use rustc_span::{Span, Symbol, edit_distance, sym}; -use rustc_target::spec::Arch; +use rustc_target::spec::{Arch, SanitizerSet}; use rustc_target::target_features::{RUSTC_SPECIFIC_FEATURES, Stability}; use smallvec::SmallVec; @@ -460,6 +460,15 @@ pub fn retpoline_features_by_flags(sess: &Session, features: &mut Vec) { } } +/// Computes the backend target features to be added to account for sanitizer flags. +pub fn sanitizer_features_by_flags(sess: &Session, features: &mut Vec) { + // It's intentional that this is done only for non-kernel version of hwaddress. This matches + // clang behavior. + if sess.sanitizers().contains(SanitizerSet::HWADDRESS) { + features.push("+tagged-globals".into()); + } +} + pub(crate) fn provide(providers: &mut Providers) { *providers = Providers { rust_target_features: |tcx, cnum| { diff --git a/compiler/rustc_const_eval/src/check_consts/qualifs.rs b/compiler/rustc_const_eval/src/check_consts/qualifs.rs index 1fbd0cd23405..a4f33ea05b2d 100644 --- a/compiler/rustc_const_eval/src/check_consts/qualifs.rs +++ b/compiler/rustc_const_eval/src/check_consts/qualifs.rs @@ -103,13 +103,10 @@ fn in_any_value_of_ty<'tcx>(cx: &ConstCx<'_, 'tcx>, ty: Ty<'tcx>) -> bool { // FIXME(#132279): Once we've got a typing mode which reveals opaque types using the HIR // typeck results without causing query cycles, we should use this here instead of defining // opaque types. - let typing_env = ty::TypingEnv { - typing_mode: ty::TypingMode::analysis_in_body( - cx.tcx, - cx.body.source.def_id().expect_local(), - ), - param_env: cx.typing_env.param_env, - }; + let typing_env = ty::TypingEnv::new( + cx.typing_env.param_env, + ty::TypingMode::analysis_in_body(cx.tcx, cx.body.source.def_id().expect_local()), + ); let (infcx, param_env) = cx.tcx.infer_ctxt().build_with_typing_env(typing_env); let ocx = ObligationCtxt::new(&infcx); let obligation = Obligation::new( diff --git a/compiler/rustc_const_eval/src/const_eval/error.rs b/compiler/rustc_const_eval/src/const_eval/error.rs index c48b33e29eb6..2c299df7b777 100644 --- a/compiler/rustc_const_eval/src/const_eval/error.rs +++ b/compiler/rustc_const_eval/src/const_eval/error.rs @@ -92,7 +92,7 @@ fn into(self) -> InterpErrorInfo<'tcx> { } } -pub fn get_span_and_frames<'tcx>( +pub(crate) fn get_span_and_frames<'tcx>( tcx: TyCtxtAt<'tcx>, stack: &[Frame<'tcx, impl Provenance, impl Sized>], ) -> (Span, Vec) { diff --git a/compiler/rustc_const_eval/src/const_eval/eval_queries.rs b/compiler/rustc_const_eval/src/const_eval/eval_queries.rs index ccfdf571fb27..316fc9ba5f97 100644 --- a/compiler/rustc_const_eval/src/const_eval/eval_queries.rs +++ b/compiler/rustc_const_eval/src/const_eval/eval_queries.rs @@ -371,10 +371,20 @@ pub fn eval_to_allocation_raw_provider<'tcx>( // This shouldn't be used for statics, since statics are conceptually places, // not values -- so what we do here could break pointer identity. assert!(key.value.promoted.is_some() || !tcx.is_static(key.value.instance.def_id())); - // Const eval always happens in PostAnalysis mode . See the comment in - // `InterpCx::new` for more details. - debug_assert_eq!(key.typing_env.typing_mode, ty::TypingMode::PostAnalysis); + if cfg!(debug_assertions) { + match key.typing_env.typing_mode() { + ty::TypingMode::PostAnalysis => {} + ty::TypingMode::Coherence + | ty::TypingMode::Analysis { .. } + | ty::TypingMode::Borrowck { .. } + | ty::TypingMode::PostBorrowckAnalysis { .. } => { + bug!( + "Const eval should always happens in PostAnalysis mode. See the comment in `InterpCx::new` for more details." + ) + } + } + // Make sure we format the instance even if we do not print it. // This serves as a regression test against an ICE on printing. // The next two lines concatenated contain some discussion: diff --git a/compiler/rustc_const_eval/src/const_eval/type_info.rs b/compiler/rustc_const_eval/src/const_eval/type_info.rs index dffc66f731af..7b63ab5bb02e 100644 --- a/compiler/rustc_const_eval/src/const_eval/type_info.rs +++ b/compiler/rustc_const_eval/src/const_eval/type_info.rs @@ -419,7 +419,7 @@ pub(crate) fn write_fn_ptr_type_info( sig: &FnSigTys>, fn_header: &FnHeader>, ) -> InterpResult<'tcx> { - let FnHeader { safety, c_variadic, abi } = fn_header; + let FnHeader { fn_sig_kind } = fn_header; for (field_idx, field) in place.layout().ty.ty_adt_def().unwrap().non_enum_variant().fields.iter_enumerated() @@ -428,9 +428,9 @@ pub(crate) fn write_fn_ptr_type_info( match field.name { sym::unsafety => { - self.write_scalar(Scalar::from_bool(safety.is_unsafe()), &field_place)?; + self.write_scalar(Scalar::from_bool(!fn_sig_kind.is_safe()), &field_place)?; } - sym::abi => match abi { + sym::abi => match fn_sig_kind.abi() { ExternAbi::C { .. } => { let (rust_variant, _rust_place) = self.downcast(&field_place, sym::ExternC)?; @@ -463,7 +463,7 @@ pub(crate) fn write_fn_ptr_type_info( self.write_type_id(output, &field_place)?; } sym::variadic => { - self.write_scalar(Scalar::from_bool(*c_variadic), &field_place)?; + self.write_scalar(Scalar::from_bool(fn_sig_kind.c_variadic()), &field_place)?; } other => span_bug!(self.tcx.def_span(field.did), "unimplemented field {other}"), } diff --git a/compiler/rustc_const_eval/src/const_eval/valtrees.rs b/compiler/rustc_const_eval/src/const_eval/valtrees.rs index 4323debd8014..9e23f56d372b 100644 --- a/compiler/rustc_const_eval/src/const_eval/valtrees.rs +++ b/compiler/rustc_const_eval/src/const_eval/valtrees.rs @@ -236,9 +236,19 @@ pub(crate) fn eval_to_valtree<'tcx>( typing_env: ty::TypingEnv<'tcx>, cid: GlobalId<'tcx>, ) -> EvalToValTreeResult<'tcx> { - // Const eval always happens in PostAnalysis mode . See the comment in - // `InterpCx::new` for more details. - debug_assert_eq!(typing_env.typing_mode, ty::TypingMode::PostAnalysis); + if cfg!(debug_assertions) { + match typing_env.typing_mode() { + ty::TypingMode::PostAnalysis => {} + ty::TypingMode::Coherence + | ty::TypingMode::Analysis { .. } + | ty::TypingMode::Borrowck { .. } + | ty::TypingMode::PostBorrowckAnalysis { .. } => { + bug!( + "Const eval should always happens in PostAnalysis mode. See the comment in `InterpCx::new` for more details." + ) + } + } + } let const_alloc = tcx.eval_to_allocation_raw(typing_env.as_query_input(cid))?; // FIXME Need to provide a span to `eval_to_valtree` diff --git a/compiler/rustc_const_eval/src/errors.rs b/compiler/rustc_const_eval/src/errors.rs index 3943be0cf15e..a61601a7b3c8 100644 --- a/compiler/rustc_const_eval/src/errors.rs +++ b/compiler/rustc_const_eval/src/errors.rs @@ -314,14 +314,14 @@ pub(crate) struct InteriorMutableBorrowEscaping { "this lint makes sure the compiler doesn't get stuck due to infinite loops in const eval. If your compilation actually takes a long time, you can safely allow the lint" )] -pub struct LongRunning { +pub(crate) struct LongRunning { #[help("the constant being evaluated")] pub item_span: Span, } #[derive(Diagnostic)] #[diag("constant evaluation is taking a long time")] -pub struct LongRunningWarn { +pub(crate) struct LongRunningWarn { #[primary_span] #[label("the const evaluator is currently interpreting this expression")] pub span: Span, @@ -339,7 +339,7 @@ pub(crate) struct NonConstImplNote { } #[derive(Clone)] -pub struct FrameNote { +pub(crate) struct FrameNote { pub span: Span, pub times: i32, pub where_: &'static str, @@ -377,7 +377,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { #[derive(Subdiagnostic)] #[note(r#"the raw bytes of the constant (size: {$size}, align: {$align}) {"{"}{$bytes}{"}"}"#)] -pub struct RawBytesNote { +pub(crate) struct RawBytesNote { pub size: u64, pub align: u64, pub bytes: String, @@ -393,7 +393,7 @@ pub struct RawBytesNote { }s"# )] #[note("`{$ty}` cannot be compared in compile-time, and therefore cannot be used in `match`es")] -pub struct NonConstMatchEq<'tcx> { +pub(crate) struct NonConstMatchEq<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -408,7 +408,7 @@ pub struct NonConstMatchEq<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstForLoopIntoIter<'tcx> { +pub(crate) struct NonConstForLoopIntoIter<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -423,7 +423,7 @@ pub struct NonConstForLoopIntoIter<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstQuestionBranch<'tcx> { +pub(crate) struct NonConstQuestionBranch<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -438,7 +438,7 @@ pub struct NonConstQuestionBranch<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstQuestionFromResidual<'tcx> { +pub(crate) struct NonConstQuestionFromResidual<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -453,7 +453,7 @@ pub struct NonConstQuestionFromResidual<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstTryBlockFromOutput<'tcx> { +pub(crate) struct NonConstTryBlockFromOutput<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -468,7 +468,7 @@ pub struct NonConstTryBlockFromOutput<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstAwait<'tcx> { +pub(crate) struct NonConstAwait<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -483,7 +483,7 @@ pub struct NonConstAwait<'tcx> { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstClosure { +pub(crate) struct NonConstClosure { #[primary_span] pub span: Span, pub kind: ConstContext, @@ -499,14 +499,14 @@ pub struct NonConstClosure { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstCVariadicCall { +pub(crate) struct NonConstCVariadicCall { #[primary_span] pub span: Span, pub kind: ConstContext, } #[derive(Subdiagnostic)] -pub enum NonConstClosureNote { +pub(crate) enum NonConstClosureNote { #[note("function defined here, but it is not `const`")] FnDef { #[primary_span] @@ -534,7 +534,7 @@ pub enum NonConstClosureNote { #[derive(Subdiagnostic)] #[multipart_suggestion("consider dereferencing here", applicability = "machine-applicable")] -pub struct ConsiderDereferencing { +pub(crate) struct ConsiderDereferencing { pub deref: String, #[suggestion_part(code = "{deref}")] pub span: Span, @@ -549,7 +549,7 @@ pub struct ConsiderDereferencing { [const_fn] constant function *[other] {""} }s"#, code = E0015)] -pub struct NonConstOperator { +pub(crate) struct NonConstOperator { #[primary_span] pub span: Span, pub kind: ConstContext, @@ -566,7 +566,7 @@ pub struct NonConstOperator { *[other] {""} }s"#, code = E0015)] #[note("attempting to deref into `{$target_ty}`")] -pub struct NonConstDerefCoercion<'tcx> { +pub(crate) struct NonConstDerefCoercion<'tcx> { #[primary_span] pub span: Span, pub ty: Ty<'tcx>, @@ -579,7 +579,7 @@ pub struct NonConstDerefCoercion<'tcx> { #[derive(Diagnostic)] #[diag("destructor of `{$dropped_ty}` cannot be evaluated at compile-time", code = E0493)] -pub struct LiveDrop<'tcx> { +pub(crate) struct LiveDrop<'tcx> { #[primary_span] #[label( r#"the destructor for this type cannot be evaluated in {$kind -> diff --git a/compiler/rustc_const_eval/src/interpret/eval_context.rs b/compiler/rustc_const_eval/src/interpret/eval_context.rs index 04f0e7099d84..466dcff35982 100644 --- a/compiler/rustc_const_eval/src/interpret/eval_context.rs +++ b/compiler/rustc_const_eval/src/interpret/eval_context.rs @@ -1,5 +1,3 @@ -use std::debug_assert_matches; - use either::{Left, Right}; use rustc_abi::{Align, HasDataLayout, Size, TargetDataLayout}; use rustc_hir::def_id::DefId; @@ -11,9 +9,10 @@ LayoutOfHelpers, TyAndLayout, }; use rustc_middle::ty::{ - self, GenericArgsRef, Ty, TyCtxt, TypeFoldable, TypeVisitableExt, TypingEnv, Variance, + self, GenericArgsRef, Ty, TyCtxt, TypeFoldable, TypeVisitableExt, TypingEnv, TypingMode, + Variance, }; -use rustc_middle::{mir, span_bug}; +use rustc_middle::{bug, mir, span_bug}; use rustc_span::Span; use rustc_target::callconv::FnAbi; use tracing::{debug, trace}; @@ -243,7 +242,18 @@ pub fn new( // opaque types. This is needed for trivial things like `size_of`, but also for using associated // types that are not specified in the opaque type. We also use MIR bodies whose opaque types have // already been revealed, so we'd be able to at least partially observe the hidden types anyways. - debug_assert_matches!(typing_env.typing_mode, ty::TypingMode::PostAnalysis); + if cfg!(debug_assertions) { + match typing_env.typing_mode() { + TypingMode::PostAnalysis => {} + TypingMode::Coherence + | TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } => { + bug!("Const eval should always happens in PostAnalysis mode."); + } + } + } + InterpCx { machine, tcx: tcx.at(root_span), diff --git a/compiler/rustc_const_eval/src/interpret/stack.rs b/compiler/rustc_const_eval/src/interpret/stack.rs index a73767264dab..3e7c57a439c6 100644 --- a/compiler/rustc_const_eval/src/interpret/stack.rs +++ b/compiler/rustc_const_eval/src/interpret/stack.rs @@ -223,7 +223,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } impl<'tcx> FrameInfo<'tcx> { - pub fn as_note(&self, tcx: TyCtxt<'tcx>) -> errors::FrameNote { + pub(crate) fn as_note(&self, tcx: TyCtxt<'tcx>) -> errors::FrameNote { let span = self.span; if tcx.def_key(self.instance.def_id()).disambiguated_data.data == DefPathData::Closure { errors::FrameNote { diff --git a/compiler/rustc_const_eval/src/interpret/step.rs b/compiler/rustc_const_eval/src/interpret/step.rs index 2dee1157e2a1..f9ab86e9888d 100644 --- a/compiler/rustc_const_eval/src/interpret/step.rs +++ b/compiler/rustc_const_eval/src/interpret/step.rs @@ -542,7 +542,7 @@ fn eval_terminator(&mut self, terminator: &mir::Terminator<'tcx>) -> InterpResul let destination = self.eval_place(destination)?; self.init_fn_call( callee, - (fn_sig.abi, fn_abi), + (fn_sig.abi(), fn_abi), &args, with_caller_location, &destination, @@ -565,7 +565,12 @@ fn eval_terminator(&mut self, terminator: &mir::Terminator<'tcx>) -> InterpResul let EvaluatedCalleeAndArgs { callee, args, fn_sig, fn_abi, with_caller_location } = self.eval_callee_and_args(terminator, func, args, &mir::Place::return_place())?; - self.init_fn_tail_call(callee, (fn_sig.abi, fn_abi), &args, with_caller_location)?; + self.init_fn_tail_call( + callee, + (fn_sig.abi(), fn_abi), + &args, + with_caller_location, + )?; if self.frame_idx() != old_frame_idx { span_bug!( diff --git a/compiler/rustc_const_eval/src/interpret/visitor.rs b/compiler/rustc_const_eval/src/interpret/visitor.rs index a8d472bc2ea2..53a1fda78d11 100644 --- a/compiler/rustc_const_eval/src/interpret/visitor.rs +++ b/compiler/rustc_const_eval/src/interpret/visitor.rs @@ -124,7 +124,12 @@ fn walk_value(&mut self, v: &Self::V) -> InterpResult<'tcx> { // ... that contains a `NonNull`... (gladly, only a single field here) assert_eq!(nonnull_ptr.layout().fields.count(), 1); - let raw_ptr = self.ecx().project_field(&nonnull_ptr, FieldIdx::ZERO)?; // the actual raw ptr + let pat_ty = self.ecx().project_field(&nonnull_ptr, FieldIdx::ZERO)?; // `*mut T is !null` + let base = match *pat_ty.layout().ty.kind() { + ty::Pat(base, _) => self.ecx().layout_of(base)?, + _ => unreachable!(), + }; + let raw_ptr = pat_ty.transmute(base, self.ecx())?; // The actual raw pointer // ... whose only field finally is a raw ptr we can dereference. self.visit_box(ty, &raw_ptr)?; diff --git a/compiler/rustc_data_structures/Cargo.toml b/compiler/rustc_data_structures/Cargo.toml index f358ffffb47d..c428810e5411 100644 --- a/compiler/rustc_data_structures/Cargo.toml +++ b/compiler/rustc_data_structures/Cargo.toml @@ -10,7 +10,7 @@ bitflags = "2.4.1" either = "1.0" elsa = "1.11.0" ena = "0.14.3" -indexmap = "2.12.1" +indexmap = "2.14.0" jobserver_crate = { version = "0.1.28", package = "jobserver" } measureme = "12.0.1" parking_lot = "0.12" @@ -23,17 +23,21 @@ rustc_index = { path = "../rustc_index", package = "rustc_index" } rustc_macros = { path = "../rustc_macros" } rustc_serialize = { path = "../rustc_serialize" } rustc_thread_pool = { path = "../rustc_thread_pool" } -smallvec = { version = "1.8.1", features = ["const_generics", "union", "may_dangle"] } +smallvec = { version = "1.8.1", features = [ + "const_generics", + "union", + "may_dangle", +] } stacker = "0.1.17" tempfile = "3.2" -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end [dependencies.hashbrown] -version = "0.16.1" +version = "0.17.0" default-features = false -features = ["nightly"] # for may_dangle +features = ["nightly"] # for may_dangle [target.'cfg(windows)'.dependencies.windows] version = "0.61.0" diff --git a/compiler/rustc_data_structures/src/aligned.rs b/compiler/rustc_data_structures/src/aligned.rs index d653847f1c60..290d30871fe6 100644 --- a/compiler/rustc_data_structures/src/aligned.rs +++ b/compiler/rustc_data_structures/src/aligned.rs @@ -1,8 +1,5 @@ use std::marker::PointeeSized; -#[cfg(not(bootstrap))] use std::mem::Alignment; -#[cfg(bootstrap)] -use std::ptr::Alignment; /// Returns the ABI-required minimum alignment of a type in bytes. /// diff --git a/compiler/rustc_data_structures/src/lib.rs b/compiler/rustc_data_structures/src/lib.rs index de086085c4cb..0cfa8dd90d53 100644 --- a/compiler/rustc_data_structures/src/lib.rs +++ b/compiler/rustc_data_structures/src/lib.rs @@ -80,7 +80,6 @@ pub mod sync; pub mod tagged_ptr; pub mod temp_dir; -pub mod thinvec; pub mod thousands; pub mod transitive_relation; pub mod unhash; diff --git a/compiler/rustc_data_structures/src/tagged_ptr.rs b/compiler/rustc_data_structures/src/tagged_ptr.rs index 32f813811089..67c8a92dd89b 100644 --- a/compiler/rustc_data_structures/src/tagged_ptr.rs +++ b/compiler/rustc_data_structures/src/tagged_ptr.rs @@ -56,9 +56,6 @@ pub unsafe trait Tag: Copy { /// (this is based on `T`'s alignment). pub const fn bits_for() -> u32 { let alignment = crate::aligned::align_of::(); - #[cfg(bootstrap)] - let alignment = alignment.as_nonzero(); - #[cfg(not(bootstrap))] let alignment = alignment.as_nonzero_usize(); alignment.trailing_zeros() } diff --git a/compiler/rustc_data_structures/src/thinvec.rs b/compiler/rustc_data_structures/src/thinvec.rs deleted file mode 100644 index e60ac2cbc8b4..000000000000 --- a/compiler/rustc_data_structures/src/thinvec.rs +++ /dev/null @@ -1,92 +0,0 @@ -//! This is a copy-paste of `Vec::extract_if` for `ThinVec`. -//! -//! FIXME: is merged, this can be removed. - -use std::{ptr, slice}; - -use thin_vec::ThinVec; - -/// An iterator for [`ThinVec`] which uses a closure to determine if an element should be removed. -#[must_use = "iterators are lazy and do nothing unless consumed"] -pub struct ExtractIf<'a, T, F> { - vec: &'a mut ThinVec, - /// The index of the item that will be inspected by the next call to `next`. - idx: usize, - /// The number of items that have been drained (removed) thus far. - del: usize, - /// The original length of `vec` prior to draining. - old_len: usize, - /// The filter test predicate. - pred: F, -} - -impl<'a, T, F> ExtractIf<'a, T, F> -where - F: FnMut(&mut T) -> bool, -{ - pub fn new(vec: &'a mut ThinVec, filter: F) -> Self { - let old_len = vec.len(); - - // Guard against us getting leaked (leak amplification) - unsafe { - vec.set_len(0); - } - - ExtractIf { vec, idx: 0, del: 0, old_len, pred: filter } - } -} - -impl Iterator for ExtractIf<'_, T, F> -where - F: FnMut(&mut T) -> bool, -{ - type Item = T; - fn next(&mut self) -> Option { - unsafe { - while self.idx < self.old_len { - let i = self.idx; - let v = slice::from_raw_parts_mut(self.vec.as_mut_ptr(), self.old_len); - let drained = (self.pred)(&mut v[i]); - // Update the index *after* the predicate is called. If the index - // is updated prior and the predicate panics, the element at this - // index would be leaked. - self.idx += 1; - if drained { - self.del += 1; - return Some(ptr::read(&v[i])); - } else if self.del > 0 { - let del = self.del; - let src: *const T = &v[i]; - let dst: *mut T = &mut v[i - del]; - ptr::copy_nonoverlapping(src, dst, 1); - } - } - None - } - } - - fn size_hint(&self) -> (usize, Option) { - (0, Some(self.old_len - self.idx)) - } -} - -impl Drop for ExtractIf<'_, A, F> { - fn drop(&mut self) { - unsafe { - if self.idx < self.old_len && self.del > 0 { - // This is a pretty messed up state, and there isn't really an - // obviously right thing to do. We don't want to keep trying - // to execute `pred`, so we just backshift all the unprocessed - // elements and tell the vec that they still exist. The backshift - // is required to prevent a double-drop of the last successfully - // drained item prior to a panic in the predicate. - let ptr = self.vec.as_mut_ptr(); - let src = ptr.add(self.idx); - let dst = src.sub(self.del); - let tail_len = self.old_len - self.idx; - src.copy_to(dst, tail_len); - } - self.vec.set_len(self.old_len - self.del); - } - } -} diff --git a/compiler/rustc_driver_impl/src/lib.rs b/compiler/rustc_driver_impl/src/lib.rs index ff7e170543be..c15c3c229398 100644 --- a/compiler/rustc_driver_impl/src/lib.rs +++ b/compiler/rustc_driver_impl/src/lib.rs @@ -28,7 +28,7 @@ use rustc_ast as ast; use rustc_codegen_ssa::traits::CodegenBackend; -use rustc_codegen_ssa::{CodegenErrors, CompiledModules}; +use rustc_codegen_ssa::{CodegenError, CompiledModules}; use rustc_data_structures::profiling::{ TimePassesFormat, get_resident_set_size, print_time_passes_entry, }; @@ -567,23 +567,21 @@ fn process_rlink(sess: &Session, compiler: &interface::Compiler) { } Err(err) => { match err { - CodegenErrors::WrongFileType => dcx.emit_fatal(RLinkWrongFileType), - CodegenErrors::EmptyVersionNumber => { - dcx.emit_fatal(RLinkEmptyVersionNumber) - } - CodegenErrors::EncodingVersionMismatch { version_array, rlink_version } => { + CodegenError::WrongFileType => dcx.emit_fatal(RLinkWrongFileType), + CodegenError::EmptyVersionNumber => dcx.emit_fatal(RLinkEmptyVersionNumber), + CodegenError::EncodingVersionMismatch { version_array, rlink_version } => { dcx.emit_fatal(RLinkEncodingVersionMismatch { version_array, rlink_version, }) } - CodegenErrors::RustcVersionMismatch { rustc_version } => { + CodegenError::RustcVersionMismatch { rustc_version } => { dcx.emit_fatal(RLinkRustcVersionMismatch { rustc_version, current_version: sess.cfg_version, }) } - CodegenErrors::CorruptFile => { + CodegenError::CorruptFile => { dcx.emit_fatal(RlinkCorruptFile { file }); } }; @@ -714,8 +712,7 @@ fn print_crate_info( let crate_name = passes::get_crate_name(sess, attrs); let lint_store = crate::unerased_lint_store(sess); let features = rustc_expand::config::features(sess, attrs, crate_name); - let registered_tools = - rustc_resolve::registered_tools_ast(sess.dcx(), attrs, sess, &features); + let registered_tools = rustc_resolve::registered_tools_ast(sess.dcx(), attrs, sess); let lint_levels = rustc_lint::LintLevelsBuilder::crate_root( sess, &features, diff --git a/compiler/rustc_driver_impl/src/session_diagnostics.rs b/compiler/rustc_driver_impl/src/session_diagnostics.rs index 97972185ebc4..f800c3f6b9d0 100644 --- a/compiler/rustc_driver_impl/src/session_diagnostics.rs +++ b/compiler/rustc_driver_impl/src/session_diagnostics.rs @@ -4,7 +4,7 @@ #[derive(Diagnostic)] #[diag("could not emit MIR: {$error}")] -pub struct CantEmitMIR { +pub(crate) struct CantEmitMIR { pub error: std::io::Error, } diff --git a/compiler/rustc_error_codes/src/error_codes/E0232.md b/compiler/rustc_error_codes/src/error_codes/E0232.md index 0e50cf589ee6..cb0797006092 100644 --- a/compiler/rustc_error_codes/src/error_codes/E0232.md +++ b/compiler/rustc_error_codes/src/error_codes/E0232.md @@ -1,19 +1,14 @@ The `#[rustc_on_unimplemented]` attribute lets you specify a custom error message for when a particular trait isn't implemented on a type placed in a -position that needs that trait. For example, when the following code is -compiled: +position that needs that trait. The attribute will let you filter on +various types, with `on`: ```compile_fail,E0232 #![feature(rustc_attrs)] #![allow(internal_features)] -#[rustc_on_unimplemented(lorem="")] // error! +#[rustc_on_unimplemented(on(blah, message = "foo"))] // error! trait BadAnnotation {} ``` - -there will be an error about `bool` not implementing `Index`, followed by a -note saying "the type `bool` cannot be indexed by `u8`". - -For this to work, some note must be specified. An empty attribute will not do -anything, please remove the attribute or add some helpful note for users of the -trait. +For this to work a cfg-like predicate must be supplied. A malformed filter +will not do anything. diff --git a/compiler/rustc_error_codes/src/error_codes/E0452.md b/compiler/rustc_error_codes/src/error_codes/E0452.md index a2471ec78eed..429813a7cdd4 100644 --- a/compiler/rustc_error_codes/src/error_codes/E0452.md +++ b/compiler/rustc_error_codes/src/error_codes/E0452.md @@ -1,9 +1,8 @@ -#### Note: this error code is no longer emitted by the compiler An invalid lint attribute has been given. Erroneous code example: -```compile_fail +```compile_fail,E0452 #![allow(foo = "")] // error: malformed lint attribute ``` diff --git a/compiler/rustc_error_messages/src/lib.rs b/compiler/rustc_error_messages/src/lib.rs index a2c026706ada..a1128f18043d 100644 --- a/compiler/rustc_error_messages/src/lib.rs +++ b/compiler/rustc_error_messages/src/lib.rs @@ -7,7 +7,7 @@ pub use fluent_bundle::types::FluentType; pub use fluent_bundle::{self, FluentArgs, FluentError, FluentValue}; -use rustc_macros::{Decodable, Encodable}; +use rustc_macros::{Decodable, Encodable, HashStable_Generic}; use rustc_span::Span; pub use unic_langid::{LanguageIdentifier, langid}; @@ -28,7 +28,7 @@ pub fn register_functions(bundle: &mut fluent_bundle::bundle::FluentBundle /// diagnostic messages. /// /// Intended to be removed once diagnostics are entirely translatable. -#[derive(Clone, Debug, PartialEq, Eq, Hash, Encodable, Decodable)] +#[derive(Clone, Debug, PartialEq, Eq, Hash, Encodable, Decodable, HashStable_Generic)] #[rustc_diagnostic_item = "DiagMessage"] pub enum DiagMessage { /// Non-translatable diagnostic message or a message that has been translated eagerly. @@ -89,7 +89,7 @@ pub struct SpanLabel { /// the error, and would be rendered with `^^^`. /// - They can have a *label*. In this case, the label is written next /// to the mark in the snippet when we render. -#[derive(Clone, Debug, Hash, PartialEq, Eq, Encodable, Decodable)] +#[derive(Clone, Debug, Hash, PartialEq, Eq, Encodable, Decodable, HashStable_Generic)] pub struct MultiSpan { primary_spans: Vec, span_labels: Vec<(Span, DiagMessage)>, diff --git a/compiler/rustc_errors/Cargo.toml b/compiler/rustc_errors/Cargo.toml index 2560ac50bba4..386467c3e1ed 100644 --- a/compiler/rustc_errors/Cargo.toml +++ b/compiler/rustc_errors/Cargo.toml @@ -9,7 +9,6 @@ annotate-snippets = { version = "0.12.15", features = ["simd"] } anstream = "0.6.20" anstyle = "1.0.13" derive_setters = "0.1.6" -rustc_abi = { path = "../rustc_abi" } rustc_ast = { path = "../rustc_ast" } rustc_data_structures = { path = "../rustc_data_structures" } rustc_error_codes = { path = "../rustc_error_codes" } diff --git a/compiler/rustc_errors/src/diagnostic.rs b/compiler/rustc_errors/src/diagnostic.rs index 7acf95d77d40..ecde304aabfc 100644 --- a/compiler/rustc_errors/src/diagnostic.rs +++ b/compiler/rustc_errors/src/diagnostic.rs @@ -7,6 +7,7 @@ use std::path::PathBuf; use std::thread::panicking; +use rustc_data_structures::sync::{DynSend, DynSync}; use rustc_error_messages::{DiagArgMap, DiagArgName, DiagArgValue, IntoDiagArg}; use rustc_lint_defs::{Applicability, LintExpectationId}; use rustc_macros::{Decodable, Encodable}; @@ -118,6 +119,28 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, G> { } } +impl<'a> Diagnostic<'a, ()> + for Box< + dyn for<'b> FnOnce(DiagCtxtHandle<'b>, Level) -> Diag<'b, ()> + DynSync + DynSend + 'static, + > +{ + fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { + self(dcx, level) + } +} + +pub struct DiagCallback<'a>( + pub &'a Box< + dyn for<'b> Fn(DiagCtxtHandle<'b>, Level) -> Diag<'b, ()> + DynSend + DynSync + 'static, + >, +); + +impl<'a, 'b> Diagnostic<'a, ()> for DiagCallback<'b> { + fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { + (self.0)(dcx, level) + } +} + /// Type used to emit diagnostic through a closure instead of implementing the `Diagnostic` trait. pub struct DiagDecorator)>(pub F); @@ -983,7 +1006,7 @@ pub fn span_suggestions( msg, suggestions, applicability, - SuggestionStyle::ShowCode, + SuggestionStyle::ShowAlways, ) } } diff --git a/compiler/rustc_errors/src/diagnostic_impls.rs b/compiler/rustc_errors/src/diagnostic_impls.rs index e50cbbbf06e0..ba7569c51a07 100644 --- a/compiler/rustc_errors/src/diagnostic_impls.rs +++ b/compiler/rustc_errors/src/diagnostic_impls.rs @@ -1,12 +1,11 @@ use std::borrow::Cow; -use rustc_abi::TargetDataLayoutErrors; use rustc_error_messages::{DiagArgValue, IntoDiagArg}; use rustc_macros::Subdiagnostic; use rustc_span::{Span, Symbol}; use crate::diagnostic::DiagLocation; -use crate::{Diag, DiagCtxtHandle, Diagnostic, EmissionGuarantee, Level, Subdiagnostic, msg}; +use crate::{Diag, EmissionGuarantee, Subdiagnostic}; impl IntoDiagArg for DiagLocation { fn into_diag_arg(self, _: &mut Option) -> DiagArgValue { @@ -37,55 +36,6 @@ fn into_diag_arg(self, _: &mut Option) -> DiagArgValue { } } -impl Diagnostic<'_, G> for TargetDataLayoutErrors<'_> { - fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { - match self { - TargetDataLayoutErrors::InvalidAddressSpace { addr_space, err, cause } => { - Diag::new(dcx, level, msg!("invalid address space `{$addr_space}` for `{$cause}` in \"data-layout\": {$err}")) - .with_arg("addr_space", addr_space) - .with_arg("cause", cause) - .with_arg("err", err) - } - TargetDataLayoutErrors::InvalidBits { kind, bit, cause, err } => { - Diag::new(dcx, level, msg!("invalid {$kind} `{$bit}` for `{$cause}` in \"data-layout\": {$err}")) - .with_arg("kind", kind) - .with_arg("bit", bit) - .with_arg("cause", cause) - .with_arg("err", err) - } - TargetDataLayoutErrors::MissingAlignment { cause } => { - Diag::new(dcx, level, msg!("missing alignment for `{$cause}` in \"data-layout\"")) - .with_arg("cause", cause) - } - TargetDataLayoutErrors::InvalidAlignment { cause, err } => { - Diag::new(dcx, level, msg!( - "invalid alignment for `{$cause}` in \"data-layout\": {$err}" - )) - .with_arg("cause", cause) - .with_arg("err", err.to_string()) - } - TargetDataLayoutErrors::InconsistentTargetArchitecture { dl, target } => { - Diag::new(dcx, level, msg!( - "inconsistent target specification: \"data-layout\" claims architecture is {$dl}-endian, while \"target-endian\" is `{$target}`" - )) - .with_arg("dl", dl).with_arg("target", target) - } - TargetDataLayoutErrors::InconsistentTargetPointerWidth { pointer_size, target } => { - Diag::new(dcx, level, msg!( - "inconsistent target specification: \"data-layout\" claims pointers are {$pointer_size}-bit, while \"target-pointer-width\" is `{$target}`" - )).with_arg("pointer_size", pointer_size).with_arg("target", target) - } - TargetDataLayoutErrors::InvalidBitsSize { err } => { - Diag::new(dcx, level, msg!("{$err}")).with_arg("err", err) - } - TargetDataLayoutErrors::UnknownPointerSpecification { err } => { - Diag::new(dcx, level, msg!("unknown pointer specification `{$err}` in datalayout string")) - .with_arg("err", err) - } - } - } -} - /// Utility struct used to apply a single label while highlighting multiple spans pub struct SingleLabelManySpans { pub spans: Vec, diff --git a/compiler/rustc_errors/src/lib.rs b/compiler/rustc_errors/src/lib.rs index d17a4d6de42f..f4874652f6ac 100644 --- a/compiler/rustc_errors/src/lib.rs +++ b/compiler/rustc_errors/src/lib.rs @@ -36,8 +36,8 @@ pub use codes::*; pub use decorate_diag::{BufferedEarlyLint, DecorateDiagCompat, LintBuffer}; pub use diagnostic::{ - BugAbort, Diag, DiagDecorator, DiagInner, DiagLocation, DiagStyledString, Diagnostic, - EmissionGuarantee, FatalAbort, StringPart, Subdiag, Subdiagnostic, + BugAbort, Diag, DiagCallback, DiagDecorator, DiagInner, DiagLocation, DiagStyledString, + Diagnostic, EmissionGuarantee, FatalAbort, StringPart, Subdiag, Subdiagnostic, }; pub use diagnostic_impls::{ DiagSymbolList, ElidedLifetimeInPathSubdiag, ExpectedLifetimeParameter, @@ -77,6 +77,7 @@ pub mod emitter; pub mod formatting; pub mod json; +pub mod lints; mod lock; pub mod markdown; pub mod timings; diff --git a/compiler/rustc_errors/src/lints.rs b/compiler/rustc_errors/src/lints.rs new file mode 100644 index 000000000000..9c93a09bf764 --- /dev/null +++ b/compiler/rustc_errors/src/lints.rs @@ -0,0 +1,15 @@ +use rustc_macros::Diagnostic; +use rustc_span::Span; + +#[derive(Diagnostic)] +#[diag("unused attribute")] +pub struct UnusedDuplicate { + #[suggestion("remove this attribute", code = "", applicability = "machine-applicable")] + pub this: Span, + #[note("attribute also specified here")] + pub other: Span, + #[warning( + "this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!" + )] + pub warning: bool, +} diff --git a/compiler/rustc_errors/src/markdown/parse.rs b/compiler/rustc_errors/src/markdown/parse.rs index e1b1b32cd3ef..cd39f9b34d43 100644 --- a/compiler/rustc_errors/src/markdown/parse.rs +++ b/compiler/rustc_errors/src/markdown/parse.rs @@ -220,7 +220,7 @@ fn parse_codeblock(buf: &[u8]) -> Parsed<'_> { let mut found = None; for idx in (0..working.len()).filter(|idx| working[*idx..].starts_with(&end_pat)) { let (eol_txt, rest) = parse_to_newline(&working[(idx + end_pat.len())..]); - if !eol_txt.iter().any(u8::is_ascii_whitespace) { + if eol_txt.iter().all(u8::is_ascii_whitespace) { found = Some((&working[..idx], rest)); break; } @@ -252,7 +252,7 @@ fn parse_heading(buf: &[u8]) -> ParseResult<'_> { fn parse_unordered_li(buf: &[u8]) -> Parsed<'_> { let (txt, rest) = get_indented_section(&buf[2..]); let ctx = Context { .. }; - let stream = parse_recursive(trim_ascii_start(txt), ctx); + let stream = parse_recursive(txt.trim_ascii_start(), ctx); (MdTree::UnorderedListItem(stream), rest) } @@ -261,7 +261,7 @@ fn parse_ordered_li(buf: &[u8]) -> Parsed<'_> { let (num, pos) = ord_list_start(buf).unwrap(); // success tested in caller let (txt, rest) = get_indented_section(&buf[pos..]); let ctx = Context { .. }; - let stream = parse_recursive(trim_ascii_start(txt), ctx); + let stream = parse_recursive(txt.trim_ascii_start(), ctx); (MdTree::OrderedListItem(num, stream), rest) } @@ -578,12 +578,6 @@ fn trim_extra_ws(mut txt: &str) -> &str { &txt[..txt.len() - end_ws] } -/// If there is more than one whitespace char at start, trim the extras -fn trim_ascii_start(buf: &[u8]) -> &[u8] { - let count = buf.iter().take_while(|ch| ch.is_ascii_whitespace()).count(); - &buf[count..] -} - #[cfg(test)] #[path = "tests/parse.rs"] mod tests; diff --git a/compiler/rustc_errors/src/markdown/tests/parse.rs b/compiler/rustc_errors/src/markdown/tests/parse.rs index bfcb3de16fa0..1a8d19a1136e 100644 --- a/compiler/rustc_errors/src/markdown/tests/parse.rs +++ b/compiler/rustc_errors/src/markdown/tests/parse.rs @@ -364,3 +364,37 @@ fn test_snake_case() { let res = entrypoint(SNAKE_CASE); assert_eq!(res, expected); } + +#[test] +fn test_codeblock_trailing_whitespace() { + let buf = "```rust\ncode\n``` \nrest"; + let (t, r) = parse_codeblock(buf.as_bytes()); + assert_eq!(t, MdTree::CodeBlock { txt: "code", lang: Some("rust") }); + assert_eq!(r, b"\nrest"); + + let buf = "```rust\ncode\n```abc\nrest"; + let (t, r) = parse_codeblock(buf.as_bytes()); + assert_eq!(t, MdTree::CodeBlock { txt: "code\n```abc\nrest", lang: Some("rust") }); + assert_eq!(r, b""); +} + +#[test] +fn test_list_item_leading_whitespace() { + // extra spaces after marker + let buf = "- hello"; + let (t, r) = parse_unordered_li(buf.as_bytes()); + assert_eq!(t, MdTree::UnorderedListItem(vec![MdTree::PlainText("hello")].into())); + assert_eq!(r, b""); + + // tab after the marker space + let buf = "- \thello"; + let (t, r) = parse_unordered_li(buf.as_bytes()); + assert_eq!(t, MdTree::UnorderedListItem(vec![MdTree::PlainText("hello")].into())); + assert_eq!(r, b""); + + // ordered list + let buf = "1. hello"; + let (t, r) = parse_ordered_li(buf.as_bytes()); + assert_eq!(t, MdTree::OrderedListItem(1, vec![MdTree::PlainText("hello")].into())); + assert_eq!(r, b""); +} diff --git a/compiler/rustc_expand/Cargo.toml b/compiler/rustc_expand/Cargo.toml index 12b0c384a8ae..0154d05266fd 100644 --- a/compiler/rustc_expand/Cargo.toml +++ b/compiler/rustc_expand/Cargo.toml @@ -30,6 +30,6 @@ rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } scoped-tls = "1.0" smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_expand/src/base.rs b/compiler/rustc_expand/src/base.rs index 4f60ba2e9725..b8325f7ba398 100644 --- a/compiler/rustc_expand/src/base.rs +++ b/compiler/rustc_expand/src/base.rs @@ -9,7 +9,7 @@ use rustc_ast::attr::MarkedAttrs; use rustc_ast::tokenstream::TokenStream; use rustc_ast::visit::{AssocCtxt, Visitor}; -use rustc_ast::{self as ast, AttrVec, HasAttrs, Item, NodeId, PatKind, Safety}; +use rustc_ast::{self as ast, AttrVec, Attribute, HasAttrs, Item, NodeId, PatKind, Safety}; use rustc_data_structures::fx::{FxHashMap, FxIndexMap}; use rustc_data_structures::sync; use rustc_errors::{BufferedEarlyLint, DiagCtxtHandle, ErrorGuaranteed, PResult}; @@ -409,17 +409,10 @@ pub trait GlobDelegationExpander { fn expand(&self, ecx: &mut ExtCtxt<'_>) -> ExpandResult)>, ()>; } -// Use a macro because forwarding to a simple function has type system issues -macro_rules! make_stmts_default { - ($me:expr) => { - $me.make_expr().map(|e| { - smallvec![ast::Stmt { - id: ast::DUMMY_NODE_ID, - span: e.span, - kind: ast::StmtKind::Expr(e), - }] - }) - }; +fn make_stmts_default(expr: Option>) -> Option> { + expr.map(|e| { + smallvec![ast::Stmt { id: ast::DUMMY_NODE_ID, span: e.span, kind: ast::StmtKind::Expr(e) }] + }) } /// The result of a macro expansion. The return values of the various @@ -465,7 +458,7 @@ fn make_pat(self: Box) -> Option> { /// By default this attempts to create an expression statement, /// returning None if that fails. fn make_stmts(self: Box) -> Option> { - make_stmts_default!(self) + make_stmts_default(self.make_expr()) } fn make_ty(self: Box) -> Option> { @@ -571,9 +564,10 @@ fn make_expr(self: Box) -> Option> { } fn make_stmts(self: Box) -> Option> { - match self.stmts.as_ref().map_or(0, |s| s.len()) { - 0 => make_stmts_default!(self), - _ => self.stmts, + if self.stmts.as_ref().is_none_or(|s| s.is_empty()) { + make_stmts_default(self.make_expr()) + } else { + self.stmts } } @@ -898,7 +892,7 @@ pub fn default(kind: SyntaxExtensionKind, edition: Edition) -> SyntaxExtension { fn get_collapse_debuginfo(sess: &Session, attrs: &[hir::Attribute], ext: bool) -> bool { let flag = sess.opts.cg.collapse_macro_debuginfo; let attr = if let Some(info) = find_attr!(attrs, CollapseDebugInfo(info) => info) { - info.clone() + *info } else if find_attr!(attrs, RustcBuiltinMacro { .. }) { CollapseMacroDebuginfo::Yes } else { @@ -1019,18 +1013,24 @@ pub fn non_macro_attr(edition: Edition) -> SyntaxExtension { pub fn glob_delegation( trait_def_id: DefId, impl_def_id: LocalDefId, + star_span: Span, edition: Edition, ) -> SyntaxExtension { struct GlobDelegationExpanderImpl { trait_def_id: DefId, impl_def_id: LocalDefId, + star_span: Span, } impl GlobDelegationExpander for GlobDelegationExpanderImpl { fn expand( &self, ecx: &mut ExtCtxt<'_>, ) -> ExpandResult)>, ()> { - match ecx.resolver.glob_delegation_suffixes(self.trait_def_id, self.impl_def_id) { + match ecx.resolver.glob_delegation_suffixes( + self.trait_def_id, + self.impl_def_id, + self.star_span, + ) { Ok(suffixes) => ExpandResult::Ready(suffixes), Err(Indeterminate) if ecx.force_mode => ExpandResult::Ready(Vec::new()), Err(Indeterminate) => ExpandResult::Retry(()), @@ -1038,7 +1038,7 @@ fn expand( } } - let expander = GlobDelegationExpanderImpl { trait_def_id, impl_def_id }; + let expander = GlobDelegationExpanderImpl { trait_def_id, impl_def_id, star_span }; SyntaxExtension::default(SyntaxExtensionKind::GlobDelegation(Arc::new(expander)), edition) } @@ -1170,6 +1170,7 @@ fn glob_delegation_suffixes( &self, trait_def_id: DefId, impl_def_id: LocalDefId, + star_span: Span, ) -> Result)>, Indeterminate>; /// Record the name of an opaque `Ty::ImplTrait` pre-expansion so that it can be used @@ -1188,6 +1189,7 @@ fn pre_expansion_lint( features: &Features, registered_tools: &RegisteredTools, node_id: NodeId, + attrs: &[Attribute], items: &[Box], name: Symbol, ); diff --git a/compiler/rustc_expand/src/build.rs b/compiler/rustc_expand/src/build.rs index 05e6b78132ae..01886a97f55a 100644 --- a/compiler/rustc_expand/src/build.rs +++ b/compiler/rustc_expand/src/build.rs @@ -715,6 +715,7 @@ pub fn item_static( mutability, expr: Some(expr), define_opaque: None, + eii_impls: Default::default(), } .into(), ), diff --git a/compiler/rustc_expand/src/config.rs b/compiler/rustc_expand/src/config.rs index ec5951e50e3a..b5f85536d9ca 100644 --- a/compiler/rustc_expand/src/config.rs +++ b/compiler/rustc_expand/src/config.rs @@ -7,13 +7,13 @@ AttrTokenStream, AttrTokenTree, LazyAttrTokenStream, Spacing, TokenTree, }; use rustc_ast::{ - self as ast, AttrItemKind, AttrKind, AttrStyle, Attribute, DUMMY_NODE_ID, EarlyParsedAttribute, - HasAttrs, HasTokens, MetaItem, MetaItemInner, NodeId, NormalAttr, + self as ast, AttrItemKind, AttrKind, AttrStyle, Attribute, EarlyParsedAttribute, HasAttrs, + HasTokens, MetaItem, MetaItemInner, NodeId, NormalAttr, }; use rustc_attr_parsing::parser::AllowExprMetavar; use rustc_attr_parsing::{ - self as attr, AttributeParser, CFG_TEMPLATE, EvalConfigResult, ShouldEmit, eval_config_entry, - parse_cfg, + self as attr, AttributeParser, AttributeSafety, CFG_TEMPLATE, EvalConfigResult, ShouldEmit, + eval_config_entry, parse_cfg, }; use rustc_data_structures::flat_map_in_place::FlatMapInPlace; use rustc_errors::msg; @@ -28,7 +28,7 @@ use rustc_parse::parser::Recovery; use rustc_session::Session; use rustc_session::parse::feature_err; -use rustc_span::{DUMMY_SP, STDLIB_STABLE_CRATES, Span, Symbol, sym}; +use rustc_span::{STDLIB_STABLE_CRATES, Span, Symbol, sym}; use tracing::instrument; use crate::errors::{ @@ -51,14 +51,7 @@ pub fn features(sess: &Session, krate_attrs: &[Attribute], crate_name: Symbol) - let mut features = Features::default(); if let Some(hir::Attribute::Parsed(AttributeKind::Feature(feature_idents, _))) = - AttributeParser::parse_limited( - sess, - krate_attrs, - sym::feature, - DUMMY_SP, - DUMMY_NODE_ID, - Some(&features), - ) + AttributeParser::parse_limited(sess, krate_attrs, &[sym::feature]) { for feature_ident in feature_idents { // If the enabled feature has been removed, issue an error. @@ -106,33 +99,24 @@ pub fn features(sess: &Session, krate_attrs: &[Attribute], crate_name: Symbol) - // If the enabled feature is unstable, record it. if UNSTABLE_LANG_FEATURES.iter().find(|f| feature_ident.name == f.name).is_some() { - // When the ICE comes from a standard library crate, there's a chance that the person - // hitting the ICE may be using -Zbuild-std or similar with an untested target. - // The bug is probably in the standard library and not the compiler in that case, - // but that doesn't really matter - we want a bug report. - if features.internal(feature_ident.name) - && !STDLIB_STABLE_CRATES.contains(&crate_name) - { - sess.using_internal_features.store(true, std::sync::atomic::Ordering::Relaxed); - } - features.set_enabled_lang_feature(EnabledLangFeature { gate_name: feature_ident.name, attr_sp: feature_ident.span, stable_since: None, }); - continue; + } else { + // Otherwise, the feature is unknown. Enable it as a lib feature. + // It will be checked later whether the feature really exists. + features.set_enabled_lib_feature(EnabledLibFeature { + gate_name: feature_ident.name, + attr_sp: feature_ident.span, + }); } - // Otherwise, the feature is unknown. Enable it as a lib feature. - // It will be checked later whether the feature really exists. - features.set_enabled_lib_feature(EnabledLibFeature { - gate_name: feature_ident.name, - attr_sp: feature_ident.span, - }); - - // Similar to above, detect internal lib features to suppress - // the ICE message that asks for a report. + // When the ICE comes from a standard library crate, there's a chance that the person + // hitting the ICE may be using -Zbuild-std or similar with an untested target. + // The bug is probably in the standard library and not the compiler in that case, + // but that doesn't really matter - we want a bug report. if features.internal(feature_ident.name) && !STDLIB_STABLE_CRATES.contains(&crate_name) { sess.using_internal_features.store(true, std::sync::atomic::Ordering::Relaxed); @@ -283,9 +267,12 @@ pub(crate) fn expand_cfg_attr(&self, cfg_attr: &Attribute, recursive: bool) -> V trace_attr.replace_args(AttrItemKind::Parsed(EarlyParsedAttribute::CfgAttrTrace)); let trace_attr = attr_into_trace(trace_attr, sym::cfg_attr_trace); - let Some((cfg_predicate, expanded_attrs)) = - rustc_attr_parsing::parse_cfg_attr(cfg_attr, &self.sess, self.features) - else { + let Some((cfg_predicate, expanded_attrs)) = rustc_attr_parsing::parse_cfg_attr( + cfg_attr, + self.sess, + self.features, + self.lint_node_id, + ) else { return vec![trace_attr]; }; @@ -404,6 +391,7 @@ pub(crate) fn cfg_true(&self, attr: &Attribute, emit_errors: ShouldEmit) -> Eval parse_cfg, &CFG_TEMPLATE, AllowExprMetavar::Yes, + AttributeSafety::Normal, ) else { // Cfg attribute was not parsable, give up return EvalConfigResult::True; @@ -419,7 +407,7 @@ pub(crate) fn maybe_emit_expr_attr_err(&self, attr: &Attribute) { && !attr.span.allows_unstable(sym::stmt_expr_attributes) { let mut err = feature_err( - &self.sess, + self.sess, sym::stmt_expr_attributes, attr.span, msg!("attributes on expressions are experimental"), diff --git a/compiler/rustc_expand/src/errors.rs b/compiler/rustc_expand/src/errors.rs index cee333e0a59f..6c5732f497f8 100644 --- a/compiler/rustc_expand/src/errors.rs +++ b/compiler/rustc_expand/src/errors.rs @@ -603,3 +603,21 @@ pub(crate) struct TrailingMacro { pub is_trailing: bool, pub name: Ident, } + +#[derive(Diagnostic)] +#[diag("unused attribute `{$attr_name}`")] +pub(crate) struct UnusedBuiltinAttribute { + #[note( + "the built-in attribute `{$attr_name}` will be ignored, since it's applied to the macro invocation `{$macro_name}`" + )] + pub invoc_span: Span, + pub attr_name: Symbol, + pub macro_name: String, + #[suggestion( + "remove the attribute", + code = "", + applicability = "machine-applicable", + style = "tool-only" + )] + pub attr_span: Span, +} diff --git a/compiler/rustc_expand/src/expand.rs b/compiler/rustc_expand/src/expand.rs index 5e7c15ba1d7b..804d3c02b413 100644 --- a/compiler/rustc_expand/src/expand.rs +++ b/compiler/rustc_expand/src/expand.rs @@ -8,15 +8,15 @@ use rustc_ast::visit::{self, AssocCtxt, Visitor, VisitorResult, try_visit, walk_list}; use rustc_ast::{ self as ast, AssocItemKind, AstNodeWrapper, AttrArgs, AttrItemKind, AttrStyle, AttrVec, - DUMMY_NODE_ID, EarlyParsedAttribute, ExprKind, ForeignItemKind, HasAttrs, HasNodeId, Inline, - ItemKind, MacStmtStyle, MetaItemInner, MetaItemKind, ModKind, NodeId, PatKind, StmtKind, - TyKind, token, + DUMMY_NODE_ID, DelegationSuffixes, EarlyParsedAttribute, ExprKind, ForeignItemKind, HasAttrs, + HasNodeId, Inline, ItemKind, MacStmtStyle, MetaItemInner, MetaItemKind, ModKind, NodeId, + PatKind, StmtKind, TyKind, token, }; use rustc_ast_pretty::pprust; use rustc_attr_parsing::parser::AllowExprMetavar; use rustc_attr_parsing::{ - AttributeParser, CFG_TEMPLATE, EvalConfigResult, ShouldEmit, eval_config_entry, parse_cfg, - validate_attr, + AttributeParser, AttributeSafety, CFG_TEMPLATE, Early, EvalConfigResult, ShouldEmit, + eval_config_entry, parse_cfg, validate_attr, }; use rustc_data_structures::flat_map_in_place::FlatMapInPlace; use rustc_data_structures::stack::ensure_sufficient_stack; @@ -30,7 +30,7 @@ RecoverColon, RecoverComma, Recovery, token_descr, }; use rustc_session::Session; -use rustc_session::lint::builtin::UNUSED_DOC_COMMENTS; +use rustc_session::lint::builtin::{UNUSED_ATTRIBUTES, UNUSED_DOC_COMMENTS}; use rustc_session::parse::feature_err; use rustc_span::hygiene::SyntaxContext; use rustc_span::{ErrorGuaranteed, FileName, Ident, LocalExpnId, Span, Symbol, sym}; @@ -815,6 +815,27 @@ fn expand_invoc( { rustc_parse::fake_token_stream_for_item(&self.cx.sess.psess, item_inner) } + Annotatable::Item(item_inner) if item_inner.tokens.is_none() => { + rustc_parse::fake_token_stream_for_item(&self.cx.sess.psess, item_inner) + } + // When a function has EII implementations attached (via `eii_impls`), + // use fake tokens so the pretty-printer re-emits the EII attribute + // (e.g. `#[hello]`) in the token stream. Without this, the EII + // attribute is lost during the token roundtrip performed by + // `AttrProcMacro` expanders like `contracts::requires/ensures`, + // breaking the EII link on the resulting re-parsed item. + Annotatable::Item(item_inner) + if matches!(&item_inner.kind, + ItemKind::Fn(f) if !f.eii_impls.is_empty()) => + { + rustc_parse::fake_token_stream_for_item(&self.cx.sess.psess, item_inner) + } + Annotatable::ForeignItem(item_inner) if item_inner.tokens.is_none() => { + rustc_parse::fake_token_stream_for_foreign_item( + &self.cx.sess.psess, + item_inner, + ) + } _ => item.to_tokens(), }; let attr_item = attr.get_normal_item(); @@ -1029,7 +1050,7 @@ fn gate_proc_macro_attr_item(&self, span: Span, item: &Annotatable) { return; } feature_err( - &self.cx.sess, + self.cx.sess, sym::proc_macro_hygiene, span, format!("custom attributes cannot be applied to {kind}"), @@ -1064,7 +1085,7 @@ fn visit_item(&mut self, item: &'ast ast::Item) { } if !self.cx.ecfg.features.proc_macro_hygiene() { - annotatable.visit_with(&mut GateProcMacroInput { sess: &self.cx.sess }); + annotatable.visit_with(&mut GateProcMacroInput { sess: self.cx.sess }); } } @@ -1403,6 +1424,7 @@ fn wrap_flat_map_node_walk_flat_map( ecx.ecfg.features, ecx.resolver.registered_tools(), ecx.current_expansion.lint_node_id, + &attrs, &items, ident.name, ); @@ -1452,7 +1474,7 @@ fn collect_use_tree_leaves(ut: &ast::UseTree, idents: &mut Vec) { } } let mut idents = Vec::new(); - collect_use_tree_leaves(&ut, &mut idents); + collect_use_tree_leaves(ut, &mut idents); idents } else { self.kind.ident().into_iter().collect() @@ -1460,7 +1482,7 @@ fn collect_use_tree_leaves(ut: &ast::UseTree, idents: &mut Vec) { } fn as_target(&self) -> Target { - Target::from_ast_item(&*self) + Target::from_ast_item(self) } } @@ -2257,7 +2279,6 @@ fn check_attributes(&self, attrs: &[ast::Attribute], call: &ast::MacCall) { self.cx.current_expansion.lint_node_id, Some(self.cx.ecfg.features), ShouldEmit::ErrorsAndLints { recovery: Recovery::Allowed }, - Some(self.cx.resolver.registered_tools()), ); let current_span = if let Some(sp) = span { sp.to(attr.span) } else { attr.span }; @@ -2274,6 +2295,21 @@ fn check_attributes(&self, attrs: &[ast::Attribute], call: &ast::MacCall) { self.cx.current_expansion.lint_node_id, crate::errors::MacroCallUnusedDocComment { span: attr.span }, ); + } else if rustc_attr_parsing::is_builtin_attr(attr) + && !AttributeParser::::is_parsed_attribute(&attr.path()) + { + let attr_name = attr.name().unwrap(); + self.cx.sess.psess.buffer_lint( + UNUSED_ATTRIBUTES, + attr.span, + self.cx.current_expansion.lint_node_id, + crate::errors::UnusedBuiltinAttribute { + attr_name, + macro_name: pprust::path_to_string(&call.path), + invoc_span: call.path.span, + attr_span: attr.span, + }, + ); } } } @@ -2295,6 +2331,7 @@ fn expand_cfg_true( parse_cfg, &CFG_TEMPLATE, AllowExprMetavar::Yes, + AttributeSafety::Normal, ) else { // Cfg attribute was not parsable, give up return EvalConfigResult::True; @@ -2365,7 +2402,7 @@ fn flat_map_node>( res } None if let Some((deleg, item)) = node.delegation() => { - let Some(suffixes) = &deleg.suffixes else { + let DelegationSuffixes::List(suffixes) = &deleg.suffixes else { let traitless_qself = matches!(&deleg.qself, Some(qself) if qself.position == 0); let (item, of_trait) = match node.to_annotatable() { diff --git a/compiler/rustc_expand/src/mbe/diagnostics.rs b/compiler/rustc_expand/src/mbe/diagnostics.rs index fd2e4e3ec39f..b8040c3d9c1a 100644 --- a/compiler/rustc_expand/src/mbe/diagnostics.rs +++ b/compiler/rustc_expand/src/mbe/diagnostics.rs @@ -288,27 +288,24 @@ pub(super) fn emit_frag_parse_err( _ => annotate_err_with_kind(&mut e, kind, site_span), }; - let mut bindings_rules = vec![]; - for rule in bindings { - let MacroRule::Func { lhs, .. } = rule else { continue }; - for param in lhs { - let MatcherLoc::MetaVarDecl { bind, .. } = param else { continue }; - bindings_rules.push(*bind); - } - } - - let mut matched_rule_bindings_rules = vec![]; - for param in matched_rule_bindings { - let MatcherLoc::MetaVarDecl { bind, .. } = param else { continue }; - matched_rule_bindings_rules.push(*bind); - } - - let matched_rule_bindings_names: Vec<_> = - matched_rule_bindings_rules.iter().map(|bind| bind.name).collect(); - let bindings_name: Vec<_> = bindings_rules.iter().map(|bind| bind.name).collect(); if parser.token.kind == token::Dollar { parser.bump(); if let token::Ident(name, _) = parser.token.kind { + let mut bindings_names = vec![]; + for rule in bindings { + let MacroRule::Func { lhs, .. } = rule else { continue }; + for param in lhs { + let MatcherLoc::MetaVarDecl { bind, .. } = param else { continue }; + bindings_names.push(bind.name); + } + } + + let mut matched_rule_bindings_names = vec![]; + for param in matched_rule_bindings { + let MatcherLoc::MetaVarDecl { bind, .. } = param else { continue }; + matched_rule_bindings_names.push(bind.name); + } + if let Some(matched_name) = rustc_span::edit_distance::find_best_match_for_name( &matched_rule_bindings_names[..], name, @@ -316,24 +313,22 @@ pub(super) fn emit_frag_parse_err( ) { e.span_suggestion_verbose( parser.token.span, - "there is a macro metavariable with similar name", - format!("{matched_name}"), + "there is a macro metavariable with a similar name", + matched_name, Applicability::MaybeIncorrect, ); - } else if bindings_name.contains(&name) { + } else if bindings_names.contains(&name) { e.span_label( parser.token.span, - format!( - "there is an macro metavariable with this name in another macro matcher" - ), + "there is an macro metavariable with this name in another macro matcher", ); } else if let Some(matched_name) = - rustc_span::edit_distance::find_best_match_for_name(&bindings_name[..], name, None) + rustc_span::edit_distance::find_best_match_for_name(&bindings_names[..], name, None) { e.span_suggestion_verbose( parser.token.span, "there is a macro metavariable with a similar name in another macro matcher", - format!("{matched_name}"), + matched_name, Applicability::MaybeIncorrect, ); } else { @@ -343,7 +338,7 @@ pub(super) fn emit_frag_parse_err( .collect::>() .join(", "); - e.span_label(parser.token.span, format!("macro metavariable not found")); + e.span_label(parser.token.span, "macro metavariable not found"); if !matched_rule_bindings_names.is_empty() { e.note(format!("available metavariable names are: {msg}")); } diff --git a/compiler/rustc_expand/src/mbe/macro_parser.rs b/compiler/rustc_expand/src/mbe/macro_parser.rs index 9c327c26849e..b8325e3ce775 100644 --- a/compiler/rustc_expand/src/mbe/macro_parser.rs +++ b/compiler/rustc_expand/src/mbe/macro_parser.rs @@ -199,8 +199,8 @@ fn inner( let idx_seq = idx_first - 1; inner(&seq.tts, locs, next_metavar, seq_depth + 1); - if let Some(separator) = &seq.separator { - locs.push(MatcherLoc::SequenceSep { separator: separator.clone() }); + if let Some(separator) = seq.separator { + locs.push(MatcherLoc::SequenceSep { separator }); locs.push(MatcherLoc::SequenceKleeneOpAfterSep { idx_first }); } else { locs.push(MatcherLoc::SequenceKleeneOpNoSep { op, idx_first }); diff --git a/compiler/rustc_expand/src/mbe/quoted.rs b/compiler/rustc_expand/src/mbe/quoted.rs index eb874a27cece..a698db543759 100644 --- a/compiler/rustc_expand/src/mbe/quoted.rs +++ b/compiler/rustc_expand/src/mbe/quoted.rs @@ -214,7 +214,7 @@ fn parse_tree<'a>( // during parsing. let mut next = outer_iter.next(); let mut iter_storage; - let mut iter: &mut TokenStreamIter<'_> = match next { + let iter: &mut TokenStreamIter<'_> = match next { Some(tokenstream::TokenTree::Delimited(.., delim, tts)) if delim.skip() => { iter_storage = tts.iter(); next = iter_storage.next(); @@ -284,7 +284,7 @@ fn parse_tree<'a>( let sequence = parse(tts, part, sess, node_id, features, edition); // Get the Kleene operator and optional separator let (separator, kleene) = - parse_sep_and_kleene_op(&mut iter, delim_span.entire(), sess); + parse_sep_and_kleene_op(iter, delim_span.entire(), sess); // Count the number of captured "names" (i.e., named metavars) let num_captures = if part.is_pattern() { count_metavar_decls(&sequence) } else { 0 }; diff --git a/compiler/rustc_expand/src/mbe/transcribe.rs b/compiler/rustc_expand/src/mbe/transcribe.rs index dcf2cd1fa36a..7152ffcd9f30 100644 --- a/compiler/rustc_expand/src/mbe/transcribe.rs +++ b/compiler/rustc_expand/src/mbe/transcribe.rs @@ -396,7 +396,7 @@ fn transcribe_sequence<'tx, 'itp>( // The first time we encounter the sequence we push it to the stack. It // then gets reused (see the beginning of the loop) until we are done // repeating. - tscx.stack.push(Frame::new_sequence(seq_rep, seq.separator.clone(), seq.kleene.op)); + tscx.stack.push(Frame::new_sequence(seq_rep, seq.separator, seq.kleene.op)); } } } @@ -629,7 +629,7 @@ fn metavar_expr_concat<'tx>( ) -> PResult<'tx, TokenTree> { let dcx = tscx.psess.dcx(); let mut concatenated = String::new(); - for element in elements.into_iter() { + for element in elements { let symbol = match element { MetaVarExprConcatElem::Ident(elem) => elem.name, MetaVarExprConcatElem::Literal(elem) => *elem, @@ -747,7 +747,7 @@ fn maybe_use_metavar_location( TokenTree::Token(Token { kind, span }, spacing) => { let span = metavar_span.with_ctxt(span.ctxt()); with_metavar_spans(|mspans| mspans.insert(span, metavar_span)); - TokenTree::Token(Token { kind: kind.clone(), span }, *spacing) + TokenTree::Token(Token { kind: *kind, span }, *spacing) } TokenTree::Delimited(dspan, dspacing, delimiter, tts) => { let open = metavar_span.with_ctxt(dspan.open.ctxt()); diff --git a/compiler/rustc_expand/src/module.rs b/compiler/rustc_expand/src/module.rs index 803803ec3f6c..f64ff982e523 100644 --- a/compiler/rustc_expand/src/module.rs +++ b/compiler/rustc_expand/src/module.rs @@ -77,7 +77,7 @@ pub(crate) fn parse_external_mod( Some(span), )); let (inner_attrs, items, inner_span) = - parser.parse_mod(exp!(Eof)).map_err(|err| ModError::ParserError(err))?; + parser.parse_mod(exp!(Eof)).map_err(ModError::ParserError)?; attrs.extend(inner_attrs); (items, inner_span, mp.file_path) }; diff --git a/compiler/rustc_expand/src/proc_macro.rs b/compiler/rustc_expand/src/proc_macro.rs index 5b2482f5c1db..8ad502aa3f70 100644 --- a/compiler/rustc_expand/src/proc_macro.rs +++ b/compiler/rustc_expand/src/proc_macro.rs @@ -1,5 +1,6 @@ use rustc_ast as ast; use rustc_ast::tokenstream::TokenStream; +use rustc_data_structures::profiling::TimingGuard; use rustc_errors::ErrorGuaranteed; use rustc_middle::ty::{self, TyCtxt}; use rustc_parse::parser::{AllowConstBlockItems, ForceCollect, Parser}; @@ -19,6 +20,16 @@ fn exec_strategy(sess: &Session) -> impl pm::bridge::server::ExecutionStrategy + } } +fn record_expand_proc_macro<'a>( + ecx: &ExtCtxt<'a>, + name: &'static str, + span: Span, +) -> TimingGuard<'a> { + ecx.sess.prof.generic_activity_with_arg_recorder(name, |recorder| { + recorder.record_arg_with_span(ecx.sess.source_map(), ecx.expansion_descr(), span); + }) +} + pub struct BangProcMacro { pub client: pm::bridge::client::Client, } @@ -30,10 +41,7 @@ fn expand( span: Span, input: TokenStream, ) -> Result { - let _timer = - ecx.sess.prof.generic_activity_with_arg_recorder("expand_proc_macro", |recorder| { - recorder.record_arg_with_span(ecx.sess.source_map(), ecx.expansion_descr(), span); - }); + let _timer = record_expand_proc_macro(ecx, "expand_proc_macro", span); let proc_macro_backtrace = ecx.ecfg.proc_macro_backtrace; let strategy = exec_strategy(ecx.sess); @@ -41,9 +49,7 @@ fn expand( self.client.run(&strategy, server, input, proc_macro_backtrace).map_err(|e| { ecx.dcx().emit_err(errors::ProcMacroPanicked { span, - message: e - .as_str() - .map(|message| errors::ProcMacroPanickedHelp { message: message.into() }), + message: e.into_string().map(|message| errors::ProcMacroPanickedHelp { message }), }) }) } @@ -61,10 +67,7 @@ fn expand( annotation: TokenStream, annotated: TokenStream, ) -> Result { - let _timer = - ecx.sess.prof.generic_activity_with_arg_recorder("expand_proc_macro", |recorder| { - recorder.record_arg_with_span(ecx.sess.source_map(), ecx.expansion_descr(), span); - }); + let _timer = record_expand_proc_macro(ecx, "expand_proc_macro", span); let proc_macro_backtrace = ecx.ecfg.proc_macro_backtrace; let strategy = exec_strategy(ecx.sess); @@ -73,9 +76,9 @@ fn expand( |e| { ecx.dcx().emit_err(errors::CustomAttributePanicked { span, - message: e.as_str().map(|message| errors::CustomAttributePanickedHelp { - message: message.into(), - }), + message: e + .into_string() + .map(|message| errors::CustomAttributePanickedHelp { message }), }) }, ) @@ -95,12 +98,7 @@ fn expand( item: Annotatable, _is_derive_const: bool, ) -> ExpandResult, Annotatable> { - let _timer = ecx.sess.prof.generic_activity_with_arg_recorder( - "expand_derive_proc_macro_outer", - |recorder| { - recorder.record_arg_with_span(ecx.sess.source_map(), ecx.expansion_descr(), span); - }, - ); + let _timer = record_expand_proc_macro(ecx, "expand_derive_proc_macro_outer", span); // We need special handling for statement items // (e.g. `fn foo() { #[derive(Debug)] struct Bar; }`) @@ -191,7 +189,7 @@ fn expand_derive_macro( let invoc_expn_data = invoc_id.expn_data(); let span = invoc_expn_data.call_site; let event_arg = invoc_expn_data.kind.descr(); - recorder.record_arg_with_span(ecx.sess.source_map(), event_arg.clone(), span); + recorder.record_arg_with_span(ecx.sess.source_map(), event_arg, span); }); let proc_macro_backtrace = ecx.ecfg.proc_macro_backtrace; @@ -206,9 +204,9 @@ fn expand_derive_macro( ecx.dcx().emit_err({ errors::ProcMacroDerivePanicked { span, - message: e.as_str().map(|message| errors::ProcMacroDerivePanickedHelp { - message: message.into(), - }), + message: e + .into_string() + .map(|message| errors::ProcMacroDerivePanickedHelp { message }), } }); Err(()) @@ -232,7 +230,7 @@ fn enter(ecx: &mut ExtCtxt<'_>, client: DeriveClient, f: F) -> R { // We need erasure to get rid of the lifetime let ctx = Self { expansion_ctx: ecx as *mut _ as *mut (), client }; - DERIVE_EXPAND_CTX.set(&ctx, || f()) + DERIVE_EXPAND_CTX.set(&ctx, f) } /// Accesses the thread local value of the derive expansion context. diff --git a/compiler/rustc_expand/src/proc_macro_server.rs b/compiler/rustc_expand/src/proc_macro_server.rs index 037afbb9f550..7b345fe5f483 100644 --- a/compiler/rustc_expand/src/proc_macro_server.rs +++ b/compiler/rustc_expand/src/proc_macro_server.rs @@ -110,26 +110,22 @@ fn from_internal(stream: TokenStream) -> Self { // Estimate the capacity as `stream.len()` rounded up to the next power // of two to limit the number of required reallocations. let mut trees = Vec::with_capacity(stream.len().next_power_of_two()); - let mut iter = stream.iter(); - while let Some(tree) = iter.next() { + for tree in stream.iter() { let (Token { kind, span }, joint) = match tree.clone() { tokenstream::TokenTree::Delimited(span, _, mut delim, mut stream) => { // In `mk_delimited` we avoid nesting invisible delimited // of the same `MetaVarKind`. Here we do the same but // ignore the `MetaVarKind` because it is discarded when we // convert it to a `Group`. - while let Delimiter::Invisible(InvisibleOrigin::MetaVar(_)) = delim { - if stream.len() == 1 - && let tree = stream.iter().next().unwrap() - && let tokenstream::TokenTree::Delimited(_, _, delim2, stream2) = tree - && let Delimiter::Invisible(InvisibleOrigin::MetaVar(_)) = delim2 - { - delim = *delim2; - stream = stream2.clone(); - } else { - break; - } + while let Delimiter::Invisible(InvisibleOrigin::MetaVar(_)) = delim + && stream.len() == 1 + && let tree = stream.get(0).unwrap() + && let tokenstream::TokenTree::Delimited(_, _, delim2, stream2) = tree + && let Delimiter::Invisible(InvisibleOrigin::MetaVar(_)) = delim2 + { + delim = *delim2; + stream = stream2.clone(); } trees.push(TokenTree::Group(Group { diff --git a/compiler/rustc_expand/src/stats.rs b/compiler/rustc_expand/src/stats.rs index 00f1c11044e0..0d60141f274e 100644 --- a/compiler/rustc_expand/src/stats.rs +++ b/compiler/rustc_expand/src/stats.rs @@ -152,7 +152,7 @@ pub(crate) fn update_macro_stats( } // The recorded size is the difference between the input and the output. - let entry = ecx.macro_stats.entry((name, macro_kind)).or_insert(MacroStat::default()); + let entry = ecx.macro_stats.entry((name, macro_kind)).or_default(); entry.uses += 1; entry.lines += num_lines; entry.bytes += num_bytes; diff --git a/compiler/rustc_feature/src/builtin_attrs.rs b/compiler/rustc_feature/src/builtin_attrs.rs index b8b9226cc602..053caee258f7 100644 --- a/compiler/rustc_feature/src/builtin_attrs.rs +++ b/compiler/rustc_feature/src/builtin_attrs.rs @@ -5,7 +5,6 @@ use AttributeGate::*; use rustc_data_structures::fx::FxHashMap; use rustc_hir::AttrStyle; -use rustc_span::edition::Edition; use rustc_span::{Symbol, sym}; use crate::Features; @@ -59,6 +58,7 @@ sym::cfg_target_has_reliable_f16_f128, Features::cfg_target_has_reliable_f16_f128, ), + (sym::target_object_format, sym::cfg_target_object_format, Features::cfg_target_object_format), ]; /// Find a gated cfg determined by the `pred`icate which is given the cfg's name. @@ -66,22 +66,6 @@ pub fn find_gated_cfg(pred: impl Fn(Symbol) -> bool) -> Option<&'static GatedCfg GATED_CFGS.iter().find(|(cfg_sym, ..)| pred(*cfg_sym)) } -// If you change this, please modify `src/doc/unstable-book` as well. You must -// move that documentation into the relevant place in the other docs, and -// remove the chapter on the flag. - -#[derive(Copy, Clone, PartialEq, Debug)] -pub enum AttributeSafety { - /// Normal attribute that does not need `#[unsafe(...)]` - Normal, - /// Unsafe attribute that requires safety obligations to be discharged. - /// - /// An error is emitted when `#[unsafe(...)]` is omitted, except when the attribute's edition - /// is less than the one stored in `unsafe_since`. This handles attributes that were safe in - /// earlier editions, but become unsafe in later ones. - Unsafe { unsafe_since: Option }, -} - #[derive(Clone, Debug, Copy)] pub enum AttributeGate { /// A gated attribute which requires a feature gate to be enabled. @@ -203,57 +187,15 @@ macro_rules! template { } macro_rules! ungated { - (unsafe($edition:ident) $attr:ident $(,)?) => { - BuiltinAttribute { - name: sym::$attr, - safety: AttributeSafety::Unsafe { unsafe_since: Some(Edition::$edition) }, - gate: Ungated, - } - }; - (unsafe $attr:ident $(,)?) => { - BuiltinAttribute { - name: sym::$attr, - safety: AttributeSafety::Unsafe { unsafe_since: None }, - gate: Ungated, - } - }; ($attr:ident $(,)?) => { - BuiltinAttribute { name: sym::$attr, safety: AttributeSafety::Normal, gate: Ungated } + BuiltinAttribute { name: sym::$attr, gate: Ungated } }; } macro_rules! gated { - (unsafe $attr:ident, $gate:ident, $message:expr $(,)?) => { - BuiltinAttribute { - name: sym::$attr, - safety: AttributeSafety::Unsafe { unsafe_since: None }, - - gate: Gated { - feature: sym::$gate, - message: $message, - check: Features::$gate, - notes: &[], - }, - } - }; - (unsafe $attr:ident, $message:expr $(,)?) => { - BuiltinAttribute { - name: sym::$attr, - safety: AttributeSafety::Unsafe { unsafe_since: None }, - - gate: Gated { - feature: sym::$attr, - message: $message, - check: Features::$attr, - notes: &[], - }, - } - }; ($attr:ident, $gate:ident, $message:expr $(,)?) => { BuiltinAttribute { name: sym::$attr, - safety: AttributeSafety::Normal, - gate: Gated { feature: sym::$gate, message: $message, @@ -265,8 +207,6 @@ macro_rules! gated { ($attr:ident, $message:expr $(,)?) => { BuiltinAttribute { name: sym::$attr, - safety: AttributeSafety::Normal, - gate: Gated { feature: sym::$attr, message: $message, @@ -279,7 +219,8 @@ macro_rules! gated { macro_rules! rustc_attr { (TEST, $attr:ident $(,)?) => { - rustc_attr!( $attr, + rustc_attr!( + $attr, concat!( "the `#[", stringify!($attr), @@ -290,7 +231,6 @@ macro_rules! rustc_attr { ($attr:ident $(, $notes:expr)* $(,)?) => { BuiltinAttribute { name: sym::$attr, - safety: AttributeSafety::Normal, gate: Gated { feature: sym::rustc_attrs, message: "use of an internal attribute", @@ -300,7 +240,7 @@ macro_rules! rustc_attr { stringify!($attr), "]` attribute is an internal implementation detail that will never be stable"), $($notes),* - ] + ] }, } }; @@ -314,7 +254,6 @@ macro_rules! experimental { pub struct BuiltinAttribute { pub name: Symbol, - pub safety: AttributeSafety, pub gate: AttributeGate, } @@ -362,23 +301,21 @@ pub struct BuiltinAttribute { ungated!(no_link), ungated!(repr), // FIXME(#82232, #143834): temporarily renamed to mitigate `#[align]` nameres ambiguity - gated!(rustc_align,fn_align, experimental!(rustc_align)), - gated!(rustc_align_static,static_align, experimental!(rustc_align_static)), - ungated!(unsafe(Edition2024) export_name), - ungated!(unsafe(Edition2024) link_section), - ungated!(unsafe(Edition2024) no_mangle), + gated!(rustc_align, fn_align, experimental!(rustc_align)), + gated!(rustc_align_static, static_align, experimental!(rustc_align_static)), + ungated!(export_name), + ungated!(link_section), + ungated!(no_mangle), ungated!(used), ungated!(link_ordinal), - ungated!(unsafe naked), + ungated!(naked), // See `TyAndLayout::pass_indirectly_in_non_rustic_abis` for details. rustc_attr!(rustc_pass_indirectly_in_non_rustic_abis, "types marked with `#[rustc_pass_indirectly_in_non_rustic_abis]` are always passed indirectly by non-Rustic ABIs"), // Limits: ungated!(recursion_limit), ungated!(type_length_limit), - gated!( - move_size_limit, large_assignments, experimental!(move_size_limit) - ), + gated!(move_size_limit, large_assignments, experimental!(move_size_limit)), // Entry point: ungated!(no_main), @@ -391,9 +328,7 @@ pub struct BuiltinAttribute { // Runtime ungated!(windows_subsystem), - ungated!(// RFC 2070 - panic_handler - ), + ungated!(panic_handler), // RFC 2070 // Code generation: ungated!(inline), @@ -402,18 +337,9 @@ pub struct BuiltinAttribute { ungated!(target_feature), ungated!(track_caller), ungated!(instruction_set), - gated!( - unsafe force_target_feature, - effective_target_features, experimental!(force_target_feature) - ), - gated!( - sanitize, - sanitize, experimental!(sanitize) - ), - gated!( - coverage, - coverage_attribute, experimental!(coverage) - ), + gated!(force_target_feature, effective_target_features, experimental!(force_target_feature)), + gated!(sanitize, sanitize, experimental!(sanitize)), + gated!(coverage, coverage_attribute, experimental!(coverage)), ungated!(doc), @@ -426,82 +352,45 @@ pub struct BuiltinAttribute { // ========================================================================== // Linking: - gated!( - export_stable, experimental!(export_stable) - ), + gated!(export_stable, experimental!(export_stable)), // Testing: - gated!( - test_runner, custom_test_frameworks, - "custom test frameworks are an unstable feature" - ), + gated!(test_runner, custom_test_frameworks, "custom test frameworks are an unstable feature"), - gated!( - reexport_test_harness_main, custom_test_frameworks, - "custom test frameworks are an unstable feature" - ), + gated!(reexport_test_harness_main, custom_test_frameworks, "custom test frameworks are an unstable feature"), // RFC #1268 - gated!( - marker,marker_trait_attr, experimental!(marker) - ), - gated!( - thread_local,"`#[thread_local]` is an experimental feature, and does not currently handle destructors" - ), - gated!( - no_core, experimental!(no_core) - ), + gated!(marker, marker_trait_attr, experimental!(marker)), + gated!(thread_local, "`#[thread_local]` is an experimental feature, and does not currently handle destructors"), + gated!(no_core, experimental!(no_core)), // RFC 2412 - gated!( - optimize, - optimize_attribute, experimental!(optimize) - ), + gated!(optimize, optimize_attribute, experimental!(optimize)), - gated!( - unsafe ffi_pure, experimental!(ffi_pure) - ), - gated!( - unsafe ffi_const, experimental!(ffi_const) - ), - gated!( - register_tool, experimental!(register_tool) - ), + gated!(ffi_pure, experimental!(ffi_pure)), + gated!(ffi_const, experimental!(ffi_const)), + gated!(register_tool, experimental!(register_tool)), // `#[cfi_encoding = ""]` - gated!( - cfi_encoding, - experimental!(cfi_encoding) - ), + gated!(cfi_encoding, experimental!(cfi_encoding)), // `#[coroutine]` attribute to be applied to closures to make them coroutines instead - gated!( - coroutine,coroutines, experimental!(coroutine) - ), + gated!(coroutine, coroutines, experimental!(coroutine)), // RFC 3543 // `#[patchable_function_entry(prefix_nops = m, entry_nops = n)]` - gated!( - patchable_function_entry, - experimental!(patchable_function_entry) - ), + gated!(patchable_function_entry, experimental!(patchable_function_entry)), // The `#[loop_match]` and `#[const_continue]` attributes are part of the // lang experiment for RFC 3720 tracked in: // // - https://github.com/rust-lang/rust/issues/132306 - gated!( - const_continue,loop_match, experimental!(const_continue) - ), - gated!( - loop_match,loop_match, experimental!(loop_match) - ), + gated!(const_continue, loop_match, experimental!(const_continue)), + gated!(loop_match, loop_match, experimental!(loop_match)), // The `#[pin_v2]` attribute is part of the `pin_ergonomics` experiment // that allows structurally pinning, tracked in: // // - https://github.com/rust-lang/rust/issues/130494 - gated!( - pin_v2,pin_ergonomics, experimental!(pin_v2), - ), + gated!(pin_v2, pin_ergonomics, experimental!(pin_v2)), // ========================================================================== // Internal attributes: Stability, deprecation, and unsafe: @@ -512,6 +401,7 @@ pub struct BuiltinAttribute { ungated!(stable), ungated!(unstable), ungated!(unstable_feature_bound), + ungated!(unstable_removed), ungated!(rustc_const_unstable), ungated!(rustc_const_stable), ungated!(rustc_default_body_unstable), @@ -520,20 +410,26 @@ pub struct BuiltinAttribute { "allow_internal_unstable side-steps feature gating and stability checks", ), gated!( - allow_internal_unsafe, "allow_internal_unsafe side-steps the unsafe_code lint", + allow_internal_unsafe, + "allow_internal_unsafe side-steps the unsafe_code lint", ), gated!( rustc_eii_foreign_item, eii_internals, "used internally to mark types with a `transparent` representation when it is guaranteed by the documentation", ), - rustc_attr!(rustc_allowed_through_unstable_modules, + rustc_attr!( + rustc_allowed_through_unstable_modules, "rustc_allowed_through_unstable_modules special cases accidental stabilizations of stable items \ through unstable paths" ), - rustc_attr!(rustc_deprecated_safe_2024,"`#[rustc_deprecated_safe_2024]` is used to declare functions unsafe across the edition 2024 boundary", + rustc_attr!( + rustc_deprecated_safe_2024, + "`#[rustc_deprecated_safe_2024]` is used to declare functions unsafe across the edition 2024 boundary", ), - rustc_attr!(rustc_pub_transparent,"used internally to mark types with a `transparent` representation when it is guaranteed by the documentation", + rustc_attr!( + rustc_pub_transparent, + "used internally to mark types with a `transparent` representation when it is guaranteed by the documentation", ), @@ -543,11 +439,13 @@ pub struct BuiltinAttribute { gated!(fundamental, experimental!(fundamental)), gated!( - may_dangle, dropck_eyepatch, - "`may_dangle` has unstable semantics and may be removed in the future" + may_dangle, + dropck_eyepatch, + "`may_dangle` has unstable semantics and may be removed in the future", ), - rustc_attr!(rustc_never_type_options, + rustc_attr!( + rustc_never_type_options, "`rustc_never_type_options` is used to experiment with never type fallback and work on \ never type stabilization" ), @@ -563,26 +461,30 @@ pub struct BuiltinAttribute { rustc_attr!(rustc_allocator_zeroed), rustc_attr!(rustc_allocator_zeroed_variant), gated!( - default_lib_allocator, allocator_internals, experimental!(default_lib_allocator), + default_lib_allocator, + allocator_internals, experimental!(default_lib_allocator), ), gated!( - needs_allocator, allocator_internals, experimental!(needs_allocator), + needs_allocator, + allocator_internals, experimental!(needs_allocator), ), gated!( - panic_runtime, experimental!(panic_runtime) + panic_runtime, + experimental!(panic_runtime) ), gated!( - needs_panic_runtime, experimental!(needs_panic_runtime) + needs_panic_runtime, + experimental!(needs_panic_runtime) ), gated!( compiler_builtins, "the `#[compiler_builtins]` attribute is used to identify the `compiler_builtins` crate \ - which contains compiler-rt intrinsics and will never be stable" + which contains compiler-rt intrinsics and will never be stable", ), gated!( profiler_runtime, "the `#[profiler_runtime]` attribute is used to identify the `profiler_builtins` crate \ - which contains the profiler runtime and will never be stable" + which contains the profiler runtime and will never be stable", ), // ========================================================================== @@ -591,7 +493,7 @@ pub struct BuiltinAttribute { gated!( linkage, - "the `linkage` attribute is experimental and not portable across platforms" + "the `linkage` attribute is experimental and not portable across platforms", ), rustc_attr!(rustc_std_internal_symbol), rustc_attr!(rustc_objc_class), @@ -603,8 +505,9 @@ pub struct BuiltinAttribute { rustc_attr!(rustc_builtin_macro), rustc_attr!(rustc_proc_macro_decls), - rustc_attr!(rustc_macro_transparency, - "used internally for testing macro hygiene" + rustc_attr!( + rustc_macro_transparency, + "used internally for testing macro hygiene", ), rustc_attr!(rustc_autodiff), rustc_attr!(rustc_offload_kernel), @@ -612,16 +515,16 @@ pub struct BuiltinAttribute { // The attributes are not gated, to avoid stability errors, but they cannot be used in stable // or unstable code directly because `sym::cfg_(attr_)trace` are not valid identifiers, they // can only be generated by the compiler. - ungated!(cfg_trace - ), - ungated!(cfg_attr_trace - ), + ungated!(cfg_trace), + ungated!(cfg_attr_trace), // ========================================================================== // Internal attributes, Diagnostics related: // ========================================================================== - rustc_attr!(rustc_on_unimplemented,"see `#[diagnostic::on_unimplemented]` for the stable equivalent of this attribute" + rustc_attr!( + rustc_on_unimplemented, + "see `#[diagnostic::on_unimplemented]` for the stable equivalent of this attribute" ), rustc_attr!(rustc_confusables), // Enumerates "identity-like" conversion methods to suggest on type mismatch. @@ -649,64 +552,115 @@ pub struct BuiltinAttribute { rustc_attr!(rustc_promotable), rustc_attr!(rustc_legacy_const_generics), // Do not const-check this function's body. It will always get replaced during CTFE via `hook_special_const_fn`. - rustc_attr!(rustc_do_not_const_check, "`#[rustc_do_not_const_check]` skips const-check for this function's body"), - rustc_attr!(rustc_const_stable_indirect, - "this is an internal implementation detail"), - rustc_attr!(rustc_intrinsic_const_stable_indirect, - "this is an internal implementation detail"), - rustc_attr!(rustc_allow_const_fn_unstable, - "rustc_allow_const_fn_unstable side-steps feature gating and stability checks" + rustc_attr!( + rustc_do_not_const_check, + "`#[rustc_do_not_const_check]` skips const-check for this function's body", + ), + rustc_attr!( + rustc_const_stable_indirect, + "this is an internal implementation detail", + ), + rustc_attr!( + rustc_intrinsic_const_stable_indirect, + "this is an internal implementation detail", + ), + rustc_attr!( + rustc_allow_const_fn_unstable, + "rustc_allow_const_fn_unstable side-steps feature gating and stability checks" ), // ========================================================================== // Internal attributes, Layout related: // ========================================================================== - rustc_attr!(rustc_layout_scalar_valid_range_start, "the `#[rustc_layout_scalar_valid_range_start]` attribute is just used to enable \ - niche optimizations in the standard library"), - rustc_attr!(rustc_layout_scalar_valid_range_end, "the `#[rustc_layout_scalar_valid_range_end]` attribute is just used to enable \ - niche optimizations in the standard library"), - rustc_attr!(rustc_simd_monomorphize_lane_limit, "the `#[rustc_simd_monomorphize_lane_limit]` attribute is just used by std::simd \ - for better error messages"), - rustc_attr!(rustc_nonnull_optimization_guaranteed, + rustc_attr!( + rustc_layout_scalar_valid_range_start, + "the `#[rustc_layout_scalar_valid_range_start]` attribute is just used to enable \ + niche optimizations in the standard library", + ), + rustc_attr!( + rustc_layout_scalar_valid_range_end, + "the `#[rustc_layout_scalar_valid_range_end]` attribute is just used to enable \ + niche optimizations in the standard library", + ), + rustc_attr!( + rustc_simd_monomorphize_lane_limit, + "the `#[rustc_simd_monomorphize_lane_limit]` attribute is just used by std::simd \ + for better error messages", + ), + rustc_attr!( + rustc_nonnull_optimization_guaranteed, "the `#[rustc_nonnull_optimization_guaranteed]` attribute is just used to document \ guaranteed niche optimizations in the standard library", "the compiler does not even check whether the type indeed is being non-null-optimized; \ - it is your responsibility to ensure that the attribute is only used on types that are optimized"), + it is your responsibility to ensure that the attribute is only used on types that are optimized", + ), // ========================================================================== // Internal attributes, Misc: // ========================================================================== gated!( - lang,lang_items, - "lang items are subject to change" + lang, lang_items, + "lang items are subject to change", ), - rustc_attr!(rustc_as_ptr, "`#[rustc_as_ptr]` is used to mark functions returning pointers to their inner allocations"), - rustc_attr!(rustc_should_not_be_called_on_const_items, "`#[rustc_should_not_be_called_on_const_items]` is used to mark methods that don't make sense to be called on interior mutable consts"), - rustc_attr!(rustc_pass_by_value, "`#[rustc_pass_by_value]` is used to mark types that must be passed by value instead of reference"), - rustc_attr!(rustc_never_returns_null_ptr, "`#[rustc_never_returns_null_ptr]` is used to mark functions returning non-null pointers"), - rustc_attr!(rustc_no_implicit_autorefs, "`#[rustc_no_implicit_autorefs]` is used to mark functions for which an autoref to the dereference of a raw pointer should not be used as an argument"), - rustc_attr!(rustc_coherence_is_core, "`#![rustc_coherence_is_core]` allows inherent methods on builtin types, only intended to be used in `core`"), - rustc_attr!(rustc_coinductive, "`#[rustc_coinductive]` changes a trait to be coinductive, allowing cycles in the trait solver"), - rustc_attr!(rustc_allow_incoherent_impl, "`#[rustc_allow_incoherent_impl]` has to be added to all impl items of an incoherent inherent impl"), - rustc_attr!(rustc_preserve_ub_checks, "`#![rustc_preserve_ub_checks]` prevents the designated crate from evaluating whether UB checks are enabled when optimizing MIR"), - rustc_attr!(rustc_deny_explicit_impl, + rustc_attr!( + rustc_as_ptr, + "`#[rustc_as_ptr]` is used to mark functions returning pointers to their inner allocations" + ), + rustc_attr!( + rustc_should_not_be_called_on_const_items, + "`#[rustc_should_not_be_called_on_const_items]` is used to mark methods that don't make sense to be called on interior mutable consts" + ), + rustc_attr!( + rustc_pass_by_value, + "`#[rustc_pass_by_value]` is used to mark types that must be passed by value instead of reference" + ), + rustc_attr!( + rustc_never_returns_null_ptr, + "`#[rustc_never_returns_null_ptr]` is used to mark functions returning non-null pointers" + ), + rustc_attr!( + rustc_no_implicit_autorefs, + "`#[rustc_no_implicit_autorefs]` is used to mark functions for which an autoref to the dereference of a raw pointer should not be used as an argument" + ), + rustc_attr!( + rustc_coherence_is_core, + "`#![rustc_coherence_is_core]` allows inherent methods on builtin types, only intended to be used in `core`" + ), + rustc_attr!( + rustc_coinductive, + "`#[rustc_coinductive]` changes a trait to be coinductive, allowing cycles in the trait solver" + ), + rustc_attr!( + rustc_allow_incoherent_impl, + "`#[rustc_allow_incoherent_impl]` has to be added to all impl items of an incoherent inherent impl" + ), + rustc_attr!( + rustc_preserve_ub_checks, + "`#![rustc_preserve_ub_checks]` prevents the designated crate from evaluating whether UB checks are enabled when optimizing MIR", + ), + rustc_attr!( + rustc_deny_explicit_impl, "`#[rustc_deny_explicit_impl]` enforces that a trait can have no user-provided impls" ), - rustc_attr!(rustc_dyn_incompatible_trait, + rustc_attr!( + rustc_dyn_incompatible_trait, "`#[rustc_dyn_incompatible_trait]` marks a trait as dyn-incompatible, \ even if it otherwise satisfies the requirements to be dyn-compatible." ), - rustc_attr!(rustc_has_incoherent_inherent_impls, "`#[rustc_has_incoherent_inherent_impls]` allows the addition of incoherent inherent impls for \ + rustc_attr!( + rustc_has_incoherent_inherent_impls, + "`#[rustc_has_incoherent_inherent_impls]` allows the addition of incoherent inherent impls for \ the given type by annotating all impl items with `#[rustc_allow_incoherent_impl]`" ), - rustc_attr!(rustc_non_const_trait_method, "`#[rustc_non_const_trait_method]` should only used by the standard library to mark trait methods \ + rustc_attr!( + rustc_non_const_trait_method, + "`#[rustc_non_const_trait_method]` should only used by the standard library to mark trait methods \ as non-const to allow large traits an easier transition to const" ), BuiltinAttribute { name: sym::rustc_diagnostic_item, - safety: AttributeSafety::Normal, gate: Gated { feature: sym::rustc_attrs, message: "use of an internal attribute", @@ -717,44 +671,81 @@ pub struct BuiltinAttribute { }, gated!( // Used in resolve: - prelude_import, "`#[prelude_import]` is for use by rustc only", + prelude_import, + "`#[prelude_import]` is for use by rustc only", ), gated!( - rustc_paren_sugar,unboxed_closures, "unboxed_closures are still evolving", + rustc_paren_sugar, + unboxed_closures, "unboxed_closures are still evolving", ), - rustc_attr!(rustc_inherit_overflow_checks,"the `#[rustc_inherit_overflow_checks]` attribute is just used to control \ + rustc_attr!( + rustc_inherit_overflow_checks, + "the `#[rustc_inherit_overflow_checks]` attribute is just used to control \ overflow checking behavior of several functions in the standard library that are inlined \ - across crates" + across crates", ), - rustc_attr!(rustc_reservation_impl,"the `#[rustc_reservation_impl]` attribute is internally used \ + rustc_attr!( + rustc_reservation_impl, + "the `#[rustc_reservation_impl]` attribute is internally used \ for reserving `impl From for T` as part of the effort to stabilize `!`" ), - rustc_attr!(rustc_test_marker, "the `#[rustc_test_marker]` attribute is used internally to track tests"), - rustc_attr!(rustc_unsafe_specialization_marker, + rustc_attr!( + rustc_test_marker, + "the `#[rustc_test_marker]` attribute is used internally to track tests", + ), + rustc_attr!( + rustc_unsafe_specialization_marker, "the `#[rustc_unsafe_specialization_marker]` attribute is used to check specializations" ), - rustc_attr!(rustc_specialization_trait, + rustc_attr!( + rustc_specialization_trait, "the `#[rustc_specialization_trait]` attribute is used to check specializations" ), - rustc_attr!(rustc_main,"the `#[rustc_main]` attribute is used internally to specify test entry point function"), - rustc_attr!(rustc_skip_during_method_dispatch, "the `#[rustc_skip_during_method_dispatch]` attribute is used to exclude a trait \ + rustc_attr!( + rustc_main, + "the `#[rustc_main]` attribute is used internally to specify test entry point function", + ), + rustc_attr!( + rustc_skip_during_method_dispatch, + "the `#[rustc_skip_during_method_dispatch]` attribute is used to exclude a trait \ from method dispatch when the receiver is of the following type, for compatibility in \ editions < 2021 (array) or editions < 2024 (boxed_slice)" ), - rustc_attr!(rustc_must_implement_one_of,"the `#[rustc_must_implement_one_of]` attribute is used to change minimal complete \ + rustc_attr!( + rustc_must_implement_one_of, + "the `#[rustc_must_implement_one_of]` attribute is used to change minimal complete \ definition of a trait. Its syntax and semantics are highly experimental and will be \ subject to change before stabilization", ), - rustc_attr!(rustc_doc_primitive,"the `#[rustc_doc_primitive]` attribute is used by the standard library \ + rustc_attr!( + rustc_doc_primitive, + "the `#[rustc_doc_primitive]` attribute is used by the standard library \ to provide a way to generate documentation for primitive types", ), gated!( - rustc_intrinsic,intrinsics, - "the `#[rustc_intrinsic]` attribute is used to declare intrinsics as function items"), - rustc_attr!(rustc_no_mir_inline,"`#[rustc_no_mir_inline]` prevents the MIR inliner from inlining a function while not affecting codegen" + rustc_intrinsic, intrinsics, + "the `#[rustc_intrinsic]` attribute is used to declare intrinsics as function items", + ), + rustc_attr!( + rustc_no_mir_inline, + "`#[rustc_no_mir_inline]` prevents the MIR inliner from inlining a function while not affecting codegen" + ), + rustc_attr!( + rustc_force_inline, + "`#[rustc_force_inline]` forces a free function to be inlined" + ), + rustc_attr!( + rustc_scalable_vector, + "`#[rustc_scalable_vector]` defines a scalable vector type" + ), + rustc_attr!( + rustc_must_match_exhaustively, + "enums with `#[rustc_must_match_exhaustively]` must be matched on with a match block that mentions all variants explicitly" + ), + rustc_attr!( + rustc_no_writable, + "`#[rustc_no_writable]` stops the compiler from considering mutable reference arguments of this function as implicitly writable" ), - rustc_attr!(rustc_force_inline,"`#[rustc_force_inline]` forces a free function to be inlined"), - rustc_attr!(rustc_scalable_vector,"`#[rustc_scalable_vector]` defines a scalable vector type"), // ========================================================================== // Internal attributes, Testing: @@ -762,14 +753,14 @@ pub struct BuiltinAttribute { rustc_attr!(TEST, rustc_effective_visibility), rustc_attr!(TEST, rustc_dump_inferred_outlives), - rustc_attr!(TEST, rustc_capture_analysis), + rustc_attr!(TEST, rustc_capture_analysis,), rustc_attr!(TEST, rustc_insignificant_dtor), rustc_attr!(TEST, rustc_no_implicit_bounds), rustc_attr!(TEST, rustc_strict_coherence), rustc_attr!(TEST, rustc_dump_variances), rustc_attr!(TEST, rustc_dump_variances_of_opaques), - rustc_attr!(TEST, rustc_hidden_type_of_opaques), - rustc_attr!(TEST, rustc_layout), + rustc_attr!(TEST, rustc_dump_hidden_type_of_opaques), + rustc_attr!(TEST, rustc_dump_layout), rustc_attr!(TEST, rustc_abi), rustc_attr!(TEST, rustc_regions), rustc_attr!(TEST, rustc_delayed_bug_from_inside_query), @@ -781,10 +772,12 @@ pub struct BuiltinAttribute { rustc_attr!(TEST, rustc_partition_reused), rustc_attr!(TEST, rustc_partition_codegened), rustc_attr!(TEST, rustc_expected_cgu_reuse), - rustc_attr!(TEST, rustc_symbol_name), - rustc_attr!(TEST, rustc_def_path), + rustc_attr!(TEST, rustc_dump_symbol_name), + rustc_attr!(TEST, rustc_dump_def_path), rustc_attr!(TEST, rustc_mir), - gated!(custom_mir,"the `#[custom_mir]` attribute is just used for the Rust test suite"), + gated!( + custom_mir, "the `#[custom_mir]` attribute is just used for the Rust test suite", + ), rustc_attr!(TEST, rustc_dump_item_bounds), rustc_attr!(TEST, rustc_dump_predicates), rustc_attr!(TEST, rustc_dump_def_parents), @@ -808,12 +801,3 @@ pub fn is_builtin_attr_name(name: Symbol) -> bool { } map }); - -pub fn is_stable_diagnostic_attribute(sym: Symbol, features: &Features) -> bool { - match sym { - sym::on_unimplemented | sym::do_not_recommend => true, - sym::on_const => features.diagnostic_on_const(), - sym::on_move => features.diagnostic_on_move(), - _ => false, - } -} diff --git a/compiler/rustc_feature/src/lib.rs b/compiler/rustc_feature/src/lib.rs index 40a637bfa0b8..ce3ce6fcccee 100644 --- a/compiler/rustc_feature/src/lib.rs +++ b/compiler/rustc_feature/src/lib.rs @@ -129,9 +129,8 @@ pub fn find_feature_issue(feature: Symbol, issue: GateIssue) -> Option bool { /// Implementation details of externally implementable items (internal, eii_internals, "1.94.0", None), /// Implementation details of field representing types. - (internal, field_representing_type_raw, "CURRENT_RUSTC_VERSION", None), + (internal, field_representing_type_raw, "1.96.0", None), /// Outputs useful `assert!` messages (unstable, generic_assert, "1.63.0", None), /// Allows using the #[rustc_intrinsic] attribute. @@ -258,7 +258,7 @@ pub fn internal(&self, feature: Symbol) -> bool { /// Allows using the `#[stable]` and `#[unstable]` attributes. (internal, staged_api, "1.0.0", None), /// Perma-unstable, only used to test the `incomplete_features` lint. - (incomplete, test_incomplete_feature, "CURRENT_RUSTC_VERSION", None), + (incomplete, test_incomplete_feature, "1.96.0", None), /// Added for testing unstable lints; perma-unstable. (internal, test_unstable_lint, "1.60.0", None), /// Use for stable + negative coherence and strict coherence depending on trait's @@ -410,6 +410,8 @@ pub fn internal(&self, feature: Symbol) -> bool { (unstable, cfg_target_has_atomic, "1.60.0", Some(94039)), /// Allows `cfg(target_has_atomic_equal_alignment = "...")`. (unstable, cfg_target_has_atomic_equal_alignment, "1.60.0", Some(93822)), + /// Allows `cfg(target_object_format = "...")`. + (unstable, cfg_target_object_format, "CURRENT_RUSTC_VERSION", Some(152586)), /// Allows `cfg(target_thread_local)`. (unstable, cfg_target_thread_local, "1.7.0", Some(29594)), /// Allows the use of `#[cfg(ub_checks)` to check if UB checks are enabled. @@ -473,7 +475,9 @@ pub fn internal(&self, feature: Symbol) -> bool { /// Allows giving non-const impls custom diagnostic messages if attempted to be used as const (unstable, diagnostic_on_const, "1.93.0", Some(143874)), /// Allows giving on-move borrowck custom diagnostic messages for a type - (unstable, diagnostic_on_move, "CURRENT_RUSTC_VERSION", Some(154181)), + (unstable, diagnostic_on_move, "1.96.0", Some(154181)), + /// Allows giving unresolved imports a custom diagnostic message + (unstable, diagnostic_on_unknown, "1.96.0", Some(152900)), /// Allows `#[doc(cfg(...))]`. (unstable, doc_cfg, "1.21.0", Some(43781)), /// Allows `#[doc(masked)]`. @@ -505,9 +509,11 @@ pub fn internal(&self, feature: Symbol) -> bool { /// Allows the use of `#[ffi_pure]` on foreign functions. (unstable, ffi_pure, "1.45.0", Some(58329)), /// Experimental field projections. - (incomplete, field_projections, "CURRENT_RUSTC_VERSION", Some(145383)), + (incomplete, field_projections, "1.96.0", Some(145383)), /// Allows marking trait functions as `final` to prevent overriding impls (unstable, final_associated_functions, "1.95.0", Some(131179)), + /// fma4 target feature on x86. + (unstable, fma4_target_feature, "CURRENT_RUSTC_VERSION", Some(155233)), /// Controlling the behavior of fmt::Debug (unstable, fmt_debug, "1.82.0", Some(129709)), /// Allows using `#[align(...)]` on function items @@ -539,7 +545,7 @@ pub fn internal(&self, feature: Symbol) -> bool { /// Target features on hexagon. (unstable, hexagon_target_feature, "1.27.0", Some(150250)), /// Allows `impl(crate) trait Foo` restrictions. - (incomplete, impl_restriction, "CURRENT_RUSTC_VERSION", Some(105077)), + (incomplete, impl_restriction, "1.96.0", Some(105077)), /// Allows `impl Trait` to be used inside associated types (RFC 2515). (unstable, impl_trait_in_assoc_type, "1.70.0", Some(63063)), /// Allows `impl Trait` in bindings (`let`). @@ -572,7 +578,7 @@ pub fn internal(&self, feature: Symbol) -> bool { /// Allow `macro_rules!` derive rules (unstable, macro_derive, "1.91.0", Some(143549)), /// Allow `$x:guard` matcher in macros - (unstable, macro_guard_matcher, "CURRENT_RUSTC_VERSION", Some(153104)), + (unstable, macro_guard_matcher, "1.96.0", Some(153104)), /// Give access to additional metadata about declarative macro meta-variables. (unstable, macro_metavar_expr, "1.61.0", Some(83527)), /// Provides a way to concatenate identifiers using metavariable expressions. @@ -583,7 +589,7 @@ pub fn internal(&self, feature: Symbol) -> bool { (incomplete, mgca_type_const_syntax, "1.95.0", Some(132980)), /// Allows additional const parameter types, such as [u8; 10] or user defined types. /// User defined types must not have fields more private than the type itself. - (unstable, min_adt_const_params, "CURRENT_RUSTC_VERSION", Some(154042)), + (unstable, min_adt_const_params, "1.96.0", Some(154042)), /// Enables the generic const args MVP (only bare paths, not arbitrary computation). (incomplete, min_generic_const_args, "1.84.0", Some(132980)), /// A minimal, sound subset of specialization intended to be used by the diff --git a/compiler/rustc_hir/Cargo.toml b/compiler/rustc_hir/Cargo.toml index 13e73acf0737..c9e54c9bf71d 100644 --- a/compiler/rustc_hir/Cargo.toml +++ b/compiler/rustc_hir/Cargo.toml @@ -13,6 +13,7 @@ rustc_ast = { path = "../rustc_ast" } rustc_ast_pretty = { path = "../rustc_ast_pretty" } rustc_data_structures = { path = "../rustc_data_structures" } rustc_error_messages = { path = "../rustc_error_messages" } +rustc_errors = { path = "../rustc_errors" } rustc_hashes = { path = "../rustc_hashes" } rustc_hir_id = { path = "../rustc_hir_id" } rustc_index = { path = "../rustc_index" } @@ -22,6 +23,6 @@ rustc_serialize = { path = "../rustc_serialize" } rustc_span = { path = "../rustc_span" } rustc_target = { path = "../rustc_target" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_hir/src/attrs/data_structures.rs b/compiler/rustc_hir/src/attrs/data_structures.rs index f18d5a1f190a..05f398058eca 100644 --- a/compiler/rustc_hir/src/attrs/data_structures.rs +++ b/compiler/rustc_hir/src/attrs/data_structures.rs @@ -15,16 +15,14 @@ use rustc_macros::{Decodable, Encodable, HashStable_Generic, PrintAttribute}; use rustc_span::def_id::DefId; use rustc_span::hygiene::Transparency; -use rustc_span::{ErrorGuaranteed, Ident, Span, Symbol, sym}; +use rustc_span::{ErrorGuaranteed, Ident, Span, Symbol}; pub use rustc_target::spec::SanitizerSet; use thin_vec::ThinVec; use crate::attrs::diagnostic::*; use crate::attrs::pretty_printing::PrintAttribute; use crate::limit::Limit; -use crate::{ - DefaultBodyStability, HashIgnoredAttrId, PartialConstStability, RustcVersion, Stability, -}; +use crate::{DefaultBodyStability, PartialConstStability, RustcVersion, Stability}; #[derive(Copy, Clone, Debug, HashStable_Generic, Encodable, Decodable, PrintAttribute)] pub enum EiiImplResolution { @@ -759,12 +757,12 @@ fn into_diag_arg(self, _: &mut Option) -> DiagArgValue { } #[derive(Clone, Debug, HashStable_Generic, Encodable, Decodable, PrintAttribute)] -pub enum RustcLayoutType { - Abi, +pub enum RustcDumpLayoutKind { Align, - Size, - HomogenousAggregate, + BackendRepr, Debug, + HomogenousAggregate, + Size, } #[derive(Clone, Debug, HashStable_Generic, Encodable, Decodable, PrintAttribute, PartialEq, Eq)] @@ -897,140 +895,11 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } #[derive(Clone, Debug, HashStable_Generic, Encodable, Decodable, PrintAttribute)] -pub struct LintAttribute { - /// See RFC #2383 - pub reason: Option, - pub kind: LintAttributeKind, - pub attr_style: AttrStyle, - pub attr_span: Span, - /// Needed by `LintExpectationId` to track fulfilled expectations - pub attr_id: HashIgnoredAttrId, - pub lint_instances: ThinVec, -} - -#[derive(Debug, Clone, Encodable, Decodable, HashStable_Generic)] -pub struct LintInstance { - /// The span of the `MetaItem` that produced this `LintInstance` - span: Span, - /// The fully resolved name of the lint - /// for renamed lints, this gets updated to match the new name - lint_name: Symbol, - /// The raw identifier for resolving this lint - /// if this is none, lint_name never diffed from the original - /// name after parsing, original_name.unwrap_or(self.lint_name) - original_name: Option, - /// Index of this lint, used to keep track of lint groups - lint_index: usize, - kind: LintAttrTool, -} - -impl fmt::Display for LintInstance { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.full_lint().fmt(f) - } -} - -impl LintInstance { - pub fn new( - original_name: Symbol, - long_lint_name: String, - span: Span, - lint_index: usize, - ) -> Self { - let original_name = (original_name.as_str() != long_lint_name).then_some(original_name); - let mut tool_name = None; - - let lint_name = match long_lint_name.split_once("::") { - Some((new_tool_name, lint_name)) => { - tool_name = Some(Symbol::intern(new_tool_name)); - Symbol::intern(lint_name) - } - None => Symbol::intern(&long_lint_name), - }; - let kind = match tool_name { - Some(tool_name) => { - let full_lint = Symbol::intern(&format!("{tool_name}::{lint_name}",)); - LintAttrTool::Present { tool_name, full_lint } - } - None => LintAttrTool::NoTool, - }; - - Self { original_name, span, lint_index, lint_name, kind } - } - - pub fn full_lint(&self) -> Symbol { - match self.kind { - LintAttrTool::Present { full_lint, .. } => full_lint, - LintAttrTool::NoTool => self.lint_name, - } - } - - pub fn span(&self) -> Span { - self.span - } - - pub fn lint_index(&self) -> usize { - self.lint_index - } - - pub fn lint_name(&self) -> Symbol { - self.lint_name - } - - pub fn original_name_without_tool(&self) -> Symbol { - let full_original_lint_name = self.original_lint_name(); - match self.kind { - LintAttrTool::Present { tool_name, .. } => Symbol::intern( - full_original_lint_name - .as_str() - .trim_start_matches(tool_name.as_str()) - .trim_start_matches("::"), - ), - LintAttrTool::NoTool => full_original_lint_name, - } - } - - pub fn tool_name(&self) -> Option { - if let LintAttrTool::Present { tool_name, .. } = self.kind { Some(tool_name) } else { None } - } - - pub fn tool_is_named(&self, other: Symbol) -> bool { - self.tool_name().is_some_and(|tool_name| tool_name == other) - } - - pub fn original_lint_name(&self) -> Symbol { - match self.original_name { - Some(name) => name, - None => self.full_lint(), - } - } -} - -#[derive(Debug, Clone, PrintAttribute, Encodable, Decodable, HashStable_Generic)] -enum LintAttrTool { - Present { tool_name: Symbol, full_lint: Symbol }, - NoTool, -} - -#[derive(Clone, Copy, Debug, HashStable_Generic, Encodable, Decodable, PrintAttribute, PartialEq)] -pub enum LintAttributeKind { - Allow, - Deny, - Expect, - Forbid, - Warn, -} - -impl LintAttributeKind { - pub const fn symbol(&self) -> Symbol { - match self { - Self::Allow => sym::allow, - Self::Deny => sym::deny, - Self::Expect => sym::expect, - Self::Forbid => sym::forbid, - Self::Warn => sym::warn, - } - } +pub struct UnstableRemovedFeature { + pub feature: Symbol, + pub reason: Symbol, + pub link: Symbol, + pub since: RustcVersion, } /// Represents parsed *built-in* inert attributes. @@ -1236,9 +1105,6 @@ pub enum AttributeKind { /// Represents `#[linkage]`. Linkage(Linkage, Span), - /// Represents `#[allow]`, `#[expect]`, `#[warn]`, `#[deny]`, `#[forbid]` - LintAttributes(ThinVec), - /// Represents `#[loop_match]`. LoopMatch(Span), @@ -1334,6 +1200,14 @@ pub enum AttributeKind { /// None if the directive was malformed in some way. directive: Option>, }, + + /// Represents `#[diagnostic::on_unknown]` + OnUnknown { + span: Span, + /// None if the directive was malformed in some way. + directive: Option>, + }, + /// Represents `#[optimize(size|speed)]` Optimize(OptimizeAttr, Span), @@ -1359,9 +1233,6 @@ pub enum AttributeKind { /// Represents `#[pin_v2]` PinV2(Span), - /// Represents `#[pointee]` - Pointee(Span), - /// Represents `#[prelude_import]` PreludeImport, @@ -1465,9 +1336,7 @@ pub enum AttributeKind { /// Represents `#[rustc_confusables]`. RustcConfusables { - symbols: ThinVec, - // FIXME(jdonszelmann): remove when target validation code is moved - first_span: Span, + confusables: ThinVec, }, /// Represents `#[rustc_const_stable]` and `#[rustc_const_unstable]`. RustcConstStability { @@ -1485,9 +1354,6 @@ pub enum AttributeKind { /// Represents `#[rustc_deallocator]` RustcDeallocator, - /// Represents `#[rustc_def_path]` - RustcDefPath(Span), - /// Represents `#[rustc_delayed_bug_from_inside_query]` RustcDelayedBugFromInsideQuery, @@ -1513,18 +1379,30 @@ pub enum AttributeKind { /// Represents `#[rustc_dump_def_parents]` RustcDumpDefParents, + /// Represents `#[rustc_dump_def_path]` + RustcDumpDefPath(Span), + + /// Represents `#[rustc_dump_hidden_type_of_opaques]` + RustcDumpHiddenTypeOfOpaques, + /// Represents `#[rustc_dump_inferred_outlives]` RustcDumpInferredOutlives, /// Represents `#[rustc_dump_item_bounds]` RustcDumpItemBounds, + /// Represents `#[rustc_dump_layout]` + RustcDumpLayout(ThinVec), + /// Represents `#[rustc_dump_object_lifetime_defaults]`. RustcDumpObjectLifetimeDefaults, /// Represents `#[rustc_dump_predicates]` RustcDumpPredicates, + /// Represents `#[rustc_dump_symbol_name]` + RustcDumpSymbolName(Span), + /// Represents `#[rustc_dump_user_args]` RustcDumpUserArgs, @@ -1551,9 +1429,6 @@ pub enum AttributeKind { RustcHasIncoherentInherentImpls, - /// Represents `#[rustc_hidden_type_of_opaques]` - RustcHiddenTypeOfOpaques, - /// Represents `#[rustc_if_this_changed]` RustcIfThisChanged(Span, Option), @@ -1569,9 +1444,6 @@ pub enum AttributeKind { /// Represents `#[rustc_intrinsic_const_stable_indirect]` RustcIntrinsicConstStableIndirect, - /// Represents `#[rustc_layout]` - RustcLayout(ThinVec), - /// Represents `#[rustc_layout_scalar_valid_range_end]`. RustcLayoutScalarValidRangeEnd(Box, Span), @@ -1613,6 +1485,9 @@ pub enum AttributeKind { fn_names: ThinVec, }, + /// Represents `#[rustc_must_match_exhaustively]` + RustcMustMatchExhaustively(Span), + /// Represents `#[rustc_never_returns_null_ptr]` RustcNeverReturnsNullPtr, @@ -1631,6 +1506,9 @@ pub enum AttributeKind { /// Represents `#[rustc_no_mir_inline]` RustcNoMirInline, + /// Represents `#[rustc_no_writable]` + RustcNoWritable, + /// Represents `#[rustc_non_const_trait_method]`. RustcNonConstTraitMethod, @@ -1712,9 +1590,6 @@ pub enum AttributeKind { /// Represents `#[rustc_strict_coherence]`. RustcStrictCoherence(Span), - /// Represents `#[rustc_symbol_name]` - RustcSymbolName(Span), - /// Represents `#[rustc_test_marker]` RustcTestMarker(Symbol), @@ -1779,6 +1654,9 @@ pub enum AttributeKind { /// Represents `#[unstable_feature_bound]`. UnstableFeatureBound(ThinVec<(Symbol, Span)>), + /// Represents all `#![unstable_removed(...)]` features + UnstableRemoved(ThinVec), + /// Represents `#[used]` Used { used_by: UsedBy, diff --git a/compiler/rustc_hir/src/attrs/encode_cross_crate.rs b/compiler/rustc_hir/src/attrs/encode_cross_crate.rs index 6612ebd6135b..ad4d0728888b 100644 --- a/compiler/rustc_hir/src/attrs/encode_cross_crate.rs +++ b/compiler/rustc_hir/src/attrs/encode_cross_crate.rs @@ -56,7 +56,6 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { LinkOrdinal { .. } => No, LinkSection { .. } => Yes, // Needed for rustdoc Linkage(..) => No, - LintAttributes { .. } => No, LoopMatch(..) => No, MacroEscape(..) => No, MacroExport { .. } => Yes, @@ -80,13 +79,13 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { OnConst { .. } => Yes, OnMove { .. } => Yes, OnUnimplemented { .. } => Yes, + OnUnknown { .. } => Yes, Optimize(..) => No, PanicRuntime => No, PatchableFunctionEntry { .. } => Yes, Path(..) => No, PatternComplexityLimit { .. } => No, PinV2(..) => Yes, - Pointee(..) => No, PreludeImport => No, ProcMacro(..) => No, ProcMacroAttribute(..) => No, @@ -117,7 +116,6 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { RustcConstStableIndirect => No, RustcConversionSuggestion => Yes, RustcDeallocator => No, - RustcDefPath(..) => No, RustcDelayedBugFromInsideQuery => No, RustcDenyExplicitImpl(..) => No, RustcDeprecatedSafe2024 { .. } => Yes, @@ -126,10 +124,14 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { RustcDocPrimitive(..) => Yes, RustcDummy => No, RustcDumpDefParents => No, + RustcDumpDefPath(..) => No, + RustcDumpHiddenTypeOfOpaques => No, RustcDumpInferredOutlives => No, RustcDumpItemBounds => No, + RustcDumpLayout(..) => No, RustcDumpObjectLifetimeDefaults => No, RustcDumpPredicates => No, + RustcDumpSymbolName(..) => Yes, RustcDumpUserArgs => No, RustcDumpVariances => No, RustcDumpVariancesOfOpaques => No, @@ -139,13 +141,11 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { RustcEiiForeignItem => No, RustcEvaluateWhereClauses => Yes, RustcHasIncoherentInherentImpls => Yes, - RustcHiddenTypeOfOpaques => No, RustcIfThisChanged(..) => No, RustcInheritOverflowChecks => No, RustcInsignificantDtor => Yes, RustcIntrinsic => Yes, RustcIntrinsicConstStableIndirect => No, - RustcLayout(..) => No, RustcLayoutScalarValidRangeEnd(..) => Yes, RustcLayoutScalarValidRangeStart(..) => Yes, RustcLegacyConstGenerics { .. } => Yes, @@ -157,11 +157,13 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { RustcMain => No, RustcMir(..) => Yes, RustcMustImplementOneOf { .. } => No, + RustcMustMatchExhaustively(..) => Yes, RustcNeverReturnsNullPtr => Yes, RustcNeverTypeOptions { .. } => No, RustcNoImplicitAutorefs => Yes, RustcNoImplicitBounds => No, RustcNoMirInline => Yes, + RustcNoWritable => Yes, RustcNonConstTraitMethod => No, // should be reported via other queries like `constness` RustcNonnullOptimizationGuaranteed => Yes, RustcNounwind => No, @@ -184,7 +186,6 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { RustcSpecializationTrait(..) => No, RustcStdInternalSymbol(..) => No, RustcStrictCoherence(..) => Yes, - RustcSymbolName(..) => Yes, RustcTestMarker(..) => No, RustcThenThisWouldNeed(..) => No, RustcTrivialFieldReads => Yes, @@ -198,6 +199,7 @@ pub fn encode_cross_crate(&self) -> EncodeCrossCrate { TrackCaller(..) => Yes, TypeLengthLimit { .. } => No, UnstableFeatureBound(..) => No, + UnstableRemoved(..) => Yes, Used { .. } => No, WindowsSubsystem(..) => No, // tidy-alphabetical-end diff --git a/compiler/rustc_hir/src/attrs/pretty_printing.rs b/compiler/rustc_hir/src/attrs/pretty_printing.rs index 811b250b6fcd..9d14f9de3078 100644 --- a/compiler/rustc_hir/src/attrs/pretty_printing.rs +++ b/compiler/rustc_hir/src/attrs/pretty_printing.rs @@ -17,8 +17,6 @@ use rustc_target::spec::SanitizerSet; use thin_vec::ThinVec; -use crate::HashIgnoredAttrId; -use crate::attrs::LintInstance; use crate::limit::Limit; /// This trait is used to print attributes in `rustc_hir_pretty`. @@ -193,8 +191,8 @@ fn print_attribute(&self, p: &mut Printer) { } print_tup!(A B C D E F G H); -print_skip!(Span, (), ErrorGuaranteed, AttrId, HashIgnoredAttrId); -print_disp!(u8, u16, u32, u128, usize, bool, NonZero, Limit, LintInstance); +print_skip!(Span, (), ErrorGuaranteed, AttrId); +print_disp!(u8, u16, u32, u128, usize, bool, NonZero, Limit); print_debug!( Symbol, Ident, diff --git a/compiler/rustc_hir/src/definitions.rs b/compiler/rustc_hir/src/definitions.rs index 5e361891f6d0..d18653f6267a 100644 --- a/compiler/rustc_hir/src/definitions.rs +++ b/compiler/rustc_hir/src/definitions.rs @@ -97,11 +97,34 @@ pub fn enumerated_keys_and_path_hashes( } } -#[derive(Debug)] +pub trait Disambiguator { + fn entry(&mut self, parent: LocalDefId, data: DefPathData) -> &mut u32; +} + +#[derive(Debug, Default, Clone)] +pub struct PerParentDisambiguatorState { + next: UnordMap, +} + +impl Disambiguator for PerParentDisambiguatorState { + #[inline] + fn entry(&mut self, _: LocalDefId, data: DefPathData) -> &mut u32 { + self.next.entry(data).or_insert(0) + } +} + +#[derive(Debug, Default, Clone)] pub struct DisambiguatorState { next: UnordMap<(LocalDefId, DefPathData), u32>, } +impl Disambiguator for DisambiguatorState { + #[inline] + fn entry(&mut self, parent: LocalDefId, data: DefPathData) -> &mut u32 { + self.next.entry((parent, data)).or_insert(0) + } +} + impl DisambiguatorState { pub const fn new() -> Self { Self { next: Default::default() } @@ -302,10 +325,6 @@ pub enum DefPathData { Ctor, /// A constant expression (see `{ast,hir}::AnonConst`). AnonConst, - /// A constant expression created during AST->HIR lowering.. - LateAnonConst, - /// A fresh anonymous lifetime created by desugaring elided lifetimes. - DesugaredAnonymousLifetime, /// An existential `impl Trait` type node. /// Argument position `impl Trait` have a `TypeNs` with their pretty-printed name. OpaqueTy, @@ -389,7 +408,7 @@ pub fn create_def( &mut self, parent: LocalDefId, data: DefPathData, - disambiguator: &mut DisambiguatorState, + disambiguator: &mut impl Disambiguator, ) -> LocalDefId { // We can't use `Debug` implementation for `LocalDefId` here, since it tries to acquire a // reference to `Definitions` and we're already holding a mutable reference. @@ -403,7 +422,7 @@ pub fn create_def( // Find the next free disambiguator for this key. let disambiguator = { - let next_disamb = disambiguator.next.entry((parent, data)).or_insert(0); + let next_disamb = disambiguator.entry(parent, data); let disambiguator = *next_disamb; *next_disamb = next_disamb.checked_add(1).expect("disambiguator overflow"); disambiguator @@ -458,8 +477,6 @@ pub fn get_opt_name(&self) -> Option { TypeNs(name) | ValueNs(name) | MacroNs(name) | LifetimeNs(name) | OpaqueLifetime(name) => Some(name), - DesugaredAnonymousLifetime => Some(kw::UnderscoreLifetime), - Impl | ForeignMod | CrateRoot @@ -468,7 +485,6 @@ pub fn get_opt_name(&self) -> Option { | Closure | Ctor | AnonConst - | LateAnonConst | OpaqueTy | AnonAssocTy(..) | SyntheticCoroutineBody @@ -482,8 +498,6 @@ fn hashed_symbol(&self) -> Option { TypeNs(name) | ValueNs(name) | MacroNs(name) | LifetimeNs(name) | AnonAssocTy(name) | OpaqueLifetime(name) => Some(name), - DesugaredAnonymousLifetime => Some(kw::UnderscoreLifetime), - Impl | ForeignMod | CrateRoot @@ -492,7 +506,6 @@ fn hashed_symbol(&self) -> Option { | Closure | Ctor | AnonConst - | LateAnonConst | OpaqueTy | SyntheticCoroutineBody | NestedStatic => None, @@ -512,8 +525,7 @@ pub fn name(&self) -> DefPathDataName { GlobalAsm => DefPathDataName::Anon { namespace: sym::global_asm }, Closure => DefPathDataName::Anon { namespace: sym::closure }, Ctor => DefPathDataName::Anon { namespace: sym::constructor }, - AnonConst | LateAnonConst => DefPathDataName::Anon { namespace: sym::constant }, - DesugaredAnonymousLifetime => DefPathDataName::Named(kw::UnderscoreLifetime), + AnonConst => DefPathDataName::Anon { namespace: sym::constant }, OpaqueTy => DefPathDataName::Anon { namespace: sym::opaque }, AnonAssocTy(..) => DefPathDataName::Anon { namespace: sym::anon_assoc }, SyntheticCoroutineBody => DefPathDataName::Anon { namespace: sym::synthetic }, diff --git a/compiler/rustc_hir/src/hir.rs b/compiler/rustc_hir/src/hir.rs index 71ef6c9a9c03..d8149b4e30a5 100644 --- a/compiler/rustc_hir/src/hir.rs +++ b/compiler/rustc_hir/src/hir.rs @@ -1304,19 +1304,6 @@ pub fn is_parsed_attr(&self) -> bool { Attribute::Unparsed(_) => false, } } - - pub fn has_span_without_desugaring_kind(&self) -> bool { - let span = match self { - Attribute::Unparsed(attr) => attr.span, - Attribute::Parsed(AttributeKind::Deprecated { span, .. }) => *span, - Attribute::Parsed(AttributeKind::LintAttributes(sub_attrs)) => { - return sub_attrs.iter().any(|attr| attr.attr_span.desugaring_kind().is_none()); - } - Attribute::Parsed(attr) => panic!("can't get span of parsed attr: {:?}", attr), - }; - - span.desugaring_kind().is_none() - } } impl AttributeExt for Attribute { @@ -1391,7 +1378,6 @@ fn span(&self) -> Span { Attribute::Parsed(AttributeKind::DocComment { span, .. }) => *span, Attribute::Parsed(AttributeKind::Deprecated { span, .. }) => *span, Attribute::Parsed(AttributeKind::CfgTrace(cfgs)) => cfgs[0].1, - Attribute::Parsed(AttributeKind::LintAttributes(sub_attrs)) => sub_attrs[0].attr_span, a => panic!("can't get the span of an arbitrary parsed attribute: {a:?}"), } } @@ -1645,6 +1631,10 @@ pub struct OwnerInfo<'hir> { /// Lints delayed during ast lowering to be emitted /// after hir has completely built + /// + /// WARNING: The delayed lints are not hashed as a part of the `OwnerInfo`, and therefore + /// should only be accessed in `eval_always` queries. + #[stable_hasher(ignore)] pub delayed_lints: DelayedLints, } @@ -3931,6 +3921,117 @@ pub struct Param<'hir> { pub span: Span, } +/// Contains the packed non-type fields of a function declaration. +// FIXME(splat): add the splatted argument index as a u16 +#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] +#[derive(Encodable, Decodable, HashStable_Generic)] +pub struct FnDeclFlags { + /// Holds the c_variadic and lifetime_elision_allowed bitflags, and 3 bits for the `ImplicitSelfKind`. + flags: u8, +} + +impl fmt::Debug for FnDeclFlags { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let mut f = f.debug_tuple("FnDeclFlags"); + f.field(&format!("ImplicitSelfKind({:?})", self.implicit_self())); + + if self.lifetime_elision_allowed() { + f.field(&"LifetimeElisionAllowed"); + } else { + f.field(&"NoLifetimeElision"); + }; + + if self.c_variadic() { + f.field(&"CVariadic"); + }; + + f.finish() + } +} + +impl FnDeclFlags { + /// Mask for the implicit self kind. + const IMPLICIT_SELF_MASK: u8 = 0b111; + + /// Bitflag for a trailing C-style variadic argument. + const C_VARIADIC_FLAG: u8 = 1 << 3; + + /// Bitflag for lifetime elision. + const LIFETIME_ELISION_ALLOWED_FLAG: u8 = 1 << 4; + + /// Create a new FnDeclKind with no implicit self, no lifetime elision, and no C-style variadic argument. + /// To modify these flags, use the `set_*` methods, for readability. + // FIXME: use Default instead when that trait is const stable. + pub const fn default() -> Self { + Self { flags: 0 } + .set_implicit_self(ImplicitSelfKind::None) + .set_lifetime_elision_allowed(false) + .set_c_variadic(false) + } + + /// Set the implicit self kind. + #[must_use = "this method does not modify the receiver"] + pub const fn set_implicit_self(mut self, implicit_self: ImplicitSelfKind) -> Self { + self.flags &= !Self::IMPLICIT_SELF_MASK; + + match implicit_self { + ImplicitSelfKind::None => self.flags |= 0, + ImplicitSelfKind::Imm => self.flags |= 1, + ImplicitSelfKind::Mut => self.flags |= 2, + ImplicitSelfKind::RefImm => self.flags |= 3, + ImplicitSelfKind::RefMut => self.flags |= 4, + } + + self + } + + /// Set the C-style variadic argument flag. + #[must_use = "this method does not modify the receiver"] + pub const fn set_c_variadic(mut self, c_variadic: bool) -> Self { + if c_variadic { + self.flags |= Self::C_VARIADIC_FLAG; + } else { + self.flags &= !Self::C_VARIADIC_FLAG; + } + + self + } + + /// Set the lifetime elision allowed flag. + #[must_use = "this method does not modify the receiver"] + pub const fn set_lifetime_elision_allowed(mut self, allowed: bool) -> Self { + if allowed { + self.flags |= Self::LIFETIME_ELISION_ALLOWED_FLAG; + } else { + self.flags &= !Self::LIFETIME_ELISION_ALLOWED_FLAG; + } + + self + } + + /// Get the implicit self kind. + pub const fn implicit_self(self) -> ImplicitSelfKind { + match self.flags & Self::IMPLICIT_SELF_MASK { + 0 => ImplicitSelfKind::None, + 1 => ImplicitSelfKind::Imm, + 2 => ImplicitSelfKind::Mut, + 3 => ImplicitSelfKind::RefImm, + 4 => ImplicitSelfKind::RefMut, + _ => unreachable!(), + } + } + + /// Do the function arguments end with a C-style variadic argument? + pub const fn c_variadic(self) -> bool { + self.flags & Self::C_VARIADIC_FLAG != 0 + } + + /// Is lifetime elision allowed? + pub const fn lifetime_elision_allowed(self) -> bool { + self.flags & Self::LIFETIME_ELISION_ALLOWED_FLAG != 0 + } +} + /// Represents the header (not the body) of a function declaration. #[derive(Debug, Clone, Copy, HashStable_Generic)] pub struct FnDecl<'hir> { @@ -3939,11 +4040,8 @@ pub struct FnDecl<'hir> { /// Additional argument data is stored in the function's [body](Body::params). pub inputs: &'hir [Ty<'hir>], pub output: FnRetTy<'hir>, - pub c_variadic: bool, - /// Does the function have an implicit self? - pub implicit_self: ImplicitSelfKind, - /// Is lifetime elision allowed. - pub lifetime_elision_allowed: bool, + /// The packed function declaration attributes. + pub fn_decl_kind: FnDeclFlags, } impl<'hir> FnDecl<'hir> { @@ -3966,6 +4064,26 @@ pub fn opt_delegation_generics(&self) -> Option<&'hir DelegationGenerics> { None } + + pub fn implicit_self(&self) -> ImplicitSelfKind { + self.fn_decl_kind.implicit_self() + } + + pub fn c_variadic(&self) -> bool { + self.fn_decl_kind.c_variadic() + } + + pub fn lifetime_elision_allowed(&self) -> bool { + self.fn_decl_kind.lifetime_elision_allowed() + } + + pub fn dummy(span: Span) -> Self { + Self { + inputs: &[], + output: FnRetTy::DefaultReturn(span), + fn_decl_kind: FnDeclFlags::default().set_lifetime_elision_allowed(true), + } + } } /// Represents what type of implicit self a function has, if any. @@ -4340,13 +4458,14 @@ pub fn is_struct_or_union(&self) -> bool { Constness, IsAuto, Safety, + &'hir ImplRestriction<'hir>, Ident, &'hir Generics<'hir>, GenericBounds<'hir>, &'hir [TraitItemId] ), - ItemKind::Trait(constness, is_auto, safety, ident, generics, bounds, items), - (*constness, *is_auto, *safety, *ident, generics, bounds, items); + ItemKind::Trait(constness, is_auto, safety, impl_restriction, ident, generics, bounds, items), + (*constness, *is_auto, *safety, impl_restriction, *ident, generics, bounds, items); expect_trait_alias, (Constness, Ident, &'hir Generics<'hir>, GenericBounds<'hir>), ItemKind::TraitAlias(constness, ident, generics, bounds), (*constness, *ident, generics, bounds); @@ -4415,6 +4534,20 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } } +#[derive(Debug, Clone, Copy, HashStable_Generic)] +pub struct ImplRestriction<'hir> { + pub kind: RestrictionKind<'hir>, + pub span: Span, +} + +#[derive(Debug, Clone, Copy, HashStable_Generic)] +pub enum RestrictionKind<'hir> { + /// The restriction does not affect the item. + Unrestricted, + /// The restriction only applies outside of this path. + Restricted(&'hir Path<'hir, DefId>), +} + /// The actual safety specified in syntax. We may treat /// its safety different within the type system to create a /// "sound by default" system that needs checking this enum @@ -4527,6 +4660,7 @@ pub enum ItemKind<'hir> { Constness, IsAuto, Safety, + &'hir ImplRestriction<'hir>, Ident, &'hir Generics<'hir>, GenericBounds<'hir>, @@ -4577,7 +4711,7 @@ pub fn ident(&self) -> Option { | ItemKind::Enum(ident, ..) | ItemKind::Struct(ident, ..) | ItemKind::Union(ident, ..) - | ItemKind::Trait(_, _, _, ident, ..) + | ItemKind::Trait(_, _, _, _, ident, ..) | ItemKind::TraitAlias(_, ident, ..) => Some(ident), ItemKind::Use(_, UseKind::Glob | UseKind::ListStem) @@ -4595,7 +4729,7 @@ pub fn generics(&self) -> Option<&Generics<'_>> { | ItemKind::Enum(_, generics, _) | ItemKind::Struct(_, generics, _) | ItemKind::Union(_, generics, _) - | ItemKind::Trait(_, _, _, _, generics, _, _) + | ItemKind::Trait(_, _, _, _, _, generics, _, _) | ItemKind::TraitAlias(_, _, generics, _) | ItemKind::Impl(Impl { generics, .. }) => generics, _ => return None, diff --git a/compiler/rustc_hir/src/intravisit.rs b/compiler/rustc_hir/src/intravisit.rs index 25ef56f8b0f2..9f7c9af79b75 100644 --- a/compiler/rustc_hir/src/intravisit.rs +++ b/compiler/rustc_hir/src/intravisit.rs @@ -622,11 +622,15 @@ pub fn walk_item<'v, V: Visitor<'v>>(visitor: &mut V, item: &'v Item<'v>) -> V:: _constness, _is_auto, _safety, + ref impl_restriction, ident, ref generics, bounds, trait_item_refs, ) => { + if let RestrictionKind::Restricted(path) = &impl_restriction.kind { + walk_list!(visitor, visit_path_segment, path.segments); + } try_visit!(visitor.visit_ident(ident)); try_visit!(visitor.visit_generics(generics)); walk_list!(visitor, visit_param_bound, bounds); @@ -1212,8 +1216,7 @@ pub fn walk_fn_decl<'v, V: Visitor<'v>>( visitor: &mut V, function_declaration: &'v FnDecl<'v>, ) -> V::Result { - let FnDecl { inputs, output, c_variadic: _, implicit_self: _, lifetime_elision_allowed: _ } = - function_declaration; + let FnDecl { inputs, output, fn_decl_kind: _ } = function_declaration; walk_list!(visitor, visit_ty_unambig, *inputs); visitor.visit_fn_ret_ty(output) } diff --git a/compiler/rustc_hir/src/lang_items.rs b/compiler/rustc_hir/src/lang_items.rs index c144f0b7dbc5..bdf63abc7a85 100644 --- a/compiler/rustc_hir/src/lang_items.rs +++ b/compiler/rustc_hir/src/lang_items.rs @@ -221,6 +221,7 @@ fn hash_stable(&self, _: &mut Hcx, hasher: &mut StableHasher) { UnsafeCell, sym::unsafe_cell, unsafe_cell_type, Target::Struct, GenericRequirement::None; UnsafePinned, sym::unsafe_pinned, unsafe_pinned_type, Target::Struct, GenericRequirement::None; + VaArgSafe, sym::va_arg_safe, va_arg_safe, Target::Trait, GenericRequirement::None; VaList, sym::va_list, va_list, Target::Struct, GenericRequirement::None; Deref, sym::deref, deref_trait, Target::Trait, GenericRequirement::Exact(0); @@ -443,6 +444,9 @@ fn hash_stable(&self, _: &mut Hcx, hasher: &mut StableHasher) { FieldBase, sym::field_base, field_base, Target::AssocTy, GenericRequirement::Exact(0); FieldType, sym::field_type, field_type, Target::AssocTy, GenericRequirement::Exact(0); FieldOffset, sym::field_offset, field_offset, Target::AssocConst, GenericRequirement::Exact(0); + + // Used to fallback `{float}` to `f32` when `f32: From<{float}>` + From, sym::From, from_trait, Target::Trait, GenericRequirement::Exact(1); } /// The requirement imposed on the generics of a lang item diff --git a/compiler/rustc_hir/src/lints.rs b/compiler/rustc_hir/src/lints.rs index 1589a6de220e..d7bd9f874dd2 100644 --- a/compiler/rustc_hir/src/lints.rs +++ b/compiler/rustc_hir/src/lints.rs @@ -1,17 +1,12 @@ -use rustc_data_structures::fingerprint::Fingerprint; +use rustc_data_structures::sync::{DynSend, DynSync}; +use rustc_error_messages::MultiSpan; +use rustc_errors::{Diag, DiagCtxtHandle, Level}; use rustc_lint_defs::LintId; pub use rustc_lint_defs::{AttributeLintKind, FormatWarning}; -use rustc_macros::HashStable_Generic; -use rustc_span::Span; use crate::HirId; -#[derive(Debug)] -pub struct DelayedLints { - pub lints: Box<[DelayedLint]>, - // Only present when the crate hash is needed. - pub opt_hash: Option, -} +pub type DelayedLints = Box<[DelayedLint]>; /// During ast lowering, no lints can be emitted. /// That is because lints attach to nodes either in the AST, or on the built HIR. @@ -19,15 +14,35 @@ pub struct DelayedLints { /// and then there's a gap where no lints can be emitted until HIR is done. /// The variants in this enum represent lints that are temporarily stashed during /// AST lowering to be emitted once HIR is built. -#[derive(Debug, HashStable_Generic)] +#[derive(Debug)] pub enum DelayedLint { - AttributeParsing(AttributeLint), + AttributeParsing(AttributeLint), + Dynamic(DynAttribute), } -#[derive(Debug, HashStable_Generic)] -pub struct AttributeLint { +#[derive(Debug)] +pub struct AttributeLint { pub lint_id: LintId, - pub id: Id, - pub span: Span, + pub id: HirId, + pub span: MultiSpan, pub kind: AttributeLintKind, } + +pub struct DynAttribute { + pub lint_id: LintId, + pub id: HirId, + pub span: MultiSpan, + pub callback: Box< + dyn for<'a> Fn(DiagCtxtHandle<'a>, Level) -> Diag<'a, ()> + DynSend + DynSync + 'static, + >, +} + +impl std::fmt::Debug for DynAttribute { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("DynAttribute") + .field("lint_id", &self.lint_id) + .field("id", &self.id) + .field("span", &self.span) + .finish() + } +} diff --git a/compiler/rustc_hir/src/stable_hash_impls.rs b/compiler/rustc_hir/src/stable_hash_impls.rs index f2cfeaf027f3..3a10f790cd5c 100644 --- a/compiler/rustc_hir/src/stable_hash_impls.rs +++ b/compiler/rustc_hir/src/stable_hash_impls.rs @@ -7,7 +7,6 @@ AttributeMap, BodyId, ForeignItemId, ImplItemId, ItemId, OwnerNodes, TraitItemId, }; use crate::hir_id::ItemLocalId; -use crate::lints::DelayedLints; impl ToStableHashKey for BodyId { type KeyType = (DefPathHash, ItemLocalId); @@ -74,13 +73,6 @@ fn hash_stable(&self, hcx: &mut Hcx, hasher: &mut StableHasher) { } } -impl HashStable for DelayedLints { - fn hash_stable(&self, hcx: &mut Hcx, hasher: &mut StableHasher) { - let DelayedLints { opt_hash, .. } = *self; - opt_hash.unwrap().hash_stable(hcx, hasher); - } -} - impl<'tcx, Hcx: HashStableContext> HashStable for AttributeMap<'tcx> { fn hash_stable(&self, hcx: &mut Hcx, hasher: &mut StableHasher) { // We ignore the `map` since it refers to information included in `opt_hash` which is diff --git a/compiler/rustc_hir_analysis/src/check/check.rs b/compiler/rustc_hir_analysis/src/check/check.rs index b55506117c1d..d825d1ab5168 100644 --- a/compiler/rustc_hir_analysis/src/check/check.rs +++ b/compiler/rustc_hir_analysis/src/check/check.rs @@ -91,7 +91,7 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { } pub fn check_custom_abi(tcx: TyCtxt<'_>, def_id: LocalDefId, fn_sig: FnSig<'_>, fn_sig_span: Span) { - if fn_sig.abi == ExternAbi::Custom { + if fn_sig.abi() == ExternAbi::Custom { // Function definitions that use `extern "custom"` must be naked functions. if !find_attr!(tcx, def_id, Naked(_)) { tcx.dcx().emit_err(crate::errors::AbiCustomClothedFunction { @@ -523,8 +523,8 @@ fn sanity_check_found_hidden_type<'tcx>( // Nothing was actually constrained. return Ok(()); } - if let &ty::Alias(alias @ ty::AliasTy { kind: ty::Opaque { def_id }, .. }) = ty.ty.kind() { - if def_id == key.def_id.to_def_id() && alias.args == key.args { + if let &ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) = ty.ty.kind() { + if def_id == key.def_id.to_def_id() && args == key.args { // Nothing was actually constrained, this is an opaque usage that was // only discovered to be opaque after inference vars resolved. return Ok(()); diff --git a/compiler/rustc_hir_analysis/src/check/compare_eii.rs b/compiler/rustc_hir_analysis/src/check/compare_eii.rs index 29213058d1d5..956e68773b79 100644 --- a/compiler/rustc_hir_analysis/src/check/compare_eii.rs +++ b/compiler/rustc_hir_analysis/src/check/compare_eii.rs @@ -15,7 +15,7 @@ use rustc_infer::infer::{self, InferCtxt, TyCtxtInferExt}; use rustc_infer::traits::{ObligationCause, ObligationCauseCode}; use rustc_middle::ty::error::{ExpectedFound, TypeError}; -use rustc_middle::ty::{self, TyCtxt, TypeVisitableExt, TypingMode}; +use rustc_middle::ty::{self, ParamEnv, Ty, TyCtxt, TypeVisitableExt, TypingMode}; use rustc_span::{ErrorGuaranteed, Ident, Span, Symbol}; use rustc_trait_selection::error_reporting::InferCtxtErrorExt; use rustc_trait_selection::regions::InferCtxtRegionExt; @@ -26,7 +26,10 @@ use crate::check::compare_impl_item::{ CheckNumberOfEarlyBoundRegionsError, check_number_of_early_bound_regions, }; -use crate::errors::{EiiWithGenerics, LifetimesOrBoundsMismatchOnEii}; +use crate::errors::{ + EiiDefkindMismatch, EiiDefkindMismatchStaticMutability, EiiDefkindMismatchStaticSafety, + EiiWithGenerics, LifetimesOrBoundsMismatchOnEii, +}; /// Checks whether the signature of some `external_impl`, matches /// the signature of `declaration`, which it is supposed to be compatible @@ -38,14 +41,7 @@ pub(crate) fn compare_eii_function_types<'tcx>( eii_name: Symbol, eii_attr_span: Span, ) -> Result<(), ErrorGuaranteed> { - // Error recovery can resolve the EII target to another value item with the same name, - // such as a tuple-struct constructor. Skip the comparison in that case and rely on the - // earlier name-resolution error instead of ICEing while building EII diagnostics. - // See . - if !is_foreign_function(tcx, foreign_item) { - return Ok(()); - } - + check_eii_target(tcx, external_impl, foreign_item, eii_name, eii_attr_span)?; check_is_structurally_compatible(tcx, external_impl, foreign_item, eii_name, eii_attr_span)?; let external_impl_span = tcx.def_span(external_impl); @@ -152,6 +148,118 @@ pub(crate) fn compare_eii_function_types<'tcx>( Ok(()) } +pub(crate) fn compare_eii_statics<'tcx>( + tcx: TyCtxt<'tcx>, + external_impl: LocalDefId, + external_impl_ty: Ty<'tcx>, + foreign_item: DefId, + eii_name: Symbol, + eii_attr_span: Span, +) -> Result<(), ErrorGuaranteed> { + check_eii_target(tcx, external_impl, foreign_item, eii_name, eii_attr_span)?; + + let external_impl_span = tcx.def_span(external_impl); + let cause = ObligationCause::new( + external_impl_span, + external_impl, + ObligationCauseCode::CompareEii { external_impl, declaration: foreign_item }, + ); + + let param_env = ParamEnv::empty(); + + let infcx = &tcx.infer_ctxt().build(TypingMode::non_body_analysis()); + let ocx = ObligationCtxt::new_with_diagnostics(infcx); + + let declaration_ty = tcx.type_of(foreign_item).instantiate_identity(); + debug!(?declaration_ty); + + // FIXME: Copied over from compare impl items, same issue: + // We'd want to keep more accurate spans than "the method signature" when + // processing the comparison between the trait and impl fn, but we sadly lose them + // and point at the whole signature when a trait bound or specific input or output + // type would be more appropriate. In other places we have a `Vec` + // corresponding to their `Vec`, but we don't have that here. + // Fixing this would improve the output of test `issue-83765.rs`. + let result = ocx.sup(&cause, param_env, declaration_ty, external_impl_ty); + + if let Err(terr) = result { + debug!(?external_impl_ty, ?declaration_ty, ?terr, "sub_types failed"); + + let mut diag = struct_span_code_err!( + tcx.dcx(), + cause.span, + E0806, + "static `{}` has a type that is incompatible with the declaration of `#[{eii_name}]`", + tcx.item_name(external_impl) + ); + diag.span_note(eii_attr_span, "expected this because of this attribute"); + + return Err(diag.emit()); + } + + // Check that all obligations are satisfied by the implementation's + // version. + let errors = ocx.evaluate_obligations_error_on_ambiguity(); + if !errors.is_empty() { + let reported = infcx.err_ctxt().report_fulfillment_errors(errors); + return Err(reported); + } + + // Finally, resolve all regions. This catches wily misuses of + // lifetime parameters. + let errors = infcx.resolve_regions(external_impl, param_env, []); + if !errors.is_empty() { + return Err(infcx + .tainted_by_errors() + .unwrap_or_else(|| infcx.err_ctxt().report_region_errors(external_impl, &errors))); + } + + Ok(()) +} + +fn check_eii_target( + tcx: TyCtxt<'_>, + external_impl: LocalDefId, + foreign_item: DefId, + eii_name: Symbol, + eii_attr_span: Span, +) -> Result<(), ErrorGuaranteed> { + // Error recovery can resolve the EII target to another value item with the same name, + // such as a tuple-struct constructor. Skip the comparison in that case and rely on the + // earlier name-resolution error instead of ICEing while building EII diagnostics. + // See . + if !tcx.is_foreign_item(foreign_item) { + return Err(tcx.dcx().delayed_bug("EII is a foreign item")); + } + let expected_kind = tcx.def_kind(foreign_item); + let actual_kind = tcx.def_kind(external_impl); + + match expected_kind { + // Correct target + _ if expected_kind == actual_kind => Ok(()), + DefKind::Static { mutability: m1, safety: s1, .. } + if let DefKind::Static { mutability: m2, safety: s2, .. } = actual_kind => + { + Err(if s1 != s2 { + tcx.dcx().emit_err(EiiDefkindMismatchStaticSafety { span: eii_attr_span, eii_name }) + } else if m1 != m2 { + tcx.dcx() + .emit_err(EiiDefkindMismatchStaticMutability { span: eii_attr_span, eii_name }) + } else { + unreachable!() + }) + } + // Not checked by attr target checking + DefKind::Fn | DefKind::Static { .. } => Err(tcx.dcx().emit_err(EiiDefkindMismatch { + span: eii_attr_span, + eii_name, + expected_kind: expected_kind.descr(foreign_item), + })), + // Checked by attr target checking + _ => Err(tcx.dcx().delayed_bug("Attribute should not be allowed by target checking")), + } +} + /// Checks a bunch of different properties of the impl/trait methods for /// compatibility, such as asyncness, number of argument, self receiver kind, /// and number of early- and late-bound generics. @@ -451,7 +559,3 @@ fn get_declaration_sig<'tcx>(tcx: TyCtxt<'tcx>, def_id: LocalDefId) -> Option<&' let hir_id: HirId = tcx.local_def_id_to_hir_id(def_id); tcx.hir_fn_sig_by_hir_id(hir_id) } - -fn is_foreign_function(tcx: TyCtxt<'_>, def_id: DefId) -> bool { - tcx.is_foreign_item(def_id) && matches!(tcx.def_kind(def_id), DefKind::Fn) -} diff --git a/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs b/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs index c4ec27e07124..20ee6e34e598 100644 --- a/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs +++ b/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs @@ -820,24 +820,25 @@ fn cx(&self) -> TyCtxt<'tcx> { } fn fold_ty(&mut self, ty: Ty<'tcx>) -> Ty<'tcx> { - if let &ty::Alias(proj @ ty::AliasTy { kind: ty::Projection { def_id }, .. }) = ty.kind() + if let &ty::Alias(ty::AliasTy { kind: ty::Projection { def_id }, args: proj_args, .. }) = + ty.kind() && self.cx().is_impl_trait_in_trait(def_id) { if let Some((ty, _)) = self.types.get(&def_id) { return *ty; } //FIXME(RPITIT): Deny nested RPITIT in args too - if proj.args.has_escaping_bound_vars() { + if proj_args.has_escaping_bound_vars() { bug!("FIXME(RPITIT): error here"); } // Replace with infer var let infer_ty = self.ocx.infcx.next_ty_var(self.span); - self.types.insert(def_id, (infer_ty, proj.args)); + self.types.insert(def_id, (infer_ty, proj_args)); // Recurse into bounds for (pred, pred_span) in self .cx() .explicit_item_bounds(def_id) - .iter_instantiated_copied(self.cx(), proj.args) + .iter_instantiated_copied(self.cx(), proj_args) { let pred = pred.fold_with(self); let pred = self.ocx.normalize( @@ -2707,8 +2708,8 @@ fn param_env_with_gat_bounds<'tcx>( let bound_vars = tcx.mk_bound_variable_kinds(&bound_vars); match normalize_impl_ty.kind() { - &ty::Alias(proj @ ty::AliasTy { kind: ty::Projection { def_id }, .. }) - if def_id == trait_ty.def_id && proj.args == rebased_args => + &ty::Alias(ty::AliasTy { kind: ty::Projection { def_id }, args, .. }) + if def_id == trait_ty.def_id && args == rebased_args => { // Don't include this predicate if the projected type is // exactly the same as the projection. This can occur in diff --git a/compiler/rustc_hir_analysis/src/check/compare_impl_item/refine.rs b/compiler/rustc_hir_analysis/src/check/compare_impl_item/refine.rs index f0f15f5e98e8..01e8a8c4b193 100644 --- a/compiler/rustc_hir_analysis/src/check/compare_impl_item/refine.rs +++ b/compiler/rustc_hir_analysis/src/check/compare_impl_item/refine.rs @@ -308,9 +308,9 @@ fn report_mismatched_rpitit_signature<'tcx>( let mut return_ty = trait_m_sig.output().fold_with(&mut super::RemapLateParam { tcx, mapping }); if tcx.asyncness(impl_m_def_id).is_async() && tcx.asyncness(trait_m_def_id).is_async() { - let &ty::Alias( - future_ty @ ty::AliasTy { kind: ty::Projection { def_id: future_ty_def_id }, .. }, - ) = return_ty.kind() + let &ty::Alias(ty::AliasTy { + kind: ty::Projection { def_id: future_ty_def_id }, args, .. + }) = return_ty.kind() else { span_bug!( tcx.def_span(trait_m_def_id), @@ -319,7 +319,7 @@ fn report_mismatched_rpitit_signature<'tcx>( }; let Some(future_output_ty) = tcx .explicit_item_bounds(future_ty_def_id) - .iter_instantiated_copied(tcx, future_ty.args) + .iter_instantiated_copied(tcx, args) .find_map(|(clause, _)| match clause.kind().no_bound_vars()? { ty::ClauseKind::Projection(proj) => proj.term.as_type(), _ => None, diff --git a/compiler/rustc_hir_analysis/src/check/entry.rs b/compiler/rustc_hir_analysis/src/check/entry.rs index a6dae521db88..16e95c96ab91 100644 --- a/compiler/rustc_hir_analysis/src/check/entry.rs +++ b/compiler/rustc_hir_analysis/src/check/entry.rs @@ -1,28 +1,28 @@ use std::ops::Not; -use rustc_abi::ExternAbi; use rustc_hir as hir; use rustc_hir::{Node, find_attr}; use rustc_infer::infer::TyCtxtInferExt; use rustc_middle::span_bug; use rustc_middle::ty::{self, TyCtxt, TypingMode}; use rustc_session::config::EntryFnType; -use rustc_span::Span; use rustc_span::def_id::{CRATE_DEF_ID, DefId, LocalDefId}; +use rustc_span::{ErrorGuaranteed, Span}; use rustc_trait_selection::error_reporting::InferCtxtErrorExt; +use rustc_trait_selection::regions::InferCtxtRegionExt; use rustc_trait_selection::traits::{self, ObligationCause, ObligationCauseCode}; use super::check_function_signature; use crate::errors; -pub(crate) fn check_for_entry_fn(tcx: TyCtxt<'_>) { +pub(crate) fn check_for_entry_fn(tcx: TyCtxt<'_>) -> Result<(), ErrorGuaranteed> { match tcx.entry_fn(()) { Some((def_id, EntryFnType::Main { .. })) => check_main_fn_ty(tcx, def_id), - _ => {} + _ => Ok(()), } } -fn check_main_fn_ty(tcx: TyCtxt<'_>, main_def_id: DefId) { +fn check_main_fn_ty(tcx: TyCtxt<'_>, main_def_id: DefId) -> Result<(), ErrorGuaranteed> { let main_fnsig = tcx.fn_sig(main_def_id).instantiate_identity(); let main_span = tcx.def_span(main_def_id); @@ -87,20 +87,20 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { } } - let mut error = false; let main_diagnostics_def_id = main_fn_diagnostics_def_id(tcx, main_def_id, main_span); let main_asyncness = tcx.asyncness(main_def_id); if main_asyncness.is_async() { let asyncness_span = main_fn_asyncness_span(tcx, main_def_id); - tcx.dcx() - .emit_err(errors::MainFunctionAsync { span: main_span, asyncness: asyncness_span }); - error = true; + return Err(tcx + .dcx() + .emit_err(errors::MainFunctionAsync { span: main_span, asyncness: asyncness_span })); } if let Some(attr_span) = find_attr!(tcx, main_def_id, TrackCaller(span) => *span) { - tcx.dcx().emit_err(errors::TrackCallerOnMain { span: attr_span, annotated: main_span }); - error = true; + return Err(tcx + .dcx() + .emit_err(errors::TrackCallerOnMain { span: attr_span, annotated: main_span })); } if !tcx.codegen_fn_attrs(main_def_id).target_features.is_empty() @@ -108,12 +108,7 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { && !tcx.sess.target.is_like_wasm && !tcx.sess.opts.actually_rustdoc { - tcx.dcx().emit_err(errors::TargetFeatureOnMain { main: main_span }); - error = true; - } - - if error { - return; + return Err(tcx.dcx().emit_err(errors::TargetFeatureOnMain { main: main_span })); } // Main should have no WC, so empty param env is OK here. @@ -123,8 +118,9 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { let return_ty = main_fnsig.output(); let return_ty_span = main_fn_return_type_span(tcx, main_def_id).unwrap_or(main_span); let Some(return_ty) = return_ty.no_bound_vars() else { - tcx.dcx().emit_err(errors::MainFunctionReturnTypeGeneric { span: return_ty_span }); - return; + return Err(tcx + .dcx() + .emit_err(errors::MainFunctionReturnTypeGeneric { span: return_ty_span })); }; let infcx = tcx.infer_ctxt().build(TypingMode::non_body_analysis()); let cause = traits::ObligationCause::new( @@ -137,8 +133,16 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { ocx.register_bound(cause, param_env, norm_return_ty, term_did); let errors = ocx.evaluate_obligations_error_on_ambiguity(); if !errors.is_empty() { - infcx.err_ctxt().report_fulfillment_errors(errors); - error = true; + return Err(infcx.err_ctxt().report_fulfillment_errors(errors)); + } + + let region_errors = + infcx.resolve_regions(main_diagnostics_def_id, param_env, ty::List::empty()); + + if !region_errors.is_empty() { + return Err(infcx + .err_ctxt() + .report_region_errors(main_diagnostics_def_id, ®ion_errors)); } // now we can take the return type of the given main function expected_return_type = norm_return_ty; @@ -147,19 +151,9 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { expected_return_type = tcx.types.unit; } - if error { - return; - } + let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig_safe_rust_abi([], expected_return_type)); - let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig( - [], - expected_return_type, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )); - - if check_function_signature( + check_function_signature( tcx, ObligationCause::new( main_span, @@ -168,26 +162,24 @@ fn main_fn_return_type_span(tcx: TyCtxt<'_>, def_id: DefId) -> Option { ), main_def_id, expected_sig, - ) - .is_err() - { - return; - } + )?; let main_fn_generics = tcx.generics_of(main_def_id); let main_fn_predicates = tcx.predicates_of(main_def_id); if main_fn_generics.count() != 0 || !main_fnsig.bound_vars().is_empty() { let generics_param_span = main_fn_generics_params_span(tcx, main_def_id); - tcx.dcx().emit_err(errors::MainFunctionGenericParameters { + return Err(tcx.dcx().emit_err(errors::MainFunctionGenericParameters { span: generics_param_span.unwrap_or(main_span), label_span: generics_param_span, - }); + })); } else if !main_fn_predicates.predicates.is_empty() { // generics may bring in implicit predicates, so we skip this check if generics is present. let generics_where_clauses_span = main_fn_where_clauses_span(tcx, main_def_id); - tcx.dcx().emit_err(errors::WhereClauseOnMain { + return Err(tcx.dcx().emit_err(errors::WhereClauseOnMain { span: generics_where_clauses_span.unwrap_or(main_span), generics_span: generics_where_clauses_span, - }); + })); } + + Ok(()) } diff --git a/compiler/rustc_hir_analysis/src/check/intrinsic.rs b/compiler/rustc_hir_analysis/src/check/intrinsic.rs index 58454cfc489c..d952faa5edb7 100644 --- a/compiler/rustc_hir_analysis/src/check/intrinsic.rs +++ b/compiler/rustc_hir_analysis/src/check/intrinsic.rs @@ -1,6 +1,5 @@ //! Type-checking for the `#[rustc_intrinsic]` intrinsics that the compiler exposes. -use rustc_abi::ExternAbi; use rustc_errors::DiagMessage; use rustc_hir::{self as hir, LangItem}; use rustc_middle::traits::{ObligationCause, ObligationCauseCode}; @@ -636,20 +635,10 @@ pub(crate) fn check_intrinsic_type( sym::catch_unwind => { let mut_u8 = Ty::new_mut_ptr(tcx, tcx.types.u8); - let try_fn_ty = ty::Binder::dummy(tcx.mk_fn_sig( - [mut_u8], - tcx.types.unit, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )); - let catch_fn_ty = ty::Binder::dummy(tcx.mk_fn_sig( - [mut_u8, mut_u8], - tcx.types.unit, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )); + let try_fn_ty = + ty::Binder::dummy(tcx.mk_fn_sig_safe_rust_abi([mut_u8], tcx.types.unit)); + let catch_fn_ty = + ty::Binder::dummy(tcx.mk_fn_sig_safe_rust_abi([mut_u8, mut_u8], tcx.types.unit)); ( 0, 0, @@ -817,7 +806,7 @@ pub(crate) fn check_intrinsic_type( return; } }; - let sig = tcx.mk_fn_sig(inputs, output, false, safety, ExternAbi::Rust); + let sig = tcx.mk_fn_sig_rust_abi(inputs, output, safety); let sig = ty::Binder::bind_with_vars(sig, bound_vars); equate_intrinsic_type(tcx, span, intrinsic_id, n_tps, n_lts, n_cts, sig) } diff --git a/compiler/rustc_hir_analysis/src/check/mod.rs b/compiler/rustc_hir_analysis/src/check/mod.rs index 950696db44ef..cf182fb116cb 100644 --- a/compiler/rustc_hir_analysis/src/check/mod.rs +++ b/compiler/rustc_hir_analysis/src/check/mod.rs @@ -478,7 +478,7 @@ fn fn_sig_suggestion<'tcx>( } }) }) - .chain(std::iter::once(if sig.c_variadic { Some("...".to_string()) } else { None })) + .chain(std::iter::once(if sig.c_variadic() { Some("...".to_string()) } else { None })) .flatten() .collect::>() .join(", "); @@ -506,7 +506,7 @@ fn fn_sig_suggestion<'tcx>( let output = if !output.is_unit() { format!(" -> {output}") } else { String::new() }; - let safety = sig.safety.prefix_str(); + let safety = sig.safety().prefix_str(); let (generics, where_clauses) = bounds_from_generic_predicates(tcx, predicates, assoc); // FIXME: this is not entirely correct, as the lifetimes from borrowed params will diff --git a/compiler/rustc_hir_analysis/src/check/wfcheck.rs b/compiler/rustc_hir_analysis/src/check/wfcheck.rs index 6120c336ea3d..4ab69f7a7b09 100644 --- a/compiler/rustc_hir_analysis/src/check/wfcheck.rs +++ b/compiler/rustc_hir_analysis/src/check/wfcheck.rs @@ -41,7 +41,7 @@ }; use tracing::{debug, instrument}; -use super::compare_eii::compare_eii_function_types; +use super::compare_eii::{compare_eii_function_types, compare_eii_statics}; use crate::autoderef::Autoderef; use crate::constrained_generic_params::{Parameter, identify_constrained_generic_params}; use crate::errors; @@ -773,10 +773,10 @@ fn visit>>( impl<'tcx> TypeVisitor> for GATArgsCollector<'tcx> { fn visit_ty(&mut self, t: Ty<'tcx>) { match t.kind() { - &ty::Alias(p @ ty::AliasTy { kind: ty::Projection { def_id }, .. }) + &ty::Alias(ty::AliasTy { kind: ty::Projection { def_id }, args, .. }) if def_id == self.gat => { - for (idx, arg) in p.args.iter().enumerate() { + for (idx, arg) in args.iter().enumerate() { match arg.kind() { GenericArgKind::Lifetime(lt) if !lt.is_bound() => { self.regions.insert((lt, idx)); @@ -904,7 +904,7 @@ fn check_param_wf(tcx: TyCtxt<'_>, param: &ty::GenericParamDef) -> Result<(), Er ) => None, Err(ConstParamTyImplementationError::UnsizedConstParamsFeatureRequired) => { Some(vec![ - (adt_const_params_feature_string, sym::adt_const_params), + (adt_const_params_feature_string, sym::min_adt_const_params), ( " references to implement the `ConstParamTy` trait".into(), sym::unsized_const_params, @@ -931,11 +931,13 @@ fn ty_is_local(ty: Ty<'_>) -> bool { ty_is_local(ty).then_some(vec![( adt_const_params_feature_string, - sym::adt_const_params, + sym::min_adt_const_params, )]) } // Implements `ConstParamTy`, suggest adding the feature to enable. - Ok(..) => Some(vec![(adt_const_params_feature_string, sym::adt_const_params)]), + Ok(..) => { + Some(vec![(adt_const_params_feature_string, sym::min_adt_const_params)]) + } }; if let Some(features) = may_suggest_feature { tcx.disabled_nightly_features(&mut diag, features); @@ -1208,7 +1210,7 @@ fn check_item_fn( decl: &hir::FnDecl<'_>, ) -> Result<(), ErrorGuaranteed> { enter_wf_checking_ctxt(tcx, def_id, |wfcx| { - check_eiis(tcx, def_id); + check_eiis_fn(tcx, def_id); let sig = tcx.fn_sig(def_id).instantiate_identity(); check_fn_or_method(wfcx, sig, decl, def_id); @@ -1216,7 +1218,7 @@ fn check_item_fn( }) } -fn check_eiis(tcx: TyCtxt<'_>, def_id: LocalDefId) { +fn check_eiis_fn(tcx: TyCtxt<'_>, def_id: LocalDefId) { // does the function have an EiiImpl attribute? that contains the defid of a *macro* // that was used to mark the implementation. This is a two step process. for EiiImpl { resolution, span, .. } in @@ -1243,6 +1245,33 @@ fn check_eiis(tcx: TyCtxt<'_>, def_id: LocalDefId) { } } +fn check_eiis_static<'tcx>(tcx: TyCtxt<'tcx>, def_id: LocalDefId, ty: Ty<'tcx>) { + // does the function have an EiiImpl attribute? that contains the defid of a *macro* + // that was used to mark the implementation. This is a two step process. + for EiiImpl { resolution, span, .. } in + find_attr!(tcx, def_id, EiiImpls(impls) => impls).into_iter().flatten() + { + let (foreign_item, name) = match resolution { + EiiImplResolution::Macro(def_id) => { + // we expect this macro to have the `EiiMacroFor` attribute, that points to a function + // signature that we'd like to compare the function we're currently checking with + if let Some(foreign_item) = + find_attr!(tcx, *def_id, EiiDeclaration(EiiDecl {foreign_item: t, ..}) => *t) + { + (foreign_item, tcx.item_name(*def_id)) + } else { + tcx.dcx().span_delayed_bug(*span, "resolved to something that's not an EII"); + continue; + } + } + EiiImplResolution::Known(decl) => (decl.foreign_item, decl.name.name), + EiiImplResolution::Error(_eg) => continue, + }; + + let _ = compare_eii_statics(tcx, def_id, ty, foreign_item, name, *span); + } +} + #[instrument(level = "debug", skip(tcx))] pub(crate) fn check_static_item<'tcx>( tcx: TyCtxt<'tcx>, @@ -1251,6 +1280,10 @@ pub(crate) fn check_static_item<'tcx>( should_check_for_sync: bool, ) -> Result<(), ErrorGuaranteed> { enter_wf_checking_ctxt(tcx, item_id, |wfcx| { + if should_check_for_sync { + check_eiis_static(tcx, item_id, ty); + } + let span = tcx.ty_span(item_id); let loc = Some(WellFormedLoc::Ty(item_id)); let item_ty = wfcx.deeply_normalize(span, loc, ty); @@ -1668,9 +1701,9 @@ fn check_fn_or_method<'tcx>( check_where_clauses(wfcx, def_id); - if sig.abi == ExternAbi::RustCall { + if sig.abi() == ExternAbi::RustCall { let span = tcx.def_span(def_id); - let has_implicit_self = hir_decl.implicit_self != hir::ImplicitSelfKind::None; + let has_implicit_self = hir_decl.implicit_self() != hir::ImplicitSelfKind::None; let mut inputs = sig.inputs().iter().skip(if has_implicit_self { 1 } else { 0 }); // Check that the argument is a tuple and is sized if let Some(ty) = inputs.next() { @@ -2372,7 +2405,8 @@ pub(super) fn check_type_wf(tcx: TyCtxt<'_>, (): ()) -> Result<(), ErrorGuarante })) .and(items.par_nested_bodies(|item| tcx.ensure_result().check_well_formed(item))) .and(items.par_opaques(|item| tcx.ensure_result().check_well_formed(item))); - super::entry::check_for_entry_fn(tcx); + + super::entry::check_for_entry_fn(tcx)?; res } diff --git a/compiler/rustc_hir_analysis/src/coherence/mod.rs b/compiler/rustc_hir_analysis/src/coherence/mod.rs index 8f83761518bd..261be884025f 100644 --- a/compiler/rustc_hir_analysis/src/coherence/mod.rs +++ b/compiler/rustc_hir_analysis/src/coherence/mod.rs @@ -100,6 +100,14 @@ fn enforce_trait_manually_implementable( return Err(tcx.dcx().emit_err(errors::SpecializationTrait { span: impl_header_span })); } } + + if !trait_def.impl_restriction.is_allowed_in(impl_def_id.to_def_id(), tcx) { + return Err(tcx.dcx().emit_err(errors::ImplOfRestrictedTrait { + impl_span: impl_header_span, + restriction_span: trait_def.impl_restriction.expect_span(), + restriction_path: trait_def.impl_restriction.restriction_path(tcx), + })); + } Ok(()) } diff --git a/compiler/rustc_hir_analysis/src/collect.rs b/compiler/rustc_hir_analysis/src/collect.rs index cfda0300f3f0..00f26a5f0667 100644 --- a/compiler/rustc_hir_analysis/src/collect.rs +++ b/compiler/rustc_hir_analysis/src/collect.rs @@ -893,11 +893,25 @@ fn adt_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::AdtDef<'_> { fn trait_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::TraitDef { let item = tcx.hir_expect_item(def_id); - let (constness, is_alias, is_auto, safety) = match item.kind { - hir::ItemKind::Trait(constness, is_auto, safety, ..) => { - (constness, false, is_auto == hir::IsAuto::Yes, safety) - } - hir::ItemKind::TraitAlias(constness, ..) => (constness, true, false, hir::Safety::Safe), + let (constness, is_alias, is_auto, safety, impl_restriction) = match item.kind { + hir::ItemKind::Trait(constness, is_auto, safety, impl_restriction, ..) => ( + constness, + false, + is_auto == hir::IsAuto::Yes, + safety, + if let hir::RestrictionKind::Restricted(path) = impl_restriction.kind { + ty::trait_def::ImplRestrictionKind::Restricted(path.res, impl_restriction.span) + } else { + ty::trait_def::ImplRestrictionKind::Unrestricted + }, + ), + hir::ItemKind::TraitAlias(constness, ..) => ( + constness, + true, + false, + hir::Safety::Safe, + ty::trait_def::ImplRestrictionKind::Unrestricted, + ), _ => span_bug!(item.span, "trait_def_of_item invoked on non-trait"), }; @@ -946,6 +960,7 @@ fn trait_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::TraitDef { def_id: def_id.to_def_id(), safety, constness, + impl_restriction, paren_sugar, has_auto_impl: is_auto, is_marker, @@ -1025,7 +1040,7 @@ fn fn_sig(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::EarlyBinder<'_, ty::PolyFn (Bound::Unbounded, Bound::Unbounded) => hir::Safety::Safe, _ => hir::Safety::Unsafe, }; - ty::Binder::dummy(tcx.mk_fn_sig(inputs, ty, false, safety, ExternAbi::Rust)) + ty::Binder::dummy(tcx.mk_fn_sig_rust_abi(inputs, ty, safety)) } Expr(&hir::Expr { kind: hir::ExprKind::Closure { .. }, .. }) => { @@ -1218,9 +1233,7 @@ fn recover_infer_ret_ty<'tcx>( let fn_sig = tcx.mk_fn_sig( fn_sig.inputs().iter().copied(), recovered_ret_ty.unwrap_or_else(|| Ty::new_error(tcx, guar)), - fn_sig.c_variadic, - fn_sig.safety, - fn_sig.abi, + fn_sig.fn_sig_kind, ); late_param_regions_to_bound(tcx, scope, bound_vars, fn_sig) diff --git a/compiler/rustc_hir_analysis/src/collect/dump.rs b/compiler/rustc_hir_analysis/src/collect/dump.rs index 3e9c83b12df0..f1bb90fcbe89 100644 --- a/compiler/rustc_hir_analysis/src/collect/dump.rs +++ b/compiler/rustc_hir_analysis/src/collect/dump.rs @@ -7,7 +7,7 @@ use rustc_span::sym; pub(crate) fn opaque_hidden_types(tcx: TyCtxt<'_>) { - if !find_attr!(tcx, crate, RustcHiddenTypeOfOpaques) { + if !find_attr!(tcx, crate, RustcDumpHiddenTypeOfOpaques) { return; } for id in tcx.hir_crate_items(()).opaques() { diff --git a/compiler/rustc_hir_analysis/src/collect/item_bounds.rs b/compiler/rustc_hir_analysis/src/collect/item_bounds.rs index eb005881245c..98ac52e95929 100644 --- a/compiler/rustc_hir_analysis/src/collect/item_bounds.rs +++ b/compiler/rustc_hir_analysis/src/collect/item_bounds.rs @@ -549,17 +549,16 @@ fn cx(&self) -> TyCtxt<'tcx> { } fn fold_ty(&mut self, ty: Ty<'tcx>) -> Ty<'tcx> { - if let &ty::Alias( - projection_ty @ ty::AliasTy { - kind: ty::Projection { def_id: projection_ty_def_id }, - .. - }, - ) = ty.kind() + if let &ty::Alias(ty::AliasTy { + kind: ty::Projection { def_id: projection_ty_def_id }, + args, + .. + }) = ty.kind() && let Some(ty::ImplTraitInTraitData::Trait { fn_def_id, .. }) = self.tcx.opt_rpitit_info(projection_ty_def_id) && fn_def_id == self.fn_def_id { - self.tcx.type_of(projection_ty_def_id).instantiate(self.tcx, projection_ty.args) + self.tcx.type_of(projection_ty_def_id).instantiate(self.tcx, args) } else { ty.super_fold_with(self) } diff --git a/compiler/rustc_hir_analysis/src/collect/predicates_of.rs b/compiler/rustc_hir_analysis/src/collect/predicates_of.rs index 30b1bf411687..d70ee74a9b2a 100644 --- a/compiler/rustc_hir_analysis/src/collect/predicates_of.rs +++ b/compiler/rustc_hir_analysis/src/collect/predicates_of.rs @@ -165,7 +165,7 @@ fn gather_explicit_predicates_of(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::Gen Some(ty::Binder::dummy(tcx.impl_trait_ref(def_id).instantiate_identity())); } } - ItemKind::Trait(_, _, _, _, _, self_bounds, ..) + ItemKind::Trait(_, _, _, _, _, _, self_bounds, ..) | ItemKind::TraitAlias(_, _, _, self_bounds) => { is_trait = Some((self_bounds, item.span)); } @@ -513,13 +513,13 @@ pub(super) fn explicit_predicates_of<'tcx>( // identity args of the trait. // * It must be an associated type for this trait (*not* a // supertrait). - if let &ty::Alias( - projection @ ty::AliasTy { - kind: ty::Projection { def_id: projection_def_id }, .. - }, - ) = ty.kind() + if let &ty::Alias(ty::AliasTy { + kind: ty::Projection { def_id: projection_def_id }, + args, + .. + }) = ty.kind() { - projection.args == trait_identity_args + args == trait_identity_args // FIXME(return_type_notation): This check should be more robust && !tcx.is_impl_trait_in_trait(projection_def_id) && tcx.parent(projection_def_id) == def_id.to_def_id() @@ -979,6 +979,32 @@ fn probe_ty_param_bounds_in_generics( ) -> Vec<(ty::Clause<'tcx>, Span)> { let mut bounds = Vec::new(); + if let PredicateFilter::All = filter { + for param in hir_generics.params { + match param.kind { + hir::GenericParamKind::Type { .. } => { + let param_ty = self.lowerer().lower_ty_param(param.hir_id); + self.lowerer().add_implicit_sizedness_bounds( + &mut bounds, + param_ty, + &[], + ImpliedBoundsContext::TyParam(param.def_id, hir_generics.predicates), + param.span, + ); + self.lowerer().add_default_traits( + &mut bounds, + param_ty, + &[], + ImpliedBoundsContext::TyParam(param.def_id, hir_generics.predicates), + param.span, + ); + } + hir::GenericParamKind::Lifetime { .. } + | hir::GenericParamKind::Const { .. } => {} + } + } + } + for predicate in hir_generics.predicates { let hir_id = predicate.hir_id; let hir::WherePredicateKind::BoundPredicate(predicate) = predicate.kind else { @@ -1038,7 +1064,7 @@ pub(super) fn const_conditions<'tcx>( Node::Item(item) => match item.kind { hir::ItemKind::Impl(impl_) => (impl_.generics, None, false), hir::ItemKind::Fn { generics, .. } => (generics, None, false), - hir::ItemKind::Trait(_, _, _, _, generics, supertraits, _) => { + hir::ItemKind::Trait(_, _, _, _, _, generics, supertraits, _) => { (generics, Some((Some(item.owner_id.def_id), supertraits)), false) } hir::ItemKind::TraitAlias(_, _, generics, supertraits) => { diff --git a/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs b/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs index 4312d5fa9ddd..ba1377acc422 100644 --- a/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs +++ b/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs @@ -645,7 +645,7 @@ fn visit_item(&mut self, item: &'tcx hir::Item<'tcx>) { | hir::ItemKind::Enum(_, generics, _) | hir::ItemKind::Struct(_, generics, _) | hir::ItemKind::Union(_, generics, _) - | hir::ItemKind::Trait(_, _, _, _, generics, ..) + | hir::ItemKind::Trait(_, _, _, _, _, generics, ..) | hir::ItemKind::TraitAlias(_, _, generics, ..) | hir::ItemKind::Impl(hir::Impl { generics, .. }) => { // These kinds of items have only early-bound lifetime parameters. @@ -1523,7 +1523,7 @@ fn remap_opaque_captures( None, DefKind::LifetimeParam, Some(DefPathData::OpaqueLifetime(ident.name)), - &mut self.disambiguator, + self.disambiguator, ); feed.def_span(ident.span); feed.def_ident_span(Some(ident.span)); diff --git a/compiler/rustc_hir_analysis/src/delegation.rs b/compiler/rustc_hir_analysis/src/delegation.rs index 730288574e76..3eb6767dd77d 100644 --- a/compiler/rustc_hir_analysis/src/delegation.rs +++ b/compiler/rustc_hir_analysis/src/delegation.rs @@ -14,7 +14,7 @@ use rustc_span::{ErrorGuaranteed, Span, kw}; use crate::collect::ItemCtxt; -use crate::hir_ty_lowering::{GenericArgPosition, HirTyLowerer}; +use crate::hir_ty_lowering::HirTyLowerer; type RemapTable = FxHashMap; @@ -318,11 +318,15 @@ fn create_generic_args<'tcx>( let (caller_kind, callee_kind) = (fn_kind(tcx, delegation_id), fn_kind(tcx, sig_id)); let delegation_args = ty::GenericArgs::identity_for_item(tcx, delegation_id); - let delegation_parent_args_count = tcx.generics_of(delegation_id).parent_count; let deleg_parent_args_without_self_count = get_delegation_parent_args_count_without_self(tcx, delegation_id, sig_id); + let delegation_generics = tcx.generics_of(delegation_id); + let real_args_count = delegation_args.len() - delegation_generics.own_synthetic_params_count(); + let synth_args = &delegation_args[real_args_count..]; + let delegation_args = &delegation_args[..real_args_count]; + let args = match (caller_kind, callee_kind) { (FnKind::Free, FnKind::Free) | (FnKind::Free, FnKind::AssocTrait) @@ -339,14 +343,15 @@ fn create_generic_args<'tcx>( assert!(child_args.is_empty(), "Child args can not be used in trait impl case"); - tcx.mk_args(&delegation_args[delegation_parent_args_count..]) + tcx.mk_args(&delegation_args[delegation_generics.parent_count..]) } (FnKind::AssocInherentImpl, FnKind::AssocTrait) => { let self_ty = tcx.type_of(tcx.local_parent(delegation_id)).instantiate_identity(); tcx.mk_args_from_iter( - std::iter::once(ty::GenericArg::from(self_ty)).chain(delegation_args.iter()), + std::iter::once(ty::GenericArg::from(self_ty)) + .chain(delegation_args.iter().copied()), ) } @@ -411,7 +416,7 @@ fn create_generic_args<'tcx>( new_args.extend_from_slice(&child_args[child_lifetimes_count..]); } else if !parent_args.is_empty() { - let child_args = &delegation_args[delegation_parent_args_count..]; + let child_args = &delegation_args[delegation_generics.parent_count..]; let child_lifetimes_count = child_args.iter().take_while(|a| a.as_region().is_some()).count(); @@ -424,6 +429,8 @@ fn create_generic_args<'tcx>( new_args.extend(&child_args[child_lifetimes_count + skip_self as usize..]); } + new_args.extend(synth_args); + new_args } @@ -523,7 +530,7 @@ fn check_constraints<'tcx>( })); }; - if tcx.fn_sig(sig_id).skip_binder().skip_binder().c_variadic { + if tcx.fn_sig(sig_id).skip_binder().skip_binder().c_variadic() { // See issue #127443 for explanation. emit("delegation to C-variadic functions is not allowed"); } @@ -581,14 +588,7 @@ fn get_delegation_user_specified_args<'tcx>( let self_ty = get_delegation_self_ty(tcx, delegation_id); lowerer - .lower_generic_args_of_path( - segment.ident.span, - def_id, - &[], - segment, - self_ty, - GenericArgPosition::Type, - ) + .lower_generic_args_of_path(segment.ident.span, def_id, &[], segment, self_ty) .0 .as_slice() }); @@ -610,17 +610,11 @@ fn get_delegation_user_specified_args<'tcx>( }; let args = lowerer - .lower_generic_args_of_path( - segment.ident.span, - def_id, - parent_args, - segment, - None, - GenericArgPosition::Value, - ) + .lower_generic_args_of_path(segment.ident.span, def_id, parent_args, segment, None) .0; - &args[parent_args.len()..] + let synth_params_count = tcx.generics_of(def_id).own_synthetic_params_count(); + &args[parent_args.len()..args.len() - synth_params_count] }); (parent_args.unwrap_or_default(), child_args.unwrap_or_default()) diff --git a/compiler/rustc_hir_analysis/src/errors.rs b/compiler/rustc_hir_analysis/src/errors.rs index c55b9e384c55..f353ace0b388 100644 --- a/compiler/rustc_hir_analysis/src/errors.rs +++ b/compiler/rustc_hir_analysis/src/errors.rs @@ -1035,6 +1035,16 @@ pub(crate) struct SpecializationTrait { pub span: Span, } +#[derive(Diagnostic)] +#[diag("trait cannot be implemented outside `{$restriction_path}`")] +pub(crate) struct ImplOfRestrictedTrait { + #[primary_span] + pub impl_span: Span, + #[note("trait restricted here")] + pub restriction_span: Span, + pub restriction_path: String, +} + #[derive(Diagnostic)] #[diag("implicit types in closure signatures are forbidden when `for<...>` is present")] pub(crate) struct ClosureImplicitHrtb { @@ -1923,3 +1933,28 @@ pub(crate) struct ImplUnpinForPinProjectedType { pub adt_span: Span, pub adt_name: Symbol, } + +#[derive(Diagnostic)] +#[diag("`#[{$eii_name}]` must be used on a {$expected_kind}")] +pub(crate) struct EiiDefkindMismatch { + #[primary_span] + pub span: Span, + pub eii_name: Symbol, + pub expected_kind: &'static str, +} + +#[derive(Diagnostic)] +#[diag("mutability does not match with the definition of`#[{$eii_name}]`")] +pub(crate) struct EiiDefkindMismatchStaticMutability { + #[primary_span] + pub span: Span, + pub eii_name: Symbol, +} + +#[derive(Diagnostic)] +#[diag("safety does not match with the definition of`#[{$eii_name}]`")] +pub(crate) struct EiiDefkindMismatchStaticSafety { + #[primary_span] + pub span: Span, + pub eii_name: Symbol, +} diff --git a/compiler/rustc_hir_analysis/src/errors/wrong_number_of_generic_args.rs b/compiler/rustc_hir_analysis/src/errors/wrong_number_of_generic_args.rs index 615c0a766a63..5cd4ea2f9edd 100644 --- a/compiler/rustc_hir_analysis/src/errors/wrong_number_of_generic_args.rs +++ b/compiler/rustc_hir_analysis/src/errors/wrong_number_of_generic_args.rs @@ -360,7 +360,7 @@ fn get_lifetime_args_suggestions_from_param_names( let in_ret = matches!(fn_decl.output, hir::FnRetTy::Return(ty) if ty.hir_id == ty_id); - if in_arg || (in_ret && fn_decl.lifetime_elision_allowed) { + if in_arg || (in_ret && fn_decl.lifetime_elision_allowed()) { return std::iter::repeat_n("'_".to_owned(), num_params_to_take) .collect::>() .join(", "); diff --git a/compiler/rustc_hir_analysis/src/hir_ty_lowering/cmse.rs b/compiler/rustc_hir_analysis/src/hir_ty_lowering/cmse.rs index a1b169c6a166..f4dca6371696 100644 --- a/compiler/rustc_hir_analysis/src/hir_ty_lowering/cmse.rs +++ b/compiler/rustc_hir_analysis/src/hir_ty_lowering/cmse.rs @@ -48,7 +48,7 @@ pub(crate) fn validate_cmse_abi<'tcx>( // An `extern "cmse-nonsecure-entry"` function cannot be c-variadic. We run // into https://github.com/rust-lang/rust/issues/132142 if we don't explicitly bail. - if decl.c_variadic { + if decl.c_variadic() { return; } diff --git a/compiler/rustc_hir_analysis/src/hir_ty_lowering/generics.rs b/compiler/rustc_hir_analysis/src/hir_ty_lowering/generics.rs index 0ca57cb50cf2..596f538a9d3b 100644 --- a/compiler/rustc_hir_analysis/src/hir_ty_lowering/generics.rs +++ b/compiler/rustc_hir_analysis/src/hir_ty_lowering/generics.rs @@ -385,17 +385,14 @@ pub fn lower_generic_args<'tcx: 'a, 'a>( /// Checks that the correct number of generic arguments have been provided. /// Used specifically for function calls. -pub fn check_generic_arg_count_for_call( +pub fn check_generic_arg_count_for_value_path( cx: &dyn HirTyLowerer<'_>, def_id: DefId, generics: &ty::Generics, seg: &hir::PathSegment<'_>, is_method_call: IsMethodCall, ) -> GenericArgCountResult { - let gen_pos = match is_method_call { - IsMethodCall::Yes => GenericArgPosition::MethodCall, - IsMethodCall::No => GenericArgPosition::Value, - }; + let gen_pos = GenericArgPosition::Value(is_method_call); check_generic_arg_count(cx, def_id, seg, generics, gen_pos, generics.has_own_self()) } @@ -649,7 +646,7 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { let note = "the late bound lifetime parameter is introduced here"; let span = args.args[0].span(); - if position == GenericArgPosition::Value + if position == GenericArgPosition::Value(IsMethodCall::No) && args.num_lifetime_params() != param_counts.lifetimes { struct_span_code_err!(cx.dcx(), span, E0794, "{}", msg) diff --git a/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs b/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs index d79f38e097fb..bf3dc3b94275 100644 --- a/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs +++ b/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs @@ -38,8 +38,9 @@ use rustc_middle::middle::stability::AllowUnstable; use rustc_middle::ty::print::PrintPolyTraitRefExt as _; use rustc_middle::ty::{ - self, Const, GenericArgKind, GenericArgsRef, GenericParamDefKind, LitToConstInput, Ty, TyCtxt, - TypeSuperFoldable, TypeVisitableExt, TypingMode, Upcast, const_lit_matches_ty, fold_regions, + self, Const, FnSigKind, GenericArgKind, GenericArgsRef, GenericParamDefKind, LitToConstInput, + Ty, TyCtxt, TypeSuperFoldable, TypeVisitableExt, TypingMode, Upcast, const_lit_matches_ty, + fold_regions, }; use rustc_middle::{bug, span_bug}; use rustc_session::lint::builtin::AMBIGUOUS_ASSOCIATED_ITEMS; @@ -318,7 +319,7 @@ pub enum ExplicitLateBound { No, } -#[derive(Copy, Clone, PartialEq)] +#[derive(Debug, Copy, Clone, PartialEq)] pub enum IsMethodCall { Yes, No, @@ -329,8 +330,7 @@ pub enum IsMethodCall { #[derive(Debug, Copy, Clone, PartialEq)] pub(crate) enum GenericArgPosition { Type, - Value, // e.g., functions - MethodCall, + Value(IsMethodCall), } /// Whether to allow duplicate associated iten constraints in a trait ref, e.g. @@ -381,24 +381,44 @@ fn inferred_kind( ) -> ty::GenericArg<'tcx>; } -struct ForbidMCGParamUsesFolder<'tcx> { +/// Context in which `ForbidParamUsesFolder` is being used, to emit appropriate diagnostics. +enum ForbidParamContext { + /// Anon const in a const argument position. + ConstArgument, + /// Enum discriminant expression. + EnumDiscriminant, +} + +struct ForbidParamUsesFolder<'tcx> { tcx: TyCtxt<'tcx>, anon_const_def_id: LocalDefId, span: Span, is_self_alias: bool, + context: ForbidParamContext, } -impl<'tcx> ForbidMCGParamUsesFolder<'tcx> { +impl<'tcx> ForbidParamUsesFolder<'tcx> { fn error(&self) -> ErrorGuaranteed { - let msg = if self.is_self_alias { - "generic `Self` types are currently not permitted in anonymous constants" - } else if self.tcx.features().generic_const_args() { - "generic parameters in const blocks are only allowed as the direct value of a `type const`" - } else { - "generic parameters may not be used in const operations" + let msg = match self.context { + ForbidParamContext::EnumDiscriminant if self.is_self_alias => { + "generic `Self` types are not permitted in enum discriminant values" + } + ForbidParamContext::EnumDiscriminant => { + "generic parameters may not be used in enum discriminant values" + } + ForbidParamContext::ConstArgument if self.is_self_alias => { + "generic `Self` types are currently not permitted in anonymous constants" + } + ForbidParamContext::ConstArgument => { + if self.tcx.features().generic_const_args() { + "generic parameters in const blocks are only allowed as the direct value of a `type const`" + } else { + "generic parameters may not be used in const operations" + } + } }; let mut diag = self.tcx.dcx().struct_span_err(self.span, msg); - if self.is_self_alias { + if self.is_self_alias && matches!(self.context, ForbidParamContext::ConstArgument) { let anon_const_hir_id: HirId = HirId::make_owner(self.anon_const_def_id); let parent_impl = self.tcx.hir_parent_owner_iter(anon_const_hir_id).find_map( |(_, node)| match node { @@ -412,18 +432,20 @@ fn error(&self) -> ErrorGuaranteed { diag.span_note(impl_.self_ty.span, "not a concrete type"); } } - if self.tcx.features().min_generic_const_args() { + if matches!(self.context, ForbidParamContext::ConstArgument) + && self.tcx.features().min_generic_const_args() + { if !self.tcx.features().generic_const_args() { diag.help("add `#![feature(generic_const_args)]` to allow generic expressions as the RHS of const items"); } else { diag.help("consider factoring the expression into a `type const` item and use it as the const argument instead"); } - }; + } diag.emit() } } -impl<'tcx> ty::TypeFolder> for ForbidMCGParamUsesFolder<'tcx> { +impl<'tcx> ty::TypeFolder> for ForbidParamUsesFolder<'tcx> { fn cx(&self) -> TyCtxt<'tcx> { self.tcx } @@ -465,37 +487,80 @@ pub fn check_param_res_if_mcg_for_instantiate_value_path( && tcx.def_kind(parent_def_id) == DefKind::AnonConst && let ty::AnonConstKind::MCG = tcx.anon_const_kind(parent_def_id) { - let folder = ForbidMCGParamUsesFolder { + let folder = ForbidParamUsesFolder { tcx, anon_const_def_id: parent_def_id, span, is_self_alias: false, + context: ForbidParamContext::ConstArgument, }; return Err(folder.error()); } Ok(()) } + /// Returns the `ForbidParamContext` for the current anon const if it is a context that + /// forbids uses of generic parameters. `None` if the current item is not such a context. + /// + /// Name resolution handles most invalid generic parameter uses in these contexts, but it + /// cannot reject `Self` that aliases a generic type, nor generic parameters introduced by + /// type-dependent name resolution (e.g. `::Assoc` resolving to a type that + /// contains params). Those cases are handled by `check_param_uses_if_mcg`. + fn anon_const_forbids_generic_params(&self) -> Option { + let tcx = self.tcx(); + let parent_def_id = self.item_def_id(); + + // Inline consts and closures can be nested inside anon consts that forbid generic + // params (e.g. an enum discriminant). Walk up the def parent chain to find the + // nearest enclosing AnonConst and use that to determine the context. + let anon_const_def_id = match tcx.def_kind(parent_def_id) { + DefKind::AnonConst => parent_def_id, + DefKind::InlineConst | DefKind::Closure => { + let root = tcx.typeck_root_def_id(parent_def_id.into()); + match tcx.def_kind(root) { + DefKind::AnonConst => root.expect_local(), + _ => return None, + } + } + _ => return None, + }; + + match tcx.anon_const_kind(anon_const_def_id) { + ty::AnonConstKind::MCG => Some(ForbidParamContext::ConstArgument), + ty::AnonConstKind::NonTypeSystem => { + // NonTypeSystem anon consts only have accessible generic parameters in specific + // positions (ty patterns and field defaults — see `generics_of`). In all other + // positions (e.g. enum discriminants) generic parameters are not in scope. + if tcx.generics_of(anon_const_def_id).count() == 0 { + Some(ForbidParamContext::EnumDiscriminant) + } else { + None + } + } + ty::AnonConstKind::GCE + | ty::AnonConstKind::GCA + | ty::AnonConstKind::RepeatExprCount => None, + } + } + /// Check for uses of generic parameters that are not in scope due to this being - /// in a non-generic anon const context. + /// in a non-generic anon const context (e.g. MCG or an enum discriminant). + /// + /// Name resolution rejects most invalid uses, but cannot handle `Self` aliasing a + /// generic type or generic parameters introduced by type-dependent name resolution. #[must_use = "need to use transformed output"] fn check_param_uses_if_mcg(&self, term: T, span: Span, is_self_alias: bool) -> T where T: ty::TypeFoldable>, { let tcx = self.tcx(); - let parent_def_id = self.item_def_id(); - if tcx.def_kind(parent_def_id) == DefKind::AnonConst - && let ty::AnonConstKind::MCG = tcx.anon_const_kind(parent_def_id) + if let Some(context) = self.anon_const_forbids_generic_params() // Fast path if contains no params/escaping bound vars. && (term.has_param() || term.has_escaping_bound_vars()) { - let mut folder = ForbidMCGParamUsesFolder { - tcx, - anon_const_def_id: parent_def_id, - span, - is_self_alias, - }; + let anon_const_def_id = self.item_def_id(); + let mut folder = + ForbidParamUsesFolder { tcx, anon_const_def_id, span, is_self_alias, context }; term.fold_with(&mut folder) } else { term @@ -561,14 +626,7 @@ pub fn lower_generic_args_of_path_segment( def_id: DefId, item_segment: &hir::PathSegment<'tcx>, ) -> GenericArgsRef<'tcx> { - let (args, _) = self.lower_generic_args_of_path( - span, - def_id, - &[], - item_segment, - None, - GenericArgPosition::Type, - ); + let (args, _) = self.lower_generic_args_of_path(span, def_id, &[], item_segment, None); if let Some(c) = item_segment.args().constraints.first() { prohibit_assoc_item_constraint(self, c, Some((def_id, item_segment, span))); } @@ -617,7 +675,6 @@ pub(crate) fn lower_generic_args_of_path( parent_args: &[ty::GenericArg<'tcx>], segment: &hir::PathSegment<'tcx>, self_ty: Option>, - pos: GenericArgPosition, ) -> (GenericArgsRef<'tcx>, GenericArgCountResult) { // If the type is parameterized by this region, then replace this // region with the current anon region binding (in other words, @@ -640,8 +697,14 @@ pub(crate) fn lower_generic_args_of_path( assert!(self_ty.is_none()); } - let arg_count = - check_generic_arg_count(self, def_id, segment, generics, pos, self_ty.is_some()); + let arg_count = check_generic_arg_count( + self, + def_id, + segment, + generics, + GenericArgPosition::Type, + self_ty.is_some(), + ); // Skip processing if type has no generic parameters. // Traits always have `Self` as a generic parameter, which means they will not return early @@ -750,7 +813,7 @@ fn inferred_kind( GenericParamDefKind::Lifetime => { self.lowerer.re_infer(self.span, RegionInferReason::Param(param)).into() } - GenericParamDefKind::Type { has_default, .. } => { + GenericParamDefKind::Type { has_default, synthetic } => { if !infer_args && has_default { // No type parameter provided, but a default exists. if let Some(prev) = @@ -766,6 +829,8 @@ fn inferred_kind( .type_of(param.def_id) .instantiate(tcx, preceding_args) .into() + } else if synthetic { + Ty::new_param(tcx, param.index, param.name).into() } else if infer_args { self.lowerer.ty_infer(Some(param), self.span).into() } else { @@ -826,14 +891,8 @@ pub fn lower_generic_args_of_assoc_item( item_segment: &hir::PathSegment<'tcx>, parent_args: GenericArgsRef<'tcx>, ) -> GenericArgsRef<'tcx> { - let (args, _) = self.lower_generic_args_of_path( - span, - item_def_id, - parent_args, - item_segment, - None, - GenericArgPosition::Type, - ); + let (args, _) = + self.lower_generic_args_of_path(span, item_def_id, parent_args, item_segment, None); if let Some(c) = item_segment.args().constraints.first() { prohibit_assoc_item_constraint(self, c, Some((item_def_id, item_segment, span))); } @@ -945,7 +1004,6 @@ pub(crate) fn lower_poly_trait_ref( &[], segment, Some(self_ty), - GenericArgPosition::Type, ); let constraints = segment.args().constraints; @@ -1121,14 +1179,8 @@ fn lower_mono_trait_ref( ) -> ty::TraitRef<'tcx> { self.report_internal_fn_trait(span, trait_def_id, trait_segment, is_impl); - let (generic_args, _) = self.lower_generic_args_of_path( - span, - trait_def_id, - &[], - trait_segment, - Some(self_ty), - GenericArgPosition::Type, - ); + let (generic_args, _) = + self.lower_generic_args_of_path(span, trait_def_id, &[], trait_segment, Some(self_ty)); if let Some(c) = trait_segment.args().constraints.first() { prohibit_assoc_item_constraint(self, c, Some((trait_def_id, trait_segment, span))); } @@ -1150,22 +1202,22 @@ fn probe_trait_that_defines_assoc_item( fn lower_path_segment( &self, span: Span, - did: DefId, + def_id: DefId, item_segment: &hir::PathSegment<'tcx>, ) -> Ty<'tcx> { let tcx = self.tcx(); - let args = self.lower_generic_args_of_path_segment(span, did, item_segment); + let args = self.lower_generic_args_of_path_segment(span, def_id, item_segment); - if let DefKind::TyAlias = tcx.def_kind(did) - && tcx.type_alias_is_lazy(did) + if let DefKind::TyAlias = tcx.def_kind(def_id) + && tcx.type_alias_is_lazy(def_id) { // Type aliases defined in crates that have the // feature `lazy_type_alias` enabled get encoded as a type alias that normalization will // then actually instantiate the where bounds of. - let alias_ty = ty::AliasTy::new_from_args(tcx, ty::Free { def_id: did }, args); + let alias_ty = ty::AliasTy::new_from_args(tcx, ty::Free { def_id }, args); Ty::new_alias(tcx, alias_ty) } else { - tcx.at(span).type_of(did).instantiate(tcx, args) + tcx.at(span).type_of(def_id).instantiate(tcx, args) } } @@ -3527,7 +3579,11 @@ pub fn lower_fn_ty( debug!(?output_ty); - let fn_ty = tcx.mk_fn_sig(input_tys, output_ty, decl.c_variadic, safety, abi); + let fn_sig_kind = FnSigKind::default() + .set_abi(abi) + .set_safe(safety.is_safe()) + .set_c_variadic(decl.fn_decl_kind.c_variadic()); + let fn_ty = tcx.mk_fn_sig(input_tys, output_ty, fn_sig_kind); let fn_ptr_ty = ty::Binder::bind_with_vars(fn_ty, bound_vars); if let hir::Node::Ty(hir::Ty { kind: hir::TyKind::FnPtr(fn_ptr_ty), span, .. }) = diff --git a/compiler/rustc_hir_analysis/src/impl_wf_check/min_specialization.rs b/compiler/rustc_hir_analysis/src/impl_wf_check/min_specialization.rs index 41af59388f79..47bd2fd37dff 100644 --- a/compiler/rustc_hir_analysis/src/impl_wf_check/min_specialization.rs +++ b/compiler/rustc_hir_analysis/src/impl_wf_check/min_specialization.rs @@ -190,7 +190,7 @@ fn get_impl_args( } let assumed_wf_types = ocx.assumed_wf_types_and_report_errors(param_env, impl1_def_id)?; - let _ = ocx.resolve_regions_and_report_errors(impl1_def_id, param_env, assumed_wf_types); + ocx.resolve_regions_and_report_errors(impl1_def_id, param_env, assumed_wf_types)?; let Ok(impl2_args) = infcx.fully_resolve(impl2_args) else { let span = tcx.def_span(impl1_def_id); let guar = tcx.dcx().emit_err(GenericArgsOnOverriddenImpl { span }); diff --git a/compiler/rustc_hir_analysis/src/lib.rs b/compiler/rustc_hir_analysis/src/lib.rs index 937bcee01161..0721bfcab519 100644 --- a/compiler/rustc_hir_analysis/src/lib.rs +++ b/compiler/rustc_hir_analysis/src/lib.rs @@ -97,7 +97,7 @@ use crate::hir_ty_lowering::HirTyLowerer; fn check_c_variadic_abi(tcx: TyCtxt<'_>, decl: &hir::FnDecl<'_>, abi: ExternAbi, span: Span) { - if !decl.c_variadic { + if !decl.c_variadic() { // Not even a variadic function. return; } diff --git a/compiler/rustc_hir_pretty/src/lib.rs b/compiler/rustc_hir_pretty/src/lib.rs index 82540a932741..46aed3c5cd08 100644 --- a/compiler/rustc_hir_pretty/src/lib.rs +++ b/compiler/rustc_hir_pretty/src/lib.rs @@ -761,6 +761,7 @@ fn print_item(&mut self, item: &hir::Item<'_>) { constness, is_auto, safety, + impl_restriction, ident, generics, bounds, @@ -770,6 +771,7 @@ fn print_item(&mut self, item: &hir::Item<'_>) { self.print_constness(constness); self.print_is_auto(is_auto); self.print_safety(safety); + self.print_impl_restriction(impl_restriction); self.word_nbsp("trait"); self.print_ident(ident); self.print_generic_params(generics.params); @@ -2262,8 +2264,8 @@ fn print_fn( assert!(arg_idents.is_empty() || body_id.is_none()); let mut i = 0; let mut print_arg = |s: &mut Self, ty: Option<&hir::Ty<'_>>| { - if i == 0 && decl.implicit_self.has_implicit_self() { - s.print_implicit_self(&decl.implicit_self); + if i == 0 && decl.implicit_self().has_implicit_self() { + s.print_implicit_self(&decl.implicit_self()); } else { if let Some(arg_ident) = arg_idents.get(i) { if let Some(arg_ident) = arg_ident { @@ -2287,7 +2289,7 @@ fn print_fn( print_arg(s, Some(ty)); s.end(ib); }); - if decl.c_variadic { + if decl.c_variadic() { if !decl.inputs.is_empty() { self.word(", "); } @@ -2645,6 +2647,18 @@ fn print_is_auto(&mut self, s: hir::IsAuto) { hir::IsAuto::No => {} } } + + fn print_impl_restriction(&mut self, r: &hir::ImplRestriction<'_>) { + match r.kind { + hir::RestrictionKind::Unrestricted => {} + hir::RestrictionKind::Restricted(path) => { + self.word("impl("); + self.word_nbsp("in"); + self.print_path(path, false); + self.word(")"); + } + } + } } /// Does this expression require a semicolon to be treated diff --git a/compiler/rustc_hir_typeck/src/callee.rs b/compiler/rustc_hir_typeck/src/callee.rs index 93662b36a05d..848fb7118bbf 100644 --- a/compiler/rustc_hir_typeck/src/callee.rs +++ b/compiler/rustc_hir_typeck/src/callee.rs @@ -89,11 +89,11 @@ pub(crate) fn check_expr_call( match *autoderef.final_ty().kind() { ty::FnDef(def_id, _) => { - let abi = self.tcx.fn_sig(def_id).skip_binder().skip_binder().abi; + let abi = self.tcx.fn_sig(def_id).skip_binder().skip_binder().abi(); self.check_call_abi(abi, call_expr.span); } ty::FnPtr(_, header) => { - self.check_call_abi(header.abi, call_expr.span); + self.check_call_abi(header.abi(), call_expr.span); } _ => { /* cannot have a non-rust abi */ } } @@ -275,9 +275,7 @@ fn try_overloaded_call_step( self.tcx.coroutine_for_closure(def_id), tupled_upvars_ty, ), - coroutine_closure_sig.c_variadic, - coroutine_closure_sig.safety, - coroutine_closure_sig.abi, + coroutine_closure_sig.fn_sig_kind, ); let adjustments = self.adjust_steps(autoderef); self.record_deferred_call_resolution( @@ -595,12 +593,12 @@ fn confirm_builtin_call( fn_sig.output(), expected, arg_exprs, - fn_sig.c_variadic, + fn_sig.c_variadic(), TupleArgumentsFlag::DontTupleArguments, def_id, ); - if fn_sig.abi == rustc_abi::ExternAbi::RustCall { + if fn_sig.abi() == rustc_abi::ExternAbi::RustCall { let sp = arg_exprs.last().map_or(call_expr.span, |expr| expr.span); if let Some(ty) = fn_sig.inputs().last().copied() { self.register_bound( @@ -905,7 +903,7 @@ fn confirm_deferred_closure_call( fn_sig.output(), expected, arg_exprs, - fn_sig.c_variadic, + fn_sig.c_variadic(), TupleArgumentsFlag::TupleArguments, Some(closure_def_id.to_def_id()), ); @@ -921,6 +919,14 @@ pub(super) fn enforce_context_effects( callee_did: DefId, callee_args: GenericArgsRef<'tcx>, ) { + // FIXME(const_trait_impl): We should be enforcing these effects unconditionally. + // This can be done as soon as we convert the standard library back to + // using const traits, since if we were to enforce these conditions now, + // we'd fail on basically every builtin trait call (i.e. `1 + 2`). + if !self.tcx.features().const_trait_impl() { + return; + } + // If we have `rustc_do_not_const_check`, do not check `[const]` bounds. if self.has_rustc_attrs && find_attr!(self.tcx, self.body_id, RustcDoNotConstCheck) { return; @@ -976,7 +982,7 @@ fn confirm_overloaded_call( method.sig.output(), expected, arg_exprs, - method.sig.c_variadic, + method.sig.c_variadic(), TupleArgumentsFlag::TupleArguments, Some(method.def_id), ); diff --git a/compiler/rustc_hir_typeck/src/check.rs b/compiler/rustc_hir_typeck/src/check.rs index 612396858841..25bba0def5c6 100644 --- a/compiler/rustc_hir_typeck/src/check.rs +++ b/compiler/rustc_hir_typeck/src/check.rs @@ -1,6 +1,5 @@ use std::cell::RefCell; -use rustc_abi::ExternAbi; use rustc_hir as hir; use rustc_hir::def::DefKind; use rustc_hir::lang_items::LangItem; @@ -55,7 +54,7 @@ pub(super) fn check_fn<'a, 'tcx>( // C-variadic fns also have a `VaList` input that's not listed in `fn_sig` // (as it's created inside the body itself, not passed in from outside). - let maybe_va_list = fn_sig.c_variadic.then(|| { + let maybe_va_list = fn_sig.c_variadic().then(|| { let span = body.params.last().unwrap().span; let va_list_did = tcx.require_lang_item(LangItem::VaList, span); let region = fcx.next_region_var(RegionVariableOrigin::Misc(span)); @@ -204,7 +203,7 @@ fn check_panic_info_fn(tcx: TyCtxt<'_>, fn_id: LocalDefId, fn_sig: ty::FnSig<'_> ty::BoundVariableKind::Region(ty::BoundRegionKind::Anon), ]); let expected_sig = ty::Binder::bind_with_vars( - tcx.mk_fn_sig([panic_info_ref_ty], tcx.types.never, false, fn_sig.safety, ExternAbi::Rust), + tcx.mk_fn_sig_rust_abi([panic_info_ref_ty], tcx.types.never, fn_sig.safety()), bounds, ); @@ -225,12 +224,10 @@ fn check_lang_start_fn<'tcx>(tcx: TyCtxt<'tcx>, fn_sig: ty::FnSig<'tcx>, def_id: let generics = tcx.generics_of(def_id); let fn_generic = generics.param_at(0, tcx); let generic_ty = Ty::new_param(tcx, fn_generic.index, fn_generic.name); - let main_fn_ty = Ty::new_fn_ptr( - tcx, - Binder::dummy(tcx.mk_fn_sig([], generic_ty, false, hir::Safety::Safe, ExternAbi::Rust)), - ); + let main_fn_ty = + Ty::new_fn_ptr(tcx, Binder::dummy(tcx.mk_fn_sig_safe_rust_abi([], generic_ty))); - let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig( + let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig_rust_abi( [ main_fn_ty, tcx.types.isize, @@ -238,9 +235,7 @@ fn check_lang_start_fn<'tcx>(tcx: TyCtxt<'tcx>, fn_sig: ty::FnSig<'tcx>, def_id: tcx.types.u8, ], tcx.types.isize, - false, - fn_sig.safety, - ExternAbi::Rust, + fn_sig.safety(), )); let _ = check_function_signature( diff --git a/compiler/rustc_hir_typeck/src/closure.rs b/compiler/rustc_hir_typeck/src/closure.rs index 28bb9c5cd75b..0597a60f9f8c 100644 --- a/compiler/rustc_hir_typeck/src/closure.rs +++ b/compiler/rustc_hir_typeck/src/closure.rs @@ -13,7 +13,7 @@ use rustc_macros::{TypeFoldable, TypeVisitable}; use rustc_middle::span_bug; use rustc_middle::ty::{ - self, ClosureKind, GenericArgs, Ty, TyCtxt, TypeSuperVisitable, TypeVisitable, + self, ClosureKind, FnSigKind, GenericArgs, Ty, TyCtxt, TypeSuperVisitable, TypeVisitable, TypeVisitableExt, TypeVisitor, }; use rustc_span::def_id::LocalDefId; @@ -85,13 +85,7 @@ pub(crate) fn check_expr_closure( // Tuple up the arguments and insert the resulting function type into // the `closures` table. let sig = bound_sig.map_bound(|sig| { - tcx.mk_fn_sig( - [Ty::new_tup(tcx, sig.inputs())], - sig.output(), - sig.c_variadic, - sig.safety, - sig.abi, - ) + tcx.mk_fn_sig([Ty::new_tup(tcx, sig.inputs())], sig.output(), sig.fn_sig_kind) }); debug!(?sig, ?expected_kind); @@ -231,9 +225,7 @@ pub(crate) fn check_expr_closure( Ty::new_tup_from_iter(tcx, sig.inputs().iter().copied()), ], Ty::new_tup(tcx, &[bound_yield_ty, bound_return_ty]), - sig.c_variadic, - sig.safety, - sig.abi, + sig.fn_sig_kind, ) }), ), @@ -273,9 +265,7 @@ pub(crate) fn check_expr_closure( liberated_sig = tcx.mk_fn_sig( liberated_sig.inputs().iter().copied(), coroutine_output_ty, - liberated_sig.c_variadic, - liberated_sig.safety, - liberated_sig.abi, + liberated_sig.fn_sig_kind, ); (Ty::new_coroutine_closure(tcx, expr_def_id.to_def_id(), closure_args.args), None) @@ -544,13 +534,7 @@ fn extract_sig_from_projection( let ret_param_ty = projection.skip_binder().term.expect_type(); debug!(?ret_param_ty); - let sig = projection.rebind(self.tcx.mk_fn_sig( - input_tys, - ret_param_ty, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )); + let sig = projection.rebind(self.tcx.mk_fn_sig_safe_rust_abi(input_tys, ret_param_ty)); Some(ExpectedSig { cause_span, sig }) } @@ -630,13 +614,7 @@ fn extract_sig_from_projection_and_future_bound( let return_ty = return_ty.unwrap_or_else(|| self.next_ty_var(cause_span.unwrap_or(DUMMY_SP))); - let sig = projection.rebind(self.tcx.mk_fn_sig( - input_tys, - return_ty, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )); + let sig = projection.rebind(self.tcx.mk_fn_sig_safe_rust_abi(input_tys, return_ty)); Some(ExpectedSig { cause_span, sig }) } @@ -727,7 +705,7 @@ fn sig_of_closure_with_expectation( // Watch out for some surprises and just ignore the // expectation if things don't see to match up with what we // expect. - if expected_sig.sig.c_variadic() != decl.c_variadic { + if expected_sig.sig.c_variadic() != decl.c_variadic() { return self.sig_of_closure_no_expectation(expr_def_id, decl, closure_kind); } else if expected_sig.sig.skip_binder().inputs_and_output.len() != decl.inputs.len() + 1 { return self.sig_of_closure_with_mismatched_number_of_arguments( @@ -742,13 +720,11 @@ fn sig_of_closure_with_expectation( // in this binder we are creating. assert!(!expected_sig.sig.skip_binder().has_vars_bound_above(ty::INNERMOST)); let bound_sig = expected_sig.sig.map_bound(|sig| { - self.tcx.mk_fn_sig( - sig.inputs().iter().cloned(), - sig.output(), - sig.c_variadic, - hir::Safety::Safe, - ExternAbi::RustCall, - ) + let fn_sig_kind = FnSigKind::default() + .set_abi(ExternAbi::RustCall) + .set_safe(true) + .set_c_variadic(sig.c_variadic()); + self.tcx.mk_fn_sig(sig.inputs().iter().cloned(), sig.output(), fn_sig_kind) }); // `deduce_expectations_from_expected_type` introduces @@ -881,13 +857,12 @@ fn merge_supplied_sig_with_expectation( let inputs = supplied_sig.inputs().into_iter().map(|&ty| self.resolve_vars_if_possible(ty)); - expected_sigs.liberated_sig = self.tcx.mk_fn_sig( - inputs, - supplied_output_ty, - expected_sigs.liberated_sig.c_variadic, - hir::Safety::Safe, - ExternAbi::RustCall, - ); + let fn_sig_kind = FnSigKind::default() + .set_abi(ExternAbi::RustCall) + .set_safe(true) + .set_c_variadic(expected_sigs.liberated_sig.c_variadic()); + expected_sigs.liberated_sig = + self.tcx.mk_fn_sig(inputs, supplied_output_ty, fn_sig_kind); Ok(InferOk { value: expected_sigs, obligations: all_obligations }) }) @@ -957,14 +932,12 @@ fn supplied_sig_of_closure( }, }; + let fn_sig_kind = FnSigKind::default() + .set_abi(ExternAbi::RustCall) + .set_safe(true) + .set_c_variadic(decl.c_variadic()); let result = ty::Binder::bind_with_vars( - self.tcx.mk_fn_sig( - supplied_arguments, - supplied_return, - decl.c_variadic, - hir::Safety::Safe, - ExternAbi::RustCall, - ), + self.tcx.mk_fn_sig(supplied_arguments, supplied_return, fn_sig_kind), bound_vars, ); @@ -1121,13 +1094,11 @@ fn error_sig_of_closure( lowerer.lower_ty(output); } - let result = ty::Binder::dummy(self.tcx.mk_fn_sig( - supplied_arguments, - err_ty, - decl.c_variadic, - hir::Safety::Safe, - ExternAbi::RustCall, - )); + let fn_sig_kind = FnSigKind::default() + .set_abi(ExternAbi::RustCall) + .set_safe(true) + .set_c_variadic(decl.c_variadic()); + let result = ty::Binder::dummy(self.tcx.mk_fn_sig(supplied_arguments, err_ty, fn_sig_kind)); debug!("supplied_sig_of_closure: result={:?}", result); diff --git a/compiler/rustc_hir_typeck/src/coercion.rs b/compiler/rustc_hir_typeck/src/coercion.rs index bfc677046e0f..444e6f2e3c77 100644 --- a/compiler/rustc_hir_typeck/src/coercion.rs +++ b/compiler/rustc_hir_typeck/src/coercion.rs @@ -944,7 +944,7 @@ fn coerce_from_fn_pointer( debug_assert!(self.shallow_resolve(b) == b); match b.kind() { - ty::FnPtr(_, b_hdr) if a_sig.safety().is_safe() && b_hdr.safety.is_unsafe() => { + ty::FnPtr(_, b_hdr) if a_sig.safety().is_safe() && b_hdr.safety().is_unsafe() => { let a = self.tcx.safe_to_unsafe_fn_ty(a_sig); let adjust = Adjust::Pointer(PointerCoercion::UnsafeFnPointer); self.unify_and(a, b, [], adjust, ForceLeakCheck::Yes) @@ -960,13 +960,13 @@ fn coerce_from_fn_item(&self, a: Ty<'tcx>, b: Ty<'tcx>) -> CoerceResult<'tcx> { match b.kind() { ty::FnPtr(_, b_hdr) => { - let a_sig = self.sig_for_fn_def_coercion(a, Some(b_hdr.safety))?; + let a_sig = self.sig_for_fn_def_coercion(a, Some(b_hdr.safety()))?; let InferOk { value: a_sig, mut obligations } = self.at(&self.cause, self.param_env).normalize(a_sig); let a = Ty::new_fn_ptr(self.tcx, a_sig); - let adjust = Adjust::Pointer(PointerCoercion::ReifyFnPointer(b_hdr.safety)); + let adjust = Adjust::Pointer(PointerCoercion::ReifyFnPointer(b_hdr.safety())); let InferOk { value, obligations: o2 } = self.unify_and(a, b, [], adjust, ForceLeakCheck::Yes)?; @@ -985,9 +985,9 @@ fn coerce_closure_to_fn(&self, a: Ty<'tcx>, b: Ty<'tcx>) -> CoerceResult<'tcx> { match b.kind() { ty::FnPtr(_, hdr) => { - let safety = hdr.safety; + let safety = hdr.safety(); let terr = TypeError::Sorts(ty::error::ExpectedFound::new(a, b)); - let closure_sig = self.sig_for_closure_coercion(a, Some(hdr.safety), terr)?; + let closure_sig = self.sig_for_closure_coercion(a, Some(hdr.safety()), terr)?; let pointer_ty = Ty::new_fn_ptr(self.tcx, closure_sig); debug!("coerce_closure_to_fn(a={:?}, b={:?}, pty={:?})", a, b, pointer_ty); diff --git a/compiler/rustc_hir_typeck/src/demand.rs b/compiler/rustc_hir_typeck/src/demand.rs index 0d49e0624053..29fc6729e4b3 100644 --- a/compiler/rustc_hir_typeck/src/demand.rs +++ b/compiler/rustc_hir_typeck/src/demand.rs @@ -346,7 +346,7 @@ fn visit_expr(&mut self, ex: &'tcx hir::Expr<'tcx>) { match infer { ty::TyVar(_) => self.next_ty_var(DUMMY_SP), ty::IntVar(_) => self.next_int_var(), - ty::FloatVar(_) => self.next_float_var(), + ty::FloatVar(_) => self.next_float_var(DUMMY_SP, None), ty::FreshTy(_) | ty::FreshIntTy(_) | ty::FreshFloatTy(_) => { bug!("unexpected fresh ty outside of the trait solver") } diff --git a/compiler/rustc_hir_typeck/src/errors.rs b/compiler/rustc_hir_typeck/src/errors.rs index 6eef15684697..b55e7933cc1e 100644 --- a/compiler/rustc_hir_typeck/src/errors.rs +++ b/compiler/rustc_hir_typeck/src/errors.rs @@ -1384,3 +1384,15 @@ pub(crate) struct ProjectOnNonPinProjectType { )] pub sugg_span: Option, } + +#[derive(Diagnostic)] +#[diag("falling back to `f32` as the trait bound `f32: From` is not satisfied")] +pub(crate) struct FloatLiteralF32Fallback { + pub literal: String, + #[suggestion( + "explicitly specify the type as `f32`", + code = "{literal}_f32", + applicability = "machine-applicable" + )] + pub span: Option, +} diff --git a/compiler/rustc_hir_typeck/src/expr.rs b/compiler/rustc_hir_typeck/src/expr.rs index b288720db9cc..5ee6dee9e1ef 100644 --- a/compiler/rustc_hir_typeck/src/expr.rs +++ b/compiler/rustc_hir_typeck/src/expr.rs @@ -16,10 +16,11 @@ Applicability, Diag, ErrorGuaranteed, MultiSpan, StashKey, Subdiagnostic, listify, pluralize, struct_span_code_err, }; +use rustc_hir as hir; use rustc_hir::def::{CtorKind, DefKind, Res}; use rustc_hir::def_id::DefId; use rustc_hir::lang_items::LangItem; -use rustc_hir::{self as hir, Attribute, ExprKind, HirId, QPath, find_attr, is_range_literal}; +use rustc_hir::{ExprKind, HirId, QPath, find_attr, is_range_literal}; use rustc_hir_analysis::NoVariantNamed; use rustc_hir_analysis::errors::NoFieldOnType; use rustc_hir_analysis::hir_ty_lowering::HirTyLowerer as _; @@ -55,21 +56,26 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { pub(crate) fn precedence(&self, expr: &hir::Expr<'_>) -> ExprPrecedence { - // For the purpose of rendering suggestions, disregard attributes - // that originate from desugaring of any kind. For example, `x?` - // desugars to `#[allow(unreachable_code)] match ...`. Failing to - // ignore the prefix attribute in the desugaring would cause this - // suggestion: - // - // let y: u32 = x?.try_into().unwrap(); - // ++++++++++++++++++++ - // - // to be rendered as: - // - // let y: u32 = (x?).try_into().unwrap(); - // + +++++++++++++++++++++ let has_attr = |id: HirId| -> bool { - self.tcx.hir_attrs(id).iter().any(Attribute::has_span_without_desugaring_kind) + for attr in self.tcx.hir_attrs(id) { + // For the purpose of rendering suggestions, disregard attributes + // that originate from desugaring of any kind. For example, `x?` + // desugars to `#[allow(unreachable_code)] match ...`. Failing to + // ignore the prefix attribute in the desugaring would cause this + // suggestion: + // + // let y: u32 = x?.try_into().unwrap(); + // ++++++++++++++++++++ + // + // to be rendered as: + // + // let y: u32 = (x?).try_into().unwrap(); + // + +++++++++++++++++++++ + if attr.span().desugaring_kind().is_none() { + return true; + } + } + false }; // Special case: range expressions are desugared to struct literals in HIR, @@ -343,7 +349,7 @@ fn check_expr_kind( let tcx = self.tcx; match expr.kind { - ExprKind::Lit(ref lit) => self.check_expr_lit(lit, expected), + ExprKind::Lit(ref lit) => self.check_expr_lit(lit, expr.hir_id, expected), ExprKind::Binary(op, lhs, rhs) => self.check_expr_binop(expr, op, lhs, rhs, expected), ExprKind::Assign(lhs, rhs, span) => { self.check_expr_assign(expr, expected, lhs, rhs, span) @@ -1483,12 +1489,12 @@ fn check_expr_method_call( method.sig.output(), expected, args, - method.sig.c_variadic, + method.sig.c_variadic(), TupleArgumentsFlag::DontTupleArguments, Some(method.def_id), ); - self.check_call_abi(method.sig.abi, expr.span); + self.check_call_abi(method.sig.abi(), expr.span); method.sig.output() } @@ -3551,6 +3557,8 @@ fn find_and_report_unsatisfied_index_impl( // Register the impl's predicates. One of these predicates // must be unsatisfied, or else we wouldn't have gotten here // in the first place. + let unnormalized_predicates = + self.tcx.predicates_of(impl_def_id).instantiate(self.tcx, impl_args); ocx.register_obligations(traits::predicates_for_generics( |idx, span| { cause.clone().derived_cause( @@ -3568,8 +3576,9 @@ fn find_and_report_unsatisfied_index_impl( }, ) }, + |pred| ocx.normalize(&cause, self.param_env, pred), self.param_env, - self.tcx.predicates_of(impl_def_id).instantiate(self.tcx, impl_args), + unnormalized_predicates, )); // Normalize the output type, which we can use later on as the diff --git a/compiler/rustc_hir_typeck/src/fallback.rs b/compiler/rustc_hir_typeck/src/fallback.rs index 5aadf37720d0..84b09d4ab477 100644 --- a/compiler/rustc_hir_typeck/src/fallback.rs +++ b/compiler/rustc_hir_typeck/src/fallback.rs @@ -5,13 +5,13 @@ use rustc_data_structures::graph; use rustc_data_structures::graph::vec_graph::VecGraph; use rustc_data_structures::unord::{UnordMap, UnordSet}; -use rustc_hir as hir; -use rustc_hir::HirId; use rustc_hir::attrs::DivergingFallbackBehavior; use rustc_hir::def::{DefKind, Res}; use rustc_hir::def_id::DefId; use rustc_hir::intravisit::{InferKind, Visitor}; -use rustc_middle::ty::{self, Ty, TyCtxt, TypeSuperVisitable, TypeVisitable}; +use rustc_hir::{self as hir, CRATE_HIR_ID, HirId}; +use rustc_lint::builtin::FLOAT_LITERAL_F32_FALLBACK; +use rustc_middle::ty::{self, FloatVid, Ty, TyCtxt, TypeSuperVisitable, TypeVisitable}; use rustc_session::lint; use rustc_span::def_id::LocalDefId; use rustc_span::{DUMMY_SP, Span}; @@ -55,6 +55,7 @@ fn fallback_types(&self) -> bool { let (diverging_fallback, diverging_fallback_ty) = self.calculate_diverging_fallback(&unresolved_variables); + let fallback_to_f32 = self.calculate_fallback_to_f32(&unresolved_variables); // We do fallback in two passes, to try to generate // better error messages. @@ -62,8 +63,12 @@ fn fallback_types(&self) -> bool { let mut fallback_occurred = false; for ty in unresolved_variables { debug!("unsolved_variable = {:?}", ty); - fallback_occurred |= - self.fallback_if_possible(ty, &diverging_fallback, diverging_fallback_ty); + fallback_occurred |= self.fallback_if_possible( + ty, + &diverging_fallback, + diverging_fallback_ty, + &fallback_to_f32, + ); } fallback_occurred @@ -73,7 +78,8 @@ fn fallback_types(&self) -> bool { /// /// - Unconstrained ints are replaced with `i32`. /// - /// - Unconstrained floats are replaced with `f64`. + /// - Unconstrained floats are replaced with `f64`, except when there is a trait predicate + /// `f32: From<{float}>`, in which case `f32` is used as the fallback instead. /// /// - Non-numerics may get replaced with `()` or `!`, depending on how they /// were categorized by [`Self::calculate_diverging_fallback`], crate's @@ -89,6 +95,7 @@ fn fallback_if_possible( ty: Ty<'tcx>, diverging_fallback: &UnordSet>, diverging_fallback_ty: Ty<'tcx>, + fallback_to_f32: &UnordSet, ) -> bool { // Careful: we do NOT shallow-resolve `ty`. We know that `ty` // is an unsolved variable, and we determine its fallback @@ -111,6 +118,7 @@ fn fallback_if_possible( let fallback = match ty.kind() { _ if let Some(e) = self.tainted_by_errors() => Ty::new_error(self.tcx, e), ty::Infer(ty::IntVar(_)) => self.tcx.types.i32, + ty::Infer(ty::FloatVar(vid)) if fallback_to_f32.contains(vid) => self.tcx.types.f32, ty::Infer(ty::FloatVar(_)) => self.tcx.types.f64, _ if diverging_fallback.contains(&ty) => { self.diverging_fallback_has_occurred.set(true); @@ -125,6 +133,52 @@ fn fallback_if_possible( true } + /// Existing code relies on `f32: From` (usually written as `T: Into`) resolving `T` to + /// `f32` when the type of `T` is inferred from an unsuffixed float literal. Using the default + /// fallback of `f64`, this would break when adding `impl From for f32`, as there are now + /// two float type which could be `T`, meaning that the fallback of `f64` would be used and + /// compilation error would occur as `f32` does not implement `From`. To avoid breaking + /// existing code, we instead fallback `T` to `f32` when there is a trait predicate + /// `f32: From`. This means code like the following will continue to compile: + /// + /// ```rust + /// fn foo>(_: T) {} + /// + /// foo(1.0); + /// ``` + fn calculate_fallback_to_f32(&self, unresolved_variables: &[Ty<'tcx>]) -> UnordSet { + let roots: UnordSet = self.from_float_for_f32_root_vids(); + if roots.is_empty() { + // Most functions have no `f32: From<{float}>` predicates, so short-circuit and return + // an empty set when this is the case. + return UnordSet::new(); + } + // Calculate all the unresolved variables that need to fallback to `f32` here. This ensures + // we don't need to find root variables in `fallback_if_possible`: see the comment at the + // top of that function for details. + let fallback_to_f32 = unresolved_variables + .iter() + .flat_map(|ty| ty.float_vid()) + .filter(|vid| roots.contains(&self.root_float_var(*vid))) + .inspect(|vid| { + let origin = self.float_var_origin(*vid); + // Show the entire literal in the suggestion to make it clearer. + let literal = self.tcx.sess.source_map().span_to_snippet(origin.span).ok(); + self.tcx.emit_node_span_lint( + FLOAT_LITERAL_F32_FALLBACK, + origin.lint_id.unwrap_or(CRATE_HIR_ID), + origin.span, + errors::FloatLiteralF32Fallback { + span: literal.as_ref().map(|_| origin.span), + literal: literal.unwrap_or_default(), + }, + ); + }) + .collect(); + debug!("calculate_fallback_to_f32: fallback_to_f32={:?}", fallback_to_f32); + fallback_to_f32 + } + fn calculate_diverging_fallback( &self, unresolved_variables: &[Ty<'tcx>], @@ -362,6 +416,11 @@ fn root_vid(&self, ty: Ty<'tcx>) -> Option { Some(self.root_var(self.shallow_resolve(ty).ty_vid()?)) } + /// If `ty` is an unresolved float type variable, returns its root vid. + pub(crate) fn root_float_vid(&self, ty: Ty<'tcx>) -> Option { + Some(self.root_float_var(self.shallow_resolve(ty).float_vid()?)) + } + /// Given a set of diverging vids and coercions, walk the HIR to gather a /// set of suggestions which can be applied to preserve fallback to unit. fn try_to_suggest_annotations( diff --git a/compiler/rustc_hir_typeck/src/fn_ctxt/_impl.rs b/compiler/rustc_hir_typeck/src/fn_ctxt/_impl.rs index 6b8dcf1258d4..2cd0a05c723a 100644 --- a/compiler/rustc_hir_typeck/src/fn_ctxt/_impl.rs +++ b/compiler/rustc_hir_typeck/src/fn_ctxt/_impl.rs @@ -13,7 +13,7 @@ use rustc_hir::{self as hir, AmbigArg, ExprKind, GenericArg, HirId, Node, QPath, intravisit}; use rustc_hir_analysis::hir_ty_lowering::errors::GenericsArgsErrExtend; use rustc_hir_analysis::hir_ty_lowering::generics::{ - check_generic_arg_count_for_call, lower_generic_args, + check_generic_arg_count_for_value_path, lower_generic_args, }; use rustc_hir_analysis::hir_ty_lowering::{ ExplicitLateBound, GenericArgCountMismatch, GenericArgCountResult, GenericArgsLowerer, @@ -423,20 +423,6 @@ pub(crate) fn apply_adjustments(&self, expr: &hir::Expr<'_>, adj: Vec, - ) -> ty::InstantiatedPredicates<'tcx> { - let bounds = self.tcx.predicates_of(def_id); - let result = bounds.instantiate(self.tcx, args); - let result = self.normalize(span, result); - debug!("instantiate_bounds(bounds={:?}, args={:?}) = {:?}", bounds, args, result); - result - } - pub(crate) fn normalize(&self, span: Span, value: T) -> T where T: TypeFoldable>, @@ -673,9 +659,16 @@ pub(crate) fn drain_stalled_coroutine_obligations(&self) { // being stalled on a coroutine. self.select_obligations_where_possible(|_| {}); - let ty::TypingMode::Analysis { defining_opaque_types_and_generators } = self.typing_mode() - else { - bug!(); + let defining_opaque_types_and_generators = match self.typing_mode() { + ty::TypingMode::Analysis { defining_opaque_types_and_generators } => { + defining_opaque_types_and_generators + } + ty::TypingMode::Coherence + | ty::TypingMode::Borrowck { .. } + | ty::TypingMode::PostBorrowckAnalysis { .. } + | ty::TypingMode::PostAnalysis => { + bug!() + } }; if defining_opaque_types_and_generators @@ -1098,8 +1091,13 @@ pub(crate) fn instantiate_value_path( // parameter internally, but we don't allow users to specify the // parameter's value explicitly, so we have to do some error- // checking here. - let arg_count = - check_generic_arg_count_for_call(self, def_id, generics, seg, IsMethodCall::No); + let arg_count = check_generic_arg_count_for_value_path( + self, + def_id, + generics, + seg, + IsMethodCall::No, + ); if let ExplicitLateBound::Yes = arg_count.explicit_late_bound { explicit_late_bound = ExplicitLateBound::Yes; @@ -1421,10 +1419,11 @@ pub(crate) fn add_required_obligations_with_code( ) { let param_env = self.param_env; - let bounds = self.instantiate_bounds(span, def_id, args); + let bounds = self.tcx.predicates_of(def_id).instantiate(self.tcx, args); for obligation in traits::predicates_for_generics( |idx, predicate_span| self.cause(span, code(idx, predicate_span)), + |pred| self.normalize(span, pred), param_env, bounds, ) { diff --git a/compiler/rustc_hir_typeck/src/fn_ctxt/checks.rs b/compiler/rustc_hir_typeck/src/fn_ctxt/checks.rs index bb31bcbf70f1..e54b44de366e 100644 --- a/compiler/rustc_hir_typeck/src/fn_ctxt/checks.rs +++ b/compiler/rustc_hir_typeck/src/fn_ctxt/checks.rs @@ -183,6 +183,7 @@ pub(in super::super) fn check_argument_types( // The expressions for each provided argument provided_args: &'tcx [hir::Expr<'tcx>], // Whether the function is variadic, for example when imported from C + // FIXME(splat): maybe change this to FnSigKind? c_variadic: bool, // Whether the arguments have been bundled in a tuple (ex: closures) tuple_arguments: TupleArgumentsFlag, @@ -494,7 +495,21 @@ fn variadic_error<'tcx>( // There are a few types which get autopromoted when passed via varargs // in C but we just error out instead and require explicit casts. + // + // We use implementations of VaArgSafe as the source of truth. On some embedded + // targets, c_double is f32 and c_int/c_uing are i16/u16, and these types implement + // VaArgSafe there. On all other targets, these types do not implement VaArgSafe. + // + // cfg(bootstrap): change the if let to an unwrap. let arg_ty = self.structurally_resolve_type(arg.span, arg_ty); + if let Some(trait_def_id) = tcx.lang_items().va_arg_safe() + && self + .type_implements_trait(trait_def_id, [arg_ty], self.param_env) + .must_apply_modulo_regions() + { + continue; + } + match arg_ty.kind() { ty::Float(ty::FloatTy::F32) => { variadic_error(tcx.sess, arg.span, arg_ty, "c_double"); @@ -718,6 +733,7 @@ fn suggest_ptr_null_mut( pub(in super::super) fn check_expr_lit( &self, lit: &hir::Lit, + lint_id: HirId, expected: Expectation<'tcx>, ) -> Ty<'tcx> { let tcx = self.tcx; @@ -765,7 +781,7 @@ pub(in super::super) fn check_expr_lit( ty::Float(_) => Some(ty), _ => None, }); - opt_ty.unwrap_or_else(|| self.next_float_var()) + opt_ty.unwrap_or_else(|| self.next_float_var(lit.span, Some(lint_id))) } ast::LitKind::Bool(_) => tcx.types.bool, ast::LitKind::CStr(_, _) => Ty::new_imm_ref( @@ -1793,14 +1809,14 @@ fn get_hir_param_info( (Some(_), Some(_)) | (None, None) => unreachable!(), (Some(body), None) => { let params = self.tcx.hir_body(body).params; - let params = - params.get(is_method as usize..params.len() - sig.decl.c_variadic as usize)?; + let params = params + .get(is_method as usize..params.len() - sig.decl.c_variadic() as usize)?; debug_assert_eq!(params.len(), fn_inputs.len()); Some((fn_inputs.zip(params.iter().map(FnParam::Param)).collect(), generics)) } (None, Some(params)) => { - let params = - params.get(is_method as usize..params.len() - sig.decl.c_variadic as usize)?; + let params = params + .get(is_method as usize..params.len() - sig.decl.c_variadic() as usize)?; debug_assert_eq!(params.len(), fn_inputs.len()); Some(( fn_inputs.zip(params.iter().map(|&ident| FnParam::Ident(ident))).collect(), diff --git a/compiler/rustc_hir_typeck/src/fn_ctxt/inspect_obligations.rs b/compiler/rustc_hir_typeck/src/fn_ctxt/inspect_obligations.rs index 1ab7ac4c2e36..652f0498b584 100644 --- a/compiler/rustc_hir_typeck/src/fn_ctxt/inspect_obligations.rs +++ b/compiler/rustc_hir_typeck/src/fn_ctxt/inspect_obligations.rs @@ -1,5 +1,7 @@ //! A utility module to inspect currently ambiguous obligations in the current context. +use rustc_data_structures::unord::UnordSet; +use rustc_hir::def_id::DefId; use rustc_infer::traits::{self, ObligationCause, PredicateObligations}; use rustc_middle::ty::{self, Ty, TypeVisitableExt}; use rustc_span::Span; @@ -96,6 +98,69 @@ pub(crate) fn obligations_for_self_ty_next( }); obligations_for_self_ty } + + /// Only needed for the `From<{float}>` for `f32` type fallback. + #[instrument(skip(self), level = "debug")] + pub(crate) fn from_float_for_f32_root_vids(&self) -> UnordSet { + if self.next_trait_solver() { + self.from_float_for_f32_root_vids_next() + } else { + let Some(from_trait) = self.tcx.lang_items().from_trait() else { + return UnordSet::new(); + }; + self.fulfillment_cx + .borrow_mut() + .pending_obligations() + .into_iter() + .filter_map(|obligation| { + self.predicate_from_float_for_f32_root_vid(from_trait, obligation.predicate) + }) + .collect() + } + } + + fn predicate_from_float_for_f32_root_vid( + &self, + from_trait: DefId, + predicate: ty::Predicate<'tcx>, + ) -> Option { + // The predicates we are looking for look like + // `TraitPredicate(>, polarity:Positive)`. + // They will have no bound variables. + match predicate.kind().no_bound_vars() { + Some(ty::PredicateKind::Clause(ty::ClauseKind::Trait(ty::TraitPredicate { + polarity: ty::PredicatePolarity::Positive, + trait_ref, + }))) if trait_ref.def_id == from_trait + && self.shallow_resolve(trait_ref.self_ty()).kind() + == &ty::Float(ty::FloatTy::F32) => + { + self.root_float_vid(trait_ref.args.type_at(1)) + } + _ => None, + } + } + + fn from_float_for_f32_root_vids_next(&self) -> UnordSet { + let Some(from_trait) = self.tcx.lang_items().from_trait() else { + return UnordSet::new(); + }; + let obligations = self.fulfillment_cx.borrow().pending_obligations(); + debug!(?obligations); + let mut vids = UnordSet::new(); + for obligation in obligations { + let mut visitor = FindFromFloatForF32RootVids { + fcx: self, + from_trait, + vids: &mut vids, + span: obligation.cause.span, + }; + + let goal = obligation.as_goal(); + self.visit_proof_tree(goal, &mut visitor); + } + vids + } } struct NestedObligationsForSelfTy<'a, 'tcx> { @@ -105,7 +170,7 @@ struct NestedObligationsForSelfTy<'a, 'tcx> { obligations_for_self_ty: &'a mut PredicateObligations<'tcx>, } -impl<'a, 'tcx> ProofTreeVisitor<'tcx> for NestedObligationsForSelfTy<'a, 'tcx> { +impl<'tcx> ProofTreeVisitor<'tcx> for NestedObligationsForSelfTy<'_, 'tcx> { fn span(&self) -> Span { self.root_cause.span } @@ -144,3 +209,37 @@ fn visit_goal(&mut self, inspect_goal: &InspectGoal<'_, 'tcx>) { } } } + +struct FindFromFloatForF32RootVids<'a, 'tcx> { + fcx: &'a FnCtxt<'a, 'tcx>, + from_trait: DefId, + vids: &'a mut UnordSet, + span: Span, +} + +impl<'tcx> ProofTreeVisitor<'tcx> for FindFromFloatForF32RootVids<'_, 'tcx> { + fn span(&self) -> Span { + self.span + } + + fn config(&self) -> InspectConfig { + // Avoid hang from exponentially growing proof trees (see `cycle-modulo-ambig-aliases.rs`). + // 3 is more than enough for all occurrences in practice (a.k.a. `Into`). + InspectConfig { max_depth: 3 } + } + + fn visit_goal(&mut self, inspect_goal: &InspectGoal<'_, 'tcx>) { + if let Some(vid) = self + .fcx + .predicate_from_float_for_f32_root_vid(self.from_trait, inspect_goal.goal().predicate) + { + self.vids.insert(vid); + } else if let Some(candidate) = inspect_goal.unique_applicable_candidate() { + let start_len = self.vids.len(); + let _ = candidate.goal().infcx().commit_if_ok(|_| { + candidate.visit_nested_no_probe(self); + if self.vids.len() > start_len { Ok(()) } else { Err(()) } + }); + } + } +} diff --git a/compiler/rustc_hir_typeck/src/fn_ctxt/mod.rs b/compiler/rustc_hir_typeck/src/fn_ctxt/mod.rs index 857713e3295c..419fc8e82be6 100644 --- a/compiler/rustc_hir_typeck/src/fn_ctxt/mod.rs +++ b/compiler/rustc_hir_typeck/src/fn_ctxt/mod.rs @@ -339,9 +339,9 @@ fn select_inherent_assoc_candidates( // Check whether the impl imposes obligations we have to worry about. let impl_bounds = tcx.predicates_of(impl_).instantiate(tcx, impl_args); - let impl_bounds = ocx.normalize(&ObligationCause::dummy(), self.param_env, impl_bounds); let impl_obligations = traits::predicates_for_generics( |_, _| ObligationCause::dummy(), + |pred| ocx.normalize(&ObligationCause::dummy(), self.param_env, pred), self.param_env, impl_bounds, ); diff --git a/compiler/rustc_hir_typeck/src/fn_ctxt/suggestions.rs b/compiler/rustc_hir_typeck/src/fn_ctxt/suggestions.rs index a2f4c57bd442..b5d138f183b9 100644 --- a/compiler/rustc_hir_typeck/src/fn_ctxt/suggestions.rs +++ b/compiler/rustc_hir_typeck/src/fn_ctxt/suggestions.rs @@ -3107,14 +3107,11 @@ pub(crate) fn suggest_deref_or_ref( { let deref_kind = if checked_ty.is_box() { // detect Box::new(..) - // FIXME: use `box_new` diagnostic item instead? if let ExprKind::Call(box_new, [_]) = expr.kind && let ExprKind::Path(qpath) = &box_new.kind && let Res::Def(DefKind::AssocFn, fn_id) = self.typeck_results.borrow().qpath_res(qpath, box_new.hir_id) - && let Some(impl_id) = self.tcx.inherent_impl_of_assoc(fn_id) - && self.tcx.type_of(impl_id).skip_binder().is_box() - && self.tcx.item_name(fn_id) == sym::new + && self.tcx.is_diagnostic_item(sym::box_new, fn_id) { let l_paren = self.tcx.sess.source_map().next_point(box_new.span); let r_paren = self.tcx.sess.source_map().end_point(expr.span); diff --git a/compiler/rustc_hir_typeck/src/intrinsicck.rs b/compiler/rustc_hir_typeck/src/intrinsicck.rs index 7567f8ba3488..c757e8a2387d 100644 --- a/compiler/rustc_hir_typeck/src/intrinsicck.rs +++ b/compiler/rustc_hir_typeck/src/intrinsicck.rs @@ -55,9 +55,6 @@ fn skeleton_string<'tcx>( bug!("{:?} overflow for u128", size) } } - Ok(SizeSkeleton::Generic(size)) => { - format!("generic size {size}") - } Err(LayoutError::TooGeneric(bad)) => { if *bad == ty { "this type does not have a fixed size".to_owned() diff --git a/compiler/rustc_hir_typeck/src/method/confirm.rs b/compiler/rustc_hir_typeck/src/method/confirm.rs index ed75609eaecd..3423f6b42bb2 100644 --- a/compiler/rustc_hir_typeck/src/method/confirm.rs +++ b/compiler/rustc_hir_typeck/src/method/confirm.rs @@ -5,7 +5,7 @@ use rustc_hir::GenericArg; use rustc_hir::def_id::DefId; use rustc_hir_analysis::hir_ty_lowering::generics::{ - check_generic_arg_count_for_call, lower_generic_args, + check_generic_arg_count_for_value_path, lower_generic_args, }; use rustc_hir_analysis::hir_ty_lowering::{ GenericArgsLowerer, HirTyLowerer, IsMethodCall, RegionInferReason, @@ -144,8 +144,7 @@ fn confirm( ); self.unify_receivers(self_ty, method_sig_rcvr, pick); - let (method_sig, method_predicates) = - self.normalize(self.span, (method_sig, method_predicates)); + let method_sig = self.normalize(self.span, method_sig); // Make sure nobody calls `drop()` explicitly. self.check_for_illegal_method_calls(pick); @@ -403,7 +402,7 @@ fn instantiate_method_args( // variables. let generics = self.tcx.generics_of(pick.item.def_id); - let arg_count_correct = check_generic_arg_count_for_call( + let arg_count_correct = check_generic_arg_count_for_value_path( self.fcx, pick.item.def_id, generics, @@ -626,6 +625,7 @@ fn add_obligations( ); self.cause(self.span, code) }, + |pred| self.normalize(self.call_expr.span, pred), self.param_env, method_predicates, ) { diff --git a/compiler/rustc_hir_typeck/src/method/mod.rs b/compiler/rustc_hir_typeck/src/method/mod.rs index 083e29bff04f..97d53a9d5aa5 100644 --- a/compiler/rustc_hir_typeck/src/method/mod.rs +++ b/compiler/rustc_hir_typeck/src/method/mod.rs @@ -1,6 +1,6 @@ //! Method lookup: the secret sauce of Rust. See the [rustc dev guide] for more information. //! -//! [rustc dev guide]: https://rustc-dev-guide.rust-lang.org/method-lookup.html +//! [rustc dev guide]: https://rustc-dev-guide.rust-lang.org/hir-typeck/method-lookup.html mod confirm; mod prelude_edition_lints; @@ -442,17 +442,21 @@ pub(super) fn lookup_method_for_operator( // any late-bound regions appearing in its bounds. let bounds = self.tcx.predicates_of(def_id).instantiate(self.tcx, args); - let InferOk { value: bounds, obligations: o } = - self.at(&obligation.cause, self.param_env).normalize(bounds); - obligations.extend(o); - assert!(!bounds.has_escaping_bound_vars()); - let predicates_cause = obligation.cause.clone(); + let mut normalization_obligations = PredicateObligations::new(); obligations.extend(traits::predicates_for_generics( move |_, _| predicates_cause.clone(), + |pred| { + let InferOk { value: pred, obligations: o } = + self.at(&obligation.cause, self.param_env).normalize(pred); + normalization_obligations.extend(o); + assert!(!pred.has_escaping_bound_vars()); + pred + }, self.param_env, bounds, )); + obligations.extend(normalization_obligations); // Also add an obligation for the method type being well-formed. debug!( diff --git a/compiler/rustc_hir_typeck/src/method/probe.rs b/compiler/rustc_hir_typeck/src/method/probe.rs index c7442373353e..121396da716e 100644 --- a/compiler/rustc_hir_typeck/src/method/probe.rs +++ b/compiler/rustc_hir_typeck/src/method/probe.rs @@ -26,7 +26,7 @@ use rustc_span::edit_distance::{ edit_distance_with_substrings, find_best_match_for_name_with_substrings, }; -use rustc_span::{DUMMY_SP, Ident, Span, Symbol, sym}; +use rustc_span::{DUMMY_SP, Ident, Span, Symbol}; use rustc_trait_selection::error_reporting::infer::need_type_info::TypeAnnotationNeeded; use rustc_trait_selection::infer::InferCtxtExt as _; use rustc_trait_selection::solve::Goal; @@ -1989,7 +1989,6 @@ fn consider_probe( let impl_def_id = probe.item.container_id(self.tcx); let impl_bounds = self.tcx.predicates_of(impl_def_id).instantiate(self.tcx, impl_args); - let impl_bounds = ocx.normalize(cause, self.param_env, impl_bounds); // Convert the bounds into obligations. ocx.register_obligations(traits::predicates_for_generics( |idx, span| { @@ -2001,6 +2000,7 @@ fn consider_probe( ); self.cause(self.span, code) }, + |pred| ocx.normalize(cause, self.param_env, pred), self.param_env, impl_bounds, )); @@ -2377,8 +2377,8 @@ fn collapse_candidates_to_subtrait_pick( continue; } - // This pick is not a supertrait of the `child_pick`. - // Check if it's a subtrait of the `child_pick`, instead. + // This candidate is not a supertrait of the `child_trait`. + // Check if it's a subtrait of the `child_trait`, instead. // If it is, then it must have been a subtrait of every // other pick we've eliminated at this point. It will // take over at this point. @@ -2392,7 +2392,8 @@ fn collapse_candidates_to_subtrait_pick( continue; } - // `child_pick` is not a supertrait of this pick. + // Neither `child_trait` or the current candidate are + // supertraits of each other. // Don't bail here, since we may be comparing two supertraits // of a common subtrait. These two supertraits won't be related // at all, but we will pick them up next round when we find their @@ -2591,38 +2592,25 @@ fn is_relevant_kind_for_mode(&self, kind: ty::AssocKind) -> bool { } /// Determine if the associated item with the given DefId matches - /// the desired name via a doc alias. + /// the desired name via a doc alias or rustc_confusables fn matches_by_doc_alias(&self, def_id: DefId) -> bool { let Some(method) = self.method_name else { return false; }; - let Some(local_def_id) = def_id.as_local() else { - return false; - }; - let hir_id = self.fcx.tcx.local_def_id_to_hir_id(local_def_id); - let attrs = self.fcx.tcx.hir_attrs(hir_id); - if let Some(d) = find_attr!(attrs, Doc(d) => d) + if let Some(d) = find_attr!(self.tcx, def_id, Doc(d) => d) && d.aliases.contains_key(&method.name) { return true; } - for attr in attrs { - if attr.has_name(sym::rustc_confusables) { - let Some(confusables) = attr.meta_item_list() else { - continue; - }; - // #[rustc_confusables("foo", "bar"))] - for n in confusables { - if let Some(lit) = n.lit() - && method.name == lit.symbol - { - return true; - } - } - } + if let Some(confusables) = + find_attr!(self.tcx, def_id, RustcConfusables{ confusables } => confusables) + && confusables.contains(&method.name) + { + return true; } + false } diff --git a/compiler/rustc_hir_typeck/src/method/suggest.rs b/compiler/rustc_hir_typeck/src/method/suggest.rs index dc5e782bc34f..c9329fef4ed8 100644 --- a/compiler/rustc_hir_typeck/src/method/suggest.rs +++ b/compiler/rustc_hir_typeck/src/method/suggest.rs @@ -1898,7 +1898,7 @@ fn handle_unsatisfied_predicates( Some( Node::Item(hir::Item { kind: - hir::ItemKind::Trait(_, _, _, ident, ..) + hir::ItemKind::Trait(_, _, _, _, ident, ..) | hir::ItemKind::TraitAlias(_, ident, ..), .. }) @@ -2276,8 +2276,8 @@ pub(crate) fn confusable_method_name( for inherent_method in self.tcx.associated_items(inherent_impl_did).in_definition_order() { - if let Some(candidates) = find_attr!(self.tcx, inherent_method.def_id, RustcConfusables{symbols, ..} => symbols) - && candidates.contains(&item_name.name) + if let Some(confusables) = find_attr!(self.tcx, inherent_method.def_id, RustcConfusables{confusables} => confusables) + && confusables.contains(&item_name.name) && inherent_method.is_fn() { let args = @@ -4366,7 +4366,7 @@ fn suggest_traits_to_import( _ => false, }; - if !fn_sig.decl.implicit_self.has_implicit_self() + if !fn_sig.decl.implicit_self().has_implicit_self() && self_first_arg { if let Some(ty) = fn_sig.decl.inputs.get(0) { @@ -4545,7 +4545,7 @@ enum Introducer { return; } Node::Item(hir::Item { - kind: hir::ItemKind::Trait(_, _, _, ident, _, bounds, _), + kind: hir::ItemKind::Trait(_, _, _, _, ident, _, bounds, _), .. }) => { let (sp, sep, article) = if bounds.is_empty() { diff --git a/compiler/rustc_hir_typeck/src/op.rs b/compiler/rustc_hir_typeck/src/op.rs index 4eac1fc004cc..8b08c7b68b78 100644 --- a/compiler/rustc_hir_typeck/src/op.rs +++ b/compiler/rustc_hir_typeck/src/op.rs @@ -294,24 +294,26 @@ fn overloaded_binop_ret_ty( self.apply_adjustments(lhs_expr, vec![autoref]); } - if let ty::Ref(_, _, mutbl) = method.sig.inputs()[1].kind() { - // Allow two-phase borrows for binops in initial deployment - // since they desugar to methods - let mutbl = AutoBorrowMutability::new(*mutbl, AllowTwoPhase::Yes); - let autoref = Adjustment { - kind: Adjust::Borrow(AutoBorrow::Ref(mutbl)), - target: method.sig.inputs()[1], - }; - // HACK(eddyb) Bypass checks due to reborrows being in - // some cases applied on the RHS, on top of which we need - // to autoref, which is not allowed by apply_adjustments. - // self.apply_adjustments(rhs_expr, vec![autoref]); - self.typeck_results - .borrow_mut() - .adjustments_mut() - .entry(rhs_expr.hir_id) - .or_default() - .push(autoref); + if by_ref_binop { + if let ty::Ref(_, _, mutbl) = method.sig.inputs()[1].kind() { + // Allow two-phase borrows for binops in initial deployment + // since they desugar to methods + let mutbl = AutoBorrowMutability::new(*mutbl, AllowTwoPhase::Yes); + let autoref = Adjustment { + kind: Adjust::Borrow(AutoBorrow::Ref(mutbl)), + target: method.sig.inputs()[1], + }; + // HACK(eddyb) Bypass checks due to reborrows being in + // some cases applied on the RHS, on top of which we need + // to autoref, which is not allowed by apply_adjustments. + // self.apply_adjustments(rhs_expr, vec![autoref]); + self.typeck_results + .borrow_mut() + .adjustments_mut() + .entry(rhs_expr.hir_id) + .or_default() + .push(autoref); + } } } diff --git a/compiler/rustc_hir_typeck/src/opaque_types.rs b/compiler/rustc_hir_typeck/src/opaque_types.rs index 18c1bf39a7c1..b73bfabe92e6 100644 --- a/compiler/rustc_hir_typeck/src/opaque_types.rs +++ b/compiler/rustc_hir_typeck/src/opaque_types.rs @@ -1,8 +1,9 @@ use rustc_hir::def::DefKind; use rustc_infer::traits::ObligationCause; +use rustc_middle::bug; use rustc_middle::ty::{ self, DefiningScopeKind, DefinitionSiteHiddenType, OpaqueTypeKey, ProvisionalHiddenType, - TypeVisitableExt, TypingMode, + TypeVisitableExt, }; use rustc_trait_selection::error_reporting::infer::need_type_info::TypeAnnotationNeeded; use rustc_trait_selection::opaque_types::{ @@ -97,9 +98,16 @@ fn compute_definition_site_hidden_types( debug!(?opaque_types); let tcx = self.tcx; - let TypingMode::Analysis { defining_opaque_types_and_generators } = self.typing_mode() - else { - unreachable!(); + let defining_opaque_types_and_generators = match self.typing_mode() { + ty::TypingMode::Analysis { defining_opaque_types_and_generators } => { + defining_opaque_types_and_generators + } + ty::TypingMode::Coherence + | ty::TypingMode::Borrowck { .. } + | ty::TypingMode::PostBorrowckAnalysis { .. } + | ty::TypingMode::PostAnalysis => { + bug!() + } }; for def_id in defining_opaque_types_and_generators { diff --git a/compiler/rustc_hir_typeck/src/pat.rs b/compiler/rustc_hir_typeck/src/pat.rs index 26f7d1ccffc9..198c177e6d44 100644 --- a/compiler/rustc_hir_typeck/src/pat.rs +++ b/compiler/rustc_hir_typeck/src/pat.rs @@ -917,7 +917,7 @@ fn should_peel_smart_pointer(&self, peel_kind: PeelKind, expected: Ty<'tcx>) -> fn check_pat_expr_unadjusted(&self, lt: &'tcx hir::PatExpr<'tcx>) -> Ty<'tcx> { let ty = match <.kind { rustc_hir::PatExprKind::Lit { lit, negated } => { - let ty = self.check_expr_lit(lit, Expectation::NoExpectation); + let ty = self.check_expr_lit(lit, lt.hir_id, Expectation::NoExpectation); if *negated { self.register_bound( ty, diff --git a/compiler/rustc_hir_typeck/src/upvar.rs b/compiler/rustc_hir_typeck/src/upvar.rs index df02974d2fb2..c35492a8042f 100644 --- a/compiler/rustc_hir_typeck/src/upvar.rs +++ b/compiler/rustc_hir_typeck/src/upvar.rs @@ -438,13 +438,7 @@ fn analyze_closure( let coroutine_captures_by_ref_ty = Ty::new_fn_ptr( self.tcx, ty::Binder::bind_with_vars( - self.tcx.mk_fn_sig( - [], - tupled_upvars_ty_for_borrow, - false, - hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, - ), + self.tcx.mk_fn_sig_safe_rust_abi([], tupled_upvars_ty_for_borrow), self.tcx.mk_bound_variable_kinds(&[ty::BoundVariableKind::Region( ty::BoundRegionKind::ClosureEnv, )]), diff --git a/compiler/rustc_index/src/lib.rs b/compiler/rustc_index/src/lib.rs index 1b8c8e3bd2c8..c84b06769e08 100644 --- a/compiler/rustc_index/src/lib.rs +++ b/compiler/rustc_index/src/lib.rs @@ -4,11 +4,6 @@ #![cfg_attr(feature = "nightly", feature(extend_one, step_trait))] // tidy-alphabetical-end -// FIXME(#125687): new_range_api recently stabilized -// Remove this when it hits stable. cfg(bootstrap) -#![allow(stable_features)] -#![cfg_attr(feature = "nightly", feature(new_range_api))] - pub mod bit_set; #[cfg(feature = "nightly")] pub mod interval; diff --git a/compiler/rustc_infer/Cargo.toml b/compiler/rustc_infer/Cargo.toml index c4fbe89315db..1896ce10faf2 100644 --- a/compiler/rustc_infer/Cargo.toml +++ b/compiler/rustc_infer/Cargo.toml @@ -17,6 +17,6 @@ rustc_middle = { path = "../rustc_middle" } rustc_span = { path = "../rustc_span" } rustc_type_ir = { path = "../rustc_type_ir" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs b/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs index 87d389a5dea5..c88938158675 100644 --- a/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs +++ b/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs @@ -13,6 +13,7 @@ self, BoundVar, GenericArg, InferConst, List, Ty, TyCtxt, TypeFlags, TypeFoldable, TypeFolder, TypeSuperFoldable, TypeVisitableExt, }; +use rustc_type_ir::TypingModeEqWrapper; use smallvec::SmallVec; use tracing::debug; @@ -72,7 +73,7 @@ pub fn canonicalize_query( query_state, ) .unchecked_map(|(param_env, value)| param_env.and(value)); - CanonicalQueryInput { canonical, typing_mode: self.typing_mode() } + CanonicalQueryInput { canonical, typing_mode: TypingModeEqWrapper(self.typing_mode()) } } /// Canonicalizes a query *response* `V`. When we canonicalize a diff --git a/compiler/rustc_infer/src/infer/canonical/mod.rs b/compiler/rustc_infer/src/infer/canonical/mod.rs index c6826d774216..55c78036c6d1 100644 --- a/compiler/rustc_infer/src/infer/canonical/mod.rs +++ b/compiler/rustc_infer/src/infer/canonical/mod.rs @@ -107,7 +107,10 @@ pub fn instantiate_canonical_var( CanonicalVarKind::Int => self.next_int_var().into(), - CanonicalVarKind::Float => self.next_float_var().into(), + CanonicalVarKind::Float => { + // There is no HirId available to pass as a lint_id. + self.next_float_var(span, None).into() + } CanonicalVarKind::PlaceholderTy(ty::PlaceholderType { universe, bound, .. }) => { let universe_mapped = universe_map(universe); diff --git a/compiler/rustc_infer/src/infer/canonical/query_response.rs b/compiler/rustc_infer/src/infer/canonical/query_response.rs index 846123b8aad9..5203b4ee5d99 100644 --- a/compiler/rustc_infer/src/infer/canonical/query_response.rs +++ b/compiler/rustc_infer/src/infer/canonical/query_response.rs @@ -22,7 +22,7 @@ Canonical, CanonicalQueryResponse, CanonicalVarValues, Certainty, OriginalQueryValues, QueryRegionConstraints, QueryResponse, }; -use crate::infer::region_constraints::RegionConstraintData; +use crate::infer::region_constraints::{ConstraintKind, RegionConstraintData}; use crate::infer::{ DefineOpaqueTypes, InferCtxt, InferOk, InferResult, OpaqueTypeStorageEntries, SubregionOrigin, TypeOutlivesConstraint, @@ -188,9 +188,16 @@ pub fn instantiate_query_response_and_region_obligations( let InferOk { value: result_args, obligations } = self.query_response_instantiation(cause, param_env, original_values, query_response)?; - for (predicate, _category) in &query_response.value.region_constraints.outlives { - let predicate = instantiate_value(self.tcx, &result_args, *predicate); - self.register_outlives_constraint(predicate, cause); + for (constraint, _category) in &query_response.value.region_constraints.constraints { + let constraint = instantiate_value(self.tcx, &result_args, *constraint); + match constraint { + ty::RegionConstraint::Outlives(predicate) => { + self.register_outlives_constraint(predicate, cause); + } + ty::RegionConstraint::Eq(predicate) => { + self.register_region_eq_constraint(predicate, cause); + } + } } for assumption in &query_response.value.region_constraints.assumptions { @@ -277,14 +284,11 @@ pub fn instantiate_nll_query_response_and_region_obligations( } (GenericArgKind::Lifetime(v_o), GenericArgKind::Lifetime(v_r)) => { - // To make `v_o = v_r`, we emit `v_o: v_r` and `v_r: v_o`. if v_o != v_r { - output_query_region_constraints - .outlives - .push((ty::OutlivesPredicate(v_o.into(), v_r), constraint_category)); - output_query_region_constraints - .outlives - .push((ty::OutlivesPredicate(v_r.into(), v_o), constraint_category)); + output_query_region_constraints.constraints.push(( + ty::RegionEqPredicate(v_o.into(), v_r).into(), + constraint_category, + )); } } @@ -311,13 +315,12 @@ pub fn instantiate_nll_query_response_and_region_obligations( } // ...also include the other query region constraints from the query. - output_query_region_constraints.outlives.extend( - query_response.value.region_constraints.outlives.iter().filter_map(|&r_c| { + output_query_region_constraints.constraints.extend( + query_response.value.region_constraints.constraints.iter().filter_map(|&r_c| { let r_c = instantiate_value(self.tcx, &result_args, r_c); - // Screen out `'a: 'a` cases. - let ty::OutlivesPredicate(k1, r2) = r_c.0; - if k1 != r2.into() { Some(r_c) } else { None } + // Screen out `'a: 'a` or `'a == 'a` cases. + if r_c.0.is_trivial() { None } else { Some(r_c) } }), ); @@ -611,20 +614,30 @@ pub fn make_query_region_constraints<'tcx>( debug!(?constraints); - let outlives: Vec<_> = constraints + let constraints: Vec<_> = constraints .iter() - .map(|(c, origin)| { - // Swap regions because we are going from sub (<=) to outlives (>=). - let constraint = ty::OutlivesPredicate(c.sup.into(), c.sub); - (constraint, origin.to_constraint_category()) + .map(|(c, origin)| match c.kind { + ConstraintKind::VarSubVar + | ConstraintKind::RegSubVar + | ConstraintKind::VarSubReg + | ConstraintKind::RegSubReg => { + // Swap regions because we are going from sub (<=) to outlives (>=). + let constraint = ty::OutlivesPredicate(c.sup.into(), c.sub).into(); + (constraint, origin.to_constraint_category()) + } + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + let constraint = ty::RegionEqPredicate(c.sup, c.sub).into(); + (constraint, origin.to_constraint_category()) + } }) .chain(outlives_obligations.into_iter().map(|obl| { ( - ty::OutlivesPredicate(obl.sup_type.into(), obl.sub_region), + ty::OutlivesPredicate(obl.sup_type.into(), obl.sub_region).into(), obl.origin.to_constraint_category(), ) })) .collect(); - QueryRegionConstraints { outlives, assumptions } + QueryRegionConstraints { constraints, assumptions } } diff --git a/compiler/rustc_infer/src/infer/lexical_region_resolve/indexed_edges.rs b/compiler/rustc_infer/src/infer/lexical_region_resolve/indexed_edges.rs index ffc6e54f3cb0..382998e55d2e 100644 --- a/compiler/rustc_infer/src/infer/lexical_region_resolve/indexed_edges.rs +++ b/compiler/rustc_infer/src/infer/lexical_region_resolve/indexed_edges.rs @@ -13,13 +13,13 @@ pub(super) enum EdgeDirection { /// Type alias for the pairs stored in [`RegionConstraintData::constraints`], /// which we are indexing. -type ConstraintPair<'tcx> = (Constraint<'tcx>, SubregionOrigin<'tcx>); +type ConstraintPair<'data, 'tcx> = (Constraint<'tcx>, &'data SubregionOrigin<'tcx>); /// An index from region variables to their corresponding constraint edges, /// used on some error paths. pub(super) struct IndexedConstraintEdges<'data, 'tcx> { - out_edges: IndexVec>>, - in_edges: IndexVec>>, + out_edges: IndexVec>>, + in_edges: IndexVec>>, } impl<'data, 'tcx> IndexedConstraintEdges<'data, 'tcx> { @@ -27,25 +27,46 @@ pub(super) fn build_index(num_vars: usize, data: &'data RegionConstraintData<'tc let mut out_edges = IndexVec::from_fn_n(|_| vec![], num_vars); let mut in_edges = IndexVec::from_fn_n(|_| vec![], num_vars); - for pair @ (c, _) in &data.constraints { + for pair @ (c, _) in data + .constraints + .iter() + .flat_map(|(c, origin)| c.iter_outlives().map(move |c| (c, origin))) + { // Only push a var out-edge for `VarSub...` constraints. match c.kind { ConstraintKind::VarSubVar | ConstraintKind::VarSubReg => { - out_edges[c.sub.as_var()].push(pair) + out_edges[c.sub.as_var()].push(pair); } + ConstraintKind::RegSubVar | ConstraintKind::RegSubReg => {} + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!(); + } } } + // FIXME: We should merge this loop with the above one eventually. // Index in-edges in reverse order, to match what current tests expect. // (It's unclear whether this is important or not.) - for pair @ (c, _) in data.constraints.iter().rev() { + + for pair @ (c, _) in data + .constraints + .iter() + .rev() + .flat_map(|(c, origin)| c.iter_outlives().map(move |c| (c, origin))) + { // Only push a var in-edge for `...SubVar` constraints. match c.kind { ConstraintKind::VarSubVar | ConstraintKind::RegSubVar => { - in_edges[c.sup.as_var()].push(pair) + in_edges[c.sup.as_var()].push(pair); } + ConstraintKind::VarSubReg | ConstraintKind::RegSubReg => {} + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!(); + } } } @@ -58,7 +79,7 @@ pub(super) fn adjacent_edges( &self, region_vid: RegionVid, dir: EdgeDirection, - ) -> &[&'data ConstraintPair<'tcx>] { + ) -> &[ConstraintPair<'data, 'tcx>] { let edges = match dir { EdgeDirection::Out => &self.out_edges, EdgeDirection::In => &self.in_edges, diff --git a/compiler/rustc_infer/src/infer/lexical_region_resolve/mod.rs b/compiler/rustc_infer/src/infer/lexical_region_resolve/mod.rs index e99dcd1ef15c..9e5c31eecbe7 100644 --- a/compiler/rustc_infer/src/infer/lexical_region_resolve/mod.rs +++ b/compiler/rustc_infer/src/infer/lexical_region_resolve/mod.rs @@ -34,6 +34,18 @@ pub(crate) fn resolve<'tcx>( var_infos: VarInfos<'tcx>, data: RegionConstraintData<'tcx>, ) -> (LexicalRegionResolutions<'tcx>, Vec>) { + assert!( + data.constraints.iter().all(|(c, _)| match c.kind { + ConstraintKind::VarSubVar + | ConstraintKind::RegSubVar + | ConstraintKind::VarSubReg + | ConstraintKind::RegSubReg => true, + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => false, + }), + "Every constraint should be decomposed into outlives here" + ); + let mut errors = vec![]; let mut resolver = LexicalResolver { region_rels, var_infos, data }; let values = resolver.infer_variable_values(&mut errors); @@ -279,6 +291,10 @@ fn expansion(&self, var_values: &mut LexicalRegionResolutions<'tcx>) { // is done, in `collect_errors`. continue; } + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!() + } } } @@ -575,6 +591,10 @@ fn collect_errors( *sub_data = VarValue::ErrorValue; } } + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!() + } } } @@ -852,12 +872,12 @@ fn process_edges<'tcx>( } ConstraintKind::RegSubVar => { - let origin = origin.clone(); + let origin = (*origin).clone(); state.result.push(RegionAndOrigin { region: c.sub, origin }); } ConstraintKind::VarSubReg => { - let origin = origin.clone(); + let origin = (*origin).clone(); state.result.push(RegionAndOrigin { region: c.sup, origin }); } @@ -865,6 +885,10 @@ fn process_edges<'tcx>( "cannot reach reg-sub-reg edge in region inference \ post-processing" ), + + ConstraintKind::VarEqVar + | ConstraintKind::VarEqReg + | ConstraintKind::RegEqReg => unreachable!(), } } } diff --git a/compiler/rustc_infer/src/infer/mod.rs b/compiler/rustc_infer/src/infer/mod.rs index 583eb1a6dbc4..26c03066c7e4 100644 --- a/compiler/rustc_infer/src/infer/mod.rs +++ b/compiler/rustc_infer/src/infer/mod.rs @@ -16,8 +16,9 @@ use rustc_data_structures::undo_log::{Rollback, UndoLogs}; use rustc_data_structures::unify as ut; use rustc_errors::{DiagCtxtHandle, ErrorGuaranteed}; -use rustc_hir as hir; use rustc_hir::def_id::{DefId, LocalDefId}; +use rustc_hir::{self as hir, HirId}; +use rustc_index::IndexVec; use rustc_macros::extension; pub use rustc_macros::{TypeFoldable, TypeVisitable}; use rustc_middle::bug; @@ -38,6 +39,7 @@ use type_variable::TypeVariableOrigin; use crate::infer::snapshot::undo_log::UndoLog; +use crate::infer::type_variable::FloatVariableOrigin; use crate::infer::unify_key::{ConstVariableOrigin, ConstVariableValue, ConstVidKey}; use crate::traits::{ self, ObligationCause, ObligationInspector, PredicateObligation, PredicateObligations, @@ -108,6 +110,11 @@ pub struct InferCtxtInner<'tcx> { /// Map from floating variable to the kind of float it represents. float_unification_storage: ut::UnificationTableStorage, + /// Map from floating variable to the origin span it came from, and the HirId that should be + /// used to lint at that location. This is only used for the FCW for the fallback to `f32`, + /// so can be removed once the `f32` fallback is removed. + float_origin_origin_storage: IndexVec, + /// Tracks the set of region variables and the constraints between them. /// /// This is initially `Some(_)` but when @@ -161,6 +168,7 @@ fn new() -> InferCtxtInner<'tcx> { const_unification_storage: Default::default(), int_unification_storage: Default::default(), float_unification_storage: Default::default(), + float_origin_origin_storage: Default::default(), region_constraint_storage: Some(Default::default()), region_obligations: Default::default(), region_assumptions: Default::default(), @@ -564,16 +572,16 @@ pub fn build_with_canonical( where T: TypeFoldable>, { - let infcx = self.build(input.typing_mode); + let infcx = self.build(input.typing_mode.0); let (value, args) = infcx.instantiate_canonical(span, &input.canonical); (infcx, value, args) } pub fn build_with_typing_env( mut self, - TypingEnv { typing_mode, param_env }: TypingEnv<'tcx>, + typing_env: TypingEnv<'tcx>, ) -> (InferCtxt<'tcx>, ty::ParamEnv<'tcx>) { - (self.build(typing_mode), param_env) + (self.build(typing_env.typing_mode()), typing_env.param_env) } pub fn build(&mut self, typing_mode: TypingMode<'tcx>) -> InferCtxt<'tcx> { @@ -644,6 +652,13 @@ pub fn type_var_origin(&self, vid: TyVid) -> TypeVariableOrigin { self.inner.borrow_mut().type_variables().var_origin(vid) } + /// Returns the origin of the float type variable identified by `vid`. + /// + /// No attempt is made to resolve `vid` to its root variable. + pub fn float_var_origin(&self, vid: FloatVid) -> FloatVariableOrigin { + self.inner.borrow_mut().float_origin_origin_storage[vid] + } + /// Returns the origin of the const variable identified by `vid` // FIXME: We should store origins separately from the unification table // so this doesn't need to be optional. @@ -687,6 +702,16 @@ pub fn sub_regions( self.inner.borrow_mut().unwrap_region_constraints().make_subregion(origin, a, b); } + #[instrument(skip(self), level = "debug")] + pub fn equate_regions( + &self, + origin: SubregionOrigin<'tcx>, + a: ty::Region<'tcx>, + b: ty::Region<'tcx>, + ) { + self.inner.borrow_mut().unwrap_region_constraints().make_eqregion(origin, a, b); + } + /// Processes a `Coerce` predicate from the fulfillment context. /// This is NOT the preferred way to handle coercion, which is to /// invoke `FnCtxt::coerce` or a similar method (see `coercion.rs`). @@ -821,9 +846,12 @@ pub fn next_int_var(&self) -> Ty<'tcx> { Ty::new_int_var(self.tcx, next_int_var_id) } - pub fn next_float_var(&self) -> Ty<'tcx> { - let next_float_var_id = - self.inner.borrow_mut().float_unification_table().new_key(ty::FloatVarValue::Unknown); + pub fn next_float_var(&self, span: Span, lint_id: Option) -> Ty<'tcx> { + let mut inner = self.inner.borrow_mut(); + let next_float_var_id = inner.float_unification_table().new_key(ty::FloatVarValue::Unknown); + let origin = FloatVariableOrigin { span, lint_id }; + let span_index = inner.float_origin_origin_storage.push(origin); + debug_assert_eq!(next_float_var_id, span_index); Ty::new_float_var(self.tcx, next_float_var_id) } @@ -1166,6 +1194,10 @@ pub fn sub_unification_table_root_var(&self, var: ty::TyVid) -> ty::TyVid { self.inner.borrow_mut().type_variables().sub_unification_table_root_var(var) } + pub fn root_float_var(&self, var: ty::FloatVid) -> ty::FloatVid { + self.inner.borrow_mut().float_unification_table().find(var) + } + pub fn root_const_var(&self, var: ty::ConstVid) -> ty::ConstVid { self.inner.borrow_mut().const_unification_table().find(var).vid } @@ -1376,7 +1408,7 @@ pub fn typing_env(&self, param_env: ty::ParamEnv<'tcx>) -> ty::TypingEnv<'tcx> { | ty::TypingMode::PostBorrowckAnalysis { .. } | ty::TypingMode::PostAnalysis) => mode, }; - ty::TypingEnv { typing_mode, param_env } + ty::TypingEnv::new(param_env, typing_mode) } /// Similar to [`Self::canonicalize_query`], except that it returns diff --git a/compiler/rustc_infer/src/infer/opaque_types/mod.rs b/compiler/rustc_infer/src/infer/opaque_types/mod.rs index 29cbbe5a1c9e..0c447f7c6997 100644 --- a/compiler/rustc_infer/src/infer/opaque_types/mod.rs +++ b/compiler/rustc_infer/src/infer/opaque_types/mod.rs @@ -89,7 +89,7 @@ pub fn handle_opaque_type( if def_id.is_local() => { let def_id = def_id.expect_local(); - if let ty::TypingMode::Coherence = self.typing_mode() { + if self.typing_mode().is_coherence() { // See comment on `insert_hidden_type` for why this is sufficient in coherence return Some(self.register_hidden_type( OpaqueTypeKey { def_id, args }, diff --git a/compiler/rustc_infer/src/infer/outlives/mod.rs b/compiler/rustc_infer/src/infer/outlives/mod.rs index c992cda8aaed..2538df46575e 100644 --- a/compiler/rustc_infer/src/infer/outlives/mod.rs +++ b/compiler/rustc_infer/src/infer/outlives/mod.rs @@ -1,5 +1,7 @@ //! Various code related to computing outlives relations. +use std::iter; + use rustc_data_structures::undo_log::UndoLogs; use rustc_middle::traits::query::{NoSolution, OutlivesBound}; use rustc_middle::ty; @@ -67,6 +69,15 @@ pub fn resolve_regions_with_normalize( inner.region_constraint_storage.take().expect("regions already resolved") }; + storage.data.constraints = storage + .data + .constraints + .iter() + .flat_map(|(constraint, origin)| { + constraint.iter_outlives().zip(iter::repeat_with(|| origin.clone())) + }) + .collect(); + // Filter out any region-region outlives assumptions that are implied by // coroutine well-formedness. if self.tcx.sess.opts.unstable_opts.higher_ranked_assumptions { @@ -74,7 +85,14 @@ pub fn resolve_regions_with_normalize( ConstraintKind::RegSubReg => !outlives_env .higher_ranked_assumptions() .contains(&ty::OutlivesPredicate(c.sup.into(), c.sub)), - _ => true, + + ConstraintKind::VarSubVar + | ConstraintKind::RegSubVar + | ConstraintKind::VarSubReg => true, + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!(); + } }); } diff --git a/compiler/rustc_infer/src/infer/outlives/obligations.rs b/compiler/rustc_infer/src/infer/outlives/obligations.rs index b7cea848098a..28e1b0718245 100644 --- a/compiler/rustc_infer/src/infer/outlives/obligations.rs +++ b/compiler/rustc_infer/src/infer/outlives/obligations.rs @@ -98,6 +98,17 @@ pub fn register_outlives_constraint( } } + pub fn register_region_eq_constraint( + &self, + ty::RegionEqPredicate(r_a, r_b): ty::RegionEqPredicate<'tcx>, + cause: &ObligationCause<'tcx>, + ) { + let origin = SubregionOrigin::from_obligation_cause(cause, || { + SubregionOrigin::RelateRegionParamBound(cause.span, None) + }); + self.equate_regions(origin, r_a, r_b); + } + pub fn register_region_outlives_constraint( &self, ty::OutlivesPredicate(r_a, r_b): ty::RegionOutlivesPredicate<'tcx>, diff --git a/compiler/rustc_infer/src/infer/region_constraints/leak_check.rs b/compiler/rustc_infer/src/infer/region_constraints/leak_check.rs index 4ef1ea5a1c4d..81a3ca6755d2 100644 --- a/compiler/rustc_infer/src/infer/region_constraints/leak_check.rs +++ b/compiler/rustc_infer/src/infer/region_constraints/leak_check.rs @@ -392,8 +392,10 @@ fn iterate_region_constraints( { match undo_entry { &AddConstraint(i) => { - let c = region_constraints.data().constraints[i].0; - each_edge(c.sub, c.sup); + region_constraints.data().constraints[i] + .0 + .iter_outlives() + .for_each(|c| each_edge(c.sub, c.sup)); } &AddVerify(i) => span_bug!( region_constraints.data().verifys[i].origin.span(), @@ -403,7 +405,12 @@ fn iterate_region_constraints( } } } else { - region_constraints.data().constraints.iter().for_each(|(c, _)| each_edge(c.sub, c.sup)) + region_constraints + .data() + .constraints + .iter() + .flat_map(|(c, _)| c.iter_outlives()) + .for_each(|c| each_edge(c.sub, c.sup)) } } diff --git a/compiler/rustc_infer/src/infer/region_constraints/mod.rs b/compiler/rustc_infer/src/infer/region_constraints/mod.rs index ae7481b5d1e7..38b87eb7a986 100644 --- a/compiler/rustc_infer/src/infer/region_constraints/mod.rs +++ b/compiler/rustc_infer/src/infer/region_constraints/mod.rs @@ -1,7 +1,7 @@ //! See `README.md`. use std::ops::Range; -use std::{cmp, fmt, mem}; +use std::{cmp, fmt, iter, mem}; use rustc_data_structures::fx::FxHashMap; use rustc_data_structures::undo_log::UndoLogs; @@ -96,6 +96,19 @@ pub enum ConstraintKind { /// directly affect inference, but instead is checked after /// inference is complete. RegSubReg, + + /// A region variable is equal to another. + VarEqVar, + + /// A region variable is equal to a concrete region. This does not + /// directly affect inference, but instead is checked after + /// inference is complete. + VarEqReg, + + /// An equality constraint where neither side is a variable. This does not + /// directly affect inference, but instead is checked after + /// inference is complete. + RegEqReg, } /// Represents a constraint that influences the inference process. @@ -112,6 +125,30 @@ impl Constraint<'_> { pub fn involves_placeholders(&self) -> bool { self.sub.is_placeholder() || self.sup.is_placeholder() } + + pub fn iter_outlives(self) -> impl Iterator { + let Constraint { kind, sub, sup } = self; + + match kind { + ConstraintKind::VarSubVar + | ConstraintKind::RegSubVar + | ConstraintKind::VarSubReg + | ConstraintKind::RegSubReg => iter::once(self).chain(None), + + ConstraintKind::VarEqVar => { + iter::once(Constraint { kind: ConstraintKind::VarSubVar, sub, sup }) + .chain(Some(Constraint { kind: ConstraintKind::VarSubVar, sub: sup, sup: sub })) + } + ConstraintKind::VarEqReg => { + iter::once(Constraint { kind: ConstraintKind::VarSubReg, sub, sup }) + .chain(Some(Constraint { kind: ConstraintKind::RegSubVar, sub: sup, sup: sub })) + } + ConstraintKind::RegEqReg => { + iter::once(Constraint { kind: ConstraintKind::RegSubReg, sub, sup }) + .chain(Some(Constraint { kind: ConstraintKind::RegSubReg, sub: sup, sup: sub })) + } + } + } } #[derive(Debug, Clone)] @@ -422,39 +459,57 @@ pub(super) fn make_eqregion( b: Region<'tcx>, ) { if a != b { - // Eventually, it would be nice to add direct support for - // equating regions. - self.make_subregion(origin.clone(), a, b); - self.make_subregion(origin, b, a); - - match (a.kind(), b.kind()) { - (ty::ReVar(a), ty::ReVar(b)) => { - debug!("make_eqregion: unifying {:?} with {:?}", a, b); - if self.unification_table_mut().unify_var_var(a, b).is_ok() { + // FIXME: We could only emit constraints if `unify_var_{var, value}` fails when + // equating region vars. + match (a.kind(), b.kind(), a, b) { + (ReBound(..), _, _, _) | (_, ReBound(..), _, _) => { + span_bug!(origin.span(), "cannot relate bound region: {:?} == {:?}", a, b); + } + (ReVar(a_vid), ReVar(b_vid), _, _) => { + self.add_constraint( + Constraint { kind: ConstraintKind::VarEqVar, sub: a, sup: b }, + origin, + ); + debug!("make_eqregion: unifying {:?} with {:?}", a_vid, b_vid); + if self.unification_table_mut().unify_var_var(a_vid, b_vid).is_ok() { self.storage.any_unifications = true; } } - (ty::ReVar(vid), _) => { - debug!("make_eqregion: unifying {:?} with {:?}", vid, b); + (ReVar(vid), _, var, reg) | (_, ReVar(vid), reg, var) => { + if reg.is_static() { + // all regions are subregions of static, so don't go bidirectional here + self.add_constraint( + Constraint { kind: ConstraintKind::RegSubVar, sub: reg, sup: var }, + origin, + ); + } else { + self.add_constraint( + Constraint { kind: ConstraintKind::VarEqReg, sub: var, sup: reg }, + origin, + ); + } + debug!("make_eqregion: unifying {:?} with {:?}", vid, reg); if self .unification_table_mut() - .unify_var_value(vid, RegionVariableValue::Known { value: b }) + .unify_var_value(vid, RegionVariableValue::Known { value: reg }) .is_ok() { self.storage.any_unifications = true; }; } - (_, ty::ReVar(vid)) => { - debug!("make_eqregion: unifying {:?} with {:?}", a, vid); - if self - .unification_table_mut() - .unify_var_value(vid, RegionVariableValue::Known { value: a }) - .is_ok() - { - self.storage.any_unifications = true; - }; + (ReStatic, _, st, reg) | (_, ReStatic, reg, st) => { + // all regions are subregions of static, so don't go bidirectional here + self.add_constraint( + Constraint { kind: ConstraintKind::RegSubReg, sub: st, sup: reg }, + origin, + ); + } + _ => { + self.add_constraint( + Constraint { kind: ConstraintKind::RegEqReg, sub: a, sup: b }, + origin, + ); } - (_, _) => {} } } } diff --git a/compiler/rustc_infer/src/infer/relate/generalize.rs b/compiler/rustc_infer/src/infer/relate/generalize.rs index ffc04eabcec1..0229af53f2a6 100644 --- a/compiler/rustc_infer/src/infer/relate/generalize.rs +++ b/compiler/rustc_infer/src/infer/relate/generalize.rs @@ -7,7 +7,7 @@ use rustc_middle::ty::error::TypeError; use rustc_middle::ty::{ self, AliasRelationDirection, InferConst, Term, Ty, TyCtxt, TypeSuperVisitable, TypeVisitable, - TypeVisitableExt, TypeVisitor, TypingMode, + TypeVisitableExt, TypeVisitor, }; use rustc_span::Span; use tracing::{debug, instrument, warn}; @@ -603,7 +603,7 @@ fn tys(&mut self, t: Ty<'tcx>, t2: Ty<'tcx>) -> RelateResult<'tcx, Ty<'tcx>> { // // cc trait-system-refactor-initiative#108 if self.infcx.next_trait_solver() - && !matches!(self.infcx.typing_mode(), TypingMode::Coherence) + && !self.infcx.typing_mode().is_coherence() && self.in_alias { inner.type_variables().equate(vid, new_var_id); @@ -735,7 +735,7 @@ fn consts( // See the comment for type inference variables // for more details. if self.infcx.next_trait_solver() - && !matches!(self.infcx.typing_mode(), TypingMode::Coherence) + && !self.infcx.typing_mode().is_coherence() && self.in_alias { variable_table.union(vid, new_var_id); diff --git a/compiler/rustc_infer/src/infer/snapshot/fudge.rs b/compiler/rustc_infer/src/infer/snapshot/fudge.rs index 6709c822dc7b..2ce98b7541af 100644 --- a/compiler/rustc_infer/src/infer/snapshot/fudge.rs +++ b/compiler/rustc_infer/src/infer/snapshot/fudge.rs @@ -10,9 +10,11 @@ use ut::UnifyKey; use super::VariableLengths; -use crate::infer::type_variable::TypeVariableOrigin; +use crate::infer::type_variable::{FloatVariableOrigin, TypeVariableOrigin}; use crate::infer::unify_key::{ConstVariableValue, ConstVidKey}; -use crate::infer::{ConstVariableOrigin, InferCtxt, RegionVariableOrigin, UnificationTable}; +use crate::infer::{ + ConstVariableOrigin, InferCtxt, InferCtxtInner, RegionVariableOrigin, UnificationTable, +}; fn vars_since_snapshot<'tcx, T>( table: &UnificationTable<'_, 'tcx, T>, @@ -25,6 +27,14 @@ fn vars_since_snapshot<'tcx, T>( T::from_index(snapshot_var_len as u32)..T::from_index(table.len() as u32) } +fn float_vars_since_snapshot( + inner: &mut InferCtxtInner<'_>, + snapshot_var_len: usize, +) -> (Range, Vec) { + let range = vars_since_snapshot(&inner.float_unification_table(), snapshot_var_len); + (range.clone(), range.map(|index| inner.float_origin_origin_storage[index]).collect()) +} + fn const_vars_since_snapshot<'tcx>( table: &mut UnificationTable<'_, 'tcx, ConstVidKey<'tcx>>, snapshot_var_len: usize, @@ -130,7 +140,7 @@ struct SnapshotVarData<'tcx> { region_vars: (Range, Vec>), type_vars: (Range, Vec), int_vars: Range, - float_vars: Range, + float_vars: (Range, Vec), const_vars: (Range, Vec), } @@ -143,8 +153,7 @@ fn new(infcx: &InferCtxt<'tcx>, vars_pre_snapshot: VariableLengths) -> SnapshotV let type_vars = inner.type_variables().vars_since_snapshot(vars_pre_snapshot.type_var_len); let int_vars = vars_since_snapshot(&inner.int_unification_table(), vars_pre_snapshot.int_var_len); - let float_vars = - vars_since_snapshot(&inner.float_unification_table(), vars_pre_snapshot.float_var_len); + let float_vars = float_vars_since_snapshot(&mut inner, vars_pre_snapshot.float_var_len); let const_vars = const_vars_since_snapshot( &mut inner.const_unification_table(), @@ -158,7 +167,7 @@ fn is_empty(&self) -> bool { region_vars.0.is_empty() && type_vars.0.is_empty() && int_vars.is_empty() - && float_vars.is_empty() + && float_vars.0.is_empty() && const_vars.0.is_empty() } } @@ -203,8 +212,11 @@ fn fold_ty(&mut self, ty: Ty<'tcx>) -> Ty<'tcx> { } } ty::FloatVar(vid) => { - if self.snapshot_vars.float_vars.contains(&vid) { - self.infcx.next_float_var() + if self.snapshot_vars.float_vars.0.contains(&vid) { + let idx = vid.as_usize() - self.snapshot_vars.float_vars.0.start.as_usize(); + let FloatVariableOrigin { span, lint_id } = + self.snapshot_vars.float_vars.1[idx]; + self.infcx.next_float_var(span, lint_id) } else { ty } diff --git a/compiler/rustc_infer/src/infer/type_variable.rs b/compiler/rustc_infer/src/infer/type_variable.rs index 65f77fe8e25f..4c56bf0923c3 100644 --- a/compiler/rustc_infer/src/infer/type_variable.rs +++ b/compiler/rustc_infer/src/infer/type_variable.rs @@ -4,6 +4,7 @@ use rustc_data_structures::undo_log::Rollback; use rustc_data_structures::{snapshot_vec as sv, unify as ut}; +use rustc_hir::HirId; use rustc_hir::def_id::DefId; use rustc_index::IndexVec; use rustc_middle::bug; @@ -99,6 +100,16 @@ pub struct TypeVariableOrigin { pub param_def_id: Option, } +#[derive(Copy, Clone, Debug)] +pub struct FloatVariableOrigin { + pub span: Span, + + /// `HirId` to lint at for this float variable, if any. + /// + /// This should only be used for diagnostics. + pub lint_id: Option, +} + #[derive(Clone)] pub(crate) struct TypeVariableData { origin: TypeVariableOrigin, diff --git a/compiler/rustc_interface/src/errors.rs b/compiler/rustc_interface/src/errors.rs index 7e4671889f57..7cae1aa54d2e 100644 --- a/compiler/rustc_interface/src/errors.rs +++ b/compiler/rustc_interface/src/errors.rs @@ -25,7 +25,7 @@ pub(crate) struct CrateNameInvalid<'a> { #[derive(Diagnostic)] #[diag("Ferris cannot be used as an identifier")] -pub struct FerrisIdentifier { +pub(crate) struct FerrisIdentifier { #[primary_span] pub spans: Vec, #[suggestion( @@ -39,7 +39,7 @@ pub struct FerrisIdentifier { #[derive(Diagnostic)] #[diag("identifiers cannot contain emoji: `{$ident}`")] -pub struct EmojiIdentifier { +pub(crate) struct EmojiIdentifier { #[primary_span] pub spans: Vec, pub ident: Symbol, @@ -47,22 +47,22 @@ pub struct EmojiIdentifier { #[derive(Diagnostic)] #[diag("cannot mix `bin` crate type with others")] -pub struct MixedBinCrate; +pub(crate) struct MixedBinCrate; #[derive(Diagnostic)] #[diag("cannot mix `proc-macro` crate type with others")] -pub struct MixedProcMacroCrate; +pub(crate) struct MixedProcMacroCrate; #[derive(Diagnostic)] #[diag("error writing dependencies to `{$path}`: {$error}")] -pub struct ErrorWritingDependencies<'a> { +pub(crate) struct ErrorWritingDependencies<'a> { pub path: &'a Path, pub error: io::Error, } #[derive(Diagnostic)] #[diag("the input file \"{$path}\" would be overwritten by the generated executable")] -pub struct InputFileWouldBeOverWritten<'a> { +pub(crate) struct InputFileWouldBeOverWritten<'a> { pub path: &'a Path, } @@ -70,22 +70,22 @@ pub struct InputFileWouldBeOverWritten<'a> { #[diag( "the generated executable for the input file \"{$input_path}\" conflicts with the existing directory \"{$dir_path}\"" )] -pub struct GeneratedFileConflictsWithDirectory<'a> { +pub(crate) struct GeneratedFileConflictsWithDirectory<'a> { pub input_path: &'a Path, pub dir_path: &'a Path, } #[derive(Diagnostic)] #[diag("failed to find or create the directory specified by `--temps-dir`")] -pub struct TempsDirError; +pub(crate) struct TempsDirError; #[derive(Diagnostic)] #[diag("failed to find or create the directory specified by `--out-dir`")] -pub struct OutDirError; +pub(crate) struct OutDirError; #[derive(Diagnostic)] #[diag("failed to write file {$path}: {$error}\"")] -pub struct FailedWritingFile<'a> { +pub(crate) struct FailedWritingFile<'a> { pub path: &'a Path, pub error: io::Error, } @@ -94,25 +94,25 @@ pub struct FailedWritingFile<'a> { #[diag( "building proc macro crate with `panic=abort` or `panic=immediate-abort` may crash the compiler should the proc-macro panic" )] -pub struct ProcMacroCratePanicAbort; +pub(crate) struct ProcMacroCratePanicAbort; #[derive(Diagnostic)] #[diag( "due to multiple output types requested, the explicitly specified output file name will be adapted for each output type" )] -pub struct MultipleOutputTypesAdaption; +pub(crate) struct MultipleOutputTypesAdaption; #[derive(Diagnostic)] #[diag("ignoring -C extra-filename flag due to -o flag")] -pub struct IgnoringExtraFilename; +pub(crate) struct IgnoringExtraFilename; #[derive(Diagnostic)] #[diag("ignoring --out-dir flag due to -o flag")] -pub struct IgnoringOutDir; +pub(crate) struct IgnoringOutDir; #[derive(Diagnostic)] #[diag("can't use option `-o` or `--emit` to write multiple output types to stdout")] -pub struct MultipleOutputTypesToStdout; +pub(crate) struct MultipleOutputTypesToStdout; #[derive(Diagnostic)] #[diag( diff --git a/compiler/rustc_interface/src/passes.rs b/compiler/rustc_interface/src/passes.rs index 43efce545fc2..bd2ab2834dbc 100644 --- a/compiler/rustc_interface/src/passes.rs +++ b/compiler/rustc_interface/src/passes.rs @@ -13,6 +13,7 @@ use rustc_data_structures::steal::Steal; use rustc_data_structures::sync::{AppendOnlyIndexVec, FreezeLock, WorkerLocal, par_fns}; use rustc_data_structures::thousands; +use rustc_errors::DiagCallback; use rustc_errors::timings::TimingSection; use rustc_expand::base::{ExtCtxt, LintStoreExpand}; use rustc_feature::Features; @@ -119,10 +120,11 @@ fn pre_expansion_lint( features: &Features, registered_tools: &RegisteredTools, node_id: ast::NodeId, + attrs: &[ast::Attribute], items: &[Box], name: Symbol, ) { - pre_expansion_lint(sess, features, self.0, registered_tools, (node_id, items), name); + pre_expansion_lint(sess, features, self.0, registered_tools, (node_id, attrs, items), name); } } @@ -303,8 +305,7 @@ fn configure_and_expand( resolver.resolve_crate(&krate); - CStore::from_tcx(tcx).report_incompatible_target_modifiers(tcx, &krate); - CStore::from_tcx(tcx).report_incompatible_async_drop_feature(tcx, &krate); + CStore::from_tcx(tcx).report_session_incompatibilities(tcx, &krate); krate } @@ -1030,13 +1031,13 @@ pub fn create_and_enter_global_ctxt FnOnce(TyCtxt<'tcx>) -> T>( pub fn emit_delayed_lints(tcx: TyCtxt<'_>) { for owner_id in tcx.hir_crate_items(()).delayed_lint_items() { if let Some(delayed_lints) = tcx.opt_ast_lowering_delayed_lints(owner_id) { - for lint in &delayed_lints.lints { + for lint in delayed_lints { match lint { DelayedLint::AttributeParsing(attribute_lint) => { tcx.emit_node_span_lint( attribute_lint.lint_id.lint, attribute_lint.id, - attribute_lint.span, + attribute_lint.span.clone(), DecorateAttrLint { sess: tcx.sess, tcx: Some(tcx), @@ -1044,6 +1045,12 @@ pub fn emit_delayed_lints(tcx: TyCtxt<'_>) { }, ); } + DelayedLint::Dynamic(attribute_lint) => tcx.emit_node_span_lint( + attribute_lint.lint_id.lint, + attribute_lint.id, + attribute_lint.span.clone(), + DiagCallback(&attribute_lint.callback), + ), } } } @@ -1113,11 +1120,11 @@ fn run_required_analyses(tcx: TyCtxt<'_>) { { let hir_items = tcx.hir_crate_items(()); for owner_id in hir_items.owners() { - if let Some(delayed_lints) = tcx.opt_ast_lowering_delayed_lints(owner_id) { - if !delayed_lints.lints.is_empty() { - // Assert that delayed_lint_items also picked up this item to have lints. - assert!(hir_items.delayed_lint_items().any(|i| i == owner_id)); - } + if let Some(delayed_lints) = tcx.opt_ast_lowering_delayed_lints(owner_id) + && !delayed_lints.is_empty() + { + // Assert that delayed_lint_items also picked up this item to have lints. + assert!(hir_items.delayed_lint_items().any(|i| i == owner_id)); } } } @@ -1273,7 +1280,7 @@ pub(crate) fn start_codegen<'tcx>( // Don't run this test assertions when not doing codegen. Compiletest tries to build // build-fail tests in check mode first and expects it to not give an error in that case. if tcx.sess.opts.output_types.should_codegen() { - rustc_symbol_mangling::test::report_symbol_names(tcx); + rustc_symbol_mangling::test::dump_symbol_names_and_def_paths(tcx); } // Don't do code generation if there were any errors. Likewise if @@ -1369,7 +1376,7 @@ pub(crate) fn parse_crate_name( AttributeParser::parse_limited_should_emit( sess, attrs, - sym::crate_name, + &[sym::crate_name], DUMMY_SP, rustc_ast::node_id::CRATE_NODE_ID, Target::Crate, @@ -1419,7 +1426,7 @@ pub fn collect_crate_types( AttributeParser::::parse_limited_should_emit( session, attrs, - sym::crate_type, + &[sym::crate_type], crate_span, CRATE_NODE_ID, Target::Crate, @@ -1476,7 +1483,7 @@ fn get_recursion_limit(krate_attrs: &[ast::Attribute], sess: &Session) -> Limit let attr = AttributeParser::parse_limited_should_emit( sess, &krate_attrs, - sym::recursion_limit, + &[sym::recursion_limit], DUMMY_SP, rustc_ast::node_id::CRATE_NODE_ID, Target::Crate, diff --git a/compiler/rustc_interface/src/tests.rs b/compiler/rustc_interface/src/tests.rs index 417cde119c21..e54f68b6391e 100644 --- a/compiler/rustc_interface/src/tests.rs +++ b/compiler/rustc_interface/src/tests.rs @@ -817,6 +817,7 @@ macro_rules! tracked { tracked!(lint_llvm_ir, true); tracked!(llvm_module_flag, vec![("bar".to_string(), 123, "max".to_string())]); tracked!(llvm_plugins, vec![String::from("plugin_name")]); + tracked!(llvm_writable, true); tracked!(location_detail, LocationDetail { file: true, line: false, column: false }); tracked!(maximal_hir_to_mir_coverage, true); tracked!(merge_functions, Some(MergeFunctions::Disabled)); diff --git a/compiler/rustc_interface/src/util.rs b/compiler/rustc_interface/src/util.rs index 0cd0275f96bb..24b23cc4199e 100644 --- a/compiler/rustc_interface/src/util.rs +++ b/compiler/rustc_interface/src/util.rs @@ -184,7 +184,7 @@ pub(crate) fn run_in_thread_pool_with_globals< use rustc_data_structures::defer; use rustc_middle::ty::tls; - use rustc_query_impl::break_query_cycles; + use rustc_query_impl::break_query_cycle; let thread_stack_size = init_stack_size(thread_builder_diag); @@ -260,7 +260,7 @@ pub(crate) fn run_in_thread_pool_with_globals< ) }, ); - break_query_cycles(job_map, ®istry); + break_query_cycle(job_map, ®istry); }) }) }); diff --git a/compiler/rustc_lint/src/builtin.rs b/compiler/rustc_lint/src/builtin.rs index b49a6e261d73..ff08898fe93a 100644 --- a/compiler/rustc_lint/src/builtin.rs +++ b/compiler/rustc_lint/src/builtin.rs @@ -312,10 +312,7 @@ fn check_item(&mut self, cx: &EarlyContext<'_>, it: &ast::Item) { AttributeParser::parse_limited( cx.builder.sess(), &it.attrs, - sym::allow_internal_unsafe, - it.span, - DUMMY_NODE_ID, - Some(cx.builder.features()), + &[sym::allow_internal_unsafe], ) { self.report_unsafe(cx, span, BuiltinUnsafe::AllowInternalUnsafe); @@ -1901,10 +1898,9 @@ fn check_ident_token( return; } - cx.sess().psess.buffer_lint( + cx.emit_span_lint( lint, ident.span, - CRATE_NODE_ID, BuiltinKeywordIdents { kw: ident, next: edition, suggestion: ident.span, prefix }, ); } diff --git a/compiler/rustc_lint/src/context.rs b/compiler/rustc_lint/src/context.rs index ae90c74c7e06..acfa3ec34397 100644 --- a/compiler/rustc_lint/src/context.rs +++ b/compiler/rustc_lint/src/context.rs @@ -25,9 +25,7 @@ use rustc_middle::ty::layout::{LayoutError, LayoutOfHelpers, TyAndLayout}; use rustc_middle::ty::print::{PrintError, PrintTraitRefExt as _, Printer, with_no_trimmed_paths}; use rustc_middle::ty::{self, GenericArg, RegisteredTools, Ty, TyCtxt, TypingEnv, TypingMode}; -use rustc_session::lint::{ - CheckLintNameResult, FutureIncompatibleInfo, Lint, LintExpectationId, LintId, TargetLint, -}; +use rustc_session::lint::{FutureIncompatibleInfo, Lint, LintExpectationId, LintId}; use rustc_session::{DynLintStore, Session}; use rustc_span::edit_distance::find_best_match_for_names; use rustc_span::{Ident, Span, Symbol, sym}; @@ -71,19 +69,26 @@ fn lint_groups_iter(&self) -> Box rustc_session::LintGroup { name, lints, is_externally_loaded } })) } +} - fn check_lint_name( - &self, - lint_name: &str, - tool_name: Option, - registered_tools: &RegisteredTools, - ) -> CheckLintNameResult<'_> { - self.check_lint_name(lint_name, tool_name, registered_tools) - } +/// The target of the `by_name` map, which accounts for renaming/deprecation. +#[derive(Debug)] +enum TargetLint { + /// A direct lint target + Id(LintId), - fn find_lints(&self, lint_name: &str) -> Option<&[LintId]> { - self.find_lints(lint_name) - } + /// Temporary renaming, used for easing migration pain; see #16545 + Renamed(String, LintId), + + /// Lint with this name existed previously, but has been removed/deprecated. + /// The string argument is the reason for removal. + Removed(String), + + /// A lint name that should give no warnings and have no effect. + /// + /// This is used by rustc to avoid warning about old rustdoc lints before rustdoc registers + /// them as tool lints. + Ignored, } struct LintAlias { @@ -98,6 +103,29 @@ struct LintGroup { depr: Option, } +#[derive(Debug)] +pub enum CheckLintNameResult<'a> { + Ok(&'a [LintId]), + /// Lint doesn't exist. Potentially contains a suggestion for a correct lint name. + NoLint(Option<(Symbol, bool)>), + /// The lint refers to a tool that has not been registered. + NoTool, + /// The lint has been renamed to a new name. + Renamed(String), + /// The lint has been removed due to the given reason. + Removed(String), + + /// The lint is from a tool. The `LintId` will be returned as if it were a + /// rustc lint. The `Option` indicates if the lint has been + /// renamed. + Tool(&'a [LintId], Option), + + /// The lint is from a tool. Either the lint does not exist in the tool or + /// the code was not compiled with the tool and therefore the lint was + /// never added to the `LintStore`. + MissingTool, +} + impl LintStore { pub fn new() -> LintStore { LintStore { @@ -276,10 +304,6 @@ pub fn register_removed(&mut self, name: &str, reason: &str) { self.by_name.insert(name.into(), Removed(reason.into())); } - pub fn get_lint_by_name(&self, lint_name: &str) -> Option<&TargetLint> { - self.by_name.get(lint_name) - } - pub fn find_lints(&self, lint_name: &str) -> Option<&[LintId]> { match self.by_name.get(lint_name) { Some(Id(lint_id)) => Some(slice::from_ref(lint_id)), @@ -369,7 +393,7 @@ pub fn check_lint_name( } } match self.by_name.get(&complete_name) { - Some(Renamed(new_name, _)) => CheckLintNameResult::Renamed(Symbol::intern(new_name)), + Some(Renamed(new_name, _)) => CheckLintNameResult::Renamed(new_name.to_string()), Some(Removed(reason)) => CheckLintNameResult::Removed(reason.to_string()), None => match self.lint_groups.get(&*complete_name) { // If neither the lint, nor the lint group exists check if there is a `clippy::` @@ -578,8 +602,6 @@ fn opt_span_lint>( } } - /// Only appropriate for use inside of the compiler - /// since the compiler doesn't track levels of tool lints fn get_lint_level(&self, lint: &'static Lint) -> LevelAndSource { self.tcx.lint_level_at_node(lint, self.last_node_with_lint_attrs) } @@ -615,7 +637,7 @@ pub fn typing_mode(&self) -> TypingMode<'tcx> { } pub fn typing_env(&self) -> TypingEnv<'tcx> { - TypingEnv { typing_mode: self.typing_mode(), param_env: self.param_env } + TypingEnv::new(self.param_env, self.typing_mode()) } pub fn type_is_copy_modulo_regions(&self, ty: Ty<'tcx>) -> bool { @@ -820,7 +842,12 @@ pub fn get_associated_type( /// be used for pretty-printing HIR by rustc_hir_pretty. pub fn precedence(&self, expr: &hir::Expr<'_>) -> ExprPrecedence { let has_attr = |id: hir::HirId| -> bool { - self.tcx.hir_attrs(id).iter().any(hir::Attribute::has_span_without_desugaring_kind) + for attr in self.tcx.hir_attrs(id) { + if attr.span().desugaring_kind().is_none() { + return true; + } + } + false }; expr.precedence(&has_attr) } diff --git a/compiler/rustc_lint/src/early.rs b/compiler/rustc_lint/src/early.rs index e55cfc052ac4..df5adf694d3a 100644 --- a/compiler/rustc_lint/src/early.rs +++ b/compiler/rustc_lint/src/early.rs @@ -12,7 +12,7 @@ use rustc_middle::ty::{RegisteredTools, TyCtxt}; use rustc_session::Session; use rustc_session::lint::LintPass; -use rustc_span::{DUMMY_SP, Ident, Span}; +use rustc_span::{Ident, Span}; use tracing::debug; use crate::context::{EarlyContext, LintContext, LintStore}; @@ -63,17 +63,13 @@ fn check_id(&mut self, id: ast::NodeId) { /// Merge the lints specified by any lint attributes into the /// current lint context, call the provided function, then reset the /// lints in effect to their previous state. - fn with_lint_attrs( - &mut self, - id: ast::NodeId, - attrs: &'_ [ast::Attribute], - f: F, - target_span: Span, - ) where + fn with_lint_attrs(&mut self, id: ast::NodeId, attrs: &'_ [ast::Attribute], f: F) + where F: FnOnce(&mut Self), { + let is_crate_node = id == ast::CRATE_NODE_ID; debug!(?id); - let push = self.context.builder.push(attrs, id, target_span); + let push = self.context.builder.push(attrs, is_crate_node, None); debug!("early context: enter_attrs({:?})", attrs); lint_callback!(self, check_attributes, attrs); @@ -92,39 +88,24 @@ fn visit_id(&mut self, id: rustc_ast::NodeId) { } fn visit_param(&mut self, param: &'ast ast::Param) { - self.with_lint_attrs( - param.id, - ¶m.attrs, - |cx| { - lint_callback!(cx, check_param, param); - ast_visit::walk_param(cx, param); - }, - param.span, - ); + self.with_lint_attrs(param.id, ¶m.attrs, |cx| { + lint_callback!(cx, check_param, param); + ast_visit::walk_param(cx, param); + }); } fn visit_item(&mut self, it: &'ast ast::Item) { - self.with_lint_attrs( - it.id, - &it.attrs, - |cx| { - lint_callback!(cx, check_item, it); - ast_visit::walk_item(cx, it); - lint_callback!(cx, check_item_post, it); - }, - it.span, - ) + self.with_lint_attrs(it.id, &it.attrs, |cx| { + lint_callback!(cx, check_item, it); + ast_visit::walk_item(cx, it); + lint_callback!(cx, check_item_post, it); + }) } fn visit_foreign_item(&mut self, it: &'ast ast::ForeignItem) { - self.with_lint_attrs( - it.id, - &it.attrs, - |cx| { - ast_visit::walk_item(cx, it); - }, - it.span, - ) + self.with_lint_attrs(it.id, &it.attrs, |cx| { + ast_visit::walk_item(cx, it); + }) } fn visit_pat(&mut self, p: &'ast ast::Pat) { @@ -134,38 +115,23 @@ fn visit_pat(&mut self, p: &'ast ast::Pat) { } fn visit_pat_field(&mut self, field: &'ast ast::PatField) { - self.with_lint_attrs( - field.id, - &field.attrs, - |cx| { - ast_visit::walk_pat_field(cx, field); - }, - field.span, - ); + self.with_lint_attrs(field.id, &field.attrs, |cx| { + ast_visit::walk_pat_field(cx, field); + }); } fn visit_expr(&mut self, e: &'ast ast::Expr) { - self.with_lint_attrs( - e.id, - &e.attrs, - |cx| { - lint_callback!(cx, check_expr, e); - ast_visit::walk_expr(cx, e); - lint_callback!(cx, check_expr_post, e); - }, - e.span, - ) + self.with_lint_attrs(e.id, &e.attrs, |cx| { + lint_callback!(cx, check_expr, e); + ast_visit::walk_expr(cx, e); + lint_callback!(cx, check_expr_post, e); + }) } fn visit_expr_field(&mut self, f: &'ast ast::ExprField) { - self.with_lint_attrs( - f.id, - &f.attrs, - |cx| { - ast_visit::walk_expr_field(cx, f); - }, - f.span, - ) + self.with_lint_attrs(f.id, &f.attrs, |cx| { + ast_visit::walk_expr_field(cx, f); + }) } fn visit_stmt(&mut self, s: &'ast ast::Stmt) { @@ -177,15 +143,10 @@ fn visit_stmt(&mut self, s: &'ast ast::Stmt) { // // Note that statements get their attributes from // the AST struct that they wrap (e.g. an item) - self.with_lint_attrs( - s.id, - s.attrs(), - |cx| { - lint_callback!(cx, check_stmt, s); - ast_visit::walk_stmt(cx, s); - }, - s.span, - ); + self.with_lint_attrs(s.id, s.attrs(), |cx| { + lint_callback!(cx, check_stmt, s); + ast_visit::walk_stmt(cx, s); + }); } fn visit_fn(&mut self, fk: ast_visit::FnKind<'ast>, _: &AttrVec, span: Span, id: ast::NodeId) { @@ -194,26 +155,16 @@ fn visit_fn(&mut self, fk: ast_visit::FnKind<'ast>, _: &AttrVec, span: Span, id: } fn visit_field_def(&mut self, s: &'ast ast::FieldDef) { - self.with_lint_attrs( - s.id, - &s.attrs, - |cx| { - ast_visit::walk_field_def(cx, s); - }, - s.span, - ) + self.with_lint_attrs(s.id, &s.attrs, |cx| { + ast_visit::walk_field_def(cx, s); + }) } fn visit_variant(&mut self, v: &'ast ast::Variant) { - self.with_lint_attrs( - v.id, - &v.attrs, - |cx| { - lint_callback!(cx, check_variant, v); - ast_visit::walk_variant(cx, v); - }, - v.span, - ) + self.with_lint_attrs(v.id, &v.attrs, |cx| { + lint_callback!(cx, check_variant, v); + ast_visit::walk_variant(cx, v); + }) } fn visit_ty(&mut self, t: &'ast ast::Ty) { @@ -226,15 +177,10 @@ fn visit_ident(&mut self, ident: &Ident) { } fn visit_local(&mut self, l: &'ast ast::Local) { - self.with_lint_attrs( - l.id, - &l.attrs, - |cx| { - lint_callback!(cx, check_local, l); - ast_visit::walk_local(cx, l); - }, - l.span, - ) + self.with_lint_attrs(l.id, &l.attrs, |cx| { + lint_callback!(cx, check_local, l); + ast_visit::walk_local(cx, l); + }) } fn visit_block(&mut self, b: &'ast ast::Block) { @@ -243,15 +189,10 @@ fn visit_block(&mut self, b: &'ast ast::Block) { } fn visit_arm(&mut self, a: &'ast ast::Arm) { - self.with_lint_attrs( - a.id, - &a.attrs, - |cx| { - lint_callback!(cx, check_arm, a); - ast_visit::walk_arm(cx, a); - }, - a.span, - ) + self.with_lint_attrs(a.id, &a.attrs, |cx| { + lint_callback!(cx, check_arm, a); + ast_visit::walk_arm(cx, a); + }) } fn visit_generic_arg(&mut self, arg: &'ast ast::GenericArg) { @@ -260,15 +201,10 @@ fn visit_generic_arg(&mut self, arg: &'ast ast::GenericArg) { } fn visit_generic_param(&mut self, param: &'ast ast::GenericParam) { - self.with_lint_attrs( - param.id, - ¶m.attrs, - |cx| { - lint_callback!(cx, check_generic_param, param); - ast_visit::walk_generic_param(cx, param); - }, - param.span(), - ); + self.with_lint_attrs(param.id, ¶m.attrs, |cx| { + lint_callback!(cx, check_generic_param, param); + ast_visit::walk_generic_param(cx, param); + }); } fn visit_generics(&mut self, g: &'ast ast::Generics) { @@ -288,30 +224,25 @@ fn visit_poly_trait_ref(&mut self, t: &'ast ast::PolyTraitRef) { } fn visit_assoc_item(&mut self, item: &'ast ast::AssocItem, ctxt: ast_visit::AssocCtxt) { - self.with_lint_attrs( - item.id, - &item.attrs, - |cx| { - match ctxt { - ast_visit::AssocCtxt::Trait => { - lint_callback!(cx, check_trait_item, item); - } - ast_visit::AssocCtxt::Impl { .. } => { - lint_callback!(cx, check_impl_item, item); - } + self.with_lint_attrs(item.id, &item.attrs, |cx| { + match ctxt { + ast_visit::AssocCtxt::Trait => { + lint_callback!(cx, check_trait_item, item); } - ast_visit::walk_assoc_item(cx, item, ctxt); - match ctxt { - ast_visit::AssocCtxt::Trait => { - lint_callback!(cx, check_trait_item_post, item); - } - ast_visit::AssocCtxt::Impl { .. } => { - lint_callback!(cx, check_impl_item_post, item); - } + ast_visit::AssocCtxt::Impl { .. } => { + lint_callback!(cx, check_impl_item, item); } - }, - item.span, - ); + } + ast_visit::walk_assoc_item(cx, item, ctxt); + match ctxt { + ast_visit::AssocCtxt::Trait => { + lint_callback!(cx, check_trait_item_post, item); + } + ast_visit::AssocCtxt::Impl { .. } => { + lint_callback!(cx, check_impl_item_post, item); + } + } + }); } fn visit_attribute(&mut self, attr: &'ast ast::Attribute) { @@ -383,15 +314,16 @@ fn check<'ecx, 'tcx, T: EarlyLintPass>(self, cx: &mut EarlyContextAndPass<'ecx, } } -impl<'a> EarlyCheckNode<'a> for (ast::NodeId, &'a [Box]) { +impl<'a> EarlyCheckNode<'a> for (ast::NodeId, &'a [ast::Attribute], &'a [Box]) { fn id(self) -> ast::NodeId { self.0 } fn attrs(self) -> &'a [ast::Attribute] { - &[] + self.1 } fn check<'ecx, 'tcx, T: EarlyLintPass>(self, cx: &mut EarlyContextAndPass<'ecx, 'tcx, T>) { - walk_list!(cx, visit_item, self.1); + walk_list!(cx, visit_attribute, self.1); + walk_list!(cx, visit_item, self.2); } } @@ -439,7 +371,7 @@ fn check_ast_node_inner<'a, T: EarlyLintPass>( ) { let mut cx = EarlyContextAndPass { context, tcx, pass }; - cx.with_lint_attrs(check_node.id(), check_node.attrs(), |cx| check_node.check(cx), DUMMY_SP); + cx.with_lint_attrs(check_node.id(), check_node.attrs(), |cx| check_node.check(cx)); // All of the buffered lints should have been emitted at this point. // If not, that means that we somehow buffered a lint for a node id diff --git a/compiler/rustc_lint/src/early/diagnostics.rs b/compiler/rustc_lint/src/early/diagnostics.rs index 0f27e04babd4..7340ba0b2f39 100644 --- a/compiler/rustc_lint/src/early/diagnostics.rs +++ b/compiler/rustc_lint/src/early/diagnostics.rs @@ -35,9 +35,6 @@ pub struct DecorateAttrLint<'a, 'sess, 'tcx> { impl<'a> Diagnostic<'a, ()> for DecorateAttrLint<'_, '_, '_> { fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { match self.diagnostic { - &AttributeLintKind::UnusedDuplicate { this, other, warning } => { - lints::UnusedDuplicate { this, other, warning }.into_diag(dcx, level) - } AttributeLintKind::IllFormedAttributeInput { suggestions, docs, help } => { lints::IllFormedAttributeInput { num_suggestions: suggestions.len(), @@ -82,15 +79,6 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { target, } .into_diag(dcx, level), - &AttributeLintKind::UnsafeAttrOutsideUnsafe { attribute_name_span, sugg_spans } => { - lints::UnsafeAttrOutsideUnsafeLint { - span: attribute_name_span, - suggestion: sugg_spans.map(|(left, right)| { - lints::UnsafeAttrOutsideUnsafeSuggestion { left, right } - }), - } - .into_diag(dcx, level) - } &AttributeLintKind::UnexpectedCfgName(name, value) => { check_cfg::unexpected_cfg_name(self.sess, self.tcx, name, value) .into_diag(dcx, level) @@ -176,12 +164,11 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { &AttributeLintKind::ExpectedNoArgs => lints::ExpectedNoArgs.into_diag(dcx, level), &AttributeLintKind::ExpectedNameValue => lints::ExpectedNameValue.into_diag(dcx, level), - &AttributeLintKind::MalformedOnUnimplementedAttr { span } => { - lints::MalformedOnUnimplementedAttrLint { span }.into_diag(dcx, level) - } - &AttributeLintKind::MalformedOnConstAttr { span } => { - lints::MalformedOnConstAttrLint { span }.into_diag(dcx, level) + &AttributeLintKind::MalFormedDiagnosticAttribute { attribute, options, span } => { + lints::MalFormedDiagnosticAttributeLint { attribute, options, span } + .into_diag(dcx, level) } + AttributeLintKind::MalformedDiagnosticFormat { warning } => match warning { FormatWarning::PositionalArgument { .. } => { lints::DisallowedPositionalArgument.into_diag(dcx, level) @@ -189,6 +176,9 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { FormatWarning::InvalidSpecifier { .. } => { lints::InvalidFormatSpecifier.into_diag(dcx, level) } + FormatWarning::DisallowedPlaceholder { .. } => { + lints::DisallowedPlaceholder.into_diag(dcx, level) + } }, AttributeLintKind::DiagnosticWrappedParserError { description, label, span } => { lints::WrappedParserError { description, label, span: *span }.into_diag(dcx, level) @@ -197,45 +187,12 @@ fn into_diag(self, dcx: DiagCtxtHandle<'a>, level: Level) -> Diag<'a, ()> { lints::IgnoredDiagnosticOption { option_name, first_span, later_span } .into_diag(dcx, level) } - &AttributeLintKind::MissingOptionsForOnUnimplemented => { - lints::MissingOptionsForOnUnimplementedAttr.into_diag(dcx, level) + &AttributeLintKind::MissingOptionsForDiagnosticAttribute { attribute, options } => { + lints::MissingOptionsForDiagnosticAttribute { attribute, options } + .into_diag(dcx, level) } - &AttributeLintKind::MissingOptionsForOnConst => { - lints::MissingOptionsForOnConstAttr.into_diag(dcx, level) - } - &AttributeLintKind::MalformedOnMoveAttr { span } => { - lints::MalformedOnMoveAttrLint { span }.into_diag(dcx, level) - } - &AttributeLintKind::OnMoveMalformedFormatLiterals { name } => { - lints::OnMoveMalformedFormatLiterals { name }.into_diag(dcx, level) - } - &AttributeLintKind::OnMoveMalformedAttrExpectedLiteralOrDelimiter => { - lints::OnMoveMalformedAttrExpectedLiteralOrDelimiter.into_diag(dcx, level) - } - &AttributeLintKind::MissingOptionsForOnMove => { - lints::MissingOptionsForOnMoveAttr.into_diag(dcx, level) - } - &AttributeLintKind::RenamedLint { name, replace, suggestion } => lints::RenamedLint { - name, - replace, - suggestion: lints::RenamedLintSuggestion::WithSpan { suggestion, replace }, - } - .into_diag(dcx, level), - &AttributeLintKind::DeprecatedLintName { name, suggestion, replace } => { - lints::DeprecatedLintName { name, suggestion, replace }.into_diag(dcx, level) - } - &AttributeLintKind::RemovedLint { name, ref reason } => { - lints::RemovedLint { name, reason }.into_diag(dcx, level) - } - &AttributeLintKind::UnknownLint { name, span, suggestion } => lints::UnknownLint { - name, - suggestion: suggestion.map(|(replace, from_rustc)| { - lints::UnknownLintSuggestion::WithSpan { suggestion: span, replace, from_rustc } - }), - } - .into_diag(dcx, level), - &AttributeLintKind::IgnoredUnlessCrateSpecified { level: attr_level, name } => { - lints::IgnoredUnlessCrateSpecified { level: attr_level, name }.into_diag(dcx, level) + &AttributeLintKind::NonMetaItemDiagnosticAttribute => { + lints::NonMetaItemDiagnosticAttribute.into_diag(dcx, level) } } } diff --git a/compiler/rustc_lint/src/errors.rs b/compiler/rustc_lint/src/errors.rs index 33ba7f6edbda..8fec30816bd1 100644 --- a/compiler/rustc_lint/src/errors.rs +++ b/compiler/rustc_lint/src/errors.rs @@ -44,6 +44,36 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { } } +#[derive(Diagnostic)] +#[diag("malformed lint attribute input", code = E0452)] +pub(crate) struct MalformedAttribute { + #[primary_span] + pub span: Span, + #[subdiagnostic] + pub sub: MalformedAttributeSub, +} + +#[derive(Subdiagnostic)] +pub(crate) enum MalformedAttributeSub { + #[label("bad attribute argument")] + BadAttributeArgument(#[primary_span] Span), + #[label("reason must be a string literal")] + ReasonMustBeStringLiteral(#[primary_span] Span), + #[label("reason in lint attribute must come last")] + ReasonMustComeLast(#[primary_span] Span), +} + +#[derive(Diagnostic)] +#[diag("unknown tool name `{$tool_name}` found in scoped lint: `{$tool_name}::{$lint_name}`", code = E0710)] +pub(crate) struct UnknownToolInScopedLint { + #[primary_span] + pub span: Option, + pub tool_name: Symbol, + pub lint_name: String, + #[help("add `#![register_tool({$tool_name})]` to the crate root")] + pub is_nightly_build: bool, +} + #[derive(Diagnostic)] #[diag("`...` range patterns are deprecated", code = E0783)] pub(crate) struct BuiltinEllipsisInclusiveRangePatterns { diff --git a/compiler/rustc_lint/src/expect.rs b/compiler/rustc_lint/src/expect.rs index 12e23eea720f..481e116d06e0 100644 --- a/compiler/rustc_lint/src/expect.rs +++ b/compiler/rustc_lint/src/expect.rs @@ -18,33 +18,33 @@ fn lint_expectations(tcx: TyCtxt<'_>, (): ()) -> Vec<(LintExpectationId, LintExp let mut expectations = Vec::new(); for owner in krate.owners() { - // Deduplicate expectations - let mut inner_expectations = Vec::new(); let lints = tcx.shallow_lint_levels_on(owner); - for expectation in &lints.expectations { - let canonicalized = canonicalize_id(&expectation.0); - if !inner_expectations.iter().any(|(id, _)| canonicalize_id(id) == canonicalized) { - inner_expectations.push(expectation.clone()); - } - } - expectations.extend(inner_expectations); + expectations.extend_from_slice(&lints.expectations); } expectations } -fn canonicalize_id(expect_id: &LintExpectationId) -> (rustc_span::AttrId, u16) { - match *expect_id { - LintExpectationId::Unstable { attr_id, lint_index, .. } => (attr_id, lint_index), - LintExpectationId::Stable { attr_id, lint_index, .. } => (attr_id, lint_index), - } -} - fn check_expectations(tcx: TyCtxt<'_>, tool_filter: Option) { let lint_expectations = tcx.lint_expectations(()); let fulfilled_expectations = tcx.dcx().steal_fulfilled_expectation_ids(); // Turn a `LintExpectationId` into a `(AttrId, lint_index)` pair. + let canonicalize_id = |expect_id: &LintExpectationId| { + match *expect_id { + LintExpectationId::Unstable { attr_id, lint_index: Some(lint_index) } => { + (attr_id, lint_index) + } + LintExpectationId::Stable { hir_id, attr_index, lint_index: Some(lint_index) } => { + // We are an `eval_always` query, so looking at the attribute's `AttrId` is ok. + let attr_id = tcx.hir_attrs(hir_id)[attr_index as usize].id(); + + (attr_id, lint_index) + } + _ => panic!("fulfilled expectations must have a lint index"), + } + }; + let fulfilled_expectations: FxHashSet<_> = fulfilled_expectations.iter().map(canonicalize_id).collect(); diff --git a/compiler/rustc_lint/src/foreign_modules.rs b/compiler/rustc_lint/src/foreign_modules.rs index 9bc04db5e790..8d48b72a1221 100644 --- a/compiler/rustc_lint/src/foreign_modules.rs +++ b/compiler/rustc_lint/src/foreign_modules.rs @@ -329,8 +329,8 @@ fn structurally_same_type_impl<'tcx>( let a_sig = tcx.instantiate_bound_regions_with_erased(a_poly_sig); let b_sig = tcx.instantiate_bound_regions_with_erased(b_poly_sig); - (a_sig.abi, a_sig.safety, a_sig.c_variadic) - == (b_sig.abi, b_sig.safety, b_sig.c_variadic) + (a_sig.abi(), a_sig.safety(), a_sig.c_variadic()) + == (b_sig.abi(), b_sig.safety(), b_sig.c_variadic()) && a_sig.inputs().iter().eq_by(b_sig.inputs().iter(), |a, b| { structurally_same_type_impl(seen_types, tcx, typing_env, *a, *b) }) diff --git a/compiler/rustc_lint/src/impl_trait_overcaptures.rs b/compiler/rustc_lint/src/impl_trait_overcaptures.rs index 6edf2e943665..e3a7be02fca5 100644 --- a/compiler/rustc_lint/src/impl_trait_overcaptures.rs +++ b/compiler/rustc_lint/src/impl_trait_overcaptures.rs @@ -242,13 +242,12 @@ fn visit_ty(&mut self, t: Ty<'tcx>) { return; } - if let ty::Alias(opaque_ty @ ty::AliasTy { kind: ty::Projection { def_id }, .. }) = - *t.kind() + if let ty::Alias(ty::AliasTy { kind: ty::Projection { def_id }, args, .. }) = *t.kind() && self.tcx.is_impl_trait_in_trait(def_id) { // visit the opaque of the RPITIT - self.tcx.type_of(def_id).instantiate(self.tcx, opaque_ty.args).visit_with(self) - } else if let ty::Alias(opaque_ty @ ty::AliasTy { kind: ty::Opaque { def_id}, .. }) = *t.kind() + self.tcx.type_of(def_id).instantiate(self.tcx, args).visit_with(self) + } else if let ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args: opaque_ty_args, .. }) = *t.kind() && let Some(opaque_def_id) = def_id.as_local() // Don't recurse infinitely on an opaque && self.seen.insert(opaque_def_id) @@ -280,7 +279,7 @@ fn visit_ty(&mut self, t: Ty<'tcx>) { continue; } - let arg = opaque_ty.args[param.index as usize]; + let arg = opaque_ty_args[param.index as usize]; // We need to turn all `ty::Param`/`ConstKind::Param` and // `ReEarlyParam`/`ReBound` into def ids. captured.insert(extract_def_id_from_arg(self.tcx, generics, arg)); @@ -413,7 +412,7 @@ fn visit_ty(&mut self, t: Ty<'tcx>) { // in this lint as well. Interestingly, one place that I expect this lint to fire // is for `impl for<'a> Bound`, since `impl Other` will begin // to capture `'a` in e2024 (even though late-bound vars in opaques are not allowed). - for clause in self.tcx.item_bounds(def_id).iter_instantiated(self.tcx, opaque_ty.args) { + for clause in self.tcx.item_bounds(def_id).iter_instantiated(self.tcx, opaque_ty_args) { clause.visit_with(self) } } diff --git a/compiler/rustc_lint/src/internal.rs b/compiler/rustc_lint/src/internal.rs index 357aa94feb1e..d637390851d9 100644 --- a/compiler/rustc_lint/src/internal.rs +++ b/compiler/rustc_lint/src/internal.rs @@ -15,8 +15,9 @@ use crate::lints::{ AttributeKindInFindAttr, BadOptAccessDiag, DefaultHashTypesDiag, ImplicitSysrootCrateImportDiag, LintPassByHand, NonGlobImportTypeIrInherent, QueryInstability, - QueryUntracked, SpanUseEqCtxtDiag, SymbolInternStringLiteralDiag, TyQualified, TykindDiag, - TykindKind, TypeIrDirectUse, TypeIrInherentUsage, TypeIrTraitUsage, + QueryUntracked, RustcMustMatchExhaustivelyNotExhaustive, SpanUseEqCtxtDiag, + SymbolInternStringLiteralDiag, TyQualified, TykindDiag, TykindKind, TypeIrDirectUse, + TypeIrInherentUsage, TypeIrTraitUsage, }; use crate::{EarlyContext, EarlyLintPass, LateContext, LateLintPass, LintContext}; @@ -713,3 +714,111 @@ fn find_attr_kind_in_pat(cx: &EarlyContext<'_>, pat: &Pat) { } } } + +declare_tool_lint! { + pub rustc::RUSTC_MUST_MATCH_EXHAUSTIVELY, + Allow, + "Forbids matches with wildcards, or if-let matching on enums marked with `#[rustc_must_match_exhaustively]`", + report_in_external_macro: true +} +declare_lint_pass!(RustcMustMatchExhaustively => [RUSTC_MUST_MATCH_EXHAUSTIVELY]); + +fn is_rustc_must_match_exhaustively(cx: &LateContext<'_>, id: HirId) -> Option { + let res = cx.typeck_results(); + + let ty = res.node_type(id); + + let ty = if let ty::Ref(_, ty, _) = ty.kind() { *ty } else { ty }; + + if let Some(adt_def) = ty.ty_adt_def() + && adt_def.is_enum() + { + find_attr!(cx.tcx, adt_def.did(), RustcMustMatchExhaustively(span) => *span) + } else { + None + } +} + +fn pat_is_not_exhaustive_heuristic(pat: &hir::Pat<'_>) -> Option<(Span, &'static str)> { + match pat.kind { + hir::PatKind::Missing => None, + hir::PatKind::Wild => Some((pat.span, "because of this wildcard pattern")), + hir::PatKind::Binding(_, _, _, Some(pat)) => pat_is_not_exhaustive_heuristic(pat), + hir::PatKind::Binding(..) => Some((pat.span, "because of this variable binding")), + hir::PatKind::Struct(..) => None, + hir::PatKind::TupleStruct(..) => None, + hir::PatKind::Or(..) => None, + hir::PatKind::Never => None, + hir::PatKind::Tuple(..) => None, + hir::PatKind::Box(pat) => pat_is_not_exhaustive_heuristic(&*pat), + hir::PatKind::Deref(pat) => pat_is_not_exhaustive_heuristic(&*pat), + hir::PatKind::Ref(pat, _, _) => pat_is_not_exhaustive_heuristic(&*pat), + hir::PatKind::Expr(..) => None, + hir::PatKind::Guard(..) => None, + hir::PatKind::Range(..) => None, + hir::PatKind::Slice(..) => None, + hir::PatKind::Err(..) => None, + } +} + +impl<'tcx> LateLintPass<'tcx> for RustcMustMatchExhaustively { + fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &hir::Expr<'_>) { + match expr.kind { + // This is not perfect exhaustiveness checking, that's why this is just a rustc internal + // attribute. But it catches most reasonable cases + hir::ExprKind::Match(expr, arms, _) => { + if let Some(attr_span) = is_rustc_must_match_exhaustively(cx, expr.hir_id) { + for arm in arms { + if let Some((span, message)) = pat_is_not_exhaustive_heuristic(arm.pat) { + cx.emit_span_lint( + RUSTC_MUST_MATCH_EXHAUSTIVELY, + expr.span, + RustcMustMatchExhaustivelyNotExhaustive { + attr_span, + pat_span: span, + message, + }, + ); + } + } + } + } + hir::ExprKind::Let(expr, ..) => { + if let Some(attr_span) = is_rustc_must_match_exhaustively(cx, expr.init.hir_id) { + cx.emit_span_lint( + RUSTC_MUST_MATCH_EXHAUSTIVELY, + expr.span, + RustcMustMatchExhaustivelyNotExhaustive { + attr_span, + pat_span: expr.span, + message: "using `if let` only matches on one variant (try using `match`)", + }, + ); + } + } + _ => {} + } + } + + fn check_stmt(&mut self, cx: &LateContext<'tcx>, stmt: &'tcx rustc_hir::Stmt<'tcx>) { + match stmt.kind { + rustc_hir::StmtKind::Let(let_stmt) => { + if let_stmt.els.is_some() + && let Some(attr_span) = + is_rustc_must_match_exhaustively(cx, let_stmt.pat.hir_id) + { + cx.emit_span_lint( + RUSTC_MUST_MATCH_EXHAUSTIVELY, + let_stmt.span, + RustcMustMatchExhaustivelyNotExhaustive { + attr_span, + pat_span: let_stmt.pat.span, + message: "using `let else` only matches on one variant (try using `match`)", + }, + ); + } + } + _ => {} + } + } +} diff --git a/compiler/rustc_lint/src/levels.rs b/compiler/rustc_lint/src/levels.rs index 12c5748d5ecd..2b859b65c9f8 100644 --- a/compiler/rustc_lint/src/levels.rs +++ b/compiler/rustc_lint/src/levels.rs @@ -1,13 +1,13 @@ use rustc_ast as ast; -use rustc_ast::{DUMMY_NODE_ID, NodeId}; -use rustc_attr_parsing::AttributeParser; +use rustc_ast::attr::AttributeExt; +use rustc_ast_pretty::pprust; use rustc_data_structures::fx::{FxHashSet, FxIndexMap}; use rustc_data_structures::unord::UnordSet; use rustc_errors::{Diag, DiagCtxtHandle, Diagnostic, MultiSpan, msg}; use rustc_feature::{Features, GateIssue}; -use rustc_hir::attrs::{LintAttribute, LintAttributeKind, LintInstance}; +use rustc_hir as hir; +use rustc_hir::HirId; use rustc_hir::intravisit::{self, Visitor}; -use rustc_hir::{self as hir, HirId, Target, find_attr}; use rustc_index::IndexVec; use rustc_middle::bug; use rustc_middle::hir::nested_filter; @@ -20,37 +20,26 @@ use rustc_session::Session; use rustc_session::lint::builtin::{ self, FORBIDDEN_LINT_GROUPS, RENAMED_AND_REMOVED_LINTS, SINGLE_USE_LIFETIMES, - UNFULFILLED_LINT_EXPECTATIONS, UNKNOWN_LINTS, -}; -use rustc_session::lint::{ - CheckLintNameResult, Level, Lint, LintExpectationId, LintId, TargetLint, + UNFULFILLED_LINT_EXPECTATIONS, UNKNOWN_LINTS, UNUSED_ATTRIBUTES, }; +use rustc_session::lint::{Level, Lint, LintExpectationId, LintId}; use rustc_span::{DUMMY_SP, Span, Symbol, sym}; use tracing::{debug, instrument}; use crate::builtin::MISSING_DOCS; -use crate::context::LintStore; +use crate::context::{CheckLintNameResult, LintStore}; use crate::errors::{ - CheckNameUnknownTool, OverruledAttribute, OverruledAttributeSub, RequestedLevel, - UnsupportedGroup, + CheckNameUnknownTool, MalformedAttribute, MalformedAttributeSub, OverruledAttribute, + OverruledAttributeSub, RequestedLevel, UnknownToolInScopedLint, UnsupportedGroup, }; use crate::late::unerased_lint_store; use crate::lints::{ - DeprecatedLintNameFromCommandLine, OverruledAttributeLint, RemovedLintFromCommandLine, - RenamedLintFromCommandLine, RenamedLintSuggestion, UnknownLintFromCommandLine, + DeprecatedLintName, DeprecatedLintNameFromCommandLine, IgnoredUnlessCrateSpecified, + OverruledAttributeLint, RemovedLint, RemovedLintFromCommandLine, RenamedLint, + RenamedLintFromCommandLine, RenamedLintSuggestion, UnknownLint, UnknownLintFromCommandLine, UnknownLintSuggestion, }; -const ALLOW_LISTED_ATTRS: &[Symbol] = &[ - sym::allow, - sym::deny, - sym::expect, - sym::forbid, - sym::warn, - sym::automatically_derived, - sym::doc, -]; - /// Collection of lint levels for the whole crate. /// This is used by AST-based lints, which do not /// wait until we have built HIR to be emitted. @@ -277,7 +266,11 @@ fn push_expectation(&mut self, id: LintExpectationId, expectation: LintExpectati impl<'tcx> LintLevelsBuilder<'_, LintLevelQueryMap<'tcx>> { fn add_id(&mut self, hir_id: HirId) { self.provider.cur = hir_id; - self.add(self.provider.attrs.get(hir_id.local_id), Some(hir_id)); + self.add( + self.provider.attrs.get(hir_id.local_id), + hir_id == hir::CRATE_HIR_ID, + Some(hir_id), + ); } } @@ -397,19 +390,7 @@ pub fn crate_root( crate_attrs: &[ast::Attribute], ) -> Self { let mut builder = Self::new(sess, features, lint_added_lints, store, registered_tools); - let parsed_crate_attrs = AttributeParser::parse_limited_all_filtered( - sess, - crate_attrs, - ALLOW_LISTED_ATTRS, - Target::Crate, - DUMMY_SP, - DUMMY_NODE_ID, - Some(features), - rustc_attr_parsing::ShouldEmit::Nothing, - registered_tools, - ); - - builder.add(&parsed_crate_attrs, None); + builder.add(crate_attrs, true, None); builder } @@ -439,31 +420,18 @@ fn process_command_line(&mut self) { pub(crate) fn push( &mut self, attrs: &[ast::Attribute], - node_id: NodeId, - target_span: Span, + is_crate_node: bool, + source_hir_id: Option, ) -> BuilderPush { let prev = self.provider.cur; self.provider.cur = self.provider.sets.list.push(LintSet { specs: FxIndexMap::default(), parent: prev }); - if !attrs.is_empty() { - let attrs = AttributeParser::parse_limited_all_filtered( - self.sess, - attrs, - ALLOW_LISTED_ATTRS, - Target::Fn, - target_span, - node_id, - Some(self.features), - rustc_attr_parsing::ShouldEmit::Nothing, - self.registered_tools, - ); - self.add(&attrs, None); + self.add(attrs, is_crate_node, source_hir_id); - if self.provider.current_specs().is_empty() { - self.provider.sets.list.pop(); - self.provider.cur = prev; - } + if self.provider.current_specs().is_empty() { + self.provider.sets.list.pop(); + self.provider.cur = prev; } BuilderPush { prev } @@ -510,7 +478,7 @@ fn add_command_line(&mut self) { .emit_err(UnsupportedGroup { lint_group: crate::WARNINGS.name_lower() }); } match self.store.check_lint_name(lint_name_only, tool_name, self.registered_tools) { - CheckLintNameResult::Renamed(replace) => { + CheckLintNameResult::Renamed(ref replace) => { let name = lint_name.as_str(); let suggestion = RenamedLintSuggestion::WithoutSpan { replace }; let requested_level = RequestedLevel { level, lint_name }; @@ -670,102 +638,297 @@ fn insert_spec(&mut self, id: LintId, LevelAndSource { level, lint_id, src }: Le }; } - fn simple_add( + fn add( &mut self, - level: Level, - lint: &LintInstance, - reason: Option, - expect_lint_id: Option, + attrs: &[impl AttributeExt], + is_crate_node: bool, + source_hir_id: Option, ) { - // If this function returns none, it means the attribute parser has already emitted appropriate errors + let sess = self.sess; + for (attr_index, attr) in attrs.iter().enumerate() { + if attr.is_automatically_derived_attr() { + self.insert( + LintId::of(SINGLE_USE_LIFETIMES), + LevelAndSource { + level: Level::Allow, + lint_id: None, + src: LintLevelSource::Default, + }, + ); + continue; + } - let src = - LintLevelSource::Node { name: lint.original_lint_name(), span: lint.span(), reason }; + // `#[doc(hidden)]` disables missing_docs check. + if attr.is_doc_hidden() { + self.insert( + LintId::of(MISSING_DOCS), + LevelAndSource { + level: Level::Allow, + lint_id: None, + src: LintLevelSource::Default, + }, + ); + continue; + } - let id = match self.store.get_lint_by_name(lint.full_lint().as_str()) { - Some(TargetLint::Id(id)) => id, - None | Some(_) => bug!( - "guaranteed to find id due to previous parsing, happened while parsing {:?}", - lint, - ), - }; + let (level, lint_id) = match Level::from_attr(attr) { + None => continue, + // This is the only lint level with a `LintExpectationId` that can be created from + // an attribute. + Some((Level::Expect, Some(unstable_id))) if let Some(hir_id) = source_hir_id => { + let LintExpectationId::Unstable { lint_index: None, attr_id: _ } = unstable_id + else { + bug!("stable id Level::from_attr") + }; - if self.check_gated_lint(*id, lint.span(), false) { - self.insert_spec(*id, LevelAndSource { level, lint_id: expect_lint_id, src }); - } - } + let stable_id = LintExpectationId::Stable { + hir_id, + attr_index: attr_index.try_into().unwrap(), + lint_index: None, + }; - fn add(&mut self, attrs: &[hir::Attribute], source_hir_id: Option) { - if find_attr!(attrs, AutomaticallyDerived(..)) { - self.insert( - LintId::of(SINGLE_USE_LIFETIMES), - LevelAndSource { - level: Level::Allow, - lint_id: None, - src: LintLevelSource::Default, - }, - ); - } - // `#[doc(hidden)]` disables missing_docs check. - if find_attr!(attrs, Doc(d) if d.hidden.is_some()) { - self.insert( - LintId::of(MISSING_DOCS), - LevelAndSource { - level: Level::Allow, - lint_id: None, - src: LintLevelSource::Default, - }, - ); - } + (Level::Expect, Some(stable_id)) + } + Some((lvl, id)) => (lvl, id), + }; - let Some(attrs) = find_attr!(attrs, LintAttributes(sub_attrs) => sub_attrs.into_iter()) - else { - return; - }; + let Some(mut metas) = attr.meta_item_list() else { continue }; - for (attr_index, LintAttribute { reason, lint_instances, attr_id, kind, .. }) in - attrs.enumerate() - { - let attr_id = attr_id.attr_id; - let level = match kind { - LintAttributeKind::Allow => Level::Allow, - LintAttributeKind::Deny => Level::Deny, - LintAttributeKind::Forbid => Level::Forbid, - LintAttributeKind::Warn => Level::Warn, - LintAttributeKind::Expect => { - for lint in lint_instances { - let lint_index = lint.lint_index().try_into().unwrap(); - let attr_index = attr_index.try_into().unwrap(); - let expectation_id = match source_hir_id { - None => LintExpectationId::Unstable { attr_id, lint_index }, - Some(hir_id) => LintExpectationId::Stable { - hir_id, - attr_id, - lint_index, - attr_index, - }, + // Check whether `metas` is empty, and get its last element. + let Some(tail_li) = metas.last() else { + // This emits the unused_attributes lint for `#[level()]` + continue; + }; + + // Before processing the lint names, look for a reason (RFC 2383) + // at the end. + let mut reason = None; + if let Some(item) = tail_li.meta_item() { + match item.kind { + ast::MetaItemKind::Word => {} // actual lint names handled later + ast::MetaItemKind::NameValue(ref name_value) => { + if item.path == sym::reason { + if let ast::LitKind::Str(rationale, _) = name_value.kind { + reason = Some(rationale); + } else { + sess.dcx().emit_err(MalformedAttribute { + span: name_value.span, + sub: MalformedAttributeSub::ReasonMustBeStringLiteral( + name_value.span, + ), + }); + } + // found reason, reslice meta list to exclude it + metas.pop().unwrap(); + } else { + sess.dcx().emit_err(MalformedAttribute { + span: item.span, + sub: MalformedAttributeSub::BadAttributeArgument(item.span), + }); + } + } + ast::MetaItemKind::List(_) => { + sess.dcx().emit_err(MalformedAttribute { + span: item.span, + sub: MalformedAttributeSub::BadAttributeArgument(item.span), + }); + } + } + } + + for (lint_index, li) in metas.iter_mut().enumerate() { + let mut lint_id = lint_id; + if let Some(id) = &mut lint_id { + id.set_lint_index(Some(lint_index as u16)); + } + + let sp = li.span(); + let meta_item = match li { + ast::MetaItemInner::MetaItem(meta_item) if meta_item.is_word() => meta_item, + _ => { + let sub = if let Some(item) = li.meta_item() + && let ast::MetaItemKind::NameValue(_) = item.kind + && item.path == sym::reason + { + MalformedAttributeSub::ReasonMustComeLast(sp) + } else { + MalformedAttributeSub::BadAttributeArgument(sp) }; - self.simple_add(Level::Expect, lint, *reason, Some(expectation_id)); + sess.dcx().emit_err(MalformedAttribute { span: sp, sub }); + continue; + } + }; + let tool_ident = if meta_item.path.segments.len() > 1 { + Some(meta_item.path.segments.remove(0).ident) + } else { + None + }; + let tool_name = tool_ident.map(|ident| ident.name); + let name = pprust::path_to_string(&meta_item.path); + let lint_result = + self.store.check_lint_name(&name, tool_name, self.registered_tools); - let is_unfulfilled_lint_expectations = - lint.lint_name().as_str() == UNFULFILLED_LINT_EXPECTATIONS.name_lower(); - self.provider.push_expectation( - expectation_id, - LintExpectation::new( - *reason, - lint.span(), - is_unfulfilled_lint_expectations, - lint.tool_name(), - ), - ); + let (ids, name) = match lint_result { + CheckLintNameResult::Ok(ids) => { + let name = + meta_item.path.segments.last().expect("empty lint name").ident.name; + (ids, name) } + CheckLintNameResult::Tool(ids, new_lint_name) => { + let name = match new_lint_name { + None => { + let complete_name = + &format!("{}::{}", tool_ident.unwrap().name, name); + Symbol::intern(complete_name) + } + Some(new_lint_name) => { + self.emit_span_lint( + builtin::RENAMED_AND_REMOVED_LINTS, + sp.into(), + DeprecatedLintName { + name, + suggestion: sp, + replace: &new_lint_name, + }, + ); + Symbol::intern(&new_lint_name) + } + }; + (ids, name) + } + + CheckLintNameResult::MissingTool => { + // If `MissingTool` is returned, then either the lint does not + // exist in the tool or the code was not compiled with the tool and + // therefore the lint was never added to the `LintStore`. To detect + // this is the responsibility of the lint tool. + continue; + } + + CheckLintNameResult::NoTool => { + sess.dcx().emit_err(UnknownToolInScopedLint { + span: tool_ident.map(|ident| ident.span), + tool_name: tool_name.unwrap(), + lint_name: pprust::path_to_string(&meta_item.path), + is_nightly_build: sess.is_nightly_build(), + }); + continue; + } + + CheckLintNameResult::Renamed(ref replace) => { + if self.lint_added_lints { + let suggestion = + RenamedLintSuggestion::WithSpan { suggestion: sp, replace }; + let name = + tool_ident.map(|tool| format!("{tool}::{name}")).unwrap_or(name); + self.emit_span_lint( + RENAMED_AND_REMOVED_LINTS, + sp.into(), + RenamedLint { name: name.as_str(), replace, suggestion }, + ); + } + + // If this lint was renamed, apply the new lint instead of ignoring the + // attribute. Ignore any errors or warnings that happen because the new + // name is inaccurate. + // NOTE: `new_name` already includes the tool name, so we don't + // have to add it again. + let CheckLintNameResult::Ok(ids) = + self.store.check_lint_name(replace, None, self.registered_tools) + else { + panic!("renamed lint does not exist: {replace}"); + }; + + (ids, Symbol::intern(&replace)) + } + + CheckLintNameResult::Removed(ref reason) => { + if self.lint_added_lints { + let name = + tool_ident.map(|tool| format!("{tool}::{name}")).unwrap_or(name); + self.emit_span_lint( + RENAMED_AND_REMOVED_LINTS, + sp.into(), + RemovedLint { name: name.as_str(), reason }, + ); + } + continue; + } + + CheckLintNameResult::NoLint(suggestion) => { + if self.lint_added_lints { + let name = + tool_ident.map(|tool| format!("{tool}::{name}")).unwrap_or(name); + let suggestion = suggestion.map(|(replace, from_rustc)| { + UnknownLintSuggestion::WithSpan { + suggestion: sp, + replace, + from_rustc, + } + }); + self.emit_span_lint( + UNKNOWN_LINTS, + sp.into(), + UnknownLint { name, suggestion }, + ); + } + continue; + } + }; + + let src = LintLevelSource::Node { name, span: sp, reason }; + for &id in ids { + if self.check_gated_lint(id, sp, false) { + self.insert_spec(id, LevelAndSource { level, lint_id, src }); + } + } + + // This checks for instances where the user writes + // `#[expect(unfulfilled_lint_expectations)]` in that case we want to avoid + // overriding the lint level but instead add an expectation that can't be + // fulfilled. The lint message will include an explanation, that the + // `unfulfilled_lint_expectations` lint can't be expected. + if let (Level::Expect, Some(expect_id)) = (level, lint_id) { + // The `unfulfilled_lint_expectations` lint is not part of any lint + // groups. Therefore. we only need to check the slice if it contains a + // single lint. + let is_unfulfilled_lint_expectations = match ids { + [lint] => *lint == LintId::of(UNFULFILLED_LINT_EXPECTATIONS), + _ => false, + }; + self.provider.push_expectation( + expect_id, + LintExpectation::new( + reason, + sp, + is_unfulfilled_lint_expectations, + tool_name, + ), + ); + } + } + } + + if self.lint_added_lints && !is_crate_node { + for (id, &LevelAndSource { level, ref src, .. }) in self.current_specs().iter() { + if !id.lint.crate_level_only { continue; } - }; - for lint in lint_instances { - self.simple_add(level, lint, *reason, None); + + let LintLevelSource::Node { name: lint_attr_name, span: lint_attr_span, .. } = *src + else { + continue; + }; + + self.emit_span_lint( + UNUSED_ATTRIBUTES, + lint_attr_span.into(), + IgnoredUnlessCrateSpecified { level: level.as_str(), name: lint_attr_name }, + ); + // don't set a separate error for every lint in the group + break; } } } diff --git a/compiler/rustc_lint/src/lib.rs b/compiler/rustc_lint/src/lib.rs index 6f6aa0f96e75..9fa550143345 100644 --- a/compiler/rustc_lint/src/lib.rs +++ b/compiler/rustc_lint/src/lib.rs @@ -128,7 +128,7 @@ #[rustfmt::skip] pub use builtin::{MissingDoc, SoftLints}; -pub use context::{EarlyContext, LateContext, LintContext, LintStore}; +pub use context::{CheckLintNameResult, EarlyContext, LateContext, LintContext, LintStore}; pub use early::diagnostics::{DecorateAttrLint, DiagAndSess}; pub use early::{EarlyCheckNode, check_ast_node}; pub use late::{check_crate, late_lint_mod, unerased_lint_store}; @@ -136,9 +136,7 @@ pub use passes::{EarlyLintPass, LateLintPass}; pub use rustc_errors::BufferedEarlyLint; pub use rustc_session::lint::Level::{self, *}; -pub use rustc_session::lint::{ - CheckLintNameResult, FutureIncompatibleInfo, Lint, LintId, LintPass, LintVec, -}; +pub use rustc_session::lint::{FutureIncompatibleInfo, Lint, LintId, LintPass, LintVec}; pub fn provide(providers: &mut Providers) { levels::provide(providers); @@ -670,6 +668,8 @@ fn register_internals(store: &mut LintStore) { store.register_early_pass(|| Box::new(ImplicitSysrootCrateImport)); store.register_lints(&BadUseOfFindAttr::lint_vec()); store.register_early_pass(|| Box::new(BadUseOfFindAttr)); + store.register_lints(&RustcMustMatchExhaustively::lint_vec()); + store.register_late_pass(|_| Box::new(RustcMustMatchExhaustively)); store.register_group( false, "rustc::internal", @@ -690,6 +690,7 @@ fn register_internals(store: &mut LintStore) { LintId::of(DIRECT_USE_OF_RUSTC_TYPE_IR), LintId::of(IMPLICIT_SYSROOT_CRATE_IMPORT), LintId::of(BAD_USE_OF_FIND_ATTR), + LintId::of(RUSTC_MUST_MATCH_EXHAUSTIVELY), ], ); } diff --git a/compiler/rustc_lint/src/lints.rs b/compiler/rustc_lint/src/lints.rs index f52b90382d95..20d88505f042 100644 --- a/compiler/rustc_lint/src/lints.rs +++ b/compiler/rustc_lint/src/lints.rs @@ -1162,6 +1162,18 @@ pub(crate) struct ImplicitSysrootCrateImportDiag<'a> { #[help("remove `AttributeKind`")] pub(crate) struct AttributeKindInFindAttr; +#[derive(Diagnostic)] +#[diag("match is not exhaustive")] +#[help("explicitly list all variants of the enum in a `match`")] +pub(crate) struct RustcMustMatchExhaustivelyNotExhaustive { + #[label("required because of this attribute")] + pub attr_span: Span, + + #[note("{$message}")] + pub pat_span: Span, + pub message: &'static str, +} + // let_underscore.rs #[derive(Diagnostic)] pub(crate) enum NonBindingLet { @@ -1238,11 +1250,11 @@ pub(crate) struct OverruledAttributeLint<'a> { #[derive(Diagnostic)] #[diag("lint name `{$name}` is deprecated and may not have an effect in the future")] -pub(crate) struct DeprecatedLintName { - pub name: Symbol, +pub(crate) struct DeprecatedLintName<'a> { + pub name: String, #[suggestion("change it to", code = "{replace}", applicability = "machine-applicable")] pub suggestion: Span, - pub replace: Symbol, + pub replace: &'a str, } #[derive(Diagnostic)] @@ -1257,32 +1269,32 @@ pub(crate) struct DeprecatedLintNameFromCommandLine<'a> { #[derive(Diagnostic)] #[diag("lint `{$name}` has been renamed to `{$replace}`")] -pub(crate) struct RenamedLint { - pub name: Symbol, - pub replace: Symbol, +pub(crate) struct RenamedLint<'a> { + pub name: &'a str, + pub replace: &'a str, #[subdiagnostic] - pub suggestion: RenamedLintSuggestion, + pub suggestion: RenamedLintSuggestion<'a>, } #[derive(Subdiagnostic)] -pub(crate) enum RenamedLintSuggestion { +pub(crate) enum RenamedLintSuggestion<'a> { #[suggestion("use the new name", code = "{replace}", applicability = "machine-applicable")] WithSpan { #[primary_span] suggestion: Span, - replace: Symbol, + replace: &'a str, }, #[help("use the new name `{$replace}`")] - WithoutSpan { replace: Symbol }, + WithoutSpan { replace: &'a str }, } #[derive(Diagnostic)] #[diag("lint `{$name}` has been renamed to `{$replace}`")] pub(crate) struct RenamedLintFromCommandLine<'a> { pub name: &'a str, - pub replace: Symbol, + pub replace: &'a str, #[subdiagnostic] - pub suggestion: RenamedLintSuggestion, + pub suggestion: RenamedLintSuggestion<'a>, #[subdiagnostic] pub requested_level: RequestedLevel<'a>, } @@ -1290,7 +1302,7 @@ pub(crate) struct RenamedLintFromCommandLine<'a> { #[derive(Diagnostic)] #[diag("lint `{$name}` has been removed: {$reason}")] pub(crate) struct RemovedLint<'a> { - pub name: Symbol, + pub name: &'a str, pub reason: &'a str, } @@ -1306,7 +1318,7 @@ pub(crate) struct RemovedLintFromCommandLine<'a> { #[derive(Diagnostic)] #[diag("unknown lint: `{$name}`")] pub(crate) struct UnknownLint { - pub name: Symbol, + pub name: String, #[subdiagnostic] pub suggestion: Option, } @@ -1348,8 +1360,8 @@ pub(crate) struct UnknownLintFromCommandLine<'a> { #[derive(Diagnostic)] #[diag("{$level}({$name}) is ignored unless specified at crate level")] -pub(crate) struct IgnoredUnlessCrateSpecified { - pub level: Symbol, +pub(crate) struct IgnoredUnlessCrateSpecified<'a> { + pub level: &'a str, pub name: Symbol, } @@ -3353,19 +3365,6 @@ pub(crate) struct InvalidAttrStyle { pub target: &'static str, } -#[derive(Diagnostic)] -#[diag("unused attribute")] -pub(crate) struct UnusedDuplicate { - #[suggestion("remove this attribute", code = "", applicability = "machine-applicable")] - pub this: Span, - #[note("attribute also specified here")] - pub other: Span, - #[warning( - "this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!" - )] - pub warning: bool, -} - #[derive(Diagnostic)] #[diag("malformed `doc` attribute input")] #[warning( @@ -3387,24 +3386,6 @@ pub(crate) struct UnusedDuplicate { )] pub(crate) struct ExpectedNameValue; -#[derive(Diagnostic)] -#[diag("unsafe attribute used without unsafe")] -pub(crate) struct UnsafeAttrOutsideUnsafeLint { - #[label("usage of unsafe attribute")] - pub span: Span, - #[subdiagnostic] - pub suggestion: Option, -} - -#[derive(Subdiagnostic)] -#[multipart_suggestion("wrap the attribute in `unsafe(...)`", applicability = "machine-applicable")] -pub(crate) struct UnsafeAttrOutsideUnsafeSuggestion { - #[suggestion_part(code = "unsafe(")] - pub left: Span, - #[suggestion_part(code = ")")] - pub right: Span, -} - #[derive(Diagnostic)] #[diag("doc alias is duplicated")] pub(crate) struct DocAliasDuplicated { @@ -3542,6 +3523,11 @@ pub(crate) struct UnknownCrateTypesSuggestion { )] pub(crate) struct DisallowedPositionalArgument; +#[derive(Diagnostic)] +#[diag("format arguments are not allowed here")] +#[help("consider removing this format argument")] +pub(crate) struct DisallowedPlaceholder; + #[derive(Diagnostic)] #[diag("invalid format specifier")] #[help("no format specifier are supported in this position")] @@ -3567,34 +3553,11 @@ pub(crate) struct IgnoredDiagnosticOption { } #[derive(Diagnostic)] -#[diag("missing options for `on_unimplemented` attribute")] -#[help("at least one of the `message`, `note` and `label` options are expected")] -pub(crate) struct MissingOptionsForOnUnimplementedAttr; - -#[derive(Diagnostic)] -#[diag("missing options for `on_const` attribute")] -#[help("at least one of the `message`, `note` and `label` options are expected")] -pub(crate) struct MissingOptionsForOnConstAttr; - -#[derive(Diagnostic)] -#[diag("missing options for `on_move` attribute")] -#[help("at least one of the `message`, `note` and `label` options are expected")] -pub(crate) struct MissingOptionsForOnMoveAttr; - -#[derive(Diagnostic)] -#[diag("malformed `on_unimplemented` attribute")] -#[help("only `message`, `note` and `label` are allowed as options")] -pub(crate) struct MalformedOnUnimplementedAttrLint { - #[label("invalid option found here")] - pub span: Span, -} - -#[derive(Diagnostic)] -#[diag("malformed `on_const` attribute")] -#[help("only `message`, `note` and `label` are allowed as options")] -pub(crate) struct MalformedOnConstAttrLint { - #[label("invalid option found here")] - pub span: Span, +#[diag("missing options for `{$attribute}` attribute")] +#[help("{$options}")] +pub(crate) struct MissingOptionsForDiagnosticAttribute { + pub attribute: &'static str, + pub options: &'static str, } #[derive(Diagnostic)] @@ -3602,26 +3565,19 @@ pub(crate) struct MalformedOnConstAttrLint { #[note("this method was used to add checks to the `Eq` derive macro")] pub(crate) struct EqInternalMethodImplemented; -#[derive(Diagnostic)] -#[diag("unknown or malformed `on_move` attribute")] -#[help( - "only `message`, `note` and `label` are allowed as options. Their values must be string literals" -)] -pub(crate) struct MalformedOnMoveAttrLint { - #[label("invalid option found here")] - pub span: Span, -} - -#[derive(Diagnostic)] -#[diag("unknown parameter `{$name}`")] -#[help("expect `Self` as format argument")] -pub(crate) struct OnMoveMalformedFormatLiterals { - pub name: Symbol, -} - #[derive(Diagnostic)] #[diag("expected a literal or missing delimiter")] #[help( "only literals are allowed as values for the `message`, `note` and `label` options. These options must be separated by a comma" )] -pub(crate) struct OnMoveMalformedAttrExpectedLiteralOrDelimiter; +pub(crate) struct NonMetaItemDiagnosticAttribute; + +#[derive(Diagnostic)] +#[diag("malformed `{$attribute}` attribute")] +#[help("{$options}")] +pub(crate) struct MalFormedDiagnosticAttributeLint { + pub attribute: &'static str, + pub options: &'static str, + #[label("invalid option found here")] + pub span: Span, +} diff --git a/compiler/rustc_lint/src/multiple_supertrait_upcastable.rs b/compiler/rustc_lint/src/multiple_supertrait_upcastable.rs index 93f067d09833..9177e00d902c 100644 --- a/compiler/rustc_lint/src/multiple_supertrait_upcastable.rs +++ b/compiler/rustc_lint/src/multiple_supertrait_upcastable.rs @@ -39,7 +39,7 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx hir::Item<'tcx>) { let def_id = item.owner_id.to_def_id(); // NOTE(nbdd0121): use `dyn_compatibility_violations` instead of `is_dyn_compatible` because // the latter will report `where_clause_object_safety` lint. - if let hir::ItemKind::Trait(_, _, _, ident, ..) = item.kind + if let hir::ItemKind::Trait(_, _, _, _, ident, ..) = item.kind && cx.tcx.is_dyn_compatible(def_id) { let direct_super_traits_iter = cx diff --git a/compiler/rustc_lint/src/nonstandard_style.rs b/compiler/rustc_lint/src/nonstandard_style.rs index 1fd6699e2506..f5f057c9f3ec 100644 --- a/compiler/rustc_lint/src/nonstandard_style.rs +++ b/compiler/rustc_lint/src/nonstandard_style.rs @@ -145,7 +145,7 @@ fn check_case(&self, cx: &EarlyContext<'_>, sort: &str, ident: &Ident) { impl EarlyLintPass for NonCamelCaseTypes { fn check_item(&mut self, cx: &EarlyContext<'_>, it: &ast::Item) { let has_repr_c = matches!( - AttributeParser::parse_limited(cx.sess(), &it.attrs, sym::repr, it.span, it.id, None), + AttributeParser::parse_limited(cx.sess(), &it.attrs, &[sym::repr]), Some(Attribute::Parsed(AttributeKind::Repr { reprs, ..})) if reprs.iter().any(|(r, _)| r == &ReprAttr::ReprC) ); diff --git a/compiler/rustc_lint/src/types/improper_ctypes.rs b/compiler/rustc_lint/src/types/improper_ctypes.rs index 38f2fbb07ed3..c40acbe07b83 100644 --- a/compiler/rustc_lint/src/types/improper_ctypes.rs +++ b/compiler/rustc_lint/src/types/improper_ctypes.rs @@ -138,6 +138,17 @@ USES_POWER_ALIGNMENT ]); +/// Getting the (normalized) type out of a field (for, e.g., an enum variant or a tuple). +#[inline] +fn get_type_from_field<'tcx>( + cx: &LateContext<'tcx>, + field: &ty::FieldDef, + args: GenericArgsRef<'tcx>, +) -> Ty<'tcx> { + let field_ty = field.ty(cx.tcx, args); + cx.tcx.try_normalize_erasing_regions(cx.typing_env(), field_ty).unwrap_or(field_ty) +} + /// Check a variant of a non-exhaustive enum for improper ctypes /// /// We treat `#[non_exhaustive] enum` as "ensure that code will compile if new variants are added". @@ -365,22 +376,6 @@ fn new(cx: &'a LateContext<'tcx>, base_ty: Ty<'tcx>, base_fn_mode: CItemKind) -> Self { cx, base_ty, base_fn_mode, cache: FxHashSet::default() } } - /// Checks if the given field's type is "ffi-safe". - fn check_field_type_for_ffi( - &mut self, - state: VisitorState, - field: &ty::FieldDef, - args: GenericArgsRef<'tcx>, - ) -> FfiResult<'tcx> { - let field_ty = field.ty(self.cx.tcx, args); - let field_ty = self - .cx - .tcx - .try_normalize_erasing_regions(self.cx.typing_env(), field_ty) - .unwrap_or(field_ty); - self.visit_type(state, field_ty) - } - /// Checks if the given `VariantDef`'s field types are "ffi-safe". fn check_variant_for_ffi( &mut self, @@ -394,7 +389,8 @@ fn check_variant_for_ffi( let transparent_with_all_zst_fields = if def.repr().transparent() { if let Some(field) = super::transparent_newtype_field(self.cx.tcx, variant) { // Transparent newtypes have at most one non-ZST field which needs to be checked.. - match self.check_field_type_for_ffi(state, field, args) { + let field_ty = get_type_from_field(self.cx, field, args); + match self.visit_type(state, field_ty) { FfiUnsafe { ty, .. } if ty.is_unit() => (), r => return r, } @@ -412,7 +408,8 @@ fn check_variant_for_ffi( // We can't completely trust `repr(C)` markings, so make sure the fields are actually safe. let mut all_phantom = !variant.fields.is_empty(); for field in &variant.fields { - all_phantom &= match self.check_field_type_for_ffi(state, field, args) { + let field_ty = get_type_from_field(self.cx, field, args); + all_phantom &= match self.visit_type(state, field_ty) { FfiSafe => false, // `()` fields are FFI-safe! FfiUnsafe { ty, .. } if ty.is_unit() => false, @@ -723,22 +720,11 @@ fn visit_ty(&mut self, ty: Ty<'tcx>) -> Self::Result { } } - if let Some(ty) = self - .cx - .tcx - .try_normalize_erasing_regions(self.cx.typing_env(), ty) - .unwrap_or(ty) - .visit_with(&mut ProhibitOpaqueTypes) - .break_value() - { - Some(FfiResult::FfiUnsafe { - ty, - reason: msg!("opaque types have no C equivalent"), - help: None, - }) - } else { - None - } + ty.visit_with(&mut ProhibitOpaqueTypes).break_value().map(|ty| FfiResult::FfiUnsafe { + ty, + reason: msg!("opaque types have no C equivalent"), + help: None, + }) } /// Check if the type is array and emit an unsafe type lint. @@ -756,12 +742,11 @@ fn check_for_array_ty(&mut self, ty: Ty<'tcx>) -> PartialFfiResult<'tcx> { /// Determine the FFI-safety of a single (MIR) type, given the context of how it is used. fn check_type(&mut self, state: VisitorState, ty: Ty<'tcx>) -> FfiResult<'tcx> { + let ty = self.cx.tcx.try_normalize_erasing_regions(self.cx.typing_env(), ty).unwrap_or(ty); if let Some(res) = self.visit_for_opaque_ty(ty) { return res; } - let ty = self.cx.tcx.try_normalize_erasing_regions(self.cx.typing_env(), ty).unwrap_or(ty); - // C doesn't really support passing arrays by value - the only way to pass an array by value // is through a struct. So, first test that the top level isn't an array, and then // recursively check the types inside. @@ -816,7 +801,7 @@ impl<'tcx> ty::TypeVisitor> for FnPtrFinder<'tcx> { fn visit_ty(&mut self, ty: Ty<'tcx>) -> Self::Result { if let ty::FnPtr(_, hdr) = ty.kind() - && !hdr.abi.is_rustic_abi() + && !hdr.abi().is_rustic_abi() { self.tys.push(ty); } diff --git a/compiler/rustc_lint_defs/Cargo.toml b/compiler/rustc_lint_defs/Cargo.toml index 2ca62f7fa8cd..c8201d5ea8cc 100644 --- a/compiler/rustc_lint_defs/Cargo.toml +++ b/compiler/rustc_lint_defs/Cargo.toml @@ -5,6 +5,7 @@ edition = "2024" [dependencies] # tidy-alphabetical-start +rustc_ast = { path = "../rustc_ast" } rustc_data_structures = { path = "../rustc_data_structures" } rustc_error_messages = { path = "../rustc_error_messages" } rustc_hir_id = { path = "../rustc_hir_id" } diff --git a/compiler/rustc_lint_defs/src/builtin.rs b/compiler/rustc_lint_defs/src/builtin.rs index 4aff294aeac6..2d9be11cb305 100644 --- a/compiler/rustc_lint_defs/src/builtin.rs +++ b/compiler/rustc_lint_defs/src/builtin.rs @@ -37,6 +37,7 @@ DEPENDENCY_ON_UNIT_NEVER_TYPE_FALLBACK, DEPRECATED, DEPRECATED_IN_FUTURE, + DEPRECATED_LLVM_INTRINSIC, DEPRECATED_SAFE_2024, DEPRECATED_WHERE_CLAUSE_LOCATION, DUPLICATE_FEATURES, @@ -46,6 +47,7 @@ EXPLICIT_BUILTIN_CFGS_IN_FLAGS, EXPORTED_PRIVATE_DEPENDENCIES, FFI_UNWIND_CALLS, + FLOAT_LITERAL_F32_FALLBACK, FORBIDDEN_LINT_GROUPS, FUNCTION_ITEM_REFERENCES, FUZZY_PROVENANCE_CASTS, @@ -2718,13 +2720,12 @@ /// /// ### Example /// - #[cfg_attr(bootstrap, doc = "```rust")] - #[cfg_attr(not(bootstrap), doc = "```rust,compile_fail")] + /// ```rust,compile_fail /// enum Void {} /// unsafe extern { /// static EXTERN: Void; /// } - #[doc = "```"] + /// ``` /// /// {{produces}} /// @@ -5558,7 +5559,8 @@ /// /// ### Example /// - /// ```rust + #[cfg_attr(bootstrap, doc = "```rust")] + #[cfg_attr(not(bootstrap), doc = "```rust,compile_fail")] /// // Using `...` in non-foreign function definitions is unstable, however stability is /// // currently only checked after attributes are expanded, so using `#[cfg(false)]` here will /// // allow this to compile on stable Rust. @@ -5566,7 +5568,7 @@ /// fn foo(...) { /// /// } - /// ``` + #[doc = "```"] /// /// {{produces}} /// @@ -5590,10 +5592,105 @@ /// /// [future-incompatible]: ../index.md#future-incompatible-lints pub VARARGS_WITHOUT_PATTERN, - Warn, + Deny, "detects usage of `...` arguments without a pattern in non-foreign items", @future_incompatible = FutureIncompatibleInfo { reason: fcw!(FutureReleaseError #145544), + report_in_deps: true, + }; +} + +declare_lint! { + /// The `deprecated_llvm_intrinsic` lint detects usage of deprecated LLVM intrinsics. + /// + /// ### Example + /// + /// ```rust,ignore (requires x86) + /// #![cfg(any(target_arch = "x86", target_arch = "x86_64"))] + /// #![feature(link_llvm_intrinsics, abi_unadjusted)] + /// #![deny(deprecated_llvm_intrinsic)] + /// + /// unsafe extern "unadjusted" { + /// #[link_name = "llvm.x86.addcarryx.u32"] + /// fn foo(a: u8, b: u32, c: u32, d: &mut u32) -> u8; + /// } + /// + /// #[inline(never)] + /// #[target_feature(enable = "adx")] + /// pub fn bar(a: u8, b: u32, c: u32, d: &mut u32) -> u8 { + /// unsafe { foo(a, b, c, d) } + /// } + /// ``` + /// + /// This will produce: + /// + /// ```text + /// error: Using deprecated intrinsic `llvm.x86.addcarryx.u32` + /// --> example.rs:7:5 + /// | + /// 7 | fn foo(a: u8, b: u32, c: u32, d: &mut u32) -> u8; + /// | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + /// | + /// ``` + /// + /// ### Explanation + /// + /// LLVM periodically updates its list of intrinsics. Deprecated intrinsics are unlikely + /// to be removed, but they may optimize less well than their new versions, so it's + /// best to use the new version. Also, some deprecated intrinsics might have buggy + /// behavior + pub DEPRECATED_LLVM_INTRINSIC, + Allow, + "detects uses of deprecated LLVM intrinsics", + @feature_gate = link_llvm_intrinsics; +} + +declare_lint! { + /// The `float_literal_f32_fallback` lint detects situations where the type of an unsuffixed + /// float literal falls back to `f32` instead of `f64` to avoid a compilation error. This occurs + /// when there is a trait bound `f32: From` (or equivalent, such as `T: Into`) and the + /// literal is inferred to have the same type as `T`. + /// + /// ### Example + /// + /// ```rust + /// fn foo(x: impl Into) -> f32 { + /// x.into() + /// } + /// + /// fn main() { + /// dbg!(foo(2.5)); + /// } + /// ``` + /// + /// {{produces}} + /// + /// ### Explanation + /// + /// Rust allows traits that are only implemented for a single floating point type to guide type + /// inference for floating point literals. This used to apply in the case of `f32: From` + /// (where `T` was inferred to be the same type as a floating point literal), as the only + /// floating point type impl was `f32: From`. However, as Rust is in the process of adding + /// support for `f16`, there are now two implementations for floating point types: + /// `f32: From` and `f32: From`. This means that the trait bound `f32: From` can no + /// longer guide inference for the type of the floating point literal. The default fallback for + /// unsuffixed floating point literals is `f64`. As `f32` does not implement `From`, + /// falling back to `f64` would cause a compilation error; therefore, the float type fallback + /// has been tempoarily adjusted to fallback to `f32` in this scenario. + /// + /// The lint will automatically provide a machine-applicable suggestion to add a `_f32` suffix + /// to the literal, which will fix the problem. + /// + /// This is a [future-incompatible] lint to transition this to a hard error in the future. See + /// [issue #154024] for more details. + /// + /// [issue #154024]: https://github.com/rust-lang/rust/issues/154024 + /// [future-incompatible]: ../index.md#future-incompatible-lints + pub FLOAT_LITERAL_F32_FALLBACK, + Warn, + "detects unsuffixed floating point literals whose type fallback to `f32`", + @future_incompatible = FutureIncompatibleInfo { + reason: fcw!(FutureReleaseError #154024), report_in_deps: false, }; } diff --git a/compiler/rustc_lint_defs/src/lib.rs b/compiler/rustc_lint_defs/src/lib.rs index 36070dac276f..ea5006c7f03f 100644 --- a/compiler/rustc_lint_defs/src/lib.rs +++ b/compiler/rustc_lint_defs/src/lib.rs @@ -1,6 +1,8 @@ use std::borrow::Cow; use std::fmt::Display; +use rustc_ast::AttrId; +use rustc_ast::attr::AttributeExt; use rustc_data_structures::fx::FxIndexSet; use rustc_data_structures::stable_hasher::{ HashStable, StableCompare, StableHasher, ToStableHashKey, @@ -10,7 +12,7 @@ use rustc_macros::{Decodable, Encodable, HashStable_Generic}; use rustc_span::def_id::DefPathHash; pub use rustc_span::edition::Edition; -use rustc_span::{AttrId, HashStableContext, Ident, Span, Symbol, sym}; +use rustc_span::{HashStableContext, Ident, Span, Symbol, sym}; use serde::{Deserialize, Serialize}; pub use self::Level::*; @@ -105,12 +107,12 @@ pub enum Applicability { pub enum LintExpectationId { /// Used for lints emitted during the `EarlyLintPass`. This id is not /// hash stable and should not be cached. - Unstable { attr_id: AttrId, lint_index: u16 }, + Unstable { attr_id: AttrId, lint_index: Option }, /// The [`HirId`] that the lint expectation is attached to. This id is /// stable and can be cached. The additional index ensures that nodes with /// several expectations can correctly match diagnostics to the individual /// expectation. - Stable { hir_id: HirId, attr_id: AttrId, attr_index: u16, lint_index: u16 }, + Stable { hir_id: HirId, attr_index: u16, lint_index: Option }, } impl LintExpectationId { @@ -121,14 +123,14 @@ pub fn is_stable(&self) -> bool { } } - pub fn get_lint_index(&self) -> u16 { + pub fn get_lint_index(&self) -> Option { let (LintExpectationId::Unstable { lint_index, .. } | LintExpectationId::Stable { lint_index, .. }) = self; *lint_index } - pub fn set_lint_index(&mut self, new_lint_index: u16) { + pub fn set_lint_index(&mut self, new_lint_index: Option) { let (LintExpectationId::Unstable { lint_index, .. } | LintExpectationId::Stable { lint_index, .. }) = self; @@ -140,7 +142,7 @@ impl HashStable for LintExpectationId { #[inline] fn hash_stable(&self, hcx: &mut Hcx, hasher: &mut StableHasher) { match self { - LintExpectationId::Stable { hir_id, attr_index, lint_index, .. } => { + LintExpectationId::Stable { hir_id, attr_index, lint_index: Some(lint_index) } => { hir_id.hash_stable(hcx, hasher); attr_index.hash_stable(hcx, hasher); lint_index.hash_stable(hcx, hasher); @@ -160,7 +162,7 @@ impl ToStableHashKey for LintExpectationId { #[inline] fn to_stable_hash_key(&self, hcx: &mut Hcx) -> Self::KeyType { match self { - LintExpectationId::Stable { hir_id, attr_index, lint_index, .. } => { + LintExpectationId::Stable { hir_id, attr_index, lint_index: Some(lint_index) } => { let (def_path_hash, lint_idx) = hir_id.to_stable_hash_key(hcx); (def_path_hash, lint_idx, *attr_index, *lint_index) } @@ -233,17 +235,6 @@ pub fn as_str(self) -> &'static str { } } - pub fn from_symbol(x: Symbol) -> Option { - match x { - sym::allow => Some(Level::Allow), - sym::deny => Some(Level::Deny), - sym::expect => Some(Level::Expect), - sym::forbid => Some(Level::Forbid), - sym::warn => Some(Level::Warn), - _ => None, - } - } - /// Converts a lower-case string to a level. This will never construct the expect /// level as that would require a [`LintExpectationId`]. pub fn from_str(x: &str) -> Option { @@ -256,6 +247,35 @@ pub fn from_str(x: &str) -> Option { } } + /// Converts an `Attribute` to a level. + pub fn from_attr(attr: &impl AttributeExt) -> Option<(Self, Option)> { + attr.name().and_then(|name| Self::from_symbol(name, || Some(attr.id()))) + } + + /// Converts a `Symbol` to a level. + pub fn from_symbol( + s: Symbol, + id: impl FnOnce() -> Option, + ) -> Option<(Self, Option)> { + match s { + sym::allow => Some((Level::Allow, None)), + sym::expect => { + if let Some(attr_id) = id() { + Some(( + Level::Expect, + Some(LintExpectationId::Unstable { attr_id, lint_index: None }), + )) + } else { + None + } + } + sym::warn => Some((Level::Warn, None)), + sym::deny => Some((Level::Deny, None)), + sym::forbid => Some((Level::Forbid, None)), + _ => None, + } + } + pub fn to_cmd_flag(self) -> &'static str { match self { Level::Warn => "-W", @@ -563,26 +583,6 @@ pub fn default_level(&self, edition: Edition) -> Level { } } -/// The target of the `by_name` map, which accounts for renaming/deprecation. -#[derive(Debug)] -pub enum TargetLint { - /// A direct lint target - Id(LintId), - - /// Temporary renaming, used for easing migration pain; see #16545 - Renamed(String, LintId), - - /// Lint with this name existed previously, but has been removed/deprecated. - /// The string argument is the reason for removal. - Removed(String), - - /// A lint name that should give no warnings and have no effect. - /// - /// This is used by rustc to avoid warning about old rustdoc lints before rustdoc registers - /// them as tool lints. - Ignored, -} - /// Identifies a lint known to the compiler. #[derive(Clone, Copy, Debug)] pub struct LintId { @@ -652,13 +652,8 @@ pub enum DeprecatedSinceKind { InVersion(String), } -#[derive(Debug, HashStable_Generic)] +#[derive(Debug)] pub enum AttributeLintKind { - UnusedDuplicate { - this: Span, - other: Span, - warning: bool, - }, IllFormedAttributeInput { suggestions: Vec, docs: Option<&'static str>, @@ -682,10 +677,6 @@ pub enum AttributeLintKind { target: &'static str, target_span: Span, }, - UnsafeAttrOutsideUnsafe { - attribute_name_span: Span, - sugg_spans: Option<(Span, Span)>, - }, UnexpectedCfgName((Symbol, Span), Option<(Symbol, Span)>), UnexpectedCfgValue((Symbol, Span), Option<(Symbol, Span)>), DuplicateDocAlias { @@ -733,13 +724,9 @@ pub enum AttributeLintKind { MalformedDoc, ExpectedNoArgs, ExpectedNameValue, - MalformedOnUnimplementedAttr { - span: Span, - }, - MalformedOnConstAttr { - span: Span, - }, - MalformedOnMoveAttr { + MalFormedDiagnosticAttribute { + attribute: &'static str, + options: &'static str, span: Span, }, MalformedDiagnosticFormat { @@ -755,67 +742,18 @@ pub enum AttributeLintKind { first_span: Span, later_span: Span, }, - MissingOptionsForOnUnimplemented, - MissingOptionsForOnConst, - MissingOptionsForOnMove, - OnMoveMalformedFormatLiterals { - name: Symbol, - }, - OnMoveMalformedAttrExpectedLiteralOrDelimiter, - RenamedLint { - name: Symbol, - replace: Symbol, - suggestion: Span, - }, - DeprecatedLintName { - name: Symbol, - suggestion: Span, - replace: Symbol, - }, - RemovedLint { - name: Symbol, - reason: String, - }, - UnknownLint { - name: Symbol, - span: Span, - suggestion: Option<(Symbol, bool)>, - }, - IgnoredUnlessCrateSpecified { - level: Symbol, - name: Symbol, + MissingOptionsForDiagnosticAttribute { + attribute: &'static str, + options: &'static str, }, + NonMetaItemDiagnosticAttribute, } #[derive(Debug, Clone, HashStable_Generic)] pub enum FormatWarning { PositionalArgument { span: Span, help: String }, InvalidSpecifier { name: String, span: Span }, -} - -#[derive(Debug)] -pub enum CheckLintNameResult<'a> { - Ok(&'a [LintId]), - /// Lint doesn't exist. Potentially contains a suggestion for a correct lint name. - NoLint(Option<(Symbol, bool)>), - /// The lint refers to a tool that has not been registered. - NoTool, - /// The lint has been renamed to a new name. - Renamed(Symbol), - /// Lint that previously was part of rustc, but now is part of external lint tool - RenamedToolLint(Symbol), - /// The lint has been removed due to the given reason. - Removed(String), - - /// The lint is from a tool. The `LintId` will be returned as if it were a - /// rustc lint. The `Option` indicates if the lint has been - /// renamed. - Tool(&'a [LintId], Option), - - /// The lint is from a tool. Either the lint does not exist in the tool or - /// the code was not compiled with the tool and therefore the lint was - /// never added to the `LintStore`. - MissingTool, + DisallowedPlaceholder { span: Span }, } pub type RegisteredTools = FxIndexSet; diff --git a/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp b/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp index f7fccf6296bd..c310e580af55 100644 --- a/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp +++ b/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp @@ -9,6 +9,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/Magic.h" #include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/IR/AutoUpgrade.h" #include "llvm/IR/DIBuilder.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DiagnosticHandler.h" @@ -1815,6 +1816,19 @@ extern "C" void LLVMRustSetNoSanitizeHWAddress(LLVMValueRef Global) { GV.setSanitizerMetadata(MD); } +extern "C" bool LLVMRustUpgradeIntrinsicFunction(LLVMValueRef Fn, + LLVMValueRef *NewFn) { + Function *F = unwrap(Fn); + Function *NewF = nullptr; + bool CanUpgrade = UpgradeIntrinsicFunction(F, NewF, false); + *NewFn = wrap(NewF); + return CanUpgrade; +} + +extern "C" bool LLVMRustIsTargetIntrinsic(unsigned ID) { + return Intrinsic::isTargetIntrinsic(ID); +} + // Statically assert that the fixed metadata kind IDs declared in // `metadata_kind.rs` match the ones actually used by LLVM. #define FIXED_MD_KIND(VARIANT, VALUE) \ diff --git a/compiler/rustc_metadata/src/creader.rs b/compiler/rustc_metadata/src/creader.rs index f36485cf0338..feeb38830e0a 100644 --- a/compiler/rustc_metadata/src/creader.rs +++ b/compiler/rustc_metadata/src/creader.rs @@ -1,5 +1,6 @@ //! Validates all used crates and extern libraries and loads their metadata +use std::collections::BTreeMap; use std::error::Error; use std::path::Path; use std::str::FromStr; @@ -23,6 +24,7 @@ use rustc_middle::ty::data_structures::IndexSet; use rustc_middle::ty::{TyCtxt, TyCtxtFeed}; use rustc_proc_macro::bridge::client::ProcMacro; +use rustc_session::config::mitigation_coverage::DeniedPartialMitigationLevel; use rustc_session::config::{ CrateType, ExtendedTargetModifierInfo, ExternLocation, Externs, OptionsTargetModifiers, TargetModifier, @@ -463,6 +465,12 @@ fn report_target_modifiers_extended( } } + pub fn report_session_incompatibilities(&self, tcx: TyCtxt<'_>, krate: &Crate) { + self.report_incompatible_target_modifiers(tcx, krate); + self.report_incompatible_partial_mitigations(tcx, krate); + self.report_incompatible_async_drop_feature(tcx, krate); + } + pub fn report_incompatible_target_modifiers(&self, tcx: TyCtxt<'_>, krate: &Crate) { for flag_name in &tcx.sess.opts.cg.unsafe_allow_abi_mismatch { if !OptionsTargetModifiers::is_target_modifier(flag_name) { @@ -484,6 +492,43 @@ pub fn report_incompatible_target_modifiers(&self, tcx: TyCtxt<'_>, krate: &Crat } } + pub fn report_incompatible_partial_mitigations(&self, tcx: TyCtxt<'_>, krate: &Crate) { + let my_mitigations = tcx.sess.gather_enabled_denied_partial_mitigations(); + let mut my_mitigations: BTreeMap<_, _> = + my_mitigations.iter().map(|mitigation| (mitigation.kind, mitigation)).collect(); + for skipped_mitigation in tcx.sess.opts.allowed_partial_mitigations(tcx.sess.edition()) { + my_mitigations.remove(&skipped_mitigation); + } + const MAX_ERRORS_PER_MITIGATION: usize = 5; + let mut errors_per_mitigation = BTreeMap::new(); + for (_cnum, data) in self.iter_crate_data() { + if data.is_proc_macro_crate() { + continue; + } + let their_mitigations = data.enabled_denied_partial_mitigations(); + for my_mitigation in my_mitigations.values() { + let their_mitigation = their_mitigations + .iter() + .find(|mitigation| mitigation.kind == my_mitigation.kind) + .map_or(DeniedPartialMitigationLevel::Enabled(false), |m| m.level); + if their_mitigation < my_mitigation.level { + let errors = errors_per_mitigation.entry(my_mitigation.kind).or_insert(0); + if *errors >= MAX_ERRORS_PER_MITIGATION { + continue; + } + *errors += 1; + + tcx.dcx().emit_err(errors::MitigationLessStrictInDependency { + span: krate.spans.inner_span.shrink_to_lo(), + mitigation_name: my_mitigation.kind.to_string(), + mitigation_level: my_mitigation.level.level_str().to_string(), + extern_crate: data.name(), + }); + } + } + } + } + // Report about async drop types in dependency if async drop feature is disabled pub fn report_incompatible_async_drop_feature(&self, tcx: TyCtxt<'_>, krate: &Crate) { if tcx.features().async_drop() { diff --git a/compiler/rustc_metadata/src/errors.rs b/compiler/rustc_metadata/src/errors.rs index 8b2895d70004..5c33fab5011d 100644 --- a/compiler/rustc_metadata/src/errors.rs +++ b/compiler/rustc_metadata/src/errors.rs @@ -13,7 +13,7 @@ #[diag( "crate `{$crate_name}` required to be available in rlib format, but was not found in this form" )] -pub struct RlibRequired { +pub(crate) struct RlibRequired { pub crate_name: Symbol, } @@ -21,7 +21,7 @@ pub struct RlibRequired { #[diag( "crate `{$crate_name}` required to be available in {$kind} format, but was not found in this form" )] -pub struct LibRequired<'a> { +pub(crate) struct LibRequired<'a> { pub crate_name: Symbol, pub kind: &'a str, } @@ -31,7 +31,7 @@ pub struct LibRequired<'a> { "crate `{$crate_name}` required to be available in {$kind} format, but was not found in this form" )] #[help("try adding `extern crate rustc_driver;` at the top level of this crate")] -pub struct RustcLibRequired<'a> { +pub(crate) struct RustcLibRequired<'a> { pub crate_name: Symbol, pub kind: &'a str, } @@ -39,7 +39,7 @@ pub struct RustcLibRequired<'a> { #[derive(Diagnostic)] #[diag("cannot satisfy dependencies so `{$crate_name}` only shows up once")] #[help("having upstream crates all available in one format will likely make this go away")] -pub struct CrateDepMultiple { +pub(crate) struct CrateDepMultiple { pub crate_name: Symbol, #[subdiagnostic] pub non_static_deps: Vec, @@ -49,14 +49,14 @@ pub struct CrateDepMultiple { #[derive(Subdiagnostic)] #[note("`{$sub_crate_name}` was unavailable as a static crate, preventing fully static linking")] -pub struct NonStaticCrateDep { +pub(crate) struct NonStaticCrateDep { /// It's different from `crate_name` in main Diagnostic. pub sub_crate_name: Symbol, } #[derive(Diagnostic)] #[diag("cannot link together two panic runtimes: {$prev_name} and {$cur_name}")] -pub struct TwoPanicRuntimes { +pub(crate) struct TwoPanicRuntimes { pub prev_name: Symbol, pub cur_name: Symbol, } @@ -65,7 +65,7 @@ pub struct TwoPanicRuntimes { #[diag( "the linked panic runtime `{$runtime}` is not compiled with this crate's panic strategy `{$strategy}`" )] -pub struct BadPanicStrategy { +pub(crate) struct BadPanicStrategy { pub runtime: Symbol, pub strategy: PanicStrategy, } @@ -74,7 +74,7 @@ pub struct BadPanicStrategy { #[diag( "the crate `{$crate_name}` requires panic strategy `{$found_strategy}` which is incompatible with this crate's strategy of `{$desired_strategy}`" )] -pub struct RequiredPanicStrategy { +pub(crate) struct RequiredPanicStrategy { pub crate_name: Symbol, pub found_strategy: PanicStrategy, pub desired_strategy: PanicStrategy, @@ -84,7 +84,7 @@ pub struct RequiredPanicStrategy { #[diag( "the crate `{$crate_name}` was compiled with a panic strategy which is incompatible with `immediate-abort`" )] -pub struct IncompatibleWithImmediateAbort { +pub(crate) struct IncompatibleWithImmediateAbort { pub crate_name: Symbol, } @@ -92,13 +92,13 @@ pub struct IncompatibleWithImmediateAbort { #[diag( "the crate `core` was compiled with a panic strategy which is incompatible with `immediate-abort`" )] -pub struct IncompatibleWithImmediateAbortCore; +pub(crate) struct IncompatibleWithImmediateAbortCore; #[derive(Diagnostic)] #[diag( "the crate `{$crate_name}` is compiled with the panic-in-drop strategy `{$found_strategy}` which is incompatible with this crate's strategy of `{$desired_strategy}`" )] -pub struct IncompatiblePanicInDropStrategy { +pub(crate) struct IncompatiblePanicInDropStrategy { pub crate_name: Symbol, pub found_strategy: PanicStrategy, pub desired_strategy: PanicStrategy, @@ -106,18 +106,18 @@ pub struct IncompatiblePanicInDropStrategy { #[derive(Diagnostic)] #[diag("`#[link_ordinal]` is only supported if link kind is `raw-dylib`")] -pub struct LinkOrdinalRawDylib { +pub(crate) struct LinkOrdinalRawDylib { #[primary_span] pub span: Span, } #[derive(Diagnostic)] #[diag("library kind `framework` is only supported on Apple targets")] -pub struct LibFrameworkApple; +pub(crate) struct LibFrameworkApple; #[derive(Diagnostic)] #[diag("an empty renaming target was specified for library `{$lib_name}`")] -pub struct EmptyRenamingTarget<'a> { +pub(crate) struct EmptyRenamingTarget<'a> { pub lib_name: &'a str, } @@ -125,46 +125,46 @@ pub struct EmptyRenamingTarget<'a> { #[diag( "renaming of the library `{$lib_name}` was specified, however this crate contains no `#[link(...)]` attributes referencing this library" )] -pub struct RenamingNoLink<'a> { +pub(crate) struct RenamingNoLink<'a> { pub lib_name: &'a str, } #[derive(Diagnostic)] #[diag("multiple renamings were specified for library `{$lib_name}`")] -pub struct MultipleRenamings<'a> { +pub(crate) struct MultipleRenamings<'a> { pub lib_name: &'a str, } #[derive(Diagnostic)] #[diag("overriding linking modifiers from command line is not supported")] -pub struct NoLinkModOverride { +pub(crate) struct NoLinkModOverride { #[primary_span] pub span: Option, } #[derive(Diagnostic)] #[diag("ABI not supported by `#[link(kind = \"raw-dylib\")]` on this architecture")] -pub struct RawDylibUnsupportedAbi { +pub(crate) struct RawDylibUnsupportedAbi { #[primary_span] pub span: Span, } #[derive(Diagnostic)] #[diag("failed to create file encoder: {$err}")] -pub struct FailCreateFileEncoder { +pub(crate) struct FailCreateFileEncoder { pub err: Error, } #[derive(Diagnostic)] #[diag("failed to write to `{$path}`: {$err}")] -pub struct FailWriteFile<'a> { +pub(crate) struct FailWriteFile<'a> { pub path: &'a Path, pub err: Error, } #[derive(Diagnostic)] #[diag("the crate `{$crate_name}` is not a panic runtime")] -pub struct CrateNotPanicRuntime { +pub(crate) struct CrateNotPanicRuntime { pub crate_name: Symbol, } @@ -172,26 +172,26 @@ pub struct CrateNotPanicRuntime { #[diag( "the crate `{$crate_name}` resolved as `compiler_builtins` but is not `#![compiler_builtins]`" )] -pub struct CrateNotCompilerBuiltins { +pub(crate) struct CrateNotCompilerBuiltins { pub crate_name: Symbol, } #[derive(Diagnostic)] #[diag("the crate `{$crate_name}` does not have the panic strategy `{$strategy}`")] -pub struct NoPanicStrategy { +pub(crate) struct NoPanicStrategy { pub crate_name: Symbol, pub strategy: PanicStrategy, } #[derive(Diagnostic)] #[diag("the crate `{$crate_name}` is not a profiler runtime")] -pub struct NotProfilerRuntime { +pub(crate) struct NotProfilerRuntime { pub crate_name: Symbol, } #[derive(Diagnostic)] #[diag("cannot define multiple global allocators")] -pub struct NoMultipleGlobalAlloc { +pub(crate) struct NoMultipleGlobalAlloc { #[primary_span] #[label("cannot define a new global allocator")] pub span2: Span, @@ -201,7 +201,7 @@ pub struct NoMultipleGlobalAlloc { #[derive(Diagnostic)] #[diag("cannot define multiple allocation error handlers")] -pub struct NoMultipleAllocErrorHandler { +pub(crate) struct NoMultipleAllocErrorHandler { #[primary_span] #[label("cannot define a new allocation error handler")] pub span2: Span, @@ -213,7 +213,7 @@ pub struct NoMultipleAllocErrorHandler { #[diag( "the `#[global_allocator]` in {$other_crate_name} conflicts with global allocator in: {$crate_name}" )] -pub struct ConflictingGlobalAlloc { +pub(crate) struct ConflictingGlobalAlloc { pub crate_name: Symbol, pub other_crate_name: Symbol, } @@ -222,7 +222,7 @@ pub struct ConflictingGlobalAlloc { #[diag( "the `#[alloc_error_handler]` in {$other_crate_name} conflicts with allocation error handler in: {$crate_name}" )] -pub struct ConflictingAllocErrorHandler { +pub(crate) struct ConflictingAllocErrorHandler { pub crate_name: Symbol, pub other_crate_name: Symbol, } @@ -231,28 +231,18 @@ pub struct ConflictingAllocErrorHandler { #[diag( "no global memory allocator found but one is required; link to std or add `#[global_allocator]` to a static item that implements the GlobalAlloc trait" )] -pub struct GlobalAllocRequired; - -#[derive(Diagnostic)] -#[diag( - "the crate `{$crate_name}` cannot depend on a crate that needs {$needs_crate_name}, but it depends on `{$deps_crate_name}`" -)] -pub struct NoTransitiveNeedsDep<'a> { - pub crate_name: Symbol, - pub needs_crate_name: &'a str, - pub deps_crate_name: Symbol, -} +pub(crate) struct GlobalAllocRequired; #[derive(Diagnostic)] #[diag("failed to write {$filename}: {$err}")] -pub struct FailedWriteError { +pub(crate) struct FailedWriteError { pub filename: PathBuf, pub err: Error, } #[derive(Diagnostic)] #[diag("failed to copy {$filename} to stdout: {$err}")] -pub struct FailedCopyToStdout { +pub(crate) struct FailedCopyToStdout { pub filename: PathBuf, pub err: Error, } @@ -261,18 +251,18 @@ pub struct FailedCopyToStdout { #[diag( "option `-o` or `--emit` is used to write binary output type `metadata` to stdout, but stdout is a tty" )] -pub struct BinaryOutputToTty; +pub(crate) struct BinaryOutputToTty; #[derive(Diagnostic)] #[diag("could not find native static library `{$libname}`, perhaps an -L flag is missing?")] -pub struct MissingNativeLibrary<'a> { +pub(crate) struct MissingNativeLibrary<'a> { libname: &'a str, #[subdiagnostic] suggest_name: Option>, } impl<'a> MissingNativeLibrary<'a> { - pub fn new(libname: &'a str, verbatim: bool) -> Self { + pub(crate) fn new(libname: &'a str, verbatim: bool) -> Self { // if it looks like the user has provided a complete filename rather just the bare lib name, // then provide a note that they might want to try trimming the name let suggested_name = if !verbatim { @@ -299,32 +289,32 @@ pub fn new(libname: &'a str, verbatim: bool) -> Self { #[derive(Subdiagnostic)] #[help("only provide the library name `{$suggested_name}`, not the full filename")] -pub struct SuggestLibraryName<'a> { +pub(crate) struct SuggestLibraryName<'a> { suggested_name: &'a str, } #[derive(Diagnostic)] #[diag("couldn't create a temp dir: {$err}")] -pub struct FailedCreateTempdir { +pub(crate) struct FailedCreateTempdir { pub err: Error, } #[derive(Diagnostic)] #[diag("failed to create the file {$filename}: {$err}")] -pub struct FailedCreateFile<'a> { +pub(crate) struct FailedCreateFile<'a> { pub filename: &'a Path, pub err: Error, } #[derive(Diagnostic)] #[diag("failed to create encoded metadata from file: {$err}")] -pub struct FailedCreateEncodedMetadata { +pub(crate) struct FailedCreateEncodedMetadata { pub err: Error, } #[derive(Diagnostic)] #[diag("cannot load a crate with a non-ascii name `{$crate_name}`")] -pub struct NonAsciiName { +pub(crate) struct NonAsciiName { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -332,7 +322,7 @@ pub struct NonAsciiName { #[derive(Diagnostic)] #[diag("extern location for {$crate_name} does not exist: {$location}")] -pub struct ExternLocationNotExist<'a> { +pub(crate) struct ExternLocationNotExist<'a> { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -341,7 +331,7 @@ pub struct ExternLocationNotExist<'a> { #[derive(Diagnostic)] #[diag("extern location for {$crate_name} is not a file: {$location}")] -pub struct ExternLocationNotFile<'a> { +pub(crate) struct ExternLocationNotFile<'a> { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -386,7 +376,7 @@ pub(crate) struct FullMetadataNotFound { #[derive(Diagnostic)] #[diag("the current crate is indistinguishable from one of its dependencies: it has the same crate-name `{$crate_name}` and was compiled with the same `-C metadata` arguments, so this will result in symbol conflicts between the two", code = E0519)] -pub struct SymbolConflictsCurrent { +pub(crate) struct SymbolConflictsCurrent { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -394,7 +384,7 @@ pub struct SymbolConflictsCurrent { #[derive(Diagnostic)] #[diag("found crates (`{$crate_name0}` and `{$crate_name1}`) with colliding StableCrateId values")] -pub struct StableCrateIdCollision { +pub(crate) struct StableCrateIdCollision { #[primary_span] pub span: Span, pub crate_name0: Symbol, @@ -403,7 +393,7 @@ pub struct StableCrateIdCollision { #[derive(Diagnostic)] #[diag("{$path}{$err}")] -pub struct DlError { +pub(crate) struct DlError { #[primary_span] pub span: Span, pub path: String, @@ -414,7 +404,7 @@ pub struct DlError { #[diag("found possibly newer version of crate `{$crate_name}`{$add_info}", code = E0460)] #[note("perhaps that crate needs to be recompiled?")] #[note("the following crate versions were found:{$found_crates}")] -pub struct NewerCrateVersion { +pub(crate) struct NewerCrateVersion { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -425,7 +415,7 @@ pub struct NewerCrateVersion { #[derive(Diagnostic)] #[diag("couldn't find crate `{$crate_name}` with expected target triple {$locator_triple}{$add_info}", code = E0461)] #[note("the following crate versions were found:{$found_crates}")] -pub struct NoCrateWithTriple<'a> { +pub(crate) struct NoCrateWithTriple<'a> { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -438,7 +428,7 @@ pub struct NoCrateWithTriple<'a> { #[diag("found staticlib `{$crate_name}` instead of rlib or dylib{$add_info}", code = E0462)] #[note("the following crate versions were found:{$found_crates}")] #[help("please recompile that crate using --crate-type lib")] -pub struct FoundStaticlib { +pub(crate) struct FoundStaticlib { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -452,7 +442,7 @@ pub struct FoundStaticlib { #[help( "please recompile that crate using this compiler ({$rustc_version}) (consider running `cargo clean` first)" )] -pub struct IncompatibleRustc { +pub(crate) struct IncompatibleRustc { #[primary_span] pub span: Span, pub crate_name: Symbol, @@ -461,7 +451,7 @@ pub struct IncompatibleRustc { pub rustc_version: String, } -pub struct InvalidMetadataFiles { +pub(crate) struct InvalidMetadataFiles { pub span: Span, pub crate_name: Symbol, pub add_info: String, @@ -487,7 +477,7 @@ fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { } } -pub struct CannotFindCrate { +pub(crate) struct CannotFindCrate { pub span: Span, pub crate_name: Symbol, pub add_info: String, @@ -560,7 +550,7 @@ fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { #[derive(Diagnostic)] #[diag("extern location for {$crate_name} is of an unknown type: {$path}")] -pub struct CrateLocationUnknownType<'a> { +pub(crate) struct CrateLocationUnknownType<'a> { #[primary_span] pub span: Span, pub path: &'a Path, @@ -569,7 +559,7 @@ pub struct CrateLocationUnknownType<'a> { #[derive(Diagnostic)] #[diag("file name should be lib*.rlib or {$dll_prefix}*{$dll_suffix}")] -pub struct LibFilenameForm<'a> { +pub(crate) struct LibFilenameForm<'a> { #[primary_span] pub span: Span, pub dll_prefix: &'a str, @@ -599,7 +589,7 @@ pub(crate) struct WasmCAbi { #[help( "if you are sure this will not cause problems, you may use `-Cunsafe-allow-abi-mismatch={$flag_name}` to silence this error" )] -pub struct IncompatibleTargetModifiers { +pub(crate) struct IncompatibleTargetModifiers { #[primary_span] pub span: Span, pub extern_crate: Symbol, @@ -624,7 +614,7 @@ pub struct IncompatibleTargetModifiers { #[help( "if you are sure this will not cause problems, you may use `-Cunsafe-allow-abi-mismatch={$flag_name}` to silence this error" )] -pub struct IncompatibleTargetModifiersLMissed { +pub(crate) struct IncompatibleTargetModifiersLMissed { #[primary_span] pub span: Span, pub extern_crate: Symbol, @@ -648,7 +638,7 @@ pub struct IncompatibleTargetModifiersLMissed { #[help( "if you are sure this will not cause problems, you may use `-Cunsafe-allow-abi-mismatch={$flag_name}` to silence this error" )] -pub struct IncompatibleTargetModifiersRMissed { +pub(crate) struct IncompatibleTargetModifiersRMissed { #[primary_span] pub span: Span, pub extern_crate: Symbol, @@ -662,7 +652,7 @@ pub struct IncompatibleTargetModifiersRMissed { #[diag( "unknown target modifier `{$flag_name}`, requested by `-Cunsafe-allow-abi-mismatch={$flag_name}`" )] -pub struct UnknownTargetModifierUnsafeAllowed { +pub(crate) struct UnknownTargetModifierUnsafeAllowed { #[primary_span] pub span: Span, pub flag_name: String, @@ -675,7 +665,7 @@ pub struct UnknownTargetModifierUnsafeAllowed { #[help( "if async drop type will be dropped in a crate without `feature(async_drop)`, sync Drop will be used" )] -pub struct AsyncDropTypesInDependency { +pub(crate) struct AsyncDropTypesInDependency { #[primary_span] pub span: Span, pub extern_crate: Symbol, @@ -684,7 +674,7 @@ pub struct AsyncDropTypesInDependency { #[derive(Diagnostic)] #[diag("link name must be well-formed if link kind is `raw-dylib`")] -pub struct RawDylibMalformed { +pub(crate) struct RawDylibMalformed { #[primary_span] pub span: Span, } @@ -696,3 +686,21 @@ pub(crate) struct UnusedCrateDependency { pub extern_crate: Symbol, pub local_crate: Symbol, } + +#[derive(Diagnostic)] +#[diag( + "your program uses the crate `{$extern_crate}`, that is not compiled with `{$mitigation_name}{$mitigation_level}` enabled" +)] +#[note( + "recompile `{$extern_crate}` with `{$mitigation_name}{$mitigation_level}` enabled, or use `-Z allow-partial-mitigations={$mitigation_name}` to allow creating an artifact that has the mitigation partially enabled " +)] +#[help( + "it is possible to disable `-Z allow-partial-mitigations={$mitigation_name}` via `-Z deny-partial-mitigations={$mitigation_name}`" +)] +pub(crate) struct MitigationLessStrictInDependency { + #[primary_span] + pub span: Span, + pub mitigation_name: String, + pub mitigation_level: String, + pub extern_crate: Symbol, +} diff --git a/compiler/rustc_metadata/src/rmeta/decoder.rs b/compiler/rustc_metadata/src/rmeta/decoder.rs index fc541f952d22..280b3b12e5c8 100644 --- a/compiler/rustc_metadata/src/rmeta/decoder.rs +++ b/compiler/rustc_metadata/src/rmeta/decoder.rs @@ -30,6 +30,7 @@ use rustc_serialize::opaque::MemDecoder; use rustc_serialize::{Decodable, Decoder}; use rustc_session::config::TargetModifier; +use rustc_session::config::mitigation_coverage::DeniedPartialMitigation; use rustc_session::cstore::{CrateSource, ExternCrate}; use rustc_span::hygiene::HygieneDecodeContext; use rustc_span::{ @@ -78,9 +79,15 @@ pub(crate) fn bytes(&self) -> &OwnedSlice { /// own crate numbers. pub(crate) type CrateNumMap = IndexVec; -/// Target modifiers - abi or exploit mitigations flags +/// Target modifiers - abi or exploit mitigations options that may cause unsoundness when mixed or +/// partially enabled. pub(crate) type TargetModifiers = Vec; +/// The set of mitigations that cannot be partially enabled (see +/// [RFC 3855](https://github.com/rust-lang/rfcs/pull/3855)), but are currently enabled for this +/// crate. +pub(crate) type DeniedPartialMitigations = Vec; + pub(crate) struct CrateMetadata { /// The primary crate data - binary metadata blob. blob: MetadataBlob, @@ -959,6 +966,13 @@ pub(crate) fn decode_target_modifiers<'a>( ) -> impl ExactSizeIterator { self.target_modifiers.decode(metadata) } + + pub(crate) fn decode_denied_partial_mitigations<'a>( + &self, + metadata: &'a MetadataBlob, + ) -> impl ExactSizeIterator { + self.denied_partial_mitigations.decode(metadata) + } } impl<'a> CrateMetadataRef<'a> { @@ -1941,6 +1955,10 @@ pub(crate) fn target_modifiers(&self) -> TargetModifiers { self.root.decode_target_modifiers(&self.blob).collect() } + pub(crate) fn enabled_denied_partial_mitigations(&self) -> DeniedPartialMitigations { + self.root.decode_denied_partial_mitigations(&self.blob).collect() + } + /// Keep `new_extern_crate` if it looks better in diagnostics pub(crate) fn update_extern_crate_diagnostics( &mut self, diff --git a/compiler/rustc_metadata/src/rmeta/decoder/cstore_impl.rs b/compiler/rustc_metadata/src/rmeta/decoder/cstore_impl.rs index 01e6d49a51c7..f9f746188f23 100644 --- a/compiler/rustc_metadata/src/rmeta/decoder/cstore_impl.rs +++ b/compiler/rustc_metadata/src/rmeta/decoder/cstore_impl.rs @@ -455,10 +455,11 @@ pub(in crate::rmeta) fn provide(providers: &mut Providers) { let mut visible_parent_map: DefIdMap = Default::default(); // This is a secondary visible_parent_map, storing the DefId of - // parents that re-export the child as `_` or module parents - // which are `#[doc(hidden)]`. Since we prefer paths that don't - // do this, merge this map at the end, only if we're missing - // keys from the former. + // parents that re-export the child as `_`, module parents + // which are `#[doc(hidden)]`, or `use` items that are themselves + // `#[doc(hidden)]`. Since we prefer paths that don't do this, + // merge this map at the end, only if we're missing keys from + // the former. // This is a rudimentary check that does not catch all cases, // just the easiest. let mut fallback_map: Vec<(DefId, DefId)> = Default::default(); @@ -500,6 +501,18 @@ pub(in crate::rmeta) fn provide(providers: &mut Providers) { return; } + // If the re-export itself is `#[doc(hidden)]`, deprioritize it. + // See PR #99698 for the case where the *parent* is doc-hidden. + if child + .reexport_chain + .first() + .and_then(|r| r.id()) + .is_some_and(|id| tcx.is_doc_hidden(id)) + { + fallback_map.push((def_id, parent)); + return; + } + match visible_parent_map.entry(def_id) { Entry::Occupied(mut entry) => { // If `child` is defined in crate `cnum`, ensure diff --git a/compiler/rustc_metadata/src/rmeta/encoder.rs b/compiler/rustc_metadata/src/rmeta/encoder.rs index 3f8c11a87e85..b516470052c3 100644 --- a/compiler/rustc_metadata/src/rmeta/encoder.rs +++ b/compiler/rustc_metadata/src/rmeta/encoder.rs @@ -10,7 +10,6 @@ use rustc_data_structures::sync::{par_for_each_in, par_join}; use rustc_data_structures::temp_dir::MaybeTempDir; use rustc_data_structures::thousands::usize_with_underscores; -use rustc_feature::Features; use rustc_hir as hir; use rustc_hir::attrs::{AttributeKind, EncodeCrossCrate}; use rustc_hir::def_id::{CRATE_DEF_ID, CRATE_DEF_INDEX, LOCAL_CRATE, LocalDefId, LocalDefIdSet}; @@ -27,6 +26,7 @@ use rustc_middle::ty::fast_reject::{self, TreatParams}; use rustc_middle::{bug, span_bug}; use rustc_serialize::{Decodable, Decoder, Encodable, Encoder, opaque}; +use rustc_session::config::mitigation_coverage::DeniedPartialMitigation; use rustc_session::config::{CrateType, OptLevel, TargetModifier}; use rustc_span::hygiene::HygieneEncodeContext; use rustc_span::{ @@ -715,6 +715,8 @@ macro_rules! stat { // `SourceFiles` we actually need to encode. let source_map = stat!("source-map", || self.encode_source_map()); let target_modifiers = stat!("target-modifiers", || self.encode_target_modifiers()); + let denied_partial_mitigations = stat!("denied-partial-mitigations", || self + .encode_enabled_denied_partial_mitigations()); let root = stat!("final", || { let attrs = tcx.hir_krate_attrs(); @@ -758,6 +760,7 @@ macro_rules! stat { foreign_modules, source_map, target_modifiers, + denied_partial_mitigations, traits, impls, incoherent_impls, @@ -842,10 +845,9 @@ macro_rules! stat { } } -struct AnalyzeAttrState<'a> { +struct AnalyzeAttrState { is_exported: bool, is_doc_hidden: bool, - features: &'a Features, } /// Returns whether an attribute needs to be recorded in metadata, that is, if it's usable and @@ -858,12 +860,17 @@ struct AnalyzeAttrState<'a> { /// visibility: this is a piece of data that can be computed once per defid, and not once per /// attribute. Some attributes would only be usable downstream if they are public. #[inline] -fn analyze_attr(attr: &hir::Attribute, state: &mut AnalyzeAttrState<'_>) -> bool { +fn analyze_attr(attr: &hir::Attribute, state: &mut AnalyzeAttrState) -> bool { let mut should_encode = false; if let hir::Attribute::Parsed(p) = attr && p.encode_cross_crate() == EncodeCrossCrate::No { // Attributes not marked encode-cross-crate don't need to be encoded for downstream crates. + } else if let Some(name) = attr.name() + && [sym::warn, sym::allow, sym::expect, sym::forbid, sym::deny].contains(&name) + { + // Lint attributes don't need to be encoded for downstream crates. + // FIXME remove this when #152369 is re-merged } else if let hir::Attribute::Parsed(AttributeKind::DocComment { .. }) = attr { // We keep all doc comments reachable to rustdoc because they might be "imported" into // downstream crates if they use `#[doc(inline)]` to copy an item's documentation into @@ -876,8 +883,6 @@ fn analyze_attr(attr: &hir::Attribute, state: &mut AnalyzeAttrState<'_>) -> bool if d.hidden.is_some() { state.is_doc_hidden = true; } - } else if let &[sym::diagnostic, seg] = &*attr.path() { - should_encode = rustc_feature::is_stable_diagnostic_attribute(seg, state.features); } else { should_encode = true; } @@ -939,6 +944,10 @@ fn should_encode_attrs(def_kind: DefKind) -> bool { | DefKind::Macro(_) | DefKind::Field | DefKind::Impl { .. } => true, + // Encoding attrs for `Use` items allows `#[doc(hidden)]` on re-exports + // to be read cross-crate, which is needed for diagnostic path selection + // in `visible_parent_map`. See #153477. + DefKind::Use => true, // Tools may want to be able to detect their tool lints on // closures from upstream crates, too. This is used by // https://github.com/model-checking/kani and is not a performance @@ -949,7 +958,6 @@ fn should_encode_attrs(def_kind: DefKind) -> bool { | DefKind::ConstParam | DefKind::Ctor(..) | DefKind::ExternCrate - | DefKind::Use | DefKind::ForeignMod | DefKind::AnonConst | DefKind::InlineConst @@ -1390,7 +1398,6 @@ fn encode_attrs(&mut self, def_id: LocalDefId) { let mut state = AnalyzeAttrState { is_exported: tcx.effective_visibilities(()).is_exported(def_id), is_doc_hidden: false, - features: &tcx.features(), }; let attr_iter = tcx .hir_attrs(tcx.local_def_id_to_hir_id(def_id)) @@ -2100,6 +2107,12 @@ fn encode_target_modifiers(&mut self) -> LazyArray { self.lazy_array(tcx.sess.opts.gather_target_modifiers()) } + fn encode_enabled_denied_partial_mitigations(&mut self) -> LazyArray { + empty_proc_macro!(self); + let tcx = self.tcx; + self.lazy_array(tcx.sess.gather_enabled_denied_partial_mitigations()) + } + fn encode_lib_features(&mut self) -> LazyArray<(Symbol, FeatureStability)> { empty_proc_macro!(self); let tcx = self.tcx; @@ -2470,8 +2483,7 @@ pub fn encode_metadata(tcx: TyCtxt<'_>, path: &Path, ref_path: Option<&Path>) { tcx.dep_graph.with_task( dep_node, tcx, - path, - |tcx, path| { + || { with_encode_metadata_header(tcx, path, |ecx| { // Encode all the entries and extra information in the crate, // culminating in the `CrateRoot` which points to all of it. diff --git a/compiler/rustc_metadata/src/rmeta/mod.rs b/compiler/rustc_metadata/src/rmeta/mod.rs index 9dee913e8389..781d3c6d1837 100644 --- a/compiler/rustc_metadata/src/rmeta/mod.rs +++ b/compiler/rustc_metadata/src/rmeta/mod.rs @@ -36,6 +36,7 @@ use rustc_middle::ty::{self, Ty, TyCtxt}; use rustc_middle::util::Providers; use rustc_serialize::opaque::FileEncoder; +use rustc_session::config::mitigation_coverage::DeniedPartialMitigation; use rustc_session::config::{SymbolManglingVersion, TargetModifier}; use rustc_session::cstore::{CrateDepKind, ForeignModule, LinkagePreference, NativeLib}; use rustc_span::edition::Edition; @@ -286,6 +287,7 @@ pub(crate) struct CrateRoot { source_map: LazyTable>>, target_modifiers: LazyArray, + denied_partial_mitigations: LazyArray, compiler_builtins: bool, needs_allocator: bool, diff --git a/compiler/rustc_metadata/src/rmeta/parameterized.rs b/compiler/rustc_metadata/src/rmeta/parameterized.rs index 8a9de07836db..1531584e9978 100644 --- a/compiler/rustc_metadata/src/rmeta/parameterized.rs +++ b/compiler/rustc_metadata/src/rmeta/parameterized.rs @@ -120,6 +120,7 @@ impl ParameterizedOverTcx for $ty { rustc_middle::ty::adjustment::CoerceUnsizedInfo, rustc_middle::ty::fast_reject::SimplifiedType, rustc_session::config::TargetModifier, + rustc_session::config::mitigation_coverage::DeniedPartialMitigation, rustc_session::cstore::ForeignModule, rustc_session::cstore::LinkagePreference, rustc_session::cstore::NativeLib, diff --git a/compiler/rustc_middle/Cargo.toml b/compiler/rustc_middle/Cargo.toml index 8bad0e291bf8..f0e47e0075ff 100644 --- a/compiler/rustc_middle/Cargo.toml +++ b/compiler/rustc_middle/Cargo.toml @@ -16,7 +16,7 @@ rustc_arena = { path = "../rustc_arena" } rustc_ast = { path = "../rustc_ast" } rustc_ast_ir = { path = "../rustc_ast_ir" } rustc_data_structures = { path = "../rustc_data_structures" } -rustc_error_messages = { path = "../rustc_error_messages" } # Used for intra-doc links +rustc_error_messages = { path = "../rustc_error_messages" } # Used for intra-doc links rustc_errors = { path = "../rustc_errors" } rustc_feature = { path = "../rustc_feature" } rustc_graphviz = { path = "../rustc_graphviz" } @@ -33,7 +33,7 @@ rustc_target = { path = "../rustc_target" } rustc_thread_pool = { path = "../rustc_thread_pool" } rustc_type_ir = { path = "../rustc_type_ir" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_middle/src/dep_graph/graph.rs b/compiler/rustc_middle/src/dep_graph/graph.rs index abd37f248800..be29e053a17c 100644 --- a/compiler/rustc_middle/src/dep_graph/graph.rs +++ b/compiler/rustc_middle/src/dep_graph/graph.rs @@ -52,6 +52,7 @@ pub enum QuerySideEffect { /// the side effect dep node as a dependency. CheckFeature { symbol: Symbol }, } + #[derive(Clone)] pub struct DepGraph { data: Option>, @@ -274,17 +275,19 @@ pub fn with_query_deserialization(&self, op: OP) -> R } #[inline(always)] - pub fn with_task<'tcx, A: Debug, R>( + pub fn with_task<'tcx, OP, R>( &self, dep_node: DepNode, tcx: TyCtxt<'tcx>, - task_arg: A, - task_fn: fn(tcx: TyCtxt<'tcx>, task_arg: A) -> R, + op: OP, hash_result: Option, &R) -> Fingerprint>, - ) -> (R, DepNodeIndex) { + ) -> (R, DepNodeIndex) + where + OP: FnOnce() -> R, + { match self.data() { - Some(data) => data.with_task(dep_node, tcx, task_arg, task_fn, hash_result), - None => (task_fn(tcx, task_arg), self.next_virtual_depnode_index()), + Some(data) => data.with_task(dep_node, tcx, op, hash_result), + None => (op(), self.next_virtual_depnode_index()), } } @@ -309,44 +312,27 @@ pub fn with_anon_task<'tcx, OP, R>( } impl DepGraphData { - /// Starts a new dep-graph task. Dep-graph tasks are specified - /// using a free function (`task`) and **not** a closure -- this - /// is intentional because we want to exercise tight control over - /// what state they have access to. In particular, we want to - /// prevent implicit 'leaks' of tracked state into the task (which - /// could then be read without generating correct edges in the - /// dep-graph -- see the [rustc dev guide] for more details on - /// the dep-graph). - /// - /// Therefore, the task function takes a `TyCtxt`, plus exactly one - /// additional argument, `task_arg`. The additional argument type can be - /// `()` if no argument is needed, or a tuple if multiple arguments are - /// needed. - /// - /// [rustc dev guide]: https://rustc-dev-guide.rust-lang.org/queries/incremental-compilation.html #[inline(always)] - pub fn with_task<'tcx, A: Debug, R>( + pub fn with_task<'tcx, OP, R>( &self, dep_node: DepNode, tcx: TyCtxt<'tcx>, - task_arg: A, - task_fn: fn(tcx: TyCtxt<'tcx>, task_arg: A) -> R, + op: OP, hash_result: Option, &R) -> Fingerprint>, - ) -> (R, DepNodeIndex) { + ) -> (R, DepNodeIndex) + where + OP: FnOnce() -> R, + { // If the following assertion triggers, it can have two reasons: // 1. Something is wrong with DepNode creation, either here or // in `DepGraph::try_mark_green()`. // 2. Two distinct query keys get mapped to the same `DepNode` // (see for example #48923). self.assert_dep_node_not_yet_allocated_in_current_session(tcx.sess, &dep_node, || { - format!( - "forcing query with already existing `DepNode`\n\ - - query-key: {task_arg:?}\n\ - - dep-node: {dep_node:?}" - ) + format!("forcing query with already existing `DepNode`: {dep_node:?}") }); - let with_deps = |task_deps| with_deps(task_deps, || task_fn(tcx, task_arg)); + let with_deps = |task_deps| with_deps(task_deps, op); let (result, edges) = if tcx.is_eval_always(dep_node.kind) { (with_deps(TaskDepsRef::EvalAlways), EdgesVec::new()) } else { diff --git a/compiler/rustc_middle/src/error.rs b/compiler/rustc_middle/src/error.rs index 44ac747726a6..90af4d785945 100644 --- a/compiler/rustc_middle/src/error.rs +++ b/compiler/rustc_middle/src/error.rs @@ -36,23 +36,8 @@ pub(crate) struct OpaqueHiddenTypeMismatch<'tcx> { pub sub: TypeMismatchReason, } -#[derive(Diagnostic)] -#[diag("we don't support unions yet: '{$ty_name}'")] -pub struct UnsupportedUnion { - pub ty_name: String, -} - -// FIXME(autodiff): I should get used somewhere -#[derive(Diagnostic)] -#[diag("reading from a `Duplicated` const {$ty} is unsafe")] -pub struct AutodiffUnsafeInnerConstRef<'tcx> { - #[primary_span] - pub span: Span, - pub ty: Ty<'tcx>, -} - #[derive(Subdiagnostic)] -pub enum TypeMismatchReason { +pub(crate) enum TypeMismatchReason { #[label("this expression supplies two conflicting concrete types for the same opaque type")] ConflictType { #[primary_span] diff --git a/compiler/rustc_middle/src/hir/map.rs b/compiler/rustc_middle/src/hir/map.rs index 499c6dae060b..68357212bebe 100644 --- a/compiler/rustc_middle/src/hir/map.rs +++ b/compiler/rustc_middle/src/hir/map.rs @@ -707,7 +707,7 @@ pub fn hir_id_to_string(self, id: HirId) -> String { Node::ImplItem(ii) => { let kind = match ii.kind { ImplItemKind::Const(..) => "associated constant", - ImplItemKind::Fn(fn_sig, _) => match fn_sig.decl.implicit_self { + ImplItemKind::Fn(fn_sig, _) => match fn_sig.decl.implicit_self() { ImplicitSelfKind::None => "associated function", _ => "method", }, @@ -718,7 +718,7 @@ pub fn hir_id_to_string(self, id: HirId) -> String { Node::TraitItem(ti) => { let kind = match ti.kind { TraitItemKind::Const(..) => "associated constant", - TraitItemKind::Fn(fn_sig, _) => match fn_sig.decl.implicit_self { + TraitItemKind::Fn(fn_sig, _) => match fn_sig.decl.implicit_self() { ImplicitSelfKind::None => "associated function", _ => "trait method", }, @@ -945,7 +945,7 @@ fn named_span(item_span: Span, ident: Ident, generics: Option<&Generics<'_>>) -> }) => until_within(*outer_span, ty.span), // With generics and bounds. Node::Item(Item { - kind: ItemKind::Trait(_, _, _, _, generics, bounds, _), + kind: ItemKind::Trait(_, _, _, _, _, generics, bounds, _), span: outer_span, .. }) diff --git a/compiler/rustc_middle/src/hir/mod.rs b/compiler/rustc_middle/src/hir/mod.rs index 814b333cfb0f..7f82b9161fe6 100644 --- a/compiler/rustc_middle/src/hir/mod.rs +++ b/compiler/rustc_middle/src/hir/mod.rs @@ -17,7 +17,6 @@ use rustc_data_structures::sync::{DynSend, DynSync, try_par_for_each_in}; use rustc_hir::def::{DefKind, Res}; use rustc_hir::def_id::{DefId, LocalDefId, LocalModDefId}; -use rustc_hir::lints::DelayedLint; use rustc_hir::*; use rustc_index::IndexVec; use rustc_macros::{Decodable, Encodable, HashStable}; @@ -236,15 +235,10 @@ pub fn hash_owner_nodes( node: OwnerNode<'_>, bodies: &SortedMap>, attrs: &SortedMap, - delayed_lints: &[DelayedLint], define_opaque: Option<&[(Span, LocalDefId)]>, ) -> Hashes { if !self.needs_crate_hash() { - return Hashes { - opt_hash_including_bodies: None, - attrs_hash: None, - delayed_lints_hash: None, - }; + return Hashes { opt_hash_including_bodies: None, attrs_hash: None }; } self.with_stable_hashing_context(|mut hcx| { @@ -262,16 +256,7 @@ pub fn hash_owner_nodes( let h2 = stable_hasher.finish(); - // hash lints emitted during ast lowering - let mut stable_hasher = StableHasher::new(); - delayed_lints.hash_stable(&mut hcx, &mut stable_hasher); - let h3 = stable_hasher.finish(); - - Hashes { - opt_hash_including_bodies: Some(h1), - attrs_hash: Some(h2), - delayed_lints_hash: Some(h3), - } + Hashes { opt_hash_including_bodies: Some(h1), attrs_hash: Some(h2) } }) } @@ -465,7 +450,6 @@ pub fn hir_owner_parent(self, owner_id: OwnerId) -> HirId { pub struct Hashes { pub opt_hash_including_bodies: Option, pub attrs_hash: Option, - pub delayed_lints_hash: Option, } pub fn provide(providers: &mut Providers) { diff --git a/compiler/rustc_middle/src/infer/canonical.rs b/compiler/rustc_middle/src/infer/canonical.rs index 32c6b6e9c0ba..033e3e36b024 100644 --- a/compiler/rustc_middle/src/infer/canonical.rs +++ b/compiler/rustc_middle/src/infer/canonical.rs @@ -79,7 +79,7 @@ pub struct QueryResponse<'tcx, R> { #[derive(Clone, Debug, Default, PartialEq, Eq, Hash)] #[derive(HashStable, TypeFoldable, TypeVisitable)] pub struct QueryRegionConstraints<'tcx> { - pub outlives: Vec>, + pub constraints: Vec>, pub assumptions: Vec>, } @@ -91,7 +91,8 @@ impl QueryRegionConstraints<'_> { /// discharge a requirement from another query, which is a potential problem if we did throw /// away these assumptions because there were no constraints. pub fn is_empty(&self) -> bool { - self.outlives.is_empty() && self.assumptions.is_empty() + let QueryRegionConstraints { constraints, assumptions } = self; + constraints.is_empty() && assumptions.is_empty() } } @@ -134,7 +135,7 @@ pub fn is_proven(&self) -> bool { } } -pub type QueryOutlivesConstraint<'tcx> = (ty::ArgOutlivesPredicate<'tcx>, ConstraintCategory<'tcx>); +pub type QueryRegionConstraint<'tcx> = (ty::RegionConstraint<'tcx>, ConstraintCategory<'tcx>); #[derive(Default)] pub struct CanonicalParamEnvCache<'tcx> { diff --git a/compiler/rustc_middle/src/mir/mod.rs b/compiler/rustc_middle/src/mir/mod.rs index 1c14b94b8d7d..36752bba9f72 100644 --- a/compiler/rustc_middle/src/mir/mod.rs +++ b/compiler/rustc_middle/src/mir/mod.rs @@ -415,10 +415,10 @@ pub fn basic_blocks_mut(&mut self) -> &mut IndexVec) -> TypingEnv<'tcx> { match self.phase { // FIXME(#132279): we should reveal the opaques defined in the body during analysis. - MirPhase::Built | MirPhase::Analysis(_) => TypingEnv { - typing_mode: ty::TypingMode::non_body_analysis(), - param_env: tcx.param_env(self.source.def_id()), - }, + MirPhase::Built | MirPhase::Analysis(_) => TypingEnv::new( + tcx.param_env(self.source.def_id()), + ty::TypingMode::non_body_analysis(), + ), MirPhase::Runtime(_) => TypingEnv::post_analysis(tcx, self.source.def_id()), } } diff --git a/compiler/rustc_middle/src/queries.rs b/compiler/rustc_middle/src/queries.rs index 1017ccffb0b2..7c6ab642b273 100644 --- a/compiler/rustc_middle/src/queries.rs +++ b/compiler/rustc_middle/src/queries.rs @@ -60,7 +60,7 @@ use rustc_data_structures::steal::Steal; use rustc_data_structures::svh::Svh; use rustc_data_structures::unord::{UnordMap, UnordSet}; -use rustc_errors::ErrorGuaranteed; +use rustc_errors::{ErrorGuaranteed, catch_fatal_errors}; use rustc_hir as hir; use rustc_hir::attrs::{EiiDecl, EiiImpl, StrippedCfgItem}; use rustc_hir::def::{DefKind, DocLinkResMap}; @@ -276,6 +276,10 @@ /// Avoid calling this query directly. query opt_ast_lowering_delayed_lints(key: hir::OwnerId) -> Option<&'tcx hir::lints::DelayedLints> { desc { "getting AST lowering delayed lints in `{}`", tcx.def_path_str(key) } + // This query has to be `no_hash` and `eval_always`, + // because it accesses `delayed_lints` which is not hashed as part of the HIR + no_hash + eval_always } /// Returns the *default* of the const pararameter given by `DefId`. @@ -1202,7 +1206,7 @@ /// Return the live symbols in the crate for dead code check. /// /// The second return value maps from ADTs to ignored derived traits (e.g. Debug and Clone). - query live_symbols_and_ignored_derived_traits(_: ()) -> &'tcx Result<( + query live_symbols_and_ignored_derived_traits(_: ()) -> Result<&'tcx ( LocalDefIdSet, LocalDefIdMap>, ), ErrorGuaranteed> { @@ -1292,7 +1296,7 @@ /// Return the set of (transitive) callees that may result in a recursive call to `key`, /// if we were able to walk all callees. - query mir_callgraph_cyclic(key: LocalDefId) -> &'tcx Option> { + query mir_callgraph_cyclic(key: LocalDefId) -> Option<&'tcx UnordSet> { arena_cache desc { "computing (transitive) callees of `{}` that may recurse", diff --git a/compiler/rustc_middle/src/query/arena_cached.rs b/compiler/rustc_middle/src/query/arena_cached.rs index 7c7ad1262260..4ab2fbe91496 100644 --- a/compiler/rustc_middle/src/query/arena_cached.rs +++ b/compiler/rustc_middle/src/query/arena_cached.rs @@ -1,6 +1,7 @@ use std::mem; use rustc_arena::TypedArena; +use rustc_span::ErrorGuaranteed; use crate::ty::TyCtxt; @@ -51,6 +52,21 @@ fn alloc_in_arena( } } +impl<'tcx, T> ArenaCached<'tcx> for Result<&'tcx T, ErrorGuaranteed> { + type Provided = Result; + /// The provide value is `Result`, but we only store `T` in the arena. + type Allocated = T; + + fn alloc_in_arena( + tcx: TyCtxt<'tcx>, + typed_arena: &'tcx TypedArena, + value: Result, + ) -> Self { + // Don't store Err(ErrorGuaranteed) in the arena, and wrap the allocated reference in Ok. + try { do_alloc(tcx, typed_arena, value?) } + } +} + /// Allocates a value in either its dedicated arena, or in the common dropless /// arena, depending on whether it needs to be dropped. fn do_alloc<'tcx, T>(tcx: TyCtxt<'tcx>, typed_arena: &'tcx TypedArena, value: T) -> &'tcx T { diff --git a/compiler/rustc_middle/src/query/job.rs b/compiler/rustc_middle/src/query/job.rs index 24c4daf9855d..8c78bf24287e 100644 --- a/compiler/rustc_middle/src/query/job.rs +++ b/compiler/rustc_middle/src/query/job.rs @@ -36,10 +36,7 @@ pub fn new(id: QueryJobId, span: Span, parent: Option) -> Self { } pub fn latch(&mut self) -> QueryLatch<'tcx> { - if self.latch.is_none() { - self.latch = Some(QueryLatch::new()); - } - self.latch.as_ref().unwrap().clone() + self.latch.get_or_insert_with(QueryLatch::new).clone() } /// Signals to waiters that the query is complete. diff --git a/compiler/rustc_middle/src/query/plumbing.rs b/compiler/rustc_middle/src/query/plumbing.rs index b0c6a8a508cc..fe3054dc18e6 100644 --- a/compiler/rustc_middle/src/query/plumbing.rs +++ b/compiler/rustc_middle/src/query/plumbing.rs @@ -99,12 +99,11 @@ pub struct QueryVTable<'tcx, C: QueryCache> { pub will_cache_on_disk_for_key_fn: fn(key: C::Key) -> bool, - pub try_load_from_disk_fn: fn( - tcx: TyCtxt<'tcx>, - key: C::Key, - prev_index: SerializedDepNodeIndex, - index: DepNodeIndex, - ) -> Option, + /// Function pointer that tries to load a query value from disk. + /// + /// This should only be called after a successful check of `will_cache_on_disk_for_key_fn`. + pub try_load_from_disk_fn: + fn(tcx: TyCtxt<'tcx>, prev_index: SerializedDepNodeIndex) -> Option, /// Function pointer that hashes this query's result values. /// @@ -167,6 +166,8 @@ pub struct QuerySystem<'tcx> { pub extern_providers: ExternProviders, pub jobs: AtomicU64, + + pub cycle_handler_nesting: Lock, } #[derive(Copy, Clone)] @@ -447,6 +448,11 @@ pub fn description(&self, tcx: TyCtxt<'tcx>) -> String { } } + /// Calls `self.description` or returns a fallback if there was a fatal error + pub fn catch_description(&self, tcx: TyCtxt<'tcx>) -> String { + catch_fatal_errors(|| self.description(tcx)).unwrap_or_else(|_| format!("", self.query_name())) + } + /// Returns the default span for this query if `span` is a dummy span. pub fn default_span(&self, tcx: TyCtxt<'tcx>, span: Span) -> Span { if !span.is_dummy() { @@ -464,6 +470,11 @@ pub fn default_span(&self, tcx: TyCtxt<'tcx>, span: Span) -> Span { )* } } + + /// Calls `self.default_span` or returns `DUMMY_SP` if there was a fatal error + pub fn catch_default_span(&self, tcx: TyCtxt<'tcx>, span: Span) -> Span { + catch_fatal_errors(|| self.default_span(tcx, span)).unwrap_or(DUMMY_SP) + } } /// Holds a `QueryVTable` for each query. diff --git a/compiler/rustc_middle/src/ty/context.rs b/compiler/rustc_middle/src/ty/context.rs index f0707cfbbb40..ffe9319b47f3 100644 --- a/compiler/rustc_middle/src/ty/context.rs +++ b/compiler/rustc_middle/src/ty/context.rs @@ -32,7 +32,7 @@ use rustc_errors::{Applicability, Diag, DiagCtxtHandle, Diagnostic, MultiSpan}; use rustc_hir::def::DefKind; use rustc_hir::def_id::{CrateNum, DefId, LOCAL_CRATE, LocalDefId}; -use rustc_hir::definitions::{DefPathData, Definitions, DisambiguatorState}; +use rustc_hir::definitions::{DefPathData, Definitions, Disambiguator}; use rustc_hir::intravisit::VisitorExt; use rustc_hir::lang_items::LangItem; use rustc_hir::limit::Limit; @@ -44,10 +44,12 @@ use rustc_session::cstore::{CrateStoreDyn, Untracked}; use rustc_session::lint::Lint; use rustc_span::def_id::{CRATE_DEF_ID, DefPathHash, StableCrateId}; -use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw}; +use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw, sym}; use rustc_type_ir::TyKind::*; pub use rustc_type_ir::lift::Lift; -use rustc_type_ir::{CollectAndApply, TypeFlags, WithCachedTypeInfo, elaborate, search_graph}; +use rustc_type_ir::{ + CollectAndApply, FnSigKind, TypeFlags, WithCachedTypeInfo, elaborate, search_graph, +}; use tracing::{debug, instrument}; use crate::arena::Arena; @@ -84,7 +86,33 @@ fn as_local(self) -> Option { } } +impl<'tcx> rustc_type_ir::inherent::FSigKind> for FnSigKind { + fn fn_sig_kind(self) -> Self { + self + } + + fn new(abi: ExternAbi, safety: hir::Safety, c_variadic: bool) -> Self { + FnSigKind::default().set_abi(abi).set_safe(safety.is_safe()).set_c_variadic(c_variadic) + } + + fn abi(self) -> ExternAbi { + self.abi() + } + + fn safety(self) -> hir::Safety { + if self.is_safe() { hir::Safety::Safe } else { hir::Safety::Unsafe } + } + + fn c_variadic(self) -> bool { + self.c_variadic() + } +} + impl<'tcx> rustc_type_ir::inherent::Abi> for ExternAbi { + fn abi(self) -> Self { + self + } + fn rust() -> Self { ExternAbi::Rust } @@ -92,6 +120,14 @@ fn rust() -> Self { fn is_rust(self) -> bool { matches!(self, ExternAbi::Rust) } + + fn pack_abi(self) -> u8 { + self.as_packed() + } + + fn unpack_abi(abi_index: u8) -> Self { + Self::from_packed(abi_index) + } } impl<'tcx> rustc_type_ir::inherent::Safety> for hir::Safety { @@ -99,6 +135,10 @@ fn safe() -> Self { hir::Safety::Safe } + fn unsafe_mode() -> Self { + hir::Safety::Unsafe + } + fn is_safe(self) -> bool { self.is_safe() } @@ -708,7 +748,7 @@ pub fn feed_hir(&self) { let attrs = hir::AttributeMap::EMPTY; let rustc_middle::hir::Hashes { opt_hash_including_bodies, .. } = - self.tcx.hash_owner_nodes(node, &bodies, &attrs.map, &[], attrs.define_opaque); + self.tcx.hash_owner_nodes(node, &bodies, &attrs.map, attrs.define_opaque); let node = node.into(); self.opt_hir_owner_nodes(Some(self.tcx.arena.alloc(hir::OwnerNodes { opt_hash_including_bodies, @@ -1332,7 +1372,10 @@ pub fn adjust_target_feature_sig( let fun_features = &self.codegen_fn_attrs(fun_def).target_features; let caller_features = &self.body_codegen_attrs(caller).target_features; if self.is_target_feature_call_safe(&fun_features, &caller_features) { - return Some(fun_sig.map_bound(|sig| ty::FnSig { safety: hir::Safety::Safe, ..sig })); + return Some(fun_sig.map_bound(|sig| ty::FnSig { + fn_sig_kind: fun_sig.fn_sig_kind().set_safe(true), + ..sig + })); } None } @@ -1355,7 +1398,7 @@ pub fn create_def( name: Option, def_kind: DefKind, override_def_path_data: Option, - disambiguator: &mut DisambiguatorState, + disambiguator: &mut impl Disambiguator, ) -> TyCtxtFeed<'tcx, LocalDefId> { let feed = self.tcx.create_def(parent, name, def_kind, override_def_path_data, disambiguator); @@ -1373,7 +1416,7 @@ pub fn create_def( name: Option, def_kind: DefKind, override_def_path_data: Option, - disambiguator: &mut DisambiguatorState, + disambiguator: &mut impl Disambiguator, ) -> TyCtxtFeed<'tcx, LocalDefId> { let data = override_def_path_data.unwrap_or_else(|| def_kind.def_path_data(name)); // The following call has the side effect of modifying the tables inside `definitions`. @@ -1705,6 +1748,10 @@ struct UnusedFeature { // in downstream crates. It should never be linted, but should we // hack this in the linter to ignore it? && f.as_str() != "restricted_std" + // `doc_cfg` affects rustdoc behavior: rustdoc checks it via + // `tcx.features().doc_cfg()`, but a normal rustc compilation may + // never observe that use. Do not lint it as unused here. + && *f != sym::doc_cfg }) .collect::>(); @@ -2092,7 +2139,10 @@ impl<'tcx> TyCtxt<'tcx> { /// unsafe. pub fn safe_to_unsafe_fn_ty(self, sig: PolyFnSig<'tcx>) -> Ty<'tcx> { assert!(sig.safety().is_safe()); - Ty::new_fn_ptr(self, sig.map_bound(|sig| ty::FnSig { safety: hir::Safety::Unsafe, ..sig })) + Ty::new_fn_ptr( + self, + sig.map_bound(|sig| ty::FnSig { fn_sig_kind: sig.fn_sig_kind.set_safe(false), ..sig }), + ) } /// Given a `fn` sig, returns an equivalent `unsafe fn` sig; @@ -2100,7 +2150,7 @@ pub fn safe_to_unsafe_fn_ty(self, sig: PolyFnSig<'tcx>) -> Ty<'tcx> { /// unsafe. pub fn safe_to_unsafe_sig(self, sig: PolyFnSig<'tcx>) -> PolyFnSig<'tcx> { assert!(sig.safety().is_safe()); - sig.map_bound(|sig| ty::FnSig { safety: hir::Safety::Unsafe, ..sig }) + sig.map_bound(|sig| ty::FnSig { fn_sig_kind: sig.fn_sig_kind.set_safe(false), ..sig }) } /// Given the def_id of a Trait `trait_def_id` and the name of an associated item `assoc_name` @@ -2142,7 +2192,11 @@ pub fn signature_unclosure(self, sig: PolyFnSig<'tcx>, safety: hir::Safety) -> P ty::Tuple(params) => *params, _ => bug!(), }; - self.mk_fn_sig(params, s.output(), s.c_variadic, safety, ExternAbi::Rust) + self.mk_fn_sig( + params, + s.output(), + s.fn_sig_kind.set_safe(safety.is_safe()).set_abi(ExternAbi::Rust), + ) }) } @@ -2415,26 +2469,40 @@ pub fn mk_const_list_from_iter(self, iter: I) -> T::Output // IntoIterator` instead of `I: Iterator`, and it doesn't have a slice // variant, because of the need to combine `inputs` and `output`. This // explains the lack of `_from_iter` suffix. - pub fn mk_fn_sig( - self, - inputs: I, - output: I::Item, - c_variadic: bool, - safety: hir::Safety, - abi: ExternAbi, - ) -> T::Output + pub fn mk_fn_sig(self, inputs: I, output: I::Item, fn_sig_kind: FnSigKind) -> T::Output where I: IntoIterator, T: CollectAndApply, ty::FnSig<'tcx>>, { T::collect_and_apply(inputs.into_iter().chain(iter::once(output)), |xs| ty::FnSig { inputs_and_output: self.mk_type_list(xs), - c_variadic, - safety, - abi, + fn_sig_kind, }) } + /// `mk_fn_sig`, but with a Rust ABI, and no C-variadic argument. + pub fn mk_fn_sig_rust_abi( + self, + inputs: I, + output: I::Item, + safety: hir::Safety, + ) -> T::Output + where + I: IntoIterator, + T: CollectAndApply, ty::FnSig<'tcx>>, + { + self.mk_fn_sig(inputs, output, FnSigKind::default().set_safe(safety.is_safe())) + } + + /// `mk_fn_sig`, but with a safe Rust ABI, and no C-variadic argument. + pub fn mk_fn_sig_safe_rust_abi(self, inputs: I, output: I::Item) -> T::Output + where + I: IntoIterator, + T: CollectAndApply, ty::FnSig<'tcx>>, + { + self.mk_fn_sig(inputs, output, FnSigKind::default().set_safe(true)) + } + pub fn mk_poly_existential_predicates_from_iter(self, iter: I) -> T::Output where I: Iterator, diff --git a/compiler/rustc_middle/src/ty/context/impl_interner.rs b/compiler/rustc_middle/src/ty/context/impl_interner.rs index 9913261b14d9..61e9b6106a1a 100644 --- a/compiler/rustc_middle/src/ty/context/impl_interner.rs +++ b/compiler/rustc_middle/src/ty/context/impl_interner.rs @@ -10,7 +10,7 @@ use rustc_hir::lang_items::LangItem; use rustc_span::{DUMMY_SP, Span, Symbol}; use rustc_type_ir::lang_items::{SolverAdtLangItem, SolverLangItem, SolverTraitLangItem}; -use rustc_type_ir::{CollectAndApply, Interner, TypeFoldable, search_graph}; +use rustc_type_ir::{CollectAndApply, FnSigKind, Interner, TypeFoldable, search_graph}; use crate::dep_graph::{DepKind, DepNodeIndex}; use crate::infer::canonical::CanonicalVarKinds; @@ -90,6 +90,7 @@ fn with_cached_task(self, task: impl FnOnce() -> T) -> (T, DepNodeIndex) { type AllocId = crate::mir::interpret::AllocId; type Pat = Pattern<'tcx>; type PatList = &'tcx List>; + type FSigKind = FnSigKind; type Safety = hir::Safety; type Abi = ExternAbi; type Const = ty::Const<'tcx>; diff --git a/compiler/rustc_middle/src/ty/generics.rs b/compiler/rustc_middle/src/ty/generics.rs index ed587cbc3c28..11a236f314c2 100644 --- a/compiler/rustc_middle/src/ty/generics.rs +++ b/compiler/rustc_middle/src/ty/generics.rs @@ -274,6 +274,10 @@ pub fn has_impl_trait(&'tcx self) -> bool { }) } + pub fn own_synthetic_params_count(&'tcx self) -> usize { + self.own_params.iter().filter(|p| p.kind.is_synthetic()).count() + } + /// Returns the args corresponding to the generic parameters /// of this item, excluding `Self`. /// diff --git a/compiler/rustc_middle/src/ty/layout.rs b/compiler/rustc_middle/src/ty/layout.rs index 969d65494180..4554900285d3 100644 --- a/compiler/rustc_middle/src/ty/layout.rs +++ b/compiler/rustc_middle/src/ty/layout.rs @@ -317,12 +317,6 @@ pub enum SizeSkeleton<'tcx> { /// Alignment can be `None` if unknown. Known(Size, Option), - /// This is a generic const expression (i.e. N * 2), which may contain some parameters. - /// It must be of type usize, and represents the size of a type in bytes. - /// It is not required to be evaluatable to a concrete value, but can be used to check - /// that another SizeSkeleton is of equal size. - Generic(ty::Const<'tcx>), - /// A potentially-wide pointer. Pointer { /// If true, this pointer is never null. @@ -426,7 +420,7 @@ pub fn compute( } Err(err) } - SizeSkeleton::Pointer { .. } | SizeSkeleton::Generic(_) => Err(err), + SizeSkeleton::Pointer { .. } => Err(err), } } @@ -460,9 +454,6 @@ pub fn compute( } ptr = Some(field); } - SizeSkeleton::Generic(_) => { - return Err(err); - } } } Ok(ptr) @@ -508,8 +499,21 @@ pub fn compute( } } - // Pattern types are always the same size as their base. - ty::Pat(base, _) => SizeSkeleton::compute(base, tcx, typing_env), + ty::Pat(base, pat) => { + // Pattern types are always the same size as their base. + let base = SizeSkeleton::compute(base, tcx, typing_env); + match *pat { + ty::PatternKind::Range { .. } | ty::PatternKind::Or(_) => base, + // But in the case of `!null` patterns we need to note that in the + // raw pointer. + ty::PatternKind::NotNull => match base? { + SizeSkeleton::Known(..) => base, + SizeSkeleton::Pointer { non_zero: _, tail } => { + Ok(SizeSkeleton::Pointer { non_zero: true, tail }) + } + }, + } + } _ => Err(err), } @@ -521,9 +525,6 @@ pub fn same_size(self, other: SizeSkeleton<'tcx>) -> bool { (SizeSkeleton::Pointer { tail: a, .. }, SizeSkeleton::Pointer { tail: b, .. }) => { a == b } - // constants are always pre-normalized into a canonical form so this - // only needs to check if their pointers are identical. - (SizeSkeleton::Generic(a), SizeSkeleton::Generic(b)) => a == b, _ => false, } } diff --git a/compiler/rustc_middle/src/ty/list.rs b/compiler/rustc_middle/src/ty/list.rs index a2bbc1ec75b9..ed5a48b094f2 100644 --- a/compiler/rustc_middle/src/ty/list.rs +++ b/compiler/rustc_middle/src/ty/list.rs @@ -275,9 +275,6 @@ unsafe impl DynSync for RawList {} // `_extern_ty` field (which is never instantiated in practice). Therefore, // aligns of `ListSkeleton` and `RawList` must be the same. unsafe impl Aligned for RawList { - #[cfg(bootstrap)] - const ALIGN: ptr::Alignment = align_of::>(); - #[cfg(not(bootstrap))] const ALIGN: mem::Alignment = align_of::>(); } diff --git a/compiler/rustc_middle/src/ty/mod.rs b/compiler/rustc_middle/src/ty/mod.rs index 36a474688f07..5261ee8f620f 100644 --- a/compiler/rustc_middle/src/ty/mod.rs +++ b/compiler/rustc_middle/src/ty/mod.rs @@ -40,6 +40,7 @@ use rustc_hir::attrs::StrippedCfgItem; use rustc_hir::def::{CtorKind, CtorOf, DefKind, DocLinkResMap, LifetimeRes, Res}; use rustc_hir::def_id::{CrateNum, DefId, DefIdMap, LocalDefId, LocalDefIdMap}; +use rustc_hir::definitions::PerParentDisambiguatorState; use rustc_hir::{LangItem, attrs as attr, find_attr}; use rustc_index::IndexVec; use rustc_index::bit_set::BitMatrix; @@ -96,7 +97,8 @@ PolyExistentialPredicate, PolyExistentialProjection, PolyExistentialTraitRef, PolyProjectionPredicate, PolyRegionOutlivesPredicate, PolySubtypePredicate, PolyTraitPredicate, PolyTraitRef, PolyTypeOutlivesPredicate, Predicate, PredicateKind, ProjectionPredicate, - RegionOutlivesPredicate, SubtypePredicate, TraitPredicate, TraitRef, TypeOutlivesPredicate, + RegionConstraint, RegionEqPredicate, RegionOutlivesPredicate, SubtypePredicate, TraitPredicate, + TraitRef, TypeOutlivesPredicate, }; pub use self::region::{ EarlyParamRegion, LateParamRegion, LateParamRegionKind, Region, RegionKind, RegionVid, @@ -104,8 +106,9 @@ pub use self::sty::{ AliasTy, AliasTyKind, Article, Binder, BoundConst, BoundRegion, BoundRegionKind, BoundTy, BoundTyKind, BoundVariableKind, CanonicalPolyFnSig, CoroutineArgsExt, EarlyBinder, FnSig, - InlineConstArgs, InlineConstArgsParts, ParamConst, ParamTy, PlaceholderConst, - PlaceholderRegion, PlaceholderType, PolyFnSig, TyKind, TypeAndMut, TypingMode, UpvarArgs, + FnSigKind, InlineConstArgs, InlineConstArgsParts, ParamConst, ParamTy, PlaceholderConst, + PlaceholderRegion, PlaceholderType, PolyFnSig, TyKind, TypeAndMut, TypingMode, + TypingModeEqWrapper, UpvarArgs, }; pub use self::trait_def::TraitDef; pub use self::typeck_results::{ @@ -223,6 +226,8 @@ pub struct ResolverAstLowering<'tcx> { // Information about delegations which is used when handling recursive delegations pub delegation_infos: LocalDefIdMap, + + pub per_parent_disambiguators: LocalDefIdMap>, } #[derive(Debug)] @@ -688,7 +693,7 @@ fn pack(self) -> Term<'tcx> { /// `[[], [U:Bar]]`. Now if there were some particular reference /// like `Foo`, then the `InstantiatedPredicates` would be `[[], /// [usize:Bar]]`. -#[derive(Clone, Debug, TypeFoldable, TypeVisitable)] +#[derive(Clone, Debug)] pub struct InstantiatedPredicates<'tcx> { pub predicates: Vec>, pub spans: Vec, @@ -980,11 +985,19 @@ pub struct ParamEnvAnd<'tcx, T> { pub struct TypingEnv<'tcx> { #[type_foldable(identity)] #[type_visitable(ignore)] - pub typing_mode: TypingMode<'tcx>, + typing_mode: TypingModeEqWrapper<'tcx>, pub param_env: ParamEnv<'tcx>, } impl<'tcx> TypingEnv<'tcx> { + pub fn new(param_env: ParamEnv<'tcx>, typing_mode: TypingMode<'tcx>) -> Self { + Self { typing_mode: TypingModeEqWrapper(typing_mode), param_env } + } + + pub fn typing_mode(&self) -> TypingMode<'tcx> { + self.typing_mode.0 + } + /// Create a typing environment with no where-clauses in scope /// where all opaque types and default associated items are revealed. /// @@ -993,7 +1006,7 @@ impl<'tcx> TypingEnv<'tcx> { /// use `TypingMode::PostAnalysis`, they may still have where-clauses /// in scope. pub fn fully_monomorphized() -> TypingEnv<'tcx> { - TypingEnv { typing_mode: TypingMode::PostAnalysis, param_env: ParamEnv::empty() } + Self::new(ParamEnv::empty(), TypingMode::PostAnalysis) } /// Create a typing environment for use during analysis outside of a body. @@ -1006,7 +1019,7 @@ pub fn non_body_analysis( def_id: impl IntoQueryKey, ) -> TypingEnv<'tcx> { let def_id = def_id.into_query_key(); - TypingEnv { typing_mode: TypingMode::non_body_analysis(), param_env: tcx.param_env(def_id) } + Self::new(tcx.param_env(def_id), TypingMode::non_body_analysis()) } pub fn post_analysis(tcx: TyCtxt<'tcx>, def_id: impl IntoQueryKey) -> TypingEnv<'tcx> { @@ -1018,8 +1031,12 @@ pub fn post_analysis(tcx: TyCtxt<'tcx>, def_id: impl IntoQueryKey) -> Typ /// opaque types in the `param_env`. pub fn with_post_analysis_normalized(self, tcx: TyCtxt<'tcx>) -> TypingEnv<'tcx> { let TypingEnv { typing_mode, param_env } = self; - if let TypingMode::PostAnalysis = typing_mode { - return self; + match typing_mode.0 { + TypingMode::Coherence + | TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } => {} + TypingMode::PostAnalysis => return self, } // No need to reveal opaques with the new solver enabled, @@ -1029,7 +1046,7 @@ pub fn with_post_analysis_normalized(self, tcx: TyCtxt<'tcx>) -> TypingEnv<'tcx> } else { ParamEnv::new(tcx.reveal_opaque_types_in_bounds(param_env.caller_bounds())) }; - TypingEnv { typing_mode: TypingMode::PostAnalysis, param_env } + TypingEnv { typing_mode: TypingModeEqWrapper(TypingMode::PostAnalysis), param_env } } /// Combine this typing environment with the given `value` to be used by @@ -1723,24 +1740,6 @@ pub fn get_attrs_by_path( } } - #[deprecated = "Though there are valid usecases for this method, especially when your attribute is not a parsed attribute, usually you want to call rustc_hir::find_attr! instead."] - pub fn get_attr(self, did: impl Into, attr: Symbol) -> Option<&'tcx hir::Attribute> { - #[allow(deprecated)] - self.get_attrs(did, attr).next() - } - - /// Determines whether an item is annotated with an attribute. - #[deprecated = "Though there are valid usecases for this method, especially when your attribute is not a parsed attribute, usually you want to call rustc_hir::find_attr! instead."] - pub fn has_attr(self, did: impl Into, attr: Symbol) -> bool { - #[allow(deprecated)] - self.get_attrs(did, attr).next().is_some() - } - - /// Determines whether an item is annotated with a multi-segment attribute - pub fn has_attrs_with_path(self, did: impl Into, attrs: &[Symbol]) -> bool { - self.get_attrs_by_path(did.into(), attrs).next().is_some() - } - /// Returns `true` if this is an `auto trait`. pub fn trait_is_auto(self, trait_def_id: DefId) -> bool { self.trait_def(trait_def_id).has_auto_impl diff --git a/compiler/rustc_middle/src/ty/predicate.rs b/compiler/rustc_middle/src/ty/predicate.rs index 3baeb7141de5..4d9f08a3e58a 100644 --- a/compiler/rustc_middle/src/ty/predicate.rs +++ b/compiler/rustc_middle/src/ty/predicate.rs @@ -26,6 +26,8 @@ pub type RegionOutlivesPredicate<'tcx> = OutlivesPredicate<'tcx, ty::Region<'tcx>>; pub type TypeOutlivesPredicate<'tcx> = OutlivesPredicate<'tcx, Ty<'tcx>>; pub type ArgOutlivesPredicate<'tcx> = OutlivesPredicate<'tcx, ty::GenericArg<'tcx>>; +pub type RegionEqPredicate<'tcx> = ir::RegionEqPredicate>; +pub type RegionConstraint<'tcx> = ir::RegionConstraint>; pub type PolyTraitPredicate<'tcx> = ty::Binder<'tcx, TraitPredicate<'tcx>>; pub type PolyRegionOutlivesPredicate<'tcx> = ty::Binder<'tcx, RegionOutlivesPredicate<'tcx>>; pub type PolyTypeOutlivesPredicate<'tcx> = ty::Binder<'tcx, TypeOutlivesPredicate<'tcx>>; diff --git a/compiler/rustc_middle/src/ty/print/pretty.rs b/compiler/rustc_middle/src/ty/print/pretty.rs index 1262974325a1..a96bf2c2277a 100644 --- a/compiler/rustc_middle/src/ty/print/pretty.rs +++ b/compiler/rustc_middle/src/ty/print/pretty.rs @@ -750,7 +750,7 @@ fn pretty_print_type(&mut self, ty: Ty<'tcx>) -> Result<(), PrintError> { if self.tcx().codegen_fn_attrs(def_id).safe_target_features { write!(self, "#[target_features] ")?; sig = sig.map_bound(|mut sig| { - sig.safety = hir::Safety::Safe; + sig.fn_sig_kind = sig.fn_sig_kind.set_safe(true); sig }); } @@ -2172,7 +2172,6 @@ fn guess_def_namespace(tcx: TyCtxt<'_>, def_id: DefId) -> Namespace { DefPathData::ValueNs(..) | DefPathData::AnonConst - | DefPathData::LateAnonConst | DefPathData::Closure | DefPathData::Ctor => Namespace::ValueNS, @@ -3131,14 +3130,14 @@ macro_rules! define_print_and_forward_display { (self, p): ty::FnSig<'tcx> { - write!(p, "{}", self.safety.prefix_str())?; + write!(p, "{}", self.safety().prefix_str())?; - if self.abi != ExternAbi::Rust { - write!(p, "extern {} ", self.abi)?; + if self.abi() != ExternAbi::Rust { + write!(p, "extern {} ", self.abi())?; } write!(p, "fn")?; - p.pretty_print_fn_sig(self.inputs(), self.c_variadic, self.output())?; + p.pretty_print_fn_sig(self.inputs(), self.c_variadic(), self.output())?; } ty::TraitRef<'tcx> { diff --git a/compiler/rustc_middle/src/ty/structural_impls.rs b/compiler/rustc_middle/src/ty/structural_impls.rs index 29b784e83795..f6d5d226683b 100644 --- a/compiler/rustc_middle/src/ty/structural_impls.rs +++ b/compiler/rustc_middle/src/ty/structural_impls.rs @@ -198,6 +198,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { rustc_hir::Safety, rustc_middle::mir::ConstValue, rustc_type_ir::BoundConstness, + rustc_type_ir::FnSigKind, rustc_type_ir::PredicatePolarity, // tidy-alphabetical-end } diff --git a/compiler/rustc_middle/src/ty/sty.rs b/compiler/rustc_middle/src/ty/sty.rs index 08bfe15137a2..cf8206b059ae 100644 --- a/compiler/rustc_middle/src/ty/sty.rs +++ b/compiler/rustc_middle/src/ty/sty.rs @@ -37,9 +37,11 @@ pub type AliasTy<'tcx> = ir::AliasTy>; pub type AliasTyKind<'tcx> = ir::AliasTyKind>; pub type FnSig<'tcx> = ir::FnSig>; +pub type FnSigKind = ir::FnSigKind; pub type Binder<'tcx, T> = ir::Binder, T>; pub type EarlyBinder<'tcx, T> = ir::EarlyBinder, T>; pub type TypingMode<'tcx> = ir::TypingMode>; +pub type TypingModeEqWrapper<'tcx> = ir::TypingModeEqWrapper>; pub type Placeholder<'tcx, T> = ir::Placeholder, T>; pub type PlaceholderRegion<'tcx> = ir::PlaceholderRegion>; pub type PlaceholderType<'tcx> = ir::PlaceholderType>; @@ -1179,6 +1181,14 @@ pub fn ty_vid(self) -> Option { } } + #[inline] + pub fn float_vid(self) -> Option { + match self.kind() { + &Infer(FloatVar(vid)) => Some(vid), + _ => None, + } + } + #[inline] pub fn is_ty_or_numeric_infer(self) -> bool { matches!(self.kind(), Infer(_)) diff --git a/compiler/rustc_middle/src/ty/trait_def.rs b/compiler/rustc_middle/src/ty/trait_def.rs index 3e69eda11ca6..af5d81a108ba 100644 --- a/compiler/rustc_middle/src/ty/trait_def.rs +++ b/compiler/rustc_middle/src/ty/trait_def.rs @@ -12,6 +12,7 @@ use crate::query::LocalCrate; use crate::traits::specialization_graph; use crate::ty::fast_reject::{self, SimplifiedType, TreatParams}; +use crate::ty::print::{with_crate_prefix, with_no_trimmed_paths}; use crate::ty::{Ident, Ty, TyCtxt}; /// A trait's definition with type information. @@ -24,6 +25,9 @@ pub struct TraitDef { /// Whether this trait is `const`. pub constness: hir::Constness, + /// Restrictions on trait implementations. + pub impl_restriction: ImplRestrictionKind, + /// If `true`, then this trait had the `#[rustc_paren_sugar]` /// attribute, indicating that it should be used with `Foo()` /// sugar. This is a temporary thing -- eventually any trait will @@ -97,6 +101,52 @@ pub enum TraitSpecializationKind { AlwaysApplicable, } +/// Whether the trait implementation is unrestricted or restricted within a specific module. +#[derive(HashStable, PartialEq, Clone, Copy, Encodable, Decodable)] +pub enum ImplRestrictionKind { + /// The restriction does not affect this trait, and it can be implemented anywhere. + Unrestricted, + /// This trait can only be implemented within the specified module. + Restricted(DefId, Span), +} + +impl ImplRestrictionKind { + /// Returns `true` if the behavior is allowed/unrestricted in the given module. + /// A value of `false` indicates that the behavior is prohibited. + pub fn is_allowed_in(self, module: DefId, tcx: TyCtxt<'_>) -> bool { + match self { + ImplRestrictionKind::Unrestricted => true, + ImplRestrictionKind::Restricted(restricted_to, _) => { + tcx.is_descendant_of(module, restricted_to) + } + } + } + + /// Obtain the [`Span`] of the restriction. Panics if the restriction is unrestricted. + pub fn expect_span(self) -> Span { + match self { + ImplRestrictionKind::Unrestricted => { + bug!("called `expect_span` on an unrestricted item") + } + ImplRestrictionKind::Restricted(_, span) => span, + } + } + + /// Obtain the path of the restriction. If unrestricted, an empty string is returned. + pub fn restriction_path(self, tcx: TyCtxt<'_>) -> String { + match self { + ImplRestrictionKind::Unrestricted => String::new(), + ImplRestrictionKind::Restricted(restricted_to, _) => { + if restricted_to.krate == rustc_hir::def_id::LOCAL_CRATE { + with_crate_prefix!(with_no_trimmed_paths!(tcx.def_path_str(restricted_to))) + } else { + tcx.def_path_str(restricted_to.krate.as_mod_def_id()) + } + } + } + } +} + #[derive(Default, Debug, HashStable)] pub struct TraitImpls { blanket_impls: Vec, diff --git a/compiler/rustc_mir_build/src/builder/matches/match_pair.rs b/compiler/rustc_mir_build/src/builder/matches/match_pair.rs index bd18a215aea7..e2d00238e2d5 100644 --- a/compiler/rustc_mir_build/src/builder/matches/match_pair.rs +++ b/compiler/rustc_mir_build/src/builder/matches/match_pair.rs @@ -12,77 +12,58 @@ FlatPat, MatchPairTree, PatConstKind, PatternExtraData, SliceLenOp, TestableCase, }; -impl<'a, 'tcx> Builder<'a, 'tcx> { - /// Builds and pushes [`MatchPairTree`] subtrees, one for each pattern in - /// `subpatterns`, representing the fields of a [`PatKind::Variant`] or - /// [`PatKind::Leaf`]. - /// - /// Used internally by [`MatchPairTree::for_pattern`]. - fn field_match_pairs( - &mut self, - match_pairs: &mut Vec>, - extra_data: &mut PatternExtraData<'tcx>, - place: PlaceBuilder<'tcx>, - subpatterns: &[FieldPat<'tcx>], - ) { - for fieldpat in subpatterns { - let place = place.clone_project(PlaceElem::Field(fieldpat.field, fieldpat.pattern.ty)); - MatchPairTree::for_pattern(place, &fieldpat.pattern, self, match_pairs, extra_data); - } +/// For an array or slice pattern's subpatterns (prefix/slice/suffix), returns a list +/// of those subpatterns, each paired with a suitably-projected [`PlaceBuilder`]. +fn prefix_slice_suffix<'a, 'tcx>( + place: &PlaceBuilder<'tcx>, + array_len: Option, // Some for array patterns; None for slice patterns + prefix: &'a [Pat<'tcx>], + opt_slice: &'a Option>>, + suffix: &'a [Pat<'tcx>], +) -> Vec<(PlaceBuilder<'tcx>, &'a Pat<'tcx>)> { + let prefix_len = u64::try_from(prefix.len()).unwrap(); + let suffix_len = u64::try_from(suffix.len()).unwrap(); + + let mut output_pairs = + Vec::with_capacity(prefix.len() + usize::from(opt_slice.is_some()) + suffix.len()); + + // For slice patterns with a `..` followed by 0 or more suffix subpatterns, + // the actual slice index of those subpatterns isn't statically known, so + // we have to index them relative to the end of the slice. + // + // For array patterns, all subpatterns are indexed relative to the start. + let (min_length, is_array) = match array_len { + Some(len) => (len, true), + None => (prefix_len + suffix_len, false), + }; + + for (offset, prefix_subpat) in (0u64..).zip(prefix) { + let elem = ProjectionElem::ConstantIndex { offset, min_length, from_end: false }; + let subplace = place.clone_project(elem); + output_pairs.push((subplace, prefix_subpat)); } - /// Builds [`MatchPairTree`] subtrees for the prefix/middle/suffix parts of an - /// array pattern or slice pattern, and adds those trees to `match_pairs`. - /// - /// Used internally by [`MatchPairTree::for_pattern`]. - fn prefix_slice_suffix( - &mut self, - match_pairs: &mut Vec>, - extra_data: &mut PatternExtraData<'tcx>, - place: &PlaceBuilder<'tcx>, - array_len: Option, - prefix: &[Pat<'tcx>], - opt_slice: &Option>>, - suffix: &[Pat<'tcx>], - ) { - let prefix_len = u64::try_from(prefix.len()).unwrap(); - let suffix_len = u64::try_from(suffix.len()).unwrap(); - - // For slice patterns with a `..` followed by 0 or more suffix subpatterns, - // the actual slice index of those subpatterns isn't statically known, so - // we have to index them relative to the end of the slice. - // - // For array patterns, all subpatterns are indexed relative to the start. - let (min_length, is_array) = match array_len { - Some(len) => (len, true), - None => (prefix_len + suffix_len, false), + if let Some(slice_subpat) = opt_slice { + let elem = PlaceElem::Subslice { + from: prefix_len, + to: if is_array { min_length - suffix_len } else { suffix_len }, + from_end: !is_array, }; - - for (offset, subpattern) in (0u64..).zip(prefix) { - let elem = ProjectionElem::ConstantIndex { offset, min_length, from_end: false }; - let place = place.clone_project(elem); - MatchPairTree::for_pattern(place, subpattern, self, match_pairs, extra_data) - } - - if let Some(subslice_pat) = opt_slice { - let subslice = place.clone_project(PlaceElem::Subslice { - from: prefix_len, - to: if is_array { min_length - suffix_len } else { suffix_len }, - from_end: !is_array, - }); - MatchPairTree::for_pattern(subslice, subslice_pat, self, match_pairs, extra_data); - } - - for (end_offset, subpattern) in (1u64..).zip(suffix.iter().rev()) { - let elem = ProjectionElem::ConstantIndex { - offset: if is_array { min_length - end_offset } else { end_offset }, - min_length, - from_end: !is_array, - }; - let place = place.clone_project(elem); - MatchPairTree::for_pattern(place, subpattern, self, match_pairs, extra_data) - } + let subplace = place.clone_project(elem); + output_pairs.push((subplace, slice_subpat)); } + + for (offset_from_end, suffix_subpat) in (1u64..).zip(suffix.iter().rev()) { + let elem = ProjectionElem::ConstantIndex { + offset: if is_array { min_length - offset_from_end } else { offset_from_end }, + min_length, + from_end: !is_array, + }; + let subplace = place.clone_project(elem); + output_pairs.push((subplace, suffix_subpat)); + } + + output_pairs } impl<'tcx> MatchPairTree<'tcx> { @@ -239,15 +220,11 @@ pub(super) fn for_pattern( _ => None, }; if let Some(array_len) = array_len { - cx.prefix_slice_suffix( - &mut subpairs, - extra_data, - &place_builder, - Some(array_len), - prefix, - slice, - suffix, - ); + for (subplace, subpat) in + prefix_slice_suffix(&place_builder, Some(array_len), prefix, slice, suffix) + { + MatchPairTree::for_pattern(subplace, subpat, cx, &mut subpairs, extra_data); + } } else { // If the array length couldn't be determined, ignore the // subpatterns and delayed-assert that compilation will fail. @@ -263,15 +240,11 @@ pub(super) fn for_pattern( None } PatKind::Slice { ref prefix, ref slice, ref suffix } => { - cx.prefix_slice_suffix( - &mut subpairs, - extra_data, - &place_builder, - None, - prefix, - slice, - suffix, - ); + for (subplace, subpat) in + prefix_slice_suffix(&place_builder, None, prefix, slice, suffix) + { + MatchPairTree::for_pattern(subplace, subpat, cx, &mut subpairs, extra_data); + } if prefix.is_empty() && slice.is_some() && suffix.is_empty() { // This pattern is shaped like `[..]`. It can match a slice @@ -294,7 +267,10 @@ pub(super) fn for_pattern( PatKind::Variant { adt_def, variant_index, args: _, ref subpatterns } => { let downcast_place = place_builder.downcast(adt_def, variant_index); // `(x as Variant)` - cx.field_match_pairs(&mut subpairs, extra_data, downcast_place, subpatterns); + for &FieldPat { field, pattern: ref subpat } in subpatterns { + let subplace = downcast_place.clone_project(PlaceElem::Field(field, subpat.ty)); + MatchPairTree::for_pattern(subplace, subpat, cx, &mut subpairs, extra_data); + } // We treat non-exhaustive enums the same independent of the crate they are // defined in, to avoid differences in the operational semantics between crates. @@ -308,7 +284,10 @@ pub(super) fn for_pattern( } PatKind::Leaf { ref subpatterns } => { - cx.field_match_pairs(&mut subpairs, extra_data, place_builder, subpatterns); + for &FieldPat { field, pattern: ref subpat } in subpatterns { + let subplace = place_builder.clone_project(PlaceElem::Field(field, subpat.ty)); + MatchPairTree::for_pattern(subplace, subpat, cx, &mut subpairs, extra_data); + } None } diff --git a/compiler/rustc_mir_build/src/builder/mod.rs b/compiler/rustc_mir_build/src/builder/mod.rs index 01c1e2e79b50..8914ff71bcb2 100644 --- a/compiler/rustc_mir_build/src/builder/mod.rs +++ b/compiler/rustc_mir_build/src/builder/mod.rs @@ -470,7 +470,7 @@ fn construct_fn<'tcx>( .output .span(); - let mut abi = fn_sig.abi; + let mut abi = fn_sig.abi(); if let DefKind::Closure = tcx.def_kind(fn_def) { // HACK(eddyb) Avoid having RustCall on closures, // as it adds unnecessary (and wrong) auto-tupling. diff --git a/compiler/rustc_mir_build/src/builder/scope.rs b/compiler/rustc_mir_build/src/builder/scope.rs index ab6368570514..91610e768d01 100644 --- a/compiler/rustc_mir_build/src/builder/scope.rs +++ b/compiler/rustc_mir_build/src/builder/scope.rs @@ -85,8 +85,7 @@ use interpret::ErrorHandled; use rustc_data_structures::fx::FxHashMap; -use rustc_hir::attrs::AttributeKind; -use rustc_hir::{Attribute, HirId}; +use rustc_hir::HirId; use rustc_index::{IndexSlice, IndexVec}; use rustc_middle::middle::region; use rustc_middle::mir::{self, *}; @@ -94,6 +93,7 @@ use rustc_middle::ty::{self, Ty, TyCtxt, TypeVisitableExt, ValTree}; use rustc_middle::{bug, span_bug}; use rustc_pattern_analysis::rustc::RustcPatCtxt; +use rustc_session::lint::Level; use rustc_span::{DUMMY_SP, Span, Spanned}; use tracing::{debug, instrument}; @@ -1298,12 +1298,7 @@ fn maybe_lint_level_root_bounded(&mut self, orig_id: HirId) -> HirId { break; } - if self - .tcx - .hir_attrs(id) - .iter() - .any(|attr| matches!(attr, Attribute::Parsed(AttributeKind::LintAttributes { .. }))) - { + if self.tcx.hir_attrs(id).iter().any(|attr| Level::from_attr(attr).is_some()) { // This is a rare case. It's for a node path that doesn't reach the root due to an // intervening lint level attribute. This result doesn't get cached. return id; diff --git a/compiler/rustc_mir_build/src/check_tail_calls.rs b/compiler/rustc_mir_build/src/check_tail_calls.rs index b8547e288027..0dca1eb062d4 100644 --- a/compiler/rustc_mir_build/src/check_tail_calls.rs +++ b/compiler/rustc_mir_build/src/check_tail_calls.rs @@ -131,12 +131,12 @@ fn check_tail_call(&mut self, call: &Expr<'_>, expr: &Expr<'_>) { let callee_sig = self.tcx.normalize_erasing_late_bound_regions(self.typing_env, ty.fn_sig(self.tcx)); - if caller_sig.abi != callee_sig.abi { - self.report_abi_mismatch(expr.span, caller_sig.abi, callee_sig.abi); + if caller_sig.abi() != callee_sig.abi() { + self.report_abi_mismatch(expr.span, caller_sig.abi(), callee_sig.abi()); } - if !callee_sig.abi.supports_guaranteed_tail_call() { - self.report_unsupported_abi(expr.span, callee_sig.abi); + if !callee_sig.abi().supports_guaranteed_tail_call() { + self.report_unsupported_abi(expr.span, callee_sig.abi()); } // FIXME(explicit_tail_calls): this currently fails for cases where opaques are used. @@ -180,11 +180,11 @@ fn check_tail_call(&mut self, call: &Expr<'_>, expr: &Expr<'_>) { } } - if caller_sig.c_variadic { + if caller_sig.c_variadic() { self.report_c_variadic_caller(expr.span); } - if callee_sig.c_variadic { + if callee_sig.c_variadic() { self.report_c_variadic_callee(expr.span); } } diff --git a/compiler/rustc_mir_build/src/thir/cx/mod.rs b/compiler/rustc_mir_build/src/thir/cx/mod.rs index f22ff92c0178..a1c39950254b 100644 --- a/compiler/rustc_mir_build/src/thir/cx/mod.rs +++ b/compiler/rustc_mir_build/src/thir/cx/mod.rs @@ -184,15 +184,15 @@ fn explicit_params( // Make sure that inferred closure args have no type span .and_then(|ty| if param.pat.span != ty.span { Some(ty.span) } else { None }); - let self_kind = if index == 0 && fn_decl.implicit_self.has_implicit_self() { - Some(fn_decl.implicit_self) + let self_kind = if index == 0 && fn_decl.implicit_self().has_implicit_self() { + Some(fn_decl.implicit_self()) } else { None }; // C-variadic fns also have a `VaList` input that's not listed in `fn_sig` // (as it's created inside the body itself, not passed in from outside). - let ty = if fn_decl.c_variadic && index == fn_decl.inputs.len() { + let ty = if fn_decl.c_variadic() && index == fn_decl.inputs.len() { let va_list_did = self.tcx.require_lang_item(LangItem::VaList, param.span); self.tcx diff --git a/compiler/rustc_mir_transform/src/add_retag.rs b/compiler/rustc_mir_transform/src/add_retag.rs index fc08c1df8703..2a15a40b6402 100644 --- a/compiler/rustc_mir_transform/src/add_retag.rs +++ b/compiler/rustc_mir_transform/src/add_retag.rs @@ -24,6 +24,7 @@ fn may_contain_reference<'tcx>(ty: Ty<'tcx>, depth: u32, tcx: TyCtxt<'tcx>) -> b | ty::Str | ty::FnDef(..) | ty::Never => false, + ty::Pat(base, ..) => may_contain_reference(*base, depth, tcx), // References and Boxes (`noalias` sources) ty::Ref(..) => true, ty::Adt(..) if ty.is_box() => true, diff --git a/compiler/rustc_mir_transform/src/copy_prop.rs b/compiler/rustc_mir_transform/src/copy_prop.rs index e04cb26e8990..8456abc8d269 100644 --- a/compiler/rustc_mir_transform/src/copy_prop.rs +++ b/compiler/rustc_mir_transform/src/copy_prop.rs @@ -3,9 +3,10 @@ use rustc_middle::mir::visit::*; use rustc_middle::mir::*; use rustc_middle::ty::TyCtxt; +use rustc_mir_dataflow::{Analysis, ResultsCursor}; use tracing::{debug, instrument}; -use crate::ssa::SsaLocals; +use crate::ssa::{MaybeUninitializedLocals, SsaLocals}; /// Unify locals that copy each other. /// @@ -16,7 +17,7 @@ /// _d = move? _c /// where each of the locals is only assigned once. /// -/// We want to replace all those locals by `copy _a`. +/// We want to replace all those locals by `_a` (the "head"), either copied or moved. pub(super) struct CopyProp; impl<'tcx> crate::MirPass<'tcx> for CopyProp { @@ -30,15 +31,19 @@ fn run_pass(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) { let typing_env = body.typing_env(tcx); let ssa = SsaLocals::new(tcx, body, typing_env); + debug!(borrowed_locals = ?ssa.borrowed_locals()); debug!(copy_classes = ?ssa.copy_classes()); let mut any_replacement = false; // Locals that participate in copy propagation either as a source or a destination. let mut unified = DenseBitSet::new_empty(body.local_decls.len()); + let mut storage_to_remove = DenseBitSet::new_empty(body.local_decls.len()); + for (local, &head) in ssa.copy_classes().iter_enumerated() { if local != head { any_replacement = true; + storage_to_remove.insert(head); unified.insert(head); unified.insert(local); } @@ -48,7 +53,46 @@ fn run_pass(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) { return; } - Replacer { tcx, copy_classes: ssa.copy_classes(), unified }.visit_body_preserves_cfg(body); + // When emitting storage statements, we want to retain the head locals' storage statements, + // as this enables better optimizations. For each local use location, we mark the head for storage removal + // only if the head might be uninitialized at that point, or if the local is borrowed + // (since we cannot easily determine when it's used). + let storage_to_remove = if tcx.sess.emit_lifetime_markers() { + storage_to_remove.clear(); + + // If the local is borrowed, we cannot easily determine if it is used, so we have to remove the storage statements. + let borrowed_locals = ssa.borrowed_locals(); + + for (local, &head) in ssa.copy_classes().iter_enumerated() { + if local != head && borrowed_locals.contains(local) { + storage_to_remove.insert(head); + } + } + + let maybe_uninit = MaybeUninitializedLocals + .iterate_to_fixpoint(tcx, body, Some("mir_opt::copy_prop")) + .into_results_cursor(body); + + let mut storage_checker = StorageChecker { + maybe_uninit, + copy_classes: ssa.copy_classes(), + storage_to_remove, + }; + + for (bb, data) in traversal::reachable(body) { + storage_checker.visit_basic_block_data(bb, data); + } + + storage_checker.storage_to_remove + } else { + // Remove the storage statements of all the head locals. + storage_to_remove + }; + + debug!(?storage_to_remove); + + Replacer { tcx, copy_classes: ssa.copy_classes(), unified, storage_to_remove } + .visit_body_preserves_cfg(body); crate::simplify::remove_unused_definitions(body); } @@ -63,6 +107,7 @@ fn is_required(&self) -> bool { struct Replacer<'a, 'tcx> { tcx: TyCtxt<'tcx>, unified: DenseBitSet, + storage_to_remove: DenseBitSet, copy_classes: &'a IndexSlice, } @@ -73,7 +118,13 @@ fn tcx(&self) -> TyCtxt<'tcx> { #[tracing::instrument(level = "trace", skip(self))] fn visit_local(&mut self, local: &mut Local, ctxt: PlaceContext, _: Location) { - *local = self.copy_classes[*local]; + let new_local = self.copy_classes[*local]; + match ctxt { + // Do not modify the local in storage statements. + PlaceContext::NonUse(NonUseContext::StorageLive | NonUseContext::StorageDead) => {} + // We access the value. + _ => *local = new_local, + } } #[tracing::instrument(level = "trace", skip(self))] @@ -93,7 +144,7 @@ fn visit_operand(&mut self, operand: &mut Operand<'tcx>, loc: Location) { fn visit_statement(&mut self, stmt: &mut Statement<'tcx>, loc: Location) { // When removing storage statements, we need to remove both (#107511). if let StatementKind::StorageLive(l) | StatementKind::StorageDead(l) = stmt.kind - && self.unified.contains(l) + && self.storage_to_remove.contains(l) { stmt.make_nop(true); } @@ -109,3 +160,39 @@ fn visit_statement(&mut self, stmt: &mut Statement<'tcx>, loc: Location) { } } } + +// Marks heads of copy classes that are maybe uninitialized at the location of a local +// as needing storage statement removal. +struct StorageChecker<'a, 'tcx> { + maybe_uninit: ResultsCursor<'a, 'tcx, MaybeUninitializedLocals>, + copy_classes: &'a IndexSlice, + storage_to_remove: DenseBitSet, +} + +impl<'a, 'tcx> Visitor<'tcx> for StorageChecker<'a, 'tcx> { + fn visit_local(&mut self, local: Local, context: PlaceContext, loc: Location) { + if !context.is_use() { + return; + } + + let head = self.copy_classes[local]; + + // If the local is the head, or if we already marked it for deletion, we do not need to check it. + if head == local || self.storage_to_remove.contains(head) { + return; + } + + self.maybe_uninit.seek_before_primary_effect(loc); + + if self.maybe_uninit.get().contains(head) { + debug!( + ?loc, + ?context, + ?local, + ?head, + "local's head is maybe uninit at this location, marking head for storage statement removal" + ); + self.storage_to_remove.insert(head); + } + } +} diff --git a/compiler/rustc_mir_transform/src/cross_crate_inline.rs b/compiler/rustc_mir_transform/src/cross_crate_inline.rs index 53aa5f450dbb..644f2d22ef7f 100644 --- a/compiler/rustc_mir_transform/src/cross_crate_inline.rs +++ b/compiler/rustc_mir_transform/src/cross_crate_inline.rs @@ -146,8 +146,9 @@ fn visit_terminator(&mut self, terminator: &Terminator<'tcx>, _: Location) { TerminatorKind::Call { func, unwind, .. } => { // We track calls because they make our function not a leaf (and in theory, the // number of calls indicates how likely this function is to perturb other CGUs). - // But intrinsics don't have a body that gets assigned to a CGU, so they are - // ignored. + // But there are a handful of intrinsics such as raw_eq that should not block + // cross-crate-inlining. Adding a broad exception for all intrinsics benchmarks well + // and seems more sustainable than an ever-growing list of intrinsics to ignore. if let Some((fn_def_id, _)) = func.const_fn_def() && find_attr!(tcx, fn_def_id, RustcIntrinsic) { diff --git a/compiler/rustc_mir_transform/src/elaborate_box_derefs.rs b/compiler/rustc_mir_transform/src/elaborate_box_derefs.rs index 68c47ec4c192..a8eb22b5c4e5 100644 --- a/compiler/rustc_mir_transform/src/elaborate_box_derefs.rs +++ b/compiler/rustc_mir_transform/src/elaborate_box_derefs.rs @@ -6,7 +6,7 @@ use rustc_middle::mir::visit::MutVisitor; use rustc_middle::mir::*; use rustc_middle::span_bug; -use rustc_middle::ty::{self, Ty, TyCtxt}; +use rustc_middle::ty::{self, PatternKind, Ty, TyCtxt}; use crate::patch::MirPatch; @@ -137,8 +137,10 @@ fn run_pass(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) { build_ptr_tys(tcx, boxed_ty, unique_def, nonnull_def); new_projections.extend_from_slice(&build_projection(unique_ty, nonnull_ty)); - // While we can't project into `NonNull<_>` in a basic block - // due to MCP#807, this is debug info where it's fine. + // While we can't project into a pattern type in a basic block, + // this is debug info where it's fine. + let pat_ty = Ty::new_pat(tcx, ptr_ty, tcx.mk_pat(PatternKind::NotNull)); + new_projections.push(PlaceElem::Field(FieldIdx::ZERO, pat_ty)); new_projections.push(PlaceElem::Field(FieldIdx::ZERO, ptr_ty)); new_projections.push(PlaceElem::Deref); } else if let Some(new_projections) = new_projections.as_mut() { diff --git a/compiler/rustc_mir_transform/src/elaborate_drop.rs b/compiler/rustc_mir_transform/src/elaborate_drop.rs index 1fe745a5d519..3da9d6aac9be 100644 --- a/compiler/rustc_mir_transform/src/elaborate_drop.rs +++ b/compiler/rustc_mir_transform/src/elaborate_drop.rs @@ -548,7 +548,16 @@ fn move_paths_for_fields( let subpath = self.elaborator.field_subpath(variant_path, field_idx); let tcx = self.tcx(); - assert_eq!(self.elaborator.typing_env().typing_mode, ty::TypingMode::PostAnalysis); + match self.elaborator.typing_env().typing_mode() { + ty::TypingMode::PostAnalysis => {} + ty::TypingMode::Coherence + | ty::TypingMode::Analysis { .. } + | ty::TypingMode::Borrowck { .. } + | ty::TypingMode::PostBorrowckAnalysis { .. } => { + bug!() + } + } + let field_ty = field.ty(tcx, args); // We silently leave an unnormalized type here to support polymorphic drop // elaboration for users of rustc internal APIs diff --git a/compiler/rustc_mir_transform/src/gvn.rs b/compiler/rustc_mir_transform/src/gvn.rs index e9a20aa01655..4cf9017fbbd3 100644 --- a/compiler/rustc_mir_transform/src/gvn.rs +++ b/compiler/rustc_mir_transform/src/gvn.rs @@ -117,11 +117,12 @@ use rustc_middle::mir::*; use rustc_middle::ty::layout::HasTypingEnv; use rustc_middle::ty::{self, Ty, TyCtxt}; +use rustc_mir_dataflow::{Analysis, ResultsCursor}; use rustc_span::DUMMY_SP; use smallvec::SmallVec; use tracing::{debug, instrument, trace}; -use crate::ssa::SsaLocals; +use crate::ssa::{MaybeUninitializedLocals, SsaLocals}; pub(super) struct GVN; @@ -154,10 +155,34 @@ fn run_pass(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) { state.visit_basic_block_data(bb, data); } - // For each local that is reused (`y` above), we remove its storage statements do avoid any - // difficulty. Those locals are SSA, so should be easy to optimize by LLVM without storage - // statements. - StorageRemover { tcx, reused_locals: state.reused_locals }.visit_body_preserves_cfg(body); + // When emitting storage statements, we want to retain the reused locals' storage statements, + // as this enables better optimizations. For each local use location, we mark it for storage removal + // only if it might be uninitialized at that point. + let storage_to_remove = if tcx.sess.emit_lifetime_markers() { + let maybe_uninit = MaybeUninitializedLocals + .iterate_to_fixpoint(tcx, body, Some("mir_opt::gvn")) + .into_results_cursor(body); + + let mut storage_checker = StorageChecker { + reused_locals: &state.reused_locals, + storage_to_remove: DenseBitSet::new_empty(body.local_decls.len()), + maybe_uninit, + }; + + for (bb, data) in traversal::reachable(body) { + storage_checker.visit_basic_block_data(bb, data); + } + + storage_checker.storage_to_remove + } else { + // Remove the storage statements of all the reused locals. + state.reused_locals.clone() + }; + + debug!(?storage_to_remove); + + StorageRemover { tcx, reused_locals: state.reused_locals, storage_to_remove } + .visit_body_preserves_cfg(body); } fn is_required(&self) -> bool { @@ -2033,6 +2058,7 @@ fn visit_terminator(&mut self, terminator: &mut Terminator<'tcx>, location: Loca struct StorageRemover<'tcx> { tcx: TyCtxt<'tcx>, reused_locals: DenseBitSet, + storage_to_remove: DenseBitSet, } impl<'tcx> MutVisitor<'tcx> for StorageRemover<'tcx> { @@ -2053,7 +2079,7 @@ fn visit_statement(&mut self, stmt: &mut Statement<'tcx>, loc: Location) { match stmt.kind { // When removing storage statements, we need to remove both (#107511). StatementKind::StorageLive(l) | StatementKind::StorageDead(l) - if self.reused_locals.contains(l) => + if self.storage_to_remove.contains(l) => { stmt.make_nop(true) } @@ -2061,3 +2087,45 @@ fn visit_statement(&mut self, stmt: &mut Statement<'tcx>, loc: Location) { } } } + +struct StorageChecker<'a, 'tcx> { + reused_locals: &'a DenseBitSet, + storage_to_remove: DenseBitSet, + maybe_uninit: ResultsCursor<'a, 'tcx, MaybeUninitializedLocals>, +} + +impl<'a, 'tcx> Visitor<'tcx> for StorageChecker<'a, 'tcx> { + fn visit_local(&mut self, local: Local, context: PlaceContext, location: Location) { + match context { + // These mutating uses do not require the local to be initialized, + // so we cannot use our maybe-uninit check on them. + // However, GVN doesn't introduce or move mutations, + // so this local must already have valid storage at this location. + PlaceContext::MutatingUse(MutatingUseContext::AsmOutput) + | PlaceContext::MutatingUse(MutatingUseContext::Call) + | PlaceContext::MutatingUse(MutatingUseContext::Store) + | PlaceContext::MutatingUse(MutatingUseContext::Yield) + | PlaceContext::NonUse(_) => { + return; + } + // Must check validity for other mutating usages and all non-mutating uses. + PlaceContext::MutatingUse(_) | PlaceContext::NonMutatingUse(_) => {} + } + + // We only need to check reused locals which we haven't already removed storage for. + if !self.reused_locals.contains(local) || self.storage_to_remove.contains(local) { + return; + } + + self.maybe_uninit.seek_before_primary_effect(location); + + if self.maybe_uninit.get().contains(local) { + debug!( + ?location, + ?local, + "local is reused and is maybe uninit at this location, marking it for storage statement removal" + ); + self.storage_to_remove.insert(local); + } + } +} diff --git a/compiler/rustc_mir_transform/src/remove_unneeded_drops.rs b/compiler/rustc_mir_transform/src/remove_unneeded_drops.rs index 6c2dfc59da24..132dc85c68ff 100644 --- a/compiler/rustc_mir_transform/src/remove_unneeded_drops.rs +++ b/compiler/rustc_mir_transform/src/remove_unneeded_drops.rs @@ -4,13 +4,7 @@ //! useful because (unlike MIR building) it runs after type checking, so it can make use of //! `TypingMode::PostAnalysis` to provide more precise type information, especially about opaque //! types. -//! -//! When we're optimizing, we also remove calls to `drop_in_place` when `T` isn't `needs_drop`, -//! as those are essentially equivalent to `Drop` terminators. While the compiler doesn't insert -//! them automatically, preferring the built-in instead, they're common in generic code (such as -//! `Vec::truncate`) so removing them from things like inlined `Vec` is helpful. -use rustc_hir::LangItem; use rustc_middle::mir::*; use rustc_middle::ty::TyCtxt; use tracing::{debug, trace}; @@ -27,19 +21,8 @@ fn run_pass(&self, tcx: TyCtxt<'tcx>, body: &mut Body<'tcx>) { let mut should_simplify = false; for block in body.basic_blocks.as_mut() { let terminator = block.terminator_mut(); - let (ty, target) = match terminator.kind { - TerminatorKind::Drop { place, target, .. } => { - (place.ty(&body.local_decls, tcx).ty, target) - } - TerminatorKind::Call { ref func, target: Some(target), .. } - if tcx.sess.mir_opt_level() > 0 - && let Some((def_id, generics)) = func.const_fn_def() - && tcx.is_lang_item(def_id, LangItem::DropInPlace) => - { - (generics.type_at(0), target) - } - _ => continue, - }; + let TerminatorKind::Drop { place, target, .. } = terminator.kind else { continue }; + let ty = place.ty(&body.local_decls, tcx).ty; if ty.needs_drop(tcx, typing_env) { continue; diff --git a/compiler/rustc_mir_transform/src/shim.rs b/compiler/rustc_mir_transform/src/shim.rs index 4fd0629befec..cee637272e09 100644 --- a/compiler/rustc_mir_transform/src/shim.rs +++ b/compiler/rustc_mir_transform/src/shim.rs @@ -1020,7 +1020,7 @@ fn build_call_shim<'tcx>( let mut body = new_body(MirSource::from_instance(instance), blocks, local_decls, sig.inputs().len(), span); - if let ExternAbi::RustCall = sig.abi { + if let ExternAbi::RustCall = sig.abi() { body.spread_arg = Some(Local::new(sig.inputs().len())); } @@ -1171,9 +1171,7 @@ fn build_construct_coroutine_by_move_shim<'tcx>( args.as_coroutine_closure().tupled_upvars_ty(), args.as_coroutine_closure().coroutine_captures_by_ref_ty(), ), - sig.c_variadic, - sig.safety, - sig.abi, + sig.fn_sig_kind, ) }); let sig = tcx.liberate_late_bound_regions(coroutine_closure_def_id, poly_sig); diff --git a/compiler/rustc_mir_transform/src/shim/async_destructor_ctor.rs b/compiler/rustc_mir_transform/src/shim/async_destructor_ctor.rs index a0f1260cd986..ee08c09c130f 100644 --- a/compiler/rustc_mir_transform/src/shim/async_destructor_ctor.rs +++ b/compiler/rustc_mir_transform/src/shim/async_destructor_ctor.rs @@ -1,6 +1,6 @@ use rustc_hir::def_id::DefId; use rustc_hir::lang_items::LangItem; -use rustc_hir::{CoroutineDesugaring, CoroutineKind, CoroutineSource, Safety}; +use rustc_hir::{CoroutineDesugaring, CoroutineKind, CoroutineSource}; use rustc_index::{Idx, IndexVec}; use rustc_middle::mir::{ BasicBlock, BasicBlockData, Body, Local, LocalDecl, MirSource, Operand, Place, Rvalue, @@ -67,13 +67,7 @@ pub(super) fn build_async_drop_shim<'tcx>( let resume_adt = tcx.adt_def(tcx.require_lang_item(LangItem::ResumeTy, DUMMY_SP)); let resume_ty = Ty::new_adt(tcx, resume_adt, ty::List::empty()); - let fn_sig = ty::Binder::dummy(tcx.mk_fn_sig( - [ty, resume_ty], - tcx.types.unit, - false, - Safety::Safe, - ExternAbi::Rust, - )); + let fn_sig = ty::Binder::dummy(tcx.mk_fn_sig_safe_rust_abi([ty, resume_ty], tcx.types.unit)); let sig = tcx.instantiate_bound_regions_with_erased(fn_sig); assert!(!drop_ty.is_coroutine()); @@ -310,13 +304,7 @@ fn build_adrop_for_adrop_shim<'tcx>( let pin_adt_ref = tcx.adt_def(tcx.require_lang_item(LangItem::Pin, span)); let env_ty = Ty::new_adt(tcx, pin_adt_ref, tcx.mk_args(&[proxy_ref.into()])); // sig = `fn (Pin<&mut proxy_ty>, &mut Context) -> Poll<()>` - let sig = tcx.mk_fn_sig( - [env_ty, Ty::new_task_context(tcx)], - ret_ty, - false, - hir::Safety::Safe, - ExternAbi::Rust, - ); + let sig = tcx.mk_fn_sig_safe_rust_abi([env_ty, Ty::new_task_context(tcx)], ret_ty); // This function will be called with pinned proxy coroutine layout. // We need to extract `Arg0.0` to get proxy layout, and then get `.0` // further to receive impl coroutine (may be needed) diff --git a/compiler/rustc_mir_transform/src/ssa.rs b/compiler/rustc_mir_transform/src/ssa.rs index 4f9f2e5fabb9..4125cd514060 100644 --- a/compiler/rustc_mir_transform/src/ssa.rs +++ b/compiler/rustc_mir_transform/src/ssa.rs @@ -14,6 +14,7 @@ use rustc_middle::mir::visit::*; use rustc_middle::mir::*; use rustc_middle::ty::{self, TyCtxt}; +use rustc_mir_dataflow::Analysis; use tracing::{debug, instrument, trace}; pub(super) struct SsaLocals { @@ -391,3 +392,64 @@ pub(crate) fn has_single_storage(&self, local: Local) -> bool { matches!(self.storage_live[local], Set1::One(_)) } } + +/// A dataflow analysis that tracks locals that are maybe uninitialized. +/// +/// This is a simpler analysis than `MaybeUninitializedPlaces`, because it does not track +/// individual fields. +pub(crate) struct MaybeUninitializedLocals; + +impl<'tcx> Analysis<'tcx> for MaybeUninitializedLocals { + type Domain = DenseBitSet; + + const NAME: &'static str = "maybe_uninit_locals"; + + fn bottom_value(&self, body: &Body<'tcx>) -> Self::Domain { + // bottom = all locals are initialized. + DenseBitSet::new_empty(body.local_decls.len()) + } + + fn initialize_start_block(&self, body: &Body<'tcx>, state: &mut Self::Domain) { + // All locals start as uninitialized... + state.insert_all(); + // ...except for arguments, which are definitely initialized. + for arg in body.args_iter() { + state.remove(arg); + } + } + + fn apply_primary_statement_effect( + &self, + state: &mut Self::Domain, + statement: &Statement<'tcx>, + _location: Location, + ) { + match statement.kind { + // An assignment makes a local initialized. + StatementKind::Assign(box (place, _)) => { + if let Some(local) = place.as_local() { + state.remove(local); + } + } + // Storage{Live,Dead} makes a local uninitialized. + StatementKind::StorageLive(local) | StatementKind::StorageDead(local) => { + state.insert(local); + } + _ => {} + } + } + + fn apply_call_return_effect( + &self, + state: &mut Self::Domain, + _block: BasicBlock, + return_places: CallReturnPlaces<'_, 'tcx>, + ) { + // The return place of a call is initialized. + return_places.for_each(|place| { + if let Some(local) = place.as_local() { + state.remove(local); + } + }); + } +} diff --git a/compiler/rustc_monomorphize/src/mono_checks/abi_check.rs b/compiler/rustc_monomorphize/src/mono_checks/abi_check.rs index 0921e57844b0..41904d7905ef 100644 --- a/compiler/rustc_monomorphize/src/mono_checks/abi_check.rs +++ b/compiler/rustc_monomorphize/src/mono_checks/abi_check.rs @@ -25,8 +25,11 @@ fn passes_vectors_by_value(mode: &PassMode, repr: &BackendRepr) -> UsesVectorReg match mode { PassMode::Ignore | PassMode::Indirect { .. } => UsesVectorRegisters::No, PassMode::Cast { pad_i32: _, cast } - if cast.prefix.iter().any(|r| r.is_some_and(|x| x.kind == RegKind::Vector)) - || cast.rest.unit.kind == RegKind::Vector => + if cast + .prefix + .iter() + .any(|r| r.is_some_and(|x| matches!(x.kind, RegKind::Vector { .. }))) + || matches!(cast.rest.unit.kind, RegKind::Vector { .. }) => { UsesVectorRegisters::FixedVector } diff --git a/compiler/rustc_next_trait_solver/src/canonical/mod.rs b/compiler/rustc_next_trait_solver/src/canonical/mod.rs index 1f64f09fe787..a32a693a899c 100644 --- a/compiler/rustc_next_trait_solver/src/canonical/mod.rs +++ b/compiler/rustc_next_trait_solver/src/canonical/mod.rs @@ -17,7 +17,7 @@ use rustc_type_ir::relate::solver_relating::RelateExt; use rustc_type_ir::{ self as ty, Canonical, CanonicalVarKind, CanonicalVarValues, InferCtxtLike, Interner, - TypeFoldable, + TypeFoldable, TypingModeEqWrapper, }; use tracing::instrument; @@ -66,7 +66,10 @@ pub(super) fn canonicalize_goal( predefined_opaques_in_body: delegate.cx().mk_predefined_opaques_in_body(opaque_types), }, ); - let query_input = ty::CanonicalQueryInput { canonical, typing_mode: delegate.typing_mode() }; + let query_input = ty::CanonicalQueryInput { + canonical, + typing_mode: TypingModeEqWrapper(delegate.typing_mode()), + }; (orig_values, query_input) } @@ -247,17 +250,22 @@ fn unify_query_var_values( fn register_region_constraints( delegate: &D, - outlives: &[ty::OutlivesPredicate], + constraints: &[ty::RegionConstraint], span: I::Span, ) where D: SolverDelegate, I: Interner, { - for &ty::OutlivesPredicate(lhs, rhs) in outlives { - match lhs.kind() { - ty::GenericArgKind::Lifetime(lhs) => delegate.sub_regions(rhs, lhs, span), - ty::GenericArgKind::Type(lhs) => delegate.register_ty_outlives(lhs, rhs, span), - ty::GenericArgKind::Const(_) => panic!("const outlives: {lhs:?}: {rhs:?}"), + for &constraint in constraints { + match constraint { + ty::RegionConstraint::Outlives(ty::OutlivesPredicate(lhs, rhs)) => match lhs.kind() { + ty::GenericArgKind::Lifetime(lhs) => delegate.sub_regions(rhs, lhs, span), + ty::GenericArgKind::Type(lhs) => delegate.register_ty_outlives(lhs, rhs, span), + ty::GenericArgKind::Const(_) => panic!("const outlives: {lhs:?}: {rhs:?}"), + }, + ty::RegionConstraint::Eq(ty::RegionEqPredicate(lhs, rhs)) => { + delegate.equate_regions(lhs, rhs, span) + } } } } diff --git a/compiler/rustc_next_trait_solver/src/delegate.rs b/compiler/rustc_next_trait_solver/src/delegate.rs index 9d5aa8bc124b..7cf4e8a9238a 100644 --- a/compiler/rustc_next_trait_solver/src/delegate.rs +++ b/compiler/rustc_next_trait_solver/src/delegate.rs @@ -45,9 +45,7 @@ fn well_formed_goals( term: ::Term, ) -> Option::Predicate>>>; - fn make_deduplicated_outlives_constraints( - &self, - ) -> Vec::GenericArg>>; + fn make_deduplicated_region_constraints(&self) -> Vec>; fn instantiate_canonical( &self, diff --git a/compiler/rustc_next_trait_solver/src/solve/assembly/mod.rs b/compiler/rustc_next_trait_solver/src/solve/assembly/mod.rs index a4f331d3fe71..2e17885b4f44 100644 --- a/compiler/rustc_next_trait_solver/src/solve/assembly/mod.rs +++ b/compiler/rustc_next_trait_solver/src/solve/assembly/mod.rs @@ -442,7 +442,7 @@ pub(super) fn assemble_and_evaluate_candidates>( // normalizing the self type as well, since type variables are not uniquified. let goal = self.resolve_vars_if_possible(goal); - if let TypingMode::Coherence = self.typing_mode() + if self.typing_mode().is_coherence() && let Ok(candidate) = self.consider_coherence_unknowable_candidate(goal) { candidates.push(candidate); @@ -466,15 +466,20 @@ pub(super) fn assemble_and_evaluate_candidates>( // as we may want to weaken inference guidance in the future and don't want // to worry about causing major performance regressions when doing so. // See trait-system-refactor-initiative#226 for some ideas here. - if TypingMode::Coherence == self.typing_mode() - || !candidates.iter().any(|c| { + let assemble_impls = match self.typing_mode() { + TypingMode::Coherence => true, + TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } + | TypingMode::PostAnalysis => !candidates.iter().any(|c| { matches!( c.source, CandidateSource::ParamEnv(ParamEnvSource::NonGlobal) | CandidateSource::AliasBound(_) ) && has_no_inference_or_external_constraints(c.result) - }) - { + }), + }; + if assemble_impls { self.assemble_impl_candidates(goal, &mut candidates); self.assemble_object_bound_candidates(goal, &mut candidates); } diff --git a/compiler/rustc_next_trait_solver/src/solve/eval_ctxt/mod.rs b/compiler/rustc_next_trait_solver/src/solve/eval_ctxt/mod.rs index 6841fe1c5124..8933ac16b2b1 100644 --- a/compiler/rustc_next_trait_solver/src/solve/eval_ctxt/mod.rs +++ b/compiler/rustc_next_trait_solver/src/solve/eval_ctxt/mod.rs @@ -1294,9 +1294,9 @@ pub(in crate::solve) fn evaluate_added_goals_and_make_canonical_response( // Remove any trivial or duplicated region constraints once we've resolved regions let mut unique = HashSet::default(); - external_constraints.region_constraints.retain(|outlives| { - outlives.0.as_region().is_none_or(|re| re != outlives.1) && unique.insert(*outlives) - }); + external_constraints + .region_constraints + .retain(|outlives| !outlives.is_trivial() && unique.insert(*outlives)); let canonical = canonicalize_response( self.delegate, @@ -1350,7 +1350,7 @@ fn compute_external_query_constraints( // `tests/ui/higher-ranked/leak-check/leak-check-in-selection-5-ambig.rs` and // `tests/ui/higher-ranked/leak-check/leak-check-in-selection-6-ambig-unify.rs`. let region_constraints = if certainty == Certainty::Yes { - self.delegate.make_deduplicated_outlives_constraints() + self.delegate.make_deduplicated_region_constraints() } else { Default::default() }; diff --git a/compiler/rustc_next_trait_solver/src/solve/normalizes_to/opaque_types.rs b/compiler/rustc_next_trait_solver/src/solve/normalizes_to/opaque_types.rs index a5f857a1dd85..9b2bd7cb74ff 100644 --- a/compiler/rustc_next_trait_solver/src/solve/normalizes_to/opaque_types.rs +++ b/compiler/rustc_next_trait_solver/src/solve/normalizes_to/opaque_types.rs @@ -93,7 +93,9 @@ pub(super) fn normalize_opaque_type( }); self.eq(goal.param_env, expected, actual)?; } - _ => unreachable!(), + TypingMode::Coherence + | TypingMode::PostBorrowckAnalysis { .. } + | TypingMode::PostAnalysis => unreachable!(), } } diff --git a/compiler/rustc_next_trait_solver/src/solve/search_graph.rs b/compiler/rustc_next_trait_solver/src/solve/search_graph.rs index 73044b7943ae..0490b285aedf 100644 --- a/compiler/rustc_next_trait_solver/src/solve/search_graph.rs +++ b/compiler/rustc_next_trait_solver/src/solve/search_graph.rs @@ -62,7 +62,7 @@ fn initial_provisional_result( // See `tests/ui/traits/next-solver/cycles/unproductive-in-coherence.rs` for an // example where this would matter. We likely should change these cycles to `NoSolution` // even in coherence once this is a bit more settled. - PathKind::Inductive => match input.typing_mode { + PathKind::Inductive => match input.typing_mode.0 { TypingMode::Coherence => { response_no_constraints(cx, input, Certainty::overflow(false)) } diff --git a/compiler/rustc_next_trait_solver/src/solve/trait_goals.rs b/compiler/rustc_next_trait_solver/src/solve/trait_goals.rs index 44a570fc4fa7..33c165fbea6c 100644 --- a/compiler/rustc_next_trait_solver/src/solve/trait_goals.rs +++ b/compiler/rustc_next_trait_solver/src/solve/trait_goals.rs @@ -1421,7 +1421,7 @@ pub(super) fn merge_trait_candidates( mut candidates: Vec>, failed_candidate_info: FailedCandidateInfo, ) -> Result<(CanonicalResponse, Option), NoSolution> { - if let TypingMode::Coherence = self.typing_mode() { + if self.typing_mode().is_coherence() { return if let Some((response, _)) = self.try_merge_candidates(&candidates) { Ok((response, Some(TraitGoalProvenVia::Misc))) } else { diff --git a/compiler/rustc_parse/Cargo.toml b/compiler/rustc_parse/Cargo.toml index 28a67ae12126..53727efb4650 100644 --- a/compiler/rustc_parse/Cargo.toml +++ b/compiler/rustc_parse/Cargo.toml @@ -17,7 +17,7 @@ rustc_lexer = { path = "../rustc_lexer" } rustc_macros = { path = "../rustc_macros" } rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" unicode-normalization = "0.1.25" unicode-width = "0.2.2" diff --git a/compiler/rustc_parse/src/errors.rs b/compiler/rustc_parse/src/errors.rs index 6faaafcc0100..cc1e0ff85dae 100644 --- a/compiler/rustc_parse/src/errors.rs +++ b/compiler/rustc_parse/src/errors.rs @@ -1304,6 +1304,14 @@ pub(crate) struct ExpectedStatementAfterOuterAttr { pub span: Span, } +#[derive(Diagnostic)] +#[diag("attribute without where predicates")] +pub(crate) struct AttrWithoutWherePredicates { + #[primary_span] + #[label("attributes are only permitted when preceding predicates")] + pub span: Span, +} + #[derive(Diagnostic)] #[diag("found a documentation comment that doesn't document anything", code = E0585)] #[help("doc comments must come before what they document, if a comment was intended use `//`")] diff --git a/compiler/rustc_parse/src/lib.rs b/compiler/rustc_parse/src/lib.rs index 6b8d6baac945..4bfa89935239 100644 --- a/compiler/rustc_parse/src/lib.rs +++ b/compiler/rustc_parse/src/lib.rs @@ -257,6 +257,15 @@ pub fn fake_token_stream_for_item(psess: &ParseSess, item: &ast::Item) -> TokenS unwrap_or_emit_fatal(source_str_to_stream(psess, filename, source, Some(item.span))) } +pub fn fake_token_stream_for_foreign_item( + psess: &ParseSess, + item: &ast::ForeignItem, +) -> TokenStream { + let source = pprust::foreign_item_to_string(item); + let filename = FileName::macro_expansion_source_code(&source); + unwrap_or_emit_fatal(source_str_to_stream(psess, filename, source, Some(item.span))) +} + pub fn fake_token_stream_for_crate(psess: &ParseSess, krate: &ast::Crate) -> TokenStream { let source = pprust::crate_to_string_for_macros(krate); let filename = FileName::macro_expansion_source_code(&source); diff --git a/compiler/rustc_parse/src/parser/expr.rs b/compiler/rustc_parse/src/parser/expr.rs index c18e8c631fec..437102d549e7 100644 --- a/compiler/rustc_parse/src/parser/expr.rs +++ b/compiler/rustc_parse/src/parser/expr.rs @@ -3464,11 +3464,7 @@ pub(super) fn parse_arm(&mut self) -> PResult<'a, Arm> { } pub(crate) fn eat_metavar_guard(&mut self) -> Option> { - self.eat_metavar_seq_with_matcher( - |mv_kind| matches!(mv_kind, MetaVarKind::Guard), - |this| this.parse_match_arm_guard(), - ) - .flatten() + self.eat_metavar_seq(MetaVarKind::Guard, |this| this.parse_match_arm_guard()).flatten() } fn parse_match_arm_guard(&mut self) -> PResult<'a, Option>> { diff --git a/compiler/rustc_parse/src/parser/generics.rs b/compiler/rustc_parse/src/parser/generics.rs index 8c02092fd678..969c8548f68b 100644 --- a/compiler/rustc_parse/src/parser/generics.rs +++ b/compiler/rustc_parse/src/parser/generics.rs @@ -473,6 +473,17 @@ fn parse_where_clause_common( } } } else { + if let [.., last] = &attrs[..] { + if last.is_doc_comment() { + this.dcx().emit_err(errors::DocCommentDoesNotDocumentAnything { + span: last.span, + missing_comma: None, + }); + } else { + this.dcx() + .emit_err(errors::AttrWithoutWherePredicates { span: last.span }); + } + } None }; let predicate = kind.map(|kind| ast::WherePredicate { diff --git a/compiler/rustc_parse/src/parser/item.rs b/compiler/rustc_parse/src/parser/item.rs index ab3683f59820..ccfc9438f1cc 100644 --- a/compiler/rustc_parse/src/parser/item.rs +++ b/compiler/rustc_parse/src/parser/item.rs @@ -857,7 +857,7 @@ fn parse_impl_delegation( kind: AssocItemKind::DelegationMac(Box::new(DelegationMac { qself: None, prefix: of_trait.trait_ref.path.clone(), - suffixes: None, + suffixes: DelegationSuffixes::Glob(whole_reuse_span), body, })), })); @@ -879,10 +879,12 @@ fn parse_path_like_delegation(&mut self) -> PResult<'a, ItemKind> { Ok(if self.eat_path_sep() { let suffixes = if self.eat(exp!(Star)) { - None + DelegationSuffixes::Glob(self.prev_token.span) } else { let parse_suffix = |p: &mut Self| Ok((p.parse_path_segment_ident()?, rename(p)?)); - Some(self.parse_delim_comma_seq(exp!(OpenBrace), exp!(CloseBrace), parse_suffix)?.0) + DelegationSuffixes::List( + self.parse_delim_comma_seq(exp!(OpenBrace), exp!(CloseBrace), parse_suffix)?.0, + ) }; ItemKind::DelegationMac(Box::new(DelegationMac { @@ -1235,6 +1237,7 @@ fn parse_assoc_item( mutability: _, expr, define_opaque, + eii_impls: _, }) => { self.dcx().emit_err(errors::AssociatedStaticItemNotAllowed { span }); AssocItemKind::Const(Box::new(ConstItem { @@ -1503,6 +1506,7 @@ pub fn parse_foreign_item( }, safety: Safety::Default, define_opaque: None, + eii_impls: ThinVec::default(), })) } _ => return self.error_bad_item_kind(span, &kind, "`extern` blocks"), @@ -1517,7 +1521,10 @@ fn error_bad_item_kind(&self, span: Span, kind: &ItemKind, ctx: &'static str) let span = self.psess.source_map().guess_head_span(span); let descr = kind.descr(); let help = match kind { - ItemKind::DelegationMac(deleg) if deleg.suffixes.is_none() => false, + ItemKind::DelegationMac(box DelegationMac { + suffixes: DelegationSuffixes::Glob(_), + .. + }) => false, _ => true, }; self.dcx().emit_err(errors::BadItemKind { span, descr, ctx, help }); @@ -1636,7 +1643,15 @@ fn parse_static_item( self.expect_semi()?; - let item = StaticItem { ident, ty, safety, mutability, expr, define_opaque: None }; + let item = StaticItem { + ident, + ty, + safety, + mutability, + expr, + define_opaque: None, + eii_impls: ThinVec::default(), + }; Ok(ItemKind::Static(Box::new(item))) } diff --git a/compiler/rustc_parse/src/parser/nonterminal.rs b/compiler/rustc_parse/src/parser/nonterminal.rs index ddf1b10e5235..37b76fc26a48 100644 --- a/compiler/rustc_parse/src/parser/nonterminal.rs +++ b/compiler/rustc_parse/src/parser/nonterminal.rs @@ -105,7 +105,10 @@ fn may_be_ident(kind: MetaVarKind) -> bool { token::Lifetime(..) | token::NtLifetime(..) => true, _ => false, }, - NonterminalKind::Guard => token.is_keyword(kw::If), + NonterminalKind::Guard => match token.kind { + token::OpenInvisible(InvisibleOrigin::MetaVar(MetaVarKind::Guard)) => true, + _ => token.is_keyword(kw::If), + }, NonterminalKind::TT | NonterminalKind::Item | NonterminalKind::Stmt => { token.kind.close_delim().is_none() } diff --git a/compiler/rustc_passes/src/check_attr.rs b/compiler/rustc_passes/src/check_attr.rs index 3e3810b7f125..1475f61532bd 100644 --- a/compiler/rustc_passes/src/check_attr.rs +++ b/compiler/rustc_passes/src/check_attr.rs @@ -9,7 +9,7 @@ use std::slice; use rustc_abi::ExternAbi; -use rustc_ast::ast; +use rustc_ast::{AttrStyle, MetaItemKind, ast}; use rustc_attr_parsing::{AttributeParser, Late}; use rustc_data_structures::thin_vec::ThinVec; use rustc_data_structures::unord::UnordMap; @@ -17,15 +17,15 @@ use rustc_feature::BUILTIN_ATTRIBUTE_MAP; use rustc_hir::attrs::diagnostic::Directive; use rustc_hir::attrs::{ - AttributeKind, CrateType, DocAttribute, DocInline, EiiDecl, EiiImpl, EiiImplResolution, - InlineAttr, LintAttribute, ReprAttr, SanitizerSet, + AttributeKind, DocAttribute, DocInline, EiiDecl, EiiImpl, EiiImplResolution, InlineAttr, + ReprAttr, SanitizerSet, }; use rustc_hir::def::DefKind; use rustc_hir::def_id::LocalModDefId; use rustc_hir::intravisit::{self, Visitor}; use rustc_hir::{ self as hir, Attribute, CRATE_HIR_ID, Constness, FnSig, ForeignItem, GenericParamKind, HirId, - Item, ItemKind, MethodKind, Node, ParamName, Safety, Target, TraitItem, find_attr, + Item, ItemKind, MethodKind, Node, ParamName, Target, TraitItem, find_attr, }; use rustc_macros::Diagnostic; use rustc_middle::hir::nested_filter; @@ -35,6 +35,7 @@ use rustc_middle::ty::error::{ExpectedFound, TypeError}; use rustc_middle::ty::{self, TyCtxt, TypingMode}; use rustc_middle::{bug, span_bug}; +use rustc_session::config::CrateType; use rustc_session::lint; use rustc_session::lint::builtin::{ CONFLICTING_REPR_HINTS, INVALID_DOC_ATTRIBUTES, MALFORMED_DIAGNOSTIC_FORMAT_LITERALS, @@ -71,6 +72,13 @@ struct DiagnosticOnConstOnlyForNonConstTraitImpls { #[diag("`#[diagnostic::on_move]` can only be applied to enums, structs or unions")] struct DiagnosticOnMoveOnlyForAdt; +#[derive(Diagnostic)] +#[diag("`#[diagnostic::on_unknown]` can only be applied to `use` statements")] +struct DiagnosticOnUnknownOnlyForImports { + #[label("not an import")] + item_span: Span, +} + fn target_from_impl_item<'tcx>(tcx: TyCtxt<'tcx>, impl_item: &hir::ImplItem<'_>) -> Target { match impl_item.kind { hir::ImplItemKind::Const(..) => Target::AssocConst, @@ -137,6 +145,7 @@ fn check_attributes( ) { let attrs = self.tcx.hir_attrs(hir_id); for attr in attrs { + let mut style = None; match attr { Attribute::Parsed(AttributeKind::ProcMacro(_)) => { self.check_proc_macro(hir_id, target, ProcMacroKind::FunctionLike) @@ -214,11 +223,11 @@ fn check_attributes( }, Attribute::Parsed(AttributeKind::DoNotRecommend{attr_span}) => {self.check_do_not_recommend(*attr_span, hir_id, target, item)}, Attribute::Parsed(AttributeKind::OnUnimplemented{span, directive}) => {self.check_diagnostic_on_unimplemented(*span, hir_id, target,directive.as_deref())}, + Attribute::Parsed(AttributeKind::OnUnknown { span, .. }) => { self.check_diagnostic_on_unknown(*span, hir_id, target) }, Attribute::Parsed(AttributeKind::OnConst{span, ..}) => {self.check_diagnostic_on_const(*span, hir_id, target, item)} Attribute::Parsed(AttributeKind::OnMove { span, directive }) => { self.check_diagnostic_on_move(*span, hir_id, target, directive.as_deref()) }, - Attribute::Parsed(AttributeKind::LintAttributes(sub_attrs)) => self.check_lint_attr(hir_id, sub_attrs), Attribute::Parsed( // tidy-alphabetical-start AttributeKind::RustcAllowIncoherentImpl(..) @@ -272,7 +281,6 @@ fn check_attributes( | AttributeKind::Path(..) | AttributeKind::PatternComplexityLimit { .. } | AttributeKind::PinV2(..) - | AttributeKind::Pointee(..) | AttributeKind::PreludeImport | AttributeKind::ProfilerRuntime | AttributeKind::RecursionLimit { .. } @@ -298,7 +306,6 @@ fn check_attributes( | AttributeKind::RustcConstStableIndirect | AttributeKind::RustcConversionSuggestion | AttributeKind::RustcDeallocator - | AttributeKind::RustcDefPath(..) | AttributeKind::RustcDelayedBugFromInsideQuery | AttributeKind::RustcDenyExplicitImpl(..) | AttributeKind::RustcDeprecatedSafe2024 {..} @@ -307,9 +314,13 @@ fn check_attributes( | AttributeKind::RustcDocPrimitive(..) | AttributeKind::RustcDummy | AttributeKind::RustcDumpDefParents + | AttributeKind::RustcDumpDefPath(..) + | AttributeKind::RustcDumpHiddenTypeOfOpaques | AttributeKind::RustcDumpInferredOutlives | AttributeKind::RustcDumpItemBounds + | AttributeKind::RustcDumpLayout(..) | AttributeKind::RustcDumpPredicates + | AttributeKind::RustcDumpSymbolName(..) | AttributeKind::RustcDumpUserArgs | AttributeKind::RustcDumpVariances | AttributeKind::RustcDumpVariancesOfOpaques @@ -319,13 +330,11 @@ fn check_attributes( | AttributeKind::RustcEiiForeignItem | AttributeKind::RustcEvaluateWhereClauses | AttributeKind::RustcHasIncoherentInherentImpls - | AttributeKind::RustcHiddenTypeOfOpaques | AttributeKind::RustcIfThisChanged(..) | AttributeKind::RustcInheritOverflowChecks | AttributeKind::RustcInsignificantDtor | AttributeKind::RustcIntrinsic | AttributeKind::RustcIntrinsicConstStableIndirect - | AttributeKind::RustcLayout(..) | AttributeKind::RustcLayoutScalarValidRangeEnd(..) | AttributeKind::RustcLayoutScalarValidRangeStart(..) | AttributeKind::RustcLintOptDenyFieldAccess { .. } @@ -335,11 +344,13 @@ fn check_attributes( | AttributeKind::RustcMacroTransparency(_) | AttributeKind::RustcMain | AttributeKind::RustcMir(_) + | AttributeKind::RustcMustMatchExhaustively(..) | AttributeKind::RustcNeverReturnsNullPtr | AttributeKind::RustcNeverTypeOptions {..} | AttributeKind::RustcNoImplicitAutorefs | AttributeKind::RustcNoImplicitBounds | AttributeKind::RustcNoMirInline + | AttributeKind::RustcNoWritable | AttributeKind::RustcNonConstTraitMethod | AttributeKind::RustcNonnullOptimizationGuaranteed | AttributeKind::RustcNounwind @@ -361,7 +372,6 @@ fn check_attributes( | AttributeKind::RustcSpecializationTrait(..) | AttributeKind::RustcStdInternalSymbol (..) | AttributeKind::RustcStrictCoherence(..) - | AttributeKind::RustcSymbolName(..) | AttributeKind::RustcTestMarker(..) | AttributeKind::RustcThenThisWouldNeed(..) | AttributeKind::RustcTrivialFieldReads @@ -372,12 +382,23 @@ fn check_attributes( | AttributeKind::ThreadLocal | AttributeKind::TypeLengthLimit { .. } | AttributeKind::UnstableFeatureBound(..) + | AttributeKind::UnstableRemoved(..) | AttributeKind::Used { .. } | AttributeKind::WindowsSubsystem(..) // tidy-alphabetical-end ) => { /* do nothing */ } - Attribute::Unparsed(_) => { + Attribute::Unparsed(attr_item) => { + style = Some(attr_item.style); match attr.path().as_slice() { + [ + // ok + sym::allow + | sym::expect + | sym::warn + | sym::deny + | sym::forbid, + .. + ] => {} [name, rest@..] => { match BUILTIN_ATTRIBUTE_MAP.get(name) { Some(_) => { @@ -401,7 +422,7 @@ fn check_attributes( } } - self.check_unused_attribute(hir_id, attr) + self.check_unused_attribute(hir_id, attr, style) } self.check_repr(attrs, span, target, item, hir_id); @@ -469,9 +490,9 @@ fn check_rustc_must_implement_one_of( fn check_eii_impl(&self, impls: &[EiiImpl], target: Target) { for EiiImpl { span, inner_span, resolution, impl_marked_unsafe, is_default: _ } in impls { match target { - Target::Fn => {} + Target::Fn | Target::Static => {} _ => { - self.dcx().emit_err(errors::EiiImplNotFunction { span: *span }); + self.dcx().emit_err(errors::EiiImplTarget { span: *span }); } } @@ -534,7 +555,7 @@ fn check_diagnostic_on_unimplemented( if let Some(directive) = directive { if let Node::Item(Item { - kind: ItemKind::Trait(_, _, _, trait_name, generics, _, _), + kind: ItemKind::Trait(_, _, _, _, trait_name, generics, _, _), .. }) = self.tcx.hir_node(hir_id) { @@ -654,6 +675,19 @@ fn check_diagnostic_on_move( } } + /// Checks if `#[diagnostic::on_unknown]` is applied to a trait impl + fn check_diagnostic_on_unknown(&self, attr_span: Span, hir_id: HirId, target: Target) { + if !matches!(target, Target::Use) { + let item_span = self.tcx.hir_span(hir_id); + self.tcx.emit_node_span_lint( + MISPLACED_DIAGNOSTIC_ATTRIBUTES, + hir_id, + attr_span, + DiagnosticOnUnknownOnlyForImports { item_span }, + ); + } + } + /// Checks if an `#[inline]` is applied to a function or a closure. fn check_inline(&self, hir_id: HirId, attr_span: Span, kind: &InlineAttr, target: Target) { match target { @@ -974,7 +1008,7 @@ fn check_doc_search_unbox(&self, span: Span, hir_id: HirId) { match item.kind { ItemKind::Enum(_, generics, _) | ItemKind::Struct(_, generics, _) if generics.params.len() != 0 => {} - ItemKind::Trait(_, _, _, _, generics, _, items) + ItemKind::Trait(_, _, _, _, _, generics, _, items) if generics.params.len() != 0 || items.iter().any(|item| { matches!(self.tcx.def_kind(item.owner_id), DefKind::AssocTy) @@ -1510,75 +1544,87 @@ fn check_macro_export(&self, hir_id: HirId, attr_span: Span, target: Target) { } } - fn check_lint_attr(&self, hir_id: HirId, sub_attrs: &[LintAttribute]) { - for LintAttribute { attr_span, lint_instances, attr_style, .. } in sub_attrs { - if !lint_instances.iter().any(|id| { - id.lint_name() == sym::linker_messages || id.lint_name() == sym::linker_info - }) { - continue; - }; - let note = if hir_id != CRATE_HIR_ID { - match attr_style { - ast::AttrStyle::Outer => { - let attr_span = attr_span; - let bang_position = self - .tcx - .sess - .source_map() - .span_until_char(*attr_span, '[') - .shrink_to_hi(); - - self.tcx.emit_node_span_lint( - UNUSED_ATTRIBUTES, - hir_id, - *attr_span, - errors::OuterCrateLevelAttr { - suggestion: errors::OuterCrateLevelAttrSuggestion { bang_position }, - }, - ) - } - ast::AttrStyle::Inner => self.tcx.emit_node_span_lint( - UNUSED_ATTRIBUTES, - hir_id, - *attr_span, - errors::InnerCrateLevelAttr, - ), - }; - continue; - } else { - let never_needs_link = self - .tcx - .crate_types() - .iter() - .all(|kind| matches!(kind, CrateType::Rlib | CrateType::StaticLib)); - if never_needs_link { - errors::UnusedNote::LinkerMessagesBinaryCrateOnly - } else { - continue; - } - }; - - self.tcx.emit_node_span_lint( - UNUSED_ATTRIBUTES, - hir_id, - *attr_span, - errors::Unused { attr_span: *attr_span, note }, - ); - } - } - - fn check_unused_attribute(&self, hir_id: HirId, attr: &Attribute) { + fn check_unused_attribute(&self, hir_id: HirId, attr: &Attribute, style: Option) { // Warn on useless empty attributes. // FIXME(jdonszelmann): this lint should be moved to attribute parsing, see `AcceptContext::warn_empty_attribute` - let note = if attr.has_any_name(&[sym::feature]) - && attr.meta_item_list().is_some_and(|list| list.is_empty()) - { - errors::UnusedNote::EmptyList { name: attr.name().unwrap() } - } else if attr.has_name(sym::default_method_body_is_const) { - errors::UnusedNote::DefaultMethodBodyConst - } else { - return; - }; + let note = + if attr.has_any_name(&[sym::allow, sym::expect, sym::warn, sym::deny, sym::forbid]) + && attr.meta_item_list().is_some_and(|list| list.is_empty()) + { + errors::UnusedNote::EmptyList { name: attr.name().unwrap() } + } else if attr.has_any_name(&[ + sym::allow, + sym::warn, + sym::deny, + sym::forbid, + sym::expect, + ]) && let Some(meta) = attr.meta_item_list() + && let [meta] = meta.as_slice() + && let Some(item) = meta.meta_item() + && let MetaItemKind::NameValue(_) = &item.kind + && item.path == sym::reason + { + errors::UnusedNote::NoLints { name: attr.name().unwrap() } + } else if attr.has_any_name(&[ + sym::allow, + sym::warn, + sym::deny, + sym::forbid, + sym::expect, + ]) && let Some(meta) = attr.meta_item_list() + && meta.iter().any(|meta| { + meta.meta_item().map_or(false, |item| { + item.path == sym::linker_messages || item.path == sym::linker_info + }) + }) + { + if hir_id != CRATE_HIR_ID { + match style { + Some(ast::AttrStyle::Outer) => { + let attr_span = attr.span(); + let bang_position = self + .tcx + .sess + .source_map() + .span_until_char(attr_span, '[') + .shrink_to_hi(); + + self.tcx.emit_node_span_lint( + UNUSED_ATTRIBUTES, + hir_id, + attr_span, + errors::OuterCrateLevelAttr { + suggestion: errors::OuterCrateLevelAttrSuggestion { + bang_position, + }, + }, + ) + } + Some(ast::AttrStyle::Inner) | None => self.tcx.emit_node_span_lint( + UNUSED_ATTRIBUTES, + hir_id, + attr.span(), + errors::InnerCrateLevelAttr, + ), + }; + return; + } else { + let never_needs_link = self + .tcx + .crate_types() + .iter() + .all(|kind| matches!(kind, CrateType::Rlib | CrateType::StaticLib)); + if never_needs_link { + errors::UnusedNote::LinkerMessagesBinaryCrateOnly + } else { + return; + } + } + } else if attr.has_name(sym::default_method_body_is_const) { + errors::UnusedNote::DefaultMethodBodyConst + } else { + return; + }; self.tcx.emit_node_span_lint( UNUSED_ATTRIBUTES, @@ -1626,7 +1672,7 @@ fn check_proc_macro(&self, hir_id: HirId, target: Target, kind: ProcMacroKind) { return; } - let expected_sig = tcx.mk_fn_sig( + let expected_sig = tcx.mk_fn_sig_safe_rust_abi( std::iter::repeat_n( token_stream, match kind { @@ -1635,9 +1681,6 @@ fn check_proc_macro(&self, hir_id: HirId, target: Target, kind: ProcMacroKind) { }, ), token_stream, - false, - Safety::Safe, - ExternAbi::Rust, ); if let Err(terr) = ocx.eq(&cause, param_env, expected_sig, sig) { diff --git a/compiler/rustc_passes/src/check_export.rs b/compiler/rustc_passes/src/check_export.rs index 7f80de9da41f..9c5f285dea02 100644 --- a/compiler/rustc_passes/src/check_export.rs +++ b/compiler/rustc_passes/src/check_export.rs @@ -204,7 +204,7 @@ fn check_fn(&mut self) { } let sig = self.tcx.fn_sig(def_id).instantiate_identity().skip_binder(); - if !matches!(sig.abi, ExternAbi::C { .. }) { + if !matches!(sig.abi(), ExternAbi::C { .. }) { self.tcx.dcx().emit_err(UnexportableItem::FnAbi(span)); return; } diff --git a/compiler/rustc_passes/src/debugger_visualizer.rs b/compiler/rustc_passes/src/debugger_visualizer.rs index 7211f3cf85b3..1f27384d4e7c 100644 --- a/compiler/rustc_passes/src/debugger_visualizer.rs +++ b/compiler/rustc_passes/src/debugger_visualizer.rs @@ -1,7 +1,6 @@ //! Detecting usage of the `#[debugger_visualizer]` attribute. -use rustc_ast::ast::NodeId; -use rustc_ast::{HasNodeId, ItemKind, ast}; +use rustc_ast::{ItemKind, ast}; use rustc_attr_parsing::AttributeParser; use rustc_expand::base::resolve_path; use rustc_hir::Attribute; @@ -10,26 +9,14 @@ use rustc_middle::query::{LocalCrate, Providers}; use rustc_middle::ty::TyCtxt; use rustc_session::Session; -use rustc_span::{DUMMY_SP, Span, sym}; +use rustc_span::sym; use crate::errors::DebugVisualizerUnreadable; impl DebuggerVisualizerCollector<'_> { - fn check_for_debugger_visualizer( - &mut self, - attrs: &[ast::Attribute], - span: Span, - node_id: NodeId, - ) { + fn check_for_debugger_visualizer(&mut self, attrs: &[ast::Attribute]) { if let Some(Attribute::Parsed(AttributeKind::DebuggerVisualizer(visualizers))) = - AttributeParser::parse_limited( - &self.sess, - attrs, - sym::debugger_visualizer, - span, - node_id, - None, - ) + AttributeParser::parse_limited(&self.sess, attrs, &[sym::debugger_visualizer]) { for DebugVisualizer { span, visualizer_type, path } in visualizers { let file = match resolve_path(&self.sess, path.as_str(), span) { @@ -69,12 +56,12 @@ struct DebuggerVisualizerCollector<'a> { impl<'ast> rustc_ast::visit::Visitor<'ast> for DebuggerVisualizerCollector<'_> { fn visit_item(&mut self, item: &'ast rustc_ast::Item) -> Self::Result { if let ItemKind::Mod(..) = item.kind { - self.check_for_debugger_visualizer(&item.attrs, item.span, item.node_id()); + self.check_for_debugger_visualizer(&item.attrs); } rustc_ast::visit::walk_item(self, item); } fn visit_crate(&mut self, krate: &'ast ast::Crate) -> Self::Result { - self.check_for_debugger_visualizer(&krate.attrs, DUMMY_SP, krate.id); + self.check_for_debugger_visualizer(&krate.attrs); rustc_ast::visit::walk_crate(self, krate); } } diff --git a/compiler/rustc_passes/src/errors.rs b/compiler/rustc_passes/src/errors.rs index 46b96ff1da35..cb56a28b8628 100644 --- a/compiler/rustc_passes/src/errors.rs +++ b/compiler/rustc_passes/src/errors.rs @@ -294,6 +294,8 @@ pub(crate) enum MacroExport { pub(crate) enum UnusedNote { #[note("attribute `{$name}` with an empty list has no effect")] EmptyList { name: Symbol }, + #[note("attribute `{$name}` without any lints has no effect")] + NoLints { name: Symbol }, #[note("`default_method_body_is_const` has been replaced with `const` on traits")] DefaultMethodBodyConst, #[note( @@ -434,47 +436,6 @@ pub(crate) struct DuplicateDiagnosticItemInCrate { pub name: Symbol, } -#[derive(Diagnostic)] -#[diag("abi: {$abi}")] -pub(crate) struct LayoutAbi { - #[primary_span] - pub span: Span, - pub abi: String, -} - -#[derive(Diagnostic)] -#[diag("align: {$align}")] -pub(crate) struct LayoutAlign { - #[primary_span] - pub span: Span, - pub align: String, -} - -#[derive(Diagnostic)] -#[diag("size: {$size}")] -pub(crate) struct LayoutSize { - #[primary_span] - pub span: Span, - pub size: String, -} - -#[derive(Diagnostic)] -#[diag("homogeneous_aggregate: {$homogeneous_aggregate}")] -pub(crate) struct LayoutHomogeneousAggregate { - #[primary_span] - pub span: Span, - pub homogeneous_aggregate: String, -} - -#[derive(Diagnostic)] -#[diag("layout_of({$normalized_ty}) = {$ty_layout}")] -pub(crate) struct LayoutOf<'tcx> { - #[primary_span] - pub span: Span, - pub normalized_ty: Ty<'tcx>, - pub ty_layout: String, -} - #[derive(Diagnostic)] #[diag("fn_abi_of({$fn_name}) = {$fn_abi}")] pub(crate) struct AbiOf { @@ -910,6 +871,20 @@ pub(crate) struct ImpliedFeatureNotExist { pub implied_by: Symbol, } +#[derive(Diagnostic)] +#[diag("feature `{$feature}` has been removed", code = E0557)] +#[note("removed in {$since}; see <{$link}> for more information")] +#[note("{$reason}")] +pub(crate) struct FeatureRemoved { + #[primary_span] + #[label("feature has been removed")] + pub span: Span, + pub feature: Symbol, + pub reason: Symbol, + pub since: String, + pub link: Symbol, +} + #[derive(Diagnostic)] #[diag( "attributes `#[rustc_const_unstable]`, `#[rustc_const_stable]` and `#[rustc_const_stable_indirect]` require the function or method to be `const`" @@ -1190,8 +1165,8 @@ pub(crate) struct ReprAlignShouldBeAlignStatic { } #[derive(Diagnostic)] -#[diag("`eii_macro_for` is only valid on functions")] -pub(crate) struct EiiImplNotFunction { +#[diag("`eii_macro_for` is only valid on functions and statics")] +pub(crate) struct EiiImplTarget { #[primary_span] pub span: Span, } diff --git a/compiler/rustc_passes/src/layout_test.rs b/compiler/rustc_passes/src/layout_test.rs index 1a9054a51ca3..3317a8d03f6d 100644 --- a/compiler/rustc_passes/src/layout_test.rs +++ b/compiler/rustc_passes/src/layout_test.rs @@ -1,5 +1,5 @@ use rustc_abi::{HasDataLayout, TargetDataLayout}; -use rustc_hir::attrs::RustcLayoutType; +use rustc_hir::attrs::RustcDumpLayoutKind; use rustc_hir::def::DefKind; use rustc_hir::def_id::LocalDefId; use rustc_hir::find_attr; @@ -11,21 +11,18 @@ use rustc_trait_selection::infer::TyCtxtInferExt; use rustc_trait_selection::traits; -use crate::errors::{LayoutAbi, LayoutAlign, LayoutHomogeneousAggregate, LayoutOf, LayoutSize}; - pub fn test_layout(tcx: TyCtxt<'_>) { if !tcx.features().rustc_attrs() { // if the `rustc_attrs` feature is not enabled, don't bother testing layout return; } for id in tcx.hir_crate_items(()).definitions() { - if let Some(attrs) = find_attr!(tcx, id, RustcLayout(attrs) => attrs) { + if let Some(kinds) = find_attr!(tcx, id, RustcDumpLayout(kinds) => kinds) { // Attribute parsing handles error reporting - if matches!( - tcx.def_kind(id), - DefKind::TyAlias | DefKind::Enum | DefKind::Struct | DefKind::Union - ) { - dump_layout_of(tcx, id, attrs); + if let DefKind::TyAlias | DefKind::Enum | DefKind::Struct | DefKind::Union = + tcx.def_kind(id) + { + dump_layout_of(tcx, id, kinds); } } } @@ -62,7 +59,7 @@ pub fn ensure_wf<'tcx>( } } -fn dump_layout_of(tcx: TyCtxt<'_>, item_def_id: LocalDefId, attrs: &[RustcLayoutType]) { +fn dump_layout_of(tcx: TyCtxt<'_>, item_def_id: LocalDefId, kinds: &[RustcDumpLayoutKind]) { let typing_env = ty::TypingEnv::post_analysis(tcx, item_def_id); let ty = tcx.type_of(item_def_id).instantiate_identity(); let span = tcx.def_span(item_def_id.to_def_id()); @@ -71,46 +68,25 @@ fn dump_layout_of(tcx: TyCtxt<'_>, item_def_id: LocalDefId, attrs: &[RustcLayout } match tcx.layout_of(typing_env.as_query_input(ty)) { Ok(ty_layout) => { - for attr in attrs { - match attr { - // FIXME: this never was about ABI and now this dump arg is confusing - RustcLayoutType::Abi => { - tcx.dcx().emit_err(LayoutAbi { - span, - abi: format!("{:?}", ty_layout.backend_repr), - }); + for kind in kinds { + let message = match kind { + RustcDumpLayoutKind::Align => format!("align: {:?}", *ty_layout.align), + RustcDumpLayoutKind::BackendRepr => { + format!("backend_repr: {:?}", ty_layout.backend_repr) } - - RustcLayoutType::Align => { - tcx.dcx().emit_err(LayoutAlign { - span, - align: format!("{:?}", ty_layout.align), - }); - } - - RustcLayoutType::Size => { - tcx.dcx() - .emit_err(LayoutSize { span, size: format!("{:?}", ty_layout.size) }); - } - - RustcLayoutType::HomogenousAggregate => { - tcx.dcx().emit_err(LayoutHomogeneousAggregate { - span, - homogeneous_aggregate: format!( - "{:?}", - ty_layout - .homogeneous_aggregate(&UnwrapLayoutCx { tcx, typing_env }) - ), - }); - } - - RustcLayoutType::Debug => { + RustcDumpLayoutKind::Debug => { let normalized_ty = tcx.normalize_erasing_regions(typing_env, ty); // FIXME: using the `Debug` impl here isn't ideal. - let ty_layout = format!("{:#?}", *ty_layout); - tcx.dcx().emit_err(LayoutOf { span, normalized_ty, ty_layout }); + format!("layout_of({normalized_ty}) = {:#?}", *ty_layout) } - } + RustcDumpLayoutKind::HomogenousAggregate => { + let data = + ty_layout.homogeneous_aggregate(&UnwrapLayoutCx { tcx, typing_env }); + format!("homogeneous_aggregate: {data:?}") + } + RustcDumpLayoutKind::Size => format!("size: {:?}", ty_layout.size), + }; + tcx.dcx().span_err(span, message); } } @@ -127,7 +103,10 @@ struct UnwrapLayoutCx<'tcx> { impl<'tcx> LayoutOfHelpers<'tcx> for UnwrapLayoutCx<'tcx> { fn handle_layout_err(&self, err: LayoutError<'tcx>, span: Span, ty: Ty<'tcx>) -> ! { - span_bug!(span, "`#[rustc_layout(..)]` test resulted in `layout_of({ty}) = Err({err})`",); + span_bug!( + span, + "`#[rustc_dump_layout(..)]` test resulted in `layout_of({ty}) = Err({err})`", + ); } } diff --git a/compiler/rustc_passes/src/stability.rs b/compiler/rustc_passes/src/stability.rs index 220cb57ddd39..e41df43e34bd 100644 --- a/compiler/rustc_passes/src/stability.rs +++ b/compiler/rustc_passes/src/stability.rs @@ -1097,7 +1097,7 @@ fn check_features<'tcx>( let lang_features = UNSTABLE_LANG_FEATURES.iter().map(|feature| feature.name).collect::>(); let lib_features = crates - .into_iter() + .iter() .flat_map(|&cnum| { tcx.lib_features(cnum).stability.keys().copied().into_sorted_stable_ord() }) @@ -1105,11 +1105,33 @@ fn check_features<'tcx>( let valid_feature_names = [lang_features, lib_features].concat(); + // Collect all of the marked as "removed" features + let unstable_removed_features = crates + .iter() + .flat_map(|&cnum| { + find_attr!(tcx, cnum.as_def_id(), UnstableRemoved(rem_features) => rem_features) + .into_iter() + .flatten() + }) + .collect::>(); + for (feature, span) in remaining_lib_features { - let suggestion = feature - .find_similar(&valid_feature_names) - .map(|(actual_name, _)| errors::MisspelledFeature { span, actual_name }); - tcx.dcx().emit_err(errors::UnknownFeature { span, feature, suggestion }); + if let Some(removed) = + unstable_removed_features.iter().find(|removed| removed.feature == feature) + { + tcx.dcx().emit_err(errors::FeatureRemoved { + span, + feature, + reason: removed.reason, + link: removed.link, + since: removed.since.to_string(), + }); + } else { + let suggestion = feature + .find_similar(&valid_feature_names) + .map(|(actual_name, _)| errors::MisspelledFeature { span, actual_name }); + tcx.dcx().emit_err(errors::UnknownFeature { span, feature, suggestion }); + } } } } diff --git a/compiler/rustc_pattern_analysis/src/errors.rs b/compiler/rustc_pattern_analysis/src/errors.rs index 109acf0ec410..bf9bcbb7f71a 100644 --- a/compiler/rustc_pattern_analysis/src/errors.rs +++ b/compiler/rustc_pattern_analysis/src/errors.rs @@ -48,7 +48,7 @@ pub fn new<'p, 'tcx>( #[derive(Diagnostic)] #[diag("multiple patterns overlap on their endpoints")] #[note("you likely meant to write mutually exclusive ranges")] -pub struct OverlappingRangeEndpoints { +pub(crate) struct OverlappingRangeEndpoints { #[label("... with this range")] pub range: Span, #[subdiagnostic] @@ -57,7 +57,7 @@ pub struct OverlappingRangeEndpoints { #[derive(Subdiagnostic)] #[label("this range overlaps on `{$range}`...")] -pub struct Overlap { +pub(crate) struct Overlap { #[primary_span] pub span: Span, pub range: String, // a printed pattern @@ -65,7 +65,7 @@ pub struct Overlap { #[derive(Diagnostic)] #[diag("exclusive range missing `{$max}`")] -pub struct ExclusiveRangeMissingMax { +pub(crate) struct ExclusiveRangeMissingMax { #[label("this range doesn't match `{$max}` because `..` is an exclusive range")] #[suggestion( "use an inclusive range instead", @@ -81,7 +81,7 @@ pub struct ExclusiveRangeMissingMax { #[derive(Diagnostic)] #[diag("multiple ranges are one apart")] -pub struct ExclusiveRangeMissingGap { +pub(crate) struct ExclusiveRangeMissingGap { #[label("this range doesn't match `{$gap}` because `..` is an exclusive range")] #[suggestion( "use an inclusive range instead", @@ -102,7 +102,7 @@ pub struct ExclusiveRangeMissingGap { #[label( "this could appear to continue range `{$first_range}`, but `{$gap}` isn't matched by either of them" )] -pub struct GappedRange { +pub(crate) struct GappedRange { #[primary_span] pub span: Span, pub gap: String, // a printed pattern diff --git a/compiler/rustc_pattern_analysis/src/rustc.rs b/compiler/rustc_pattern_analysis/src/rustc.rs index 2ec434de61c1..b0f589955124 100644 --- a/compiler/rustc_pattern_analysis/src/rustc.rs +++ b/compiler/rustc_pattern_analysis/src/rustc.rs @@ -126,12 +126,12 @@ impl<'p, 'tcx: 'p> RustcPatCtxt<'p, 'tcx> { #[inline] pub fn reveal_opaque_ty(&self, ty: Ty<'tcx>) -> RevealedTy<'tcx> { fn reveal_inner<'tcx>(cx: &RustcPatCtxt<'_, 'tcx>, ty: Ty<'tcx>) -> RevealedTy<'tcx> { - let ty::Alias(alias_ty @ ty::AliasTy { kind: ty::Opaque { .. }, .. }) = *ty.kind() + let ty::Alias(ty::AliasTy { kind: ty::Opaque { def_id }, args, .. }) = *ty.kind() else { bug!() }; - if let Some(local_def_id) = alias_ty.kind.def_id().as_local() { - let key = ty::OpaqueTypeKey { def_id: local_def_id, args: alias_ty.args }; + if let Some(local_def_id) = def_id.as_local() { + let key = ty::OpaqueTypeKey { def_id: local_def_id, args }; if let Some(ty) = cx.reveal_opaque_key(key) { return RevealedTy(ty); } diff --git a/compiler/rustc_public/src/unstable/convert/internal.rs b/compiler/rustc_public/src/unstable/convert/internal.rs index b8533dcaa8d6..4f3e9f94c599 100644 --- a/compiler/rustc_public/src/unstable/convert/internal.rs +++ b/compiler/rustc_public/src/unstable/convert/internal.rs @@ -308,11 +308,13 @@ fn internal<'tcx>( tables: &mut Tables<'_, BridgeTys>, tcx: impl InternalCx<'tcx>, ) -> Self::T<'tcx> { + let fn_sig_kind = rustc_ty::FnSigKind::default() + .set_abi(self.abi.internal(tables, tcx)) + .set_safe(self.safety == Safety::Safe) + .set_c_variadic(self.c_variadic); tcx.lift(rustc_ty::FnSig { inputs_and_output: tcx.mk_type_list(&self.inputs_and_output.internal(tables, tcx)), - c_variadic: self.c_variadic, - safety: self.safety.internal(tables, tcx), - abi: self.abi.internal(tables, tcx), + fn_sig_kind, }) .unwrap() } diff --git a/compiler/rustc_public/src/unstable/convert/stable/ty.rs b/compiler/rustc_public/src/unstable/convert/stable/ty.rs index 57115467366c..9a9576d47efd 100644 --- a/compiler/rustc_public/src/unstable/convert/stable/ty.rs +++ b/compiler/rustc_public/src/unstable/convert/stable/ty.rs @@ -252,6 +252,23 @@ fn stable<'cx>( } } +// This internal type isn't publicly exposed, because it is an implementation detail. +// But it's a public field of FnSig (which has a public mirror type), so allow conversions. +impl<'tcx> Stable<'tcx> for ty::FnSigKind { + type T = (bool /*c_variadic*/, crate::mir::Safety, crate::ty::Abi); + fn stable<'cx>( + &self, + tables: &mut Tables<'cx, BridgeTys>, + cx: &CompilerCtxt<'cx, BridgeTys>, + ) -> Self::T { + ( + self.c_variadic(), + if self.is_safe() { crate::mir::Safety::Safe } else { crate::mir::Safety::Unsafe }, + self.abi().stable(tables, cx), + ) + } +} + impl<'tcx> Stable<'tcx> for ty::FnSig<'tcx> { type T = crate::ty::FnSig; fn stable<'cx>( @@ -260,6 +277,7 @@ fn stable<'cx>( cx: &CompilerCtxt<'cx, BridgeTys>, ) -> Self::T { use crate::ty::FnSig; + let (c_variadic, safety, abi) = self.fn_sig_kind.stable(tables, cx); FnSig { inputs_and_output: self @@ -267,9 +285,9 @@ fn stable<'cx>( .iter() .map(|ty| ty.stable(tables, cx)) .collect(), - c_variadic: self.c_variadic, - safety: self.safety.stable(tables, cx), - abi: self.abi.stable(tables, cx), + c_variadic, + safety, + abi, } } } diff --git a/compiler/rustc_query_impl/Cargo.toml b/compiler/rustc_query_impl/Cargo.toml index 02d3b0110cb8..ec1d8dab7451 100644 --- a/compiler/rustc_query_impl/Cargo.toml +++ b/compiler/rustc_query_impl/Cargo.toml @@ -6,7 +6,6 @@ edition = "2024" [dependencies] # tidy-alphabetical-start measureme = "12.0.1" -rustc_abi = { path = "../rustc_abi" } rustc_data_structures = { path = "../rustc_data_structures" } rustc_errors = { path = "../rustc_errors" } rustc_hir = { path = "../rustc_hir" } diff --git a/compiler/rustc_query_impl/src/error.rs b/compiler/rustc_query_impl/src/error.rs index 44d53f87aae2..54c2d96078c6 100644 --- a/compiler/rustc_query_impl/src/error.rs +++ b/compiler/rustc_query_impl/src/error.rs @@ -79,3 +79,28 @@ pub(crate) struct Cycle { )] pub note_span: (), } + +#[derive(Subdiagnostic)] +#[note("...when {$stack_bottom}")] +pub(crate) struct NestedCycleBottom { + pub stack_bottom: String, +} + +#[derive(Diagnostic)] +#[diag("internal compiler error: query cycle when printing cycle detected")] +pub(crate) struct NestedCycle { + #[primary_span] + pub span: Span, + #[subdiagnostic] + pub stack_bottom: NestedCycleBottom, + #[subdiagnostic] + pub cycle_stack: Vec, + #[subdiagnostic] + pub stack_count: StackCount, + #[subdiagnostic] + pub cycle_usage: Option, + #[note( + "see https://rustc-dev-guide.rust-lang.org/overview.html#queries and https://rustc-dev-guide.rust-lang.org/query.html for more information" + )] + pub note_span: (), +} diff --git a/compiler/rustc_query_impl/src/execution.rs b/compiler/rustc_query_impl/src/execution.rs index 44995f3f9826..ed9ad8c7a0a6 100644 --- a/compiler/rustc_query_impl/src/execution.rs +++ b/compiler/rustc_query_impl/src/execution.rs @@ -4,7 +4,7 @@ use rustc_data_structures::hash_table::{Entry, HashTable}; use rustc_data_structures::stack::ensure_sufficient_stack; use rustc_data_structures::sync::{DynSend, DynSync}; -use rustc_data_structures::{outline, sharded, sync}; +use rustc_data_structures::{defer, outline, sharded, sync}; use rustc_errors::FatalError; use rustc_middle::dep_graph::{DepGraphData, DepNodeKey, SerializedDepNodeIndex}; use rustc_middle::query::{ @@ -17,6 +17,7 @@ use tracing::warn; use crate::dep_graph::{DepNode, DepNodeIndex}; +use crate::handle_cycle_error; use crate::job::{QueryJobInfo, QueryJobMap, create_cycle_error, find_cycle_in_stack}; use crate::plumbing::{current_query_job, loadable_from_disk, next_job_id, start_query}; use crate::query_impl::for_each_query_vtable; @@ -114,8 +115,29 @@ fn handle_cycle<'tcx, C: QueryCache>( key: C::Key, cycle: Cycle<'tcx>, ) -> C::Value { - let error = create_cycle_error(tcx, &cycle); - (query.handle_cycle_error_fn)(tcx, key, cycle, error) + let nested; + { + let mut nesting = tcx.query_system.cycle_handler_nesting.lock(); + nested = match *nesting { + 0 => false, + 1 => true, + _ => { + // Don't print further nested errors to avoid cases of infinite recursion + tcx.dcx().delayed_bug("doubly nested cycle error").raise_fatal() + } + }; + *nesting += 1; + } + let _guard = defer(|| *tcx.query_system.cycle_handler_nesting.lock() -= 1); + + let error = create_cycle_error(tcx, &cycle, nested); + + if nested { + // Avoid custom handlers and only use the robust `create_cycle_error` for nested cycle errors + handle_cycle_error::default(error) + } else { + (query.handle_cycle_error_fn)(tcx, key, cycle, error) + } } /// Guard object representing the responsibility to execute a query job and @@ -447,8 +469,7 @@ fn execute_job_incr<'tcx, C: QueryCache>( dep_graph_data.with_task( dep_node, tcx, - (query, key), - |tcx, (query, key)| (query.invoke_provider_fn)(tcx, key), + || (query.invoke_provider_fn)(tcx, key), query.hash_value_fn, ) }); @@ -477,16 +498,20 @@ fn load_from_disk_or_invoke_provider_green<'tcx, C: QueryCache>( debug_assert!(dep_graph_data.is_index_green(prev_index)); // First try to load the result from the on-disk cache. Some things are never cached on disk. - let value; - let verify; - match (query.try_load_from_disk_fn)(tcx, key, prev_index, dep_node_index) { - Some(loaded_value) => { + let try_value = if (query.will_cache_on_disk_for_key_fn)(key) { + let prof_timer = tcx.prof.incr_cache_loading(); + let value = (query.try_load_from_disk_fn)(tcx, prev_index); + prof_timer.finish_with_query_invocation_id(dep_node_index.into()); + value + } else { + None + }; + let (value, verify) = match try_value { + Some(value) => { if std::intrinsics::unlikely(tcx.sess.opts.unstable_opts.query_dep_graph) { dep_graph_data.mark_debug_loaded_from_disk(*dep_node) } - value = loaded_value; - let prev_fingerprint = dep_graph_data.prev_value_fingerprint_of(prev_index); // If `-Zincremental-verify-ich` is specified, re-hash results from // the cache and make sure that they have the expected fingerprint. @@ -495,17 +520,19 @@ fn load_from_disk_or_invoke_provider_green<'tcx, C: QueryCache>( // from disk. Re-hashing results is fairly expensive, so we can't // currently afford to verify every hash. This subset should still // give us some coverage of potential bugs. - verify = prev_fingerprint.split().1.as_u64().is_multiple_of(32) + let verify = prev_fingerprint.split().1.as_u64().is_multiple_of(32) || tcx.sess.opts.unstable_opts.incremental_verify_ich; + + (value, verify) } None => { // We could not load a result from the on-disk cache, so recompute. The dep-graph for // this computation is already in-place, so we can just call the query provider. let prof_timer = tcx.prof.query_provider(); - value = tcx.dep_graph.with_ignore(|| (query.invoke_provider_fn)(tcx, key)); + let value = tcx.dep_graph.with_ignore(|| (query.invoke_provider_fn)(tcx, key)); prof_timer.finish_with_query_invocation_id(dep_node_index.into()); - verify = true; + (value, true) } }; diff --git a/compiler/rustc_query_impl/src/handle_cycle_error.rs b/compiler/rustc_query_impl/src/handle_cycle_error.rs index 07565254969c..79e7788cafe8 100644 --- a/compiler/rustc_query_impl/src/handle_cycle_error.rs +++ b/compiler/rustc_query_impl/src/handle_cycle_error.rs @@ -43,13 +43,9 @@ pub(crate) fn fn_sig<'tcx>( unreachable!() }; - ty::EarlyBinder::bind(ty::Binder::dummy(tcx.mk_fn_sig( - std::iter::repeat_n(err, arity), - err, - false, - rustc_hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, - ))) + ty::EarlyBinder::bind(ty::Binder::dummy( + tcx.mk_fn_sig_safe_rust_abi(std::iter::repeat_n(err, arity), err), + )) } pub(crate) fn check_representability<'tcx>( @@ -210,7 +206,7 @@ pub(crate) fn layout_of<'tcx>( ControlFlow::Continue(()) } }, - || create_cycle_error(tcx, &cycle), + || create_cycle_error(tcx, &cycle, false), ); diag.emit().raise_fatal() diff --git a/compiler/rustc_query_impl/src/job.rs b/compiler/rustc_query_impl/src/job.rs index f8098da59371..bf0493b29fd1 100644 --- a/compiler/rustc_query_impl/src/job.rs +++ b/compiler/rustc_query_impl/src/job.rs @@ -303,29 +303,17 @@ struct EntryPoint { } } -/// Looks for a query cycle using the last query in `jobs`. -/// If a cycle is found, all queries in the cycle is removed from `jobs` and -/// the function return true. -/// If a cycle was not found, the starting query is removed from `jobs` and -/// the function returns false. -fn remove_cycle<'tcx>( +/// Looks for a query cycle starting at `query`. +/// Returns a waiter to resume if a cycle is found. +fn find_and_process_cycle<'tcx>( job_map: &QueryJobMap<'tcx>, - jobs: &mut Vec, - wakelist: &mut Vec>>, -) -> bool { + query: QueryJobId, +) -> Option>> { let mut visited = FxHashSet::default(); let mut stack = Vec::new(); - // Look for a cycle starting with the last query in `jobs` if let ControlFlow::Break(resumable) = - find_cycle(job_map, jobs.pop().unwrap(), DUMMY_SP, &mut stack, &mut visited) + find_cycle(job_map, query, DUMMY_SP, &mut stack, &mut visited) { - // Remove the queries in our cycle from the list of jobs to look at - for r in &stack { - if let Some(pos) = jobs.iter().position(|j| j == &r.1) { - jobs.remove(pos); - } - } - // Create the cycle error let error = process_cycle(job_map, stack); @@ -340,62 +328,31 @@ fn remove_cycle<'tcx>( *waiter.cycle.lock() = Some(error); // Put the waiter on the list of things to resume - wakelist.push(waiter); - - true + Some(waiter) } else { - false + None } } /// Detects query cycles by using depth first search over all active query jobs. /// If a query cycle is found it will break the cycle by finding an edge which /// uses a query latch and then resuming that waiter. -/// There may be multiple cycles involved in a deadlock, so this searches -/// all active queries for cycles before finally resuming all the waiters at once. -pub fn break_query_cycles<'tcx>( - job_map: QueryJobMap<'tcx>, - registry: &rustc_thread_pool::Registry, -) { - let mut wakelist = Vec::new(); - // It is OK per the comments: - // - https://github.com/rust-lang/rust/pull/131200#issuecomment-2798854932 - // - https://github.com/rust-lang/rust/pull/131200#issuecomment-2798866392 - #[allow(rustc::potential_query_instability)] - let mut jobs: Vec = job_map.map.keys().copied().collect(); +/// +/// There may be multiple cycles involved in a deadlock, but this only breaks one at a time so +/// there will be multiple rounds through the deadlock handler if multiple cycles are present. +#[allow(rustc::potential_query_instability)] +pub fn break_query_cycle<'tcx>(job_map: QueryJobMap<'tcx>, registry: &rustc_thread_pool::Registry) { + // Look for a cycle starting at each query job + let waiter = job_map + .map + .keys() + .find_map(|query| find_and_process_cycle(&job_map, *query)) + .expect("unable to find a query cycle"); - let mut found_cycle = false; + // Mark the thread we're about to wake up as unblocked. + rustc_thread_pool::mark_unblocked(registry); - while jobs.len() > 0 { - if remove_cycle(&job_map, &mut jobs, &mut wakelist) { - found_cycle = true; - } - } - - // Check that a cycle was found. It is possible for a deadlock to occur without - // a query cycle if a query which can be waited on uses Rayon to do multithreading - // internally. Such a query (X) may be executing on 2 threads (A and B) and A may - // wait using Rayon on B. Rayon may then switch to executing another query (Y) - // which in turn will wait on X causing a deadlock. We have a false dependency from - // X to Y due to Rayon waiting and a true dependency from Y to X. The algorithm here - // only considers the true dependency and won't detect a cycle. - if !found_cycle { - panic!( - "deadlock detected as we're unable to find a query cycle to break\n\ - current query map:\n{job_map:#?}", - ); - } - - // Mark all the thread we're about to wake up as unblocked. This needs to be done before - // we wake the threads up as otherwise Rayon could detect a deadlock if a thread we - // resumed fell asleep and this thread had yet to mark the remaining threads as unblocked. - for _ in 0..wakelist.len() { - rustc_thread_pool::mark_unblocked(registry); - } - - for waiter in wakelist.into_iter() { - waiter.condvar.notify_one(); - } + assert!(waiter.condvar.notify_one(), "unable to wake the waiter"); } pub fn print_query_stack<'tcx>( @@ -456,15 +413,16 @@ pub fn print_query_stack<'tcx>( pub(crate) fn create_cycle_error<'tcx>( tcx: TyCtxt<'tcx>, Cycle { usage, frames }: &Cycle<'tcx>, + nested: bool, ) -> Diag<'tcx> { assert!(!frames.is_empty()); - let span = frames[0].tagged_key.default_span(tcx, frames[1 % frames.len()].span); + let span = frames[0].tagged_key.catch_default_span(tcx, frames[1 % frames.len()].span); let mut cycle_stack = Vec::new(); use crate::error::StackCount; - let stack_bottom = frames[0].tagged_key.description(tcx); + let stack_bottom = frames[0].tagged_key.catch_description(tcx); let stack_count = if frames.len() == 1 { StackCount::Single { stack_bottom: stack_bottom.clone() } } else { @@ -473,14 +431,14 @@ pub(crate) fn create_cycle_error<'tcx>( for i in 1..frames.len() { let frame = &frames[i]; - let span = frame.tagged_key.default_span(tcx, frames[(i + 1) % frames.len()].span); + let span = frame.tagged_key.catch_default_span(tcx, frames[(i + 1) % frames.len()].span); cycle_stack - .push(crate::error::CycleStack { span, desc: frame.tagged_key.description(tcx) }); + .push(crate::error::CycleStack { span, desc: frame.tagged_key.catch_description(tcx) }); } let cycle_usage = usage.as_ref().map(|usage| crate::error::CycleUsage { - span: usage.tagged_key.default_span(tcx, usage.span), - usage: usage.tagged_key.description(tcx), + span: usage.tagged_key.catch_default_span(tcx, usage.span), + usage: usage.tagged_key.catch_description(tcx), }); let is_all_def_kind = |def_kind| { @@ -497,23 +455,36 @@ pub(crate) fn create_cycle_error<'tcx>( }) }; - let alias = if is_all_def_kind(DefKind::TyAlias) { - Some(crate::error::Alias::Ty) - } else if is_all_def_kind(DefKind::TraitAlias) { - Some(crate::error::Alias::Trait) + let alias = if !nested { + if is_all_def_kind(DefKind::TyAlias) { + Some(crate::error::Alias::Ty) + } else if is_all_def_kind(DefKind::TraitAlias) { + Some(crate::error::Alias::Trait) + } else { + None + } } else { None }; - let cycle_diag = crate::error::Cycle { - span, - cycle_stack, - stack_bottom, - alias, - cycle_usage, - stack_count, - note_span: (), - }; - - tcx.sess.dcx().create_err(cycle_diag) + if nested { + tcx.sess.dcx().create_err(crate::error::NestedCycle { + span, + cycle_stack, + stack_bottom: crate::error::NestedCycleBottom { stack_bottom }, + cycle_usage, + stack_count, + note_span: (), + }) + } else { + tcx.sess.dcx().create_err(crate::error::Cycle { + span, + cycle_stack, + stack_bottom, + alias, + cycle_usage, + stack_count, + note_span: (), + }) + } } diff --git a/compiler/rustc_query_impl/src/lib.rs b/compiler/rustc_query_impl/src/lib.rs index 27bfe1451f64..d5133aa04dcc 100644 --- a/compiler/rustc_query_impl/src/lib.rs +++ b/compiler/rustc_query_impl/src/lib.rs @@ -8,7 +8,7 @@ #![feature(try_blocks)] // tidy-alphabetical-end -use rustc_data_structures::sync::AtomicU64; +use rustc_data_structures::sync::{AtomicU64, Lock}; use rustc_middle::dep_graph; use rustc_middle::queries::{ExternProviders, Providers}; use rustc_middle::query::on_disk_cache::OnDiskCache; @@ -17,7 +17,7 @@ pub use crate::dep_kind_vtables::make_dep_kind_vtables; pub use crate::execution::{CollectActiveJobsKind, collect_active_query_jobs}; -pub use crate::job::{QueryJobMap, break_query_cycles, print_query_stack}; +pub use crate::job::{QueryJobMap, break_query_cycle, print_query_stack}; mod dep_kind_vtables; mod error; @@ -56,6 +56,7 @@ pub fn query_system<'tcx>( local_providers, extern_providers, jobs: AtomicU64::new(1), + cycle_handler_nesting: Lock::new(0), } } diff --git a/compiler/rustc_query_impl/src/plumbing.rs b/compiler/rustc_query_impl/src/plumbing.rs index dfc66a2225f2..11f960598c38 100644 --- a/compiler/rustc_query_impl/src/plumbing.rs +++ b/compiler/rustc_query_impl/src/plumbing.rs @@ -5,7 +5,7 @@ use rustc_middle::bug; #[expect(unused_imports, reason = "used by doc comments")] use rustc_middle::dep_graph::DepKindVTable; -use rustc_middle::dep_graph::{DepNode, DepNodeIndex, DepNodeKey, SerializedDepNodeIndex}; +use rustc_middle::dep_graph::{DepNode, DepNodeKey, SerializedDepNodeIndex}; use rustc_middle::query::erase::{Erasable, Erased}; use rustc_middle::query::on_disk_cache::{CacheDecoder, CacheEncoder}; use rustc_middle::query::{QueryCache, QueryJobId, QueryMode, QueryVTable, erase}; @@ -184,23 +184,14 @@ pub(crate) fn loadable_from_disk<'tcx>(tcx: TyCtxt<'tcx>, id: SerializedDepNodeI pub(crate) fn try_load_from_disk<'tcx, V>( tcx: TyCtxt<'tcx>, prev_index: SerializedDepNodeIndex, - index: DepNodeIndex, ) -> Option where V: for<'a> Decodable>, { let on_disk_cache = tcx.query_system.on_disk_cache.as_ref()?; - let prof_timer = tcx.prof.incr_cache_loading(); - // The call to `with_query_deserialization` enforces that no new `DepNodes` // are created during deserialization. See the docs of that method for more // details. - let value = tcx - .dep_graph - .with_query_deserialization(|| on_disk_cache.try_load_query_value(tcx, prev_index)); - - prof_timer.finish_with_query_invocation_id(index.into()); - - value + tcx.dep_graph.with_query_deserialization(|| on_disk_cache.try_load_query_value(tcx, prev_index)) } diff --git a/compiler/rustc_query_impl/src/query_impl.rs b/compiler/rustc_query_impl/src/query_impl.rs index 101bf2c4e80f..4425acc6b86b 100644 --- a/compiler/rustc_query_impl/src/query_impl.rs +++ b/compiler/rustc_query_impl/src/query_impl.rs @@ -160,22 +160,17 @@ pub(crate) fn make_query_vtable<'tcx>(incremental: bool) $crate::query_impl::$name::will_cache_on_disk_for_key, #[cfg($cache_on_disk)] - try_load_from_disk_fn: |tcx, key, prev_index, index| { + try_load_from_disk_fn: |tcx, prev_index| { use rustc_middle::queries::$name::{ProvidedValue, provided_to_erased}; - // Check the cache-on-disk condition for this key. - if !$crate::query_impl::$name::will_cache_on_disk_for_key(key) { - return None; - } - let loaded_value: ProvidedValue<'tcx> = - $crate::plumbing::try_load_from_disk(tcx, prev_index, index)?; + $crate::plumbing::try_load_from_disk(tcx, prev_index)?; // Arena-alloc the value if appropriate, and erase it. Some(provided_to_erased(tcx, loaded_value)) }, #[cfg(not($cache_on_disk))] - try_load_from_disk_fn: |_tcx, _key, _prev_index, _index| None, + try_load_from_disk_fn: |_tcx, _prev_index| None, #[cfg($handle_cycle_error)] handle_cycle_error_fn: |tcx, key, cycle, err| { diff --git a/compiler/rustc_resolve/Cargo.toml b/compiler/rustc_resolve/Cargo.toml index feb0a93d0788..2fc251e2b525 100644 --- a/compiler/rustc_resolve/Cargo.toml +++ b/compiler/rustc_resolve/Cargo.toml @@ -7,7 +7,9 @@ edition = "2024" # tidy-alphabetical-start indexmap = "2.4.0" itertools = "0.12" -pulldown-cmark = { version = "0.11", features = ["html"], default-features = false } +pulldown-cmark = { version = "0.11", features = [ + "html", +], default-features = false } rustc_arena = { path = "../rustc_arena" } rustc_ast = { path = "../rustc_ast" } rustc_ast_pretty = { path = "../rustc_ast_pretty" } @@ -24,6 +26,6 @@ rustc_middle = { path = "../rustc_middle" } rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_resolve/src/build_reduced_graph.rs b/compiler/rustc_resolve/src/build_reduced_graph.rs index d00c306329b7..237f69eb534e 100644 --- a/compiler/rustc_resolve/src/build_reduced_graph.rs +++ b/compiler/rustc_resolve/src/build_reduced_graph.rs @@ -32,17 +32,16 @@ use crate::Namespace::{MacroNS, TypeNS, ValueNS}; use crate::def_collector::collect_definitions; -use crate::imports::{ImportData, ImportKind}; +use crate::diagnostics::StructCtor; +use crate::imports::{ImportData, ImportKind, OnUnknownData}; use crate::macros::{MacroRulesDecl, MacroRulesScope, MacroRulesScopeRef}; use crate::ref_mut::CmCell; use crate::{ - BindingKey, Decl, DeclData, DeclKind, ExternPreludeEntry, Finalize, IdentKey, MacroData, - Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, - Segment, Used, VisResolutionError, errors, + BindingKey, Decl, DeclData, DeclKind, ExternModule, ExternPreludeEntry, Finalize, IdentKey, + LocalModule, MacroData, Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, Res, + ResolutionError, Resolver, Segment, Used, VisResolutionError, errors, }; -type Res = def::Res; - impl<'ra, 'tcx> Resolver<'ra, 'tcx> { /// Attempt to put the declaration with the given name and namespace into the module, /// and report an error in case of a collision. @@ -63,7 +62,7 @@ pub(crate) fn plant_decl_into_local_module( /// Create a name definition from the given components, and put it into the local module. fn define_local( &mut self, - parent: Module<'ra>, + parent: LocalModule<'ra>, orig_ident: Ident, ns: Namespace, res: Res, @@ -71,7 +70,8 @@ fn define_local( span: Span, expn_id: LocalExpnId, ) { - let decl = self.arenas.new_def_decl(res, vis.to_def_id(), span, expn_id, Some(parent)); + let decl = + self.arenas.new_def_decl(res, vis.to_def_id(), span, expn_id, Some(parent.to_module())); let ident = IdentKey::new(orig_ident); self.plant_decl_into_local_module(ident, orig_ident.span, ns, decl); } @@ -79,7 +79,7 @@ fn define_local( /// Create a name definition from the given components, and put it into the extern module. fn define_extern( &self, - parent: Module<'ra>, + parent: ExternModule<'ra>, ident: IdentKey, orig_ident_span: Span, ns: Namespace, @@ -98,7 +98,7 @@ fn define_extern( vis: CmCell::new(vis), span, expansion, - parent_module: Some(parent), + parent_module: Some(parent.to_module()), }); // Even if underscore names cannot be looked up, we still need to add them to modules, // because they can be fetched by glob imports from those modules, and bring traits @@ -106,7 +106,7 @@ fn define_extern( let key = BindingKey::new_disambiguated(ident, ns, || (child_index + 1).try_into().unwrap()); // 0 indicates no underscore if self - .resolution_or_default(parent, key, orig_ident_span) + .resolution_or_default(parent.to_module(), key, orig_ident_span) .borrow_mut_unchecked() .non_glob_decl .replace(decl) @@ -150,30 +150,30 @@ pub(crate) fn expect_module(&self, def_id: DefId) -> Module<'ra> { /// returns `None`. pub(crate) fn get_module(&self, def_id: DefId) -> Option> { match def_id.as_local() { - Some(local_def_id) => self.local_module_map.get(&local_def_id).copied(), + Some(local_def_id) => self.local_module_map.get(&local_def_id).map(|m| m.to_module()), None => { if let module @ Some(..) = self.extern_module_map.borrow().get(&def_id) { - return module.copied(); + return module.map(|m| m.to_module()); } // Query `def_kind` is not used because query system overhead is too expensive here. let def_kind = self.cstore().def_kind_untracked(self.tcx, def_id); if def_kind.is_module_like() { - let parent = self - .tcx - .opt_parent(def_id) - .map(|parent_id| self.get_nearest_non_block_module(parent_id)); + let parent = self.tcx.opt_parent(def_id).map(|parent_id| { + self.get_nearest_non_block_module(parent_id).expect_extern() + }); // Query `expn_that_defined` is not used because // hashing spans in its result is expensive. let expn_id = self.cstore().expn_that_defined_untracked(self.tcx, def_id); - return Some(self.new_extern_module( + let module = self.new_extern_module( parent, ModuleKind::Def(def_kind, def_id, Some(self.tcx.item_name(def_id))), expn_id, self.def_span(def_id), // FIXME: Account for `#[no_implicit_prelude]` attributes. parent.is_some_and(|module| module.no_implicit_prelude), - )); + ); + return Some(module.to_module()); } None @@ -187,13 +187,14 @@ pub(crate) fn expn_def_scope(&self, expn_id: ExpnId) -> Module<'ra> { None => expn_id .as_local() .and_then(|expn_id| self.ast_transform_scopes.get(&expn_id).copied()) - .unwrap_or(self.graph_root), + .unwrap_or(self.graph_root) + .to_module(), } } pub(crate) fn macro_def_scope(&self, def_id: DefId) -> Module<'ra> { if let Some(id) = def_id.as_local() { - self.local_macro_def_scopes[&id] + self.local_macro_def_scopes[&id].to_module() } else { self.get_nearest_non_block_module(def_id) } @@ -247,10 +248,10 @@ pub(crate) fn build_reduced_graph( visitor.parent_scope.macro_rules } - pub(crate) fn build_reduced_graph_external(&self, module: Module<'ra>) { + pub(crate) fn build_reduced_graph_external(&self, module: ExternModule<'ra>) { let def_id = module.def_id(); let children = self.tcx.module_children(def_id); - let parent_scope = ParentScope::module(module, self.arenas); + let parent_scope = ParentScope::module(module.to_module(), self.arenas); for (i, child) in children.iter().enumerate() { self.build_reduced_graph_for_external_crate_res(child, parent_scope, i, None) } @@ -274,7 +275,7 @@ fn build_reduced_graph_for_external_crate_res( child_index: usize, ambig_child: Option<&ModChild>, ) { - let parent = parent_scope.module; + let parent = parent_scope.module.expect_extern(); let child_span = |this: &Self, reexport_chain: &[Reexport], res: def::Res<_>| { this.def_span( reexport_chain @@ -292,7 +293,7 @@ fn build_reduced_graph_for_external_crate_res( let ModChild { ident: _, res, vis, ref reexport_chain } = *ambig_child; let span = child_span(self, reexport_chain, res); let res = res.expect_non_local(); - self.arenas.new_def_decl(res, vis, span, expansion, Some(parent)) + self.arenas.new_def_decl(res, vis, span, expansion, Some(parent.to_module())) }); // Record primary definitions. @@ -545,6 +546,7 @@ fn add_import( root_id, vis, vis_span: item.vis.span, + on_unknown_attr: OnUnknownData::from_attrs(self.r.tcx, item), }); self.r.indeterminate_imports.push(import); @@ -626,42 +628,42 @@ fn build_reduced_graph_for_use_tree( match use_tree.kind { ast::UseTreeKind::Simple(rename) => { - let mut ident = use_tree.ident(); let mut module_path = prefix; - let mut source = module_path.pop().unwrap(); + let source = module_path.pop().unwrap(); // `true` for `...::{self [as target]}` imports, `false` otherwise. let type_ns_only = nested && source.ident.name == kw::SelfLower; + // Suggest `use prefix::{self};` for `use prefix::self;` if source.ident.name == kw::SelfLower - && let Some(parent) = module_path.pop() + && let Some(parent) = module_path.last() + && !type_ns_only + && (parent.ident.name != kw::PathRoot + || self.r.path_root_is_crate_root(parent.ident)) { - // Suggest `use prefix::{self};` for `use prefix::self;` - if !type_ns_only - && (parent.ident.name != kw::PathRoot - || self.r.path_root_is_crate_root(parent.ident)) - { - let span_with_rename = match rename { - Some(rename) => source.ident.span.to(rename.span), - None => source.ident.span, - }; + let span_with_rename = match rename { + Some(rename) => source.ident.span.to(rename.span), + None => source.ident.span, + }; - self.r.report_error( - parent.ident.span.shrink_to_hi().to(source.ident.span), - ResolutionError::SelfImportsOnlyAllowedWithin { - root: parent.ident.name == kw::PathRoot, - span_with_rename, - }, - ); - } - - let self_span = source.ident.span; - source = parent; - if rename.is_none() { - ident = Ident::new(source.ident.name, self_span); - } + self.r.report_error( + parent.ident.span.shrink_to_hi().to(source.ident.span), + ResolutionError::SelfImportsOnlyAllowedWithin { + root: parent.ident.name == kw::PathRoot, + span_with_rename, + }, + ); } + let ident = if source.ident.name == kw::SelfLower + && rename.is_none() + && let Some(parent) = module_path.last() + { + Ident::new(parent.ident.name, source.ident.span) + } else { + use_tree.ident() + }; + match source.ident.name { kw::DollarCrate => { if !module_path.is_empty() { @@ -698,7 +700,11 @@ fn build_reduced_graph_for_use_tree( } } // Deny `use ::{self};` after edition 2015 - kw::PathRoot if !self.r.path_root_is_crate_root(source.ident) => { + kw::SelfLower + if let Some(parent) = module_path.last() + && parent.ident.name == kw::PathRoot + && !self.r.path_root_is_crate_root(parent.ident) => + { self.r.dcx().span_err(use_tree.span(), "extern prelude cannot be imported"); return; } @@ -797,7 +803,7 @@ fn build_reduced_graph_for_struct_variant( adt_span: Span, ) { let parent_scope = &self.parent_scope; - let parent = parent_scope.module; + let parent = parent_scope.module.expect_local(); let expansion = parent_scope.expansion; // Define a name in the type namespace if it is not anonymous. @@ -813,7 +819,7 @@ fn build_reduced_graph_for_struct_variant( /// Constructs the reduced graph for one item. fn build_reduced_graph_for_item(&mut self, item: &'a Item) { let parent_scope = &self.parent_scope; - let parent = parent_scope.module; + let parent = parent_scope.module.expect_local(); let expansion = parent_scope.expansion; let sp = item.span; let vis = self.resolve_visibility(&item.vis); @@ -858,7 +864,7 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { { self.r.mods_with_parse_errors.insert(def_id); } - self.parent_scope.module = self.r.new_local_module( + let module = self.r.new_local_module( Some(parent), ModuleKind::Def(def_kind, def_id, Some(ident.name)), expansion.to_expn_id(), @@ -866,6 +872,7 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { parent.no_implicit_prelude || ast::attr::contains_name(&item.attrs, sym::no_implicit_prelude), ); + self.parent_scope.module = module.to_module(); } // These items live in the value namespace. @@ -891,13 +898,14 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { ItemKind::Enum(ident, _, _) | ItemKind::Trait(box ast::Trait { ident, .. }) => { self.r.define_local(parent, ident, TypeNS, res, vis, sp, expansion); - self.parent_scope.module = self.r.new_local_module( + let module = self.r.new_local_module( Some(parent), ModuleKind::Def(def_kind, def_id, Some(ident.name)), expansion.to_expn_id(), item.span, parent.no_implicit_prelude, ); + self.parent_scope.module = module.to_module(); } // These items live in both the type and value namespaces. @@ -924,7 +932,7 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { vis }; - let mut ret_fields = Vec::with_capacity(vdata.fields().len()); + let mut field_visibilities = Vec::with_capacity(vdata.fields().len()); for field in vdata.fields() { // NOTE: The field may be an expansion placeholder, but expansion sets @@ -936,7 +944,7 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { if ctor_vis.is_at_least(field_vis, self.r.tcx) { ctor_vis = field_vis; } - ret_fields.push(field_vis.to_def_id()); + field_visibilities.push(field_vis.to_def_id()); } let feed = self.r.feed(ctor_node_id); let ctor_def_id = feed.key(); @@ -946,9 +954,9 @@ fn build_reduced_graph_for_item(&mut self, item: &'a Item) { // We need the field visibility spans also for the constructor for E0603. self.insert_field_visibilities_local(ctor_def_id.to_def_id(), vdata.fields()); - self.r - .struct_constructors - .insert(local_def_id, (ctor_res, ctor_vis.to_def_id(), ret_fields)); + let ctor = + StructCtor { res: ctor_res, vis: ctor_vis.to_def_id(), field_visibilities }; + self.r.struct_ctors.insert(local_def_id, ctor); } self.r.struct_generics.insert(local_def_id, generics.clone()); } @@ -993,7 +1001,7 @@ fn build_reduced_graph_for_extern_crate( self.r.dcx().emit_err(errors::ExternCrateSelfRequiresRenaming { span: sp }); return; } else if orig_name == Some(kw::SelfLower) { - Some(self.r.graph_root) + Some(self.r.graph_root.to_module()) } else { let tcx = self.r.tcx; let crate_id = self.r.cstore_mut().process_extern_crate( @@ -1026,6 +1034,7 @@ fn build_reduced_graph_for_extern_crate( module_path: Vec::new(), vis, vis_span: item.vis.span, + on_unknown_attr: OnUnknownData::from_attrs(self.r.tcx, item), }); if used { self.r.import_use_map.insert(import, Used::Other); @@ -1033,7 +1042,7 @@ fn build_reduced_graph_for_extern_crate( self.r.potentially_unused_imports.push(import); let import_decl = self.r.new_import_decl(decl, import); let ident = IdentKey::new(orig_ident); - if ident.name != kw::Underscore && parent == self.r.graph_root { + if ident.name != kw::Underscore && parent == self.r.graph_root.to_module() { // FIXME: this error is technically unnecessary now when extern prelude is split into // two scopes, remove it with lang team approval. if let Some(entry) = self.r.extern_prelude.get(&ident) @@ -1078,7 +1087,7 @@ fn build_reduced_graph_for_foreign_item(&mut self, item: &ForeignItem, ident: Id ForeignItemKind::TyAlias(..) => TypeNS, ForeignItemKind::MacCall(..) => unreachable!(), }; - let parent = self.parent_scope.module; + let parent = self.parent_scope.module.expect_local(); let expansion = self.parent_scope.expansion; let vis = self.resolve_visibility(&item.vis); self.r.define_local(parent, ident, ns, self.res(def_id), vis, item.span, expansion); @@ -1086,7 +1095,7 @@ fn build_reduced_graph_for_foreign_item(&mut self, item: &ForeignItem, ident: Id } fn build_reduced_graph_for_block(&mut self, block: &Block) { - let parent = self.parent_scope.module; + let parent = self.parent_scope.module.expect_local(); let expansion = self.parent_scope.expansion; if self.block_needs_anonymous_module(block) { let module = self.r.new_local_module( @@ -1097,7 +1106,7 @@ fn build_reduced_graph_for_block(&mut self, block: &Block) { parent.no_implicit_prelude, ); self.r.block_map.insert(block.id, module); - self.parent_scope.module = module; // Descend into the block. + self.parent_scope.module = module.to_module(); // Descend into the block. } } @@ -1118,14 +1127,7 @@ fn process_macro_use_imports(&mut self, item: &Item, module: Module<'ra>) -> boo let mut import_all = None; let mut single_imports = ThinVec::new(); if let Some(Attribute::Parsed(AttributeKind::MacroUse { span, arguments })) = - AttributeParser::parse_limited( - self.r.tcx.sess, - &item.attrs, - sym::macro_use, - item.span, - item.id, - None, - ) + AttributeParser::parse_limited(self.r.tcx.sess, &item.attrs, &[sym::macro_use]) { if self.parent_scope.module.parent.is_some() { self.r @@ -1158,6 +1160,7 @@ fn process_macro_use_imports(&mut self, item: &Item, module: Module<'ra>) -> boo module_path: Vec::new(), vis: Visibility::Restricted(CRATE_DEF_ID), vis_span: item.vis.span, + on_unknown_attr: OnUnknownData::from_attrs(this.r.tcx, item), }) }; @@ -1296,7 +1299,7 @@ fn define_macro(&mut self, item: &ast::Item) -> MacroRulesScopeRef<'ra> { _ => unreachable!(), }; - self.r.local_macro_def_scopes.insert(def_id, parent_scope.module); + self.r.local_macro_def_scopes.insert(def_id, parent_scope.module.expect_local()); if macro_rules { let ident = IdentKey::new(orig_ident); @@ -1319,7 +1322,10 @@ fn define_macro(&mut self, item: &ast::Item) -> MacroRulesScopeRef<'ra> { let import = self.r.arenas.alloc_import(ImportData { kind: ImportKind::MacroExport, root_id: item.id, - parent_scope: ParentScope { module: self.r.graph_root, ..parent_scope }, + parent_scope: ParentScope { + module: self.r.graph_root.to_module(), + ..parent_scope + }, imported_module: CmCell::new(None), has_attributes: false, use_span_with_attributes: span, @@ -1329,6 +1335,7 @@ fn define_macro(&mut self, item: &ast::Item) -> MacroRulesScopeRef<'ra> { module_path: Vec::new(), vis, vis_span: item.vis.span, + on_unknown_attr: OnUnknownData::from_attrs(self.r.tcx, item), }); self.r.import_use_map.insert(import, Used::Other); let import_decl = self.r.new_import_decl(decl, import); @@ -1349,7 +1356,7 @@ fn define_macro(&mut self, item: &ast::Item) -> MacroRulesScopeRef<'ra> { self.r.macro_rules_scopes.insert(def_id, scope); scope } else { - let module = parent_scope.module; + let module = parent_scope.module.expect_local(); let vis = match item.kind { // Visibilities must not be resolved non-speculatively twice // and we already resolved this one as a `fn` item visibility. @@ -1497,7 +1504,7 @@ fn visit_assoc_item(&mut self, item: &'a AssocItem, ctxt: AssocCtxt) { } if ctxt == AssocCtxt::Trait { - let parent = self.parent_scope.module; + let parent = self.parent_scope.module.expect_local(); let expansion = self.parent_scope.expansion; self.r.define_local(parent, ident, ns, self.res(def_id), vis, item.span, expansion); } else if !matches!(&item.kind, AssocItemKind::Delegation(deleg) if deleg.from_glob) @@ -1579,7 +1586,7 @@ fn visit_variant(&mut self, variant: &'a ast::Variant) { return; } - let parent = self.parent_scope.module; + let parent = self.parent_scope.module.expect_local(); let expn_id = self.parent_scope.expansion; let ident = variant.ident; diff --git a/compiler/rustc_resolve/src/check_unused.rs b/compiler/rustc_resolve/src/check_unused.rs index b5246808cd5a..7e1b1bce3ff7 100644 --- a/compiler/rustc_resolve/src/check_unused.rs +++ b/compiler/rustc_resolve/src/check_unused.rs @@ -545,7 +545,7 @@ pub(crate) fn check_unused(&mut self, krate: &ast::Crate) { let unused_imports = visitor.unused_imports; let mut check_redundant_imports = FxIndexSet::default(); for module in &self.local_modules { - for (_key, resolution) in self.resolutions(*module).borrow().iter() { + for (_key, resolution) in self.resolutions(module.to_module()).borrow().iter() { if let Some(decl) = resolution.borrow().best_decl() && let DeclKind::Import { import, .. } = decl.kind && let ImportKind::Single { id, .. } = import.kind diff --git a/compiler/rustc_resolve/src/def_collector.rs b/compiler/rustc_resolve/src/def_collector.rs index 0cc633e713b3..78dcb0620e5b 100644 --- a/compiler/rustc_resolve/src/def_collector.rs +++ b/compiler/rustc_resolve/src/def_collector.rs @@ -146,7 +146,7 @@ fn visit_item(&mut self, i: &'a Item) { let mut parser = AttributeParser::<'_, Early>::new( &self.resolver.tcx.sess, self.resolver.tcx.features(), - self.resolver.tcx().registered_tools(()), + Vec::new(), Early { emit_errors: ShouldEmit::Nothing }, ); let attrs = parser.parse_attribute_list( @@ -274,6 +274,7 @@ fn visit_foreign_item(&mut self, fi: &'a ForeignItem) { expr: _, safety, define_opaque: _, + eii_impls: _, }) => { let safety = match safety { ast::Safety::Unsafe(_) | ast::Safety::Default => hir::Safety::Unsafe, diff --git a/compiler/rustc_resolve/src/diagnostics.rs b/compiler/rustc_resolve/src/diagnostics.rs index 9e0f04e82b47..bf260d823b76 100644 --- a/compiler/rustc_resolve/src/diagnostics.rs +++ b/compiler/rustc_resolve/src/diagnostics.rs @@ -17,11 +17,11 @@ use rustc_feature::BUILTIN_ATTRIBUTES; use rustc_hir::attrs::{CfgEntry, StrippedCfgItem}; use rustc_hir::def::Namespace::{self, *}; -use rustc_hir::def::{self, CtorKind, CtorOf, DefKind, MacroKinds, NonMacroAttrKind, PerNS}; +use rustc_hir::def::{CtorKind, CtorOf, DefKind, MacroKinds, NonMacroAttrKind, PerNS}; use rustc_hir::def_id::{CRATE_DEF_ID, DefId}; use rustc_hir::{PrimTy, Stability, StabilityLevel, find_attr}; use rustc_middle::bug; -use rustc_middle::ty::TyCtxt; +use rustc_middle::ty::{TyCtxt, Visibility}; use rustc_session::Session; use rustc_session::lint::builtin::{ ABSOLUTE_PATHS_NOT_STARTING_WITH_CRATE, AMBIGUOUS_GLOB_IMPORTS, AMBIGUOUS_IMPORT_VISIBILITIES, @@ -49,13 +49,11 @@ use crate::{ AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingError, BindingKey, Decl, DeclKind, Finalize, ForwardGenericParamBanReason, HasGenericParams, IdentKey, LateDecl, MacroRulesScope, - Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, + Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, Res, ResolutionError, Resolver, Scope, ScopeSet, Segment, UseError, Used, VisResolutionError, errors as errs, path_names_to_string, }; -type Res = def::Res; - /// A vector of spans and replacements, a message and applicability. pub(crate) type Suggestion = (Vec<(Span, String)>, String, Applicability); @@ -63,6 +61,19 @@ /// similarly named label and whether or not it is reachable. pub(crate) type LabelSuggestion = (Ident, bool); +#[derive(Clone)] +pub(crate) struct StructCtor { + pub res: Res, + pub vis: Visibility, + pub field_visibilities: Vec>, +} + +impl StructCtor { + pub(crate) fn has_private_fields<'ra>(&self, m: Module<'ra>, r: &Resolver<'ra, '_>) -> bool { + self.field_visibilities.iter().any(|&vis| !r.is_accessible_from(vis, m)) + } +} + #[derive(Debug)] pub(crate) enum SuggestionTarget { /// The target has a similar name as the name used by the programmer (probably a typo) @@ -1574,7 +1585,7 @@ pub(crate) fn lookup_import_candidates( lookup_ident, namespace, parent_scope, - self.graph_root, + self.graph_root.to_module(), crate_path, &filter_fn, ); @@ -2063,7 +2074,7 @@ fn ambiguity_diagnostic(&self, ambiguity_error: &AmbiguityError<'ra>) -> errors: if kind != AmbiguityKind::GlobVsGlob { if let Scope::ModuleNonGlobs(module, _) | Scope::ModuleGlobs(module, _) = scope { - if module == self.graph_root { + if module == self.graph_root.to_module() { help_msgs.push(format!( "use `crate::{ident}` to refer to this {thing} unambiguously" )); @@ -2441,7 +2452,8 @@ pub(crate) fn find_similarly_named_module_or_crate( self.local_module_map .iter() .filter(|(_, module)| { - current_module.is_ancestor_of(**module) && current_module != **module + let module = module.to_module(); + current_module.is_ancestor_of(module) && current_module != module }) .flat_map(|(_, module)| module.kind.name()), ) @@ -2450,7 +2462,8 @@ pub(crate) fn find_similarly_named_module_or_crate( .borrow() .iter() .filter(|(_, module)| { - current_module.is_ancestor_of(**module) && current_module != **module + let module = module.to_module(); + current_module.is_ancestor_of(module) && current_module != module }) .flat_map(|(_, module)| module.kind.name()), ) @@ -2983,7 +2996,7 @@ pub(crate) fn check_for_module_export_macro( } let binding_key = BindingKey::new(IdentKey::new(ident), MacroNS); - let binding = self.resolution(crate_module, binding_key)?.binding()?; + let binding = self.resolution(crate_module, binding_key)?.best_decl()?; let Res::Def(DefKind::Macro(kinds), _) = binding.res() else { return None; }; @@ -3176,6 +3189,25 @@ fn comes_from_same_module_for_glob( err.subdiagnostic(note); } } + + pub(crate) fn struct_ctor(&self, def_id: DefId) -> Option { + match def_id.as_local() { + Some(def_id) => self.struct_ctors.get(&def_id).cloned(), + None => { + self.cstore().ctor_untracked(self.tcx, def_id).map(|(ctor_kind, ctor_def_id)| { + let res = Res::Def(DefKind::Ctor(CtorOf::Struct, ctor_kind), ctor_def_id); + let vis = self.tcx.visibility(ctor_def_id); + let field_visibilities = self + .tcx + .associated_item_def_ids(def_id) + .iter() + .map(|&field_id| self.tcx.visibility(field_id)) + .collect(); + StructCtor { res, vis, field_visibilities } + }) + } + } + } } /// Given a `binding_span` of a binding within a use statement: diff --git a/compiler/rustc_resolve/src/effective_visibilities.rs b/compiler/rustc_resolve/src/effective_visibilities.rs index 55518276a4f0..cd7790f27b5f 100644 --- a/compiler/rustc_resolve/src/effective_visibilities.rs +++ b/compiler/rustc_resolve/src/effective_visibilities.rs @@ -114,7 +114,7 @@ pub(crate) fn compute_effective_visibilities<'c>( fn set_bindings_effective_visibilities(&mut self, module_id: LocalDefId) { let module = self.r.expect_module(module_id.to_def_id()); for (_, name_resolution) in self.r.resolutions(module).borrow().iter() { - let Some(mut decl) = name_resolution.borrow().binding() else { + let Some(mut decl) = name_resolution.borrow().best_decl() else { continue; }; // Set the given effective visibility level to `Level::Direct` and diff --git a/compiler/rustc_resolve/src/errors.rs b/compiler/rustc_resolve/src/errors.rs index bcc754fd984d..8c7bf61949a2 100644 --- a/compiler/rustc_resolve/src/errors.rs +++ b/compiler/rustc_resolve/src/errors.rs @@ -1521,20 +1521,24 @@ pub(crate) struct RedundantImportVisibility { #[diag("unknown diagnostic attribute")] pub(crate) struct UnknownDiagnosticAttribute { #[subdiagnostic] - pub typo: Option, + pub help: Option, } #[derive(Subdiagnostic)] -#[suggestion( - "an attribute with a similar name exists", - style = "verbose", - code = "{typo_name}", - applicability = "machine-applicable" -)] -pub(crate) struct UnknownDiagnosticAttributeTypoSugg { - #[primary_span] - pub span: Span, - pub typo_name: Symbol, +pub(crate) enum UnknownDiagnosticAttributeHelp { + #[suggestion( + "an attribute with a similar name exists", + style = "verbose", + code = "{typo_name}", + applicability = "machine-applicable" + )] + Typo { + #[primary_span] + span: Span, + typo_name: Symbol, + }, + #[help("add `#![feature({$feature})]` to the crate attributes to enable")] + UseFeature { feature: Symbol }, } // FIXME: Make this properly translatable. diff --git a/compiler/rustc_resolve/src/ident.rs b/compiler/rustc_resolve/src/ident.rs index 95d68e2f8b39..56a0ee2acc1a 100644 --- a/compiler/rustc_resolve/src/ident.rs +++ b/compiler/rustc_resolve/src/ident.rs @@ -24,9 +24,9 @@ use crate::macros::{MacroRulesScope, sub_namespace_match}; use crate::{ AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingKey, CmResolver, Decl, DeclKind, - Determinacy, Finalize, IdentKey, ImportKind, LateDecl, Module, ModuleKind, ModuleOrUniformRoot, - ParentScope, PathResult, PrivacyError, Res, ResolutionError, Resolver, Scope, ScopeSet, - Segment, Stage, Symbol, Used, errors, + Determinacy, Finalize, IdentKey, ImportKind, LateDecl, LocalModule, Module, ModuleKind, + ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, Res, ResolutionError, Resolver, + Scope, ScopeSet, Segment, Stage, Symbol, Used, errors, }; #[derive(Copy, Clone)] @@ -346,7 +346,7 @@ pub(crate) fn resolve_ident_in_lexical_scope( } else if let RibKind::Block(Some(module)) = rib.kind && let Ok(binding) = self.cm().resolve_ident_in_scope_set( ident, - ScopeSet::Module(ns, module), + ScopeSet::Module(ns, module.to_module()), parent_scope, finalize.map(|finalize| Finalize { used: Used::Scope, ..finalize }), ignore_decl, @@ -357,7 +357,7 @@ pub(crate) fn resolve_ident_in_lexical_scope( return Some(LateDecl::Decl(binding)); } else if let RibKind::Module(module) = rib.kind { // Encountered a module item, abandon ribs and look into that module and preludes. - let parent_scope = &ParentScope { module, ..*parent_scope }; + let parent_scope = &ParentScope { module: module.to_module(), ..*parent_scope }; let finalize = finalize.map(|f| Finalize { stage: Stage::Late, ..f }); return self .cm() @@ -658,7 +658,7 @@ fn resolve_ident_in_scope<'r>( ) }; let binding = self.reborrow().resolve_ident_in_module_globs_unadjusted( - module, + module.expect_local(), ident, orig_ident_span, ns, @@ -959,12 +959,16 @@ pub(crate) fn resolve_ident_in_module<'r>( ) -> Result, Determinacy> { match module { ModuleOrUniformRoot::Module(module) => { - if ns == TypeNS - && ident.name == kw::Super - && let Some(module) = - self.resolve_super_in_module(ident, Some(module), parent_scope) - { - return Ok(module.self_decl.unwrap()); + if ns == TypeNS { + if ident.name == kw::SelfLower { + return Ok(module.self_decl.unwrap()); + } + if ident.name == kw::Super + && let Some(module) = + self.resolve_super_in_module(ident, Some(module), parent_scope) + { + return Ok(module.self_decl.unwrap()); + } } let (ident_key, def) = IdentKey::new_adjusted(ident, module.expansion); @@ -1032,7 +1036,7 @@ pub(crate) fn resolve_ident_in_module<'r>( { let module = self.resolve_crate_root(ident); return Ok(module.self_decl.unwrap()); - } else if ident.name == kw::Super || ident.name == kw::SelfLower { + } else if ident.name == kw::Super { // FIXME: Implement these with renaming requirements so that e.g. // `use super;` doesn't work, but `use super as name;` does. // Fall through here to get an error from `early_resolve_...`. @@ -1083,7 +1087,6 @@ fn resolve_ident_in_module_non_globs_unadjusted<'r>( orig_ident_span, binding, parent_scope, - module, finalize, shadowing, ); @@ -1119,7 +1122,7 @@ fn resolve_ident_in_module_non_globs_unadjusted<'r>( /// Attempts to resolve `ident` in namespace `ns` of glob bindings in `module`. fn resolve_ident_in_module_globs_unadjusted<'r>( mut self: CmResolver<'r, 'ra, 'tcx>, - module: Module<'ra>, + module: LocalModule<'ra>, ident: IdentKey, orig_ident_span: Span, ns: Namespace, @@ -1134,7 +1137,7 @@ fn resolve_ident_in_module_globs_unadjusted<'r>( // doesn't need to be mutable. It will fail when there is a cycle of imports, and without // the exclusive access infinite recursion will crash the compiler with stack overflow. let resolution = &*self - .resolution_or_default(module, key, orig_ident_span) + .resolution_or_default(module.to_module(), key, orig_ident_span) .try_borrow_mut_unchecked() .map_err(|_| ControlFlow::Continue(Determined))?; @@ -1146,7 +1149,6 @@ fn resolve_ident_in_module_globs_unadjusted<'r>( orig_ident_span, binding, parent_scope, - module, finalize, shadowing, ); @@ -1256,7 +1258,6 @@ fn finalize_module_binding( orig_ident_span: Span, binding: Option>, parent_scope: &ParentScope<'ra>, - module: Module<'ra>, finalize: Finalize, shadowing: Shadowing, ) -> Result, ControlFlow> { @@ -1291,37 +1292,6 @@ fn finalize_module_binding( self.macro_expanded_macro_export_errors.insert((path_span, binding.span)); } - // If we encounter a re-export for a type with private fields, it will not be able to - // be constructed through this re-export. We track that case here to expand later - // privacy errors with appropriate information. - if let Res::Def(_, def_id) = binding.res() { - let struct_ctor = match def_id.as_local() { - Some(def_id) => self.struct_constructors.get(&def_id).cloned(), - None => { - let ctor = self.cstore().ctor_untracked(self.tcx(), def_id); - ctor.map(|(ctor_kind, ctor_def_id)| { - let ctor_res = Res::Def( - DefKind::Ctor(rustc_hir::def::CtorOf::Struct, ctor_kind), - ctor_def_id, - ); - let ctor_vis = self.tcx.visibility(ctor_def_id); - let field_visibilities = self - .tcx - .associated_item_def_ids(def_id) - .iter() - .map(|&field_id| self.tcx.visibility(field_id)) - .collect(); - (ctor_res, ctor_vis, field_visibilities) - }) - } - }; - if let Some((_, _, fields)) = struct_ctor - && fields.iter().any(|vis| !self.is_accessible_from(*vis, module)) - { - self.inaccessible_ctor_reexport.insert(path_span, binding.span); - } - } - self.record_use(ident, binding, used); return Ok(binding); } diff --git a/compiler/rustc_resolve/src/imports.rs b/compiler/rustc_resolve/src/imports.rs index d51ce9fb7946..067dbd06d7b0 100644 --- a/compiler/rustc_resolve/src/imports.rs +++ b/compiler/rustc_resolve/src/imports.rs @@ -2,16 +2,20 @@ use std::mem; -use rustc_ast::NodeId; +use rustc_ast::{Item, NodeId}; +use rustc_attr_parsing::AttributeParser; use rustc_data_structures::fx::{FxHashSet, FxIndexSet}; use rustc_data_structures::intern::Interned; use rustc_errors::codes::*; use rustc_errors::{Applicability, Diagnostic, MultiSpan, pluralize, struct_span_code_err}; +use rustc_hir::Attribute; +use rustc_hir::attrs::AttributeKind; +use rustc_hir::attrs::diagnostic::{CustomDiagnostic, Directive, FormatArgs}; use rustc_hir::def::{self, DefKind, PartialRes}; use rustc_hir::def_id::{DefId, LocalDefIdMap}; use rustc_middle::metadata::{AmbigModChild, ModChild, Reexport}; use rustc_middle::span_bug; -use rustc_middle::ty::Visibility; +use rustc_middle::ty::{TyCtxt, Visibility}; use rustc_session::lint::builtin::{ AMBIGUOUS_GLOB_REEXPORTS, EXPORTED_PRIVATE_DEPENDENCIES, HIDDEN_GLOB_REEXPORTS, PUB_USE_OF_PRIVATE_EXTERN_CRATE, REDUNDANT_IMPORTS, UNUSED_IMPORTS, @@ -33,12 +37,10 @@ use crate::ref_mut::CmCell; use crate::{ AmbiguityError, BindingKey, CmResolver, Decl, DeclData, DeclKind, Determinacy, Finalize, - IdentKey, ImportSuggestion, Module, ModuleOrUniformRoot, ParentScope, PathResult, PerNS, - ResolutionError, Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string, + IdentKey, ImportSuggestion, LocalModule, ModuleOrUniformRoot, ParentScope, PathResult, PerNS, + Res, ResolutionError, Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string, }; -type Res = def::Res; - /// A potential import declaration in the process of being planted into a module. /// Also used for lazily planting names from `--extern` flags to extern prelude. #[derive(Clone, Copy, Default, PartialEq, Debug)] @@ -140,6 +142,28 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { } } +#[derive(Debug, Clone, Default)] +pub(crate) struct OnUnknownData { + directive: Box, +} + +impl OnUnknownData { + pub(crate) fn from_attrs<'tcx>(tcx: TyCtxt<'tcx>, item: &Item) -> Option { + if tcx.features().diagnostic_on_unknown() + && let Some(Attribute::Parsed(AttributeKind::OnUnknown { directive, .. })) = + AttributeParser::parse_limited( + tcx.sess, + &item.attrs, + &[sym::diagnostic, sym::on_unknown], + ) + { + Some(Self { directive: directive? }) + } else { + None + } + } +} + /// One import. #[derive(Debug, Clone)] pub(crate) struct ImportData<'ra> { @@ -186,6 +210,13 @@ pub(crate) struct ImportData<'ra> { /// Span of the visibility. pub vis_span: Span, + + /// A `#[diagnostic::on_unknown]` attribute applied + /// to the given import. This allows crates to specify + /// custom error messages for a specific import + /// + /// This is `None` if the feature flag for `diagnostic::on_unknown` is disabled. + pub on_unknown_attr: Option, } /// All imports are unique and allocated on a same arena, @@ -256,15 +287,22 @@ pub(crate) fn new(orig_ident_span: Span) -> Self { NameResolution { single_imports: FxIndexSet::default(), orig_ident_span, .. } } - /// Returns the binding for the name if it is known or None if it not known. - pub(crate) fn binding(&self) -> Option> { - self.best_decl().and_then(|binding| { - if !binding.is_glob_import() || self.single_imports.is_empty() { - Some(binding) - } else { - None - } - }) + /// Returns the best declaration if it is not going to change, and `None` if the best + /// declaration may still change to something else. + /// FIXME: this function considers `single_imports`, but not `unexpanded_invocations`, so + /// the returned declaration may actually change after expanding macros in the same module, + /// because of this fact we have glob overwriting (`select_glob_decl`). Consider using + /// `unexpanded_invocations` here and avoiding glob overwriting entirely, if it doesn't cause + /// code breakage in practice. + /// FIXME: relationship between this function and similar `DeclData::determined` is unclear. + pub(crate) fn determined_decl(&self) -> Option> { + if self.non_glob_decl.is_some() { + self.non_glob_decl + } else if self.glob_decl.is_some() && self.single_imports.is_empty() { + self.glob_decl + } else { + None + } } pub(crate) fn best_decl(&self) -> Option> { @@ -284,6 +322,7 @@ struct UnresolvedImportError { segment: Option, /// comes from `PathRes::Failed { module }` module: Option, + on_unknown_attr: Option, } // Reexports of the form `pub use foo as bar;` where `foo` is `extern crate foo;` @@ -432,7 +471,7 @@ pub(crate) fn try_plant_decl_into_local_module( decl: Decl<'ra>, warn_ambiguity: bool, ) -> Result<(), Decl<'ra>> { - let module = decl.parent_module.unwrap(); + let module = decl.parent_module.unwrap().expect_local(); let res = decl.res(); self.check_reserved_macro_name(ident.name, orig_ident_span, res); // Even if underscore names cannot be looked up, we still need to add them to modules, @@ -448,41 +487,21 @@ pub(crate) fn try_plant_decl_into_local_module( orig_ident_span, warn_ambiguity, |this, resolution| { - if let Some(old_decl) = resolution.best_decl() { - assert_ne!(decl, old_decl); - assert!(!decl.warn_ambiguity.get()); - if res == Res::Err && old_decl.res() != Res::Err { - // Do not override real declarations with `Res::Err`s from error recovery. - return Ok(()); - } - match (old_decl.is_glob_import(), decl.is_glob_import()) { - (true, true) => { - resolution.glob_decl = - Some(this.select_glob_decl(old_decl, decl, warn_ambiguity)); - } - (old_glob @ true, false) | (old_glob @ false, true) => { - let (glob_decl, non_glob_decl) = - if old_glob { (old_decl, decl) } else { (decl, old_decl) }; - resolution.non_glob_decl = Some(non_glob_decl); - if let Some(old_glob_decl) = resolution.glob_decl - && old_glob_decl != glob_decl - { - resolution.glob_decl = - Some(this.select_glob_decl(old_glob_decl, glob_decl, false)); - } else { - resolution.glob_decl = Some(glob_decl); - } - } - (false, false) => { - return Err(old_decl); - } - } + assert!(!decl.warn_ambiguity.get()); + if decl.is_glob_import() { + resolution.glob_decl = Some(match resolution.glob_decl { + Some(old_decl) => this.select_glob_decl( + old_decl, + decl, + warn_ambiguity && resolution.non_glob_decl.is_none(), + ), + None => decl, + }) } else { - if decl.is_glob_import() { - resolution.glob_decl = Some(decl); - } else { - resolution.non_glob_decl = Some(decl); - } + resolution.non_glob_decl = Some(match resolution.non_glob_decl { + Some(old_decl) => return Err(old_decl), + None => decl, + }) } Ok(()) @@ -494,7 +513,7 @@ pub(crate) fn try_plant_decl_into_local_module( // If the resolution becomes a success, define it in the module's glob importers. fn update_local_resolution( &mut self, - module: Module<'ra>, + module: LocalModule<'ra>, key: BindingKey, orig_ident_span: Span, warn_ambiguity: bool, @@ -507,13 +526,13 @@ fn update_local_resolution( // during which the resolution might end up getting re-defined via a glob cycle. let (binding, t, warn_ambiguity) = { let resolution = &mut *self - .resolution_or_default(module, key, orig_ident_span) + .resolution_or_default(module.to_module(), key, orig_ident_span) .borrow_mut_unchecked(); - let old_decl = resolution.binding(); + let old_decl = resolution.determined_decl(); let t = f(self, resolution); - if let Some(binding) = resolution.binding() + if let Some(binding) = resolution.determined_decl() && old_decl != Some(binding) { (binding, t, warn_ambiguity || old_decl.is_some()) @@ -539,13 +558,14 @@ fn update_local_resolution( }; if self.is_accessible_from(binding.vis(), scope) { let import_decl = self.new_import_decl(binding, *import); - let _ = self.try_plant_decl_into_local_module( + self.try_plant_decl_into_local_module( ident, orig_ident_span, key.ns, import_decl, warn_ambiguity, - ); + ) + .expect("planting a glob cannot fail"); } } @@ -562,8 +582,8 @@ fn import_dummy_binding(&mut self, import: Import<'ra>, is_indeterminate: bool) let dummy_decl = self.dummy_decl; let dummy_decl = self.new_import_decl(dummy_decl, import); self.per_ns(|this, ns| { - let module = import.parent_scope.module; let ident = IdentKey::new(target); + // This can fail, dummies are inserted only in non-occupied slots. let _ = this.try_plant_decl_into_local_module( ident, target.span, @@ -575,7 +595,7 @@ fn import_dummy_binding(&mut self, import: Import<'ra>, is_indeterminate: bool) if target.name != kw::Underscore { let key = BindingKey::new(ident, ns); this.update_local_resolution( - module, + import.parent_scope.module.expect_local(), key, target.span, false, @@ -700,6 +720,7 @@ pub(crate) fn finalize_imports(&mut self) { candidates: None, segment: None, module: None, + on_unknown_attr: import.on_unknown_attr.clone(), }; errors.push((*import, err)) } @@ -712,7 +733,7 @@ pub(crate) fn finalize_imports(&mut self) { pub(crate) fn lint_reexports(&mut self, exported_ambiguities: FxHashSet>) { for module in &self.local_modules { - for (key, resolution) in self.resolutions(*module).borrow().iter() { + for (key, resolution) in self.resolutions(module.to_module()).borrow().iter() { let resolution = resolution.borrow(); let Some(binding) = resolution.best_decl() else { continue }; @@ -822,11 +843,41 @@ fn throw_unresolved_import_error( format!("`{path}`") }) .collect::>(); - let msg = format!("unresolved import{} {}", pluralize!(paths.len()), paths.join(", "),); + let default_message = + format!("unresolved import{} {}", pluralize!(paths.len()), paths.join(", "),); + let (message, label, notes) = + // Feature gating for `on_unknown_attr` happens initialization of the field + if let Some(directive) = errors[0].1.on_unknown_attr.as_ref().map(|a| &a.directive) { + let args = FormatArgs { + this: paths.join(", "), + // Unused + this_sugared: String::new(), + // Unused + item_context: "", + // Unused + generic_args: Vec::new(), + }; + let CustomDiagnostic { message, label, notes, .. } = directive.eval(None, &args); - let mut diag = struct_span_code_err!(self.dcx(), span, E0432, "{msg}"); + (message, label, notes) + } else { + (None, None, Vec::new()) + }; + let has_custom_message = message.is_some(); + let message = message.as_deref().unwrap_or(default_message.as_str()); - if let Some((_, UnresolvedImportError { note: Some(note), .. })) = errors.iter().last() { + let mut diag = struct_span_code_err!(self.dcx(), span, E0432, "{message}"); + if has_custom_message { + diag.note(default_message); + } + + if !notes.is_empty() { + for note in notes { + diag.note(note); + } + } else if let Some((_, UnresolvedImportError { note: Some(note), .. })) = + errors.iter().last() + { diag.note(note.clone()); } @@ -834,8 +885,10 @@ fn throw_unresolved_import_error( const MAX_LABEL_COUNT: usize = 10; for (import, err) in errors.into_iter().take(MAX_LABEL_COUNT) { - if let Some(label) = err.label { - diag.span_label(err.span, label); + if let Some(label) = &label { + diag.span_label(err.span, label.clone()); + } else if let Some(label) = &err.label { + diag.span_label(err.span, label.clone()); } if let Some((suggestions, msg, applicability)) = err.suggestion { @@ -973,7 +1026,7 @@ fn resolve_import<'r>(mut self: CmResolver<'r, 'ra, 'tcx>, import: Import<'ra>) if target.name != kw::Underscore { let key = BindingKey::new(IdentKey::new(target), ns); this.get_mut_unchecked().update_local_resolution( - parent, + parent.expect_local(), key, target.span, false, @@ -1101,6 +1154,7 @@ fn finalize_import(&mut self, import: Import<'ra>) -> Option UnresolvedImportError { span, @@ -1110,6 +1164,7 @@ fn finalize_import(&mut self, import: Import<'ra>) -> Option) -> Option) -> Option) { .iter() .filter_map(|(key, resolution)| { let resolution = resolution.borrow(); - resolution.binding().map(|binding| (*key, binding, resolution.orig_ident_span)) + resolution.determined_decl().map(|decl| (*key, decl, resolution.orig_ident_span)) }) .collect::>(); for (mut key, binding, orig_ident_span) in bindings { @@ -1621,15 +1678,16 @@ fn resolve_glob_import(&mut self, import: Import<'ra>) { let import_decl = self.new_import_decl(binding, import); let warn_ambiguity = self .resolution(import.parent_scope.module, key) - .and_then(|r| r.binding()) + .and_then(|r| r.determined_decl()) .is_some_and(|binding| binding.warn_ambiguity_recursive()); - let _ = self.try_plant_decl_into_local_module( + self.try_plant_decl_into_local_module( key.ident, orig_ident_span, key.ns, import_decl, warn_ambiguity, - ); + ) + .expect("planting a glob cannot fail"); } } @@ -1641,7 +1699,7 @@ fn resolve_glob_import(&mut self, import: Import<'ra>) { // reporting conflicts, and reporting unresolved imports. fn finalize_resolutions_in( &self, - module: Module<'ra>, + module: LocalModule<'ra>, module_children: &mut LocalDefIdMap>, ambig_module_children: &mut LocalDefIdMap>, ) { @@ -1653,7 +1711,7 @@ fn finalize_resolutions_in( let mut children = Vec::new(); let mut ambig_children = Vec::new(); - module.for_each_child(self, |this, ident, orig_ident_span, _, binding| { + module.to_module().for_each_child(self, |this, ident, orig_ident_span, _, binding| { let res = binding.res().expect_non_local(); if res != def::Res::Err { let ident = ident.orig(orig_ident_span); diff --git a/compiler/rustc_resolve/src/late.rs b/compiler/rustc_resolve/src/late.rs index 57765cc379a5..db71f7ed79d8 100644 --- a/compiler/rustc_resolve/src/late.rs +++ b/compiler/rustc_resolve/src/late.rs @@ -25,7 +25,7 @@ StashKey, Suggestions, elided_lifetime_in_path_suggestion, pluralize, }; use rustc_hir::def::Namespace::{self, *}; -use rustc_hir::def::{self, CtorKind, DefKind, LifetimeRes, NonMacroAttrKind, PartialRes, PerNS}; +use rustc_hir::def::{CtorKind, DefKind, LifetimeRes, NonMacroAttrKind, PartialRes, PerNS}; use rustc_hir::def_id::{CRATE_DEF_ID, DefId, LOCAL_CRATE, LocalDefId}; use rustc_hir::{MissingLifetimeKind, PrimTy, TraitCandidate}; use rustc_middle::middle::resolve_bound_vars::Set1; @@ -40,15 +40,13 @@ use tracing::{debug, instrument, trace}; use crate::{ - BindingError, BindingKey, Decl, DelegationFnSig, Finalize, IdentKey, LateDecl, Module, - ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, Segment, Stage, - TyCtxt, UseError, Used, errors, path_names_to_string, rustdoc, + BindingError, BindingKey, Decl, DelegationFnSig, Finalize, IdentKey, LateDecl, LocalModule, + Module, ModuleOrUniformRoot, ParentScope, PathResult, Res, ResolutionError, Resolver, Segment, + Stage, TyCtxt, UseError, Used, errors, path_names_to_string, rustdoc, }; mod diagnostics; -type Res = def::Res; - use diagnostics::{ElisionFnParameter, LifetimeElisionCandidate, MissingLifetime}; #[derive(Copy, Clone, Debug)] @@ -198,7 +196,7 @@ pub(crate) enum RibKind<'ra> { /// `Block(None)` must be always processed in the same way as `Block(Some(module))` /// with empty `module`. The module can be `None` only because creation of some definitely /// empty modules is skipped as an optimization. - Block(Option>), + Block(Option>), /// We passed through an impl or trait and are now in one of its /// methods or associated types. Allow references to ty params that impl or trait @@ -219,7 +217,7 @@ pub(crate) enum RibKind<'ra> { ConstantItem(ConstantHasGenerics, Option<(Ident, ConstantItemKind)>), /// We passed through a module item. - Module(Module<'ra>), + Module(LocalModule<'ra>), /// We passed through a `macro_rules!` statement MacroDefinition(DefId), @@ -441,6 +439,8 @@ pub(crate) enum PathSource<'a, 'ast, 'ra> { TraitItem(Namespace, &'a PathSource<'a, 'ast, 'ra>), /// Paths in delegation item Delegation, + /// Paths in externally implementable item declarations. + ExternItemImpl, /// An arg in a `use<'a, N>` precise-capturing bound. PreciseCapturingArg(Namespace), /// Paths that end with `(..)`, for return type notation. @@ -465,6 +465,7 @@ fn namespace(self) -> Namespace { | PathSource::Pat | PathSource::TupleStruct(..) | PathSource::Delegation + | PathSource::ExternItemImpl | PathSource::ReturnTypeNotation => ValueNS, PathSource::TraitItem(ns, _) => ns, PathSource::PreciseCapturingArg(ns) => ns, @@ -484,6 +485,7 @@ fn defer_to_typeck(self) -> bool { | PathSource::TraitItem(..) | PathSource::DefineOpaques | PathSource::Delegation + | PathSource::ExternItemImpl | PathSource::PreciseCapturingArg(..) | PathSource::Macro | PathSource::Module => false, @@ -527,6 +529,7 @@ fn descr_expected(self) -> &'static str { _ => "value", }, PathSource::ReturnTypeNotation | PathSource::Delegation => "function", + PathSource::ExternItemImpl => "function or static", PathSource::PreciseCapturingArg(..) => "type or const parameter", PathSource::Macro => "macro", PathSource::Module => "module", @@ -618,6 +621,15 @@ pub(crate) fn is_expected(self, res: Res) -> bool { _ => false, }, PathSource::Delegation => matches!(res, Res::Def(DefKind::Fn | DefKind::AssocFn, _)), + PathSource::ExternItemImpl => { + matches!( + res, + Res::Def( + DefKind::Fn | DefKind::AssocFn | DefKind::Ctor(..) | DefKind::Static { .. }, + _ + ) + ) + } PathSource::PreciseCapturingArg(ValueNS) => { matches!(res, Res::Def(DefKind::ConstParam, _)) } @@ -640,8 +652,12 @@ fn error_code(self, has_unexpected_resolution: bool) -> ErrCode { (PathSource::Type | PathSource::DefineOpaques, false) => E0425, (PathSource::Struct(_), true) => E0574, (PathSource::Struct(_), false) => E0422, - (PathSource::Expr(..), true) | (PathSource::Delegation, true) => E0423, - (PathSource::Expr(..), false) | (PathSource::Delegation, false) => E0425, + (PathSource::Expr(..), true) + | (PathSource::Delegation, true) + | (PathSource::ExternItemImpl, true) => E0423, + (PathSource::Expr(..), false) + | (PathSource::Delegation, false) + | (PathSource::ExternItemImpl, false) => E0425, (PathSource::Pat | PathSource::TupleStruct(..), true) => E0532, (PathSource::Pat | PathSource::TupleStruct(..), false) => E0531, (PathSource::TraitItem(..) | PathSource::ReturnTypeNotation, true) => E0575, @@ -1082,21 +1098,7 @@ fn visit_fn(&mut self, fn_kind: FnKind<'ast>, _: &AttrVec, sp: Span, fn_id: Node debug!("(resolving function) entering function"); if let FnKind::Fn(_, _, f) = fn_kind { - for EiiImpl { node_id, eii_macro_path, known_eii_macro_resolution, .. } in &f.eii_impls - { - // See docs on the `known_eii_macro_resolution` field: - // if we already know the resolution statically, don't bother resolving it. - if let Some(target) = known_eii_macro_resolution { - self.smart_resolve_path( - *node_id, - &None, - &target.foreign_item, - PathSource::Expr(None), - ); - } else { - self.smart_resolve_path(*node_id, &None, &eii_macro_path, PathSource::Macro); - } - } + self.resolve_eii(&f.eii_impls); } // Create a value rib for the function. @@ -1471,7 +1473,7 @@ fn new(resolver: &'a mut Resolver<'ra, 'tcx>) -> LateResolutionVisitor<'a, 'ast, // During late resolution we only track the module component of the parent scope, // although it may be useful to track other components as well for diagnostics. let graph_root = resolver.graph_root; - let parent_scope = ParentScope::module(graph_root, resolver.arenas); + let parent_scope = ParentScope::module(graph_root.to_module(), resolver.arenas); let start_rib_kind = RibKind::Module(graph_root); LateResolutionVisitor { r: resolver, @@ -2198,7 +2200,8 @@ fn resolve_elided_lifetimes_in_path( | PathSource::Struct(_) | PathSource::TupleStruct(..) | PathSource::DefineOpaques - | PathSource::Delegation => true, + | PathSource::Delegation + | PathSource::ExternItemImpl => true, }; if inferred { // Do not create a parameter for patterns and expressions: type checking can infer @@ -2872,8 +2875,8 @@ fn resolve_item(&mut self, item: &'ast Item) { ItemKind::Mod(..) => { let module = self.r.expect_module(self.r.local_def_id(item.id).to_def_id()); let orig_module = replace(&mut self.parent_scope.module, module); - self.with_rib(ValueNS, RibKind::Module(module), |this| { - this.with_rib(TypeNS, RibKind::Module(module), |this| { + self.with_rib(ValueNS, RibKind::Module(module.expect_local()), |this| { + this.with_rib(TypeNS, RibKind::Module(module.expect_local()), |this| { if mod_inner_docs { this.resolve_doc_links(&item.attrs, MaybeExported::Ok(item.id)); } @@ -2891,7 +2894,14 @@ fn resolve_item(&mut self, item: &'ast Item) { self.parent_scope.module = orig_module; } - ItemKind::Static(box ast::StaticItem { ident, ty, expr, define_opaque, .. }) => { + ItemKind::Static(box ast::StaticItem { + ident, + ty, + expr, + define_opaque, + eii_impls, + .. + }) => { self.with_static_rib(def_kind, |this| { this.with_lifetime_rib(LifetimeRibKind::Elided(LifetimeRes::Static), |this| { this.visit_ty(ty); @@ -2903,6 +2913,7 @@ fn resolve_item(&mut self, item: &'ast Item) { } }); self.resolve_define_opaques(define_opaque); + self.resolve_eii(&eii_impls); } ItemKind::Const(box ast::ConstItem { @@ -3004,7 +3015,7 @@ fn resolve_item(&mut self, item: &'ast Item) { item.id, &None, extern_item_path, - PathSource::Expr(None), + PathSource::ExternItemImpl, ); } } @@ -3859,8 +3870,7 @@ fn resolve_delegation( let Some(body) = &delegation.body else { return }; self.with_rib(ValueNS, RibKind::FnOrCoroutine, |this| { - let span = delegation.path.segments.last().unwrap().ident.span; - let ident = Ident::new(kw::SelfLower, span.normalize_to_macro_rules()); + let ident = Ident::new(kw::SelfLower, body.span.normalize_to_macro_rules()); let res = Res::Local(delegation.id); this.innermost_rib_bindings(ValueNS).insert(ident, res); @@ -5005,7 +5015,7 @@ fn resolve_block(&mut self, block: &'ast Block) { debug!("(resolving block) found anonymous module, moving down"); self.ribs[ValueNS].push(Rib::new(RibKind::Block(Some(anonymous_module)))); self.ribs[TypeNS].push(Rib::new(RibKind::Block(Some(anonymous_module)))); - self.parent_scope.module = anonymous_module; + self.parent_scope.module = anonymous_module.to_module(); } else { self.ribs[ValueNS].push(Rib::new(RibKind::Block(None))); } @@ -5482,6 +5492,23 @@ fn resolve_define_opaques(&mut self, define_opaque: &Option; - /// A field or associated item from self type suggested in case of resolution failure. enum AssocSuggestion { Field(Span), @@ -980,12 +978,15 @@ fn try_lookup_name_relaxed( AssocSuggestion::Field(field_span) => { if self_is_available { let source_map = self.r.tcx.sess.source_map(); - // check if the field is used in a format string, such as `"{x}"` - let field_is_format_named_arg = source_map + let field_is_format_named_arg = matches!( + span.desugaring_kind(), + Some(DesugaringKind::FormatLiteral { .. }) + ) && source_map .span_to_source(span, |s, start, _| { - Ok(s.get(start - 1..start) == Some("{")) - }); - if let Ok(true) = field_is_format_named_arg { + Ok(s.get(start.saturating_sub(1)..start) == Some("{")) + }) + .unwrap_or(false); + if field_is_format_named_arg { err.help( format!("you might have meant to use the available field in a format string: `\"{{}}\", self.{}`", segment.ident.name), ); @@ -1040,14 +1041,15 @@ fn try_lookup_name_relaxed( } if let Some(Res::Def(DefKind::Struct, def_id)) = res { - let private_fields = self.has_private_fields(def_id); - let adjust_error_message = - private_fields && self.is_struct_with_fn_ctor(def_id); - if adjust_error_message { - self.update_err_for_private_tuple_struct_fields(err, &source, def_id); - } - - if private_fields { + if let Some(ctor) = self.r.struct_ctor(def_id) + && ctor.has_private_fields(self.parent_scope.module, self.r) + { + if matches!( + ctor.res, + Res::Def(DefKind::Ctor(CtorOf::Struct, CtorKind::Fn), _) + ) { + self.update_err_for_private_tuple_struct_fields(err, &source, def_id); + } err.note("constructor is not visible here due to private fields"); } } else { @@ -1131,7 +1133,7 @@ fn lookup_doc_alias_name(&mut self, path: &[Segment], ns: Namespace) -> Option<( for rib in self.ribs[ns].iter().rev() { let item = path[0].ident; if let RibKind::Module(module) | RibKind::Block(Some(module)) = rib.kind - && let Some(did) = find_doc_alias_name(self.r, module, item.name) + && let Some(did) = find_doc_alias_name(self.r, module.to_module(), item.name) { return Some((did, item)); } @@ -1892,10 +1894,7 @@ fn restrict_assoc_type_in_where_clause(&self, span: Span, err: &mut Diag<'_>) -> let ast::TyKind::Path(Some(qself), path) = &bounded_ty.kind else { return false }; // use this to verify that ident is a type param. let Some(partial_res) = self.r.partial_res_map.get(&bounded_ty.id) else { return false }; - if !matches!( - partial_res.full_res(), - Some(hir::def::Res::Def(hir::def::DefKind::AssocTy, _)) - ) { + if !matches!(partial_res.full_res(), Some(Res::Def(DefKind::AssocTy, _))) { return false; } @@ -1905,10 +1904,7 @@ fn restrict_assoc_type_in_where_clause(&self, span: Span, err: &mut Diag<'_>) -> let Some(partial_res) = self.r.partial_res_map.get(&peeled_ty.id) else { return false; }; - if !matches!( - partial_res.full_res(), - Some(hir::def::Res::Def(hir::def::DefKind::TyParam, _)) - ) { + if !matches!(partial_res.full_res(), Some(Res::Def(DefKind::TyParam, _))) { return false; } let ([ast::PathSegment { args: None, .. }], [ast::GenericBound::Trait(poly_trait_ref)]) = @@ -1928,7 +1924,7 @@ fn restrict_assoc_type_in_where_clause(&self, span: Span, err: &mut Diag<'_>) -> let Some(partial_res) = self.r.partial_res_map.get(&id) else { return false; }; - if !matches!(partial_res.full_res(), Some(hir::def::Res::Def(..))) { + if !matches!(partial_res.full_res(), Some(Res::Def(..))) { return false; } @@ -2015,19 +2011,6 @@ fn followed_by_brace(&self, span: Span) -> (bool, Option) { } } - fn is_struct_with_fn_ctor(&mut self, def_id: DefId) -> bool { - def_id - .as_local() - .and_then(|local_id| self.r.struct_constructors.get(&local_id)) - .map(|struct_ctor| { - matches!( - struct_ctor.0, - def::Res::Def(DefKind::Ctor(CtorOf::Struct, CtorKind::Fn), _) - ) - }) - .unwrap_or(false) - } - fn update_err_for_private_tuple_struct_fields( &mut self, err: &mut Diag<'_>, @@ -2201,7 +2184,17 @@ fn smart_resolve_context_dependent_help( _ => (": val", "literal", Applicability::HasPlaceholders, None), }; - if !this.has_private_fields(def_id) { + // Imprecise for local structs without ctors, we don't keep fields for them. + let has_private_fields = match def_id.as_local() { + Some(def_id) => this.r.struct_ctors.get(&def_id).is_some_and(|ctor| { + ctor.has_private_fields(this.parent_scope.module, this.r) + }), + None => this.r.tcx.associated_item_def_ids(def_id).iter().any(|field_id| { + let vis = this.r.tcx.visibility(*field_id); + !this.r.is_accessible_from(vis, this.parent_scope.module) + }), + }; + if !has_private_fields { // If the fields of the type are private, we shouldn't be suggesting using // the struct literal syntax at all, as that will cause a subsequent error. let fields = this.r.field_idents(def_id); @@ -2367,53 +2360,39 @@ fn smart_resolve_context_dependent_help( self.suggest_using_enum_variant(err, source, def_id, span); } (Res::Def(DefKind::Struct, def_id), source) if ns == ValueNS => { - let struct_ctor = match def_id.as_local() { - Some(def_id) => self.r.struct_constructors.get(&def_id).cloned(), - None => { - let ctor = self.r.cstore().ctor_untracked(self.r.tcx(), def_id); - ctor.map(|(ctor_kind, ctor_def_id)| { - let ctor_res = - Res::Def(DefKind::Ctor(CtorOf::Struct, ctor_kind), ctor_def_id); - let ctor_vis = self.r.tcx.visibility(ctor_def_id); - let field_visibilities = self - .r - .tcx - .associated_item_def_ids(def_id) - .iter() - .map(|&field_id| self.r.tcx.visibility(field_id)) - .collect(); - (ctor_res, ctor_vis, field_visibilities) - }) - } - }; - - let (ctor_def, ctor_vis, fields) = if let Some(struct_ctor) = struct_ctor { - if let PathSource::Expr(Some(parent)) = source - && let ExprKind::Field(..) | ExprKind::MethodCall(..) = parent.kind - { - bad_struct_syntax_suggestion(self, err, def_id); - return true; - } - struct_ctor - } else { + if let PathSource::Expr(Some(parent)) = source + && let ExprKind::Field(..) | ExprKind::MethodCall(..) = parent.kind + { + bad_struct_syntax_suggestion(self, err, def_id); + return true; + } + let Some(ctor) = self.r.struct_ctor(def_id) else { bad_struct_syntax_suggestion(self, err, def_id); return true; }; - let is_accessible = self.r.is_accessible_from(ctor_vis, self.parent_scope.module); - if let Some(use_span) = self.r.inaccessible_ctor_reexport.get(&span) - && is_accessible + // A type is re-exported and has an inaccessible constructor because it has fields + // that are inaccessible from the reexport's scope, extend the diagnostic. + let is_accessible = self.r.is_accessible_from(ctor.vis, self.parent_scope.module); + if is_accessible + && let mod_path = &path[..path.len() - 1] + && let PathResult::Module(ModuleOrUniformRoot::Module(import_mod)) = + self.resolve_path(mod_path, Some(TypeNS), None, PathSource::Module) + && ctor.has_private_fields(import_mod, self.r) + && let Ok(import_decl) = self.r.cm().maybe_resolve_ident_in_module( + ModuleOrUniformRoot::Module(import_mod), + path.last().unwrap().ident, + TypeNS, + &self.parent_scope, + None, + ) { err.span_note( - *use_span, + import_decl.span, "the type is accessed through this re-export, but the type's constructor \ is not visible in this import's scope due to private fields", ); - if is_accessible - && fields - .iter() - .all(|vis| self.r.is_accessible_from(*vis, self.parent_scope.module)) - { + if !ctor.has_private_fields(self.parent_scope.module, self.r) { err.span_suggestion_verbose( span, "the type can be constructed directly, because its fields are \ @@ -2430,17 +2409,17 @@ fn smart_resolve_context_dependent_help( } self.update_err_for_private_tuple_struct_fields(err, &source, def_id); } - if !is_expected(ctor_def) || is_accessible { + if !is_expected(ctor.res) || is_accessible { return true; } let field_spans = self.update_err_for_private_tuple_struct_fields(err, &source, def_id); - if let Some(spans) = - field_spans.filter(|spans| spans.len() > 0 && fields.len() == spans.len()) + if let Some(spans) = field_spans + .filter(|spans| spans.len() > 0 && ctor.field_visibilities.len() == spans.len()) { - let non_visible_spans: Vec = iter::zip(&fields, &spans) + let non_visible_spans: Vec = iter::zip(&ctor.field_visibilities, &spans) .filter(|(vis, _)| { !self.r.is_accessible_from(**vis, self.parent_scope.module) }) @@ -2715,24 +2694,6 @@ fn suggest_alternative_construction_methods( } } - fn has_private_fields(&self, def_id: DefId) -> bool { - let fields = match def_id.as_local() { - Some(def_id) => self.r.struct_constructors.get(&def_id).cloned().map(|(_, _, f)| f), - None => Some( - self.r - .tcx - .associated_item_def_ids(def_id) - .iter() - .map(|&field_id| self.r.tcx.visibility(field_id)) - .collect(), - ), - }; - - fields.is_some_and(|fields| { - fields.iter().any(|vis| !self.r.is_accessible_from(*vis, self.parent_scope.module)) - }) - } - /// Given the target `ident` and `kind`, search for the similarly named associated item /// in `self.current_trait_ref`. pub(crate) fn find_similarly_named_assoc_item( @@ -2903,10 +2864,16 @@ fn lookup_typo_candidate( } if let RibKind::Block(Some(module)) = rib.kind { - self.r.add_module_candidates(module, &mut names, &filter_fn, Some(ctxt)); + self.r.add_module_candidates( + module.to_module(), + &mut names, + &filter_fn, + Some(ctxt), + ); } else if let RibKind::Module(module) = rib.kind { // Encountered a module item, abandon ribs and look into that module and preludes. - let parent_scope = &ParentScope { module, ..self.parent_scope }; + let parent_scope = + &ParentScope { module: module.to_module(), ..self.parent_scope }; self.r.add_scope_set_candidates( &mut names, ScopeSet::All(ns), @@ -3049,7 +3016,7 @@ fn find_module(&self, def_id: DefId) -> Option<(Module<'ra>, ImportSuggestion)> let mut seen_modules = FxHashSet::default(); let root_did = self.r.graph_root.def_id(); let mut worklist = vec![( - self.r.graph_root, + self.r.graph_root.to_module(), ThinVec::new(), root_did.is_local() || !self.r.tcx.is_doc_hidden(root_did), )]; diff --git a/compiler/rustc_resolve/src/lib.rs b/compiler/rustc_resolve/src/lib.rs index d75f2981a772..af3006eda385 100644 --- a/compiler/rustc_resolve/src/lib.rs +++ b/compiler/rustc_resolve/src/lib.rs @@ -26,7 +26,7 @@ use std::ops::ControlFlow; use std::sync::Arc; -use diagnostics::{ImportSuggestion, LabelSuggestion, Suggestion}; +use diagnostics::{ImportSuggestion, LabelSuggestion, StructCtor, Suggestion}; use effective_visibilities::EffectiveVisibilitiesVisitor; use errors::{ParamKindInEnumDiscriminant, ParamKindInNonTrivialAnonConst}; use hygiene::Macros20NormalizedSyntaxContext; @@ -57,7 +57,7 @@ PerNS, }; use rustc_hir::def_id::{CRATE_DEF_ID, CrateNum, DefId, LOCAL_CRATE, LocalDefId, LocalDefIdMap}; -use rustc_hir::definitions::DisambiguatorState; +use rustc_hir::definitions::PerParentDisambiguatorState; use rustc_hir::{PrimTy, TraitCandidate, find_attr}; use rustc_index::bit_set::DenseBitSet; use rustc_metadata::creader::CStore; @@ -686,6 +686,16 @@ struct ModuleData<'ra> { #[rustc_pass_by_value] struct Module<'ra>(Interned<'ra, ModuleData<'ra>>); +/// Same as `Module`, but is guaranteed to be from the current crate. +#[derive(Clone, Copy, PartialEq, Eq, Hash)] +#[rustc_pass_by_value] +struct LocalModule<'ra>(Interned<'ra, ModuleData<'ra>>); + +/// Same as `Module`, but is guaranteed to be from an external crate. +#[derive(Clone, Copy, PartialEq, Eq, Hash)] +#[rustc_pass_by_value] +struct ExternModule<'ra>(Interned<'ra, ModuleData<'ra>>); + // Allows us to use Interned without actually enforcing (via Hash/PartialEq/...) uniqueness of the // contained data. // FIXME: We may wish to actually have at least debug-level assertions that Interned's guarantees @@ -728,6 +738,21 @@ fn new( self_decl, } } + + fn opt_def_id(&self) -> Option { + self.kind.opt_def_id() + } + + fn def_id(&self) -> DefId { + self.opt_def_id().expect("`ModuleData::def_id` is called on a block module") + } + + fn res(&self) -> Option { + match self.kind { + ModuleKind::Def(kind, def_id, _) => Some(Res::Def(kind, def_id)), + _ => None, + } + } } impl<'ra> Module<'ra> { @@ -779,21 +804,6 @@ fn ensure_traits<'tcx>(self, resolver: &impl AsRef>) { } } - fn res(self) -> Option { - match self.kind { - ModuleKind::Def(kind, def_id, _) => Some(Res::Def(kind, def_id)), - _ => None, - } - } - - fn def_id(self) -> DefId { - self.opt_def_id().expect("`ModuleData::def_id` is called on a block module") - } - - fn opt_def_id(self) -> Option { - self.kind.opt_def_id() - } - // `self` resolves to the first module ancestor that `is_normal`. fn is_normal(self) -> bool { matches!(self.kind, ModuleKind::Def(DefKind::Mod, _, _)) @@ -831,6 +841,38 @@ fn is_ancestor_of(self, mut other: Self) -> bool { } true } + + #[track_caller] + fn expect_local(self) -> LocalModule<'ra> { + match self.kind { + ModuleKind::Def(_, def_id, _) if !def_id.is_local() => { + panic!("`Module::expect_local` is called on a non-local module: {self:?}") + } + ModuleKind::Def(..) | ModuleKind::Block => LocalModule(self.0), + } + } + + #[track_caller] + fn expect_extern(self) -> ExternModule<'ra> { + match self.kind { + ModuleKind::Def(_, def_id, _) if !def_id.is_local() => ExternModule(self.0), + ModuleKind::Def(..) | ModuleKind::Block => { + panic!("`Module::expect_extern` is called on a local module: {self:?}") + } + } + } +} + +impl<'ra> LocalModule<'ra> { + fn to_module(self) -> Module<'ra> { + Module(self.0) + } +} + +impl<'ra> ExternModule<'ra> { + fn to_module(self) -> Module<'ra> { + Module(self.0) + } } impl<'ra> std::ops::Deref for Module<'ra> { @@ -841,6 +883,22 @@ fn deref(&self) -> &Self::Target { } } +impl<'ra> std::ops::Deref for LocalModule<'ra> { + type Target = ModuleData<'ra>; + + fn deref(&self) -> &Self::Target { + &self.0 + } +} + +impl<'ra> std::ops::Deref for ExternModule<'ra> { + type Target = ModuleData<'ra>; + + fn deref(&self) -> &Self::Target { + &self.0 + } +} + impl<'ra> fmt::Debug for Module<'ra> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self.kind { @@ -850,6 +908,12 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } } +impl<'ra> fmt::Debug for LocalModule<'ra> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.to_module().fmt(f) + } +} + /// Data associated with any name declaration. #[derive(Clone, Debug)] struct DeclData<'ra> { @@ -1101,9 +1165,11 @@ fn may_appear_after(&self, invoc_parent_expansion: LocalExpnId, decl: Decl<'_>) !(certainly_before_other_or_simultaneously || certainly_before_invoc_or_simultaneously) } - // Its purpose is to postpone the determination of a single binding because - // we can't predict whether it will be overwritten by recently expanded macros. - // FIXME: How can we integrate it with the `update_resolution`? + /// Returns whether this declaration may be shadowed or overwritten by something else later. + /// FIXME: this function considers `unexpanded_invocations`, but not `single_imports`, so + /// the declaration may not be as "determined" as we think. + /// FIXME: relationship between this function and similar `NameResolution::determined_decl` + /// is unclear. fn determined(&self) -> bool { match &self.kind { DeclKind::Import { source_decl, import, .. } if import.is_glob() => { @@ -1195,7 +1261,7 @@ pub struct Resolver<'ra, 'tcx> { /// Item with a given `LocalDefId` was defined during macro expansion with ID `ExpnId`. expn_that_defined: UnordMap = Default::default(), - graph_root: Module<'ra>, + graph_root: LocalModule<'ra>, /// Assert that we are in speculative resolution mode. assert_speculative: bool, @@ -1254,17 +1320,17 @@ pub struct Resolver<'ra, 'tcx> { /// /// There will be an anonymous module created around `g` with the ID of the /// entry block for `f`. - block_map: NodeMap> = Default::default(), + block_map: NodeMap> = Default::default(), /// A fake module that contains no definition and no prelude. Used so that /// some AST passes can generate identifiers that only resolve to local or /// lang items. - empty_module: Module<'ra>, + empty_module: LocalModule<'ra>, /// All local modules, including blocks. - local_modules: Vec>, + local_modules: Vec>, /// Eagerly populated map of all local non-block modules. - local_module_map: FxIndexMap>, + local_module_map: FxIndexMap>, /// Lazily populated cache of modules loaded from external crates. - extern_module_map: CacheRefCell>>, + extern_module_map: CacheRefCell>>, /// Maps glob imports to the names of items actually imported. glob_map: FxIndexMap>, @@ -1283,11 +1349,6 @@ pub struct Resolver<'ra, 'tcx> { /// Crate-local macro expanded `macro_export` referred to by a module-relative path. macro_expanded_macro_export_errors: BTreeSet<(Span, Span)> = BTreeSet::new(), - /// When a type is re-exported that has an inaccessible constructor because it has fields that - /// are inaccessible from the import's scope, we mark that as the type won't be able to be built - /// through the re-export. We use this information to extend the existing diagnostic. - inaccessible_ctor_reexport: FxHashMap = default::fx_hash_map(), - arenas: &'ra ResolverArenas<'ra>, dummy_decl: Decl<'ra>, builtin_type_decls: FxHashMap>, @@ -1304,8 +1365,8 @@ pub struct Resolver<'ra, 'tcx> { dummy_ext_bang: Arc, dummy_ext_derive: Arc, non_macro_attr: &'ra MacroData, - local_macro_def_scopes: FxHashMap> = default::fx_hash_map(), - ast_transform_scopes: FxHashMap> = default::fx_hash_map(), + local_macro_def_scopes: FxHashMap> = default::fx_hash_map(), + ast_transform_scopes: FxHashMap> = default::fx_hash_map(), unused_macros: FxIndexMap, /// A map from the macro to all its potentially unused arms. unused_macro_rules: FxIndexMap>, @@ -1344,7 +1405,7 @@ pub struct Resolver<'ra, 'tcx> { /// Table for mapping struct IDs into struct constructor IDs, /// it's not used during normal resolution, only for better error reporting. /// Also includes of list of each fields visibility - struct_constructors: LocalDefIdMap<(Res, Visibility, Vec>)> = Default::default(), + struct_ctors: LocalDefIdMap = Default::default(), /// for all the struct /// it's not used during normal resolution, only for better error reporting. @@ -1356,7 +1417,7 @@ pub struct Resolver<'ra, 'tcx> { node_id_to_def_id: NodeMap>, - disambiguator: DisambiguatorState = DisambiguatorState::new(), + per_parent_disambiguators: LocalDefIdMap, /// Indices of unnamed struct or variant fields with unresolved attributes. placeholder_field_indices: FxHashMap = default::fx_hash_map(), @@ -1560,7 +1621,13 @@ fn create_def( ); // FIXME: remove `def_span` body, pass in the right spans here and call `tcx.at().create_def()` - let feed = self.tcx.create_def(parent, name, def_kind, None, &mut self.disambiguator); + let feed = self.tcx.create_def( + parent, + name, + def_kind, + None, + self.per_parent_disambiguators.entry(parent).or_default(), + ); let def_id = feed.def_id(); // Create the definition. @@ -1653,6 +1720,7 @@ pub fn new( crate_span, attr::contains_name(attrs, sym::no_implicit_prelude), ); + let graph_root = graph_root.expect_local(); let local_modules = vec![graph_root]; let local_module_map = FxIndexMap::from_iter([(CRATE_DEF_ID, graph_root)]); let empty_module = arenas.new_module( @@ -1663,6 +1731,7 @@ pub fn new( DUMMY_SP, true, ); + let empty_module = empty_module.expect_local(); let mut node_id_to_def_id = NodeMap::default(); let crate_feed = tcx.create_local_crate_def_id(crate_span); @@ -1742,10 +1811,11 @@ pub fn new( doc_link_resolutions: Default::default(), doc_link_traits_in_scope: Default::default(), current_crate_outer_attr_insert_span, + per_parent_disambiguators: Default::default(), .. }; - let root_parent_scope = ParentScope::module(graph_root, resolver.arenas); + let root_parent_scope = ParentScope::module(graph_root.to_module(), resolver.arenas); resolver.invocation_parent_scopes.insert(LocalExpnId::ROOT, root_parent_scope); resolver.feed_visibility(crate_feed, Visibility::Public); @@ -1754,15 +1824,19 @@ pub fn new( fn new_local_module( &mut self, - parent: Option>, + parent: Option>, kind: ModuleKind, expn_id: ExpnId, span: Span, no_implicit_prelude: bool, - ) -> Module<'ra> { + ) -> LocalModule<'ra> { + let parent = parent.map(|m| m.to_module()); let vis = kind.opt_def_id().map_or(Visibility::Public, |def_id| self.tcx.visibility(def_id)); - let module = self.arenas.new_module(parent, kind, vis, expn_id, span, no_implicit_prelude); + let module = self + .arenas + .new_module(parent, kind, vis, expn_id, span, no_implicit_prelude) + .expect_local(); self.local_modules.push(module); if let Some(def_id) = module.opt_def_id() { self.local_module_map.insert(def_id.expect_local(), module); @@ -1772,15 +1846,19 @@ fn new_local_module( fn new_extern_module( &self, - parent: Option>, + parent: Option>, kind: ModuleKind, expn_id: ExpnId, span: Span, no_implicit_prelude: bool, - ) -> Module<'ra> { + ) -> ExternModule<'ra> { + let parent = parent.map(|m| m.to_module()); let vis = kind.opt_def_id().map_or(Visibility::Public, |def_id| self.tcx.visibility(def_id)); - let module = self.arenas.new_module(parent, kind, vis, expn_id, span, no_implicit_prelude); + let module = self + .arenas + .new_module(parent, kind, vis, expn_id, span, no_implicit_prelude) + .expect_extern(); self.extern_module_map.borrow_mut().insert(module.def_id(), module); module } @@ -1873,6 +1951,11 @@ pub fn into_outputs(self) -> ResolverOutputs<'tcx> { lifetime_elision_allowed: self.lifetime_elision_allowed, lint_buffer: Steal::new(self.lint_buffer), delegation_infos: self.delegation_infos, + per_parent_disambiguators: self + .per_parent_disambiguators + .into_items() + .map(|(k, d)| (k, Steal::new(d))) + .collect(), }; ResolverOutputs { global_ctxt, ast_lowering } } @@ -2066,7 +2149,7 @@ fn find_transitive_imports( fn resolutions(&self, module: Module<'ra>) -> &'ra Resolutions<'ra> { if module.populate_on_access.get() { module.populate_on_access.set(false); - self.build_reduced_graph_external(module); + self.build_reduced_graph_external(module.expect_extern()); } &module.0.0.lazy_resolutions } @@ -2139,7 +2222,7 @@ fn record_use_inner( // Do not report the lint if the macro name resolves in stdlib prelude // even without the problematic `macro_use` import. let found_in_stdlib_prelude = self.prelude.is_some_and(|prelude| { - let empty_module = self.empty_module; + let empty_module = self.empty_module.to_module(); let arenas = self.arenas; self.cm() .maybe_resolve_ident_in_module( @@ -2251,7 +2334,7 @@ fn resolve_crate_root(&self, ident: Ident) -> Module<'ra> { "resolve_crate_root({:?}): found no mark (ident.span = {:?})", ident, ident.span ); - return self.graph_root; + return self.graph_root.to_module(); } }; let module = self.expect_module( @@ -2506,7 +2589,7 @@ fn resolve_main(&mut self) { return; } - let module = self.graph_root; + let module = self.graph_root.to_module(); let ident = Ident::with_dummy_span(sym::main); let parent_scope = &ParentScope::module(module, self.arenas); diff --git a/compiler/rustc_resolve/src/macros.rs b/compiler/rustc_resolve/src/macros.rs index 619e61211984..a5024f5ef694 100644 --- a/compiler/rustc_resolve/src/macros.rs +++ b/compiler/rustc_resolve/src/macros.rs @@ -4,7 +4,7 @@ use std::mem; use std::sync::Arc; -use rustc_ast::{self as ast, Crate, DUMMY_NODE_ID, NodeId}; +use rustc_ast::{self as ast, Crate, DelegationSuffixes, NodeId}; use rustc_ast_pretty::pprust; use rustc_attr_parsing::AttributeParser; use rustc_errors::{Applicability, DiagCtxtHandle, StashKey}; @@ -16,9 +16,8 @@ use rustc_expand::expand::{ AstFragment, AstFragmentKind, Invocation, InvocationKind, SupportsMacroExpansion, }; -use rustc_feature::Features; use rustc_hir::attrs::{AttributeKind, CfgEntry, StrippedCfgItem}; -use rustc_hir::def::{self, DefKind, MacroKinds, Namespace, NonMacroAttrKind}; +use rustc_hir::def::{DefKind, MacroKinds, Namespace, NonMacroAttrKind}; use rustc_hir::def_id::{CrateNum, DefId, LocalDefId}; use rustc_hir::{Attribute, StabilityLevel}; use rustc_middle::middle::stability; @@ -43,12 +42,10 @@ use crate::imports::Import; use crate::{ BindingKey, CacheCell, CmResolver, Decl, DeclKind, DeriveData, Determinacy, Finalize, IdentKey, - InvocationParent, MacroData, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, + InvocationParent, MacroData, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, Res, ResolutionError, Resolver, ScopeSet, Segment, Used, }; -type Res = def::Res; - /// Name declaration produced by a `macro_rules` item definition. /// Not modularized, can shadow previous `macro_rules` definitions, etc. #[derive(Debug)] @@ -125,26 +122,18 @@ fn fast_print_path(path: &ast::Path) -> Symbol { pub(crate) fn registered_tools(tcx: TyCtxt<'_>, (): ()) -> RegisteredTools { let (_, pre_configured_attrs) = &*tcx.crate_for_resolver(()).borrow(); - registered_tools_ast(tcx.dcx(), pre_configured_attrs, tcx.sess, tcx.features()) + registered_tools_ast(tcx.dcx(), pre_configured_attrs, tcx.sess) } pub fn registered_tools_ast( dcx: DiagCtxtHandle<'_>, pre_configured_attrs: &[ast::Attribute], sess: &Session, - features: &Features, ) -> RegisteredTools { let mut registered_tools = RegisteredTools::default(); if let Some(Attribute::Parsed(AttributeKind::RegisterTool(tools, _))) = - AttributeParser::parse_limited( - sess, - pre_configured_attrs, - sym::register_tool, - DUMMY_SP, - DUMMY_NODE_ID, - Some(features), - ) + AttributeParser::parse_limited(sess, pre_configured_attrs, &[sym::register_tool]) { for tool in tools { if let Some(old_tool) = registered_tools.replace(tool) { @@ -242,8 +231,8 @@ fn expansion_for_ast_pass( ) }); - let parent_scope = - parent_module.map_or(self.empty_module, |def_id| self.expect_module(def_id)); + let parent_scope = parent_module + .map_or(self.empty_module, |def_id| self.expect_module(def_id).expect_local()); self.ast_transform_scopes.insert(expn_id, parent_scope); expn_id @@ -286,7 +275,8 @@ fn resolve_macro_invocation( InvocationKind::Derive { ref path, .. } => (path, MacroKind::Derive), InvocationKind::GlobDelegation { ref item, .. } => { let ast::AssocItemKind::DelegationMac(deleg) = &item.kind else { unreachable!() }; - deleg_impl = Some(self.invocation_parent(invoc_id)); + let DelegationSuffixes::Glob(star_span) = deleg.suffixes else { unreachable!() }; + deleg_impl = Some((self.invocation_parent(invoc_id), star_span)); // It is sufficient to consider glob delegation a bang macro for now. (&deleg.prefix, MacroKind::Bang) } @@ -530,6 +520,7 @@ fn glob_delegation_suffixes( &self, trait_def_id: DefId, impl_def_id: LocalDefId, + star_span: Span, ) -> Result)>, Indeterminate> { let target_trait = self.expect_module(trait_def_id); if !target_trait.unexpanded_invocations.borrow().is_empty() { @@ -549,13 +540,13 @@ fn glob_delegation_suffixes( let mut idents = Vec::new(); target_trait.for_each_child(self, |this, ident, orig_ident_span, ns, _binding| { - // FIXME: Adjust hygiene for idents from globs, like for glob imports. if let Some(overriding_keys) = this.impl_binding_keys.get(&impl_def_id) && overriding_keys.contains(&BindingKey::new(ident, ns)) { // The name is overridden, do not produce it from the glob delegation. } else { - idents.push((ident.orig(orig_ident_span), None)); + // FIXME: Adjust hygiene for idents from globs, like for glob imports. + idents.push((ident.orig(star_span.with_ctxt(orig_ident_span.ctxt())), None)); } }); Ok(idents) @@ -579,7 +570,7 @@ fn smart_resolve_macro_path( parent_scope: &ParentScope<'ra>, node_id: NodeId, force: bool, - deleg_impl: Option, + deleg_impl: Option<(LocalDefId, Span)>, invoc_in_mod_inert_attr: Option, suggestion_span: Option, ) -> Result<(Arc, Res), Indeterminate> { @@ -712,24 +703,55 @@ fn smart_resolve_macro_path( feature_err(&self.tcx.sess, sym::custom_inner_attributes, path.span, msg).emit(); } - const DIAG_ATTRS: &[Symbol] = - &[sym::on_unimplemented, sym::do_not_recommend, sym::on_const, sym::on_move]; + const DIAGNOSTIC_ATTRIBUTES: &[(Symbol, Option)] = &[ + (sym::on_unimplemented, None), + (sym::do_not_recommend, None), + (sym::on_move, Some(sym::diagnostic_on_move)), + (sym::on_const, Some(sym::diagnostic_on_const)), + (sym::on_unknown, Some(sym::diagnostic_on_unknown)), + ]; if res == Res::NonMacroAttr(NonMacroAttrKind::Tool) && let [namespace, attribute, ..] = &*path.segments && namespace.ident.name == sym::diagnostic - && !DIAG_ATTRS.contains(&attribute.ident.name) + && !DIAGNOSTIC_ATTRIBUTES.iter().any(|(attr, feature)| { + attribute.ident.name == *attr + && feature.is_none_or(|f| self.tcx.features().enabled(f)) + }) { + let name = attribute.ident.name; let span = attribute.span(); - let typo = find_best_match_for_name(DIAG_ATTRS, attribute.ident.name, Some(5)) - .map(|typo_name| errors::UnknownDiagnosticAttributeTypoSugg { span, typo_name }); + let help = 'help: { + if self.tcx.sess.is_nightly_build() { + for (attr, feature) in DIAGNOSTIC_ATTRIBUTES { + if let Some(feature) = *feature + && *attr == name + { + break 'help Some(errors::UnknownDiagnosticAttributeHelp::UseFeature { + feature, + }); + } + } + } + + let candidates = DIAGNOSTIC_ATTRIBUTES + .iter() + .filter_map(|(attr, feature)| { + feature.is_none_or(|f| self.tcx.features().enabled(f)).then_some(*attr) + }) + .collect::>(); + + find_best_match_for_name(&candidates, name, None).map(|typo_name| { + errors::UnknownDiagnosticAttributeHelp::Typo { span, typo_name } + }) + }; self.tcx.sess.psess.buffer_lint( UNKNOWN_DIAGNOSTIC_ATTRIBUTES, span, node_id, - errors::UnknownDiagnosticAttribute { typo }, + errors::UnknownDiagnosticAttribute { help }, ); } @@ -761,7 +783,7 @@ fn resolve_macro_or_delegation_path<'r>( kind: MacroKind, parent_scope: &ParentScope<'ra>, force: bool, - deleg_impl: Option, + deleg_impl: Option<(LocalDefId, Span)>, invoc_in_mod_inert_attr: Option<(LocalDefId, NodeId)>, ignore_import: Option>, suggestion_span: Option, @@ -846,10 +868,15 @@ fn resolve_macro_or_delegation_path<'r>( let res = res?; let ext = match deleg_impl { - Some(impl_def_id) => match res { - def::Res::Def(DefKind::Trait, def_id) => { + Some((impl_def_id, star_span)) => match res { + Res::Def(DefKind::Trait, def_id) => { let edition = self.tcx.sess.edition(); - Some(Arc::new(SyntaxExtension::glob_delegation(def_id, impl_def_id, edition))) + Some(Arc::new(SyntaxExtension::glob_delegation( + def_id, + impl_def_id, + star_span, + edition, + ))) } _ => None, }, diff --git a/compiler/rustc_sanitizers/src/cfi/typeid/itanium_cxx_abi/encode.rs b/compiler/rustc_sanitizers/src/cfi/typeid/itanium_cxx_abi/encode.rs index 26979c24bdb6..1f9590947392 100644 --- a/compiler/rustc_sanitizers/src/cfi/typeid/itanium_cxx_abi/encode.rs +++ b/compiler/rustc_sanitizers/src/cfi/typeid/itanium_cxx_abi/encode.rs @@ -183,7 +183,7 @@ fn encode_fnsig<'tcx>( let mut encode_ty_options = EncodeTyOptions::from_bits(options.bits()) .unwrap_or_else(|| bug!("encode_fnsig: invalid option(s) `{:?}`", options.bits())); - match fn_sig.abi { + match fn_sig.abi() { ExternAbi::C { .. } => { encode_ty_options.insert(EncodeTyOptions::GENERALIZE_REPR_C); } @@ -207,10 +207,10 @@ fn encode_fnsig<'tcx>( s.push_str(&encode_ty(tcx, ty, dict, encode_ty_options)); } - if fn_sig.c_variadic { + if fn_sig.c_variadic() { s.push('z'); } - } else if fn_sig.c_variadic { + } else if fn_sig.c_variadic() { s.push('z'); } else { // Empty parameter lists, whether declared as () or conventionally as (void), are @@ -680,7 +680,6 @@ fn encode_ty_name(tcx: TyCtxt<'_>, def_id: DefId) -> String { hir::definitions::DefPathData::Closure => "C", hir::definitions::DefPathData::Ctor => "c", hir::definitions::DefPathData::AnonConst => "K", - hir::definitions::DefPathData::LateAnonConst => "k", hir::definitions::DefPathData::OpaqueTy => "i", hir::definitions::DefPathData::SyntheticCoroutineBody => "s", hir::definitions::DefPathData::NestedStatic => "n", @@ -690,7 +689,6 @@ fn encode_ty_name(tcx: TyCtxt<'_>, def_id: DefId) -> String { | hir::definitions::DefPathData::MacroNs(..) | hir::definitions::DefPathData::OpaqueLifetime(..) | hir::definitions::DefPathData::LifetimeNs(..) - | hir::definitions::DefPathData::DesugaredAnonymousLifetime | hir::definitions::DefPathData::AnonAssocTy(..) => { bug!("encode_ty_name: unexpected `{:?}`", disambiguated_data.data); } diff --git a/compiler/rustc_serialize/Cargo.toml b/compiler/rustc_serialize/Cargo.toml index 948242352e7a..193c89a29598 100644 --- a/compiler/rustc_serialize/Cargo.toml +++ b/compiler/rustc_serialize/Cargo.toml @@ -8,7 +8,7 @@ edition = "2024" indexmap = "2.0.0" rustc_hashes = { path = "../rustc_hashes" } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2.12" +thin-vec = "0.2.15" # tidy-alphabetical-end [dev-dependencies] diff --git a/compiler/rustc_session/src/config.rs b/compiler/rustc_session/src/config.rs index e4ef1d40d72d..c255d546e393 100644 --- a/compiler/rustc_session/src/config.rs +++ b/compiler/rustc_session/src/config.rs @@ -1320,7 +1320,8 @@ pub fn split_dwarf_path( } } -pub(crate) fn parse_remap_path_scope( +// pub for rustdoc +pub fn parse_remap_path_scope( early_dcx: &EarlyDiagCtxt, matches: &getopts::Matches, unstable_opts: &UnstableOptions, @@ -1449,6 +1450,7 @@ fn default() -> Options { logical_env: FxIndexMap::default(), verbose: false, target_modifiers: BTreeMap::default(), + mitigation_coverage_map: Default::default(), } } } @@ -1615,6 +1617,19 @@ pub fn build_target_config( let mut err = early_dcx.early_struct_fatal(format!("error loading target specification: {e}")); err.help("run `rustc --print target-list` for a list of built-in targets"); + let typed = target.tuple(); + let limit = typed.len() / 3 + 1; + if let Some(suggestion) = rustc_target::spec::TARGETS + .iter() + .filter_map(|&t| { + rustc_span::edit_distance::edit_distance_with_substrings(typed, t, limit) + .map(|d| (d, t)) + }) + .min_by_key(|(d, _)| *d) + .map(|(_, t)| t) + { + err.help(format!("did you mean `{suggestion}`?")); + } err.emit() } } @@ -2456,9 +2471,9 @@ pub fn build_session_options(early_dcx: &mut EarlyDiagCtxt, matches: &getopts::M let crate_types = parse_crate_types_from_list(unparsed_crate_types) .unwrap_or_else(|e| early_dcx.early_fatal(e)); - let mut target_modifiers = BTreeMap::::new(); + let mut collected_options = Default::default(); - let mut unstable_opts = UnstableOptions::build(early_dcx, matches, &mut target_modifiers); + let mut unstable_opts = UnstableOptions::build(early_dcx, matches, &mut collected_options); let (lint_opts, describe_lints, lint_cap) = get_cmd_lint_options(early_dcx, matches); if !unstable_opts.unstable_options && json_timings { @@ -2474,7 +2489,7 @@ pub fn build_session_options(early_dcx: &mut EarlyDiagCtxt, matches: &getopts::M let output_types = parse_output_types(early_dcx, &unstable_opts, matches); - let mut cg = CodegenOptions::build(early_dcx, matches, &mut target_modifiers); + let mut cg = CodegenOptions::build(early_dcx, matches, &mut collected_options); let (disable_local_thinlto, codegen_units) = should_override_cgus_and_disable_thinlto( early_dcx, &output_types, @@ -2625,7 +2640,7 @@ pub fn build_session_options(early_dcx: &mut EarlyDiagCtxt, matches: &getopts::M // -Zretpoline-external-thunk also requires -Zretpoline if unstable_opts.retpoline_external_thunk { unstable_opts.retpoline = true; - target_modifiers.insert( + collected_options.target_modifiers.insert( OptionsTargetModifiers::UnstableOptions(UnstableOptionsTargetModifiers::retpoline), "true".to_string(), ); @@ -2785,7 +2800,8 @@ pub fn build_session_options(early_dcx: &mut EarlyDiagCtxt, matches: &getopts::M color, logical_env, verbose, - target_modifiers, + target_modifiers: collected_options.target_modifiers, + mitigation_coverage_map: collected_options.mitigations, } } diff --git a/compiler/rustc_session/src/config/cfg.rs b/compiler/rustc_session/src/config/cfg.rs index 1d5287cfd80a..9c76f4f3db92 100644 --- a/compiler/rustc_session/src/config/cfg.rs +++ b/compiler/rustc_session/src/config/cfg.rs @@ -144,6 +144,7 @@ pub(crate) fn disallow_cfgs(sess: &Session, user_cfgs: &Cfg) { | (sym::target_endian, Some(_)) | (sym::target_env, None | Some(_)) | (sym::target_family, Some(_)) + | (sym::target_object_format, Some(_)) | (sym::target_os, Some(_)) | (sym::target_pointer_width, Some(_)) | (sym::target_vendor, None | Some(_)) @@ -252,8 +253,9 @@ macro_rules! ins_sym { ins_sym!(sym::target_abi, sess.target.cfg_abi.desc_symbol()); ins_sym!(sym::target_arch, sess.target.arch.desc_symbol()); - ins_str!(sym::target_endian, sess.target.endian.as_str()); + ins_sym!(sym::target_endian, sess.target.endian.desc_symbol()); ins_sym!(sym::target_env, sess.target.env.desc_symbol()); + ins_sym!(sym::target_object_format, sess.target.options.binary_format.desc_symbol()); for family in sess.target.families.as_ref() { ins_str!(sym::target_family, family); @@ -420,12 +422,13 @@ macro_rules! ins { // sym::target_* { - const VALUES: [&Symbol; 8] = [ + const VALUES: [&Symbol; 9] = [ &sym::target_abi, &sym::target_arch, &sym::target_endian, &sym::target_env, &sym::target_family, + &sym::target_object_format, &sym::target_os, &sym::target_pointer_width, &sym::target_vendor, @@ -449,6 +452,7 @@ macro_rules! ins { Some(values_target_endian), Some(values_target_env), Some(values_target_family), + Some(values_target_object_format), Some(values_target_os), Some(values_target_pointer_width), Some(values_target_vendor), @@ -460,11 +464,12 @@ macro_rules! ins { for target in Target::builtins().chain(iter::once(current_target.clone())) { values_target_abi.insert(target.options.cfg_abi.desc_symbol()); values_target_arch.insert(target.arch.desc_symbol()); - values_target_endian.insert(Symbol::intern(target.options.endian.as_str())); + values_target_endian.insert(target.options.endian.desc_symbol()); values_target_env.insert(target.options.env.desc_symbol()); values_target_family.extend( target.options.families.iter().map(|family| Symbol::intern(family)), ); + values_target_object_format.insert(target.options.binary_format.desc_symbol()); values_target_os.insert(target.options.os.desc_symbol()); values_target_pointer_width.insert(sym::integer(target.pointer_width)); values_target_vendor.insert(target.vendor_symbol()); diff --git a/compiler/rustc_session/src/errors.rs b/compiler/rustc_session/src/errors.rs index 295d9c361777..54f88aa22bdc 100644 --- a/compiler/rustc_session/src/errors.rs +++ b/compiler/rustc_session/src/errors.rs @@ -71,7 +71,7 @@ pub(crate) struct FeatureDiagnosticHelp { applicability = "maybe-incorrect", code = "#![feature({feature})]\n" )] -pub struct FeatureDiagnosticSuggestion { +pub(crate) struct FeatureDiagnosticSuggestion { pub feature: Symbol, #[primary_span] pub span: Span, @@ -83,13 +83,6 @@ pub(crate) struct CliFeatureDiagnosticHelp { pub(crate) feature: Symbol, } -#[derive(Diagnostic)] -#[diag("must be a name of an associated function")] -pub struct MustBeNameOfAssociatedFunction { - #[primary_span] - pub span: Span, -} - #[derive(Diagnostic)] #[diag( "`-Zunleash-the-miri-inside-of-you` may not be used to circumvent feature gates, except when testing error paths in the CTFE engine" diff --git a/compiler/rustc_session/src/options.rs b/compiler/rustc_session/src/options.rs index 027a7045791e..9580642ba72b 100644 --- a/compiler/rustc_session/src/options.rs +++ b/compiler/rustc_session/src/options.rs @@ -51,14 +51,14 @@ macro_rules! hash_substruct { ($opt_name:ident, $opt_expr:expr, $error_format:expr, $for_crate_hash:expr, $hasher:expr, [UNTRACKED]) => {{}}; ($opt_name:ident, $opt_expr:expr, $error_format:expr, $for_crate_hash:expr, $hasher:expr, [TRACKED]) => {{}}; ($opt_name:ident, $opt_expr:expr, $error_format:expr, $for_crate_hash:expr, $hasher:expr, [TRACKED_NO_CRATE_HASH]) => {{}}; - ($opt_name:ident, $opt_expr:expr, $error_format:expr, $for_crate_hash:expr, $hasher:expr, [SUBSTRUCT]) => { + ($opt_name:ident, $opt_expr:expr, $error_format:expr, $for_crate_hash:expr, $hasher:expr, [SUBSTRUCT]) => {{ use crate::config::dep_tracking::DepTrackingHash; $opt_expr.dep_tracking_hash($for_crate_hash, $error_format).hash( $hasher, $error_format, $for_crate_hash, ); - }; + }}; } /// Extended target modifier info. @@ -84,6 +84,8 @@ pub struct TargetModifier { pub value_name: String, } +pub mod mitigation_coverage; + mod target_modifier_consistency_check { use super::*; pub(super) fn sanitizer(l: &TargetModifier, r: Option<&TargetModifier>) -> bool { @@ -198,15 +200,15 @@ macro_rules! gather_tmods { tmod_push!($struct_name, $tmod_enum_name, $opt_name, $opt_expr, $init, $mods, $tmod_vals) }; ($struct_name:ident, $tmod_enum_name:ident, $opt_name:ident, $opt_expr:expr, $init:expr, $mods:expr, $tmod_vals:expr, - [SUBSTRUCT], []) => { + [SUBSTRUCT], [$(MITIGATION)?]) => { $opt_expr.gather_target_modifiers($mods, $tmod_vals); }; ($struct_name:ident, $tmod_enum_name:ident, $opt_name:ident, $opt_expr:expr, $init:expr, $mods:expr, $tmod_vals:expr, - [UNTRACKED], []) => {{}}; + [UNTRACKED], [$(MITIGATION)?]) => {{}}; ($struct_name:ident, $tmod_enum_name:ident, $opt_name:ident, $opt_expr:expr, $init:expr, $mods:expr, $tmod_vals:expr, - [TRACKED], []) => {{}}; + [TRACKED], [$(MITIGATION)?]) => {{}}; ($struct_name:ident, $tmod_enum_name:ident, $opt_name:ident, $opt_expr:expr, $init:expr, $mods:expr, $tmod_vals:expr, - [TRACKED_NO_CRATE_HASH], []) => {{}}; + [TRACKED_NO_CRATE_HASH], [$(MITIGATION)?]) => {{}}; } macro_rules! gather_tmods_top_level { @@ -216,7 +218,7 @@ macro_rules! gather_tmods_top_level { ($opt_name:ident, $opt_expr:expr, $mods:expr, $tmod_vals:expr, [$non_substruct:ident TARGET_MODIFIER]) => { compile_error!("Top level option can't be target modifier"); }; - ($opt_name:ident, $opt_expr:expr, $mods:expr, $tmod_vals:expr, [$non_substruct:ident]) => {}; + ($opt_name:ident, $opt_expr:expr, $mods:expr, $tmod_vals:expr, [$non_substruct:ident $(MITIGATION)?]) => {}; } /// Macro for generating OptionsTargetsModifiers top-level enum with impl. @@ -307,60 +309,85 @@ pub fn is_target_modifier(flag_name: &str) -> bool { } macro_rules! top_level_options { - ( $( #[$top_level_attr:meta] )* pub struct Options { $( - $( #[$attr:meta] )* - $opt:ident : $t:ty [$dep_tracking_marker:ident $( $tmod:ident $variant:ident )?], - )* } ) => ( - top_level_tmod_enum!( {$([$dep_tracking_marker $($tmod $variant),*])|*} ); - - #[derive(Clone)] - $( #[$top_level_attr] )* + ( + $(#[$top_level_attr:meta])* pub struct Options { $( - $( #[$attr] )* - pub $opt: $t - ),*, + $(#[$attr:meta])* + $opt:ident : $t:ty [ + $dep_tracking_marker:ident + $( $tmod:ident $variant:ident )? + ], + )* + } + ) => { + top_level_tmod_enum!( + { + $( + [$dep_tracking_marker $($tmod $variant),*] + )|* + } + ); + + #[derive(Clone)] + $(#[$top_level_attr])* + pub struct Options { + $( + $(#[$attr])* + pub $opt: $t, + )* pub target_modifiers: BTreeMap, + pub mitigation_coverage_map: mitigation_coverage::MitigationCoverageMap, } impl Options { pub fn dep_tracking_hash(&self, for_crate_hash: bool) -> Hash64 { let mut sub_hashes = BTreeMap::new(); - $({ - hash_opt!($opt, - &self.$opt, - &mut sub_hashes, - for_crate_hash, - [$dep_tracking_marker]); - })* + $( + hash_opt!( + $opt, + &self.$opt, + &mut sub_hashes, + for_crate_hash, + [$dep_tracking_marker] + ); + )* let mut hasher = StableHasher::new(); - dep_tracking::stable_hash(sub_hashes, - &mut hasher, - self.error_format, - for_crate_hash); - $({ - hash_substruct!($opt, + dep_tracking::stable_hash( + sub_hashes, + &mut hasher, + self.error_format, + for_crate_hash, + ); + $( + hash_substruct!( + $opt, &self.$opt, self.error_format, for_crate_hash, &mut hasher, - [$dep_tracking_marker]); - })* + [$dep_tracking_marker] + ); + )* hasher.finish() } pub fn gather_target_modifiers(&self) -> Vec { let mut mods = Vec::::new(); - $({ - gather_tmods_top_level!($opt, - &self.$opt, &mut mods, &self.target_modifiers, - [$dep_tracking_marker $($tmod),*]); - })* + $( + gather_tmods_top_level!( + $opt, + &self.$opt, + &mut mods, + &self.target_modifiers, + [$dep_tracking_marker $($tmod),*] + ); + )* mods.sort_by(|a, b| a.opt.cmp(&b.opt)); mods } } - ); + } } top_level_options!( @@ -503,11 +530,20 @@ pub struct Options { } ); +macro_rules! mitigation_enum_opt { + ($opt:ident, MITIGATION) => { + Some(mitigation_coverage::DeniedPartialMitigationKind::$opt) + }; + ($opt:ident, $(TARGET_MODIFIER)?) => { + None + }; +} + macro_rules! tmod_enum_opt { - ($struct_name:ident, $tmod_enum_name:ident, $opt:ident, $v:ident) => { + ($struct_name:ident, $tmod_enum_name:ident, $opt:ident, TARGET_MODIFIER) => { Some(OptionsTargetModifiers::$struct_name($tmod_enum_name::$opt)) }; - ($struct_name:ident, $tmod_enum_name:ident, $opt:ident, ) => { + ($struct_name:ident, $tmod_enum_name:ident, $opt:ident, $(MITIGATION)?) => { None }; } @@ -579,7 +615,7 @@ pub fn is_target_modifier(flag_name: &str) -> bool { ( $tmod_enum_name:ident, $prefix:expr, @parse {$($eout:tt)*}, ($puser_value:ident){$($pout:tt)*}; - $opt:ident, $parse:ident, $t:ty, [] | + $opt:ident, $parse:ident, $t:ty, [$(MITIGATION)?] | $($tail:tt)* ) => { tmod_enum! { @@ -596,6 +632,47 @@ pub fn is_target_modifier(flag_name: &str) -> bool { }; } +#[derive(Default)] +pub struct CollectedOptions { + pub target_modifiers: BTreeMap, + pub mitigations: mitigation_coverage::MitigationCoverageMap, +} + +macro_rules! setter_for { + // the allow/deny-mitigations options use collected/index instead of the cg, since they + // work across option groups + (allow_partial_mitigations, $struct_name:ident, $parse:ident) => { + pub(super) fn allow_partial_mitigations( + _cg: &mut super::$struct_name, + collected: &mut super::CollectedOptions, + v: Option<&str>, + index: usize, + ) -> bool { + collected.mitigations.handle_allowdeny_mitigation_option(v, index, true) + } + }; + (deny_partial_mitigations, $struct_name:ident, $parse:ident) => { + pub(super) fn deny_partial_mitigations( + _cg: &mut super::$struct_name, + collected: &mut super::CollectedOptions, + v: Option<&str>, + index: usize, + ) -> bool { + collected.mitigations.handle_allowdeny_mitigation_option(v, index, false) + } + }; + ($opt:ident, $struct_name:ident, $parse:ident) => { + pub(super) fn $opt( + cg: &mut super::$struct_name, + _collected: &mut super::CollectedOptions, + v: Option<&str>, + _index: usize, + ) -> bool { + super::parse::$parse(&mut redirect_field!(cg.$opt), v) + } + }; +} + /// Defines all `CodegenOptions`/`DebuggingOptions` fields and parsers all at once. The goal of this /// macro is to define an interface that can be programmatically used by the option parser /// to initialize the struct without hardcoding field names all over the place. @@ -605,80 +682,130 @@ pub fn is_target_modifier(flag_name: &str) -> bool { /// generated code to parse an option into its respective field in the struct. There are a few /// hand-written parsers for parsing specific types of values in this module. macro_rules! options { - ($struct_name:ident, $tmod_enum_name:ident, $stat:ident, $optmod:ident, $prefix:expr, $outputname:expr, - $($( #[$attr:meta] )* $opt:ident : $t:ty = ( - $init:expr, - $parse:ident, - [$dep_tracking_marker:ident $( $tmod:ident )?], - $desc:expr - $(, removed: $removed:ident )?) - ),* ,) => -( - #[derive(Clone)] - #[rustc_lint_opt_ty] - pub struct $struct_name { $( $( #[$attr] )* pub $opt: $t),* } + ( + $struct_name:ident, + $tmod_enum_name:ident, + $stat:ident, + $optmod:ident, + $prefix:expr, + $outputname:expr, - tmod_enum!( $tmod_enum_name, $prefix, {$($opt, $parse, $t, [$($tmod),*])|*} ); + $( + $(#[$attr:meta])* + $opt:ident : $t:ty = ( + $init:expr, + $parse:ident, + [$dep_tracking_marker:ident $( $modifier_kind:ident )?], + $desc:expr + $(, removed: $removed:ident )? + ), + )* + ) => { + #[derive(Clone)] + #[rustc_lint_opt_ty] + pub struct $struct_name { + $( + $(#[$attr])* + pub $opt: $t, + )* + } - impl Default for $struct_name { - fn default() -> $struct_name { - $struct_name { $($opt: $init),* } + tmod_enum!( + $tmod_enum_name, + $prefix, + { + $( + $opt, $parse, $t, [$($modifier_kind),*] + )|* + } + ); + + impl Default for $struct_name { + fn default() -> $struct_name { + $struct_name { + $( + $opt: $init, + )* + } + } + } + + impl $struct_name { + pub fn build( + early_dcx: &EarlyDiagCtxt, + matches: &getopts::Matches, + target_modifiers: &mut CollectedOptions, + ) -> $struct_name { + build_options(early_dcx, matches, target_modifiers, $stat, $prefix, $outputname) + } + + fn dep_tracking_hash( + &self, + for_crate_hash: bool, + error_format: ErrorOutputType, + ) -> Hash64 { + let mut sub_hashes = BTreeMap::new(); + $( + hash_opt!( + $opt, + &self.$opt, + &mut sub_hashes, + for_crate_hash, + [$dep_tracking_marker] + ); + )* + let mut hasher = StableHasher::new(); + dep_tracking::stable_hash( + sub_hashes, + &mut hasher, + error_format, + for_crate_hash, + ); + hasher.finish() + } + + pub fn gather_target_modifiers( + &self, + _mods: &mut Vec, + _tmod_vals: &BTreeMap, + ) { + $( + gather_tmods!( + $struct_name, + $tmod_enum_name, + $opt, + &self.$opt, + $init, + _mods, + _tmod_vals, + [$dep_tracking_marker], + [$($modifier_kind),*] + ); + )* + } + } + + pub const $stat: OptionDescrs<$struct_name> = &[ + $( + OptionDesc { + name: stringify!($opt), + setter: $optmod::$opt, + type_desc: desc::$parse, + desc: $desc, + removed: None $( .or(Some(RemovedOption::$removed)) )?, + tmod: tmod_enum_opt!($struct_name, $tmod_enum_name, $opt, $($modifier_kind),*), + mitigation: mitigation_enum_opt!($opt, $($modifier_kind),*), + }, + )* + ]; + + mod $optmod { + $( + setter_for!($opt, $struct_name, $parse); + )* } } - - impl $struct_name { - pub fn build( - early_dcx: &EarlyDiagCtxt, - matches: &getopts::Matches, - target_modifiers: &mut BTreeMap, - ) -> $struct_name { - build_options(early_dcx, matches, target_modifiers, $stat, $prefix, $outputname) - } - - fn dep_tracking_hash(&self, for_crate_hash: bool, error_format: ErrorOutputType) -> Hash64 { - let mut sub_hashes = BTreeMap::new(); - $({ - hash_opt!($opt, - &self.$opt, - &mut sub_hashes, - for_crate_hash, - [$dep_tracking_marker]); - })* - let mut hasher = StableHasher::new(); - dep_tracking::stable_hash(sub_hashes, - &mut hasher, - error_format, - for_crate_hash - ); - hasher.finish() - } - - pub fn gather_target_modifiers( - &self, - _mods: &mut Vec, - _tmod_vals: &BTreeMap, - ) { - $({ - gather_tmods!($struct_name, $tmod_enum_name, $opt, &self.$opt, $init, _mods, _tmod_vals, - [$dep_tracking_marker], [$($tmod),*]); - })* - } - } - - pub const $stat: OptionDescrs<$struct_name> = - &[ $( OptionDesc{ name: stringify!($opt), setter: $optmod::$opt, - type_desc: desc::$parse, desc: $desc, removed: None $( .or(Some(RemovedOption::$removed)) )?, - tmod: tmod_enum_opt!($struct_name, $tmod_enum_name, $opt, $($tmod),*) } ),* ]; - - mod $optmod { - $( - pub(super) fn $opt(cg: &mut super::$struct_name, v: Option<&str>) -> bool { - super::parse::$parse(&mut redirect_field!(cg.$opt), v) - } - )* - } - -) } +} impl CodegenOptions { // JUSTIFICATION: defn of the suggested wrapper fn @@ -702,7 +829,7 @@ macro_rules! redirect_field { }; } -type OptionSetter = fn(&mut O, v: Option<&str>) -> bool; +type OptionSetter = fn(&mut O, &mut CollectedOptions, v: Option<&str>, pos: usize) -> bool; type OptionDescrs = &'static [OptionDesc]; /// Indicates whether a removed option should warn or error. @@ -720,6 +847,7 @@ pub struct OptionDesc { desc: &'static str, removed: Option, tmod: Option, + mitigation: Option, } impl OptionDesc { @@ -735,13 +863,13 @@ pub fn desc(&self) -> &'static str { fn build_options( early_dcx: &EarlyDiagCtxt, matches: &getopts::Matches, - target_modifiers: &mut BTreeMap, + collected_options: &mut CollectedOptions, descrs: OptionDescrs, prefix: &str, outputname: &str, ) -> O { let mut op = O::default(); - for option in matches.opt_strs(prefix) { + for (index, option) in matches.opt_strs_pos(prefix) { let (key, value) = match option.split_once('=') { None => (option, None), Some((k, v)) => (k.to_string(), Some(v)), @@ -749,7 +877,7 @@ fn build_options( let option_to_lookup = key.replace('-', "_"); match descrs.iter().find(|opt_desc| opt_desc.name == option_to_lookup) { - Some(OptionDesc { name: _, setter, type_desc, desc, removed, tmod }) => { + Some(OptionDesc { name: _, setter, type_desc, desc, removed, tmod, mitigation }) => { if let Some(removed) = removed { // deprecation works for prefixed options only assert!(!prefix.is_empty()); @@ -762,7 +890,7 @@ fn build_options( } } } - if !setter(&mut op, value) { + if !setter(&mut op, collected_options, value, index) { match value { None => early_dcx.early_fatal( format!( @@ -778,7 +906,10 @@ fn build_options( } if let Some(tmod) = *tmod { let v = value.map_or(String::new(), ToOwned::to_owned); - target_modifiers.insert(tmod, v); + collected_options.target_modifiers.insert(tmod, v); + } + if let Some(mitigation) = mitigation { + collected_options.mitigations.reset_mitigation(*mitigation, index); } } None => early_dcx.early_fatal(format!("unknown {outputname} option: `{key}`")), @@ -889,6 +1020,10 @@ mod desc { "either a boolean (`yes`, `no`, `on`, `off`, etc), or `nll` (default: `nll`)"; pub(crate) const parse_align: &str = "a number that is a power of 2 between 1 and 2^29"; pub(crate) const parse_assert_incr_state: &str = "one of: `loaded`, `not-loaded`"; + pub(crate) const parse_allow_partial_mitigations: &str = + super::mitigation_coverage::DeniedPartialMitigationKind::KINDS; + pub(crate) const parse_deny_partial_mitigations: &str = + super::mitigation_coverage::DeniedPartialMitigationKind::KINDS; } pub mod parse { @@ -2095,7 +2230,7 @@ pub(crate) fn parse_assert_incr_state( collapse_macro_debuginfo: CollapseMacroDebuginfo = (CollapseMacroDebuginfo::Unspecified, parse_collapse_macro_debuginfo, [TRACKED], "set option to collapse debuginfo for macros"), - control_flow_guard: CFGuard = (CFGuard::Disabled, parse_cfguard, [TRACKED], + control_flow_guard: CFGuard = (CFGuard::Disabled, parse_cfguard, [TRACKED MITIGATION], "use Windows Control Flow Guard (default: no)"), debug_assertions: Option = (None, parse_opt_bool, [TRACKED], "explicitly enable the `cfg(debug_assertions)` directive"), @@ -2237,6 +2372,10 @@ pub(crate) fn parse_assert_incr_state( // tidy-alphabetical-start allow_features: Option> = (None, parse_opt_comma_list, [TRACKED], "only allow the listed language features to be enabled in code (comma separated)"), + // the real parser is at the `setter_for` macro, to allow `-Z` and `-C` options to + // work together. + allow_partial_mitigations: () = ((), parse_allow_partial_mitigations, [UNTRACKED], + "Allow mitigations not enabled for all dependency crates (comma separated list)"), always_encode_mir: bool = (false, parse_bool, [TRACKED], "encode MIR of all functions into the crate metadata (default: no)"), annotate_moves: AnnotateMoves = (AnnotateMoves::Disabled, parse_annotate_moves, [TRACKED], @@ -2304,6 +2443,8 @@ pub(crate) fn parse_assert_incr_state( "deduplicate identical diagnostics (default: yes)"), default_visibility: Option = (None, parse_opt_symbol_visibility, [TRACKED], "overrides the `default_visibility` setting of the target"), + deny_partial_mitigations: () = ((), parse_deny_partial_mitigations, [UNTRACKED], + "Deny mitigations not enabled for all dependency crates (comma separated list)"), dep_info_omit_d_target: bool = (false, parse_bool, [TRACKED], "in dep-info output, omit targets for tracking dependencies of the dep-info files \ themselves (default: no)"), @@ -2463,6 +2604,8 @@ pub(crate) fn parse_assert_incr_state( "a list LLVM plugins to enable (space separated)"), llvm_time_trace: bool = (false, parse_bool, [UNTRACKED], "generate JSON tracing data file from LLVM data (default: no)"), + llvm_writable: bool = (false, parse_bool, [TRACKED], + "emit the LLVM writable attribute for mutable reference arguments (default: no)"), location_detail: LocationDetail = (LocationDetail::all(), parse_location_detail, [TRACKED], "what location details should be tracked when using caller_location, either \ `none`, or a comma separated list of location details, for which \ @@ -2693,7 +2836,7 @@ pub(crate) fn parse_assert_incr_state( src_hash_algorithm: Option = (None, parse_src_file_hash, [TRACKED], "hash algorithm of source files in debug info (`md5`, `sha1`, or `sha256`)"), #[rustc_lint_opt_deny_field_access("use `Session::stack_protector` instead of this field")] - stack_protector: StackProtector = (StackProtector::None, parse_stack_protector, [TRACKED], + stack_protector: StackProtector = (StackProtector::None, parse_stack_protector, [TRACKED MITIGATION], "control stack smash protection strategy (`rustc --print stack-protector-strategies` for details)"), staticlib_allow_rdylib_deps: bool = (false, parse_bool, [TRACKED], "allow staticlibs to have rust dylib dependencies"), diff --git a/compiler/rustc_session/src/options/mitigation_coverage.rs b/compiler/rustc_session/src/options/mitigation_coverage.rs new file mode 100644 index 000000000000..f396392cd263 --- /dev/null +++ b/compiler/rustc_session/src/options/mitigation_coverage.rs @@ -0,0 +1,244 @@ +use std::collections::{BTreeMap, BTreeSet}; +use std::str::FromStr; + +use rustc_macros::{BlobDecodable, Encodable}; +use rustc_span::edition::Edition; +use rustc_target::spec::StackProtector; + +use crate::Session; +use crate::config::Options; +use crate::options::CFGuard; + +#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Encodable, BlobDecodable)] +pub enum DeniedPartialMitigationLevel { + // Enabled(false) should be the bottom of the Ord hierarchy + Enabled(bool), + StackProtector(StackProtector), +} + +impl DeniedPartialMitigationLevel { + pub fn level_str(&self) -> &'static str { + match self { + DeniedPartialMitigationLevel::StackProtector(StackProtector::All) => "=all", + DeniedPartialMitigationLevel::StackProtector(StackProtector::Basic) => "=basic", + DeniedPartialMitigationLevel::StackProtector(StackProtector::Strong) => "=strong", + // currently `=disabled` should not appear + DeniedPartialMitigationLevel::Enabled(false) => "=disabled", + DeniedPartialMitigationLevel::StackProtector(StackProtector::None) + | DeniedPartialMitigationLevel::Enabled(true) => "", + } + } +} + +impl std::fmt::Display for DeniedPartialMitigationLevel { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self { + DeniedPartialMitigationLevel::StackProtector(StackProtector::All) => { + write!(f, "all") + } + DeniedPartialMitigationLevel::StackProtector(StackProtector::Basic) => { + write!(f, "basic") + } + DeniedPartialMitigationLevel::StackProtector(StackProtector::Strong) => { + write!(f, "strong") + } + DeniedPartialMitigationLevel::Enabled(true) => { + write!(f, "enabled") + } + DeniedPartialMitigationLevel::StackProtector(StackProtector::None) + | DeniedPartialMitigationLevel::Enabled(false) => { + write!(f, "disabled") + } + } + } +} + +impl From for DeniedPartialMitigationLevel { + fn from(value: bool) -> Self { + DeniedPartialMitigationLevel::Enabled(value) + } +} + +impl From for DeniedPartialMitigationLevel { + fn from(value: StackProtector) -> Self { + DeniedPartialMitigationLevel::StackProtector(value) + } +} + +#[derive(Copy, Clone)] +struct MitigationStatus { + // This is the index of the option in the command line. This is needed because + // re-enabling a mitigation resets the partial mitigation status if it's later in the command + // line, and this works across `-C` and `-Z` args. + // + // e.g. `-Z stack-protector=strong` resets `-C allow-partial-mitigations=stack-protector`. + index: usize, + allowed: Option, +} + +#[derive(Clone, Default)] +pub struct MitigationCoverageMap { + map: BTreeMap, +} + +impl MitigationCoverageMap { + fn apply_mitigation( + &mut self, + kind: DeniedPartialMitigationKind, + index: usize, + allowed: Option, + ) { + self.map + .entry(kind) + .and_modify(|e| { + if index >= e.index { + *e = MitigationStatus { index, allowed } + } + }) + .or_insert(MitigationStatus { index, allowed }); + } + + pub(crate) fn handle_allowdeny_mitigation_option( + &mut self, + v: Option<&str>, + index: usize, + allowed: bool, + ) -> bool { + match v { + Some(s) => { + for sub in s.split(',') { + match sub.parse() { + Ok(kind) => self.apply_mitigation(kind, index, Some(allowed)), + Err(_) => return false, + } + } + true + } + None => false, + } + } + + pub(crate) fn reset_mitigation(&mut self, kind: DeniedPartialMitigationKind, index: usize) { + self.apply_mitigation(kind, index, None); + } +} + +pub struct DeniedPartialMitigationKindParseError; + +macro_rules! intersperse { + ($sep:expr, ($first:expr $(, $rest:expr)* $(,)?)) => { + concat!($first $(, $sep, $rest)*) + }; +} + +macro_rules! denied_partial_mitigations { + ([$self:ident] enum $kind:ident {$(($name:ident, $text:expr, $since:ident, $code:expr)),*}) => { + #[allow(non_camel_case_types)] + #[derive(Copy, Clone, Debug, PartialEq, Eq, Hash, PartialOrd, Ord, Encodable, BlobDecodable)] + pub enum DeniedPartialMitigationKind { + $($name),* + } + + impl std::fmt::Display for DeniedPartialMitigationKind { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self { + $(DeniedPartialMitigationKind::$name => write!(f, $text)),* + } + } + } + + impl DeniedPartialMitigationKind { + pub(crate) const KINDS: &'static str = concat!("comma-separated list of mitigation kinds (available: ", + intersperse!(", ", ($(concat!("`", $text, "`")),*)), ")"); + } + + impl FromStr for DeniedPartialMitigationKind { + type Err = DeniedPartialMitigationKindParseError; + + fn from_str(v: &str) -> Result { + match v { + $($text => Ok(DeniedPartialMitigationKind::$name)),* + , + _ => Err(DeniedPartialMitigationKindParseError), + } + } + } + + #[allow(unused)] + impl DeniedPartialMitigationKind { + pub fn allowed_by_default_at(&self, edition: Edition) -> bool { + let denied_since = match self { + // Should change the denied-since edition of StackProtector to 2015 + // (all editions) when `-C stack-protector` is stabilized. + $(DeniedPartialMitigationKind::$name => Edition::$since),* + }; + edition < denied_since + } + } + + impl Options { + pub fn all_denied_partial_mitigations(&self) -> impl Iterator { + [$(DeniedPartialMitigationKind::$name),*].into_iter() + } + } + + impl Session { + pub fn gather_enabled_denied_partial_mitigations(&$self) -> Vec { + let mut mitigations = [ + $( + DeniedPartialMitigation { + kind: DeniedPartialMitigationKind::$name, + level: From::from($code), + } + ),* + ]; + mitigations.sort(); + mitigations.into_iter().collect() + } + } + } +} + +denied_partial_mitigations! { + [self] + enum DeniedPartialMitigationKind { + // The mitigation name should match the option name in rustc_session::options, + // to allow for resetting the mitigation + (stack_protector, "stack-protector", EditionFuture, self.stack_protector()), + (control_flow_guard, "control-flow-guard", EditionFuture, self.opts.cg.control_flow_guard == CFGuard::Checks) + } +} + +/// A mitigation that cannot be partially enabled (see +/// [RFC 3855](https://github.com/rust-lang/rfcs/pull/3855)), but are currently enabled for this +/// crate. +#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Encodable, BlobDecodable)] +pub struct DeniedPartialMitigation { + pub kind: DeniedPartialMitigationKind, + pub level: DeniedPartialMitigationLevel, +} + +impl Options { + // Return the list of mitigations that are allowed to be partial + pub fn allowed_partial_mitigations( + &self, + edition: Edition, + ) -> impl Iterator { + let mut result: BTreeSet<_> = self + .all_denied_partial_mitigations() + .filter(|mitigation| mitigation.allowed_by_default_at(edition)) + .collect(); + for (kind, MitigationStatus { index: _, allowed }) in &self.mitigation_coverage_map.map { + match allowed { + Some(true) => { + result.insert(*kind); + } + Some(false) => { + result.remove(kind); + } + None => {} + } + } + result.into_iter() + } +} diff --git a/compiler/rustc_session/src/session.rs b/compiler/rustc_session/src/session.rs index 786cf0a373d8..a9e7f1503b9c 100644 --- a/compiler/rustc_session/src/session.rs +++ b/compiler/rustc_session/src/session.rs @@ -40,7 +40,7 @@ Input, InstrumentCoverage, OptLevel, OutFileName, OutputType, SwitchWithOptPath, }; use crate::filesearch::FileSearch; -use crate::lint::{CheckLintNameResult, LintId, RegisteredTools}; +use crate::lint::LintId; use crate::parse::{ParseSess, add_feature_diagnostics}; use crate::search_paths::SearchPath; use crate::{errors, filesearch, lint}; @@ -81,15 +81,6 @@ pub struct CompilerIO { pub trait DynLintStore: Any + DynSync + DynSend { /// Provides a way to access lint groups without depending on `rustc_lint` fn lint_groups_iter(&self) -> Box + '_>; - - fn check_lint_name( - &self, - lint_name: &str, - tool_name: Option, - registered_tools: &RegisteredTools, - ) -> CheckLintNameResult<'_>; - - fn find_lints(&self, lint_name: &str) -> Option<&[LintId]>; } /// Represents the data associated with a compilation diff --git a/compiler/rustc_span/src/caching_source_map_view.rs b/compiler/rustc_span/src/caching_source_map_view.rs index 5c8b1400f36b..3a3f238a7e55 100644 --- a/compiler/rustc_span/src/caching_source_map_view.rs +++ b/compiler/rustc_span/src/caching_source_map_view.rs @@ -141,7 +141,7 @@ pub fn span_data_to_lines_and_cols( lo_line_number, span_data.lo - lo_line_bounds.start, hi_line_number, - span_data.hi, + span_data.hi - hi_line_bounds.start, )) } diff --git a/compiler/rustc_span/src/source_map.rs b/compiler/rustc_span/src/source_map.rs index a42d4e0d0555..47c933e245d4 100644 --- a/compiler/rustc_span/src/source_map.rs +++ b/compiler/rustc_span/src/source_map.rs @@ -743,7 +743,7 @@ pub fn span_extend_prev_while( let n = s[..start] .char_indices() .rfind(|&(_, c)| !f(c)) - .map_or(start, |(i, _)| start - i - 1); + .map_or(start, |(i, c)| start - i - c.len_utf8()); Ok(span.with_lo(span.lo() - BytePos(n as u32))) }) } diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs index 33bc5a578e8b..981bfed363dc 100644 --- a/compiler/rustc_span/src/symbol.rs +++ b/compiler/rustc_span/src/symbol.rs @@ -196,6 +196,7 @@ Continue, ControlFlow, Copy, + Cow, Debug, Default, Deref, @@ -505,6 +506,7 @@ avx512f, await_macro, backchain, + backend_repr, bang, begin_panic, bench, @@ -587,6 +589,7 @@ cfg_target_has_atomic, cfg_target_has_atomic_equal_alignment, cfg_target_has_reliable_f16_f128, + cfg_target_object_format, cfg_target_thread_local, cfg_target_vendor, cfg_trace: "", // must not be a valid identifier @@ -621,6 +624,7 @@ coerce_pointee_validated, coerce_shared, coerce_unsized, + coff, cold, cold_path, collapse_debuginfo, @@ -637,7 +641,6 @@ compiler_move, concat, concat_bytes, - concat_idents, conservative_impl_trait, console, const_allocate, @@ -799,6 +802,7 @@ diagnostic_namespace, diagnostic_on_const, diagnostic_on_move, + diagnostic_on_unknown, dialect, direct, discriminant_kind, @@ -850,6 +854,7 @@ eii_internals, eii_shared_macro, element_ty, + elf, // Notes about `sym::empty`: // - It should only be used when it genuinely means "empty symbol". Use // `Option` when "no symbol" is a possibility. @@ -947,6 +952,7 @@ floorf32, floorf64, floorf128, + fma4_target_feature, fmaf16, fmaf32, fmaf64, @@ -1164,6 +1170,7 @@ linkonce_odr, lint_reasons, literal, + little, big, load, loaded_from_disk, local, @@ -1190,6 +1197,7 @@ lt, m68k, m68k_target_feature, + macho: "mach-o", macro_at_most_once_rep, macro_attr, macro_attributes_in_derive_output, @@ -1418,6 +1426,7 @@ on_const, on_move, on_unimplemented, + on_unknown, opaque, opaque_module_name_placeholder: "", ops, @@ -1708,7 +1717,6 @@ rustc_const_unstable, rustc_conversion_suggestion, rustc_deallocator, - rustc_def_path, rustc_default_body_unstable, rustc_delayed_bug_from_inside_query, rustc_deny_explicit_impl, @@ -1720,10 +1728,14 @@ rustc_driver, rustc_dummy, rustc_dump_def_parents, + rustc_dump_def_path, + rustc_dump_hidden_type_of_opaques, rustc_dump_inferred_outlives, rustc_dump_item_bounds, + rustc_dump_layout, rustc_dump_object_lifetime_defaults, rustc_dump_predicates, + rustc_dump_symbol_name, rustc_dump_user_args, rustc_dump_variances, rustc_dump_variances_of_opaques, @@ -1735,13 +1747,11 @@ rustc_expected_cgu_reuse, rustc_force_inline, rustc_has_incoherent_inherent_impls, - rustc_hidden_type_of_opaques, rustc_if_this_changed, rustc_inherit_overflow_checks, rustc_insignificant_dtor, rustc_intrinsic, rustc_intrinsic_const_stable_indirect, - rustc_layout, rustc_layout_scalar_valid_range_end, rustc_layout_scalar_valid_range_start, rustc_legacy_const_generics, @@ -1753,11 +1763,13 @@ rustc_main, rustc_mir, rustc_must_implement_one_of, + rustc_must_match_exhaustively, rustc_never_returns_null_ptr, rustc_never_type_options, rustc_no_implicit_autorefs, rustc_no_implicit_bounds, rustc_no_mir_inline, + rustc_no_writable, rustc_non_const_trait_method, rustc_nonnull_optimization_guaranteed, rustc_nounwind, @@ -1789,7 +1801,6 @@ rustc_specialization_trait, rustc_std_internal_symbol, rustc_strict_coherence, - rustc_symbol_name, rustc_test_marker, rustc_then_this_would_need, rustc_trivial_field_reads, @@ -2009,6 +2020,7 @@ target_has_reliable_f16_math, target_has_reliable_f128, target_has_reliable_f128_math, + target_object_format, target_os, target_pointer_width, target_thread_local, @@ -2174,6 +2186,7 @@ unstable_location_reason_default: "this crate is being loaded from the sysroot, an \ unstable location; did you mean to load this crate \ from crates.io via `Cargo.toml` instead?", + unstable_removed, untagged_unions, unused_imports, unwind, @@ -2198,6 +2211,7 @@ v1, v8plus, va_arg, + va_arg_safe, va_copy, va_end, va_list, @@ -2232,6 +2246,7 @@ vtable_size, warn, wasip2, + wasm, wasm32, wasm64, wasm_abi, @@ -2266,6 +2281,7 @@ x86_amx_intrinsics, x87_reg, x87_target_feature, + xcoff, xer, xmm_reg, xop_target_feature, diff --git a/compiler/rustc_symbol_mangling/Cargo.toml b/compiler/rustc_symbol_mangling/Cargo.toml index d28eb3f04706..1df8d641a4ca 100644 --- a/compiler/rustc_symbol_mangling/Cargo.toml +++ b/compiler/rustc_symbol_mangling/Cargo.toml @@ -9,7 +9,6 @@ punycode = "0.4.0" rustc-demangle = "0.1.27" rustc_abi = { path = "../rustc_abi" } rustc_data_structures = { path = "../rustc_data_structures" } -rustc_errors = { path = "../rustc_errors" } rustc_hashes = { path = "../rustc_hashes" } rustc_hir = { path = "../rustc_hir" } rustc_middle = { path = "../rustc_middle" } diff --git a/compiler/rustc_symbol_mangling/src/errors.rs b/compiler/rustc_symbol_mangling/src/errors.rs deleted file mode 100644 index ada9e3fb1562..000000000000 --- a/compiler/rustc_symbol_mangling/src/errors.rs +++ /dev/null @@ -1,41 +0,0 @@ -//! Errors emitted by symbol_mangling. - -use std::fmt; - -use rustc_errors::{Diag, DiagCtxtHandle, Diagnostic, EmissionGuarantee, Level}; -use rustc_span::Span; - -pub struct TestOutput { - pub span: Span, - pub kind: Kind, - pub content: String, -} - -// This diagnostic doesn't need translation because (a) it doesn't contain any -// natural language, and (b) it's only used in tests. So we construct it -// manually and avoid the fluent machinery. -impl Diagnostic<'_, G> for TestOutput { - fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { - let TestOutput { span, kind, content } = self; - - Diag::new(dcx, level, format!("{kind}({content})")).with_span(span) - } -} - -pub enum Kind { - SymbolName, - Demangling, - DemanglingAlt, - DefPath, -} - -impl fmt::Display for Kind { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self { - Kind::SymbolName => write!(f, "symbol-name"), - Kind::Demangling => write!(f, "demangling"), - Kind::DemanglingAlt => write!(f, "demangling-alt"), - Kind::DefPath => write!(f, "def-path"), - } - } -} diff --git a/compiler/rustc_symbol_mangling/src/export.rs b/compiler/rustc_symbol_mangling/src/export.rs index 89ee4743a6f4..70b63bfcf64e 100644 --- a/compiler/rustc_symbol_mangling/src/export.rs +++ b/compiler/rustc_symbol_mangling/src/export.rs @@ -134,7 +134,7 @@ fn abi_hash(&self, tcx: TyCtxt<'tcx>, hasher: &mut StableHasher) { for ty in self.inputs_and_output { ty.abi_hash(tcx, hasher); } - self.safety.is_safe().abi_hash(tcx, hasher); + self.safety().is_safe().abi_hash(tcx, hasher); } } diff --git a/compiler/rustc_symbol_mangling/src/lib.rs b/compiler/rustc_symbol_mangling/src/lib.rs index 3ac8a566374c..c052037f05b3 100644 --- a/compiler/rustc_symbol_mangling/src/lib.rs +++ b/compiler/rustc_symbol_mangling/src/lib.rs @@ -101,7 +101,6 @@ mod legacy; mod v0; -pub mod errors; pub mod test; pub use v0::mangle_internal_symbol; diff --git a/compiler/rustc_symbol_mangling/src/test.rs b/compiler/rustc_symbol_mangling/src/test.rs index b4d9031469dd..a4364cc20b68 100644 --- a/compiler/rustc_symbol_mangling/src/test.rs +++ b/compiler/rustc_symbol_mangling/src/test.rs @@ -1,17 +1,14 @@ //! Walks the crate looking for items/impl-items/trait-items that have -//! either a `rustc_symbol_name` or `rustc_def_path` attribute and +//! either a `rustc_dump_symbol_name` or `rustc_dump_def_path` attribute and //! generates an error giving, respectively, the symbol name or //! def-path. This is used for unit testing the code that generates //! paths etc in all kinds of annoying scenarios. -use rustc_hir::def_id::LocalDefId; -use rustc_hir::find_attr; +use rustc_hir::{CRATE_OWNER_ID, find_attr}; use rustc_middle::ty::print::with_no_trimmed_paths; use rustc_middle::ty::{GenericArgs, Instance, TyCtxt}; -use crate::errors::{Kind, TestOutput}; - -pub fn report_symbol_names(tcx: TyCtxt<'_>) { +pub fn dump_symbol_names_and_def_paths(tcx: TyCtxt<'_>) { // if the `rustc_attrs` feature is not enabled, then the // attributes we are interested in cannot be present anyway, so // skip the walk. @@ -20,73 +17,33 @@ pub fn report_symbol_names(tcx: TyCtxt<'_>) { } tcx.dep_graph.with_ignore(|| { - let mut symbol_names = SymbolNamesTest { tcx }; - let crate_items = tcx.hir_crate_items(()); + for id in tcx.hir_crate_items(()).owners() { + if id == CRATE_OWNER_ID { + continue; + } - for id in crate_items.free_items() { - symbol_names.process_attrs(id.owner_id.def_id); - } + // The format `$tag($value)` is chosen so that tests can elect to test the + // entirety of the string, if they choose, or else just some subset. - for id in crate_items.trait_items() { - symbol_names.process_attrs(id.owner_id.def_id); - } + if let Some(&span) = find_attr!(tcx, id.def_id, RustcDumpSymbolName(span) => span) { + let def_id = id.def_id.to_def_id(); + let args = GenericArgs::identity_for_item(tcx, id.def_id); + let args = tcx.erase_and_anonymize_regions(args); + let instance = Instance::new_raw(def_id, args); + let mangled = tcx.symbol_name(instance); - for id in crate_items.impl_items() { - symbol_names.process_attrs(id.owner_id.def_id); - } + tcx.dcx().span_err(span, format!("symbol-name({mangled})")); - for id in crate_items.foreign_items() { - symbol_names.process_attrs(id.owner_id.def_id); + if let Ok(demangling) = rustc_demangle::try_demangle(mangled.name) { + tcx.dcx().span_err(span, format!("demangling({demangling})")); + tcx.dcx().span_err(span, format!("demangling-alt({demangling:#})")); + } + } + + if let Some(&span) = find_attr!(tcx, id.def_id, RustcDumpDefPath(span) => span) { + let def_path = with_no_trimmed_paths!(tcx.def_path_str(id.def_id)); + tcx.dcx().span_err(span, format!("def-path({def_path})")); + } } }) } - -struct SymbolNamesTest<'tcx> { - tcx: TyCtxt<'tcx>, -} - -impl SymbolNamesTest<'_> { - fn process_attrs(&mut self, def_id: LocalDefId) { - let tcx = self.tcx; - // The formatting of `tag({})` is chosen so that tests can elect - // to test the entirety of the string, if they choose, or else just - // some subset. - - if let Some(attr_span) = find_attr!(tcx, def_id, RustcSymbolName(span) => span) { - let def_id = def_id.to_def_id(); - let instance = Instance::new_raw( - def_id, - tcx.erase_and_anonymize_regions(GenericArgs::identity_for_item(tcx, def_id)), - ); - let mangled = tcx.symbol_name(instance); - tcx.dcx().emit_err(TestOutput { - span: *attr_span, - kind: Kind::SymbolName, - content: format!("{mangled}"), - }); - if let Ok(demangling) = rustc_demangle::try_demangle(mangled.name) { - tcx.dcx().emit_err(TestOutput { - span: *attr_span, - kind: Kind::Demangling, - content: format!("{demangling}"), - }); - tcx.dcx().emit_err(TestOutput { - span: *attr_span, - kind: Kind::DemanglingAlt, - content: format!("{demangling:#}"), - }); - } - } - - if let Some(attr_span) = find_attr!( - tcx, def_id, - RustcDefPath(span) => span - ) { - tcx.dcx().emit_err(TestOutput { - span: *attr_span, - kind: Kind::DefPath, - content: with_no_trimmed_paths!(tcx.def_path_str(def_id)), - }); - } - } -} diff --git a/compiler/rustc_symbol_mangling/src/v0.rs b/compiler/rustc_symbol_mangling/src/v0.rs index fa839eb84558..da31e0598d3e 100644 --- a/compiler/rustc_symbol_mangling/src/v0.rs +++ b/compiler/rustc_symbol_mangling/src/v0.rs @@ -551,10 +551,10 @@ fn print_type(&mut self, ty: Ty<'tcx>) -> Result<(), PrintError> { let sig = sig_tys.with(hdr); self.push("F"); self.wrap_binder(&sig, |p, sig| { - if sig.safety.is_unsafe() { + if sig.safety().is_unsafe() { p.push("U"); } - match sig.abi { + match sig.abi() { ExternAbi::Rust => {} ExternAbi::C { unwind: false } => p.push("KC"), abi => { @@ -570,7 +570,7 @@ fn print_type(&mut self, ty: Ty<'tcx>) -> Result<(), PrintError> { for &ty in sig.inputs() { ty.print(p)?; } - if sig.c_variadic { + if sig.c_variadic() { p.push("v"); } p.push("E"); @@ -888,7 +888,6 @@ fn print_path_with_simple( DefPathData::Closure => 'C', DefPathData::Ctor => 'c', DefPathData::AnonConst => 'K', - DefPathData::LateAnonConst => 'k', DefPathData::OpaqueTy => 'i', DefPathData::SyntheticCoroutineBody => 's', DefPathData::NestedStatic => 'n', @@ -900,7 +899,6 @@ fn print_path_with_simple( | DefPathData::Impl | DefPathData::MacroNs(_) | DefPathData::LifetimeNs(_) - | DefPathData::DesugaredAnonymousLifetime | DefPathData::OpaqueLifetime(_) | DefPathData::AnonAssocTy(..) => { bug!("symbol_names: unexpected DefPathData: {:?}", disambiguated_data.data) diff --git a/compiler/rustc_target/src/callconv/aarch64.rs b/compiler/rustc_target/src/callconv/aarch64.rs index e9a19aa7024b..ce69427cbdd5 100644 --- a/compiler/rustc_target/src/callconv/aarch64.rs +++ b/compiler/rustc_target/src/callconv/aarch64.rs @@ -35,7 +35,7 @@ fn is_homogeneous_aggregate<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>) -> Opti // The softfloat ABI treats floats like integers, so they // do not get homogeneous aggregate treatment. RegKind::Float => cx.target_spec().rustc_abi != Some(RustcAbi::Softfloat), - RegKind::Vector => size.bits() == 64 || size.bits() == 128, + RegKind::Vector { .. } => size.bits() == 64 || size.bits() == 128, }; valid_unit.then_some(Uniform::consecutive(unit, size)) diff --git a/compiler/rustc_target/src/callconv/arm.rs b/compiler/rustc_target/src/callconv/arm.rs index 4c1ff27aac50..41c3a0a0210f 100644 --- a/compiler/rustc_target/src/callconv/arm.rs +++ b/compiler/rustc_target/src/callconv/arm.rs @@ -19,7 +19,7 @@ fn is_homogeneous_aggregate<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>) -> Opti let valid_unit = match unit.kind { RegKind::Integer => false, RegKind::Float => true, - RegKind::Vector => size.bits() == 64 || size.bits() == 128, + RegKind::Vector { .. } => size.bits() == 64 || size.bits() == 128, }; valid_unit.then_some(Uniform::consecutive(unit, size)) diff --git a/compiler/rustc_target/src/callconv/mod.rs b/compiler/rustc_target/src/callconv/mod.rs index 7dc270795281..f8c82faaf8bd 100644 --- a/compiler/rustc_target/src/callconv/mod.rs +++ b/compiler/rustc_target/src/callconv/mod.rs @@ -110,9 +110,9 @@ mod attr_impl { // The subset of llvm::Attribute needed for arguments, packed into a bitfield. #[derive(Clone, Copy, Default, Hash, PartialEq, Eq, HashStable_Generic)] - pub struct ArgAttribute(u8); + pub struct ArgAttribute(u16); bitflags::bitflags! { - impl ArgAttribute: u8 { + impl ArgAttribute: u16 { const CapturesNone = 0b111; const CapturesAddress = 0b110; const CapturesReadOnly = 0b100; @@ -121,6 +121,7 @@ impl ArgAttribute: u8 { const ReadOnly = 1 << 5; const InReg = 1 << 6; const NoUndef = 1 << 7; + const Writable = 1 << 8; } } rustc_data_structures::external_bitflags_debug! { ArgAttribute } diff --git a/compiler/rustc_target/src/callconv/powerpc64.rs b/compiler/rustc_target/src/callconv/powerpc64.rs index d807617491d1..6a8a6841781c 100644 --- a/compiler/rustc_target/src/callconv/powerpc64.rs +++ b/compiler/rustc_target/src/callconv/powerpc64.rs @@ -36,7 +36,7 @@ fn is_homogeneous_aggregate<'a, Ty, C>( let valid_unit = match unit.kind { RegKind::Integer => false, RegKind::Float => true, - RegKind::Vector => arg.layout.size.bits() == 128, + RegKind::Vector { .. } => arg.layout.size.bits() == 128, }; valid_unit.then_some(Uniform::consecutive(unit, arg.layout.size)) diff --git a/compiler/rustc_target/src/callconv/s390x.rs b/compiler/rustc_target/src/callconv/s390x.rs index a2ff6f5a3a03..581c1e2e862c 100644 --- a/compiler/rustc_target/src/callconv/s390x.rs +++ b/compiler/rustc_target/src/callconv/s390x.rs @@ -3,7 +3,7 @@ use rustc_abi::{BackendRepr, HasDataLayout, TyAbiInterface}; -use crate::callconv::{ArgAbi, FnAbi, Reg, RegKind}; +use crate::callconv::{ArgAbi, FnAbi, Reg}; use crate::spec::{Env, HasTargetSpec, Os}; fn classify_ret(ret: &mut ArgAbi<'_, Ty>) { @@ -51,7 +51,7 @@ fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>) if arg.layout.is_single_vector_element(cx, size) { // pass non-transparent wrappers around a vector as `PassMode::Cast` - arg.cast_to(Reg { kind: RegKind::Vector, size }); + arg.cast_to(Reg::opaque_vector(size)); return; } } diff --git a/compiler/rustc_target/src/callconv/x86.rs b/compiler/rustc_target/src/callconv/x86.rs index 9aaa411db6c0..81ff1a2a4590 100644 --- a/compiler/rustc_target/src/callconv/x86.rs +++ b/compiler/rustc_target/src/callconv/x86.rs @@ -1,9 +1,8 @@ use rustc_abi::{ - AddressSpace, Align, BackendRepr, HasDataLayout, Primitive, Reg, RegKind, TyAbiInterface, - TyAndLayout, + AddressSpace, Align, BackendRepr, HasDataLayout, Primitive, Reg, RegKind, TyAndLayout, }; -use crate::callconv::{ArgAttribute, FnAbi, PassMode}; +use crate::callconv::{ArgAttribute, FnAbi, PassMode, TyAbiInterface}; use crate::spec::{HasTargetSpec, RustcAbi}; #[derive(PartialEq)] @@ -175,7 +174,7 @@ pub(crate) fn fill_inregs<'a, Ty, C>( // At this point we know this must be a primitive of sorts. let unit = arg.layout.homogeneous_aggregate(cx).unwrap().unit().unwrap(); assert_eq!(unit.size, arg.layout.size); - if matches!(unit.kind, RegKind::Float | RegKind::Vector) { + if matches!(unit.kind, RegKind::Float | RegKind::Vector { .. }) { continue; } @@ -226,7 +225,7 @@ pub(crate) fn compute_rust_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty // This is a single scalar that fits into an SSE register, and the target uses the // SSE ABI. We prefer this over integer registers as float scalars need to be in SSE // registers for float operations, so that's the best place to pass them around. - fn_abi.ret.cast_to(Reg { kind: RegKind::Vector, size: fn_abi.ret.layout.size }); + fn_abi.ret.cast_to(Reg::opaque_vector(fn_abi.ret.layout.size)); } else if fn_abi.ret.layout.size <= Primitive::Pointer(AddressSpace::ZERO).size(cx) { // Same size or smaller than pointer, return in an integer register. fn_abi.ret.cast_to(Reg { kind: RegKind::Integer, size: fn_abi.ret.layout.size }); diff --git a/compiler/rustc_target/src/callconv/x86_64.rs b/compiler/rustc_target/src/callconv/x86_64.rs index dc73907c0c18..3055d18ffa01 100644 --- a/compiler/rustc_target/src/callconv/x86_64.rs +++ b/compiler/rustc_target/src/callconv/x86_64.rs @@ -151,7 +151,7 @@ fn reg_component(cls: &[Option], i: &mut usize, size: Size) -> Option Reg::f64(), } } else { - Reg { kind: RegKind::Vector, size: Size::from_bytes(8) * (vec_len as u64) } + Reg::opaque_vector(Size::from_bytes(8) * (vec_len as u64)) }) } Some(c) => unreachable!("reg_component: unhandled class {:?}", c), diff --git a/compiler/rustc_target/src/callconv/x86_win64.rs b/compiler/rustc_target/src/callconv/x86_win64.rs index 624563c68e5b..cece9d032b53 100644 --- a/compiler/rustc_target/src/callconv/x86_win64.rs +++ b/compiler/rustc_target/src/callconv/x86_win64.rs @@ -1,4 +1,4 @@ -use rustc_abi::{BackendRepr, Float, Integer, Primitive, RegKind, Size, TyAbiInterface}; +use rustc_abi::{BackendRepr, Float, Integer, Primitive, Size, TyAbiInterface}; use crate::callconv::{ArgAbi, FnAbi, Reg}; use crate::spec::{HasTargetSpec, RustcAbi}; @@ -33,8 +33,7 @@ pub(crate) fn compute_abi_info<'a, Ty, C: HasTargetSpec>(cx: &C, fn_abi: &mut Fn } else { // `i128` is returned in xmm0 by Clang and GCC // FIXME(#134288): This may change for the `-msvc` targets in the future. - let reg = Reg { kind: RegKind::Vector, size: Size::from_bits(128) }; - a.cast_to(reg); + a.cast_to(Reg::opaque_vector(Size::from_bits(128))); } } else if a.layout.size.bytes() > 8 && !matches!(scalar.primitive(), Primitive::Float(Float::F128)) diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index 68d6162bd590..768e43146a0c 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -47,7 +47,7 @@ use std::{fmt, io}; use rustc_abi::{ - Align, CanonAbi, Endian, ExternAbi, Integer, Size, TargetDataLayout, TargetDataLayoutErrors, + Align, CanonAbi, Endian, ExternAbi, Integer, Size, TargetDataLayout, TargetDataLayoutError, }; use rustc_data_structures::fx::{FxHashSet, FxIndexSet}; use rustc_error_messages::{DiagArgValue, IntoDiagArg, into_diag_arg_using_display}; @@ -1347,6 +1347,7 @@ pub fn ratchet(&mut self, rhs: FramePointer) -> FramePointer { crate::target_spec_enum! { /// Controls use of stack canaries. + #[derive(Encodable, BlobDecodable, HashStable_Generic)] pub enum StackProtector { /// Disable stack canary generation. None = "none", @@ -1395,6 +1396,16 @@ pub fn to_object(&self) -> object::BinaryFormat { Self::Xcoff => object::BinaryFormat::Xcoff, } } + + pub fn desc_symbol(&self) -> Symbol { + match self { + Self::Coff => sym::coff, + Self::Elf => sym::elf, + Self::MachO => sym::macho, + Self::Wasm => sym::wasm, + Self::Xcoff => sym::xcoff, + } + } } impl ToJson for Align { @@ -2166,7 +2177,7 @@ pub struct TargetMetadata { } impl Target { - pub fn parse_data_layout(&self) -> Result> { + pub fn parse_data_layout(&self) -> Result> { let mut dl = TargetDataLayout::parse_from_llvm_datalayout_string( &self.data_layout, self.options.default_address_space, @@ -2174,7 +2185,7 @@ pub fn parse_data_layout(&self) -> Result Result Result Target { let mut base = base::fuchsia::opts(); base.code_model = Some(CodeModel::Medium); base.cpu = "generic-rv64".into(); - base.features = "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(); + base.features = "+m,+a,+f,+d,+c,+v,+zicsr,+zifencei".into(); base.llvm_abiname = LlvmAbi::Lp64d; base.max_atomic_width = Some(64); base.stack_probes = StackProbeType::Inline; diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index 161bb31c664e..9040c4eb1e39 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -422,6 +422,7 @@ pub fn toggle_allowed(&self) -> Result<(), &'static str> { ("ermsb", Unstable(sym::ermsb_target_feature), &[]), ("f16c", Stable, &["avx"]), ("fma", Stable, &["avx"]), + ("fma4", Unstable(sym::fma4_target_feature), &["avx", "sse4a"]), ("fxsr", Stable, &[]), ("gfni", Stable, &["sse2"]), ("kl", Stable, &["sse2"]), @@ -467,7 +468,7 @@ pub fn toggle_allowed(&self) -> Result<(), &'static str> { ("vpclmulqdq", Stable, &["avx", "pclmulqdq"]), ("widekl", Stable, &["kl"]), ("x87", Unstable(sym::x87_target_feature), &[]), - ("xop", Unstable(sym::xop_target_feature), &[/*"fma4", */ "avx", "sse4a"]), + ("xop", Unstable(sym::xop_target_feature), &["fma4", "avx", "sse4a"]), ("xsave", Stable, &[]), ("xsavec", Stable, &["xsave"]), ("xsaveopt", Stable, &["xsave"]), @@ -477,6 +478,7 @@ pub fn toggle_allowed(&self) -> Result<(), &'static str> { const HEXAGON_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ // tidy-alphabetical-start + ("audio", Unstable(sym::hexagon_target_feature), &[]), ("hvx", Unstable(sym::hexagon_target_feature), &[]), ("hvx-ieee-fp", Unstable(sym::hexagon_target_feature), &["hvx"]), ("hvx-length64b", Unstable(sym::hexagon_target_feature), &["hvx"]), @@ -493,6 +495,17 @@ pub fn toggle_allowed(&self) -> Result<(), &'static str> { ("hvxv73", Unstable(sym::hexagon_target_feature), &["hvxv71"]), ("hvxv75", Unstable(sym::hexagon_target_feature), &["hvxv73"]), ("hvxv79", Unstable(sym::hexagon_target_feature), &["hvxv75"]), + ("v60", Unstable(sym::hexagon_target_feature), &[]), + ("v62", Unstable(sym::hexagon_target_feature), &["v60"]), + ("v65", Unstable(sym::hexagon_target_feature), &["v62"]), + ("v66", Unstable(sym::hexagon_target_feature), &["v65"]), + ("v67", Unstable(sym::hexagon_target_feature), &["v66"]), + ("v68", Unstable(sym::hexagon_target_feature), &["v67"]), + ("v69", Unstable(sym::hexagon_target_feature), &["v68"]), + ("v71", Unstable(sym::hexagon_target_feature), &["v69"]), + ("v73", Unstable(sym::hexagon_target_feature), &["v71"]), + ("v75", Unstable(sym::hexagon_target_feature), &["v73"]), + ("v79", Unstable(sym::hexagon_target_feature), &["v75"]), ("zreg", Unstable(sym::hexagon_target_feature), &[]), // tidy-alphabetical-end ]; diff --git a/compiler/rustc_trait_selection/Cargo.toml b/compiler/rustc_trait_selection/Cargo.toml index 0ba46c6ddd56..802fdda6f037 100644 --- a/compiler/rustc_trait_selection/Cargo.toml +++ b/compiler/rustc_trait_selection/Cargo.toml @@ -19,6 +19,6 @@ rustc_session = { path = "../rustc_session" } rustc_span = { path = "../rustc_span" } rustc_transmute = { path = "../rustc_transmute", features = ["rustc"] } smallvec = { version = "1.8.1", features = ["union", "may_dangle"] } -thin-vec = "0.2" +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/mod.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/mod.rs index 19a6c5dfe5ee..051cf29b45b7 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/mod.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/mod.rs @@ -783,12 +783,12 @@ fn cmp_fn_sig( // unsafe extern "C" for<'a> fn(&'a T) -> &'a T // ^^^^^^ let safety = |fn_def, sig: ty::FnSig<'_>| match fn_def { - None => sig.safety.prefix_str(), + None => sig.safety().prefix_str(), Some((did, _)) => { if self.tcx.codegen_fn_attrs(did).safe_target_features { "#[target_features] " } else { - sig.safety.prefix_str() + sig.safety().prefix_str() } } }; @@ -799,11 +799,11 @@ fn cmp_fn_sig( // unsafe extern "C" for<'a> fn(&'a T) -> &'a T // ^^^^^^^^^^ - if sig1.abi != ExternAbi::Rust { - values.0.push(format!("extern {} ", sig1.abi), sig1.abi != sig2.abi); + if sig1.abi() != ExternAbi::Rust { + values.0.push(format!("extern {} ", sig1.abi()), sig1.abi() != sig2.abi()); } - if sig2.abi != ExternAbi::Rust { - values.1.push(format!("extern {} ", sig2.abi), sig1.abi != sig2.abi); + if sig2.abi() != ExternAbi::Rust { + values.1.push(format!("extern {} ", sig2.abi()), sig1.abi() != sig2.abi()); } // unsafe extern "C" for<'a> fn(&'a T) -> &'a T @@ -843,17 +843,17 @@ fn cmp_fn_sig( } } - if sig1.c_variadic { + if sig1.c_variadic() { if len1 > 0 { values.0.push_normal(", "); } - values.0.push("...", !sig2.c_variadic); + values.0.push("...", !sig2.c_variadic()); } - if sig2.c_variadic { + if sig2.c_variadic() { if len2 > 0 { values.1.push_normal(", "); } - values.1.push("...", !sig1.c_variadic); + values.1.push("...", !sig1.c_variadic()); } // unsafe extern "C" for<'a> fn(&'a T) -> &'a T @@ -1826,7 +1826,7 @@ enum Similar<'tcx> { debug!(?diag); } - pub fn type_error_additional_suggestions( + pub(crate) fn type_error_additional_suggestions( &self, trace: &TypeTrace<'tcx>, terr: TypeError<'tcx>, @@ -2274,6 +2274,7 @@ fn as_failure_code(&self, terr: TypeError<'tcx>) -> FailureCode { }, } } + fn as_failure_code_diag( &self, terr: TypeError<'tcx>, diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_error.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_error.rs index 373b756dcdb7..50dbae0a05d6 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_error.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_error.rs @@ -18,9 +18,8 @@ use crate::infer::{RegionResolutionError, SubregionOrigin, TypeTrace, ValuePairs}; use crate::traits::{ObligationCause, ObligationCauseCode}; -// HACK(eddyb) maybe move this in a more central location. #[derive(Copy, Clone)] -pub struct Highlighted<'tcx, T> { +pub(crate) struct Highlighted<'tcx, T> { pub tcx: TyCtxt<'tcx>, pub highlight: RegionHighlightMode<'tcx>, pub value: T, diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/util.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/util.rs index 5f2aab38c31c..252735bbf56b 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/util.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/util.rs @@ -71,7 +71,7 @@ pub fn find_param_with_region<'tcx>( let fn_sig = tcx.liberate_late_bound_regions(id, poly_fn_sig); body.params .iter() - .take(if fn_sig.c_variadic { + .take(if fn_sig.c_variadic() { fn_sig.inputs().len() } else { assert_eq!(fn_sig.inputs().len(), body.params.len()); diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/note_and_explain.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/note_and_explain.rs index fb1d25999116..b34eb2037d01 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/note_and_explain.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/note_and_explain.rs @@ -523,7 +523,7 @@ fn foo(&self, x: T) -> T { x } } (ty::FnPtr(_, hdr), ty::FnDef(def_id, _)) | (ty::FnDef(def_id, _), ty::FnPtr(_, hdr)) => { - if tcx.fn_sig(def_id).skip_binder().safety() < hdr.safety { + if tcx.fn_sig(def_id).skip_binder().safety() < hdr.safety() { if !tcx.codegen_fn_attrs(def_id).safe_target_features { diag.note( "unsafe functions cannot be coerced into safe function pointers", diff --git a/compiler/rustc_trait_selection/src/error_reporting/traits/fulfillment_errors.rs b/compiler/rustc_trait_selection/src/error_reporting/traits/fulfillment_errors.rs index 5e7a59bd7ae8..9ba92cfa2bdf 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/traits/fulfillment_errors.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/traits/fulfillment_errors.rs @@ -4,7 +4,6 @@ use std::collections::hash_set; use std::path::PathBuf; -use rustc_abi::ExternAbi; use rustc_ast::ast::LitKind; use rustc_ast::{LitIntType, TraitObjectSyntax}; use rustc_data_structures::fx::{FxHashMap, FxHashSet}; @@ -39,9 +38,7 @@ use tracing::{debug, instrument}; use super::suggestions::get_explanation_based_on_obligation; -use super::{ - ArgKind, CandidateSimilarity, FindExprBySpan, GetSafeTransmuteErrorAndReason, ImplCandidate, -}; +use super::{ArgKind, CandidateSimilarity, GetSafeTransmuteErrorAndReason, ImplCandidate}; use crate::error_reporting::TypeErrCtxt; use crate::error_reporting::infer::TyCategory; use crate::error_reporting::traits::report_dyn_incompatibility; @@ -452,50 +449,13 @@ pub fn report_selection_error( self.suggest_dereferencing_index(&obligation, &mut err, leaf_trait_predicate); suggested |= self.suggest_dereferences(&obligation, &mut err, leaf_trait_predicate); suggested |= self.suggest_fn_call(&obligation, &mut err, leaf_trait_predicate); - let impl_candidates = self.find_similar_impl_candidates(leaf_trait_predicate); - suggested = if let &[cand] = &impl_candidates[..] { - let cand = cand.trait_ref; - if let (ty::FnPtr(..), ty::FnDef(..)) = - (cand.self_ty().kind(), main_trait_predicate.self_ty().skip_binder().kind()) - { - // Wrap method receivers and `&`-references in parens - let suggestion = if self.tcx.sess.source_map().span_followed_by(span, ".").is_some() { - vec![ - (span.shrink_to_lo(), format!("(")), - (span.shrink_to_hi(), format!(" as {})", cand.self_ty())), - ] - } else if let Some(body) = self.tcx.hir_maybe_body_owned_by(obligation.cause.body_id) { - let mut expr_finder = FindExprBySpan::new(span, self.tcx); - expr_finder.visit_expr(body.value); - if let Some(expr) = expr_finder.result && - let hir::ExprKind::AddrOf(_, _, expr) = expr.kind { - vec![ - (expr.span.shrink_to_lo(), format!("(")), - (expr.span.shrink_to_hi(), format!(" as {})", cand.self_ty())), - ] - } else { - vec![(span.shrink_to_hi(), format!(" as {}", cand.self_ty()))] - } - } else { - vec![(span.shrink_to_hi(), format!(" as {}", cand.self_ty()))] - }; - let trait_ = self.tcx.short_string(cand.print_trait_sugared(), err.long_ty_path()); - let ty = self.tcx.short_string(cand.self_ty(), err.long_ty_path()); - err.multipart_suggestion( - format!( - "the trait `{trait_}` is implemented for fn pointer \ - `{ty}`, try casting using `as`", - ), - suggestion, - Applicability::MaybeIncorrect, - ); - true - } else { - false - } - } else { - false - } || suggested; + suggested |= self.suggest_cast_to_fn_pointer( + &obligation, + &mut err, + leaf_trait_predicate, + main_trait_predicate, + span, + ); suggested |= self.suggest_remove_reference(&obligation, &mut err, leaf_trait_predicate); suggested |= self.suggest_semicolon_removal( @@ -874,7 +834,9 @@ fn report_host_effect_error( } if let Ok(Some(ImplSource::UserDefined(impl_data))) = - SelectionContext::new(self).select(&obligation.with(self.tcx, trait_ref.skip_binder())) + self.enter_forall(trait_ref, |trait_ref_for_select| { + SelectionContext::new(self).select(&obligation.with(self.tcx, trait_ref_for_select)) + }) { let impl_did = impl_data.impl_def_id; let trait_did = trait_ref.def_id(); @@ -3240,23 +3202,11 @@ fn add_help_message_for_fn_trait( let given_ty = Ty::new_fn_ptr( self.tcx, - params.rebind(self.tcx.mk_fn_sig( - given, - self.tcx.types.unit, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )), + params.rebind(self.tcx.mk_fn_sig_safe_rust_abi(given, self.tcx.types.unit)), ); let expected_ty = Ty::new_fn_ptr( self.tcx, - trait_pred.rebind(self.tcx.mk_fn_sig( - expected, - self.tcx.types.unit, - false, - hir::Safety::Safe, - ExternAbi::Rust, - )), + trait_pred.rebind(self.tcx.mk_fn_sig_safe_rust_abi(expected, self.tcx.types.unit)), ); if !self.same_type_modulo_infer(given_ty, expected_ty) { diff --git a/compiler/rustc_trait_selection/src/error_reporting/traits/mod.rs b/compiler/rustc_trait_selection/src/error_reporting/traits/mod.rs index 69afa4f20b3e..0b80666457e4 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/traits/mod.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/traits/mod.rs @@ -577,7 +577,7 @@ pub fn report_dyn_incompatibility<'tcx>( let trait_str = tcx.def_path_str(trait_def_id); let trait_span = tcx.hir_get_if_local(trait_def_id).and_then(|node| match node { hir::Node::Item(item) => match item.kind { - hir::ItemKind::Trait(_, _, _, ident, ..) + hir::ItemKind::Trait(_, _, _, _, ident, ..) | hir::ItemKind::TraitAlias(_, ident, _, _) => Some(ident.span), _ => unreachable!(), }, diff --git a/compiler/rustc_trait_selection/src/error_reporting/traits/suggestions.rs b/compiler/rustc_trait_selection/src/error_reporting/traits/suggestions.rs index e4689e311b64..5a5d8af4ce14 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/traits/suggestions.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/traits/suggestions.rs @@ -29,7 +29,8 @@ use rustc_middle::ty::error::TypeError; use rustc_middle::ty::print::{ PrintPolyTraitPredicateExt as _, PrintPolyTraitRefExt, PrintTraitPredicateExt as _, - with_forced_trimmed_paths, with_no_trimmed_paths, with_types_for_suggestion, + PrintTraitRefExt as _, with_forced_trimmed_paths, with_no_trimmed_paths, + with_types_for_suggestion, }; use rustc_middle::ty::{ self, AdtKind, GenericArgs, InferTy, IsSuggestable, Ty, TyCtxt, TypeFoldable, TypeFolder, @@ -484,7 +485,7 @@ pub fn suggest_restricting_param_bound( let node = self.tcx.hir_node_by_def_id(body_id); match node { hir::Node::Item(hir::Item { - kind: hir::ItemKind::Trait(_, _, _, ident, generics, bounds, _), + kind: hir::ItemKind::Trait(_, _, _, _, ident, generics, bounds, _), .. }) if self_ty == self.tcx.types.self_param => { assert!(param_ty); @@ -547,7 +548,7 @@ pub fn suggest_restricting_param_bound( } hir::Node::Item(hir::Item { kind: - hir::ItemKind::Trait(_, _, _, _, generics, ..) + hir::ItemKind::Trait(_, _, _, _, _, generics, ..) | hir::ItemKind::Impl(hir::Impl { generics, .. }), .. }) if projection.is_some() => { @@ -571,7 +572,7 @@ pub fn suggest_restricting_param_bound( hir::ItemKind::Struct(_, generics, _) | hir::ItemKind::Enum(_, generics, _) | hir::ItemKind::Union(_, generics, _) - | hir::ItemKind::Trait(_, _, _, _, generics, ..) + | hir::ItemKind::Trait(_, _, _, _, _, generics, ..) | hir::ItemKind::Impl(hir::Impl { generics, .. }) | hir::ItemKind::Fn { generics, .. } | hir::ItemKind::TyAlias(_, generics, _) @@ -651,7 +652,7 @@ pub fn suggest_restricting_param_bound( hir::ItemKind::Struct(_, generics, _) | hir::ItemKind::Enum(_, generics, _) | hir::ItemKind::Union(_, generics, _) - | hir::ItemKind::Trait(_, _, _, _, generics, ..) + | hir::ItemKind::Trait(_, _, _, _, _, generics, ..) | hir::ItemKind::Impl(hir::Impl { generics, .. }) | hir::ItemKind::Fn { generics, .. } | hir::ItemKind::TyAlias(_, generics, _) @@ -1142,6 +1143,62 @@ pub(super) fn suggest_fn_call( true } + pub(super) fn suggest_cast_to_fn_pointer( + &self, + obligation: &PredicateObligation<'tcx>, + err: &mut Diag<'_>, + leaf_trait_predicate: ty::PolyTraitPredicate<'tcx>, + main_trait_predicate: ty::PolyTraitPredicate<'tcx>, + span: Span, + ) -> bool { + let &[candidate] = &self.find_similar_impl_candidates(leaf_trait_predicate)[..] else { + return false; + }; + let candidate = candidate.trait_ref; + + if !matches!( + (candidate.self_ty().kind(), main_trait_predicate.self_ty().skip_binder().kind(),), + (ty::FnPtr(..), ty::FnDef(..)) + ) { + return false; + } + + let parenthesized_cast = |span: Span| { + vec![ + (span.shrink_to_lo(), "(".to_string()), + (span.shrink_to_hi(), format!(" as {})", candidate.self_ty())), + ] + }; + // Wrap method receivers and `&`-references in parens. + let suggestion = if self.tcx.sess.source_map().span_followed_by(span, ".").is_some() { + parenthesized_cast(span) + } else if let Some(body) = self.tcx.hir_maybe_body_owned_by(obligation.cause.body_id) { + let mut expr_finder = FindExprBySpan::new(span, self.tcx); + expr_finder.visit_expr(body.value); + if let Some(expr) = expr_finder.result + && let hir::ExprKind::AddrOf(_, _, expr) = expr.kind + { + parenthesized_cast(expr.span) + } else { + vec![(span.shrink_to_hi(), format!(" as {}", candidate.self_ty()))] + } + } else { + vec![(span.shrink_to_hi(), format!(" as {}", candidate.self_ty()))] + }; + + let trait_ = self.tcx.short_string(candidate.print_trait_sugared(), err.long_ty_path()); + let self_ty = self.tcx.short_string(candidate.self_ty(), err.long_ty_path()); + err.multipart_suggestion( + format!( + "the trait `{trait_}` is implemented for fn pointer \ + `{self_ty}`, try casting using `as`", + ), + suggestion, + Applicability::MaybeIncorrect, + ); + true + } + pub(super) fn check_for_binding_assigned_block_without_tail_expression( &self, obligation: &PredicateObligation<'tcx>, @@ -2287,21 +2344,9 @@ pub(crate) fn build_fn_sig_ty<'tcx>( let inputs = trait_ref.args.type_at(1); let sig = match inputs.kind() { ty::Tuple(inputs) if infcx.tcx.is_fn_trait(trait_ref.def_id) => { - infcx.tcx.mk_fn_sig( - *inputs, - infcx.next_ty_var(DUMMY_SP), - false, - hir::Safety::Safe, - ExternAbi::Rust, - ) + infcx.tcx.mk_fn_sig_safe_rust_abi(*inputs, infcx.next_ty_var(DUMMY_SP)) } - _ => infcx.tcx.mk_fn_sig( - [inputs], - infcx.next_ty_var(DUMMY_SP), - false, - hir::Safety::Safe, - ExternAbi::Rust, - ), + _ => infcx.tcx.mk_fn_sig_safe_rust_abi([inputs], infcx.next_ty_var(DUMMY_SP)), }; Ty::new_fn_ptr(infcx.tcx, ty::Binder::dummy(sig)) @@ -3831,7 +3876,7 @@ pub(super) fn note_obligation_cause_code( let mut is_auto_trait = false; match tcx.hir_get_if_local(data.impl_or_alias_def_id) { Some(Node::Item(hir::Item { - kind: hir::ItemKind::Trait(_, is_auto, _, ident, ..), + kind: hir::ItemKind::Trait(_, is_auto, _, _, ident, _, _, _), .. })) => { // FIXME: we should do something else so that it works even on crate foreign @@ -4612,11 +4657,11 @@ fn suggest_option_method_if_applicable( && let [self_ty, found_ty] = trait_ref.args.as_slice() && let Some(fn_ty) = self_ty.as_type().filter(|ty| ty.is_fn()) && let fn_sig @ ty::FnSig { - abi: ExternAbi::Rust, - c_variadic: false, - safety: hir::Safety::Safe, .. } = fn_ty.fn_sig(tcx).skip_binder() + && fn_sig.abi() == ExternAbi::Rust + && !fn_sig.c_variadic() + && fn_sig.safety() == hir::Safety::Safe // Extract first param of fn sig with peeled refs, e.g. `fn(&T)` -> `T` && let Some(&ty::Ref(_, target_ty, needs_mut)) = fn_sig.inputs().first().map(|t| t.kind()) @@ -6074,7 +6119,16 @@ fn point_at_assoc_type_restriction( let ty::ClauseKind::Projection(proj) = clause else { return; }; - let name = tcx.item_name(proj.projection_term.def_id); + let Some(name) = tcx + .opt_rpitit_info(proj.projection_term.def_id) + .and_then(|data| match data { + ty::ImplTraitInTraitData::Trait { fn_def_id, .. } => Some(tcx.item_name(fn_def_id)), + ty::ImplTraitInTraitData::Impl { .. } => None, + }) + .or_else(|| tcx.opt_item_name(proj.projection_term.def_id)) + else { + return; + }; let mut predicates = generics.predicates.iter().peekable(); let mut prev: Option<(&hir::WhereBoundPredicate<'_>, Span)> = None; while let Some(pred) = predicates.next() { diff --git a/compiler/rustc_trait_selection/src/errors.rs b/compiler/rustc_trait_selection/src/errors.rs index 042c17c28195..1656493fc309 100644 --- a/compiler/rustc_trait_selection/src/errors.rs +++ b/compiler/rustc_trait_selection/src/errors.rs @@ -18,26 +18,17 @@ use crate::error_reporting::infer::need_type_info::UnderspecifiedArgKind; use crate::error_reporting::infer::nice_region_error::placeholder_error::Highlighted; -pub mod note_and_explain; +pub(crate) mod note_and_explain; #[derive(Diagnostic)] #[diag("unable to construct a constant value for the unevaluated constant {$unevaluated}")] -pub struct UnableToConstructConstantValue<'a> { +pub(crate) struct UnableToConstructConstantValue<'a> { #[primary_span] pub span: Span, pub unevaluated: ty::UnevaluatedConst<'a>, } -#[derive(Diagnostic)] -#[diag("this attribute must have a value", code = E0232)] -#[note("e.g. `#[rustc_on_unimplemented(message=\"foo\")]`")] -pub struct NoValueInOnUnimplemented { - #[primary_span] - #[label("expected value here")] - pub span: Span, -} - -pub struct NegativePositiveConflict<'tcx> { +pub(crate) struct NegativePositiveConflict<'tcx> { pub impl_span: Span, pub trait_desc: ty::TraitRef<'tcx>, pub self_ty: Option>, @@ -86,13 +77,13 @@ fn into_diag(self, dcx: DiagCtxtHandle<'_>, level: Level) -> Diag<'_, G> { #[derive(Diagnostic)] #[diag("overflow evaluating associated type `{$ty}`")] -pub struct InherentProjectionNormalizationOverflow { +pub(crate) struct InherentProjectionNormalizationOverflow { #[primary_span] pub span: Span, pub ty: String, } -pub enum AdjustSignatureBorrow { +pub(crate) enum AdjustSignatureBorrow { Borrow { to_borrow: Vec<(Span, String)> }, RemoveBorrow { remove_borrow: Vec<(Span, String)> }, } @@ -132,7 +123,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { #[derive(Diagnostic)] #[diag("expected a closure that implements the `{$trait_prefix}{$expected}` trait, but this closure only implements `{$trait_prefix}{$found}`", code = E0525)] -pub struct ClosureKindMismatch { +pub(crate) struct ClosureKindMismatch { #[primary_span] #[label("this closure implements `{$trait_prefix}{$found}`, not `{$trait_prefix}{$expected}`")] pub closure_span: Span, @@ -154,7 +145,7 @@ pub struct ClosureKindMismatch { #[label( "closure is `{$trait_prefix}FnOnce` because it moves the variable `{$place}` out of its environment" )] -pub struct ClosureFnOnceLabel { +pub(crate) struct ClosureFnOnceLabel { #[primary_span] pub span: Span, pub place: String, @@ -163,7 +154,7 @@ pub struct ClosureFnOnceLabel { #[derive(Subdiagnostic)] #[label("closure is `{$trait_prefix}FnMut` because it mutates the variable `{$place}` here")] -pub struct ClosureFnMutLabel { +pub(crate) struct ClosureFnMutLabel { #[primary_span] pub span: Span, pub place: String, @@ -187,7 +178,7 @@ pub(crate) struct CoroClosureNotFn { [normal] type annotations needed for `{$source_name}` *[other] type annotations needed }", code = E0282)] -pub struct AnnotationRequired<'a> { +pub(crate) struct AnnotationRequired<'a> { #[primary_span] pub span: Span, pub source_kind: &'static str, @@ -209,7 +200,7 @@ pub struct AnnotationRequired<'a> { [normal] type annotations needed for `{$source_name}` *[other] type annotations needed }", code = E0283)] -pub struct AmbiguousImpl<'a> { +pub(crate) struct AmbiguousImpl<'a> { #[primary_span] pub span: Span, pub source_kind: &'static str, @@ -231,7 +222,7 @@ pub struct AmbiguousImpl<'a> { [normal] type annotations needed for `{$source_name}` *[other] type annotations needed }", code = E0284)] -pub struct AmbiguousReturn<'a> { +pub(crate) struct AmbiguousReturn<'a> { #[primary_span] pub span: Span, pub source_kind: &'static str, @@ -261,7 +252,7 @@ pub struct AmbiguousReturn<'a> { } }" )] -pub struct InferenceBadError<'a> { +pub(crate) struct InferenceBadError<'a> { #[primary_span] pub span: Span, pub bad_kind: &'static str, @@ -274,7 +265,7 @@ pub struct InferenceBadError<'a> { } #[derive(Subdiagnostic)] -pub enum SourceKindSubdiag<'a> { +pub(crate) enum SourceKindSubdiag<'a> { #[suggestion( "{$kind -> [with_pattern] consider giving `{$name}` an explicit type @@ -343,7 +334,7 @@ pub enum SourceKindSubdiag<'a> { } #[derive(Subdiagnostic)] -pub enum SourceKindMultiSuggestion<'a> { +pub(crate) enum SourceKindMultiSuggestion<'a> { #[multipart_suggestion( "try using a fully qualified path to specify the expected types", style = "verbose", @@ -373,7 +364,7 @@ pub enum SourceKindMultiSuggestion<'a> { } impl<'a> SourceKindMultiSuggestion<'a> { - pub fn new_fully_qualified( + pub(crate) fn new_fully_qualified( span: Span, def_path: String, adjustment: &'a str, @@ -388,7 +379,7 @@ pub fn new_fully_qualified( } } - pub fn new_closure_return( + pub(crate) fn new_closure_return( ty_info: String, data: &'a FnRetTy<'a>, should_wrap_expr: Option, @@ -405,7 +396,7 @@ pub fn new_closure_return( } } -pub enum RegionOriginNote<'a> { +pub(crate) enum RegionOriginNote<'a> { Plain { span: Span, msg: DiagMessage, @@ -501,7 +492,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { } } -pub enum LifetimeMismatchLabels { +pub(crate) enum LifetimeMismatchLabels { InRet { param_span: Span, ret_span: Span, @@ -582,7 +573,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { } } -pub struct AddLifetimeParamsSuggestion<'a> { +pub(crate) struct AddLifetimeParamsSuggestion<'a> { pub tcx: TyCtxt<'a>, pub generic_param_scope: LocalDefId, pub sub: Region<'a>, @@ -609,7 +600,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { match self.tcx.parent_hir_node(self.tcx.local_def_id_to_hir_id(anon_reg.scope)) { hir::Node::Item(hir::Item { - kind: hir::ItemKind::Trait(_, _, _, _, generics, ..), + kind: hir::ItemKind::Trait(_, _, _, _, _, generics, ..), .. }) | hir::Node::Item(hir::Item { @@ -762,7 +753,7 @@ fn visit_ty(&mut self, ty: &'v hir::Ty<'v, AmbigArg>) { #[derive(Diagnostic)] #[diag("lifetime mismatch", code = E0623)] -pub struct LifetimeMismatch<'a> { +pub(crate) struct LifetimeMismatch<'a> { #[primary_span] pub span: Span, #[subdiagnostic] @@ -771,7 +762,7 @@ pub struct LifetimeMismatch<'a> { pub suggestion: AddLifetimeParamsSuggestion<'a>, } -pub struct IntroducesStaticBecauseUnmetLifetimeReq { +pub(crate) struct IntroducesStaticBecauseUnmetLifetimeReq { pub unmet_requirements: MultiSpan, pub binding_span: Span, } @@ -791,7 +782,7 @@ fn add_to_diag(mut self, diag: &mut Diag<'_, G>) { // FIXME(#100717): replace with a `Option` when subdiagnostic supports that #[derive(Subdiagnostic)] -pub enum DoesNotOutliveStaticFromImpl { +pub(crate) enum DoesNotOutliveStaticFromImpl { #[note( "...does not necessarily outlive the static lifetime introduced by the compatible `impl`" )] @@ -806,7 +797,7 @@ pub enum DoesNotOutliveStaticFromImpl { } #[derive(Subdiagnostic)] -pub enum ImplicitStaticLifetimeSubdiag { +pub(crate) enum ImplicitStaticLifetimeSubdiag { #[note("this has an implicit `'static` lifetime requirement")] Note { #[primary_span] @@ -826,7 +817,7 @@ pub enum ImplicitStaticLifetimeSubdiag { #[derive(Diagnostic)] #[diag("incompatible lifetime on type")] -pub struct MismatchedStaticLifetime<'a> { +pub(crate) struct MismatchedStaticLifetime<'a> { #[primary_span] pub cause_span: Span, #[subdiagnostic] @@ -840,7 +831,7 @@ pub struct MismatchedStaticLifetime<'a> { } #[derive(Diagnostic)] -pub enum ExplicitLifetimeRequired<'a> { +pub(crate) enum ExplicitLifetimeRequired<'a> { #[diag("explicit lifetime required in the type of `{$simple_ident}`", code = E0621)] WithIdent { #[primary_span] @@ -876,7 +867,7 @@ pub enum ExplicitLifetimeRequired<'a> { }, } -pub enum TyOrSig<'tcx> { +pub(crate) enum TyOrSig<'tcx> { Ty(Highlighted<'tcx, Ty<'tcx>>), ClosureSig(Highlighted<'tcx, Binder<'tcx, FnSig<'tcx>>>), } @@ -891,7 +882,7 @@ fn into_diag_arg(self, path: &mut Option) -> rustc_errors::D } #[derive(Subdiagnostic)] -pub enum ActualImplExplNotes<'tcx> { +pub(crate) enum ActualImplExplNotes<'tcx> { #[note("{$leading_ellipsis -> [true] ... *[false] {\"\"} @@ -1059,13 +1050,13 @@ pub enum ActualImplExplNotes<'tcx> { }, } -pub enum ActualImplExpectedKind { +pub(crate) enum ActualImplExpectedKind { Signature, Passive, Other, } -pub enum ActualImplExpectedLifetimeKind { +pub(crate) enum ActualImplExpectedLifetimeKind { Two, Any, Some, @@ -1073,7 +1064,7 @@ pub enum ActualImplExpectedLifetimeKind { } impl<'tcx> ActualImplExplNotes<'tcx> { - pub fn new_expected( + pub(crate) fn new_expected( kind: ActualImplExpectedKind, lt_kind: ActualImplExpectedLifetimeKind, leading_ellipsis: bool, @@ -1143,7 +1134,7 @@ pub fn new_expected( #[derive(Diagnostic)] #[diag("implementation of `{$trait_def_id}` is not general enough")] -pub struct TraitPlaceholderMismatch<'tcx> { +pub(crate) struct TraitPlaceholderMismatch<'tcx> { #[primary_span] pub span: Span, #[label("doesn't satisfy where-clause")] @@ -1159,7 +1150,7 @@ pub struct TraitPlaceholderMismatch<'tcx> { pub actual_impl_expl_notes: Vec>, } -pub struct ConsiderBorrowingParamHelp { +pub(crate) struct ConsiderBorrowingParamHelp { pub spans: Vec, } @@ -1180,7 +1171,7 @@ fn add_to_diag(self, diag: &mut Diag<'_, G>) { #[derive(Diagnostic)] #[diag("`impl` item signature doesn't match `trait` item signature")] -pub struct TraitImplDiff { +pub(crate) struct TraitImplDiff { #[primary_span] #[label("found `{$found}`")] pub sp: Span, @@ -1201,60 +1192,6 @@ pub struct TraitImplDiff { pub found: String, } -pub struct DynTraitConstraintSuggestion { - pub span: Span, - pub ident: Ident, -} - -impl Subdiagnostic for DynTraitConstraintSuggestion { - fn add_to_diag(self, diag: &mut Diag<'_, G>) { - let mut multi_span: MultiSpan = vec![self.span].into(); - multi_span.push_span_label( - self.span, - msg!("this has an implicit `'static` lifetime requirement"), - ); - multi_span.push_span_label( - self.ident.span, - msg!("calling this method introduces the `impl`'s `'static` requirement"), - ); - let msg = msg!("the used `impl` has a `'static` requirement"); - diag.span_note(multi_span, msg); - let msg = msg!("consider relaxing the implicit `'static` requirement"); - diag.span_suggestion_verbose( - self.span.shrink_to_hi(), - msg, - " + '_", - Applicability::MaybeIncorrect, - ); - } -} - -pub struct ReqIntroducedLocations { - pub span: MultiSpan, - pub spans: Vec, - pub fn_decl_span: Span, - pub cause_span: Span, - pub add_label: bool, -} - -impl Subdiagnostic for ReqIntroducedLocations { - fn add_to_diag(mut self, diag: &mut Diag<'_, G>) { - for sp in self.spans { - self.span.push_span_label(sp, msg!("`'static` requirement introduced here")); - } - - if self.add_label { - self.span.push_span_label( - self.fn_decl_span, - msg!("requirement introduced by this return type"), - ); - } - self.span.push_span_label(self.cause_span, msg!("because of this returned expression")); - let msg = msg!("\"`'static` lifetime requirement introduced by the return type"); - diag.span_note(self.span, msg); - } -} - #[derive(Diagnostic)] #[diag("{$has_param_name -> [true] `{$param_name}` @@ -1263,7 +1200,7 @@ fn add_to_diag(mut self, diag: &mut Diag<'_, G>) { [true] lifetime `{$lifetime}` *[false] an anonymous lifetime `'_` } but it needs to satisfy a `'static` lifetime requirement", code = E0759)] -pub struct ButNeedsToSatisfy { +pub(crate) struct ButNeedsToSatisfy { #[primary_span] pub sp: Span, #[label( @@ -1301,7 +1238,7 @@ pub struct ButNeedsToSatisfy { #[derive(Diagnostic)] #[diag("lifetime of reference outlives lifetime of borrowed content...", code = E0312)] -pub struct OutlivesContent<'a> { +pub(crate) struct OutlivesContent<'a> { #[primary_span] pub span: Span, #[subdiagnostic] @@ -1310,7 +1247,7 @@ pub struct OutlivesContent<'a> { #[derive(Diagnostic)] #[diag("lifetime of the source pointer does not outlive lifetime bound of the object type", code = E0476)] -pub struct OutlivesBound<'a> { +pub(crate) struct OutlivesBound<'a> { #[primary_span] pub span: Span, #[subdiagnostic] @@ -1319,7 +1256,7 @@ pub struct OutlivesBound<'a> { #[derive(Diagnostic)] #[diag("the type `{$ty}` does not fulfill the required lifetime", code = E0477)] -pub struct FulfillReqLifetime<'a> { +pub(crate) struct FulfillReqLifetime<'a> { #[primary_span] pub span: Span, pub ty: Ty<'a>, @@ -1329,7 +1266,7 @@ pub struct FulfillReqLifetime<'a> { #[derive(Diagnostic)] #[diag("lifetime bound not satisfied", code = E0478)] -pub struct LfBoundNotSatisfied<'a> { +pub(crate) struct LfBoundNotSatisfied<'a> { #[primary_span] pub span: Span, #[subdiagnostic] @@ -1338,7 +1275,7 @@ pub struct LfBoundNotSatisfied<'a> { #[derive(Diagnostic)] #[diag("in type `{$ty}`, reference has a longer lifetime than the data it references", code = E0491)] -pub struct RefLongerThanData<'a> { +pub(crate) struct RefLongerThanData<'a> { #[primary_span] pub span: Span, pub ty: Ty<'a>, @@ -1347,7 +1284,7 @@ pub struct RefLongerThanData<'a> { } #[derive(Subdiagnostic)] -pub enum WhereClauseSuggestions { +pub(crate) enum WhereClauseSuggestions { #[suggestion( "remove the `where` clause", code = "", @@ -1373,7 +1310,7 @@ pub enum WhereClauseSuggestions { } #[derive(Subdiagnostic)] -pub enum SuggestRemoveSemiOrReturnBinding { +pub(crate) enum SuggestRemoveSemiOrReturnBinding { #[multipart_suggestion( "consider removing this semicolon and boxing the expressions", applicability = "machine-applicable" @@ -1420,7 +1357,7 @@ pub enum SuggestRemoveSemiOrReturnBinding { } #[derive(Subdiagnostic)] -pub enum ConsiderAddingAwait { +pub(crate) enum ConsiderAddingAwait { #[help("consider `await`ing on both `Future`s")] BothFuturesHelp, #[multipart_suggestion( @@ -1460,7 +1397,7 @@ pub enum ConsiderAddingAwait { } #[derive(Diagnostic)] -pub enum PlaceholderRelationLfNotSatisfied { +pub(crate) enum PlaceholderRelationLfNotSatisfied { #[diag("lifetime bound not satisfied")] HasBoth { #[primary_span] @@ -1530,7 +1467,7 @@ pub enum PlaceholderRelationLfNotSatisfied { #[derive(Diagnostic)] #[diag("hidden type for `{$opaque_ty}` captures lifetime that does not appear in bounds", code = E0700)] -pub struct OpaqueCapturesLifetime<'tcx> { +pub(crate) struct OpaqueCapturesLifetime<'tcx> { #[primary_span] pub span: Span, #[label("opaque type defined here")] @@ -1539,7 +1476,7 @@ pub struct OpaqueCapturesLifetime<'tcx> { } #[derive(Subdiagnostic)] -pub enum FunctionPointerSuggestion<'a> { +pub(crate) enum FunctionPointerSuggestion<'a> { #[suggestion( "consider using a reference", code = "&", @@ -1620,26 +1557,26 @@ pub enum FunctionPointerSuggestion<'a> { #[derive(Subdiagnostic)] #[note("fn items are distinct from fn pointers")] -pub struct FnItemsAreDistinct; +pub(crate) struct FnItemsAreDistinct; #[derive(Subdiagnostic)] #[note("different fn items have unique types, even if their signatures are the same")] -pub struct FnUniqTypes; +pub(crate) struct FnUniqTypes; #[derive(Subdiagnostic)] #[help("consider casting the fn item to a fn pointer: `{$casting}`")] -pub struct FnConsiderCasting { +pub(crate) struct FnConsiderCasting { pub casting: String, } #[derive(Subdiagnostic)] #[help("consider casting both fn items to fn pointers using `as {$sig}`")] -pub struct FnConsiderCastingBoth<'a> { +pub(crate) struct FnConsiderCastingBoth<'a> { pub sig: Binder<'a, FnSig<'a>>, } #[derive(Subdiagnostic)] -pub enum SuggestAccessingField<'a> { +pub(crate) enum SuggestAccessingField<'a> { #[suggestion( "you might have meant to use field `{$name}` whose type is `{$ty}`", code = "{snippet}.{name}", @@ -1673,7 +1610,7 @@ pub enum SuggestAccessingField<'a> { "try wrapping the pattern in `{$variant}`", applicability = "maybe-incorrect" )] -pub struct SuggestTuplePatternOne { +pub(crate) struct SuggestTuplePatternOne { pub variant: String, #[suggestion_part(code = "{variant}(")] pub span_low: Span, @@ -1681,7 +1618,7 @@ pub struct SuggestTuplePatternOne { pub span_high: Span, } -pub struct SuggestTuplePatternMany { +pub(crate) struct SuggestTuplePatternMany { pub path: String, pub cause_span: Span, pub compatible_variants: Vec, @@ -1899,7 +1836,7 @@ pub enum ObligationCauseFailureCode { } #[derive(Subdiagnostic)] -pub enum AddPreciseCapturing { +pub(crate) enum AddPreciseCapturing { #[suggestion( "add a `use<...>` bound to explicitly capture `{$new_lifetime}`", style = "verbose", @@ -1927,7 +1864,7 @@ pub enum AddPreciseCapturing { }, } -pub struct AddPreciseCapturingAndParams { +pub(crate) struct AddPreciseCapturingAndParams { pub suggs: Vec<(Span, String)>, pub new_lifetime: Symbol, pub apit_spans: Vec, diff --git a/compiler/rustc_trait_selection/src/errors/note_and_explain.rs b/compiler/rustc_trait_selection/src/errors/note_and_explain.rs index fd943bff3700..07b8adb898aa 100644 --- a/compiler/rustc_trait_selection/src/errors/note_and_explain.rs +++ b/compiler/rustc_trait_selection/src/errors/note_and_explain.rs @@ -83,7 +83,7 @@ fn new<'tcx>( } } -pub enum PrefixKind { +pub(crate) enum PrefixKind { Empty, RefValidFor, ContentValidFor, @@ -99,7 +99,7 @@ pub enum PrefixKind { DataValidFor, } -pub enum SuffixKind { +pub(crate) enum SuffixKind { Empty, Continues, ReqByBinding, @@ -139,14 +139,14 @@ fn into_diag_arg(self, _: &mut Option) -> rustc_errors::Diag } } -pub struct RegionExplanation<'a> { +pub(crate) struct RegionExplanation<'a> { desc: DescriptionCtx<'a>, prefix: PrefixKind, suffix: SuffixKind, } impl RegionExplanation<'_> { - pub fn new<'tcx>( + pub(crate) fn new<'tcx>( tcx: TyCtxt<'tcx>, generic_param_scope: LocalDefId, region: ty::Region<'tcx>, diff --git a/compiler/rustc_trait_selection/src/solve/delegate.rs b/compiler/rustc_trait_selection/src/solve/delegate.rs index 62572694de32..05ecc4725a7b 100644 --- a/compiler/rustc_trait_selection/src/solve/delegate.rs +++ b/compiler/rustc_trait_selection/src/solve/delegate.rs @@ -204,7 +204,7 @@ fn well_formed_goals( .map(|obligations| obligations.into_iter().map(|obligation| obligation.as_goal()).collect()) } - fn make_deduplicated_outlives_constraints(&self) -> Vec> { + fn make_deduplicated_region_constraints(&self) -> Vec> { // Cannot use `take_registered_region_obligations` as we may compute the response // inside of a `probe` whenever we have multiple choices inside of the solver. let region_obligations = self.0.inner.borrow().region_obligations().to_owned(); @@ -219,7 +219,7 @@ fn make_deduplicated_outlives_constraints(&self) -> Vec) { // we get all obligations involved in the overflow. We pretty much check: if // we were to do another step of `try_evaluate_obligations`, which goals would // change. - // FIXME: is merged, this can be removed. self.overflowed.extend( - ExtractIf::new(&mut self.pending, |(o, stalled_on)| { - let goal = o.as_goal(); - let result = <&SolverDelegate<'tcx>>::from(infcx).evaluate_root_goal( - goal, - o.cause.span, - stalled_on.take(), - ); - matches!(result, Ok(GoalEvaluation { has_changed: HasChanged::Yes, .. })) - }) - .map(|(o, _)| o), + self.pending + .extract_if(.., |(o, stalled_on)| { + let goal = o.as_goal(); + let result = <&SolverDelegate<'tcx>>::from(infcx).evaluate_root_goal( + goal, + o.cause.span, + stalled_on.take(), + ); + matches!(result, Ok(GoalEvaluation { has_changed: HasChanged::Yes, .. })) + }) + .map(|(o, _)| o), ); }) } diff --git a/compiler/rustc_trait_selection/src/traits/auto_trait.rs b/compiler/rustc_trait_selection/src/traits/auto_trait.rs index a21ff44f40f3..f28e6f32b5f8 100644 --- a/compiler/rustc_trait_selection/src/traits/auto_trait.rs +++ b/compiler/rustc_trait_selection/src/traits/auto_trait.rs @@ -453,7 +453,7 @@ fn map_vid_to_region<'cx>( let mut vid_map = FxIndexMap::, RegionDeps<'cx>>::default(); let mut finished_map = FxIndexMap::default(); - for (c, _) in ®ions.constraints { + for c in regions.constraints.iter().flat_map(|(c, _)| c.iter_outlives()) { match c.kind { ConstraintKind::VarSubVar => { let sub_vid = c.sub.as_var(); @@ -489,6 +489,10 @@ fn map_vid_to_region<'cx>( let deps2 = vid_map.entry(RegionTarget::Region(c.sup)).or_default(); deps2.smaller.insert(RegionTarget::Region(c.sub)); } + + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!() + } } } diff --git a/compiler/rustc_trait_selection/src/traits/dyn_compatibility.rs b/compiler/rustc_trait_selection/src/traits/dyn_compatibility.rs index 1ca0aa3bab19..254760c1d5f0 100644 --- a/compiler/rustc_trait_selection/src/traits/dyn_compatibility.rs +++ b/compiler/rustc_trait_selection/src/traits/dyn_compatibility.rs @@ -465,7 +465,7 @@ fn virtual_call_violations_for_method<'tcx>( if let Some(error) = contains_illegal_impl_trait_in_trait(tcx, method.def_id, sig.output()) { errors.push(error); } - if sig.skip_binder().c_variadic { + if sig.skip_binder().c_variadic() { errors.push(MethodViolation::CVariadic); } diff --git a/compiler/rustc_trait_selection/src/traits/effects.rs b/compiler/rustc_trait_selection/src/traits/effects.rs index 45e0b5d74af7..9959c92a6f89 100644 --- a/compiler/rustc_trait_selection/src/traits/effects.rs +++ b/compiler/rustc_trait_selection/src/traits/effects.rs @@ -8,7 +8,7 @@ use rustc_middle::traits::query::NoSolution; use rustc_middle::ty::elaborate::elaborate; use rustc_middle::ty::fast_reject::DeepRejectCtxt; -use rustc_middle::ty::{self, Ty, TypingMode}; +use rustc_middle::ty::{self, Ty}; use thin_vec::{ThinVec, thin_vec}; use super::SelectionContext; @@ -25,7 +25,7 @@ pub fn evaluate_host_effect_obligation<'tcx>( selcx: &mut SelectionContext<'_, 'tcx>, obligation: &HostEffectObligation<'tcx>, ) -> Result>, EvaluationFailure> { - if selcx.infcx.typing_mode() == TypingMode::Coherence { + if selcx.infcx.typing_mode().is_coherence() { span_bug!( obligation.cause.span, "should not select host obligation in old solver in intercrate mode" diff --git a/compiler/rustc_trait_selection/src/traits/fulfill.rs b/compiler/rustc_trait_selection/src/traits/fulfill.rs index a575630a0503..2dbeff4a5050 100644 --- a/compiler/rustc_trait_selection/src/traits/fulfill.rs +++ b/compiler/rustc_trait_selection/src/traits/fulfill.rs @@ -841,8 +841,7 @@ fn process_trait_obligation( stalled_on: &mut Vec, ) -> ProcessResult, FulfillmentErrorCode<'tcx>> { let infcx = self.selcx.infcx; - if obligation.predicate.is_global() && !matches!(infcx.typing_mode(), TypingMode::Coherence) - { + if obligation.predicate.is_global() && !infcx.typing_mode().is_coherence() { // no type variables present, can use evaluation for better caching. // FIXME: consider caching errors too. if infcx.predicate_must_hold_considering_regions(obligation) { @@ -896,8 +895,7 @@ fn process_projection_obligation( ) -> ProcessResult, FulfillmentErrorCode<'tcx>> { let tcx = self.selcx.tcx(); let infcx = self.selcx.infcx; - if obligation.predicate.is_global() && !matches!(infcx.typing_mode(), TypingMode::Coherence) - { + if obligation.predicate.is_global() && !infcx.typing_mode().is_coherence() { // no type variables present, can use evaluation for better caching. // FIXME: consider caching errors too. if infcx.predicate_must_hold_considering_regions(obligation) { diff --git a/compiler/rustc_trait_selection/src/traits/mod.rs b/compiler/rustc_trait_selection/src/traits/mod.rs index 94ce7631b3c8..89a6132b0dc7 100644 --- a/compiler/rustc_trait_selection/src/traits/mod.rs +++ b/compiler/rustc_trait_selection/src/traits/mod.rs @@ -34,8 +34,8 @@ use rustc_middle::span_bug; use rustc_middle::ty::error::{ExpectedFound, TypeError}; use rustc_middle::ty::{ - self, GenericArgs, GenericArgsRef, Ty, TyCtxt, TypeFoldable, TypeFolder, TypeSuperFoldable, - TypeSuperVisitable, TypeVisitable, TypeVisitableExt, TypingMode, Upcast, + self, Clause, GenericArgs, GenericArgsRef, Ty, TyCtxt, TypeFoldable, TypeFolder, + TypeSuperFoldable, TypeSuperVisitable, TypeVisitable, TypeVisitableExt, TypingMode, Upcast, }; use rustc_span::Span; use rustc_span::def_id::DefId; @@ -177,9 +177,10 @@ pub enum TraitQueryMode { } /// Creates predicate obligations from the generic bounds. -#[instrument(level = "debug", skip(cause, param_env))] +#[instrument(level = "debug", skip(cause, param_env, normalize_predicate))] pub fn predicates_for_generics<'tcx>( cause: impl Fn(usize, Span) -> ObligationCause<'tcx>, + mut normalize_predicate: impl FnMut(Clause<'tcx>) -> Clause<'tcx>, param_env: ty::ParamEnv<'tcx>, generic_bounds: ty::InstantiatedPredicates<'tcx>, ) -> impl Iterator> { @@ -187,7 +188,7 @@ pub fn predicates_for_generics<'tcx>( cause: cause(idx, span), recursion_depth: 0, param_env, - predicate: clause.as_predicate(), + predicate: normalize_predicate(clause).as_predicate(), }) } diff --git a/compiler/rustc_trait_selection/src/traits/outlives_bounds.rs b/compiler/rustc_trait_selection/src/traits/outlives_bounds.rs index 53518038f8d5..8bbdc9d76c51 100644 --- a/compiler/rustc_trait_selection/src/traits/outlives_bounds.rs +++ b/compiler/rustc_trait_selection/src/traits/outlives_bounds.rs @@ -81,10 +81,17 @@ fn implied_outlives_bounds<'a, 'tcx>( // FIXME(higher_ranked_auto): Should we register assumptions here? // We otherwise would get spurious errors if normalizing an implied // outlives bound required proving some higher-ranked coroutine obl. - let QueryRegionConstraints { outlives, assumptions: _ } = constraints; + let QueryRegionConstraints { constraints, assumptions: _ } = constraints; let cause = ObligationCause::misc(span, body_id); - for &(predicate, _) in &outlives { - infcx.register_outlives_constraint(predicate, &cause); + for &(constraint, _) in &constraints { + match constraint { + ty::RegionConstraint::Outlives(predicate) => { + infcx.register_outlives_constraint(predicate, &cause) + } + ty::RegionConstraint::Eq(predicate) => { + infcx.register_region_eq_constraint(predicate, &cause) + } + } } }; diff --git a/compiler/rustc_trait_selection/src/traits/project.rs b/compiler/rustc_trait_selection/src/traits/project.rs index 72d3ba9629f4..a318d5961279 100644 --- a/compiler/rustc_trait_selection/src/traits/project.rs +++ b/compiler/rustc_trait_selection/src/traits/project.rs @@ -1655,13 +1655,8 @@ fn confirm_closure_candidate<'cx, 'tcx>( tupled_upvars_ty, ) }; - tcx.mk_fn_sig( - [sig.tupled_inputs_ty], - output_ty, - sig.c_variadic, - sig.safety, - sig.abi, - ) + + tcx.mk_fn_sig([sig.tupled_inputs_ty], output_ty, sig.fn_sig_kind) }) } diff --git a/compiler/rustc_trait_selection/src/traits/query/normalize.rs b/compiler/rustc_trait_selection/src/traits/query/normalize.rs index a08838414629..216df6ba82cf 100644 --- a/compiler/rustc_trait_selection/src/traits/query/normalize.rs +++ b/compiler/rustc_trait_selection/src/traits/query/normalize.rs @@ -211,7 +211,7 @@ fn try_fold_ty(&mut self, ty: Ty<'tcx>) -> Result, Self::Error> { // See note in `rustc_trait_selection::traits::project` about why we // wait to fold the args. let res = match data.kind { - ty::Opaque { .. } => { + ty::Opaque { def_id } => { // Only normalize `impl Trait` outside of type inference, usually in codegen. match self.infcx.typing_mode() { TypingMode::Coherence @@ -236,7 +236,7 @@ fn try_fold_ty(&mut self, ty: Ty<'tcx>) -> Result, Self::Error> { return Ok(Ty::new_error(self.cx(), guar)); } - let generic_ty = self.cx().type_of(data.kind.def_id()); + let generic_ty = self.cx().type_of(def_id); let mut concrete_ty = generic_ty.instantiate(self.cx(), args); self.anon_depth += 1; if concrete_ty == ty { diff --git a/compiler/rustc_trait_selection/src/traits/query/type_op/mod.rs b/compiler/rustc_trait_selection/src/traits/query/type_op/mod.rs index 4b8bf8681231..ea062db3128a 100644 --- a/compiler/rustc_trait_selection/src/traits/query/type_op/mod.rs +++ b/compiler/rustc_trait_selection/src/traits/query/type_op/mod.rs @@ -180,8 +180,8 @@ fn fully_perform( Ok(output) })?; output.error_info = error_info; - if let Some(QueryRegionConstraints { outlives, assumptions }) = output.constraints { - region_constraints.outlives.extend(outlives.iter().cloned()); + if let Some(QueryRegionConstraints { constraints, assumptions }) = output.constraints { + region_constraints.constraints.extend(constraints.iter().cloned()); region_constraints.assumptions.extend(assumptions.iter().cloned()); } output.constraints = if region_constraints.is_empty() { diff --git a/compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs b/compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs index ab8e1354b6b3..f7614e7c9730 100644 --- a/compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs +++ b/compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs @@ -15,7 +15,7 @@ use rustc_infer::traits::{Obligation, PolyTraitObligation, PredicateObligation, SelectionError}; use rustc_middle::ty::fast_reject::DeepRejectCtxt; use rustc_middle::ty::{ - self, FieldInfo, SizedTraitKind, TraitRef, Ty, TypeVisitableExt, TypingMode, elaborate, + self, FieldInfo, SizedTraitKind, TraitRef, Ty, TypeVisitableExt, elaborate, }; use rustc_middle::{bug, span_bug}; use rustc_span::DUMMY_SP; @@ -849,7 +849,7 @@ fn assemble_candidates_from_auto_impls( // // Note that this is only sound as projection candidates of opaque types // are always applicable for auto traits. - } else if let TypingMode::Coherence = self.infcx.typing_mode() { + } else if self.infcx.typing_mode().is_coherence() { // We do not emit auto trait candidates for opaque types in coherence. // Doing so can result in weird dependency cycles. candidates.ambiguous = true; diff --git a/compiler/rustc_trait_selection/src/traits/select/mod.rs b/compiler/rustc_trait_selection/src/traits/select/mod.rs index 527353bed5ad..a564e8060d93 100644 --- a/compiler/rustc_trait_selection/src/traits/select/mod.rs +++ b/compiler/rustc_trait_selection/src/traits/select/mod.rs @@ -3,9 +3,9 @@ //! [rustc dev guide]: https://rustc-dev-guide.rust-lang.org/traits/resolution.html#selection use std::cell::{Cell, RefCell}; +use std::cmp; use std::fmt::{self, Display}; use std::ops::ControlFlow; -use std::{assert_matches, cmp}; use hir::def::DefKind; use rustc_data_structures::fx::{FxIndexMap, FxIndexSet}; @@ -210,8 +210,9 @@ pub fn with_query_mode( /// Enables tracking of intercrate ambiguity causes. See /// the documentation of [`Self::intercrate_ambiguity_causes`] for more. pub fn enable_tracking_intercrate_ambiguity_causes(&mut self) { - assert_matches!(self.infcx.typing_mode(), TypingMode::Coherence); + assert!(self.infcx.typing_mode().is_coherence()); assert!(self.intercrate_ambiguity_causes.is_none()); + self.intercrate_ambiguity_causes = Some(FxIndexSet::default()); debug!("selcx: enable_tracking_intercrate_ambiguity_causes"); } @@ -222,7 +223,8 @@ pub fn enable_tracking_intercrate_ambiguity_causes(&mut self) { pub fn take_intercrate_ambiguity_causes( &mut self, ) -> FxIndexSet> { - assert_matches!(self.infcx.typing_mode(), TypingMode::Coherence); + assert!(self.infcx.typing_mode().is_coherence()); + self.intercrate_ambiguity_causes.take().unwrap_or_default() } @@ -1016,7 +1018,7 @@ fn evaluate_trait_predicate_recursively<'o>( previous_stack: TraitObligationStackList<'o, 'tcx>, mut obligation: PolyTraitObligation<'tcx>, ) -> Result { - if !matches!(self.infcx.typing_mode(), TypingMode::Coherence) + if !self.infcx.typing_mode().is_coherence() && obligation.is_global() && obligation.param_env.caller_bounds().iter().all(|bound| bound.has_param()) { @@ -2548,7 +2550,7 @@ fn match_impl( nested_obligations.extend(obligations); if impl_trait_header.polarity == ty::ImplPolarity::Reservation - && !matches!(self.infcx.typing_mode(), TypingMode::Coherence) + && !self.infcx.typing_mode().is_coherence() { debug!("reservation impls only apply in intercrate mode"); return Err(()); diff --git a/compiler/rustc_trait_selection/src/traits/specialize/mod.rs b/compiler/rustc_trait_selection/src/traits/specialize/mod.rs index fa9d617604e5..d6dcb97562d0 100644 --- a/compiler/rustc_trait_selection/src/traits/specialize/mod.rs +++ b/compiler/rustc_trait_selection/src/traits/specialize/mod.rs @@ -185,12 +185,13 @@ fn fulfill_implication<'tcx>( // Now check that the source trait ref satisfies all the where clauses of the target impl. // This is not just for correctness; we also need this to constrain any params that may // only be referenced via projection predicates. - let predicates = ocx.normalize( - cause, + let predicates = infcx.tcx.predicates_of(target_impl).instantiate(infcx.tcx, target_args); + let obligations = predicates_for_generics( + |_, _| cause.clone(), + |pred| ocx.normalize(cause, param_env, pred), param_env, - infcx.tcx.predicates_of(target_impl).instantiate(infcx.tcx, target_args), + predicates, ); - let obligations = predicates_for_generics(|_, _| cause.clone(), param_env, predicates); ocx.register_obligations(obligations); let errors = ocx.evaluate_obligations_error_on_ambiguity(); @@ -315,12 +316,14 @@ pub(super) fn specializes( // Now check that the source trait ref satisfies all the where clauses of the target impl. // This is not just for correctness; we also need this to constrain any params that may // only be referenced via projection predicates. - let predicates = ocx.normalize( - cause, + let predicates = + infcx.tcx.predicates_of(parent_impl_def_id).instantiate(infcx.tcx, parent_args); + let obligations = predicates_for_generics( + |_, _| cause.clone(), + |pred| ocx.normalize(cause, param_env, pred), param_env, - infcx.tcx.predicates_of(parent_impl_def_id).instantiate(infcx.tcx, parent_args), + predicates, ); - let obligations = predicates_for_generics(|_, _| cause.clone(), param_env, predicates); ocx.register_obligations(obligations); let errors = ocx.evaluate_obligations_error_on_ambiguity(); diff --git a/compiler/rustc_traits/src/coroutine_witnesses.rs b/compiler/rustc_traits/src/coroutine_witnesses.rs index 2544cd8a13cd..0dd4ea823c94 100644 --- a/compiler/rustc_traits/src/coroutine_witnesses.rs +++ b/compiler/rustc_traits/src/coroutine_witnesses.rs @@ -69,18 +69,18 @@ fn compute_assumptions<'tcx>( let region_assumptions = infcx.take_registered_region_assumptions(); let region_constraints = infcx.take_and_reset_region_constraints(); - let outlives = make_query_region_constraints( + let constraints = make_query_region_constraints( region_obligations, ®ion_constraints, region_assumptions, ) - .outlives + .constraints .fold_with(&mut OpportunisticRegionResolver::new(&infcx)); tcx.mk_outlives_from_iter( - outlives + constraints .into_iter() - .map(|(o, _)| o) + .flat_map(|(constraint, _)| constraint.iter_outlives()) // FIXME(higher_ranked_auto): We probably should deeply resolve these before // filtering out infers which only correspond to unconstrained infer regions // which we can sometimes get. diff --git a/compiler/rustc_ty_utils/src/abi.rs b/compiler/rustc_ty_utils/src/abi.rs index 5008794bcb19..2962e4b6a4f6 100644 --- a/compiler/rustc_ty_utils/src/abi.rs +++ b/compiler/rustc_ty_utils/src/abi.rs @@ -2,8 +2,8 @@ use rustc_abi::Primitive::Pointer; use rustc_abi::{Align, BackendRepr, ExternAbi, PointerKind, Scalar, Size}; -use rustc_hir as hir; use rustc_hir::lang_items::LangItem; +use rustc_hir::{self as hir, find_attr}; use rustc_middle::bug; use rustc_middle::middle::deduced_param_attrs::DeducedParamAttrs; use rustc_middle::query::Providers; @@ -39,13 +39,7 @@ fn fn_sig_for_fn_abi<'tcx>( typing_env: ty::TypingEnv<'tcx>, ) -> ty::FnSig<'tcx> { if let InstanceKind::ThreadLocalShim(..) = instance.def { - return tcx.mk_fn_sig( - [], - tcx.thread_local_ptr_ty(instance.def_id()), - false, - hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, - ); + return tcx.mk_fn_sig_safe_rust_abi([], tcx.thread_local_ptr_ty(instance.def_id())); } let ty = instance.ty(tcx, typing_env); @@ -74,9 +68,7 @@ fn fn_sig_for_fn_abi<'tcx>( tcx.mk_fn_sig( iter::once(env_ty).chain(sig.inputs().iter().cloned()), sig.output(), - sig.c_variadic, - sig.safety, - sig.abi, + sig.fn_sig_kind, ) } ty::CoroutineClosure(def_id, args) => { @@ -119,9 +111,7 @@ fn fn_sig_for_fn_abi<'tcx>( args.as_coroutine_closure().tupled_upvars_ty(), args.as_coroutine_closure().coroutine_captures_by_ref_ty(), ), - sig.c_variadic, - sig.safety, - sig.abi, + sig.fn_sig_kind, ) } ty::Coroutine(did, args) => { @@ -224,22 +214,10 @@ fn fn_sig_for_fn_abi<'tcx>( }; if let Some(resume_ty) = resume_ty { - tcx.mk_fn_sig( - [env_ty, resume_ty], - ret_ty, - false, - hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, - ) + tcx.mk_fn_sig_safe_rust_abi([env_ty, resume_ty], ret_ty) } else { // `Iterator::next` doesn't have a `resume` argument. - tcx.mk_fn_sig( - [env_ty], - ret_ty, - false, - hir::Safety::Safe, - rustc_abi::ExternAbi::Rust, - ) + tcx.mk_fn_sig_safe_rust_abi([env_ty], ret_ty) } } _ => bug!("unexpected type {:?} in Instance::fn_sig", ty), @@ -334,7 +312,7 @@ fn fn_abi_of_instance_raw<'tcx>( // If the function's body can be used to deduce parameter attributes, then adjust such // "no deduced attrs" ABI; otherwise, return that ABI unadjusted. params.determined_fn_def_id.map_or(fn_abi, |fn_def_id| { - fn_abi_adjust_for_deduced_attrs(¶ms.layout_cx, fn_abi, params.sig.abi, fn_def_id) + fn_abi_adjust_for_deduced_attrs(¶ms.layout_cx, fn_abi, params.sig.abi(), fn_def_id) }) }) } @@ -355,6 +333,7 @@ fn arg_attrs_for_rust_scalar<'tcx>( offset: Size, is_return: bool, drop_target_pointee: Option>, + determined_fn_def_id: Option, ) -> ArgAttributes { let mut attrs = ArgAttributes::new(); @@ -432,6 +411,21 @@ fn arg_attrs_for_rust_scalar<'tcx>( attrs.set(ArgAttribute::NoAlias); } + // Set writable if no_alias is set, it's a mutable reference and the feature is enabled. + if tcx.sess.opts.unstable_opts.llvm_writable + && matches!(kind, PointerKind::MutableRef { unpin: true }) + && !is_return + { + let rustc_no_writable = match determined_fn_def_id { + Some(def_id) => find_attr!(tcx, def_id, RustcNoWritable), + None => true, // If no def_id exists, we make the conservative choice and disable the feature. + }; + + if !rustc_no_writable { + attrs.set(ArgAttribute::Writable); + } + } + if matches!(kind, PointerKind::SharedRef { frozen: true }) && !is_return { attrs.set(ArgAttribute::ReadOnly); attrs.set(ArgAttribute::CapturesReadOnly); @@ -567,11 +561,11 @@ fn fn_abi_new_uncached<'tcx>( let tcx = cx.tcx(); let abi_map = AbiMap::from_target(&tcx.sess.target); - let conv = abi_map.canonize_abi(sig.abi, sig.c_variadic).unwrap(); + let conv = abi_map.canonize_abi(sig.abi(), sig.c_variadic()).unwrap(); let mut inputs = sig.inputs(); - let extra_args = if sig.abi == ExternAbi::RustCall { - assert!(!sig.c_variadic && extra_args.is_empty()); + let extra_args = if sig.abi() == ExternAbi::RustCall { + assert!(!sig.c_variadic() && extra_args.is_empty()); if let Some(input) = sig.inputs().last() && let ty::Tuple(tupled_arguments) = input.kind() @@ -585,7 +579,7 @@ fn fn_abi_new_uncached<'tcx>( ); } } else { - assert!(sig.c_variadic || extra_args.is_empty()); + assert!(sig.c_variadic() || extra_args.is_empty()); extra_args }; @@ -624,6 +618,7 @@ fn fn_abi_new_uncached<'tcx>( // Only set `drop_target_pointee` for the data part of a wide pointer. // See `arg_attrs_for_rust_scalar` docs for more information. drop_target_pointee.filter(|_| offset == Size::ZERO), + determined_fn_def_id, ) })) }; @@ -638,7 +633,7 @@ fn fn_abi_new_uncached<'tcx>( .enumerate() .map(|(i, ty)| arg_of(ty, Some(i))) .collect::>()?, - c_variadic: sig.c_variadic, + c_variadic: sig.c_variadic(), fixed_count: inputs.len() as u32, conv, // FIXME return false for tls shim @@ -646,12 +641,12 @@ fn fn_abi_new_uncached<'tcx>( tcx, // Since `#[rustc_nounwind]` can change unwinding, we cannot infer unwinding by `fn_def_id` for a virtual call. determined_fn_def_id, - sig.abi, + sig.abi(), ), }; - fn_abi_adjust_for_abi(cx, &mut fn_abi, sig.abi); + fn_abi_adjust_for_abi(cx, &mut fn_abi, sig.abi()); debug!("fn_abi_new_uncached = {:?}", fn_abi); - fn_abi_sanity_check(cx, &fn_abi, sig.abi); + fn_abi_sanity_check(cx, &fn_abi, sig.abi()); Ok(tcx.arena.alloc(fn_abi)) } diff --git a/compiler/rustc_ty_utils/src/instance.rs b/compiler/rustc_ty_utils/src/instance.rs index cf881961b3ce..e48e525e571d 100644 --- a/compiler/rustc_ty_utils/src/instance.rs +++ b/compiler/rustc_ty_utils/src/instance.rs @@ -154,7 +154,7 @@ fn resolve_associated_item<'tcx>( // and the obligation is monomorphic, otherwise passes such as // transmute checking and polymorphic MIR optimizations could // get a result which isn't correct for all monomorphizations. - match typing_env.typing_mode { + match typing_env.typing_mode() { ty::TypingMode::Coherence | ty::TypingMode::Analysis { .. } | ty::TypingMode::Borrowck { .. } diff --git a/compiler/rustc_ty_utils/src/opaque_types.rs b/compiler/rustc_ty_utils/src/opaque_types.rs index b5fa54d42ffb..37db892ce2e9 100644 --- a/compiler/rustc_ty_utils/src/opaque_types.rs +++ b/compiler/rustc_ty_utils/src/opaque_types.rs @@ -92,12 +92,14 @@ fn visit_nested_body(&mut self, id: rustc_hir::BodyId) { #[instrument(level = "debug", skip(self))] fn visit_opaque_ty(&mut self, alias_ty: ty::AliasTy<'tcx>) { - if !self.seen.insert(alias_ty.kind.def_id().expect_local()) { + let ty::Opaque { def_id } = alias_ty.kind else { bug!("{alias_ty:?}") }; + + if !self.seen.insert(def_id.expect_local()) { return; } // TAITs outside their defining scopes are ignored. - match self.tcx.local_opaque_ty_origin(alias_ty.kind.def_id().expect_local()) { + match self.tcx.local_opaque_ty_origin(def_id.expect_local()) { rustc_hir::OpaqueTyOrigin::FnReturn { .. } | rustc_hir::OpaqueTyOrigin::AsyncFn { .. } => {} rustc_hir::OpaqueTyOrigin::TyAlias { in_assoc_ty, .. } => match self.mode { @@ -122,9 +124,9 @@ fn visit_opaque_ty(&mut self, alias_ty: ty::AliasTy<'tcx>) { } trace!(?alias_ty, "adding"); - self.opaques.push(alias_ty.kind.def_id().expect_local()); + self.opaques.push(def_id.expect_local()); - let parent_count = self.tcx.generics_of(alias_ty.kind.def_id()).parent_count; + let parent_count = self.tcx.generics_of(def_id).parent_count; // Only check that the parent generics of the TAIT/RPIT are unique. // the args owned by the opaque are going to always be duplicate // lifetime params for RPITs, and empty for TAITs. @@ -140,9 +142,7 @@ fn visit_opaque_ty(&mut self, alias_ty: ty::AliasTy<'tcx>) { // Collect opaque types nested within the associated type bounds of this opaque type. // We use identity args here, because we already know that the opaque type uses // only generic parameters, and thus instantiating would not give us more information. - for (pred, span) in - self.tcx.explicit_item_bounds(alias_ty.kind.def_id()).iter_identity_copied() - { + for (pred, span) in self.tcx.explicit_item_bounds(def_id).iter_identity_copied() { trace!(?pred); self.visit_spanned(span, pred); } @@ -151,14 +151,14 @@ fn visit_opaque_ty(&mut self, alias_ty: ty::AliasTy<'tcx>) { self.tcx.dcx().emit_err(NotParam { arg, span: self.span(), - opaque_span: self.tcx.def_span(alias_ty.kind.def_id()), + opaque_span: self.tcx.def_span(def_id), }); } Err(NotUniqueParam::DuplicateParam(arg)) => { self.tcx.dcx().emit_err(DuplicateArg { arg, span: self.span(), - opaque_span: self.tcx.def_span(alias_ty.kind.def_id()), + opaque_span: self.tcx.def_span(def_id), }); } } @@ -210,13 +210,13 @@ fn visit_ty(&mut self, t: Ty<'tcx>) { } // Skips type aliases, as they are meant to be transparent. // FIXME(type_alias_impl_trait): can we require mentioning nested type aliases explicitly? - ty::Alias(alias_ty @ ty::AliasTy { kind: ty::Free { def_id }, .. }) + ty::Alias(ty::AliasTy { kind: ty::Free { def_id }, args, .. }) if let Some(def_id) = def_id.as_local() => { if !self.seen.insert(def_id) { return; } - self.tcx.type_of(def_id).instantiate(self.tcx, alias_ty.args).visit_with(self); + self.tcx.type_of(def_id).instantiate(self.tcx, args).visit_with(self); } ty::Alias( alias_ty @ ty::AliasTy { kind: ty::Projection { def_id: alias_def_id }, .. }, diff --git a/compiler/rustc_type_ir/Cargo.toml b/compiler/rustc_type_ir/Cargo.toml index 58fc4d8788b1..7b0b4aa89972 100644 --- a/compiler/rustc_type_ir/Cargo.toml +++ b/compiler/rustc_type_ir/Cargo.toml @@ -20,8 +20,10 @@ rustc_macros = { path = "../rustc_macros", optional = true } rustc_serialize = { path = "../rustc_serialize", optional = true } rustc_span = { path = "../rustc_span", optional = true } rustc_type_ir_macros = { path = "../rustc_type_ir_macros" } -smallvec = { version = "1.8.1", default-features = false, features = ["const_generics"] } -thin-vec = "0.2.12" +smallvec = { version = "1.8.1", default-features = false, features = [ + "const_generics", +] } +thin-vec = "0.2.15" tracing = "0.1" # tidy-alphabetical-end diff --git a/compiler/rustc_type_ir/src/binder.rs b/compiler/rustc_type_ir/src/binder.rs index 0b0f0fd2f424..76140e6a762f 100644 --- a/compiler/rustc_type_ir/src/binder.rs +++ b/compiler/rustc_type_ir/src/binder.rs @@ -956,7 +956,7 @@ pub enum BoundVarIndexKind { /// identified by both a universe, as well as a name residing within that universe. Distinct bound /// regions/types/consts within the same universe simply have an unknown relationship to one #[derive_where(Clone, Copy, PartialOrd, Ord, PartialEq, Eq, Hash; I: Interner, T)] -#[derive(TypeVisitable_Generic, TypeFoldable_Generic)] +#[derive(TypeVisitable_Generic, TypeFoldable_Generic, GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) @@ -995,7 +995,7 @@ fn lift_to_interner(self, cx: U) -> Option { } #[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] -#[derive(Lift_Generic)] +#[derive(Lift_Generic, GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) @@ -1058,7 +1058,7 @@ pub fn get_id(&self) -> Option { } #[derive_where(Clone, Copy, PartialEq, Eq, Debug, Hash; I: Interner)] -#[derive(Lift_Generic)] +#[derive(Lift_Generic, GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) @@ -1069,7 +1069,7 @@ pub enum BoundTyKind { } #[derive_where(Clone, Copy, PartialEq, Eq, Debug, Hash; I: Interner)] -#[derive(Lift_Generic)] +#[derive(Lift_Generic, GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) @@ -1104,6 +1104,7 @@ pub fn expect_const(self) { } #[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] +#[derive(GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, HashStable_NoContext, Decodable_NoContext) @@ -1164,6 +1165,7 @@ pub fn new_anon(ui: UniverseIndex, var: ty::BoundVar) -> Self { } #[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] +#[derive(GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) @@ -1229,6 +1231,7 @@ pub fn new_anon(ui: UniverseIndex, var: ty::BoundVar) -> Self { } #[derive_where(Clone, Copy, PartialEq, Debug, Eq, Hash; I: Interner)] +#[derive(GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) diff --git a/compiler/rustc_type_ir/src/canonical.rs b/compiler/rustc_type_ir/src/canonical.rs index 8e7414674c6e..be5e483c808d 100644 --- a/compiler/rustc_type_ir/src/canonical.rs +++ b/compiler/rustc_type_ir/src/canonical.rs @@ -11,7 +11,7 @@ use crate::data_structures::HashMap; use crate::inherent::*; -use crate::{self as ty, Interner, TypingMode, UniverseIndex}; +use crate::{self as ty, Interner, TypingModeEqWrapper, UniverseIndex}; #[derive_where(Clone, Hash, PartialEq, Debug; I: Interner, V)] #[derive_where(Copy; I: Interner, V: Copy)] @@ -21,7 +21,7 @@ )] pub struct CanonicalQueryInput { pub canonical: Canonical, - pub typing_mode: TypingMode, + pub typing_mode: TypingModeEqWrapper, } impl Eq for CanonicalQueryInput {} diff --git a/compiler/rustc_type_ir/src/const_kind.rs b/compiler/rustc_type_ir/src/const_kind.rs index 2877364762f4..68c87dd0bbeb 100644 --- a/compiler/rustc_type_ir/src/const_kind.rs +++ b/compiler/rustc_type_ir/src/const_kind.rs @@ -141,7 +141,7 @@ fn hash_stable(&self, hcx: &mut Hcx, hasher: &mut StableHasher) { /// `ValTree` does not have this problem with representation, as it only contains integers or /// lists of (nested) `ty::Const`s (which may indirectly contain more `ValTree`s). #[derive_where(Clone, Copy, Debug, Hash, Eq, PartialEq; I: Interner)] -#[derive(TypeVisitable_Generic, TypeFoldable_Generic)] +#[derive(TypeVisitable_Generic, TypeFoldable_Generic, GenericTypeVisitable)] #[cfg_attr( feature = "nightly", derive(Decodable_NoContext, Encodable_NoContext, HashStable_NoContext) diff --git a/compiler/rustc_type_ir/src/generic_visit.rs b/compiler/rustc_type_ir/src/generic_visit.rs index ee55c63ab477..543397ff155b 100644 --- a/compiler/rustc_type_ir/src/generic_visit.rs +++ b/compiler/rustc_type_ir/src/generic_visit.rs @@ -1,45 +1,13 @@ -//! A visiting traversal mechanism for complex data structures that contain type -//! information. +//! Special visiting used by rust-analyzer only. //! -//! This is a read-only traversal of the data structure. +//! It is different from `TypeVisitable` in two ways: //! -//! This traversal has limited flexibility. Only a small number of "types of -//! interest" within the complex data structures can receive custom -//! visitation. These are the ones containing the most important type-related -//! information, such as `Ty`, `Predicate`, `Region`, and `Const`. -//! -//! There are three traits involved in each traversal. -//! - `GenericTypeVisitable`. This is implemented once for many types, including: -//! - Types of interest, for which the methods delegate to the visitor. -//! - All other types, including generic containers like `Vec` and `Option`. -//! It defines a "skeleton" of how they should be visited. -//! - `TypeSuperVisitable`. This is implemented only for recursive types of -//! interest, and defines the visiting "skeleton" for these types. (This -//! excludes `Region` because it is non-recursive, i.e. it never contains -//! other types of interest.) -//! - `CustomizableTypeVisitor`. This is implemented for each visitor. This defines how -//! types of interest are visited. -//! -//! This means each visit is a mixture of (a) generic visiting operations, and (b) -//! custom visit operations that are specific to the visitor. -//! - The `GenericTypeVisitable` impls handle most of the traversal, and call into -//! `CustomizableTypeVisitor` when they encounter a type of interest. -//! - A `CustomizableTypeVisitor` may call into another `GenericTypeVisitable` impl, because some of -//! the types of interest are recursive and can contain other types of interest. -//! - A `CustomizableTypeVisitor` may also call into a `TypeSuperVisitable` impl, because each -//! visitor might provide custom handling only for some types of interest, or -//! only for some variants of each type of interest, and then use default -//! traversal for the remaining cases. -//! -//! For example, if you have `struct S(Ty, U)` where `S: GenericTypeVisitable` and `U: -//! GenericTypeVisitable`, and an instance `s = S(ty, u)`, it would be visited like so: -//! ```text -//! s.generic_visit_with(visitor) calls -//! - ty.generic_visit_with(visitor) calls -//! - visitor.visit_ty(ty) may call -//! - ty.super_generic_visit_with(visitor) -//! - u.generic_visit_with(visitor) -//! ``` +//! - The visitor is a generic of the trait and not the method, allowing types to attach +//! special behavior to visitors (as long as they know it; we don't use this capability +//! in rustc crates, but rust-analyzer needs it). +//! - It **must visit** every field. This is why we don't have an attribute like `#[type_visitable(ignore)]` +//! for this visit. The reason for this is soundness: rust-analyzer uses this visit to +//! garbage collect types, so a missing field can mean a use after free use std::sync::Arc; @@ -53,16 +21,6 @@ /// To implement this conveniently, use the derive macro located in /// `rustc_macros`. pub trait GenericTypeVisitable { - /// The entry point for visiting. To visit a value `t` with a visitor `v` - /// call: `t.generic_visit_with(v)`. - /// - /// For most types, this just traverses the value, calling `generic_visit_with` on - /// each field/element. - /// - /// For types of interest (such as `Ty`), the implementation of this method - /// that calls a visitor method specifically for that type (such as - /// `V::visit_ty`). This is where control transfers from `GenericTypeVisitable` to - /// `CustomizableTypeVisitor`. fn generic_visit_with(&self, visitor: &mut V); } @@ -216,6 +174,10 @@ fn generic_visit_with(&self, _visitor: &mut V) {} }; } +impl GenericTypeVisitable for std::marker::PhantomData { + fn generic_visit_with(&self, _visitor: &mut V) {} +} + trivial_impls!( (), rustc_ast_ir::Mutability, diff --git a/compiler/rustc_type_ir/src/infer_ctxt.rs b/compiler/rustc_type_ir/src/infer_ctxt.rs index feafcee7bad9..905b005cd48f 100644 --- a/compiler/rustc_type_ir/src/infer_ctxt.rs +++ b/compiler/rustc_type_ir/src/infer_ctxt.rs @@ -1,3 +1,5 @@ +use std::hash::{Hash, Hasher}; + use derive_where::derive_where; #[cfg(feature = "nightly")] use rustc_macros::{Decodable_NoContext, Encodable_NoContext, HashStable_NoContext}; @@ -18,11 +20,28 @@ /// /// If neither of these functions are available, feel free to reach out to /// t-types for help. -#[derive_where(Clone, Copy, Hash, PartialEq, Debug; I: Interner)] +/// +/// Because typing rules get subtly different based on what typing mode we're in, +/// subtle enough that changing the behavior of typing modes can sometimes cause +/// changes that we don't even have tests for, we'd like to enforce the rule that +/// any place where we specialize behavior based on the typing mode, we match +/// *exhaustively* on the typing mode. That way, it's easy to determine all the +/// places that must change when anything about typing modes changes. +/// +/// Hence, `TypingMode` does not implement `Eq`, though [`TypingModeEqWrapper`] is available +/// in the rare case that you do need this. Most cases where this currently matters is +/// where we pass typing modes through the query system and want to cache based on it. +/// See also `#[rustc_must_match_exhaustively]`, which tries to detect non-exhaustive +/// matches. +/// +/// Since matching on typing mode to single out `Coherence` is so common, and `Coherence` +/// is so different from the other modes: see also [`is_coherence`](TypingMode::is_coherence) +#[derive_where(Clone, Copy, Hash, Debug; I: Interner)] #[cfg_attr( feature = "nightly", derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) )] +#[cfg_attr(feature = "nightly", rustc_must_match_exhaustively)] pub enum TypingMode { /// When checking whether impls overlap, we check whether any obligations /// are guaranteed to never hold when unifying the impls. This requires us @@ -90,9 +109,71 @@ pub enum TypingMode { PostAnalysis, } -impl Eq for TypingMode {} +/// We want to highly discourage using equality checks on typing modes. +/// Instead you should match, **exhaustively**, so when we ever modify the enum we get a compile +/// error. Only use `TypingModeEqWrapper` when you really really really have to. +/// Prefer unwrapping `TypingModeEqWrapper` in apis that should return a `TypingMode` whenever +/// possible, and if you ever get an `TypingModeEqWrapper`, prefer unwrapping it and matching on it **exhaustively**. +#[derive_where(Clone, Copy, Debug; I: Interner)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub struct TypingModeEqWrapper(pub TypingMode); + +impl Hash for TypingModeEqWrapper { + fn hash(&self, state: &mut H) { + self.0.hash(state); + } +} + +impl PartialEq for TypingModeEqWrapper { + fn eq(&self, other: &Self) -> bool { + match (self.0, other.0) { + (TypingMode::Coherence, TypingMode::Coherence) => true, + ( + TypingMode::Analysis { defining_opaque_types_and_generators: l }, + TypingMode::Analysis { defining_opaque_types_and_generators: r }, + ) => l == r, + ( + TypingMode::Borrowck { defining_opaque_types: l }, + TypingMode::Borrowck { defining_opaque_types: r }, + ) => l == r, + ( + TypingMode::PostBorrowckAnalysis { defined_opaque_types: l }, + TypingMode::PostBorrowckAnalysis { defined_opaque_types: r }, + ) => l == r, + (TypingMode::PostAnalysis, TypingMode::PostAnalysis) => true, + ( + TypingMode::Coherence + | TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } + | TypingMode::PostAnalysis, + _, + ) => false, + } + } +} + +impl Eq for TypingModeEqWrapper {} impl TypingMode { + /// There are a bunch of places in the compiler where we single out `Coherence`, + /// and alter behavior. We'd like to *always* match on `TypingMode` exhaustively, + /// but not having this method leads to a bunch of noisy code. + /// + /// See also the documentation on [`TypingMode`] about exhaustive matching. + pub fn is_coherence(&self) -> bool { + match self { + TypingMode::Coherence => true, + TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } + | TypingMode::PostAnalysis => false, + } + } + /// Analysis outside of a body does not define any opaque types. pub fn non_body_analysis() -> TypingMode { TypingMode::Analysis { defining_opaque_types_and_generators: Default::default() } @@ -322,6 +403,13 @@ pub fn may_use_unstable_feature<'a, I: Interner, Infcx>( // Note: `feature_bound_holds_in_crate` does not consider a feature to be enabled // if we are in std/core even if there is a corresponding `feature` attribute on the crate. - (infcx.typing_mode() == TypingMode::PostAnalysis) - || infcx.cx().features().feature_bound_holds_in_crate(symbol) + match infcx.typing_mode() { + TypingMode::Coherence + | TypingMode::Analysis { .. } + | TypingMode::Borrowck { .. } + | TypingMode::PostBorrowckAnalysis { .. } => { + infcx.cx().features().feature_bound_holds_in_crate(symbol) + } + TypingMode::PostAnalysis => true, + } } diff --git a/compiler/rustc_type_ir/src/inherent.rs b/compiler/rustc_type_ir/src/inherent.rs index e5ca3d2db0dc..cf94dc429895 100644 --- a/compiler/rustc_type_ir/src/inherent.rs +++ b/compiler/rustc_type_ir/src/inherent.rs @@ -203,18 +203,51 @@ pub trait Tys>: fn output(self) -> I::Ty; } +pub trait FSigKind>: Copy + Debug + Hash + Eq { + /// The identity function. + fn fn_sig_kind(self) -> Self; + + /// Create a new FnSigKind with the given ABI, safety, and C-style variadic flag. + fn new(abi: I::Abi, safety: I::Safety, c_variadic: bool) -> Self; + + /// Returns the ABI. + fn abi(self) -> I::Abi; + + /// Returns the safety mode. + fn safety(self) -> I::Safety; + + /// Do the function arguments end with a C-style variadic argument? + fn c_variadic(self) -> bool; +} + pub trait Abi>: Copy + Debug + Hash + Eq { - fn rust() -> Self; + /// The identity function. + fn abi(self) -> Self; + + /// The ABI `extern "Rust"`. + fn rust() -> I::Abi; /// Whether this ABI is `extern "Rust"`. fn is_rust(self) -> bool; + + /// Pack the ABI into a small dense integer, so it can be stored as packed `FnSigKind` flags. + fn pack_abi(self) -> u8; + + /// Unpack the ABI from packed `FnSigKind` flags. + fn unpack_abi(abi_index: u8) -> Self; } pub trait Safety>: Copy + Debug + Hash + Eq { + /// The `safe` safety mode. fn safe() -> Self; + /// The `unsafe` safety mode. + fn unsafe_mode() -> Self; + + /// Is the safety mode `Safe`? fn is_safe(self) -> bool; + /// The string prefix for this safety mode. fn prefix_str(self) -> &'static str; } diff --git a/compiler/rustc_type_ir/src/interner.rs b/compiler/rustc_type_ir/src/interner.rs index baae3f2ebe36..f71f7c7c1ab3 100644 --- a/compiler/rustc_type_ir/src/interner.rs +++ b/compiler/rustc_type_ir/src/interner.rs @@ -145,6 +145,7 @@ fn mk_tracked( + Eq + TypeVisitable + SliceLike; + type FSigKind: FSigKind; type Safety: Safety; type Abi: Abi; diff --git a/compiler/rustc_type_ir/src/predicate.rs b/compiler/rustc_type_ir/src/predicate.rs index 5277e0a992fc..e480b089b655 100644 --- a/compiler/rustc_type_ir/src/predicate.rs +++ b/compiler/rustc_type_ir/src/predicate.rs @@ -1,5 +1,5 @@ -use std::fmt; use std::hash::Hash; +use std::{fmt, iter}; use derive_where::derive_where; #[cfg(feature = "nightly")] @@ -42,6 +42,72 @@ fn lift_to_interner(self, cx: U) -> Option { } } +/// `'a == 'b`. +/// For the rationale behind having this instead of a pair of bidirectional +/// `'a: 'b` and `'b: 'a`, see +/// [this discusstion on Zulip](https://rust-lang.zulipchat.com/#narrow/channel/364551-t-types.2Ftrait-system-refactor/topic/A.20question.20on.20.23251/near/584167074). +#[derive_where(Clone, Copy, Hash, PartialEq, Eq, Debug; I: Interner)] +#[derive(TypeVisitable_Generic, GenericTypeVisitable, TypeFoldable_Generic, Lift_Generic)] +#[cfg_attr( + feature = "nightly", + derive(Decodable_NoContext, Encodable_NoContext, HashStable_NoContext) +)] +pub struct RegionEqPredicate(pub I::Region, pub I::Region); + +impl RegionEqPredicate { + /// Decompose `'a == 'b` into `['a: 'b, 'b: 'a]` + pub fn into_bidirectional_outlives(self) -> [OutlivesPredicate; 2] { + [OutlivesPredicate(self.0.into(), self.1), OutlivesPredicate(self.1.into(), self.0)] + } +} + +#[derive_where(Clone, Copy, Hash, PartialEq, Eq, Debug; I: Interner)] +#[derive(TypeVisitable_Generic, GenericTypeVisitable, TypeFoldable_Generic, Lift_Generic)] +#[cfg_attr( + feature = "nightly", + derive(Decodable_NoContext, Encodable_NoContext, HashStable_NoContext) +)] +pub enum RegionConstraint { + Outlives(OutlivesPredicate), + Eq(RegionEqPredicate), +} + +impl From> for RegionConstraint { + fn from(value: OutlivesPredicate) -> Self { + RegionConstraint::Outlives(value) + } +} + +impl From> for RegionConstraint { + fn from(value: RegionEqPredicate) -> Self { + RegionConstraint::Eq(value) + } +} + +impl RegionConstraint { + /// Whether the given constraint is either `'a: 'a` or `'a == 'a`. + pub fn is_trivial(self) -> bool { + match self { + RegionConstraint::Outlives(outlives) => { + outlives.0.as_region().is_some_and(|re| re == outlives.1) + } + RegionConstraint::Eq(eq) => eq.0 == eq.1, + } + } + + /// If `self` is an eq constraint, iterate through its decomposed bidirectional outlives + /// bounds and if not, just iterate once for the outlives bound itself. + pub fn iter_outlives(self) -> impl Iterator> { + match self { + RegionConstraint::Outlives(outlives) => iter::once(outlives).chain(None), + RegionConstraint::Eq(eq) => { + let [outlives1, outlives2] = eq.into_bidirectional_outlives(); + iter::once(outlives1).chain(Some(outlives2)) + } + } + } +} + /// A complete reference to a trait. /// /// These take numerous guises in syntax, diff --git a/compiler/rustc_type_ir/src/relate.rs b/compiler/rustc_type_ir/src/relate.rs index 61095a00d041..23d447e8e606 100644 --- a/compiler/rustc_type_ir/src/relate.rs +++ b/compiler/rustc_type_ir/src/relate.rs @@ -154,19 +154,19 @@ fn relate>( ) -> RelateResult> { let cx = relation.cx(); - if a.c_variadic != b.c_variadic { + if a.c_variadic() != b.c_variadic() { return Err(TypeError::VariadicMismatch(ExpectedFound::new( - a.c_variadic, - b.c_variadic, + a.c_variadic(), + b.c_variadic(), ))); } - if a.safety != b.safety { - return Err(TypeError::SafetyMismatch(ExpectedFound::new(a.safety, b.safety))); + if a.safety() != b.safety() { + return Err(TypeError::SafetyMismatch(ExpectedFound::new(a.safety(), b.safety()))); } - if a.abi != b.abi { - return Err(TypeError::AbiMismatch(ExpectedFound::new(a.abi, b.abi))); + if a.abi() != b.abi() { + return Err(TypeError::AbiMismatch(ExpectedFound::new(a.abi(), b.abi()))); }; let a_inputs = a.inputs(); @@ -202,9 +202,7 @@ fn relate>( }); Ok(ty::FnSig { inputs_and_output: cx.mk_type_list_from_iter(inputs_and_output)?, - c_variadic: a.c_variadic, - safety: a.safety, - abi: a.abi, + fn_sig_kind: a.fn_sig_kind, }) } } diff --git a/compiler/rustc_type_ir/src/solve/mod.rs b/compiler/rustc_type_ir/src/solve/mod.rs index 72b7df22b30d..fe779b66dc24 100644 --- a/compiler/rustc_type_ir/src/solve/mod.rs +++ b/compiler/rustc_type_ir/src/solve/mod.rs @@ -253,7 +253,7 @@ impl Eq for Response {} #[derive(TypeVisitable_Generic, GenericTypeVisitable, TypeFoldable_Generic)] #[cfg_attr(feature = "nightly", derive(HashStable_NoContext))] pub struct ExternalConstraintsData { - pub region_constraints: Vec>, + pub region_constraints: Vec>, pub opaque_types: Vec<(ty::OpaqueTypeKey, I::Ty)>, pub normalization_nested_goals: NestedNormalizationGoals, } diff --git a/compiler/rustc_type_ir/src/ty_kind.rs b/compiler/rustc_type_ir/src/ty_kind.rs index 9c57d04159cc..eed44442b77a 100644 --- a/compiler/rustc_type_ir/src/ty_kind.rs +++ b/compiler/rustc_type_ir/src/ty_kind.rs @@ -2,6 +2,7 @@ use std::ops::Deref; use derive_where::derive_where; +use rustc_abi::ExternAbi; use rustc_ast_ir::Mutability; #[cfg(feature = "nightly")] use rustc_data_structures::stable_hasher::{HashStable, StableHasher}; @@ -308,12 +309,7 @@ pub fn fn_sig(self, interner: I) -> ty::Binder> { ty::FnDef(def_id, args) => interner.fn_sig(def_id).instantiate(interner, args), ty::Error(_) => { // ignore errors (#54954) - ty::Binder::dummy(ty::FnSig { - inputs_and_output: Default::default(), - c_variadic: false, - safety: I::Safety::safe(), - abi: I::Abi::rust(), - }) + ty::Binder::dummy(ty::FnSig::dummy()) } ty::Closure(..) => panic!( "to get the signature of a closure, use `args.as_closure().sig()` not `fn_sig()`", @@ -762,6 +758,109 @@ pub struct TypeAndMut { impl Eq for TypeAndMut {} +/// Contains the packed non-type fields of a function signature. +// FIXME(splat): add the splatted argument index as a u16 +#[derive(Copy, Clone, PartialEq, Eq, Hash)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub struct FnSigKind { + /// Holds the c_variadic and safety bitflags, and 6 bits for the `ExternAbi` variant and unwind + /// flag. + flags: u8, +} + +impl fmt::Debug for FnSigKind { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let mut f = f.debug_tuple("FnSigKind"); + + if self.is_safe() { + f.field(&"Safe"); + } else { + f.field(&"Unsafe"); + } + + f.field(&self.abi()); + + if self.c_variadic() { + f.field(&"CVariadic"); + }; + + f.finish() + } +} + +impl FnSigKind { + /// Mask for the `ExternAbi` variant, including the unwind flag. + const EXTERN_ABI_MASK: u8 = 0b111111; + + /// Bitflag for `Safety::Safe`. The default is `Unsafe`. + const SAFE_FLAG: u8 = 1 << 6; + + /// Bitflag for a trailing C-style variadic argument. + const C_VARIADIC_FLAG: u8 = 1 << 7; + + /// Create a new FnSigKind with the "Rust" ABI, "Unsafe" safety, and no C-style variadic argument. + /// To modify these flags, use the `set_*` methods, for readability. + // FIXME: use Default instead when that trait is const stable. + pub const fn default() -> Self { + Self { flags: 0 }.set_abi(ExternAbi::Rust).set_safe(false).set_c_variadic(false) + } + + /// Set the ABI, including the unwind flag. + #[must_use = "this method does not modify the receiver"] + pub const fn set_abi(mut self, abi: ExternAbi) -> Self { + let abi_index = abi.as_packed(); + assert!(abi_index <= Self::EXTERN_ABI_MASK); + + self.flags &= !Self::EXTERN_ABI_MASK; + self.flags |= abi_index; + + self + } + + /// Set the safety flag, `true` is `Safe`. + #[must_use = "this method does not modify the receiver"] + pub const fn set_safe(mut self, is_safe: bool) -> Self { + if is_safe { + self.flags |= Self::SAFE_FLAG; + } else { + self.flags &= !Self::SAFE_FLAG; + } + + self + } + + /// Set the C-style variadic argument flag. + #[must_use = "this method does not modify the receiver"] + pub const fn set_c_variadic(mut self, c_variadic: bool) -> Self { + if c_variadic { + self.flags |= Self::C_VARIADIC_FLAG; + } else { + self.flags &= !Self::C_VARIADIC_FLAG; + } + + self + } + + /// Get the ABI, including the unwind flag. + pub const fn abi(self) -> ExternAbi { + let abi_index = self.flags & Self::EXTERN_ABI_MASK; + ExternAbi::from_packed(abi_index) + } + + /// Get the safety flag. + pub const fn is_safe(self) -> bool { + self.flags & Self::SAFE_FLAG != 0 + } + + /// Do the function arguments end with a C-style variadic argument? + pub const fn c_variadic(self) -> bool { + self.flags & Self::C_VARIADIC_FLAG != 0 + } +} + #[derive_where(Clone, Copy, PartialEq, Hash; I: Interner)] #[cfg_attr( feature = "nightly", @@ -770,13 +869,9 @@ impl Eq for TypeAndMut {} #[derive(TypeVisitable_Generic, GenericTypeVisitable, TypeFoldable_Generic, Lift_Generic)] pub struct FnSig { pub inputs_and_output: I::Tys, - pub c_variadic: bool, #[type_visitable(ignore)] #[type_foldable(identity)] - pub safety: I::Safety, - #[type_visitable(ignore)] - #[type_foldable(identity)] - pub abi: I::Abi, + pub fn_sig_kind: I::FSigKind, } impl Eq for FnSig {} @@ -791,8 +886,37 @@ pub fn output(self) -> I::Ty { } pub fn is_fn_trait_compatible(self) -> bool { - let FnSig { safety, abi, c_variadic, .. } = self; - !c_variadic && safety.is_safe() && abi.is_rust() + !self.c_variadic() && self.safety().is_safe() && self.abi().is_rust() + } + + pub fn set_safe(self, is_safe: bool) -> Self { + Self { + fn_sig_kind: I::FSigKind::new( + self.abi(), + if is_safe { I::Safety::safe() } else { I::Safety::unsafe_mode() }, + self.c_variadic(), + ), + ..self + } + } + + pub fn safety(self) -> I::Safety { + self.fn_sig_kind.safety() + } + + pub fn abi(self) -> I::Abi { + self.fn_sig_kind.abi() + } + + pub fn c_variadic(self) -> bool { + self.fn_sig_kind.c_variadic() + } + + pub fn dummy() -> Self { + Self { + inputs_and_output: Default::default(), + fn_sig_kind: I::FSigKind::new(I::Abi::rust(), I::Safety::safe(), false), + } } } @@ -817,16 +941,20 @@ pub fn output(self) -> ty::Binder { self.map_bound(|fn_sig| fn_sig.output()) } + pub fn fn_sig_kind(self) -> I::FSigKind { + self.skip_binder().fn_sig_kind + } + pub fn c_variadic(self) -> bool { - self.skip_binder().c_variadic + self.skip_binder().c_variadic() } pub fn safety(self) -> I::Safety { - self.skip_binder().safety + self.skip_binder().safety() } pub fn abi(self) -> I::Abi { - self.skip_binder().abi + self.skip_binder().abi() } pub fn is_fn_trait_compatible(&self) -> bool { @@ -835,8 +963,7 @@ pub fn is_fn_trait_compatible(&self) -> bool { // Used to split a single value into the two fields in `TyKind::FnPtr`. pub fn split(self) -> (ty::Binder>, FnHeader) { - let hdr = - FnHeader { c_variadic: self.c_variadic(), safety: self.safety(), abi: self.abi() }; + let hdr = FnHeader { fn_sig_kind: self.fn_sig_kind() }; (self.map_bound(|sig| FnSigTys { inputs_and_output: sig.inputs_and_output }), hdr) } } @@ -844,11 +971,11 @@ pub fn split(self) -> (ty::Binder>, FnHeader) { impl fmt::Debug for FnSig { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let sig = self; - let FnSig { inputs_and_output: _, c_variadic, safety, abi } = sig; + let FnSig { inputs_and_output: _, fn_sig_kind } = sig; - write!(f, "{}", safety.prefix_str())?; - if !abi.is_rust() { - write!(f, "extern \"{abi:?}\" ")?; + write!(f, "{}", fn_sig_kind.safety().prefix_str())?; + if !fn_sig_kind.abi().is_rust() { + write!(f, "extern \"{:?}\" ", fn_sig_kind.abi())?; } write!(f, "fn(")?; @@ -859,7 +986,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } write!(f, "{ty:?}")?; } - if *c_variadic { + if fn_sig_kind.c_variadic() { if inputs.is_empty() { write!(f, "...")?; } else { @@ -968,9 +1095,7 @@ impl ty::Binder> { pub fn with(self, hdr: FnHeader) -> ty::Binder> { self.map_bound(|sig_tys| FnSig { inputs_and_output: sig_tys.inputs_and_output, - c_variadic: hdr.c_variadic, - safety: hdr.safety, - abi: hdr.abi, + fn_sig_kind: hdr.fn_sig_kind, }) } @@ -1002,9 +1127,27 @@ pub fn output(self) -> ty::Binder { )] #[derive(TypeVisitable_Generic, GenericTypeVisitable, TypeFoldable_Generic, Lift_Generic)] pub struct FnHeader { - pub c_variadic: bool, - pub safety: I::Safety, - pub abi: I::Abi, + #[type_visitable(ignore)] + #[type_foldable(identity)] + pub fn_sig_kind: I::FSigKind, +} + +impl FnHeader { + pub fn c_variadic(self) -> bool { + self.fn_sig_kind.c_variadic() + } + + pub fn safety(self) -> I::Safety { + self.fn_sig_kind.safety() + } + + pub fn abi(self) -> I::Abi { + self.fn_sig_kind.abi() + } + + pub fn dummy() -> Self { + Self { fn_sig_kind: I::FSigKind::new(I::Abi::rust(), I::Safety::safe(), false) } + } } impl Eq for FnHeader {} diff --git a/compiler/rustc_type_ir/src/ty_kind/closure.rs b/compiler/rustc_type_ir/src/ty_kind/closure.rs index e8f94c8e7cc9..1ad5ed45e8b1 100644 --- a/compiler/rustc_type_ir/src/ty_kind/closure.rs +++ b/compiler/rustc_type_ir/src/ty_kind/closure.rs @@ -307,9 +307,7 @@ pub fn coroutine_closure_sig(self) -> ty::Binder resume_ty, yield_ty, return_ty, - c_variadic: hdr.c_variadic, - safety: hdr.safety, - abi: hdr.abi, + fn_sig_kind: hdr.fn_sig_kind, } }) } @@ -366,16 +364,10 @@ pub struct CoroutineClosureSignature { // Like the `fn_sig_as_fn_ptr_ty` of a regular closure, these types // never actually differ. But we save them rather than recreating them // from scratch just for good measure. - /// Always false - pub c_variadic: bool, - /// Always `Normal` (safe) + /// Always safe, RustCall, non-c-variadic #[type_visitable(ignore)] #[type_foldable(identity)] - pub safety: I::Safety, - /// Always `RustCall` - #[type_visitable(ignore)] - #[type_foldable(identity)] - pub abi: I::Abi, + pub fn_sig_kind: I::FSigKind, } impl Eq for CoroutineClosureSignature {} diff --git a/library/Cargo.lock b/library/Cargo.lock index ffa9a6302ef8..834babacdb96 100644 --- a/library/Cargo.lock +++ b/library/Cargo.lock @@ -125,9 +125,9 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.16.1" +version = "0.17.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" +checksum = "4f467dd6dccf739c208452f8014c75c18bb8301b050ad1cfb27153803edb0f51" dependencies = [ "foldhash", "rustc-std-workspace-alloc", @@ -146,9 +146,9 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.183" +version = "0.2.185" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b5b646652bf6661599e1da8901b3b9522896f01e736bad5f723fe7a3a27f899d" +checksum = "52ff2c0fe9bc6cb6b14a0592c2ff4fa9ceb83eea9db979b0487cd054946a2b8f" dependencies = [ "rustc-std-workspace-core", ] @@ -344,8 +344,8 @@ dependencies = [ "std_detect", "unwind", "vex-sdk", - "wasi 0.11.1+wasi-snapshot-preview1", - "wasi 0.14.4+wasi-0.2.4", + "wasip1", + "wasip2", "windows-link 0.0.0", ] @@ -407,20 +407,20 @@ dependencies = [ ] [[package]] -name = "wasi" -version = "0.11.1+wasi-snapshot-preview1" +name = "wasip1" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" +checksum = "b5e26842486624357dbeb8f0381cf1fb42f022291fd787d4a816768fec8cc760" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", ] [[package]] -name = "wasi" -version = "0.14.4+wasi-0.2.4" +name = "wasip2" +version = "1.0.2+wasi-0.2.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88a5f4a424faf49c3c2c344f166f0662341d470ea185e939657aaff130f0ec4a" +checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -513,9 +513,9 @@ checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650" [[package]] name = "wit-bindgen" -version = "0.45.1" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5c573471f125075647d03df72e026074b7203790d41351cd6edc96f46bcccd36" +checksum = "d7249219f66ced02969388cf2bb044a09756a083d0fab1e566056b04d9fbcaa5" dependencies = [ "rustc-std-workspace-alloc", "rustc-std-workspace-core", diff --git a/library/alloc/src/boxed.rs b/library/alloc/src/boxed.rs index 2c87d4724649..ef7422302d97 100644 --- a/library/alloc/src/boxed.rs +++ b/library/alloc/src/boxed.rs @@ -1006,26 +1006,6 @@ pub fn try_new_zeroed_slice(len: usize) -> Result]>, Al }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, Global).into_box(len)) } } - - /// Converts the boxed slice into a boxed array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *mut [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Box::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Box<[T], A> { @@ -1157,6 +1137,36 @@ pub fn try_new_zeroed_slice_in( }; unsafe { Ok(RawVec::from_raw_parts_in(ptr.as_ptr(), len, alloc).into_box(len)) } } + + /// Converts the boxed slice into a boxed array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// let box_slice: Box<[i32]> = Box::new([1, 2, 3]); + /// + /// let box_array: Box<[i32; 3]> = box_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Option> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *mut [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Box::from_raw_in(ptr, alloc) }; + Some(me) + } else { + None + } + } } impl Box, A> { @@ -1277,6 +1287,7 @@ impl Box { /// The raw pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// @@ -1302,6 +1313,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[stable(feature = "box_raw", since = "1.4.0")] #[inline] #[must_use = "call `drop(Box::from_raw(ptr))` if you intend to drop the `Box`"] @@ -1326,6 +1338,7 @@ pub unsafe fn from_raw(raw: *mut T) -> Self { /// The non-null pointer must point to a block of memory allocated by the global allocator. /// /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. /// /// # Examples /// @@ -1356,6 +1369,7 @@ pub unsafe fn from_raw(raw: *mut T) -> Self { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] #[must_use = "call `drop(Box::from_non_null(ptr))` if you intend to drop the `Box`"] @@ -1499,6 +1513,9 @@ impl Box { /// /// The raw pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a raw pointer @@ -1530,6 +1547,7 @@ impl Box { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] #[inline] pub unsafe fn from_raw_in(raw: *mut T, alloc: A) -> Self { @@ -1552,6 +1570,9 @@ pub unsafe fn from_raw_in(raw: *mut T, alloc: A) -> Self { /// /// The non-null pointer must point to a block of memory allocated by `alloc`. /// + /// The safety conditions are described in the [memory layout] section. + /// Note that the [considerations for unsafe code] apply to all `Box` values. + /// /// # Examples /// /// Recreate a `Box` which was previously converted to a `NonNull` pointer @@ -1582,6 +1603,7 @@ pub unsafe fn from_raw_in(raw: *mut T, alloc: A) -> Self { /// ``` /// /// [memory layout]: self#memory-layout + /// [considerations for unsafe code]: self#considerations-for-unsafe-code #[unstable(feature = "allocator_api", issue = "32838")] // #[unstable(feature = "box_vec_non_null", issue = "130364")] #[inline] diff --git a/library/alloc/src/rc.rs b/library/alloc/src/rc.rs index af76fddaced7..4e6d88665859 100644 --- a/library/alloc/src/rc.rs +++ b/library/alloc/src/rc.rs @@ -1167,26 +1167,6 @@ pub fn new_zeroed_slice(len: usize) -> Rc<[mem::MaybeUninit]> { )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Rc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Rc<[T], A> { @@ -1260,6 +1240,38 @@ pub fn new_zeroed_slice_in(len: usize, alloc: A) -> Rc<[mem::MaybeUninit], A> ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::rc::Rc; + /// + /// let rc_slice: Rc<[i32]> = Rc::new([1, 2, 3]); + /// + /// let rc_array: Rc<[i32; 3]> = rc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Option> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Rc::from_raw_in(ptr, alloc) }; + Some(me) + } else { + None + } + } } impl Rc, A> { @@ -3501,7 +3513,13 @@ pub unsafe fn from_raw_in(ptr: *const T, alloc: A) -> Self { /// Attempts to upgrade the `Weak` pointer to an [`Rc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// diff --git a/library/alloc/src/str.rs b/library/alloc/src/str.rs index 8a3326c7d76a..2966f3ccc179 100644 --- a/library/alloc/src/str.rs +++ b/library/alloc/src/str.rs @@ -335,13 +335,19 @@ pub fn replacen(&self, pat: P, to: &str, count: usize) -> String { /// Returns the lowercase equivalent of this string slice, as a new [`String`]. /// - /// 'Lowercase' is defined according to the terms of the Unicode Derived Core Property - /// `Lowercase`. + /// 'Lowercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34432) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Unlike [`char::to_lowercase()`], this method fully handles the context-dependent + /// casing of Greek sigma. However, like that method, it does not handle locale-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See that method's documentation + /// for more information. + /// /// # Examples /// /// Basic usage: @@ -378,7 +384,9 @@ pub fn replacen(&self, pat: P, to: &str, count: usize) -> String { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_lowercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_lowercase); + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_lowercase) }; let prefix_len = s.len(); @@ -426,13 +434,18 @@ fn case_ignorable_then_cased>(iter: I) -> bool { /// Returns the uppercase equivalent of this string slice, as a new [`String`]. /// - /// 'Uppercase' is defined according to the terms of the Unicode Derived Core Property - /// `Uppercase`. + /// 'Uppercase' is defined according to the terms of + /// [Chapter 3 (Conformance)](https://www.unicode.org/versions/latest/core-spec/chapter-3/#G34431) + /// of the Unicode standard. /// /// Since some characters can expand into multiple characters when changing /// the case, this function returns a [`String`] instead of modifying the /// parameter in-place. /// + /// Like [`char::to_uppercase()`] this method does not handle language-specific + /// casing, like Turkish and Azeri I/ı/İ/i. See that method's documentation + /// for more information. + /// /// # Examples /// /// Basic usage: @@ -463,7 +476,9 @@ fn case_ignorable_then_cased>(iter: I) -> bool { without modifying the original"] #[stable(feature = "unicode_case_mapping", since = "1.2.0")] pub fn to_uppercase(&self) -> String { - let (mut s, rest) = convert_while_ascii(self, u8::to_ascii_uppercase); + // SAFETY: `to_ascii_uppercase` preserves ASCII bytes, so the converted + // prefix remains valid UTF-8. + let (mut s, rest) = unsafe { convert_while_ascii(self, u8::to_ascii_uppercase) }; for c in rest.chars() { match conversions::to_upper(c) { @@ -626,11 +641,15 @@ pub unsafe fn from_boxed_utf8_unchecked(v: Box<[u8]>) -> Box { /// /// This function is only public so that it can be verified in a codegen test, /// see `issue-123712-str-to-lower-autovectorization.rs`. +/// +/// # Safety +/// +/// `convert` must return an ASCII byte for every ASCII input byte. #[unstable(feature = "str_internals", issue = "none")] #[doc(hidden)] #[inline] #[cfg(not(no_global_oom_handling))] -pub fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { +pub unsafe fn convert_while_ascii(s: &str, convert: fn(&u8) -> u8) -> (String, &str) { // Process the input in chunks of 16 bytes to enable auto-vectorization. // Previously the chunk size depended on the size of `usize`, // but on 32-bit platforms with sse or neon is also the better choice. diff --git a/library/alloc/src/sync.rs b/library/alloc/src/sync.rs index af1eaf2015e9..8004dd38d073 100644 --- a/library/alloc/src/sync.rs +++ b/library/alloc/src/sync.rs @@ -1313,26 +1313,6 @@ pub fn new_zeroed_slice(len: usize) -> Arc<[mem::MaybeUninit]> { )) } } - - /// Converts the reference-counted slice into a reference-counted array. - /// - /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. - /// - /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. - #[unstable(feature = "alloc_slice_into_array", issue = "148082")] - #[inline] - #[must_use] - pub fn into_array(self) -> Option> { - if self.len() == N { - let ptr = Self::into_raw(self) as *const [T; N]; - - // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. - let me = unsafe { Arc::from_raw(ptr) }; - Some(me) - } else { - None - } - } } impl Arc<[T], A> { @@ -1407,6 +1387,38 @@ pub fn new_zeroed_slice_in(len: usize, alloc: A) -> Arc<[mem::MaybeUninit], A ) } } + + /// Converts the reference-counted slice into a reference-counted array. + /// + /// This operation does not reallocate; the underlying array of the slice is simply reinterpreted as an array type. + /// + /// If `N` is not exactly equal to the length of `self`, then this method returns `None`. + /// + /// # Examples + /// + /// ``` + /// #![feature(alloc_slice_into_array)] + /// use std::sync::Arc; + /// + /// let arc_slice: Arc<[i32]> = Arc::new([1, 2, 3]); + /// + /// let arc_array: Arc<[i32; 3]> = arc_slice.into_array().unwrap(); + /// ``` + #[unstable(feature = "alloc_slice_into_array", issue = "148082")] + #[inline] + #[must_use] + pub fn into_array(self) -> Option> { + if self.len() == N { + let (ptr, alloc) = Self::into_raw_with_allocator(self); + let ptr = ptr as *const [T; N]; + + // SAFETY: The underlying array of a slice has the exact same layout as an actual array `[T; N]` if `N` is equal to the slice's length. + let me = unsafe { Arc::from_raw_in(ptr, alloc) }; + Some(me) + } else { + None + } + } } impl Arc, A> { @@ -3232,7 +3244,13 @@ impl Weak { /// Attempts to upgrade the `Weak` pointer to an [`Arc`], delaying /// dropping of the inner value if successful. /// - /// Returns [`None`] if the inner value has since been dropped. + /// Returns [`None`] in the following cases: + /// + /// 1. The inner value has since been dropped or moved out. + /// + /// 2. This `Weak` does not point to an allocation. + /// + /// 3. The owning reference this `Weak` is associated with is either not fully-constructed or does not allow an upgrade. /// /// # Examples /// diff --git a/library/core/src/any.rs b/library/core/src/any.rs index 71a529400511..53c5e28c0be2 100644 --- a/library/core/src/any.rs +++ b/library/core/src/any.rs @@ -666,7 +666,7 @@ pub unsafe fn downcast_unchecked_mut(&mut self) -> &mut T { /// /// The following is an example program that tries to use `TypeId::of` to /// implement a generic type `Unique` that guarantees unique instances for each `Unique`, -/// that is, and for each type `T` there can be at most one value of type `Unique` at any time. +/// that is, for each type `T` there can be at most one value of type `Unique` at any time. /// /// ``` /// mod unique { diff --git a/library/core/src/array/mod.rs b/library/core/src/array/mod.rs index fc540e2d20dd..12883e252ca8 100644 --- a/library/core/src/array/mod.rs +++ b/library/core/src/array/mod.rs @@ -11,7 +11,7 @@ use crate::error::Error; use crate::hash::{self, Hash}; use crate::intrinsics::transmute_unchecked; -use crate::iter::{UncheckedIterator, repeat_n}; +use crate::iter::{TrustedLen, UncheckedIterator, repeat_n}; use crate::marker::Destruct; use crate::mem::{self, ManuallyDrop, MaybeUninit}; use crate::ops::{ @@ -1010,19 +1010,66 @@ fn drop(&mut self) { pub(crate) const fn iter_next_chunk( iter: &mut impl [const] Iterator, ) -> Result<[T; N], IntoIter> { - let mut array = [const { MaybeUninit::uninit() }; N]; - let r = iter_next_chunk_erased(&mut array, iter); - match r { - Ok(()) => { - // SAFETY: All elements of `array` were populated. - Ok(unsafe { MaybeUninit::array_assume_init(array) }) - } - Err(initialized) => { - // SAFETY: Only the first `initialized` elements were populated - Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + iter.spec_next_chunk() +} + +pub(crate) const trait SpecNextChunk: Iterator { + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter>; +} +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +impl, T, const N: usize> const SpecNextChunk for I { + #[inline] + default fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let mut array = [const { MaybeUninit::uninit() }; N]; + let r = iter_next_chunk_erased(&mut array, self); + match r { + Ok(()) => { + // SAFETY: All elements of `array` were populated. + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + Err(initialized) => { + // SAFETY: Only the first `initialized` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..initialized) }) + } } } } +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +impl + TrustedLen, T, const N: usize> const SpecNextChunk + for I +{ + fn spec_next_chunk(&mut self) -> Result<[T; N], IntoIter> { + let len = (*self).size_hint().0; + let mut array = [const { MaybeUninit::uninit() }; N]; + if len < N { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get len items out of it. + unsafe { write(&mut array, self, len) }; + // SAFETY: Only the first `len` elements were populated + Err(unsafe { IntoIter::new_unchecked(array, 0..len) }) + } else { + // SAFETY: `TrustedLen`, an unsafe trait, requires that i can get N items out of it. + unsafe { write(&mut array, self, N) }; + // SAFETY: All N items were populated + Ok(unsafe { MaybeUninit::array_assume_init(array) }) + } + } +} +// SAFETY: `from` must have len items, and len items must be < N. +#[rustc_const_unstable(feature = "const_iter", issue = "92476")] +const unsafe fn write( + to: &mut [MaybeUninit; N], + from: &mut impl [const] Iterator, + len: usize, +) { + let mut guard = Guard { array_mut: to, initialized: 0 }; + while guard.initialized < len { + // SAFETY: caller has guaranteed, from has len items. + let item = unsafe { from.next().unwrap_unchecked() }; + // SAFETY: guard.initialized < len < N + unsafe { guard.push_unchecked(item) }; + } + crate::mem::forget(guard); +} /// Version of [`iter_next_chunk`] using a passed-in slice in order to avoid /// needing to monomorphize for every array length. diff --git a/library/core/src/cell/lazy.rs b/library/core/src/cell/lazy.rs index ae559e599f48..66436ed7d94f 100644 --- a/library/core/src/cell/lazy.rs +++ b/library/core/src/cell/lazy.rs @@ -346,7 +346,8 @@ fn deref_mut(&mut self) -> &mut T { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyCell { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +impl const Default for LazyCell { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyCell { @@ -366,7 +367,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } } -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for LazyCell { /// Constructs a `LazyCell` that starts already initialized /// with the provided value. diff --git a/library/core/src/char/methods.rs b/library/core/src/char/methods.rs index ce33fd1d8f9d..00b735e91a37 100644 --- a/library/core/src/char/methods.rs +++ b/library/core/src/char/methods.rs @@ -810,7 +810,7 @@ pub fn is_cased(self) -> bool { match self { 'a'..='z' | 'A'..='Z' => true, '\0'..='\u{A9}' => false, - _ => unicode::Cased(self), + _ => unicode::Lowercase(self) || unicode::Uppercase(self) || unicode::Lt(self), } } @@ -840,10 +840,10 @@ pub fn case(self) -> Option { 'a'..='z' => Some(CharCase::Lower), 'A'..='Z' => Some(CharCase::Upper), '\0'..='\u{A9}' => None, - _ if !unicode::Cased(self) => None, _ if unicode::Lowercase(self) => Some(CharCase::Lower), _ if unicode::Uppercase(self) => Some(CharCase::Upper), - _ => Some(CharCase::Title), + _ if unicode::Lt(self) => Some(CharCase::Title), + _ => None, } } @@ -919,7 +919,7 @@ pub const fn is_lowercase(self) -> bool { pub fn is_titlecase(self) -> bool { match self { '\0'..='\u{01C4}' => false, - _ => self.is_cased() && !self.is_lowercase() && !self.is_uppercase(), + _ => unicode::Lt(self), } } @@ -1151,13 +1151,14 @@ pub fn is_numeric(self) -> bool { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#notes-on-context-and-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1199,6 +1200,48 @@ pub fn is_numeric(self) -> bool { /// // convert into themselves. /// assert_eq!('山'.to_lowercase().to_string(), "山"); /// ``` + /// # Notes on context and locale + /// + /// As stated earlier, this method does not take into account language or context. + /// Below is a non-exhaustive list of situations where this can be relevant. + /// If you need to handle locale-depedendent casing in your code, consider using + /// an external crate, like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. + /// + /// ## Greek sigma + /// + /// In Greek, the letter simga (uppercase Σ) has two lowercase forms: + /// ς which is used only at the end of a word, and σ which is used everywhere else. + /// `to_lowercase()` always uses the second form: + /// + /// ``` + /// assert_eq!('Σ'.to_lowercase().to_string(), "σ"); + /// ``` + /// + /// ## Turkish and Azeri I/ı/İ/i + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the uppercase undotted 'I' is the same as the Latin. Therefore: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// ``` + /// + /// The value of `lower_i` here relies on the language of the text: if we're + /// in `en-US`, it should be `"i"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"ı"`. `to_lowercase()` does not take this into account, and so: + /// + /// ``` + /// let lower_i = 'I'.to_lowercase().to_string(); + /// + /// assert_eq!(lower_i, "i"); + /// ``` + /// + /// holds across languages. #[must_use = "this returns the lowercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] @@ -1211,8 +1254,10 @@ pub fn to_lowercase(self) -> ToLowercase { /// `char`s. /// /// This is usually, but not always, equivalent to the uppercase mapping - /// returned by [`Self::to_uppercase`]. Prefer this method when seeking to capitalize - /// Only The First Letter of a word, but use [`Self::to_uppercase`] for ALL CAPS. + /// returned by [`to_uppercase()`]. Prefer this method when seeking to capitalize + /// Only The First Letter of a word, but use [`to_uppercase()`] for ALL CAPS. + /// See [below](#difference-from-uppercase) for a thorough explanation + /// of the difference between the two methods. /// /// If this `char` does not have a titlecase mapping, the iterator yields the same `char`. /// @@ -1222,13 +1267,14 @@ pub fn to_lowercase(self) -> ToLowercase { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1265,8 +1311,9 @@ pub fn to_lowercase(self) -> ToLowercase { /// ``` /// #![feature(titlecase)] /// assert_eq!('c'.to_titlecase().to_string(), "C"); + /// assert_eq!('ა'.to_titlecase().to_string(), "ა"); /// assert_eq!('dž'.to_titlecase().to_string(), "Dž"); - /// assert_eq!('ῼ'.to_titlecase().to_string(), "ῼ"); + /// assert_eq!('ᾨ'.to_titlecase().to_string(), "ᾨ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ß'.to_titlecase().to_string(), "Ss"); @@ -1276,8 +1323,78 @@ pub fn to_lowercase(self) -> ToLowercase { /// assert_eq!('山'.to_titlecase().to_string(), "山"); /// ``` /// + /// # Difference from uppercase + /// + /// Currently, there are three classes of characters where [`to_uppercase()`] + /// and `to_titlecase()` give different results: + /// + /// ## Georgian script + /// + /// Each letter in the modern Georgian alphabet can be written in one of two forms: + /// the typical lowercase-like "mkhedruli" form, and a variant uppercase-like "mtavruli" + /// form. However, unlike uppercase in most cased scripts, mtavruli is not typically used + /// to start sentences, denote proper nouns, or for any other purpose + /// in running text. It is instead confined to titles and headings, which are written entirely + /// in mtavruli. For this reason, [`to_uppercase()`] applied to a Georgian letter + /// will return the mtavruli form, but `to_titlecase()` will return the mkhedruli form. + /// + /// ``` + /// #![feature(titlecase)] + /// let ani = 'ა'; // First letter of the Georgian alphabet, in mkhedruli form + /// + /// // Titlecasing mkhedruli maps it to itself... + /// assert_eq!(ani.to_titlecase().to_string(), ani.to_string()); + /// + /// // but uppercasing it maps it to mtavruli + /// assert_eq!(ani.to_uppercase().to_string(), "Ა"); + /// ``` + /// + /// ## Compatibility digraphs for Latin-alphabet Serbo-Croatian + /// + /// The standard Latin alphabet for the Serbo-Croatian language + /// (Bosnian, Croatian, Montenegrin, and Serbian) contains + /// three digraphs: Dž, Lj, and Nj. These are usually represented as + /// two characters. However, for compatibility with older character sets, + /// Unicode includes single-character versions of these digraphs. + /// Each has a uppercase, titlecase, and lowercase version: + /// + /// - `'DŽ'`, `'Dž'`, `'dž'` + /// - `'LJ'`, `'Lj'`, `'lj'` + /// - `'NJ'`, `'Nj'`, `'nj'` + /// + /// Unicode additionally encodes a casing triad for the Dz digraph + /// without the caron: `'DZ'`, `'Dz'`, `'dz'`. + /// + /// ## Iota-subscritped Greek vowels + /// + /// In ancient Greek, the long vowels alpha (α), eta (η), and omega (ω) + /// were sometimes followed by an iota (ι), forming a diphthong. Over time, + /// the diphthong pronunciation was slowly lost, with the iota becoming mute. + /// Eventually, the ι disappeared from the spelling as well. + /// However, there remains a need to represent ancient texts faithfully. + /// + /// Modern editions of ancient Greek texts commonly use a reduced-sized + /// ι symbol to denote mute iotas, while distinguishing them from ιs + /// which continued to affect pronunciation. The exact standard differs + /// between different publications. Some render the mute ι below its associated + /// vowel (subscript), while others place it to the right of said vowel (adscript). + /// The interaction of mute ι symbols with casing also varies. + /// + /// The Unicode Standard, for its default casing rules, chose to make lowercase + /// Greek vowels with iota subscipt (e.g. `'ᾠ'`) titlecase to the uppercase vowel + /// with iota subscript (`'ᾨ'`) but uppercase to the uppercase vowel followed by + /// full-size uppercase iota (`"ὨΙ"`). This is just one convention among many + /// in common use, but it is the one Unicode settled on, + /// so it is what this method does also. + /// /// # Note on locale /// + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of a common + /// locale-dependent casing issue follows: + /// /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï @@ -1302,6 +1419,8 @@ pub fn to_lowercase(self) -> ToLowercase { /// ``` /// /// holds across languages. + /// + /// [`to_uppercase()`]: Self::to_uppercase() #[must_use = "this returns the titlecased character as a new iterator, \ without modifying the original"] #[unstable(feature = "titlecase", issue = "153892")] @@ -1313,8 +1432,9 @@ pub fn to_titlecase(self) -> ToTitlecase { /// Returns an iterator that yields the uppercase mapping of this `char` as one or more /// `char`s. /// - /// Prefer this method when converting a word into ALL CAPS, but consider [`Self::to_titlecase`] - /// instead if you seek to capitalize Only The First Letter. + /// Prefer this method when converting a word into ALL CAPS, but consider [`to_titlecase()`] + /// instead if you seek to capitalize Only The First Letter. See that method's documentation + /// for more information on the difference between the two. /// /// If this `char` does not have an uppercase mapping, the iterator yields the same `char`. /// @@ -1324,13 +1444,14 @@ pub fn to_titlecase(self) -> ToTitlecase { /// [ucd]: https://www.unicode.org/reports/tr44/ /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt /// - /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields - /// the `char`(s) given by [`SpecialCasing.txt`]. + /// If this `char` expands to multiple `char`s, the iterator yields the `char`s given by + /// [`SpecialCasing.txt`]. The maximum number of `char`s in a case mapping is 3. /// /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt /// /// This operation performs an unconditional mapping without tailoring. That is, the conversion - /// is independent of context and language. + /// is independent of context and language. See [below](#note-on-locale) + /// for more information. /// /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. @@ -1338,6 +1459,7 @@ pub fn to_titlecase(self) -> ToTitlecase { /// [Unicode Standard]: https://www.unicode.org/versions/latest/ /// /// # Examples + /// /// `'ſt'` (U+FB05) is a single Unicode code point (a ligature) that maps to "ST" in uppercase. /// /// As an iterator: @@ -1365,11 +1487,12 @@ pub fn to_titlecase(self) -> ToTitlecase { /// /// ``` /// assert_eq!('c'.to_uppercase().to_string(), "C"); + /// assert_eq!('ა'.to_uppercase().to_string(), "Ა"); /// assert_eq!('dž'.to_uppercase().to_string(), "DŽ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ſt'.to_uppercase().to_string(), "ST"); - /// assert_eq!('ῼ'.to_uppercase().to_string(), "ΩΙ"); + /// assert_eq!('ᾨ'.to_uppercase().to_string(), "ὨΙ"); /// /// // Characters that do not have both uppercase and lowercase /// // convert into themselves. @@ -1378,6 +1501,12 @@ pub fn to_titlecase(self) -> ToTitlecase { /// /// # Note on locale /// + /// As stated above, this method is locale-insensitive. + /// If you need locale support, consider using an external crate, + /// like [`icu_casemap`](https://crates.io/crates/icu_casemap) + /// which is developed by Unicode. A description of a common + /// locale-dependent casing issue follows: + /// /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï @@ -1400,6 +1529,8 @@ pub fn to_titlecase(self) -> ToTitlecase { /// ``` /// /// holds across languages. + /// + /// [`to_titlecase()`]: Self::to_titlecase() #[must_use = "this returns the uppercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] @@ -1932,6 +2063,9 @@ pub const fn is_ascii_graphic(&self) -> bool { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `c.is_ascii_whitespace()` is **not** equivalent to `c.is_ascii() && c.is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes diff --git a/library/core/src/clone.rs b/library/core/src/clone.rs index 85b09ee06f1f..f2fa6fd0ca3e 100644 --- a/library/core/src/clone.rs +++ b/library/core/src/clone.rs @@ -680,7 +680,7 @@ impl const Clone for &T { #[inline(always)] #[rustc_diagnostic_item = "noop_method_clone"] fn clone(&self) -> Self { - self + *self } } diff --git a/library/core/src/convert/mod.rs b/library/core/src/convert/mod.rs index ef4ab15f93c0..4a4c7ee388f9 100644 --- a/library/core/src/convert/mod.rs +++ b/library/core/src/convert/mod.rs @@ -577,6 +577,7 @@ pub const trait Into: Sized { /// [`from`]: From::from /// [book]: ../../book/ch09-00-error-handling.html #[rustc_diagnostic_item = "From"] +#[lang = "From"] #[stable(feature = "rust1", since = "1.0.0")] #[rustc_on_unimplemented(on( all(Self = "&str", T = "alloc::string::String"), diff --git a/library/core/src/convert/num.rs b/library/core/src/convert/num.rs index 673245056e79..a56ce1806d52 100644 --- a/library/core/src/convert/num.rs +++ b/library/core/src/convert/num.rs @@ -1,4 +1,4 @@ -use crate::num::TryFromIntError; +use crate::num::{IntErrorKind, TryFromIntError}; mod private { /// This trait being unreachable from outside the crate @@ -172,8 +172,14 @@ fn from(small: $small) -> Self { impl_from!(u64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // float -> float -// FIXME(f16,f128): adding additional `From<{float}>` impls to `f32` breaks inference. See -// + +// FIXME(f16): adding the additional `From<{float}>` impl to `f32` would break inference in cases +// like `f32::from(1.0)`. The type checker has a custom workaround to keep that and similar code +// compiling even with the second `From<16> for f32` instance. We keep this instance unstable for +// now so that we can later remove the workaround. +// +// See also . +impl_from!(f16 => f32, #[unstable(feature = "f32_from_f16", issue = "154005")], #[unstable_feature_bound(f32_from_f16)]); impl_from!(f16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(f16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(f32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); @@ -272,7 +278,7 @@ fn try_from(u: $source) -> Result { if u >= 0 { Ok(u as Self) } else { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::NegOverflow)) } } } @@ -293,7 +299,7 @@ impl const TryFrom<$source> for $target { #[inline] fn try_from(u: $source) -> Result { if u > (Self::MAX as $source) { - Err(TryFromIntError(())) + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -317,8 +323,10 @@ impl const TryFrom<$source> for $target { fn try_from(u: $source) -> Result { let min = Self::MIN as $source; let max = Self::MAX as $source; - if u < min || u > max { - Err(TryFromIntError(())) + if u < min { + Err(TryFromIntError(IntErrorKind::NegOverflow)) + } else if u > max { + Err(TryFromIntError(IntErrorKind::PosOverflow)) } else { Ok(u as Self) } @@ -329,7 +337,7 @@ fn try_from(u: $source) -> Result { /// Implement `TryFrom` for `bool` macro_rules! impl_try_from_integer_for_bool { - ($($int:ty)+) => {$( + ($signedness:ident $($int:ty)+) => {$( #[stable(feature = "bool_try_from_int", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const TryFrom<$int> for bool { @@ -349,10 +357,23 @@ impl const TryFrom<$int> for bool { /// ``` #[inline] fn try_from(i: $int) -> Result { - match i { - 0 => Ok(false), - 1 => Ok(true), - _ => Err(TryFromIntError(())), + sign_dependent_expr!{ + $signedness ? + if signed { + match i { + 0 => Ok(false), + 1 => Ok(true), + ..0 => Err(TryFromIntError(IntErrorKind::NegOverflow)), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } + if unsigned { + match i { + 0 => Ok(false), + 1 => Ok(true), + 2.. => Err(TryFromIntError(IntErrorKind::PosOverflow)), + } + } } } } @@ -366,8 +387,8 @@ macro_rules! rev { } // integer -> bool -impl_try_from_integer_for_bool!(u128 u64 u32 u16 u8); -impl_try_from_integer_for_bool!(i128 i64 i32 i16 i8); +impl_try_from_integer_for_bool!(unsigned u128 u64 u32 u16 u8); +impl_try_from_integer_for_bool!(signed i128 i64 i32 i16 i8); // unsigned integer -> unsigned integer impl_try_from_upper_bounded!(u16 => u8); @@ -405,7 +426,7 @@ macro_rules! rev { #[cfg(target_pointer_width = "16")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8); impl_try_from_unbounded!(usize => u16, u32, u64, u128); @@ -427,7 +448,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "32")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16); impl_try_from_unbounded!(usize => u32, u64, u128); @@ -452,7 +473,7 @@ mod ptr_try_from_impls { #[cfg(target_pointer_width = "64")] mod ptr_try_from_impls { - use super::TryFromIntError; + use super::{IntErrorKind, TryFromIntError}; impl_try_from_upper_bounded!(usize => u8, u16, u32); impl_try_from_unbounded!(usize => u64, u128); @@ -550,7 +571,7 @@ impl const TryFrom<$Int> for NonZero<$Int> { #[doc = concat!("to [NonZero]\\<[", stringify!($Int), "]>.")] #[inline] fn try_from(value: $Int) -> Result { - Self::new(value).ok_or(TryFromIntError(())) + Self::new(value).ok_or(TryFromIntError(IntErrorKind::Zero)) } } }; diff --git a/library/core/src/error.rs b/library/core/src/error.rs index 011d6ac4a1c7..0f01c09c8d91 100644 --- a/library/core/src/error.rs +++ b/library/core/src/error.rs @@ -494,7 +494,7 @@ fn request_by_type_tag<'a, I>(err: &'a (impl Error + ?Sized)) -> Option(err: &'a (impl Error + ?Sized)) -> Option` in the responses offered by the producer. /// /// * A Producer initializes the value of one of its fields of a specific type. (or is otherwise -/// prepared to generate a value requested). eg, `backtrace::Backtrace` or -/// `std::backtrace::Backtrace` +/// prepared to generate a value requested). e.g., `backtrace::Backtrace` or +/// `std::backtrace::Backtrace`. /// * A Consumer requests an object of a specific type (say `std::backtrace::Backtrace`). In the /// case of a `dyn Error` trait object (the Producer), there are functions called `request_ref` and /// `request_value` to simplify obtaining an `Option` for a given type. /// * The Producer, when requested, populates the given Request object which is given as a mutable /// reference. /// * The Consumer extracts a value or reference to the requested type from the `Request` object -/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and ` -/// request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at +/// wrapped in an `Option`; in the case of `dyn Error` the aforementioned `request_ref` and +/// `request_value` methods mean that `dyn Error` users don't have to deal with the `Request` type at /// all (but `Error` implementors do). The `None` case of the `Option` suggests only that the -/// Producer cannot currently offer an instance of the requested type, not it can't or never will. +/// Producer cannot currently offer an instance of the requested type, not that it can't or never will. /// /// # Examples /// diff --git a/library/core/src/ffi/c_str.rs b/library/core/src/ffi/c_str.rs index 62b3d75d7a77..e3a3aed4a794 100644 --- a/library/core/src/ffi/c_str.rs +++ b/library/core/src/ffi/c_str.rs @@ -716,7 +716,7 @@ fn index(&self, index: ops::RangeFrom) -> &CStr { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl ops::Index> for CStr { type Output = CStr; diff --git a/library/core/src/ffi/va_list.rs b/library/core/src/ffi/va_list.rs index f0f58a0f8343..034e4ad728b8 100644 --- a/library/core/src/ffi/va_list.rs +++ b/library/core/src/ffi/va_list.rs @@ -266,14 +266,17 @@ fn drop(&mut self) { mod sealed { pub trait Sealed {} + impl Sealed for i16 {} impl Sealed for i32 {} impl Sealed for i64 {} impl Sealed for isize {} + impl Sealed for u16 {} impl Sealed for u32 {} impl Sealed for u64 {} impl Sealed for usize {} + impl Sealed for f32 {} impl Sealed for f64 {} impl Sealed for *mut T {} @@ -297,24 +300,64 @@ impl Sealed for *const T {} // We may unseal this trait in the future, but currently our `va_arg` implementations don't support // types with an alignment larger than 8, or with a non-scalar layout. Inline assembly can be used // to accept unsupported types in the meantime. +#[lang = "va_arg_safe"] pub unsafe trait VaArgSafe: sealed::Sealed {} -// i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. +crate::cfg_select! { + any(target_arch = "avr", target_arch = "msp430") => { + // c_int/c_uint are i16/u16 on these targets. + // + // - i8 is implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 is implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + unsafe impl VaArgSafe for i16 {} + unsafe impl VaArgSafe for u16 {} + } + _ => { + // c_int/c_uint are i32/u32 on this target. + // + // - i8 and i16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. + // - u8 and u16 are implicitly promoted to c_uint in C, and cannot implement `VaArgSafe`. + } +} + +crate::cfg_select! { + target_arch = "avr" => { + // c_double is f32 on this target. + unsafe impl VaArgSafe for f32 {} + } + _ => { + // c_double is f64 on this target. + // + // - f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. + } +} + unsafe impl VaArgSafe for i32 {} unsafe impl VaArgSafe for i64 {} unsafe impl VaArgSafe for isize {} -// u8 and u16 are implicitly promoted to c_int in C, and cannot implement `VaArgSafe`. unsafe impl VaArgSafe for u32 {} unsafe impl VaArgSafe for u64 {} unsafe impl VaArgSafe for usize {} -// f32 is implicitly promoted to c_double in C, and cannot implement `VaArgSafe`. unsafe impl VaArgSafe for f64 {} unsafe impl VaArgSafe for *mut T {} unsafe impl VaArgSafe for *const T {} +// Check that relevant `core::ffi` types implement `VaArgSafe`. +const _: () = { + const fn va_arg_safe_check() {} + + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); + va_arg_safe_check::(); +}; + impl<'f> VaList<'f> { /// Read an argument from the variable argument list, and advance to the next argument. /// diff --git a/library/core/src/intrinsics/mod.rs b/library/core/src/intrinsics/mod.rs index 6f9d35130016..94d0c7eab922 100644 --- a/library/core/src/intrinsics/mod.rs +++ b/library/core/src/intrinsics/mod.rs @@ -364,6 +364,8 @@ pub const fn prefetch_write_instruction(data: *const T) /// On Unix, the /// process will probably terminate with a signal like `SIGABRT`, `SIGILL`, `SIGTRAP`, `SIGSEGV` or /// `SIGBUS`. The precise behavior is not guaranteed and not stable. +/// +/// The stabilization-track version of this intrinsic is [`core::process::abort_immediate`]. #[rustc_nounwind] #[rustc_intrinsic] pub fn abort() -> !; diff --git a/library/core/src/intrinsics/simd/scalable.rs b/library/core/src/intrinsics/simd/scalable.rs index b2b0fec487c0..a8984b3a2f7d 100644 --- a/library/core/src/intrinsics/simd/scalable.rs +++ b/library/core/src/intrinsics/simd/scalable.rs @@ -2,27 +2,6 @@ //! //! In this module, a "vector" is any `#[rustc_scalable_vector]`-annotated type. -/// Numerically casts a vector, elementwise. -/// -/// `T` and `U` must be vectors of integers or floats, and must have the same length. -/// -/// When casting floats to integers, the result is truncated. Out-of-bounds result lead to UB. -/// When casting integers to floats, the result is rounded. -/// Otherwise, truncates or extends the value, maintaining the sign for signed integers. -/// -/// # Safety -/// Casting from integer types is always safe. -/// Casting between two float types is also always safe. -/// -/// Casting floats to integers truncates, following the same rules as `to_int_unchecked`. -/// Specifically, each element must: -/// * Not be `NaN` -/// * Not be infinite -/// * Be representable in the return type, after truncating off its fractional part -#[rustc_intrinsic] -#[rustc_nounwind] -pub unsafe fn sve_cast(x: T) -> U; - /// Create a tuple of two vectors. /// /// `SVecTup` must be a scalable vector tuple (`#[rustc_scalable_vector]`) and `SVec` must be a diff --git a/library/core/src/iter/sources/repeat_n.rs b/library/core/src/iter/sources/repeat_n.rs index c29ab24a0835..4cbaf4185214 100644 --- a/library/core/src/iter/sources/repeat_n.rs +++ b/library/core/src/iter/sources/repeat_n.rs @@ -102,6 +102,15 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } } +/// Creates an empty iterator, like [`repeat_n(value, 0)`][`repeat_n`] +/// but without needing any such value at hand. +#[stable(feature = "iter_repeat_n_default", since = "CURRENT_RUSTC_VERSION")] +impl Default for RepeatN { + fn default() -> Self { + RepeatN { inner: None } + } +} + #[stable(feature = "iter_repeat_n", since = "1.82.0")] impl Iterator for RepeatN { type Item = A; diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs index 299aa9f113bf..3b72752cee9a 100644 --- a/library/core/src/lib.rs +++ b/library/core/src/lib.rs @@ -316,6 +316,8 @@ pub mod autodiff { #[unstable(feature = "pattern_type_macro", issue = "123646")] pub mod pat; pub mod pin; +#[unstable(feature = "abort_immediate", issue = "154601")] +pub mod process; #[unstable(feature = "random", issue = "130703")] pub mod random; #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] diff --git a/library/core/src/marker.rs b/library/core/src/marker.rs index e0f8e1048473..f56a4d7308e9 100644 --- a/library/core/src/marker.rs +++ b/library/core/src/marker.rs @@ -846,7 +846,7 @@ impl Copy for PhantomData {} #[stable(feature = "rust1", since = "1.0.0")] impl Clone for PhantomData { fn clone(&self) -> Self { - Self + *self } } @@ -937,6 +937,8 @@ impl !UnsafeUnpin for UnsafePinned {} {T: PointeeSized} *mut T, {T: PointeeSized} &T, {T: PointeeSized} &mut T, + {T: PointeeSized} pattern_type!(*const T is !null), + {T: PointeeSized} pattern_type!(*mut T is !null), } /// Types that do not require any pinning guarantees. @@ -1093,9 +1095,13 @@ pub trait ConstParamTy_: StructuralPartialEq + Eq {} /* compiler built-in */ } +// For `adt_const_params` to be recognized as a feature +#[unstable(feature = "adt_const_params", issue = "95174")] +const _: () = (); + // FIXME(adt_const_params): handle `ty::FnDef`/`ty::Closure` marker_impls! { - #[unstable(feature = "adt_const_params", issue = "95174")] + #[unstable(feature = "min_adt_const_params", issue = "154042")] ConstParamTy_ for usize, u8, u16, u32, u64, u128, isize, i8, i16, i32, i64, i128, diff --git a/library/core/src/mem/alignment.rs b/library/core/src/mem/alignment.rs index a8c4c8ea78ff..a57d8e853590 100644 --- a/library/core/src/mem/alignment.rs +++ b/library/core/src/mem/alignment.rs @@ -178,7 +178,7 @@ pub const fn as_usize(self) -> usize { /// Returns the alignment as a [NonZero]<[usize]>. #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[deprecated( - since = "CURRENT_RUSTC_VERSION", + since = "1.96.0", note = "renamed to `as_nonzero_usize`", suggestion = "as_nonzero_usize" )] @@ -281,7 +281,7 @@ impl const TryFrom for Alignment { #[inline] fn try_from(align: usize) -> Result { - Self::new(align).ok_or(num::TryFromIntError(())) + Self::new(align).ok_or(num::TryFromIntError(num::IntErrorKind::NotAPowerOfTwo)) } } diff --git a/library/core/src/mem/mod.rs b/library/core/src/mem/mod.rs index a987970c9bcc..91934cfceb4e 100644 --- a/library/core/src/mem/mod.rs +++ b/library/core/src/mem/mod.rs @@ -32,6 +32,7 @@ use crate::alloc::Layout; use crate::clone::TrivialClone; +use crate::cmp::Ordering; use crate::marker::{Destruct, DiscriminantKind}; use crate::panic::const_assert; use crate::{clone, cmp, fmt, hash, intrinsics, ptr}; @@ -1088,6 +1089,102 @@ pub const fn copy(x: &T) -> T { } } +/// Like [`transmute`], but only initializes the "common prefix" of the first +/// `min(size_of::(), size_of::())` bytes of the destination from the +/// corresponding bytes of the source. +/// +/// This is equivalent to a "union cast" through a `union` with `#[repr(C)]`. +/// +/// That means some size mismatches are not UB, like `[T; 2]` to `[T; 1]`. +/// Increasing size is usually UB from being insufficiently initialized -- like +/// `u8` to `u32` -- but isn't always. For example, going from `u8` to +/// `#[repr(C, align(4))] AlignedU8(u8);` is sound. +/// +/// Prefer normal `transmute` where possible, for the extra checking, since +/// both do exactly the same thing at runtime, if they both compile. +/// +/// # Safety +/// +/// If `size_of::() >= size_of::()`, the first `size_of::()` bytes +/// of `src` must be be *valid* when interpreted as a `Dst`. (In this case, the +/// preconditions are the same as for `transmute_copy(&ManuallyDrop::new(src))`.) +/// +/// If `size_of::() <= size_of::()`, the bytes of `src` padded with +/// uninitialized bytes afterwards up to a total size of `size_of::()` +/// must be *valid* when interpreted as a `Dst`. +/// +/// In both cases, any safety preconditions of the `Dst` type must also be upheld. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_prefix)] +/// use std::mem::transmute_prefix; +/// +/// assert_eq!(unsafe { transmute_prefix::<[i32; 4], [i32; 2]>([1, 2, 3, 4]) }, [1, 2]); +/// +/// let expected = if cfg!(target_endian = "little") { 0x34 } else { 0x12 }; +/// assert_eq!(unsafe { transmute_prefix::(0x1234) }, expected); +/// +/// // Would be UB because the destination is incompletely initialized. +/// // transmute_prefix::(123) +/// +/// // OK because the destination is allowed to be partially initialized. +/// let _: std::mem::MaybeUninit = unsafe { transmute_prefix(123_u8) }; +/// ``` +#[unstable(feature = "transmute_prefix", issue = "155079")] +pub const unsafe fn transmute_prefix(src: Src) -> Dst { + #[repr(C)] + union Transmute { + a: ManuallyDrop, + b: ManuallyDrop, + } + + match const { Ord::cmp(&Src::SIZE, &Dst::SIZE) } { + // SAFETY: When Dst is bigger, the union is the size of Dst + Ordering::Less => unsafe { + let a = transmute_neo(src); + intrinsics::transmute_unchecked(Transmute:: { a }) + }, + // SAFETY: When they're the same size, we can use the MIR primitive + Ordering::Equal => unsafe { intrinsics::transmute_unchecked::(src) }, + // SAFETY: When Src is bigger, the union is the size of Src + Ordering::Greater => unsafe { + let u: Transmute = intrinsics::transmute_unchecked(src); + transmute_neo(u.b) + }, + } +} + +/// New version of `transmute`, exposed under this name so it can be iterated upon +/// without risking breakage to uses of "real" transmute. +/// +/// It will not be stabilized under this name. +/// +/// # Examples +/// +/// ``` +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// assert_eq!(unsafe { transmute_neo::(0.0) }, 0); +/// ``` +/// +/// ```compile_fail,E0080 +/// #![feature(transmute_neo)] +/// use std::mem::transmute_neo; +/// +/// unsafe { transmute_neo::(123) }; +/// ``` +#[unstable(feature = "transmute_neo", issue = "155079")] +pub const unsafe fn transmute_neo(src: Src) -> Dst { + const { assert!(Src::SIZE == Dst::SIZE) }; + + // SAFETY: the const-assert just checked that they're the same size, + // and any other safety invariants need to be upheld by the caller. + unsafe { intrinsics::transmute_unchecked(src) } +} + /// Opaque type representing the discriminant of an enum. /// /// See the [`discriminant`] function in this module for more information. diff --git a/library/core/src/num/error.rs b/library/core/src/num/error.rs index 8a353dc0fbe9..f01c0f92567a 100644 --- a/library/core/src/num/error.rs +++ b/library/core/src/num/error.rs @@ -7,7 +7,16 @@ /// The error type returned when a checked integral type conversion fails. #[stable(feature = "try_from", since = "1.34.0")] #[derive(Debug, Copy, Clone, PartialEq, Eq)] -pub struct TryFromIntError(pub(crate) ()); +pub struct TryFromIntError(pub(crate) IntErrorKind); + +impl TryFromIntError { + /// Outputs the detailed cause of converting an integer failing. + #[must_use] + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + pub const fn kind(&self) -> &IntErrorKind { + &self.0 + } +} #[stable(feature = "try_from", since = "1.34.0")] impl fmt::Display for TryFromIntError { @@ -66,7 +75,8 @@ pub struct ParseIntError { pub(super) kind: IntErrorKind, } -/// Enum to store the various types of errors that can cause parsing an integer to fail. +/// Enum to store the various types of errors that can cause parsing or converting an +/// integer to fail. /// /// # Example /// @@ -103,10 +113,19 @@ pub enum IntErrorKind { NegOverflow, /// Value was Zero /// - /// This variant will be emitted when the parsing string has a value of zero, which - /// would be illegal for non-zero types. + /// This variant will be emitted when the parsing string or the converting integer + /// has a value of zero, which would be illegal for non-zero types. #[stable(feature = "int_error_matching", since = "1.55.0")] Zero, + /// Value is not a power of two. + /// + /// This variant will be emitted when converting an integer that is not a power of + /// two. This is required in some cases such as constructing an [`Alignment`]. + /// + /// [`Alignment`]: core::ptr::Alignment "ptr::Alignment" + #[unstable(feature = "try_from_int_error_kind", issue = "153978")] + // Also, #[unstable(feature = "ptr_alignment_type", issue = "102070")] + NotAPowerOfTwo, } impl ParseIntError { @@ -128,6 +147,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { IntErrorKind::PosOverflow => "number too large to fit in target type", IntErrorKind::NegOverflow => "number too small to fit in target type", IntErrorKind::Zero => "number would be zero for non-zero type", + IntErrorKind::NotAPowerOfTwo => "number is not a power of two", } .fmt(f) } diff --git a/library/core/src/num/int_macros.rs b/library/core/src/num/int_macros.rs index 6a403542dd23..1b1489261f62 100644 --- a/library/core/src/num/int_macros.rs +++ b/library/core/src/num/int_macros.rs @@ -173,14 +173,13 @@ pub const fn trailing_ones(self) -> u32 { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -194,14 +193,13 @@ pub const fn isolate_highest_one(self) -> Self { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -215,14 +213,13 @@ pub const fn isolate_lowest_one(self) -> Self { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -236,14 +233,13 @@ pub const fn highest_one(self) -> Option { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] diff --git a/library/core/src/num/mod.rs b/library/core/src/num/mod.rs index 5ba3695bc45c..e305cff31189 100644 --- a/library/core/src/num/mod.rs +++ b/library/core/src/num/mod.rs @@ -1065,6 +1065,9 @@ pub const fn is_ascii_graphic(&self) -> bool { /// U+0020 SPACE, U+0009 HORIZONTAL TAB, U+000A LINE FEED, /// U+000C FORM FEED, or U+000D CARRIAGE RETURN. /// + /// **Warning:** Because the list above excludes U+000B VERTICAL TAB, + /// `b.is_ascii_whitespace()` is **not** equivalent to `char::from(b).is_whitespace()`. + /// /// Rust uses the WhatWG Infra Standard's [definition of ASCII /// whitespace][infra-aw]. There are several other definitions in /// wide use. For instance, [the POSIX locale][pct] includes diff --git a/library/core/src/num/nonzero.rs b/library/core/src/num/nonzero.rs index c270b947d4fd..7cb022b08290 100644 --- a/library/core/src/num/nonzero.rs +++ b/library/core/src/num/nonzero.rs @@ -650,8 +650,6 @@ pub const fn trailing_zeros(self) -> u32 { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -662,7 +660,8 @@ pub const fn trailing_zeros(self) -> u32 { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -683,8 +682,6 @@ pub const fn isolate_highest_one(self) -> Self { /// # Example /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -695,7 +692,8 @@ pub const fn isolate_highest_one(self) -> Self { /// # Some(()) /// # } /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -713,8 +711,6 @@ pub const fn isolate_lowest_one(self) -> Self { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -724,7 +720,8 @@ pub const fn isolate_lowest_one(self) -> Self { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -737,8 +734,6 @@ pub const fn highest_one(self) -> u32 { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// /// # use core::num::NonZero; /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { @@ -748,7 +743,8 @@ pub const fn highest_one(self) -> u32 { /// # Some(()) /// # } /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -1950,19 +1946,18 @@ pub const fn cast_signed(self) -> NonZero<$Sint> { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// /// # use core::num::NonZero; /// # /// # fn main() { test().unwrap(); } /// # fn test() -> Option<()> { - #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::MIN.bit_width(), NonZero::new(1)?);")] + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1)?.bit_width(), NonZero::new(1)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b111)?.bit_width(), NonZero::new(3)?);")] #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::new(0b1110)?.bit_width(), NonZero::new(4)?);")] /// # Some(()) /// # } /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "uint_bit_width", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] diff --git a/library/core/src/num/uint_macros.rs b/library/core/src/num/uint_macros.rs index c35deee920e4..5be1b837798f 100644 --- a/library/core/src/num/uint_macros.rs +++ b/library/core/src/num/uint_macros.rs @@ -232,14 +232,13 @@ pub const fn trailing_ones(self) -> u32 { /// # Examples /// /// ``` - /// #![feature(uint_bit_width)] - /// #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".bit_width(), 0);")] #[doc = concat!("assert_eq!(0b111_", stringify!($SelfT), ".bit_width(), 3);")] #[doc = concat!("assert_eq!(0b1110_", stringify!($SelfT), ".bit_width(), 4);")] #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.bit_width(), ", stringify!($BITS), ");")] /// ``` - #[unstable(feature = "uint_bit_width", issue = "142326")] + #[stable(feature = "uint_bit_width", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "uint_bit_width", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -253,14 +252,13 @@ pub const fn bit_width(self) -> u32 { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_highest_one(), 0b_01000000); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_highest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -274,14 +272,13 @@ pub const fn isolate_highest_one(self) -> Self { /// # Examples /// /// ``` - /// #![feature(isolate_most_least_significant_one)] - /// #[doc = concat!("let n: ", stringify!($SelfT), " = 0b_01100100;")] /// /// assert_eq!(n.isolate_lowest_one(), 0b_00000100); #[doc = concat!("assert_eq!(0_", stringify!($SelfT), ".isolate_lowest_one(), 0);")] /// ``` - #[unstable(feature = "isolate_most_least_significant_one", issue = "136909")] + #[stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "isolate_most_least_significant_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -295,14 +292,13 @@ pub const fn isolate_lowest_one(self) -> Self { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".highest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".highest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".highest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".highest_one(), Some(4));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -319,14 +315,13 @@ pub const fn highest_one(self) -> Option { /// # Examples /// /// ``` - /// #![feature(int_lowest_highest_one)] - /// #[doc = concat!("assert_eq!(0b0_", stringify!($SelfT), ".lowest_one(), None);")] #[doc = concat!("assert_eq!(0b1_", stringify!($SelfT), ".lowest_one(), Some(0));")] #[doc = concat!("assert_eq!(0b1_0000_", stringify!($SelfT), ".lowest_one(), Some(4));")] #[doc = concat!("assert_eq!(0b1_1111_", stringify!($SelfT), ".lowest_one(), Some(0));")] /// ``` - #[unstable(feature = "int_lowest_highest_one", issue = "145203")] + #[stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "int_lowest_highest_one", since = "CURRENT_RUSTC_VERSION")] #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline(always)] @@ -871,7 +866,7 @@ pub const fn strict_add(self, rhs: Self) -> Self { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX` or `self + rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self + rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_add`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1050,7 +1045,7 @@ pub const fn strict_sub(self, rhs: Self) -> Self { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self - rhs > ", stringify!($SelfT), "::MAX` or `self - rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self - rhs < ", stringify!($SelfT), "::MIN`,")] /// i.e. when [`checked_sub`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked @@ -1259,7 +1254,7 @@ pub const fn strict_mul(self, rhs: Self) -> Self { /// # Safety /// /// This results in undefined behavior when - #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX` or `self * rhs < ", stringify!($SelfT), "::MIN`,")] + #[doc = concat!("`self * rhs > ", stringify!($SelfT), "::MAX`,")] /// i.e. when [`checked_mul`] would return `None`. /// /// [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked diff --git a/library/core/src/ops/control_flow.rs b/library/core/src/ops/control_flow.rs index b15712d3599c..5f8974133a94 100644 --- a/library/core/src/ops/control_flow.rs +++ b/library/core/src/ops/control_flow.rs @@ -134,7 +134,8 @@ fn from_residual(residual: ControlFlow) -> Self { } #[unstable(feature = "try_trait_v2_residual", issue = "91285")] -impl ops::Residual for ControlFlow { +#[rustc_const_unstable(feature = "const_try_residual", issue = "91285")] +impl const ops::Residual for ControlFlow { type TryType = ControlFlow; } @@ -261,8 +262,8 @@ pub const fn break_value(self) -> Option /// assert_eq!(res, Ok(&5)); /// ``` #[inline] - #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn break_ok(self) -> Result { match self { @@ -373,8 +374,8 @@ pub const fn continue_value(self) -> Option /// assert_eq!(res, Err("too big value detected")); /// ``` #[inline] - #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "control_flow_ok", since = "1.96.0")] + #[rustc_const_stable(feature = "control_flow_ok", since = "1.96.0")] #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn continue_ok(self) -> Result { match self { diff --git a/library/core/src/ops/deref.rs b/library/core/src/ops/deref.rs index 305861ea7b69..e46204c6246a 100644 --- a/library/core/src/ops/deref.rs +++ b/library/core/src/ops/deref.rs @@ -293,6 +293,7 @@ fn deref_mut(&mut self) -> &mut T { /// unchanged. #[unstable(feature = "deref_pure_trait", issue = "87121")] #[lang = "deref_pure"] +#[rustc_dyn_incompatible_trait] pub unsafe trait DerefPure: PointeeSized {} #[unstable(feature = "deref_pure_trait", issue = "87121")] diff --git a/library/core/src/ops/try_trait.rs b/library/core/src/ops/try_trait.rs index 34000f6d6b21..9521213e1bc7 100644 --- a/library/core/src/ops/try_trait.rs +++ b/library/core/src/ops/try_trait.rs @@ -157,7 +157,7 @@ pub const trait Try: [const] FromResidual { /// type: that type will have a "hole" in the correct place, and will maintain the /// "foo-ness" of the residual so other types need to opt-in to interconversion. #[unstable(feature = "try_trait_v2", issue = "84277", old_name = "try_trait")] - type Residual; + type Residual: Residual; /// Constructs the type from its `Output` type. /// diff --git a/library/core/src/ops/unsize.rs b/library/core/src/ops/unsize.rs index f0781ee01fd5..45a6e973ca71 100644 --- a/library/core/src/ops/unsize.rs +++ b/library/core/src/ops/unsize.rs @@ -33,7 +33,7 @@ /// [nomicon-coerce]: ../../nomicon/coercions.html #[unstable(feature = "coerce_unsized", issue = "18598")] #[lang = "coerce_unsized"] -pub trait CoerceUnsized { +pub trait CoerceUnsized: Sized { // Empty. } @@ -116,7 +116,7 @@ impl, U: PointeeSized> CoerceUnsized<*const U> for * /// [^1]: Formerly known as *object safety*. #[unstable(feature = "dispatch_from_dyn", issue = "none")] #[lang = "dispatch_from_dyn"] -pub trait DispatchFromDyn { +pub trait DispatchFromDyn: Sized { // Empty. } diff --git a/library/core/src/panic/unwind_safe.rs b/library/core/src/panic/unwind_safe.rs index 20f85b5ca9cd..f7f485488e0f 100644 --- a/library/core/src/panic/unwind_safe.rs +++ b/library/core/src/panic/unwind_safe.rs @@ -317,7 +317,7 @@ fn size_hint(&self) -> (usize, Option) { /// If a value's type is already `UnwindSafe`, /// wrapping it in `AssertUnwindSafe` is never incorrect. -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for AssertUnwindSafe where T: UnwindSafe, diff --git a/library/core/src/process.rs b/library/core/src/process.rs new file mode 100644 index 000000000000..81481b2cba26 --- /dev/null +++ b/library/core/src/process.rs @@ -0,0 +1,43 @@ +//! A module for working with processes. +//! +//! Most process-related functionality requires std, but [`abort_immediate`] +//! is available on all targets. + +/// Terminates the process in a violent fashion. +/// +/// The function will never return and will immediately terminate the current +/// process in a platform specific "abnormal" manner. As a consequence, +/// no destructors on the current stack or any other thread's stack +/// will be run, Rust IO buffers (eg, from `BufWriter`) will not be flushed, +/// and C stdio buffers will not be flushed. +/// +/// Unlike [`abort`](../../std/process/fn.abort.html), `abort_immediate` does +/// not attempt to match C `abort()` or otherwise perform a "clean" abort. +/// Instead, it emits code that will crash the process with as little overhead +/// as possible, such as a "halt and catch fire" style instruction. You should +/// generally prefer using `abort` instead except where the absolute minimum +/// overhead is required. +/// +/// # Platform-specific behavior +/// +/// `abort_immediate` lowers to a trap instruction on *most* architectures; on +/// some architectures it simply lowers to call the unmangled `abort` function. +/// The exact behavior is architecture and system dependent. +/// +/// On bare-metal (no OS) systems the trap instruction usually causes a +/// *hardware* exception to be raised in a *synchronous* fashion; hardware +/// exceptions have nothing to do with C++ exceptions and are closer in +/// semantics to POSIX signals. +/// +/// On hosted applications (applications running under an OS), the trap +/// instruction *usually* terminates the whole process with an exit code that +/// corresponds to `SIGILL` or equivalent, *unless* this signal is handled. +/// Other signals such as `SIGABRT`, `SIGTRAP`, `SIGSEGV`, and `SIGBUS` may be +/// produced instead, depending on specifics. This is not an exhaustive list. +#[unstable(feature = "abort_immediate", issue = "154601")] +#[cold] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[doc(alias = "halt")] +pub fn abort_immediate() -> ! { + crate::intrinsics::abort() +} diff --git a/library/core/src/ptr/mod.rs b/library/core/src/ptr/mod.rs index ddeb1ccc72af..ece65111c9d2 100644 --- a/library/core/src/ptr/mod.rs +++ b/library/core/src/ptr/mod.rs @@ -262,16 +262,15 @@ //! [`with_addr`] method: //! //! ```text -//! /// Creates a new pointer with the given address. -//! /// -//! /// This performs the same operation as an `addr as ptr` cast, but copies -//! /// the *provenance* of `self` to the new pointer. -//! /// This allows us to dynamically preserve and propagate this important -//! /// information in a way that is otherwise impossible with a unary cast. -//! /// -//! /// This is equivalent to using `wrapping_offset` to offset `self` to the -//! /// given address, and therefore has all the same capabilities and restrictions. -//! pub fn with_addr(self, addr: usize) -> Self; +//! /// Creates a new pointer with the given address and the provenance of `self`. +//! /// +//! /// This is similar to a `addr as *const T` cast, +//! /// but copies the provenance of `self` to the new pointer. +//! /// This avoids the inherent ambiguity of the unary cast. +//! /// +//! /// This is equivalent to using `wrapping_offset` to offset `self` to the given address, +//! /// and therefore has all the same capabilities and restrictions. +//! pub fn with_addr(self, addr: usize) -> Self; //! ``` //! //! So you're still able to drop down to the address representation and do whatever @@ -413,7 +412,7 @@ use crate::{fmt, hash, intrinsics, ub_checks}; #[unstable(feature = "ptr_alignment_type", issue = "102070")] -#[deprecated(since = "CURRENT_RUSTC_VERSION", note = "moved from `ptr` to `mem`")] +#[deprecated(since = "1.96.0", note = "moved from `ptr` to `mem`")] /// Deprecated re-export of [mem::Alignment]. pub type Alignment = mem::Alignment; diff --git a/library/core/src/ptr/mut_ptr.rs b/library/core/src/ptr/mut_ptr.rs index 289dd972f679..98b70a77fad7 100644 --- a/library/core/src/ptr/mut_ptr.rs +++ b/library/core/src/ptr/mut_ptr.rs @@ -594,7 +594,7 @@ pub fn mask(self, mask: usize) -> *mut T { /// /// [`as_mut`]: #method.as_mut /// [`as_uninit_mut`]: #method.as_uninit_mut - /// [`as_ref_unchecked`]: #method.as_mut_unchecked + /// [`as_ref_unchecked`]: #method.as_ref_unchecked /// /// # Safety /// diff --git a/library/core/src/ptr/non_null.rs b/library/core/src/ptr/non_null.rs index 90f27ca8bdb0..262e1781629f 100644 --- a/library/core/src/ptr/non_null.rs +++ b/library/core/src/ptr/non_null.rs @@ -69,13 +69,10 @@ /// [null pointer optimization]: crate::option#representation #[stable(feature = "nonnull", since = "1.25.0")] #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] #[rustc_diagnostic_item = "NonNull"] pub struct NonNull { - // Remember to use `.as_ptr()` instead of `.pointer`, as field projecting to - // this is banned by . - pointer: *const T, + pointer: crate::pattern_type!(*const T is !null), } /// `NonNull` pointers are not `Send` because the data they reference may be aliased. diff --git a/library/core/src/range.rs b/library/core/src/range.rs index 1200f8922c81..ade9a35b0ab3 100644 --- a/library/core/src/range.rs +++ b/library/core/src/range.rs @@ -24,13 +24,13 @@ pub mod legacy; #[doc(inline)] -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] pub use iter::RangeFromIter; #[doc(inline)] #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub use iter::RangeInclusiveIter; #[doc(inline)] -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub use iter::RangeIter; // FIXME(#125687): re-exports temporarily removed @@ -68,17 +68,17 @@ #[lang = "RangeCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, Default, PartialEq, Eq)] -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub struct Range { /// The lower bound of the range (inclusive). - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub start: Idx, /// The upper bound of the range (exclusive). - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] pub end: Idx, } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl fmt::Debug for Range { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -103,7 +103,7 @@ impl Range { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeIter { self.clone().into_iter() @@ -132,7 +132,7 @@ impl> Range { /// assert!(!Range::from(f32::NAN..1.0).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -164,7 +164,7 @@ pub const fn contains(&self, item: &U) -> bool /// assert!( Range::from(f32::NAN..5.0).is_empty()); /// ``` #[inline] - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool where @@ -174,7 +174,7 @@ pub const fn is_empty(&self) -> bool } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { @@ -191,7 +191,7 @@ fn end_bound(&self) -> Bound<&T> { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { @@ -210,7 +210,7 @@ fn into_bounds(self) -> (Bound, Bound) { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for legacy::Range { #[inline] @@ -218,7 +218,7 @@ fn from(value: Range) -> Self { Self { start: value.start, end: value.end } } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for Range { #[inline] @@ -444,14 +444,14 @@ fn from(value: legacy::RangeInclusive) -> Self { #[lang = "RangeFromCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, PartialEq, Eq)] -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] pub struct RangeFrom { /// The lower bound of the range (inclusive). - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] pub start: Idx, } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl fmt::Debug for RangeFrom { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -475,7 +475,7 @@ impl RangeFrom { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[inline] pub fn iter(&self) -> RangeFromIter { self.clone().into_iter() @@ -499,7 +499,7 @@ impl> RangeFrom { /// assert!(!RangeFrom::from(f32::NAN..).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -510,7 +510,7 @@ pub const fn contains(&self, item: &U) -> bool } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { @@ -527,7 +527,7 @@ fn end_bound(&self) -> Bound<&T> { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { @@ -557,7 +557,7 @@ fn bound(self) -> (OneSidedRangeBound, T) { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] impl const From> for legacy::RangeFrom { #[inline] @@ -565,7 +565,7 @@ fn from(value: RangeFrom) -> Self { Self { start: value.start } } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] impl const From> for RangeFrom { #[inline] @@ -619,14 +619,14 @@ fn from(value: legacy::RangeFrom) -> Self { #[lang = "RangeToInclusiveCopy"] #[doc(alias = "..=")] #[derive(Copy, Clone, PartialEq, Eq, Hash)] -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub struct RangeToInclusive { /// The upper bound of the range (inclusive) - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] pub last: Idx, } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl fmt::Debug for RangeToInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { write!(fmt, "..=")?; @@ -650,7 +650,7 @@ impl> RangeToInclusive { /// assert!(!(..=f32::NAN).contains(&0.5)); /// ``` #[inline] - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -661,13 +661,13 @@ pub const fn contains(&self, item: &U) -> bool } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for RangeToInclusive { fn from(value: legacy::RangeToInclusive) -> Self { Self { last: value.end } } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl From> for legacy::RangeToInclusive { fn from(value: RangeToInclusive) -> Self { Self { end: value.last } @@ -677,7 +677,7 @@ fn from(value: RangeToInclusive) -> Self { // RangeToInclusive cannot impl From> // because underflow would be possible with (..0).into() -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { @@ -688,7 +688,7 @@ fn end_bound(&self) -> Bound<&T> { } } -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeToInclusive<&T> { fn start_bound(&self) -> Bound<&T> { diff --git a/library/core/src/range/iter.rs b/library/core/src/range/iter.rs index a5db3699bc40..01b69554a0b1 100644 --- a/library/core/src/range/iter.rs +++ b/library/core/src/range/iter.rs @@ -6,7 +6,7 @@ use crate::{intrinsics, mem}; /// By-value [`Range`] iterator. -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[derive(Debug, Clone)] pub struct RangeIter(legacy::Range); @@ -64,7 +64,7 @@ unsafe impl TrustedRandomAccessNoCoerce for RangeIter<$t> { u64 i64 } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl Iterator for RangeIter { type Item = A; @@ -132,7 +132,7 @@ unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl DoubleEndedIterator for RangeIter { #[inline] fn next_back(&mut self) -> Option { @@ -153,10 +153,10 @@ fn advance_back_by(&mut self, n: usize) -> Result<(), NonZero> { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeIter {} -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl FusedIterator for RangeIter {} -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] impl IntoIterator for Range { type Item = A; type IntoIter = RangeIter; @@ -299,7 +299,7 @@ fn into_iter(self) -> Self::IntoIter { // since e.g. `(0..=u64::MAX).len()` would be `u64::MAX + 1`. macro_rules! range_exact_iter_impl { ($($t:ty)*) => ($( - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] impl ExactSizeIterator for RangeIter<$t> { } )*) } @@ -322,7 +322,7 @@ impl ExactSizeIterator for RangeInclusiveIter<$t> { } } /// By-value [`RangeFrom`] iterator. -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[derive(Debug, Clone)] pub struct RangeFromIter { start: A, @@ -361,7 +361,7 @@ pub fn remainder(self) -> RangeFrom { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl Iterator for RangeFromIter { type Item = A; @@ -432,10 +432,10 @@ fn nth(&mut self, n: usize) -> Option { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeFromIter {} -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl FusedIterator for RangeFromIter {} -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] impl IntoIterator for RangeFrom { type Item = A; type IntoIter = RangeFromIter; diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs index edf058c96a52..9db07d8abbbe 100644 --- a/library/core/src/slice/ascii.rs +++ b/library/core/src/slice/ascii.rs @@ -222,7 +222,11 @@ pub fn escape_ascii(&self) -> EscapeAscii<'_> { /// Returns a byte slice with leading ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -251,7 +255,11 @@ pub const fn trim_ascii_start(&self) -> &[u8] { /// Returns a byte slice with trailing ASCII whitespace bytes removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -281,7 +289,11 @@ pub const fn trim_ascii_end(&self) -> &[u8] { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the `\0x0B` byte even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. + /// + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// diff --git a/library/core/src/slice/index.rs b/library/core/src/slice/index.rs index f1727a1f629c..0efe87a2d536 100644 --- a/library/core/src/slice/index.rs +++ b/library/core/src/slice/index.rs @@ -125,13 +125,13 @@ impl Sealed for ops::RangeToInclusive {} #[stable(feature = "slice_index_with_ops_bound_pair", since = "1.53.0")] impl Sealed for (ops::Bound, ops::Bound) {} - #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_api", since = "1.96.0")] impl Sealed for range::Range {} #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl Sealed for range::RangeInclusive {} - #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] impl Sealed for range::RangeToInclusive {} - #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "new_range_from_api", since = "1.96.0")] impl Sealed for range::RangeFrom {} impl Sealed for ops::IndexRange {} @@ -458,7 +458,7 @@ fn index_mut(self, slice: &mut [T]) -> &mut [T] { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::Range { type Output = [T]; @@ -588,7 +588,7 @@ fn index_mut(self, slice: &mut [T]) -> &mut [T] { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeFrom { type Output = [T]; @@ -801,7 +801,7 @@ fn index_mut(self, slice: &mut [T]) -> &mut [T] { } /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { type Output = [T]; diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs index d3c37e3caf6a..a838ba009b48 100644 --- a/library/core/src/slice/mod.rs +++ b/library/core/src/slice/mod.rs @@ -754,6 +754,7 @@ pub const fn as_ptr(&self) -> *const T { #[rustc_as_ptr] #[inline(always)] #[must_use] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut T { self as *mut [T] as *mut T } diff --git a/library/core/src/str/mod.rs b/library/core/src/str/mod.rs index 1a4493de30a1..5af399ab1b34 100644 --- a/library/core/src/str/mod.rs +++ b/library/core/src/str/mod.rs @@ -589,6 +589,7 @@ pub const fn as_ptr(&self) -> *const u8 { #[rustc_as_ptr] #[must_use] #[inline(always)] + #[rustc_no_writable] pub const fn as_mut_ptr(&mut self) -> *mut u8 { self as *mut str as *mut u8 } @@ -1202,6 +1203,9 @@ pub fn split_whitespace(&self) -> SplitWhitespace<'_> { /// /// This uses the same definition as [`char::is_ascii_whitespace`]. /// To split by Unicode `Whitespace` instead, use [`split_whitespace`]. + /// Note that because of this difference in definition, even if `s.is_ascii()` + /// is `true`, `s.split_ascii_whitespace()` behavior will differ from `s.split_whitespace()` + /// if `s` contains U+000B VERTICAL TAB. /// /// [`split_whitespace`]: str::split_whitespace /// @@ -2896,9 +2900,12 @@ pub const fn make_ascii_lowercase(&mut self) { /// Returns a string slice with leading ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_start`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2921,9 +2928,12 @@ pub const fn trim_ascii_start(&self) -> &str { /// Returns a string slice with trailing ASCII whitespace removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim_end`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// @@ -2947,9 +2957,12 @@ pub const fn trim_ascii_end(&self) -> &str { /// removed. /// /// 'Whitespace' refers to the definition used by - /// [`u8::is_ascii_whitespace`]. + /// [`u8::is_ascii_whitespace`]. Importantly, this definition excludes + /// the U+000B code point even though it has the Unicode [`White_Space`] property + /// and is removed by [`str::trim`]. /// /// [`u8::is_ascii_whitespace`]: u8::is_ascii_whitespace + /// [`White_Space`]: https://www.unicode.org/reports/tr44/#White_Space /// /// # Examples /// diff --git a/library/core/src/str/traits.rs b/library/core/src/str/traits.rs index da0039f055fd..3b5cec22b69e 100644 --- a/library/core/src/str/traits.rs +++ b/library/core/src/str/traits.rs @@ -258,7 +258,7 @@ fn index_mut(self, slice: &mut str) -> &mut Self::Output { } } -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::Range { type Output = str; @@ -555,7 +555,7 @@ fn index_mut(self, slice: &mut str) -> &mut Self::Output { } } -#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_from_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::RangeFrom { type Output = str; @@ -777,7 +777,7 @@ fn index_mut(self, slice: &mut str) -> &mut Self::Output { /// Panics if `last` does not point to the ending byte offset of a character /// (`last + 1` is either a starting byte offset as defined by /// `is_char_boundary`, or equal to `len`), or if `last >= len`. -#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_to_inclusive_api", since = "1.96.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::RangeToInclusive { type Output = str; diff --git a/library/core/src/tuple.rs b/library/core/src/tuple.rs index 58f81372aff7..187e201c3cea 100644 --- a/library/core/src/tuple.rs +++ b/library/core/src/tuple.rs @@ -47,8 +47,7 @@ impl<$($T: [const] Eq),+> const Eq for ($($T,)+) maybe_tuple_doc! { $($T)+ @ - #[unstable(feature = "adt_const_params", issue = "95174")] - #[unstable_feature_bound(unsized_const_params)] + #[unstable(feature = "min_adt_const_params", issue = "154042")] impl<$($T: ConstParamTy_),+> ConstParamTy_ for ($($T,)+) {} } diff --git a/library/core/src/unicode/mod.rs b/library/core/src/unicode/mod.rs index 22a1166fdf16..8b2c526a0887 100644 --- a/library/core/src/unicode/mod.rs +++ b/library/core/src/unicode/mod.rs @@ -9,9 +9,9 @@ #[rustfmt::skip] pub(crate) use unicode_data::alphabetic::lookup as Alphabetic; pub(crate) use unicode_data::case_ignorable::lookup as Case_Ignorable; -pub(crate) use unicode_data::cased::lookup as Cased; pub(crate) use unicode_data::grapheme_extend::lookup as Grapheme_Extend; pub(crate) use unicode_data::lowercase::lookup as Lowercase; +pub(crate) use unicode_data::lt::lookup as Lt; pub(crate) use unicode_data::n::lookup as N; pub(crate) use unicode_data::uppercase::lookup as Uppercase; pub(crate) use unicode_data::white_space::lookup as White_Space; diff --git a/library/core/src/unicode/unicode_data.rs b/library/core/src/unicode/unicode_data.rs index f602cd5c5b6b..83d380805184 100644 --- a/library/core/src/unicode/unicode_data.rs +++ b/library/core/src/unicode/unicode_data.rs @@ -1,16 +1,16 @@ //! This file is generated by `./x run src/tools/unicode-table-generator`; do not edit manually! // Alphabetic : 1723 bytes, 147369 codepoints in 759 ranges (U+0000AA - U+03347A) using skiplist // Case_Ignorable : 1063 bytes, 2789 codepoints in 459 ranges (U+0000A8 - U+0E01F0) using skiplist -// Cased : 401 bytes, 4580 codepoints in 156 ranges (U+0000AA - U+01F18A) using skiplist // Grapheme_Extend : 899 bytes, 2232 codepoints in 383 ranges (U+000300 - U+0E01F0) using skiplist // Lowercase : 943 bytes, 2569 codepoints in 676 ranges (U+0000AA - U+01E944) using bitset +// Lt : 33 bytes, 31 codepoints in 10 ranges (U+0001C5 - U+001FFD) using skiplist // N : 463 bytes, 1914 codepoints in 145 ranges (U+0000B2 - U+01FBFA) using skiplist // Uppercase : 799 bytes, 1980 codepoints in 659 ranges (U+0000C0 - U+01F18A) using bitset // White_Space : 256 bytes, 19 codepoints in 8 ranges (U+000085 - U+003001) using cascading // to_lower : 1112 bytes, 1462 codepoints in 185 ranges (U+0000C0 - U+01E921) using 2-level LUT // to_upper : 1998 bytes, 1554 codepoints in 299 ranges (U+0000B5 - U+01E943) using 2-level LUT // to_title : 340 bytes, 135 codepoints in 49 ranges (U+0000DF - U+00FB17) using 2-level LUT -// Total : 9997 bytes +// Total : 9629 bytes #[inline(always)] const fn bitset_search< @@ -337,59 +337,6 @@ fn lookup_slow(c: char) -> bool { } } -#[rustfmt::skip] -pub mod cased { - use super::ShortOffsetRunHeader; - - static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 22] = [ - ShortOffsetRunHeader::new(0, 4256), ShortOffsetRunHeader::new(51, 5024), - ShortOffsetRunHeader::new(61, 7296), ShortOffsetRunHeader::new(65, 7958), - ShortOffsetRunHeader::new(74, 9398), ShortOffsetRunHeader::new(149, 11264), - ShortOffsetRunHeader::new(151, 42560), ShortOffsetRunHeader::new(163, 43824), - ShortOffsetRunHeader::new(177, 64256), ShortOffsetRunHeader::new(183, 65313), - ShortOffsetRunHeader::new(187, 66560), ShortOffsetRunHeader::new(191, 67456), - ShortOffsetRunHeader::new(213, 68736), ShortOffsetRunHeader::new(221, 71840), - ShortOffsetRunHeader::new(229, 93760), ShortOffsetRunHeader::new(231, 119808), - ShortOffsetRunHeader::new(237, 120486), ShortOffsetRunHeader::new(274, 122624), - ShortOffsetRunHeader::new(297, 122928), ShortOffsetRunHeader::new(303, 125184), - ShortOffsetRunHeader::new(305, 127280), ShortOffsetRunHeader::new(307, 1241482), - ]; - static OFFSETS: [u8; 313] = [ - 170, 1, 10, 1, 4, 1, 5, 23, 1, 31, 1, 195, 1, 4, 4, 208, 2, 35, 7, 2, 30, 5, 96, 1, 42, 4, - 2, 2, 2, 4, 1, 1, 6, 1, 1, 3, 1, 1, 1, 20, 1, 83, 1, 139, 8, 166, 1, 38, 9, 41, 0, 38, 1, 1, - 5, 1, 2, 43, 1, 4, 0, 86, 2, 6, 0, 11, 5, 43, 2, 3, 64, 192, 64, 0, 2, 6, 2, 38, 2, 6, 2, 8, - 1, 1, 1, 1, 1, 1, 1, 31, 2, 53, 1, 7, 1, 1, 3, 3, 1, 7, 3, 4, 2, 6, 4, 13, 5, 3, 1, 7, 116, - 1, 13, 1, 16, 13, 101, 1, 4, 1, 2, 10, 1, 1, 3, 5, 6, 1, 1, 1, 1, 1, 1, 4, 1, 6, 4, 1, 2, 4, - 5, 5, 4, 1, 17, 32, 3, 2, 0, 52, 0, 229, 6, 4, 3, 2, 12, 38, 1, 1, 5, 1, 0, 46, 18, 30, 132, - 102, 3, 4, 1, 77, 20, 6, 1, 3, 0, 43, 1, 14, 6, 80, 0, 7, 12, 5, 0, 26, 6, 26, 0, 80, 96, - 36, 4, 36, 116, 11, 1, 15, 1, 7, 1, 2, 1, 11, 1, 15, 1, 7, 1, 2, 0, 1, 2, 3, 1, 42, 1, 9, 0, - 51, 13, 51, 93, 22, 10, 22, 0, 64, 0, 64, 32, 25, 2, 25, 0, 85, 1, 71, 1, 2, 2, 1, 2, 2, 2, - 4, 1, 12, 1, 1, 1, 7, 1, 65, 1, 4, 2, 8, 1, 7, 1, 28, 1, 4, 1, 5, 1, 1, 3, 7, 1, 0, 2, 25, - 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 31, 1, 25, 1, 8, 0, 10, 1, 20, 6, 6, 0, - 62, 0, 68, 0, 26, 6, 26, 6, 26, 0, - ]; - #[inline] - pub fn lookup(c: char) -> bool { - debug_assert!(!c.is_ascii()); - (c as u32) >= 0xaa && lookup_slow(c) - } - - #[inline(never)] - fn lookup_slow(c: char) -> bool { - const { - assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); - let mut i = 0; - while i < SHORT_OFFSET_RUNS.len() { - assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); - i += 1; - } - } - // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` - // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. - unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } - } -} - #[rustfmt::skip] pub mod grapheme_extend { use super::ShortOffsetRunHeader; @@ -574,6 +521,39 @@ pub const fn lookup(c: char) -> bool { } } +#[rustfmt::skip] +pub mod lt { + use super::ShortOffsetRunHeader; + + static SHORT_OFFSET_RUNS: [ShortOffsetRunHeader; 3] = [ + ShortOffsetRunHeader::new(0, 453), ShortOffsetRunHeader::new(1, 8072), + ShortOffsetRunHeader::new(9, 1122301), + ]; + static OFFSETS: [u8; 21] = [ + 0, 1, 2, 1, 2, 1, 38, 1, 0, 8, 8, 8, 8, 8, 12, 1, 15, 1, 47, 1, 0, + ]; + #[inline] + pub fn lookup(c: char) -> bool { + debug_assert!(!c.is_ascii()); + (c as u32) >= 0x1c5 && lookup_slow(c) + } + + #[inline(never)] + fn lookup_slow(c: char) -> bool { + const { + assert!(SHORT_OFFSET_RUNS.last().unwrap().0 > char::MAX as u32); + let mut i = 0; + while i < SHORT_OFFSET_RUNS.len() { + assert!(SHORT_OFFSET_RUNS[i].start_index() < OFFSETS.len()); + i += 1; + } + } + // SAFETY: We just ensured the last element of `SHORT_OFFSET_RUNS` is greater than `std::char::MAX` + // and the start indices of all elements in `SHORT_OFFSET_RUNS` are smaller than `OFFSETS.len()`. + unsafe { super::skip_search(c, &SHORT_OFFSET_RUNS, &OFFSETS) } + } +} + #[rustfmt::skip] pub mod n { use super::ShortOffsetRunHeader; diff --git a/library/coretests/tests/iter/sources.rs b/library/coretests/tests/iter/sources.rs index 420f3088e6ee..c1df278b5406 100644 --- a/library/coretests/tests/iter/sources.rs +++ b/library/coretests/tests/iter/sources.rs @@ -192,3 +192,19 @@ fn clone(&self) -> Self { let _z = y; assert_eq!(0, *x); } + +#[test] +fn test_repeat_n_default() { + #[derive(Clone)] + pub struct PanicOnDrop; + + impl Drop for PanicOnDrop { + fn drop(&mut self) { + unreachable!() + } + } + + // The default is an empty iterator, so there's never any item to drop. + let iter = RepeatN::::default(); + assert_eq!(iter.count(), 0); +} diff --git a/library/coretests/tests/iter/traits/iterator.rs b/library/coretests/tests/iter/traits/iterator.rs index 5ef1f797ae55..386946461e9f 100644 --- a/library/coretests/tests/iter/traits/iterator.rs +++ b/library/coretests/tests/iter/traits/iterator.rs @@ -619,6 +619,23 @@ fn test_next_chunk() { assert_eq!(it.next_chunk::<0>().unwrap(), []); } +#[test] +fn test_next_chunk_untrusted() { + struct Untrusted(I); + impl Iterator for Untrusted { + type Item = I::Item; + + fn next(&mut self) -> Option { + self.0.next() + } + } + let mut it = Untrusted(0..12); + assert_eq!(it.next_chunk().unwrap(), [0, 1, 2, 3]); + assert_eq!(it.next_chunk().unwrap(), []); + assert_eq!(it.next_chunk().unwrap(), [4, 5, 6, 7, 8, 9]); + assert_eq!(it.next_chunk::<4>().unwrap_err().as_slice(), &[10, 11]); +} + #[test] fn test_collect_into_tuples() { let a = vec![(1, 2, 3), (4, 5, 6), (7, 8, 9)]; diff --git a/library/coretests/tests/lib.rs b/library/coretests/tests/lib.rs index 129d2c013cd2..2c561b5b0529 100644 --- a/library/coretests/tests/lib.rs +++ b/library/coretests/tests/lib.rs @@ -66,11 +66,9 @@ #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] #![feature(int_from_ascii)] -#![feature(int_lowest_highest_one)] #![feature(int_roundings)] #![feature(ip)] #![feature(is_ascii_octdigit)] -#![feature(isolate_most_least_significant_one)] #![feature(iter_advance_by)] #![feature(iter_array_chunks)] #![feature(iter_collect_into)] @@ -119,9 +117,9 @@ #![feature(trusted_random_access)] #![feature(try_blocks)] #![feature(try_find)] +#![feature(try_from_int_error_kind)] #![feature(try_trait_v2)] #![feature(type_info)] -#![feature(uint_bit_width)] #![feature(uint_carryless_mul)] #![feature(uint_gather_scatter_bits)] #![feature(unicode_internals)] diff --git a/library/coretests/tests/nonzero.rs b/library/coretests/tests/nonzero.rs index 861e9e05081f..55d479efb4b4 100644 --- a/library/coretests/tests/nonzero.rs +++ b/library/coretests/tests/nonzero.rs @@ -282,11 +282,11 @@ fn test_nonzero_from_int_on_success() { #[test] fn test_nonzero_from_int_on_err() { - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); - assert!(NonZero::::try_from(0).is_err()); - assert!(NonZero::::try_from(0).is_err()); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); + assert_eq!(NonZero::::try_from(0).unwrap_err().kind(), &IntErrorKind::Zero); } #[test] diff --git a/library/coretests/tests/num/mod.rs b/library/coretests/tests/num/mod.rs index e0214c6ae686..a82ac6fcd45f 100644 --- a/library/coretests/tests/num/mod.rs +++ b/library/coretests/tests/num/mod.rs @@ -374,6 +374,43 @@ fn test_f32f64() { assert!(nan.is_nan()); } +/// Conversions where $source can be represented as bool. +macro_rules! test_impl_try_from_integer_to_bool { + ($fn_name:ident, $source:ty) => { + #[test] + fn $fn_name() { + let max: $source = <$source>::MAX; + let min: $source = <$source>::MIN; + let zero: $source = 0; + let one: $source = 1; + let two: $source = 2; + assert_eq!(bool::try_from(max).unwrap_err().kind(), &IntErrorKind::PosOverflow); + if min != 0 { + assert_eq!(bool::try_from(min).unwrap_err().kind(), &IntErrorKind::NegOverflow); + assert_eq!( + bool::try_from(zero - 1).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); + } + assert_eq!(bool::try_from(zero).unwrap(), false); + assert_eq!(bool::try_from(one).unwrap(), true); + assert_eq!(bool::try_from(two).unwrap_err().kind(), &IntErrorKind::PosOverflow); + } + }; +} + +test_impl_try_from_integer_to_bool! { test_try_u8bool, u8 } +test_impl_try_from_integer_to_bool! { test_try_u16bool, u16 } +test_impl_try_from_integer_to_bool! { test_try_u32bool, u32 } +test_impl_try_from_integer_to_bool! { test_try_u64bool, u64 } +test_impl_try_from_integer_to_bool! { test_try_u128bool, u128 } + +test_impl_try_from_integer_to_bool! { test_try_i8bool, i8 } +test_impl_try_from_integer_to_bool! { test_try_i16bool, i16 } +test_impl_try_from_integer_to_bool! { test_try_i32bool, i32 } +test_impl_try_from_integer_to_bool! { test_try_i64bool, i64 } +test_impl_try_from_integer_to_bool! { test_try_i128bool, i128 } + /// Conversions where the full width of $source can be represented as $target macro_rules! test_impl_try_from_always_ok { ($fn_name:ident, $source:ty, $target: ty) => { @@ -497,9 +534,15 @@ fn $fn_name() { let zero: $source = 0; let neg_one: $source = -1; assert_eq!(<$target as TryFrom<$source>>::try_from(max).unwrap(), max as $target); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); - assert!(<$target as TryFrom<$source>>::try_from(neg_one).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(neg_one).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } }; } @@ -560,7 +603,10 @@ fn $fn_name() { let max = <$source>::MAX; let min = <$source>::MIN; let zero: $source = 0; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(min).unwrap(), min as $target); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); } @@ -623,9 +669,15 @@ fn $fn_name() { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); if min != 0 { - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); } assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( @@ -712,8 +764,14 @@ fn $fn_name() { let zero: $source = 0; let t_max = <$target>::MAX; let t_min = <$target>::MIN; - assert!(<$target as TryFrom<$source>>::try_from(max).is_err()); - assert!(<$target as TryFrom<$source>>::try_from(min).is_err()); + assert_eq!( + <$target as TryFrom<$source>>::try_from(max).unwrap_err().kind(), + &IntErrorKind::PosOverflow + ); + assert_eq!( + <$target as TryFrom<$source>>::try_from(min).unwrap_err().kind(), + &IntErrorKind::NegOverflow + ); assert_eq!(<$target as TryFrom<$source>>::try_from(zero).unwrap(), zero as $target); assert_eq!( <$target as TryFrom<$source>>::try_from(t_max as $source).unwrap(), diff --git a/library/coretests/tests/unicode.rs b/library/coretests/tests/unicode.rs index a8a221db8f95..12eed25a1fea 100644 --- a/library/coretests/tests/unicode.rs +++ b/library/coretests/tests/unicode.rs @@ -60,9 +60,9 @@ fn case_ignorable() { #[test] #[cfg_attr(miri, ignore)] // Miri is too slow -fn cased() { - test_boolean_property(test_data::CASED, unicode_data::cased::lookup); - test_boolean_property(test_data::CASED, char::is_cased); +fn lt() { + test_boolean_property(test_data::LT, unicode_data::lt::lookup); + test_boolean_property(test_data::LT, char::is_titlecase); } #[test] diff --git a/library/coretests/tests/unicode/test_data.rs b/library/coretests/tests/unicode/test_data.rs index 3071aedcae07..962770a0ff83 100644 --- a/library/coretests/tests/unicode/test_data.rs +++ b/library/coretests/tests/unicode/test_data.rs @@ -392,60 +392,6 @@ '\u{e0100}'..='\u{e01ef}', ]; -#[rustfmt::skip] -pub(super) static CASED: &[RangeInclusive; 156] = &[ - '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{c0}'..='\u{d6}', - '\u{d8}'..='\u{f6}', '\u{f8}'..='\u{1ba}', '\u{1bc}'..='\u{1bf}', '\u{1c4}'..='\u{293}', - '\u{296}'..='\u{2b8}', '\u{2c0}'..='\u{2c1}', '\u{2e0}'..='\u{2e4}', '\u{345}'..='\u{345}', - '\u{370}'..='\u{373}', '\u{376}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{37f}'..='\u{37f}', - '\u{386}'..='\u{386}', '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{3a1}', - '\u{3a3}'..='\u{3f5}', '\u{3f7}'..='\u{481}', '\u{48a}'..='\u{52f}', '\u{531}'..='\u{556}', - '\u{560}'..='\u{588}', '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', - '\u{10cd}'..='\u{10cd}', '\u{10d0}'..='\u{10fa}', '\u{10fc}'..='\u{10ff}', - '\u{13a0}'..='\u{13f5}', '\u{13f8}'..='\u{13fd}', '\u{1c80}'..='\u{1c8a}', - '\u{1c90}'..='\u{1cba}', '\u{1cbd}'..='\u{1cbf}', '\u{1d00}'..='\u{1dbf}', - '\u{1e00}'..='\u{1f15}', '\u{1f18}'..='\u{1f1d}', '\u{1f20}'..='\u{1f45}', - '\u{1f48}'..='\u{1f4d}', '\u{1f50}'..='\u{1f57}', '\u{1f59}'..='\u{1f59}', - '\u{1f5b}'..='\u{1f5b}', '\u{1f5d}'..='\u{1f5d}', '\u{1f5f}'..='\u{1f7d}', - '\u{1f80}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fbc}', '\u{1fbe}'..='\u{1fbe}', - '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fcc}', '\u{1fd0}'..='\u{1fd3}', - '\u{1fd6}'..='\u{1fdb}', '\u{1fe0}'..='\u{1fec}', '\u{1ff2}'..='\u{1ff4}', - '\u{1ff6}'..='\u{1ffc}', '\u{2071}'..='\u{2071}', '\u{207f}'..='\u{207f}', - '\u{2090}'..='\u{209c}', '\u{2102}'..='\u{2102}', '\u{2107}'..='\u{2107}', - '\u{210a}'..='\u{2113}', '\u{2115}'..='\u{2115}', '\u{2119}'..='\u{211d}', - '\u{2124}'..='\u{2124}', '\u{2126}'..='\u{2126}', '\u{2128}'..='\u{2128}', - '\u{212a}'..='\u{212d}', '\u{212f}'..='\u{2134}', '\u{2139}'..='\u{2139}', - '\u{213c}'..='\u{213f}', '\u{2145}'..='\u{2149}', '\u{214e}'..='\u{214e}', - '\u{2160}'..='\u{217f}', '\u{2183}'..='\u{2184}', '\u{24b6}'..='\u{24e9}', - '\u{2c00}'..='\u{2ce4}', '\u{2ceb}'..='\u{2cee}', '\u{2cf2}'..='\u{2cf3}', - '\u{2d00}'..='\u{2d25}', '\u{2d27}'..='\u{2d27}', '\u{2d2d}'..='\u{2d2d}', - '\u{a640}'..='\u{a66d}', '\u{a680}'..='\u{a69d}', '\u{a722}'..='\u{a787}', - '\u{a78b}'..='\u{a78e}', '\u{a790}'..='\u{a7dc}', '\u{a7f1}'..='\u{a7f6}', - '\u{a7f8}'..='\u{a7fa}', '\u{ab30}'..='\u{ab5a}', '\u{ab5c}'..='\u{ab69}', - '\u{ab70}'..='\u{abbf}', '\u{fb00}'..='\u{fb06}', '\u{fb13}'..='\u{fb17}', - '\u{ff21}'..='\u{ff3a}', '\u{ff41}'..='\u{ff5a}', '\u{10400}'..='\u{1044f}', - '\u{104b0}'..='\u{104d3}', '\u{104d8}'..='\u{104fb}', '\u{10570}'..='\u{1057a}', - '\u{1057c}'..='\u{1058a}', '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', - '\u{10597}'..='\u{105a1}', '\u{105a3}'..='\u{105b1}', '\u{105b3}'..='\u{105b9}', - '\u{105bb}'..='\u{105bc}', '\u{10780}'..='\u{10780}', '\u{10783}'..='\u{10785}', - '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', '\u{10c80}'..='\u{10cb2}', - '\u{10cc0}'..='\u{10cf2}', '\u{10d50}'..='\u{10d65}', '\u{10d70}'..='\u{10d85}', - '\u{118a0}'..='\u{118df}', '\u{16e40}'..='\u{16e7f}', '\u{16ea0}'..='\u{16eb8}', - '\u{16ebb}'..='\u{16ed3}', '\u{1d400}'..='\u{1d454}', '\u{1d456}'..='\u{1d49c}', - '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', '\u{1d4a5}'..='\u{1d4a6}', - '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b9}', '\u{1d4bb}'..='\u{1d4bb}', - '\u{1d4bd}'..='\u{1d4c3}', '\u{1d4c5}'..='\u{1d505}', '\u{1d507}'..='\u{1d50a}', - '\u{1d50d}'..='\u{1d514}', '\u{1d516}'..='\u{1d51c}', '\u{1d51e}'..='\u{1d539}', - '\u{1d53b}'..='\u{1d53e}', '\u{1d540}'..='\u{1d544}', '\u{1d546}'..='\u{1d546}', - '\u{1d54a}'..='\u{1d550}', '\u{1d552}'..='\u{1d6a5}', '\u{1d6a8}'..='\u{1d6c0}', - '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6fa}', '\u{1d6fc}'..='\u{1d714}', - '\u{1d716}'..='\u{1d734}', '\u{1d736}'..='\u{1d74e}', '\u{1d750}'..='\u{1d76e}', - '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d7a8}', '\u{1d7aa}'..='\u{1d7c2}', - '\u{1d7c4}'..='\u{1d7cb}', '\u{1df00}'..='\u{1df09}', '\u{1df0b}'..='\u{1df1e}', - '\u{1df25}'..='\u{1df2a}', '\u{1e030}'..='\u{1e06d}', '\u{1e900}'..='\u{1e943}', - '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', '\u{1f170}'..='\u{1f189}', -]; - #[rustfmt::skip] pub(super) static GRAPHEME_EXTEND: &[RangeInclusive; 383] = &[ '\u{300}'..='\u{36f}', '\u{483}'..='\u{489}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', @@ -776,6 +722,13 @@ '\u{1e030}'..='\u{1e06d}', '\u{1e922}'..='\u{1e943}', ]; +#[rustfmt::skip] +pub(super) static LT: &[RangeInclusive; 10] = &[ + '\u{1c5}'..='\u{1c5}', '\u{1c8}'..='\u{1c8}', '\u{1cb}'..='\u{1cb}', '\u{1f2}'..='\u{1f2}', + '\u{1f88}'..='\u{1f8f}', '\u{1f98}'..='\u{1f9f}', '\u{1fa8}'..='\u{1faf}', + '\u{1fbc}'..='\u{1fbc}', '\u{1fcc}'..='\u{1fcc}', '\u{1ffc}'..='\u{1ffc}', +]; + #[rustfmt::skip] pub(super) static N: &[RangeInclusive; 145] = &[ '\u{b2}'..='\u{b3}', '\u{b9}'..='\u{b9}', '\u{bc}'..='\u{be}', '\u{660}'..='\u{669}', diff --git a/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md b/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md index 31422b793450..5d354305e56d 100644 --- a/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md +++ b/library/portable-simd/.github/PULL_REQUEST_TEMPLATE.md @@ -10,7 +10,7 @@ For a given vector math operation on TxN, please add tests for interactions with - [ ] 0 -For a given vector math operation on TxN where T is a float, please add tests for test interactions with: +For a given vector math operation on TxN where T is a float, please add tests for interactions with: - [ ] a really large number, larger than the mantissa - [ ] a really small "subnormal" number - [ ] NaN diff --git a/library/portable-simd/Cargo.lock b/library/portable-simd/Cargo.lock index 5a5f0d8907ae..c3b950bd5069 100644 --- a/library/portable-simd/Cargo.lock +++ b/library/portable-simd/Cargo.lock @@ -2,6 +2,17 @@ # It is not intended for manual editing. version = 4 +[[package]] +name = "async-trait" +version = "0.1.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9035ad2d096bed7955a320ee7e2230574d28fd3c3a0f186cbea1ff3c7eed5dbb" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "autocfg" version = "1.5.0" @@ -10,41 +21,43 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "1.3.2" +version = "2.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af" [[package]] name = "bumpalo" -version = "3.19.0" +version = "3.20.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "46c5e41b57b8bba42a04676d81cb89e9ee8e859a1a66f80a5a72e1cb76b34d43" +checksum = "5d20789868f4b01b2f2caec9f5c4e0213b41e3e5702a50157d699ae31ced2fcb" [[package]] -name = "byteorder" -version = "1.5.0" +name = "cast" +version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" +checksum = "37b2a672a2cb129a2e41c10b1224bb368f9f37a2b16b612598138befd7b37eb5" [[package]] name = "cc" -version = "1.2.33" +version = "1.2.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ee0f8803222ba5a7e2777dd72ca451868909b1ac410621b676adf07280e9b5f" +checksum = "e1e928d4b69e3077709075a938a05ffbedfa53a84c8f766efbf8220bb1ff60e1" dependencies = [ + "find-msvc-tools", "shlex", ] [[package]] name = "cfg-if" -version = "1.0.1" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9555578bc9e57714c812a1f84e4fc5b4d21fcb063490c624de019f7464c91268" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "core_simd" version = "0.1.0" dependencies = [ + "getrandom", "proptest", "std_float", "test_helpers", @@ -52,6 +65,12 @@ dependencies = [ "wasm-bindgen-test", ] +[[package]] +name = "find-msvc-tools" +version = "0.1.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" + [[package]] name = "float-cmp" version = "0.10.0" @@ -62,31 +81,98 @@ dependencies = [ ] [[package]] -name = "js-sys" -version = "0.3.77" +name = "futures-core" +version = "0.3.32" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1cfaf33c695fc6e08064efbc1f72ec937429614f25eef83af942d0e227c3a28f" +checksum = "7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d" + +[[package]] +name = "futures-task" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "037711b3d59c33004d3856fbdc83b99d4ff37a24768fa1be9ce3538a1cde4393" + +[[package]] +name = "futures-util" +version = "0.3.32" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "389ca41296e6190b48053de0321d02a77f32f8a5d2461dd38762c0593805c6d6" dependencies = [ + "futures-core", + "futures-task", + "pin-project-lite", + "slab", +] + +[[package]] +name = "getrandom" +version = "0.3.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd" +dependencies = [ + "cfg-if", + "js-sys", + "libc", + "r-efi", + "wasip2", + "wasm-bindgen", +] + +[[package]] +name = "itoa" +version = "1.0.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8f42a60cbdf9a97f5d2305f08a87dc4e09308d1276d28c869c684d7777685682" + +[[package]] +name = "js-sys" +version = "0.3.92" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cc4c90f45aa2e6eacbe8645f77fdea542ac97a494bcd117a67df9ff4d611f995" +dependencies = [ + "cfg-if", + "futures-util", "once_cell", "wasm-bindgen", ] [[package]] -name = "log" -version = "0.4.27" +name = "libc" +version = "0.2.183" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "13dc2df351e3202783a1fe0d44375f7295ffb4049267b0f3018346dc122a1d94" +checksum = "b5b646652bf6661599e1da8901b3b9522896f01e736bad5f723fe7a3a27f899d" + +[[package]] +name = "libm" +version = "0.2.16" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6d2cec3eae94f9f509c767b45932f1ada8350c4bdb85af2fcab4a3c14807981" + +[[package]] +name = "memchr" +version = "2.8.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79" [[package]] name = "minicov" -version = "0.3.7" +version = "0.3.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f27fe9f1cc3c22e1687f9446c2083c4c5fc7f0bcf1c7a86bdbded14985895b4b" +checksum = "4869b6a491569605d66d3952bcdf03df789e5b536e5f0cf7758a7f08a55ae24d" dependencies = [ "cc", "walkdir", ] +[[package]] +name = "nu-ansi-term" +version = "0.50.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7957b9740744892f114936ab4a57b3f487491bbeafaf8083688b16841a4240e5" +dependencies = [ + "windows-sys", +] + [[package]] name = "num-traits" version = "0.2.19" @@ -94,13 +180,26 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" dependencies = [ "autocfg", + "libm", ] [[package]] name = "once_cell" -version = "1.21.3" +version = "1.21.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d" +checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50" + +[[package]] +name = "oorandom" +version = "11.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d6790f58c7ff633d8771f42965289203411a5e5c68388703c06e14f24770b41e" + +[[package]] +name = "pin-project-lite" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd" [[package]] name = "ppv-lite86" @@ -113,52 +212,58 @@ dependencies = [ [[package]] name = "proc-macro2" -version = "1.0.101" +version = "1.0.106" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "89ae43fd86e4158d6db51ad8e2b80f313af9cc74f5c0e03ccb87de09998732de" +checksum = "8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934" dependencies = [ "unicode-ident", ] [[package]] name = "proptest" -version = "0.10.1" +version = "1.11.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "12e6c80c1139113c28ee4670dc50cc42915228b51f56a9e407f0ec60f966646f" +checksum = "4b45fcc2344c680f5025fe57779faef368840d0bd1f42f216291f0dc4ace4744" dependencies = [ "bitflags", - "byteorder", "num-traits", "rand", "rand_chacha", "rand_xorshift", + "regex-syntax", + "unarray", ] [[package]] name = "quote" -version = "1.0.40" +version = "1.0.45" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1885c039570dc00dcb4ff087a89e185fd56bae234ddc7f056a945bf36467248d" +checksum = "41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924" dependencies = [ "proc-macro2", ] [[package]] -name = "rand" -version = "0.7.3" +name = "r-efi" +version = "5.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6a6b1679d49b24bbfe0c803429aa1874472f50d9b363131f0e89fc356b544d03" +checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f" + +[[package]] +name = "rand" +version = "0.9.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6db2770f06117d490610c7488547d543617b21bfa07796d7a12f6f1bd53850d1" dependencies = [ "rand_chacha", "rand_core", - "rand_hc", ] [[package]] name = "rand_chacha" -version = "0.2.2" +version = "0.9.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f4c8ed856279c9737206bf725bf36935d8666ead7aa69b52be55af369d193402" +checksum = "d3022b5f1df60f26e1ffddd6c66e8aa15de382ae63b3a0c1bfc0e4d3e3f325cb" dependencies = [ "ppv-lite86", "rand_core", @@ -166,28 +271,28 @@ dependencies = [ [[package]] name = "rand_core" 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"zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.26" +version = "0.8.48" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9ecf5b4cc5364572d7f4c329661bcc82724222973f2cab6f050a4e5c22f75181" +checksum = "70e3cd084b1788766f53af483dd21f93881ff30d7320490ec3ef7526d203bad4" dependencies = [ "proc-macro2", "quote", "syn", ] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/library/portable-simd/Cargo.toml b/library/portable-simd/Cargo.toml index 21d4584a9f4d..883140bae3f6 100644 --- a/library/portable-simd/Cargo.toml +++ b/library/portable-simd/Cargo.toml @@ -11,3 +11,8 @@ opt-level = 2 [profile.test.package.test_helpers] opt-level = 2 + +[workspace.dependencies.proptest] +version = "1.11" +default-features = false +features = ["alloc", "f16"] diff --git a/library/portable-simd/beginners-guide.md b/library/portable-simd/beginners-guide.md index 4250a18315a6..c56873ea4b8d 100644 --- a/library/portable-simd/beginners-guide.md +++ b/library/portable-simd/beginners-guide.md @@ -56,7 +56,7 @@ The list notes the bit widths available at each feature level, though the operat ### Selecting Additional Target Features -If you want to enable support for a target feature within your build, generally you should use a [target-feature](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-feature) setting within you `RUSTFLAGS` setting. +If you want to enable support for a target feature within your build, generally you should use a [target-feature](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-feature) setting within your `RUSTFLAGS` setting. If you know that you're targeting a specific CPU you can instead use the [target-cpu](https://rust-lang.github.io/packed_simd/perf-guide/target-feature/rustflags.html#target-cpu) flag and the compiler will enable the correct set of features for that CPU. diff --git a/library/portable-simd/crates/core_simd/Cargo.toml b/library/portable-simd/crates/core_simd/Cargo.toml index 537ce459c07c..6e576084ecfb 100644 --- a/library/portable-simd/crates/core_simd/Cargo.toml +++ b/library/portable-simd/crates/core_simd/Cargo.toml @@ -18,9 +18,13 @@ wasm-bindgen = "0.2" wasm-bindgen-test = "0.3" [dev-dependencies.proptest] -version = "0.10" +workspace = true + +# Enable the `wasm_js` feature so that getrandom works on wasm32-unknown-unknown. +[dev-dependencies.getrandom] +version = "0.3.4" default-features = false -features = ["alloc"] +features = ["wasm_js"] [dev-dependencies.test_helpers] path = "../test_helpers" diff --git a/library/portable-simd/crates/core_simd/src/alias.rs b/library/portable-simd/crates/core_simd/src/alias.rs index 23f121c46197..6dcfcb660c26 100644 --- a/library/portable-simd/crates/core_simd/src/alias.rs +++ b/library/portable-simd/crates/core_simd/src/alias.rs @@ -153,6 +153,16 @@ macro_rules! mask_alias { usizex64 64 } + f16 = { + f16x1 1 + f16x2 2 + f16x4 4 + f16x8 8 + f16x16 16 + f16x32 32 + f16x64 64 + } + f32 = { f32x1 1 f32x2 2 diff --git a/library/portable-simd/crates/core_simd/src/cast.rs b/library/portable-simd/crates/core_simd/src/cast.rs index 1c3592f80757..69dc7ba50d58 100644 --- a/library/portable-simd/crates/core_simd/src/cast.rs +++ b/library/portable-simd/crates/core_simd/src/cast.rs @@ -44,6 +44,9 @@ impl SimdCast for u64 {} unsafe impl Sealed for usize {} impl SimdCast for usize {} // Safety: primitive number types can be cast to other primitive number types +unsafe impl Sealed for f16 {} +impl SimdCast for f16 {} +// Safety: primitive number types can be cast to other primitive number types unsafe impl Sealed for f32 {} impl SimdCast for f32 {} // Safety: primitive number types can be cast to other primitive number types diff --git a/library/portable-simd/crates/core_simd/src/lib.rs b/library/portable-simd/crates/core_simd/src/lib.rs index fe26d99b9194..413a886f6c5b 100644 --- a/library/portable-simd/crates/core_simd/src/lib.rs +++ b/library/portable-simd/crates/core_simd/src/lib.rs @@ -1,17 +1,16 @@ #![no_std] #![feature( - const_eval_select, convert_float_to_int, + f16, core_intrinsics, decl_macro, - intra_doc_pointers, repr_simd, - simd_ffi, staged_api, prelude_import, ptr_metadata, rustc_attrs )] +#![cfg_attr(doc, feature(intra_doc_pointers))] #![cfg_attr( all( any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm",), @@ -31,6 +30,7 @@ any(target_arch = "powerpc", target_arch = "powerpc64"), feature(stdarch_powerpc) )] +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really #![deny( unsafe_op_in_unsafe_fn, diff --git a/library/portable-simd/crates/core_simd/src/masks.rs b/library/portable-simd/crates/core_simd/src/masks.rs index 3e2209556b66..a5334afbe5f8 100644 --- a/library/portable-simd/crates/core_simd/src/masks.rs +++ b/library/portable-simd/crates/core_simd/src/masks.rs @@ -371,22 +371,20 @@ pub fn first_set(self) -> Option { // * perform _unsigned_ reduce-min // * check if the result is -1 or an index - let index = Simd::from_array( - const { - let mut index = [0; N]; - let mut i = 0; - while i < N { - index[i] = i; - i += 1; - } - index - }, - ); + let index: Simd = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + // Safety: the input and output are integer vectors + unsafe { core::intrinsics::simd::simd_cast(Simd::from_array(index)) } + }; // Safety: the input and output are integer vectors - let index: Simd = unsafe { core::intrinsics::simd::simd_cast(index) }; - - let masked_index = self.select(index, Self::splat(true).to_simd()); + let masked_index: Simd = + unsafe { core::intrinsics::simd::simd_or((!self).to_simd(), index) }; // Safety: the input and output are integer vectors let masked_index: Simd = diff --git a/library/portable-simd/crates/core_simd/src/ops.rs b/library/portable-simd/crates/core_simd/src/ops.rs index eb6601f73483..c0a06ed46512 100644 --- a/library/portable-simd/crates/core_simd/src/ops.rs +++ b/library/portable-simd/crates/core_simd/src/ops.rs @@ -245,7 +245,7 @@ impl Shr::shr { // We don't need any special precautions here: // Floats always accept arithmetic ops, but may become NaN. for_base_ops! { - T = (f32, f64); + T = (f16, f32, f64); type Lhs = Simd; type Rhs = Simd; type Output = Self; diff --git a/library/portable-simd/crates/core_simd/src/ops/unary.rs b/library/portable-simd/crates/core_simd/src/ops/unary.rs index e1c06167f979..af7aa8a823d9 100644 --- a/library/portable-simd/crates/core_simd/src/ops/unary.rs +++ b/library/portable-simd/crates/core_simd/src/ops/unary.rs @@ -19,6 +19,8 @@ fn neg(self) -> Self::Output { } neg! { + impl Neg for Simd + impl Neg for Simd impl Neg for Simd diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs index d553d6c040c9..76836404cbc4 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs @@ -42,7 +42,7 @@ fn simd_ne(self, other: Self) -> Self::Mask { } } -impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } +impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs index 5672fbbf54ca..5a4e74c753b5 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs @@ -144,7 +144,7 @@ fn simd_ge(self, other: Self) -> Self::Mask { } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } macro_rules! impl_mask { { $($integer:ty),* } => { diff --git a/library/portable-simd/crates/core_simd/src/simd/num/float.rs b/library/portable-simd/crates/core_simd/src/simd/num/float.rs index 175cbce4f58b..510f4c9eea39 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/float.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/float.rs @@ -444,4 +444,4 @@ fn reduce_min(self) -> Self::Scalar { } } -impl_trait! { f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } +impl_trait! { f16 { bits: u16, mask: i16 }, f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } } diff --git a/library/portable-simd/crates/core_simd/src/simd/prelude.rs b/library/portable-simd/crates/core_simd/src/simd/prelude.rs index e5d7a2aeb73d..6e93f16e10b1 100644 --- a/library/portable-simd/crates/core_simd/src/simd/prelude.rs +++ b/library/portable-simd/crates/core_simd/src/simd/prelude.rs @@ -7,7 +7,7 @@ #[doc(no_inline)] pub use super::{ - Mask, Simd, + Mask, Select, Simd, ToBytes, cmp::{SimdOrd, SimdPartialEq, SimdPartialOrd}, num::{SimdFloat, SimdInt, SimdUint}, ptr::{SimdConstPtr, SimdMutPtr}, diff --git a/library/portable-simd/crates/core_simd/src/vector.rs b/library/portable-simd/crates/core_simd/src/vector.rs index 5b3a689f3611..fbef69f267aa 100644 --- a/library/portable-simd/crates/core_simd/src/vector.rs +++ b/library/portable-simd/crates/core_simd/src/vector.rs @@ -363,7 +363,7 @@ pub fn load_or(slice: &[T], or: Self) -> Self { /// corresponding element in `enable` is `true`. /// /// When the element is disabled or out of bounds for the slice, that memory location - /// is not accessed and the corresponding value from `or` is passed through. + /// is not accessed and the default value for the element type is returned. /// /// # Examples /// ``` @@ -371,12 +371,11 @@ pub fn load_or(slice: &[T], or: Self) -> Self { /// # #[cfg(feature = "as_crate")] use core_simd::simd; /// # #[cfg(not(feature = "as_crate"))] use core::simd; /// # use simd::{Simd, Mask}; - /// let vec: Vec = vec![10, 11, 12, 13, 14, 15, 16, 17, 18]; - /// let enable = Mask::from_array([true, true, false, true]); - /// let or = Simd::from_array([-5, -4, -3, -2]); + /// let vec: Vec = vec![10, 11, 12]; + /// let enable = Mask::from_array([false, true, true, true]); /// - /// let result = Simd::load_select(&vec, enable, or); - /// assert_eq!(result, Simd::from_array([10, 11, -3, 13])); + /// let result = Simd::load_select_or_default(&vec, enable); + /// assert_eq!(result, Simd::from_array([0, 11, 12, 0])); /// ``` #[must_use] #[inline] @@ -1147,6 +1146,13 @@ unsafe impl SimdElement for isize { type Mask = isize; } +impl Sealed for f16 {} + +// Safety: f16 is a valid SIMD element type, and is supported by this API +unsafe impl SimdElement for f16 { + type Mask = i16; +} + impl Sealed for f32 {} // Safety: f32 is a valid SIMD element type, and is supported by this API diff --git a/library/portable-simd/crates/core_simd/src/vendor.rs b/library/portable-simd/crates/core_simd/src/vendor.rs index 57536e4fc77d..6b3c640c2f7c 100644 --- a/library/portable-simd/crates/core_simd/src/vendor.rs +++ b/library/portable-simd/crates/core_simd/src/vendor.rs @@ -32,3 +32,6 @@ fn from(value: $from) -> $to { #[cfg(target_arch = "loongarch64")] mod loongarch64; + +#[cfg(target_arch = "hexagon")] +mod hexagon; diff --git a/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs b/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs new file mode 100644 index 000000000000..2b8ea55fde65 --- /dev/null +++ b/library/portable-simd/crates/core_simd/src/vendor/hexagon.rs @@ -0,0 +1,40 @@ +//! Conversions to Hexagon HVX SIMD types. + +use crate::simd::*; + +// HVX 128-byte mode (1024-bit vectors) +// Enable with: -C target-feature=+hvx-length128b +#[cfg(target_feature = "hvx-length128b")] +mod hvx_128b { + use super::*; + use core::arch::hexagon::v128::HvxVector; + + // Full vectors (1024-bit) map to HvxVector + from_transmute! { unsafe u16x64 => HvxVector } + from_transmute! { unsafe i16x64 => HvxVector } + from_transmute! { unsafe u32x32 => HvxVector } + from_transmute! { unsafe i32x32 => HvxVector } + from_transmute! { unsafe u64x16 => HvxVector } + from_transmute! { unsafe i64x16 => HvxVector } + + // FIXME: u8x128/i8x128 don't exist in portable-simd (max lane count is 64) + // u8x64/i8x64 are only 512-bit (half of HvxVector in 128B mode) +} + +// HVX 64-byte mode (512-bit vectors) +// Default when hvx-length128b is not specified +#[cfg(not(target_feature = "hvx-length128b"))] +mod hvx_64b { + use super::*; + use core::arch::hexagon::v64::HvxVector; + + // Full vectors (512-bit) map to HvxVector + from_transmute! { unsafe u8x64 => HvxVector } + from_transmute! { unsafe i8x64 => HvxVector } + from_transmute! { unsafe u16x32 => HvxVector } + from_transmute! { unsafe i16x32 => HvxVector } + from_transmute! { unsafe u32x16 => HvxVector } + from_transmute! { unsafe i32x16 => HvxVector } + from_transmute! { unsafe u64x8 => HvxVector } + from_transmute! { unsafe i64x8 => HvxVector } +} diff --git a/library/portable-simd/crates/core_simd/tests/f16_ops.rs b/library/portable-simd/crates/core_simd/tests/f16_ops.rs new file mode 100644 index 000000000000..f89bdf4738f8 --- /dev/null +++ b/library/portable-simd/crates/core_simd/tests/f16_ops.rs @@ -0,0 +1,10 @@ +#![feature(portable_simd)] +#![feature(f16)] + +#[macro_use] +mod ops_macros; + +// FIXME: some f16 operations cause rustc to hang on wasm simd +// https://github.com/llvm/llvm-project/issues/189251 +#[cfg(not(all(target_arch = "wasm32", target_feature = "simd128")))] +impl_float_tests! { f16, i16 } diff --git a/library/portable-simd/crates/core_simd/tests/masks.rs b/library/portable-simd/crates/core_simd/tests/masks.rs index 53fb2367b605..98a74be8e395 100644 --- a/library/portable-simd/crates/core_simd/tests/masks.rs +++ b/library/portable-simd/crates/core_simd/tests/masks.rs @@ -133,6 +133,19 @@ fn cast_impl() cast_impl::(); cast_impl::(); } + + #[test] + fn first_set() { + for bitmask in 0..=u8::MAX { + let mask = Mask::<$type, 8>::from_bitmask(bitmask as u64); + let expected = if bitmask == 0 { + None + } else { + Some(bitmask.trailing_zeros() as usize) + }; + assert_eq!(mask.first_set(), expected); + } + } } } } diff --git a/library/portable-simd/crates/core_simd/tests/round.rs b/library/portable-simd/crates/core_simd/tests/round.rs index 4c1ac3c36f89..95b17f415822 100644 --- a/library/portable-simd/crates/core_simd/tests/round.rs +++ b/library/portable-simd/crates/core_simd/tests/round.rs @@ -42,6 +42,14 @@ fn trunc() { ) } + fn round_ties_even() { + test_helpers::test_unary_elementwise( + &Vector::::round_ties_even, + &Scalar::round_ties_even, + &|_| true, + ) + } + fn fract() { test_helpers::test_unary_elementwise_flush_subnormals( &Vector::::fract, diff --git a/library/portable-simd/crates/std_float/src/lib.rs b/library/portable-simd/crates/std_float/src/lib.rs index b269efc9b1d7..ff3525452231 100644 --- a/library/portable-simd/crates/std_float/src/lib.rs +++ b/library/portable-simd/crates/std_float/src/lib.rs @@ -2,6 +2,7 @@ feature = "as_crate", feature(core_intrinsics), feature(portable_simd), + feature(f16), allow(internal_features) )] #[cfg(not(feature = "as_crate"))] @@ -156,14 +157,30 @@ fn trunc(self) -> Self { unsafe { intrinsics::simd_trunc(self) } } + /// Rounds each element to the nearest integer-valued float. + /// Ties are resolved by rounding to the number with an even least significant digit. + #[must_use = "method returns a new vector and does not mutate the original value"] + #[inline] + fn round_ties_even(self) -> Self { + unsafe { intrinsics::simd_round_ties_even(self) } + } + /// Returns the floating point's fractional value, with its integer part removed. #[must_use = "method returns a new vector and does not mutate the original value"] fn fract(self) -> Self; } +impl Sealed for Simd {} impl Sealed for Simd {} impl Sealed for Simd {} +impl StdFloat for Simd { + #[inline] + fn fract(self) -> Self { + self - self.trunc() + } +} + impl StdFloat for Simd { #[inline] fn fract(self) -> Self { diff --git a/library/portable-simd/crates/std_float/tests/float.rs b/library/portable-simd/crates/std_float/tests/float.rs index c608ba49564e..0fa5da3dca50 100644 --- a/library/portable-simd/crates/std_float/tests/float.rs +++ b/library/portable-simd/crates/std_float/tests/float.rs @@ -25,7 +25,7 @@ fn $func() { &core_simd::simd::Simd::<$scalar, LANES>::$func, &$scalar::$func, &|_| true, - 8, + 16, ) } )* @@ -71,7 +71,7 @@ macro_rules! impl_tests { mod $scalar { use std_float::StdFloat; - unary_test! { $scalar, sqrt, ceil, floor, round, trunc } + unary_test! { $scalar, sqrt, ceil, floor, round, trunc, round_ties_even } ternary_test! { $scalar, mul_add } // https://github.com/rust-lang/miri/issues/3555 diff --git a/library/portable-simd/crates/test_helpers/Cargo.toml b/library/portable-simd/crates/test_helpers/Cargo.toml index 408bb04c7aa4..da7ef7bd9945 100644 --- a/library/portable-simd/crates/test_helpers/Cargo.toml +++ b/library/portable-simd/crates/test_helpers/Cargo.toml @@ -5,5 +5,5 @@ edition = "2021" publish = false [dependencies] -proptest = { version = "0.10", default-features = false, features = ["alloc"] } +proptest = { workspace = true, features = ["alloc", "std"] } float-cmp = "0.10" diff --git a/library/portable-simd/crates/test_helpers/src/biteq.rs b/library/portable-simd/crates/test_helpers/src/biteq.rs index cbc20cda0d62..36761e37dea7 100644 --- a/library/portable-simd/crates/test_helpers/src/biteq.rs +++ b/library/portable-simd/crates/test_helpers/src/biteq.rs @@ -53,7 +53,7 @@ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { }; } -impl_float_biteq! { f32, f64 } +impl_float_biteq! { f16, f32, f64 } impl BitEq for *const T { fn biteq(&self, other: &Self) -> bool { diff --git a/library/portable-simd/crates/test_helpers/src/lib.rs b/library/portable-simd/crates/test_helpers/src/lib.rs index eb3d3f68bc2e..82adb06d8a9d 100644 --- a/library/portable-simd/crates/test_helpers/src/lib.rs +++ b/library/portable-simd/crates/test_helpers/src/lib.rs @@ -1,7 +1,7 @@ -#![feature(powerpc_target_feature)] +#![feature(f16)] #![cfg_attr( any(target_arch = "powerpc", target_arch = "powerpc64"), - feature(stdarch_powerpc) + feature(powerpc_target_feature, stdarch_powerpc) )] pub mod array; @@ -47,6 +47,7 @@ fn default_strategy() -> Self::Strategy { impl_num! { u32 } impl_num! { u64 } impl_num! { usize } +impl_num! { f16 } impl_num! { f32 } impl_num! { f64 } diff --git a/library/portable-simd/crates/test_helpers/src/subnormals.rs b/library/portable-simd/crates/test_helpers/src/subnormals.rs index b5f19ba47b81..44dfbb3d6c95 100644 --- a/library/portable-simd/crates/test_helpers/src/subnormals.rs +++ b/library/portable-simd/crates/test_helpers/src/subnormals.rs @@ -39,7 +39,7 @@ impl FlushSubnormals for $ty {} } } -impl_float! { f32, f64 } +impl_float! { f16, f32, f64 } impl_else! { i8, i16, i32, i64, isize, u8, u16, u32, u64, usize } /// AltiVec should flush subnormal inputs to zero, but QEMU seems to only flush outputs. diff --git a/library/portable-simd/rust-toolchain.toml b/library/portable-simd/rust-toolchain.toml index 639d07df7337..6a58e59fb93e 100644 --- a/library/portable-simd/rust-toolchain.toml +++ b/library/portable-simd/rust-toolchain.toml @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2026-01-26" +channel = "nightly-2026-03-18" components = ["rustfmt", "clippy", "miri", "rust-src"] diff --git a/library/portable-simd/triagebot.toml b/library/portable-simd/triagebot.toml new file mode 100644 index 000000000000..43048b5e4514 --- /dev/null +++ b/library/portable-simd/triagebot.toml @@ -0,0 +1,44 @@ +## See for documentation +## of these features. + +# Allow users to use labels commands. +# Documentation at: https://forge.rust-lang.org/triagebot/labeling.html +[relabel] +allow-unauthenticated = [ + "A-*", + "C-*", + "E-*", + "F-*", + "I-*", + "ISA-*", + "O-*", +] + +# Allow users to assign 'r?` someone to an issue or PR. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-assignment.html +[assign] +warn_non_default_branch = true + +# Warns when a PR contains merge commits +# Documentation at: https://forge.rust-lang.org/triagebot/no-merge.html +[no-merges] +exclude_titles = ["Sync from"] + +# Canonicalize issue numbers to avoid closing the wrong issue +# when commits are included in upstream sync, as well as warning links in commits. +# Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html +[issue-links] +check-commits = "uncanonicalized" + +# Enable issue transfers within the org +# Documentation at: https://forge.rust-lang.org/triagebot/transfer.html +[transfer] + +# Enable comments linking to triagebot range-diff when a PR is rebased +# onto a different base commit +# Documentation at: https://forge.rust-lang.org/triagebot/range-diff.html +[range-diff] + +# Add link to the review body to review changes since posting it. +# Documentation at: https://forge.rust-lang.org/triagebot/review-changes-since.html +[review-changes-since] diff --git a/library/proc_macro/src/bridge/arena.rs b/library/proc_macro/src/bridge/arena.rs index 5e0393e98fdd..d4879021f9d8 100644 --- a/library/proc_macro/src/bridge/arena.rs +++ b/library/proc_macro/src/bridge/arena.rs @@ -58,11 +58,10 @@ fn grow(&self, additional: usize) { // Also ensure that this chunk can fit `additional`. new_cap = cmp::max(additional, new_cap); - let mut chunk = Box::new_uninit_slice(new_cap); + let chunk = chunks.push_mut(Box::new_uninit_slice(new_cap)); let Range { start, end } = chunk.as_mut_ptr_range(); self.start.set(start); self.end.set(end); - chunks.push(chunk); } /// Allocates a byte slice with specified size from the current memory diff --git a/library/proc_macro/src/bridge/rpc.rs b/library/proc_macro/src/bridge/rpc.rs index 7fee8654bc78..2ada18205673 100644 --- a/library/proc_macro/src/bridge/rpc.rs +++ b/library/proc_macro/src/bridge/rpc.rs @@ -244,6 +244,14 @@ pub fn as_str(&self) -> Option<&str> { PanicMessage::Unknown => None, } } + + pub fn into_string(self) -> Option { + match self { + PanicMessage::StaticStr(s) => Some(s.into()), + PanicMessage::String(s) => Some(s), + PanicMessage::Unknown => None, + } + } } impl Encode for PanicMessage { diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml index f7bc729598cd..ebd09f31e25a 100644 --- a/library/std/Cargo.toml +++ b/library/std/Cargo.toml @@ -20,7 +20,7 @@ panic_unwind = { path = "../panic_unwind", optional = true } panic_abort = { path = "../panic_abort" } core = { path = "../core", public = true } unwind = { path = "../unwind" } -hashbrown = { version = "0.16.1", default-features = false, features = [ +hashbrown = { version = "0.17.0", default-features = false, features = [ 'rustc-dep-of-std', ] } std_detect = { path = "../std_detect", public = true } @@ -33,7 +33,7 @@ miniz_oxide = { version = "0.8.0", optional = true, default-features = false } addr2line = { version = "0.25.0", optional = true, default-features = false } [target.'cfg(not(all(windows, target_env = "msvc")))'.dependencies] -libc = { version = "0.2.183", default-features = false, features = [ +libc = { version = "0.2.185", default-features = false, features = [ 'rustc-dep-of-std', ], public = true } @@ -79,19 +79,19 @@ hermit-abi = { version = "0.5.0", features = [ ], public = true } [target.'cfg(all(target_os = "wasi", target_env = "p1"))'.dependencies] -wasi = { version = "0.11.0", features = [ +wasip1 = { version = "1.0.0", features = [ 'rustc-dep-of-std', ], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p2"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip2 = { version = '1.0.2', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(all(target_os = "wasi", target_env = "p3"))'.dependencies] -wasip2 = { version = '0.14.4', features = [ +wasip2 = { version = '1.0.2', features = [ 'rustc-dep-of-std', -], default-features = false, package = 'wasi' } +], default-features = false } [target.'cfg(target_os = "uefi")'.dependencies] r-efi = { version = "5.2.0", features = ['rustc-dep-of-std'] } diff --git a/library/std/src/collections/hash/map.rs b/library/std/src/collections/hash/map.rs index 4192254f6c82..4d190d90ca73 100644 --- a/library/std/src/collections/hash/map.rs +++ b/library/std/src/collections/hash/map.rs @@ -20,7 +20,7 @@ /// reasonable best-effort is made to generate this seed from a high quality, /// secure source of randomness provided by the host without blocking the /// program. Because of this, the randomness of the seed depends on the output -/// quality of the system's random number coroutine when the seed is created. +/// quality of the system's random number generator when the seed is created. /// In particular, seeds generated when the system's entropy pool is abnormally /// low such as during system boot may be of a lower quality. /// diff --git a/library/std/src/fs.rs b/library/std/src/fs.rs index 9643d3fcae66..c75f005f1802 100644 --- a/library/std/src/fs.rs +++ b/library/std/src/fs.rs @@ -2896,7 +2896,7 @@ pub fn copy, Q: AsRef>(from: P, to: Q) -> io::Result { /// /// # Platform-specific behavior /// -/// This function currently corresponds the `CreateHardLink` function on Windows. +/// This function currently corresponds to the `CreateHardLink` function on Windows. /// On most Unix systems, it corresponds to the `linkat` function with no flags. /// On Android, VxWorks, and Redox, it instead corresponds to the `link` function. /// On MacOS, it uses the `linkat` function if it is available, but on very old diff --git a/library/std/src/fs/tests.rs b/library/std/src/fs/tests.rs index cdb12cd0ba03..7b53f2ead1c0 100644 --- a/library/std/src/fs/tests.rs +++ b/library/std/src/fs/tests.rs @@ -1731,6 +1731,8 @@ fn create_dir_all_with_junctions() { #[test] fn metadata_access_times() { + let start_time = SystemTime::now(); + let tmpdir = tmpdir(); let b = tmpdir.join("b"); @@ -1751,7 +1753,14 @@ fn metadata_access_times() { if cfg!(target_os = "linux") { // Not always available match (a.created(), b.created()) { - (Ok(t1), Ok(t2)) => assert!(t1 <= t2), + // It could be that, when the system clock goes backwards (e.g., due time change) + // b, that gets created after a, has a greater creation date than a. + // When such rare case occurs we skip the test, since the test to check that b + // should be created after a would fail. + (Ok(t1), Ok(t2)) => match start_time.elapsed() { + Ok(_) => assert!(t1 <= t2), + Err(_) => {} + }, (Err(e1), Err(e2)) if e1.kind() == ErrorKind::Uncategorized && e2.kind() == ErrorKind::Uncategorized diff --git a/library/std/src/io/buffered/bufreader/buffer.rs b/library/std/src/io/buffered/bufreader/buffer.rs index 6982000c4a02..314f39225e65 100644 --- a/library/std/src/io/buffered/bufreader/buffer.rs +++ b/library/std/src/io/buffered/bufreader/buffer.rs @@ -21,11 +21,11 @@ pub struct Buffer { // Each call to `fill_buf` sets `filled` to indicate how many bytes at the start of `buf` are // initialized with bytes from a read. filled: usize, - // This is the max number of bytes returned across all `fill_buf` calls. We track this so that we - // can accurately tell `read_buf` how many bytes of buf are initialized, to bypass as much of its - // defensive initialization as possible. Note that while this often the same as `filled`, it - // doesn't need to be. Calls to `fill_buf` are not required to actually fill the buffer, and - // omitting this is a huge perf regression for `Read` impls that do not. + // Whether `buf` has been fully initialized. We track this so that we can accurately tell + // `read_buf` how many bytes of buf are initialized, to bypass as much of its defensive + // initialization as possible. Note that while this often the same as `filled`, it doesn't need + // to be. Calls to `fill_buf` are not required to actually fill the buffer, and omitting this + // is a huge perf regression for `Read` impls that do not. initialized: bool, } @@ -112,6 +112,9 @@ pub fn read_more(&mut self, mut reader: impl Read) -> io::Result { let mut buf = BorrowedBuf::from(&mut self.buf[self.filled..]); if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. unsafe { buf.set_init() }; } @@ -138,9 +141,11 @@ pub fn fill_buf(&mut self, mut reader: impl Read) -> io::Result<&[u8]> { debug_assert!(self.pos == self.filled); let mut buf = BorrowedBuf::from(&mut *self.buf); - // SAFETY: `self.filled` bytes will always have been initialized. if self.initialized { + // SAFETY: `self.initialized` is only set after `self.buf` was + // fully initialized, and once `self.buf` is fully initialized + // no part will become uninitialized. unsafe { buf.set_init() }; } diff --git a/library/std/src/io/mod.rs b/library/std/src/io/mod.rs index e449545ce17a..1166ba8baf43 100644 --- a/library/std/src/io/mod.rs +++ b/library/std/src/io/mod.rs @@ -3087,8 +3087,9 @@ fn read_buf(&mut self, mut buf: BorrowedCursor<'_>) -> Result<()> { let mut sliced_buf: BorrowedBuf<'_> = ibuf.into(); - // SAFETY: extra_init bytes of ibuf are known to be initialized if is_init { + // SAFETY: `sliced_buf` is a subslice of `buf`, so if `buf` was initialized then + // `sliced_buf` is. unsafe { sliced_buf.set_init() }; } diff --git a/library/std/src/keyword_docs.rs b/library/std/src/keyword_docs.rs index dc0d11b07a9f..1c8927435c3a 100644 --- a/library/std/src/keyword_docs.rs +++ b/library/std/src/keyword_docs.rs @@ -418,7 +418,7 @@ mod else_keyword {} /// The first enum shown is the usual kind of enum you'd find in a C-style language. The second /// shows off a hypothetical example of something storing location data, with `Coord` being any /// other type that's needed, for example a struct. The third example demonstrates the kind of -/// data a variant can store, ranging from nothing, to a tuple, to an anonymous struct. +/// data a variant can store, ranging from nothing, to a tuple, to a struct-like variant. /// /// Instantiating enum variants involves explicitly using the enum's name as its namespace, /// followed by one of its variants. `SimpleEnum::SecondVariant` would be an example from above. @@ -2042,10 +2042,19 @@ mod type_keyword {} /// system. /// /// The `unsafe` keyword has two uses: -/// - to declare the existence of contracts the compiler can't check (`unsafe fn` and `unsafe -/// trait`), -/// - and to declare that a programmer has checked that these contracts have been upheld (`unsafe -/// {}` and `unsafe impl`, but also `unsafe fn` -- see below). +/// - to declare the existence of contracts the compiler can't check, +/// - and to declare that a programmer has checked that these contracts have been upheld. +/// +/// Typically, each `unsafe` is either of the first or second kind: `unsafe fn` and `unsafe trait` +/// declare the existence of an unsafe contract; `unsafe {}` and `unsafe impl` declare that an +/// unsafe contract (which must have been declared elsewhere) is being upheld. +/// +/// However, historically, these two are not mutually exclusive: the body of an `unsafe fn` is, on +/// old editions, treated like an unsafe block, which means that this use of `unsafe` both declares +/// the existence of a contract to call the current function, and declares that the contracts of the +/// unsafe operations inside this function are being upheld. The `unsafe_op_in_unsafe_fn` lint can +/// be enabled to change that and make `unsafe fn` only play the former role. That lint is enabled +/// by default since edition 2024. /// /// # Unsafe abilities /// @@ -2088,6 +2097,13 @@ mod type_keyword {} /// - `unsafe impl`: the contract necessary to implement the trait has been /// checked by the programmer and is guaranteed to be respected. /// +/// On old editions, `unsafe fn` also acts like an `unsafe {}` block around the code inside the +/// function. This means it is not just a signal to the caller, but also promises that the +/// preconditions for the operations inside the function are upheld. Mixing these two meanings can +/// be confusing, so the `unsafe_op_in_unsafe_fn` lint has been introduced and enabled by default +/// since edition 2024 to warn against that and require explicit unsafe blocks even inside `unsafe +/// fn`. +/// /// See the [Rustonomicon] and the [Reference] for more information. /// /// # Examples diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs index e6467dd0546a..faac8d9e51fd 100644 --- a/library/std/src/lib.rs +++ b/library/std/src/lib.rs @@ -347,6 +347,7 @@ #![feature(ip)] #![feature(iter_advance_by)] #![feature(iter_next_chunk)] +#![feature(maybe_dangling)] #![feature(maybe_uninit_array_assume_init)] #![feature(maybe_uninit_fill)] #![feature(panic_can_unwind)] @@ -418,6 +419,13 @@ // tidy-alphabetical-end // #![default_lib_allocator] +// Removed features +#![unstable_removed( + feature = "concat_idents", + reason = "Replaced by the macro_metavar_expr_concat feature", + link = "https://github.com/rust-lang/rust/issues/29599#issuecomment-2986866250", + since = "1.90.0" +)] // The Rust prelude // The compiler expects the prelude definition to be defined before its use statement. @@ -538,7 +546,7 @@ pub use core::pin; #[stable(feature = "rust1", since = "1.0.0")] pub use core::ptr; -#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "new_range_api", since = "1.96.0")] pub use core::range; #[stable(feature = "rust1", since = "1.0.0")] pub use core::result; diff --git a/library/std/src/macros.rs b/library/std/src/macros.rs index 108cd3cd98eb..a23aa0d87701 100644 --- a/library/std/src/macros.rs +++ b/library/std/src/macros.rs @@ -369,7 +369,8 @@ macro_rules! dbg { /// E.g. `dbg_internal!(() () (1, 2))` expands into /// ```rust, ignore /// match (1, 2) { -/// (tmp_1, tmp_2) => { +/// args => { +/// let (tmp_1, tmp_2) = args; /// eprint!("...", &tmp_1, &tmp_2, /* some other arguments */); /// (tmp_1, tmp_2) /// } @@ -385,7 +386,9 @@ macro_rules! dbg { // of temporaries - https://stackoverflow.com/a/48732525/1063961 // Always put the arguments in a tuple to avoid an unused parens lint on the pattern. match ($($processed,)+) { - ($($bound,)+) => { + // Move the entire tuple so it doesn't stick around as a temporary (#154988). + args => { + let ($($bound,)+) = args; $crate::eprint!( $crate::concat!($($piece),+), $( diff --git a/library/std/src/macros/tests.rs b/library/std/src/macros/tests.rs index db2be925ff30..230bfdf3c983 100644 --- a/library/std/src/macros/tests.rs +++ b/library/std/src/macros/tests.rs @@ -1,5 +1,7 @@ // ignore-tidy-dbg +use core::fmt::Debug; + /// Test for : /// `dbg!` shouldn't drop arguments' temporaries. #[test] @@ -11,3 +13,25 @@ fn temp() {} *dbg!(0, &temp()).1; *dbg!(0, &temp(), 2).1; } + +/// Test for : +/// `dbg!` shouldn't create a temporary that lives past its invocation. +#[test] +fn no_leaking_internal_temps_from_dbg() { + #[derive(Debug)] + struct Foo; + + #[derive(Debug)] + struct Bar<'a>(#[allow(unused)] &'a Foo); + impl Drop for Bar<'_> { + fn drop(&mut self) {} + } + + let foo = Foo; + let bar = Bar(&foo); + // If `dbg!` creates a `(Bar<'_>,)` temporary that lasts past its expansion, this will fail + // to compile, because it will be dropped after `foo`, which it borrows from. The tuple + // mimics the drop order of block tail expressions before Rust 2024: first the result of `dbg!` + // is dropped, then `foo`, then any temporaries left over from `dbg!` are dropped, if present. + (drop(dbg!(bar)), drop(foo)); +} diff --git a/library/std/src/net/tcp.rs b/library/std/src/net/tcp.rs index dac568e419f3..a8046a5541c5 100644 --- a/library/std/src/net/tcp.rs +++ b/library/std/src/net/tcp.rs @@ -582,8 +582,8 @@ pub fn take_error(&self) -> io::Result> { /// to be retried, an error with kind [`io::ErrorKind::WouldBlock`] is /// returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples @@ -988,8 +988,8 @@ pub fn take_error(&self) -> io::Result> { /// IO operation could not be completed and needs to be retried, an error /// with kind [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples diff --git a/library/std/src/net/udp.rs b/library/std/src/net/udp.rs index 5da6b38037f0..cd925b9bdfdf 100644 --- a/library/std/src/net/udp.rs +++ b/library/std/src/net/udp.rs @@ -786,8 +786,8 @@ pub fn peek(&self, buf: &mut [u8]) -> io::Result { /// and needs to be retried, an error with kind /// [`io::ErrorKind::WouldBlock`] is returned. /// - /// On Unix platforms, calling this method corresponds to calling `fcntl` - /// `FIONBIO`. On Windows calling this method corresponds to calling + /// On most Unix platforms, calling this method corresponds to calling `ioctl` + /// `FIONBIO`. On Windows, calling this method corresponds to calling /// `ioctlsocket` `FIONBIO`. /// /// # Examples diff --git a/library/std/src/os/unix/io/tests.rs b/library/std/src/os/unix/io/tests.rs index fc147730578a..ce5e7aac5a99 100644 --- a/library/std/src/os/unix/io/tests.rs +++ b/library/std/src/os/unix/io/tests.rs @@ -2,8 +2,7 @@ #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types, with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/library/std/src/os/wasi/fs.rs b/library/std/src/os/wasi/fs.rs index 248112cb369d..ffc8737df16f 100644 --- a/library/std/src/os/wasi/fs.rs +++ b/library/std/src/os/wasi/fs.rs @@ -246,13 +246,15 @@ fn write_vectored_at(&self, bufs: &[IoSlice<'_>], offset: u64) -> io::Result io::Result<()> { - unsafe { wasi::fd_fdstat_set_flags(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { + wasip1::fd_fdstat_set_flags(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) + } } #[cfg(target_env = "p1")] fn fdstat_set_rights(&self, rights: u64, inheriting: u64) -> io::Result<()> { unsafe { - wasi::fd_fdstat_set_rights(self.as_raw_fd() as wasi::Fd, rights, inheriting) + wasip1::fd_fdstat_set_rights(self.as_raw_fd() as wasip1::Fd, rights, inheriting) .map_err(err2io) } } @@ -260,12 +262,12 @@ fn fdstat_set_rights(&self, rights: u64, inheriting: u64) -> io::Result<()> { #[cfg(target_env = "p1")] fn advise(&self, offset: u64, len: u64, advice: u8) -> io::Result<()> { let advice = match advice { - a if a == wasi::ADVICE_NORMAL.raw() => wasi::ADVICE_NORMAL, - a if a == wasi::ADVICE_SEQUENTIAL.raw() => wasi::ADVICE_SEQUENTIAL, - a if a == wasi::ADVICE_RANDOM.raw() => wasi::ADVICE_RANDOM, - a if a == wasi::ADVICE_WILLNEED.raw() => wasi::ADVICE_WILLNEED, - a if a == wasi::ADVICE_DONTNEED.raw() => wasi::ADVICE_DONTNEED, - a if a == wasi::ADVICE_NOREUSE.raw() => wasi::ADVICE_NOREUSE, + a if a == wasip1::ADVICE_NORMAL.raw() => wasip1::ADVICE_NORMAL, + a if a == wasip1::ADVICE_SEQUENTIAL.raw() => wasip1::ADVICE_SEQUENTIAL, + a if a == wasip1::ADVICE_RANDOM.raw() => wasip1::ADVICE_RANDOM, + a if a == wasip1::ADVICE_WILLNEED.raw() => wasip1::ADVICE_WILLNEED, + a if a == wasip1::ADVICE_DONTNEED.raw() => wasip1::ADVICE_DONTNEED, + a if a == wasip1::ADVICE_NOREUSE.raw() => wasip1::ADVICE_NOREUSE, _ => { return Err(io::const_error!( io::ErrorKind::InvalidInput, @@ -275,31 +277,35 @@ fn advise(&self, offset: u64, len: u64, advice: u8) -> io::Result<()> { }; unsafe { - wasi::fd_advise(self.as_raw_fd() as wasi::Fd, offset, len, advice).map_err(err2io) + wasip1::fd_advise(self.as_raw_fd() as wasip1::Fd, offset, len, advice).map_err(err2io) } } #[cfg(target_env = "p1")] fn allocate(&self, offset: u64, len: u64) -> io::Result<()> { - unsafe { wasi::fd_allocate(self.as_raw_fd() as wasi::Fd, offset, len).map_err(err2io) } + unsafe { wasip1::fd_allocate(self.as_raw_fd() as wasip1::Fd, offset, len).map_err(err2io) } } #[cfg(target_env = "p1")] fn create_directory>(&self, dir: P) -> io::Result<()> { let path = osstr2str(dir.as_ref().as_ref())?; - unsafe { wasi::path_create_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_create_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } #[cfg(target_env = "p1")] fn remove_file>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_unlink_file(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { wasip1::path_unlink_file(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) } } #[cfg(target_env = "p1")] fn remove_directory>(&self, path: P) -> io::Result<()> { let path = osstr2str(path.as_ref().as_ref())?; - unsafe { wasi::path_remove_directory(self.as_raw_fd() as wasi::Fd, path).map_err(err2io) } + unsafe { + wasip1::path_remove_directory(self.as_raw_fd() as wasip1::Fd, path).map_err(err2io) + } } } @@ -388,11 +394,11 @@ pub fn link, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_link( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_link( + old_fd.as_raw_fd() as wasip1::Fd, old_flags, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -411,10 +417,10 @@ pub fn rename, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_rename( - old_fd.as_raw_fd() as wasi::Fd, + wasip1::path_rename( + old_fd.as_raw_fd() as wasip1::Fd, osstr2str(old_path.as_ref().as_ref())?, - new_fd.as_raw_fd() as wasi::Fd, + new_fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) @@ -432,9 +438,9 @@ pub fn symlink, U: AsRef>( new_path: U, ) -> io::Result<()> { unsafe { - wasi::path_symlink( + wasip1::path_symlink( osstr2str(old_path.as_ref().as_ref())?, - fd.as_raw_fd() as wasi::Fd, + fd.as_raw_fd() as wasip1::Fd, osstr2str(new_path.as_ref().as_ref())?, ) .map_err(err2io) diff --git a/library/std/src/os/wasi/io/tests.rs b/library/std/src/os/wasi/io/tests.rs index c5c6a19a6c88..d18b9fe10cab 100644 --- a/library/std/src/os/wasi/io/tests.rs +++ b/library/std/src/os/wasi/io/tests.rs @@ -2,8 +2,7 @@ #[test] fn test_raw_fd_layout() { - // `OwnedFd` and `BorrowedFd` use `rustc_layout_scalar_valid_range_start` - // and `rustc_layout_scalar_valid_range_end`, with values that depend on + // `OwnedFd` and `BorrowedFd` use pattern types with ranges that depend on // the bit width of `RawFd`. If this ever changes, those values will need // to be updated. assert_eq!(size_of::(), 4); diff --git a/library/std/src/os/wasi/net/mod.rs b/library/std/src/os/wasi/net/mod.rs index 9430cd3b05ee..fd5889bf9b7b 100644 --- a/library/std/src/os/wasi/net/mod.rs +++ b/library/std/src/os/wasi/net/mod.rs @@ -18,6 +18,6 @@ pub trait TcpListenerExt { impl TcpListenerExt for net::TcpListener { fn sock_accept(&self, flags: u16) -> io::Result { - unsafe { wasi::sock_accept(self.as_raw_fd() as wasi::Fd, flags).map_err(err2io) } + unsafe { wasip1::sock_accept(self.as_raw_fd() as wasip1::Fd, flags).map_err(err2io) } } } diff --git a/library/std/src/process.rs b/library/std/src/process.rs index 321b68b3225a..69cbc113bb05 100644 --- a/library/std/src/process.rs +++ b/library/std/src/process.rs @@ -617,21 +617,50 @@ impl Command { /// Builder methods are provided to change these defaults and /// otherwise configure the process. /// - /// If `program` is not an absolute path, the `PATH` will be searched in - /// an OS-defined way. - /// - /// The search path to be used may be controlled by setting the - /// `PATH` environment variable on the Command, - /// but this has some implementation limitations on Windows - /// (see issue #37519). + /// If `program` is not an absolute path, the `PATH` environment variable + /// will be searched in an OS-defined way. /// /// # Platform-specific behavior /// - /// Note on Windows: For executable files with the .exe extension, - /// it can be omitted when specifying the program for this Command. - /// However, if the file has a different extension, - /// a filename including the extension needs to be provided, - /// otherwise the file won't be found. + /// The details below describe the current behavior, but these details + /// may change in future versions of Rust. + /// + /// On Unix, the `PATH` searched comes from the child's environment: + /// + /// - If the environment is unmodified, the child inherits the parent's + /// `PATH` and that is what is searched. + /// - If `PATH` is explicitly set via [`env`], that new value is searched. + /// - If [`env_clear`] or [`env_remove`] removes `PATH` without a + /// replacement, `execvp` falls back to an OS-defined default (typically + /// `/bin:/usr/bin`), **not** the parent's `PATH`. This may fail to find + /// programs that rely on the parent's `PATH`. + /// + /// To avoid surprises, use an absolute path or explicitly set `PATH` on + /// the `Command` when modifying the child's environment. + /// + /// On Windows, Rust resolves the executable path before spawning, rather + /// than passing the name to `CreateProcessW` for resolution. When + /// `program` is not an absolute path, the following locations are searched + /// in order: + /// + /// 1. The child's `PATH`, if explicitly set via [`env`]. + /// 2. The directory of the current executable. + /// 3. The system directory (`GetSystemDirectoryW`). + /// 4. The Windows directory (`GetWindowsDirectoryW`). + /// 5. The parent process's `PATH`. + /// + /// Note: when `PATH` is cleared via [`env_clear`] or [`env_remove`] on + /// Windows, step 1 is skipped but the parent process's `PATH` is still + /// searched at step 5, unlike on Unix. + /// + /// For executable files, the `.exe` extension may be omitted. Files with + /// other extensions must include the extension, otherwise they will not be + /// found. Note that this behavior has some known limitations + /// (see issue #37519). + /// + /// [`env`]: Self::env + /// [`env_remove`]: Self::env_remove + /// [`env_clear`]: Self::env_clear /// /// # Examples /// @@ -2536,6 +2565,10 @@ pub fn abort() -> ! { crate::sys::abort_internal(); } +#[doc(inline)] +#[unstable(feature = "abort_immediate", issue = "154601")] +pub use core::process::abort_immediate; + /// Returns the OS-assigned process identifier associated with this process. /// /// # Examples diff --git a/library/std/src/sync/lazy_lock.rs b/library/std/src/sync/lazy_lock.rs index 9bdde0ae4a53..2f2579e37aaf 100644 --- a/library/std/src/sync/lazy_lock.rs +++ b/library/std/src/sync/lazy_lock.rs @@ -375,7 +375,8 @@ fn deref_mut(&mut self) -> &mut T { } #[stable(feature = "lazy_cell", since = "1.80.0")] -impl Default for LazyLock { +#[rustc_const_unstable(feature = "const_default", issue = "143894")] +impl const Default for LazyLock { /// Creates a new lazy value using `Default` as the initializing function. #[inline] fn default() -> LazyLock { @@ -395,7 +396,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { } } -#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "from_wrapper_impls", since = "1.96.0")] impl From for LazyLock { /// Constructs a `LazyLock` that starts already initialized /// with the provided value. diff --git a/library/std/src/sys/alloc/windows.rs b/library/std/src/sys/alloc/windows.rs index 90da0b7e9965..9336a6ec085a 100644 --- a/library/std/src/sys/alloc/windows.rs +++ b/library/std/src/sys/alloc/windows.rs @@ -118,6 +118,9 @@ unsafe fn allocate(layout: Layout, zeroed: bool) -> *mut u8 { process_heap_alloc(MaybeUninit::uninit(), flags, layout.size()) as *mut u8 } else { // Allocate extra padding in order to be able to satisfy the alignment. + // This addition does not overflow due to `Layout` type invariants, + // `size()` is at most `isize::MAX` while + // `align()` is at most `1 << (bits in usize - 2)` if `size()` is non-zero. let total = layout.align() + layout.size(); let ptr = process_heap_alloc(MaybeUninit::uninit(), flags, total) as *mut u8; diff --git a/library/std/src/sys/args/wasip1.rs b/library/std/src/sys/args/wasip1.rs index 72063a87dc9f..c09175a23f50 100644 --- a/library/std/src/sys/args/wasip1.rs +++ b/library/std/src/sys/args/wasip1.rs @@ -11,10 +11,10 @@ pub fn args() -> Args { fn maybe_args() -> Option> { unsafe { - let (argc, buf_size) = wasi::args_sizes_get().ok()?; + let (argc, buf_size) = wasip1::args_sizes_get().ok()?; let mut argv = Vec::with_capacity(argc); let mut buf = Vec::with_capacity(buf_size); - wasi::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; + wasip1::args_get(argv.as_mut_ptr(), buf.as_mut_ptr()).ok()?; argv.set_len(argc); let mut ret = Vec::with_capacity(argc); for ptr in argv { diff --git a/library/std/src/sys/fs/uefi.rs b/library/std/src/sys/fs/uefi.rs index 8135519317a0..ef523a9807f1 100644 --- a/library/std/src/sys/fs/uefi.rs +++ b/library/std/src/sys/fs/uefi.rs @@ -588,6 +588,11 @@ pub(crate) struct File { path: crate::path::PathBuf, } + // SAFETY: UEFI has no regular threads, and as per + // std does not support being invoked from "irregular threads" such as interrupt handlers or other + // CPU cores that run outside the scope of UEFI. + unsafe impl Send for File {} + impl File { pub(crate) fn from_path(path: &Path, open_mode: u64, attr: u64) -> io::Result { let absolute = crate::path::absolute(path)?; diff --git a/library/std/src/sys/fs/unix.rs b/library/std/src/sys/fs/unix.rs index 9b0ef5539d32..5d2cfdf6718a 100644 --- a/library/std/src/sys/fs/unix.rs +++ b/library/std/src/sys/fs/unix.rs @@ -339,7 +339,7 @@ fn get_path(fd: c_int) -> Option { // alternatives. If a better method is invented, it should be used // instead. let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_ptr()) }; + let n = unsafe { libc::fcntl(fd, libc::F_GETPATH, buf.as_mut_ptr()) }; if n == -1 { cfg_select! { target_os = "netbsd" => { @@ -375,7 +375,7 @@ fn get_path(fd: c_int) -> Option { #[cfg(target_os = "vxworks")] fn get_path(fd: c_int) -> Option { let mut buf = vec![0; libc::PATH_MAX as usize]; - let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_ptr()) }; + let n = unsafe { libc::ioctl(fd, libc::FIOGETNAME, buf.as_mut_ptr()) }; if n == -1 { return None; } diff --git a/library/std/src/sys/net/connection/wasip1.rs b/library/std/src/sys/net/connection/wasip1.rs index 95a4ab2fbf0f..d6c7e023e865 100644 --- a/library/std/src/sys/net/connection/wasip1.rs +++ b/library/std/src/sys/net/connection/wasip1.rs @@ -125,12 +125,12 @@ pub fn socket_addr(&self) -> io::Result { pub fn shutdown(&self, how: Shutdown) -> io::Result<()> { let wasi_how = match how { - Shutdown::Read => wasi::SDFLAGS_RD, - Shutdown::Write => wasi::SDFLAGS_WR, - Shutdown::Both => wasi::SDFLAGS_RD | wasi::SDFLAGS_WR, + Shutdown::Read => wasip1::SDFLAGS_RD, + Shutdown::Write => wasip1::SDFLAGS_WR, + Shutdown::Both => wasip1::SDFLAGS_RD | wasip1::SDFLAGS_WR, }; - unsafe { wasi::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } + unsafe { wasip1::sock_shutdown(self.socket().as_raw_fd() as _, wasi_how).map_err(err2io) } } pub fn duplicate(&self) -> io::Result { @@ -167,19 +167,20 @@ pub fn take_error(&self) -> io::Result> { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } @@ -221,7 +222,7 @@ pub fn socket_addr(&self) -> io::Result { pub fn accept(&self) -> io::Result<(TcpStream, SocketAddr)> { let fd = unsafe { - wasi::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? + wasip1::sock_accept(self.as_inner().as_inner().as_raw_fd() as _, 0).map_err(err2io)? }; Ok(( @@ -258,19 +259,20 @@ pub fn take_error(&self) -> io::Result> { pub fn set_nonblocking(&self, state: bool) -> io::Result<()> { let fdstat = unsafe { - wasi::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasi::Fd).map_err(err2io)? + wasip1::fd_fdstat_get(self.socket().as_inner().as_raw_fd() as wasip1::Fd) + .map_err(err2io)? }; let mut flags = fdstat.fs_flags; if state { - flags |= wasi::FDFLAGS_NONBLOCK; + flags |= wasip1::FDFLAGS_NONBLOCK; } else { - flags &= !wasi::FDFLAGS_NONBLOCK; + flags &= !wasip1::FDFLAGS_NONBLOCK; } unsafe { - wasi::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasi::Fd, flags) + wasip1::fd_fdstat_set_flags(self.socket().as_inner().as_raw_fd() as wasip1::Fd, flags) .map_err(err2io) } } diff --git a/library/std/src/sys/pal/wasi/mod.rs b/library/std/src/sys/pal/wasi/mod.rs index 6f6099350925..8ea26faca7e7 100644 --- a/library/std/src/sys/pal/wasi/mod.rs +++ b/library/std/src/sys/pal/wasi/mod.rs @@ -29,7 +29,7 @@ pub fn abort_internal() -> ! { #[inline] #[cfg(target_env = "p1")] -pub(crate) fn err2io(err: wasi::Errno) -> crate::io::Error { +pub(crate) fn err2io(err: wasip1::Errno) -> crate::io::Error { crate::io::Error::from_raw_os_error(err.raw().into()) } diff --git a/library/std/src/sys/paths/unix.rs b/library/std/src/sys/paths/unix.rs index 544d495340db..616456c6d4a4 100644 --- a/library/std/src/sys/paths/unix.rs +++ b/library/std/src/sys/paths/unix.rs @@ -207,7 +207,7 @@ fn sysctl() -> io::Result { cvt(libc::sysctl( mib.as_ptr(), mib.len() as libc::c_uint, - path.as_ptr() as *mut libc::c_void, + path.as_mut_ptr() as *mut libc::c_void, &mut path_len, ptr::null(), 0, diff --git a/library/std/src/sys/random/wasip1.rs b/library/std/src/sys/random/wasip1.rs index d41da3751fc0..cb91575fe30e 100644 --- a/library/std/src/sys/random/wasip1.rs +++ b/library/std/src/sys/random/wasip1.rs @@ -1,5 +1,5 @@ pub fn fill_bytes(bytes: &mut [u8]) { unsafe { - wasi::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") + wasip1::random_get(bytes.as_mut_ptr(), bytes.len()).expect("failed to generate random data") } } diff --git a/library/std/src/sys/thread/unix.rs b/library/std/src/sys/thread/unix.rs index 2f3ef1741cdf..81ef39581d74 100644 --- a/library/std/src/sys/thread/unix.rs +++ b/library/std/src/sys/thread/unix.rs @@ -155,6 +155,7 @@ pub fn available_parallelism() -> io::Result> { target_os = "aix", target_vendor = "apple", target_os = "cygwin", + target_os = "wasi", ) => { #[allow(unused_assignments)] #[allow(unused_mut)] diff --git a/library/std/src/thread/lifecycle.rs b/library/std/src/thread/lifecycle.rs index 0bb1f347ffaa..af239bee5518 100644 --- a/library/std/src/thread/lifecycle.rs +++ b/library/std/src/thread/lifecycle.rs @@ -7,7 +7,7 @@ use super::{Result, spawnhook}; use crate::cell::UnsafeCell; use crate::marker::PhantomData; -use crate::mem::{ManuallyDrop, MaybeUninit}; +use crate::mem::MaybeDangling; use crate::sync::Arc; use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; use crate::sys::{AsInner, IntoInner, thread as imp}; @@ -57,29 +57,8 @@ pub(super) unsafe fn spawn_unchecked<'scope, F, T>( Arc::new(Packet { scope: scope_data, result: UnsafeCell::new(None), _marker: PhantomData }); let their_packet = my_packet.clone(); - // Pass `f` in `MaybeUninit` because actually that closure might *run longer than the lifetime of `F`*. + // Pass `f` in `MaybeDangling` because actually that closure might *run longer than the lifetime of `F`*. // See for more details. - // To prevent leaks we use a wrapper that drops its contents. - #[repr(transparent)] - struct MaybeDangling(MaybeUninit); - impl MaybeDangling { - fn new(x: T) -> Self { - MaybeDangling(MaybeUninit::new(x)) - } - fn into_inner(self) -> T { - // Make sure we don't drop. - let this = ManuallyDrop::new(self); - // SAFETY: we are always initialized. - unsafe { this.0.assume_init_read() } - } - } - impl Drop for MaybeDangling { - fn drop(&mut self) { - // SAFETY: we are always initialized. - unsafe { self.0.assume_init_drop() }; - } - } - let f = MaybeDangling::new(f); // The entrypoint of the Rust thread, after platform-specific thread diff --git a/library/std/src/thread/scoped.rs b/library/std/src/thread/scoped.rs index 929f7fdc6dca..d8e018bde747 100644 --- a/library/std/src/thread/scoped.rs +++ b/library/std/src/thread/scoped.rs @@ -177,7 +177,7 @@ impl<'scope, 'env> Scope<'scope, 'env> { /// Spawns a new thread within a scope, returning a [`ScopedJoinHandle`] for it. /// /// Unlike non-scoped threads, threads spawned with this function may - /// borrow non-`'static` data from the outside the scope. See [`scope`] for + /// borrow non-`'static` data from outside the scope. See [`scope`] for /// details. /// /// The join handle provides a [`join`] method that can be used to join the spawned diff --git a/library/std/tests/sync/lazy_lock.rs b/library/std/tests/sync/lazy_lock.rs index 68aeea834b4f..c549094dd138 100644 --- a/library/std/tests/sync/lazy_lock.rs +++ b/library/std/tests/sync/lazy_lock.rs @@ -33,6 +33,15 @@ fn default() -> Self { assert_eq!(CALLED.load(SeqCst), 1); } +#[test] +fn const_lazy_default() { + // using Box as it cannot be initialized in const contexts + const X: LazyLock> = <_>::default(); + const Y: LazyCell> = <_>::default(); + assert_eq!(**X, 0); + assert_eq!(**Y, 0); +} + #[test] #[cfg_attr(any(target_os = "emscripten", target_os = "wasi"), ignore)] // no threads fn sync_lazy_new() { diff --git a/library/std/tests/sync/lib.rs b/library/std/tests/sync/lib.rs index 32a7efde2a25..92c4c2f511be 100644 --- a/library/std/tests/sync/lib.rs +++ b/library/std/tests/sync/lib.rs @@ -1,3 +1,5 @@ +#![feature(const_default)] +#![feature(const_trait_impl)] #![feature(mapped_lock_guards)] #![feature(mpmc_channel)] #![feature(oneshot_channel)] diff --git a/library/std/tests/sync/rwlock.rs b/library/std/tests/sync/rwlock.rs index d6287305481e..7369d671f873 100644 --- a/library/std/tests/sync/rwlock.rs +++ b/library/std/tests/sync/rwlock.rs @@ -917,19 +917,23 @@ fn test_rwlock_max_readers() { target_os = "fuchsia", all(target_family = "wasm", target_feature = "atomics"), target_os = "hermit", - target_os = "motor", + target_os = "motor", ) => { (1 << 30) - 2 }, any( target_family = "unix", - all(target_os = "windows", target_vendor = "win7"), + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "64"), all(target_vendor = "fortanix", target_env = "sgx"), target_os = "xous", target_os = "teeos", ) => { u32::MAX }, + // Otherwise a form of deadlock is observed. + all(target_os = "windows", target_vendor = "win7", target_pointer_width = "32") => { + (1 << 28) - 1 + }, target_os = "solid_asp3" => { (1 << 30) }, diff --git a/library/std/tests/thread.rs b/library/std/tests/thread.rs index dc8eadd75148..ef13ce44d318 100644 --- a/library/std/tests/thread.rs +++ b/library/std/tests/thread.rs @@ -85,7 +85,6 @@ fn thread_local_hygeiene() { target_env = "sgx", target_os = "solid_asp3", target_os = "teeos", - target_os = "wasi" ), should_panic )] diff --git a/library/stdarch/.github/workflows/main.yml b/library/stdarch/.github/workflows/main.yml index 3749ed1f6ac8..1f598f6e20d4 100644 --- a/library/stdarch/.github/workflows/main.yml +++ b/library/stdarch/.github/workflows/main.yml @@ -96,8 +96,9 @@ jobs: os: ubuntu-latest - tuple: loongarch64-unknown-linux-gnu os: ubuntu-latest - - tuple: hexagon-unknown-linux-musl - os: ubuntu-latest + # hexagon doesn't build at the moment due to a libc issue. + # - tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest - tuple: wasm32-wasip1 os: ubuntu-latest @@ -209,11 +210,12 @@ jobs: tuple: amdgcn-amd-amdhsa os: ubuntu-latest norun: true - - target: - tuple: hexagon-unknown-linux-musl - os: ubuntu-latest - norun: true - build_std: true + # hexagon doesn't build at the moment due to a libc issue. + # - target: + # tuple: hexagon-unknown-linux-musl + # os: ubuntu-latest + # norun: true + # build_std: true steps: - uses: actions/checkout@v6 @@ -270,7 +272,7 @@ jobs: intrinsic-test: needs: [style] name: Intrinsic Test - runs-on: ubuntu-latest + runs-on: ubuntu-latest strategy: matrix: target: @@ -330,11 +332,33 @@ jobs: cargo run -p stdarch-gen-hexagon --release git diff --exit-code + # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics + # that Miri does not support. Also Miri is reltively slow. + # + # Below we run some tests where Miri might catch UB, for instance on intrinsics that read from + # or write to pointers. + miri: + needs: [style] + name: Run some tests with miri + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v6 + - name: Install Rust + run: rustup update nightly && rustup default nightly && rustup component add miri + - name: Run miri tests + env: + TARGET: "aarch64-unknown-linux-gnu" + run: | + # read filters and join them with a space. + FILTERS=$(cat aarch64-miri-tests.txt | tr '\n' ' ') + cargo miri test -p core_arch --target aarch64-unknown-linux-gnu -- $FILTERS + conclusion: needs: - docs - verify - test + - miri - intrinsic-test - check-stdarch-gen runs-on: ubuntu-latest diff --git a/library/stdarch/.github/workflows/rustc-pull.yml b/library/stdarch/.github/workflows/rustc-pull.yml index ee0c498878f4..d2feb1add634 100644 --- a/library/stdarch/.github/workflows/rustc-pull.yml +++ b/library/stdarch/.github/workflows/rustc-pull.yml @@ -13,6 +13,7 @@ jobs: uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-stdarch[bot]" # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782 zulip-stream-id: 208962 zulip-bot-email: "stdarch-ci-bot@rust-lang.zulipchat.com" diff --git a/library/stdarch/aarch64-miri-tests.txt b/library/stdarch/aarch64-miri-tests.txt new file mode 100644 index 000000000000..2c0dbb8297a1 --- /dev/null +++ b/library/stdarch/aarch64-miri-tests.txt @@ -0,0 +1,4 @@ +test_vld3 +test_vld4 +neon::load_tests +neon::store_tests diff --git a/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index a8b352881e81..8bcd6409453c 100644 --- a/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 147a3df61455..9aa0ce05783c 100644 --- a/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:25.10 +FROM ubuntu:25.04 # gcc-mips64el-linux-gnuabi64 not available in 25.10 RUN apt-get update && apt-get install -y --no-install-recommends \ gcc libc6-dev qemu-user ca-certificates \ diff --git a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index a357449d51e3..17c6d25215ae 100644 --- a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -12,7 +12,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ build-essential \ lld -RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-10.5.0-2026-01-13-lin.tar.xz -O sde.tar.xz +RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.xz -O sde.tar.xz RUN mkdir intel-sde RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \ diff --git a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def index acf023ed0dc4..3bd657873e55 100644 --- a/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def +++ b/library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2025 Intel Corporation. +# Copyright (C) 2017-2026 Intel Corporation. # # This software and the related documents are Intel copyrighted materials, and your # use of them is governed by the express license under which they were provided to @@ -23,8 +23,9 @@ 00000004 00000004 => 00000000 00000000 00000000 00000000 00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT 00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power -00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features +00000007 00000000 => 00000002 f3bfbfbf bac05ffe 03d54130 #Extended Features 00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e +00000007 00000002 => 00000000 00000000 00000000 00000010 00000008 ******** => 00000000 00000000 00000000 00000000 00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache 0000000a ******** => 07300403 00000000 00000000 00000603 diff --git a/library/stdarch/crates/assert-instr-macro/src/lib.rs b/library/stdarch/crates/assert-instr-macro/src/lib.rs index 13c3c3851b43..839aae67cb2b 100644 --- a/library/stdarch/crates/assert-instr-macro/src/lib.rs +++ b/library/stdarch/crates/assert-instr-macro/src/lib.rs @@ -14,6 +14,7 @@ use proc_macro2::TokenStream; use quote::ToTokens; +use syn::spanned::Spanned; #[proc_macro_attribute] pub fn assert_instr( @@ -67,21 +68,21 @@ pub fn assert_instr( ); let mut inputs = Vec::new(); let mut input_vals = Vec::new(); - let mut const_vals = Vec::new(); + let mut param_vals = Vec::new(); let ret = &func.sig.output; for arg in func.sig.inputs.iter() { let capture = match *arg { - syn::FnArg::Typed(ref c) => c, + syn::FnArg::Typed(ref c) => c.to_owned(), ref v => panic!( "arguments must not have patterns: `{:?}`", v.clone().into_token_stream() ), }; - let ident = match *capture.pat { - syn::Pat::Ident(ref i) => &i.ident, + let ident = match capture.pat.as_ref() { + syn::Pat::Ident(i) => &i.ident.to_owned(), _ => panic!("must have bare arguments"), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| *ident == a.0) { + if let Some(&(_, ref tokens)) = invoc.args.iter().find(|a| *ident == a.0) { input_vals.push(quote! { #tokens }); } else { inputs.push(capture); @@ -89,18 +90,48 @@ pub fn assert_instr( } } for arg in func.sig.generics.params.iter() { - let c = match *arg { - syn::GenericParam::Const(ref c) => c, + match *arg { + syn::GenericParam::Const(ref c) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { + param_vals.push(quote! { #tokens }); + } else { + panic!("const generics must have a value for tests"); + } + } + syn::GenericParam::Type(ref t) => { + if let Some((_, tokens)) = invoc.args.iter().find(|a| t.ident == a.0) + && let syn::Expr::Path(syn::ExprPath { qself, path, .. }) = tokens + { + param_vals.push(syn::Token![_](tokens.span()).to_token_stream()); + + let generic_ty_value = syn::TypePath { + qself: qself.clone(), + path: path.clone(), + }; + + // Replace any function arguments that use generic parameters with the + // instantiation provided in the macro invocation. + inputs.iter_mut().for_each(|arg| { + update_type_path(arg.ty.as_mut(), |type_path: &mut syn::TypePath| { + if let Some(syn::PathSegment { + ident: last_ident, .. + }) = type_path.path.segments.last_mut() + { + if *last_ident == t.ident { + *type_path = generic_ty_value.to_owned() + } + } + }) + }); + } else { + panic!("type generics must have a type for tests"); + } + } ref v => panic!( - "only const generics are allowed: `{:?}`", + "only type and const generics are allowed: `{:?}`", v.clone().into_token_stream() ), }; - if let Some((_, tokens)) = invoc.args.iter().find(|a| c.ident == a.0) { - const_vals.push(quote! { #tokens }); - } else { - panic!("const generics must have a value for tests"); - } } let attrs = func @@ -138,7 +169,7 @@ pub fn assert_instr( #[unsafe(no_mangle)] #[inline(never)] pub unsafe extern #abi fn #shim_name(#(#inputs),*) #ret { - #name::<#(#const_vals),*>(#(#input_vals),*) + #name::<#(#param_vals),*>(#(#input_vals),*) } }; @@ -222,3 +253,23 @@ fn to_tokens(&self, tokens: &mut proc_macro2::TokenStream) { } } } + +/// Calls `update` on type paths so that type generics can be replaced with the instantiation from +/// the attribute. +fn update_type_path(ty: &mut syn::Type, update: F) +where + F: Fn(&mut syn::TypePath), +{ + use syn::Type::*; + match ty { + Array(syn::TypeArray { elem, .. }) + | Group(syn::TypeGroup { elem, .. }) + | Paren(syn::TypeParen { elem, .. }) + | Ptr(syn::TypePtr { elem, .. }) + | Reference(syn::TypeReference { elem, .. }) + | Slice(syn::TypeSlice { elem, .. }) => update_type_path(elem.as_mut(), update), + Path(path @ syn::TypePath { .. }) => update(path), + Tuple(..) => panic!("tuples and generic types together are not yet supported"), + _ => {} + } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/mod.rs index d7295659c3c9..0292be2e0d77 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/mod.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/mod.rs @@ -25,6 +25,20 @@ #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub use self::neon::*; +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(target_arch = "aarch64", doc))] +mod sve; +#[cfg(any(target_arch = "aarch64", doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve::*; + +// The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`. +#[cfg(any(target_arch = "aarch64", doc))] +mod sve2; +#[cfg(any(target_arch = "aarch64", doc))] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::sve2::*; + mod prefetch; #[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")] pub use self::prefetch::*; diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 74af50016690..c9ce7a69a657 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -12127,14 +12127,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f64.p0" - )] - fn _vld3q_f64(ptr: *const float64x2_t) -> float64x2x3_t; - } - _vld3q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] @@ -12145,14 +12138,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i64.p0" - )] - fn _vld3q_s64(ptr: *const int64x2_t) -> int64x2x3_t; - } - _vld3q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] @@ -12535,14 +12521,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f64.p0" - )] - fn _vld4q_f64(ptr: *const float64x2_t) -> float64x2x4_t; - } - _vld4q_f64(a as _) + crate::core_arch::macros::deinterleaving_load!(f64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] @@ -12553,14 +12532,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i64.p0" - )] - fn _vld4q_s64(ptr: *const int64x2_t) -> int64x2x4_t; - } - _vld4q_s64(a as _) + crate::core_arch::macros::deinterleaving_load!(i64, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs index 2fbd2255aa0f..29a278b80df8 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs @@ -1022,8 +1022,12 @@ macro_rules! wide_store_load_roundtrip { ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => { let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); let a: $vec_ty = transmute(vals); - let mut tmp = [0 as $elem_ty; $len]; + let mut tmp = core::mem::MaybeUninit::<[$elem_ty; $len]>::uninit(); $store(tmp.as_mut_ptr().cast(), a); + + // With Miri this will check that all elements were initialized. + let tmp = tmp.assume_init(); + let r: $vec_ty = $load(tmp.as_ptr().cast()); let out: [$elem_ty; $len] = transmute(r); assert_eq!(out, vals); diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs new file mode 100644 index 000000000000..ed28e98a813e --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs @@ -0,0 +1,44957 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; +use crate::core_arch::arch::aarch64::*; + +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv4f32")] + fn _svabd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svabd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svabd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabd.nxv2f64")] + fn _svabd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svabd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabd))] +pub fn svabd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svabd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv16i8")] + fn _svabd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_s8_m(pg, op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svabd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svabd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv8i16")] + fn _svabd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svabd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svabd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv4i32")] + fn _svabd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svabd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svabd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabd.nxv2i64")] + fn _svabd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svabd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabd))] +pub fn svabd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svabd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv16i8")] + fn _svabd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svabd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svabd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svabd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv8i16")] + fn _svabd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svabd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svabd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svabd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv4i32")] + fn _svabd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svabd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svabd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svabd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabd.nxv2i64")] + fn _svabd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svabd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, op1, op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svabd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabd))] +pub fn svabd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svabd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv4f32")] + fn _svabs_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svabs_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svabs_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fabs.nxv2f64")] + fn _svabs_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svabs_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fabs))] +pub fn svabs_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svabs_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv16i8")] + fn _svabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svabs_s8_m(inactive, pg, op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv8i16")] + fn _svabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv4i32")] + fn _svabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.abs.nxv2i64")] + fn _svabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(op, pg, op) +} +#[doc = "Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabs[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(abs))] +pub fn svabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv4f32")] + fn _svacge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facge.nxv2f64")] + fn _svacge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacge[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv4f32")] + fn _svacgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svacgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.facgt.nxv2f64")] + fn _svacgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svacgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacgt[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svacgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacge_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svacle_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacge_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svacle[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facge))] +pub fn svacle_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svacle_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svacgt_f32(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svaclt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svacgt_f64(pg, op2, op1) +} +#[doc = "Absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaclt[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(facgt))] +pub fn svaclt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svaclt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv4f32")] + fn _svadd_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svadd_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svadd_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svadd_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadd.nxv2f64")] + fn _svadd_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svadd_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svadd_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadd))] +pub fn svadd_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svadd_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv16i8")] + fn _svadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svadd_s8_m(pg, op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv8i16")] + fn _svadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv4i32")] + fn _svadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.add.nxv2i64")] + fn _svadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svadd_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svadd_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svadd_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svadd_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, op1, op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(add))] +pub fn svadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f32(pg: svbool_t, initial: f32, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv4f32")] + fn _svadda_f32(pg: svbool4_t, initial: f32, op: svfloat32_t) -> f32; + } + unsafe { _svadda_f32(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction (strictly-ordered)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadda[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fadda))] +pub fn svadda_f64(pg: svbool_t, initial: f64, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fadda.nxv2f64")] + fn _svadda_f64(pg: svbool2_t, initial: f64, op: svfloat64_t) -> f64; + } + unsafe { _svadda_f64(pg.sve_into(), initial, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv4f32")] + fn _svaddv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svaddv_f32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddv))] +pub fn svaddv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddv.nxv2f64")] + fn _svaddv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svaddv_f64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv2i64")] + fn _svaddv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_s64(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv2i64")] + fn _svaddv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svaddv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s8(pg: svbool_t, op: svint8_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv16i8")] + fn _svaddv_s8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_s8(pg, op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s16(pg: svbool_t, op: svint16_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv8i16")] + fn _svaddv_s16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_s16(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddv))] +pub fn svaddv_s32(pg: svbool_t, op: svint32_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddv.nxv4i32")] + fn _svaddv_s32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_s32(pg.sve_into(), op) } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u8(pg: svbool_t, op: svuint8_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv16i8")] + fn _svaddv_u8(pg: svbool_t, op: svint8_t) -> i64; + } + unsafe { _svaddv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u16(pg: svbool_t, op: svuint16_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv8i16")] + fn _svaddv_u16(pg: svbool8_t, op: svint16_t) -> i64; + } + unsafe { _svaddv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Add reduction"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddv))] +pub fn svaddv_u32(pg: svbool_t, op: svuint32_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddv.nxv4i32")] + fn _svaddv_u32(pg: svbool4_t, op: svint32_t) -> i64; + } + unsafe { _svaddv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[s32]offset)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_s32offset(bases: svuint32_t, offsets: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv4i32")] + fn _svadrb_u32base_s32offset(bases: svint32_t, offsets: svint32_t) -> svint32_t; + } + unsafe { _svadrb_u32base_s32offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[s32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv4i32")] + fn _svadrh_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrh_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[s32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv4i32")] + fn _svadrw_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrw_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[s32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_s32index(bases: svuint32_t, indices: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv4i32")] + fn _svadrd_u32base_s32index(bases: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svadrd_u32base_s32index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u32base]_[u32]offset)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u32base_u32offset(bases: svuint32_t, offsets: svuint32_t) -> svuint32_t { + unsafe { svadrb_u32base_s32offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u32base]_[u32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrh_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u32base]_[u32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrw_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u32base]_[u32]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u32base_u32index(bases: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svadrd_u32base_s32index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[s64]offset)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_s64offset(bases: svuint64_t, offsets: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrb.nxv2i64")] + fn _svadrb_u64base_s64offset(bases: svint64_t, offsets: svint64_t) -> svint64_t; + } + unsafe { _svadrb_u64base_s64offset(bases.as_signed(), offsets).as_unsigned() } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[s64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrh.nxv2i64")] + fn _svadrh_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrh_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[s64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrw.nxv2i64")] + fn _svadrw_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrw_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[s64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_s64index(bases: svuint64_t, indices: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adrd.nxv2i64")] + fn _svadrd_u64base_s64index(bases: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svadrd_u64base_s64index(bases.as_signed(), indices).as_unsigned() } +} +#[doc = "Compute vector addresses for 8-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrb[_u64base]_[u64]offset)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrb_u64base_u64offset(bases: svuint64_t, offsets: svuint64_t) -> svuint64_t { + unsafe { svadrb_u64base_s64offset(bases, offsets.as_signed()) } +} +#[doc = "Compute vector addresses for 16-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrh[_u64base]_[u64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrh_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrh_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 32-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrw[_u64base]_[u64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrw_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrw_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Compute vector addresses for 64-bit data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadrd[_u64base]_[u64]index)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adr))] +pub fn svadrd_u64base_u64index(bases: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svadrd_u64base_s64index(bases, indices.as_signed()) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.z.nvx16i1")] + fn _svand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svand_b_z(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv16i8")] + fn _svand_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svand_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svand_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svand_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv8i16")] + fn _svand_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svand_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svand_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svand_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv4i32")] + fn _svand_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svand_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svand_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svand_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.and.nxv2i64")] + fn _svand_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svand_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svand_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svand_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svand_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svand_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svand_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svand_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svand_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svand_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svand_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svand_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svand_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svand_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, op1, op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svand_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise AND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svand[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(and))] +pub fn svand_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svand_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv16i8")] + fn _svandv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svandv_s8(pg, op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv8i16")] + fn _svandv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svandv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv4i32")] + fn _svandv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svandv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.andv.nxv2i64")] + fn _svandv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svandv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svandv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svandv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svandv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise AND reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svandv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(andv))] +pub fn svandv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svandv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv16i8")] + fn _svasr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svasr_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svasr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svasr_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv8i16")] + fn _svasr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svasr_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svasr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svasr_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv4i32")] + fn _svasr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svasr_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svasr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svasr_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asr.nxv2i64")] + fn _svasr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svasr_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svasr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svasr_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv16i8" + )] + fn _svasr_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svasr_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svasr_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svasr_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv8i16" + )] + fn _svasr_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svasr_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svasr_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svasr_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.asr.wide.nxv4i32" + )] + fn _svasr_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svasr_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, op1, op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svasr_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Arithmetic shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasr_wide[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asr))] +pub fn svasr_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svasr_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv16i8")] + fn _svasrd_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svasrd_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svasrd_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv8i16")] + fn _svasrd_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svasrd_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svasrd_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv4i32")] + fn _svasrd_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svasrd_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svasrd_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.asrd.nxv2i64")] + fn _svasrd_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svasrd_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, op1) +} +#[doc = "Arithmetic shift right for divide by immediate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svasrd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(asrd, IMM2 = 1))] +pub fn svasrd_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svasrd_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.z.nvx16i1")] + fn _svbic_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbic_b_z(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv16i8")] + fn _svbic_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbic_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svbic_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svbic_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv8i16")] + fn _svbic_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbic_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svbic_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svbic_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv4i32")] + fn _svbic_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbic_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svbic_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svbic_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bic.nxv2i64")] + fn _svbic_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbic_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svbic_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svbic_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svbic_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svbic_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svbic_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svbic_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svbic_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svbic_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svbic_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svbic_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svbic_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svbic_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, op1, op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svbic_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise clear"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbic[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bic))] +pub fn svbic_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svbic_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.nxv16i1")] + fn _svbrka_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_m(inactive, pg, op) } +} +#[doc = "Break after first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrka[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brka))] +pub fn svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brka.z.nxv16i1")] + fn _svbrka_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrka_b_z(pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.nxv16i1")] + fn _svbrkb_b_m(inactive: svbool_t, pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_m(inactive, pg, op) } +} +#[doc = "Break before first true condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkb[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkb))] +pub fn svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkb.z.nxv16i1")] + fn _svbrkb_b_z(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svbrkb_b_z(pg, op) } +} +#[doc = "Propagate break to next partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkn[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkn))] +pub fn svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.brkn.z.nxv16i1")] + fn _svbrkn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkn_b_z(pg, op1, op2) } +} +#[doc = "Break after first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpa[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpa))] +pub fn svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpa.z.nxv16i1" + )] + fn _svbrkpa_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpa_b_z(pg, op1, op2) } +} +#[doc = "Break before first true condition, propagating from previous partition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbrkpb[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(brkpb))] +pub fn svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.brkpb.z.nxv16i1" + )] + fn _svbrkpb_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svbrkpb_b_z(pg, op1, op2) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv4f32")] + fn _svcadd_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcadd_f32_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, +) -> svfloat32_t { + svcadd_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcadd.nxv2f64")] + fn _svcadd_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcadd_f64_m(pg.sve_into(), op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, op1, op2) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcadd, IMM_ROTATION = 90))] +pub fn svcadd_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, +) -> svfloat64_t { + svcadd_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4f32")] + fn _svclasta_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclasta_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2f64")] + fn _svclasta_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclasta_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv16i8")] + fn _svclasta_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclasta_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv8i16")] + fn _svclasta_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclasta_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv4i32")] + fn _svclasta_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclasta_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clasta.nxv2i64")] + fn _svclasta_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclasta_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclasta_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclasta_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclasta_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclasta_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4f32" + )] + fn _svclasta_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclasta_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2f64" + )] + fn _svclasta_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclasta_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv16i8" + )] + fn _svclasta_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclasta_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv8i16" + )] + fn _svclasta_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclasta_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv4i32" + )] + fn _svclasta_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclasta_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clasta.n.nxv2i64" + )] + fn _svclasta_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclasta_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclasta_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclasta_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclasta_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclasta[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clasta))] +pub fn svclasta_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclasta_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f32(pg: svbool_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4f32")] + fn _svclastb_f32(pg: svbool4_t, fallback: svfloat32_t, data: svfloat32_t) -> svfloat32_t; + } + unsafe { _svclastb_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_f64(pg: svbool_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2f64")] + fn _svclastb_f64(pg: svbool2_t, fallback: svfloat64_t, data: svfloat64_t) -> svfloat64_t; + } + unsafe { _svclastb_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv16i8")] + fn _svclastb_s8(pg: svbool_t, fallback: svint8_t, data: svint8_t) -> svint8_t; + } + unsafe { _svclastb_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s16(pg: svbool_t, fallback: svint16_t, data: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv8i16")] + fn _svclastb_s16(pg: svbool8_t, fallback: svint16_t, data: svint16_t) -> svint16_t; + } + unsafe { _svclastb_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s32(pg: svbool_t, fallback: svint32_t, data: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv4i32")] + fn _svclastb_s32(pg: svbool4_t, fallback: svint32_t, data: svint32_t) -> svint32_t; + } + unsafe { _svclastb_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_s64(pg: svbool_t, fallback: svint64_t, data: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clastb.nxv2i64")] + fn _svclastb_s64(pg: svbool2_t, fallback: svint64_t, data: svint64_t) -> svint64_t; + } + unsafe { _svclastb_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u8(pg: svbool_t, fallback: svuint8_t, data: svuint8_t) -> svuint8_t { + unsafe { svclastb_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u16(pg: svbool_t, fallback: svuint16_t, data: svuint16_t) -> svuint16_t { + unsafe { svclastb_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u32(pg: svbool_t, fallback: svuint32_t, data: svuint32_t) -> svuint32_t { + unsafe { svclastb_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_u64(pg: svbool_t, fallback: svuint64_t, data: svuint64_t) -> svuint64_t { + unsafe { svclastb_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f32(pg: svbool_t, fallback: f32, data: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4f32" + )] + fn _svclastb_n_f32(pg: svbool4_t, fallback: f32, data: svfloat32_t) -> f32; + } + unsafe { _svclastb_n_f32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_f64(pg: svbool_t, fallback: f64, data: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2f64" + )] + fn _svclastb_n_f64(pg: svbool2_t, fallback: f64, data: svfloat64_t) -> f64; + } + unsafe { _svclastb_n_f64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv16i8" + )] + fn _svclastb_n_s8(pg: svbool_t, fallback: i8, data: svint8_t) -> i8; + } + unsafe { _svclastb_n_s8(pg, fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s16(pg: svbool_t, fallback: i16, data: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv8i16" + )] + fn _svclastb_n_s16(pg: svbool8_t, fallback: i16, data: svint16_t) -> i16; + } + unsafe { _svclastb_n_s16(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s32(pg: svbool_t, fallback: i32, data: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv4i32" + )] + fn _svclastb_n_s32(pg: svbool4_t, fallback: i32, data: svint32_t) -> i32; + } + unsafe { _svclastb_n_s32(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_s64(pg: svbool_t, fallback: i64, data: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.clastb.n.nxv2i64" + )] + fn _svclastb_n_s64(pg: svbool2_t, fallback: i64, data: svint64_t) -> i64; + } + unsafe { _svclastb_n_s64(pg.sve_into(), fallback, data) } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u8(pg: svbool_t, fallback: u8, data: svuint8_t) -> u8 { + unsafe { svclastb_n_s8(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u16(pg: svbool_t, fallback: u16, data: svuint16_t) -> u16 { + unsafe { svclastb_n_s16(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u32(pg: svbool_t, fallback: u32, data: svuint32_t) -> u32 { + unsafe { svclastb_n_s32(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Conditionally extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclastb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clastb))] +pub fn svclastb_n_u64(pg: svbool_t, fallback: u64, data: svuint64_t) -> u64 { + unsafe { svclastb_n_s64(pg, fallback.as_signed(), data.as_signed()).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv16i8")] + fn _svcls_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcls_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcls_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcls_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv8i16")] + fn _svcls_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcls_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcls_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcls_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv4i32")] + fn _svcls_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcls_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcls_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcls_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cls.nxv2i64")] + fn _svcls_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcls_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcls_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcls[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cls))] +pub fn svcls_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcls_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv16i8")] + fn _svclz_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svclz_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svclz_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svclz_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv8i16")] + fn _svclz_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svclz_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svclz_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svclz_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv4i32")] + fn _svclz_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svclz_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svclz_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svclz_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.clz.nxv2i64")] + fn _svclz_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svclz_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svclz_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svclz_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svclz_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svclz_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svclz_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svclz_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svclz_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svclz_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svclz_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(op, pg, op) +} +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svclz[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(clz))] +pub fn svclz_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svclz_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv4f32")] + fn _svcmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_f32_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svcmla_f32_m::(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmla.nxv2f64")] + fn _svcmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + imm_rotation: i32, + ) -> svfloat64_t; + } + unsafe { _svcmla_f64_m(pg.sve_into(), op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, op1, op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_ROTATION = 90))] +pub fn svcmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svcmla_f64_m::(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fcmla.lane.x.nxv4f32" + )] + fn _svcmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svfloat32_t; + } + unsafe { _svcmla_lane_f32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv4f32")] + fn _svcmpeq_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpeq_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpeq_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpeq.nxv2f64")] + fn _svcmpeq_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpeq_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmeq))] +pub fn svcmpeq_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpeq_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv16i8")] + fn _svcmpeq_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpeq_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpeq_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv8i16")] + fn _svcmpeq_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpeq_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpeq_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv4i32")] + fn _svcmpeq_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpeq_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpeq_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpeq.nxv2i64")] + fn _svcmpeq_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpeq_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpeq_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpeq_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpeq_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpeq_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpeq_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpeq_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpeq_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpeq_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpeq_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv16i8" + )] + fn _svcmpeq_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpeq_wide_s8(pg, op1, op2) } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpeq_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv8i16" + )] + fn _svcmpeq_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpeq_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpeq_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpeq.wide.nxv4i32" + )] + fn _svcmpeq_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpeq_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpeq_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpeq))] +pub fn svcmpeq_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpeq_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv4f32")] + fn _svcmpge_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpge_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpge_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpge.nxv2f64")] + fn _svcmpge_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpge_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmpge_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpge_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv16i8")] + fn _svcmpge_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpge_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv8i16")] + fn _svcmpge_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpge_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv4i32")] + fn _svcmpge_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpge_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpge.nxv2i64")] + fn _svcmpge_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpge_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv16i8")] + fn _svcmpge_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpge_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpge_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv8i16")] + fn _svcmpge_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpge_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpge_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv4i32")] + fn _svcmpge_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpge_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpge_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphs.nxv2i64")] + fn _svcmpge_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpge_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpge_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv16i8" + )] + fn _svcmpge_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpge_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv8i16" + )] + fn _svcmpge_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpge_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpge.wide.nxv4i32" + )] + fn _svcmpge_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmpge_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpge_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv16i8" + )] + fn _svcmpge_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpge_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpge_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv8i16" + )] + fn _svcmpge_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpge_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpge_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphs.wide.nxv4i32" + )] + fn _svcmpge_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpge_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpge_wide[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmpge_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpge_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv4f32")] + fn _svcmpgt_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpgt_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpgt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpgt.nxv2f64")] + fn _svcmpgt_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpgt_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmpgt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpgt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv16i8")] + fn _svcmpgt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpgt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv8i16")] + fn _svcmpgt_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpgt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv4i32")] + fn _svcmpgt_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpgt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpgt.nxv2i64")] + fn _svcmpgt_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpgt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv16i8")] + fn _svcmpgt_u8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpgt_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpgt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv8i16")] + fn _svcmpgt_u16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpgt_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpgt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv4i32")] + fn _svcmpgt_u32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpgt_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpgt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmphi.nxv2i64")] + fn _svcmpgt_u64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpgt_u64(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpgt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv16i8" + )] + fn _svcmpgt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpgt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv8i16" + )] + fn _svcmpgt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpgt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpgt.wide.nxv4i32" + )] + fn _svcmpgt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmpgt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpgt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv16i8" + )] + fn _svcmpgt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpgt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmpgt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv8i16" + )] + fn _svcmpgt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpgt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmpgt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmphi.wide.nxv4i32" + )] + fn _svcmpgt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpgt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpgt_wide[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmpgt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmpgt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpge_f32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmple_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpge_f64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmge))] +pub fn svcmple_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmple_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpge_s8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmple_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpge_s16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmple_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpge_s32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmple_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpge_s64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpge))] +pub fn svcmple_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmple_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpge_u8(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmple_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpge_u16(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmple_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpge_u32(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmple_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpge_u64(pg, op2, op1) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphs))] +pub fn svcmple_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmple_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv16i8" + )] + fn _svcmple_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmple_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv8i16" + )] + fn _svcmple_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmple_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmple.wide.nxv4i32" + )] + fn _svcmple_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmple))] +pub fn svcmple_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmple_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv16i8" + )] + fn _svcmple_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmple_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmple_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv8i16" + )] + fn _svcmple_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmple_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmple_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpls.wide.nxv4i32" + )] + fn _svcmple_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmple_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmple_wide[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpls))] +pub fn svcmple_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmple_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + svcmpgt_f32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmplt_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + svcmpgt_f64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmgt))] +pub fn svcmplt_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmplt_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + svcmpgt_s8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmplt_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + svcmpgt_s16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmplt_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + svcmpgt_s32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmplt_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + svcmpgt_s64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpgt))] +pub fn svcmplt_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmplt_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + svcmpgt_u8(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmplt_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + svcmpgt_u16(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmplt_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + svcmpgt_u32(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmplt_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + svcmpgt_u64(pg, op2, op1) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmphi))] +pub fn svcmplt_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmplt_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv16i8" + )] + fn _svcmplt_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_s8(pg, op1, op2) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmplt_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv8i16" + )] + fn _svcmplt_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmplt_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplt.wide.nxv4i32" + )] + fn _svcmplt_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplt))] +pub fn svcmplt_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmplt_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u8(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv16i8" + )] + fn _svcmplt_wide_u8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmplt_wide_u8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u8(pg: svbool_t, op1: svuint8_t, op2: u64) -> svbool_t { + svcmplt_wide_u8(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u16(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv8i16" + )] + fn _svcmplt_wide_u16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmplt_wide_u16(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u16(pg: svbool_t, op1: svuint16_t, op2: u64) -> svbool_t { + svcmplt_wide_u16(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_u32(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmplo.wide.nxv4i32" + )] + fn _svcmplt_wide_u32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmplt_wide_u32(pg.sve_into(), op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmplt_wide[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmplo))] +pub fn svcmplt_wide_n_u32(pg: svbool_t, op1: svuint32_t, op2: u64) -> svbool_t { + svcmplt_wide_u32(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv4f32")] + fn _svcmpne_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpne_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpne_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpne.nxv2f64")] + fn _svcmpne_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpne_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmne))] +pub fn svcmpne_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpne_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv16i8")] + fn _svcmpne_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svcmpne_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s8(pg: svbool_t, op1: svint8_t, op2: i8) -> svbool_t { + svcmpne_s8(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv8i16")] + fn _svcmpne_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svcmpne_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s16(pg: svbool_t, op1: svint16_t, op2: i16) -> svbool_t { + svcmpne_s16(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv4i32")] + fn _svcmpne_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svbool4_t; + } + unsafe { _svcmpne_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s32(pg: svbool_t, op1: svint32_t, op2: i32) -> svbool_t { + svcmpne_s32(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmpne.nxv2i64")] + fn _svcmpne_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svbool2_t; + } + unsafe { _svcmpne_s64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_s64(pg: svbool_t, op1: svint64_t, op2: i64) -> svbool_t { + svcmpne_s64(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svcmpne_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u8(pg: svbool_t, op1: svuint8_t, op2: u8) -> svbool_t { + svcmpne_u8(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svcmpne_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u16(pg: svbool_t, op1: svuint16_t, op2: u16) -> svbool_t { + svcmpne_u16(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svbool_t { + unsafe { svcmpne_s32(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u32(pg: svbool_t, op1: svuint32_t, op2: u32) -> svbool_t { + svcmpne_u32(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svbool_t { + unsafe { svcmpne_s64(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_n_u64(pg: svbool_t, op1: svuint64_t, op2: u64) -> svbool_t { + svcmpne_u64(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv16i8" + )] + fn _svcmpne_wide_s8(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svbool_t; + } + unsafe { _svcmpne_wide_s8(pg, op1, op2) } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s8(pg: svbool_t, op1: svint8_t, op2: i64) -> svbool_t { + svcmpne_wide_s8(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s16(pg: svbool_t, op1: svint16_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv8i16" + )] + fn _svcmpne_wide_s16(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svbool8_t; + } + unsafe { _svcmpne_wide_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s16(pg: svbool_t, op1: svint16_t, op2: i64) -> svbool_t { + svcmpne_wide_s16(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_s32(pg: svbool_t, op1: svint32_t, op2: svint64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmpne.wide.nxv4i32" + )] + fn _svcmpne_wide_s32(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svbool4_t; + } + unsafe { _svcmpne_wide_s32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare not equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpne_wide[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmpne))] +pub fn svcmpne_wide_n_s32(pg: svbool_t, op1: svint32_t, op2: i64) -> svbool_t { + svcmpne_wide_s32(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv4f32")] + fn _svcmpuo_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svbool4_t; + } + unsafe { _svcmpuo_f32(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f32(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svbool_t { + svcmpuo_f32(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcmpuo.nxv2f64")] + fn _svcmpuo_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svbool2_t; + } + unsafe { _svcmpuo_f64(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Compare unordered with"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmpuo[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcmuo))] +pub fn svcmpuo_n_f64(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svbool_t { + svcmpuo_f64(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv16i8")] + fn _svcnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnot_s8_m(inactive, pg, op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svcnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv8i16")] + fn _svcnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svcnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv4i32")] + fn _svcnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svcnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnot.nxv2i64")] + fn _svcnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svcnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(op, pg, op) +} +#[doc = "Logically invert boolean condition"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnot[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnot))] +pub fn svcnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4f32")] + fn _svcnt_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcnt_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcnt_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcnt_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2f64")] + fn _svcnt_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcnt_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcnt_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcnt_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_m(inactive: svuint8_t, pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv16i8")] + fn _svcnt_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svcnt_s8_m(inactive.as_signed(), pg, op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_x(pg: svbool_t, op: svint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s8_z(pg: svbool_t, op: svint8_t) -> svuint8_t { + svcnt_s8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_m(inactive: svuint16_t, pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv8i16")] + fn _svcnt_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svcnt_s16_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_x(pg: svbool_t, op: svint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s16_z(pg: svbool_t, op: svint16_t) -> svuint16_t { + svcnt_s16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_m(inactive: svuint32_t, pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv4i32")] + fn _svcnt_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcnt_s32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_x(pg: svbool_t, op: svint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s32_z(pg: svbool_t, op: svint32_t) -> svuint32_t { + svcnt_s32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_m(inactive: svuint64_t, pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnt.nxv2i64")] + fn _svcnt_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcnt_s64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_x(pg: svbool_t, op: svint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(op.as_unsigned(), pg, op) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_s64_z(pg: svbool_t, op: svint64_t) -> svuint64_t { + svcnt_s64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svcnt_s8_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svcnt_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svcnt_s16_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svcnt_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcnt_s32_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svcnt_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcnt_s64_m(inactive, pg, op.as_signed()) } +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(op, pg, op) +} +#[doc = "Count nonzero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnt[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnt))] +pub fn svcnt_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svcnt_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svcntb() -> u64 { + svcntb_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svcnth() -> u64 { + svcnth_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svcntw() -> u64 { + svcntw_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svcntd() -> u64 { + svcntd_pat::<{ svpattern::SV_ALL }>() +} +#[doc = "Count the number of 8-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntb_pat)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (rdvl , PATTERN = { svpattern :: SV_ALL }))] +# [cfg_attr (test , assert_instr (cntb , PATTERN = { svpattern :: SV_MUL4 }))] +pub fn svcntb_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntb")] + fn _svcntb_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntb_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 16-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcnth_pat)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cnth , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcnth_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cnth")] + fn _svcnth_pat(pattern: svpattern) -> i64; + } + unsafe { _svcnth_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 32-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntw_pat)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntw , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntw_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntw")] + fn _svcntw_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntw_pat(PATTERN).as_unsigned() } +} +#[doc = "Count the number of 64-bit elements in a vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntd_pat)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (cntd , PATTERN = { svpattern :: SV_ALL }))] +pub fn svcntd_pat() -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntd")] + fn _svcntd_pat(pattern: svpattern) -> i64; + } + unsafe { _svcntd_pat(PATTERN).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b8(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv16i1")] + fn _svcntp_b8(pg: svbool_t, op: svbool_t) -> i64; + } + unsafe { _svcntp_b8(pg, op).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b16(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv8i1")] + fn _svcntp_b16(pg: svbool8_t, op: svbool8_t) -> i64; + } + unsafe { _svcntp_b16(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b32(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv4i1")] + fn _svcntp_b32(pg: svbool4_t, op: svbool4_t) -> i64; + } + unsafe { _svcntp_b32(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Count set predicate bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcntp_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntp))] +pub fn svcntp_b64(pg: svbool_t, op: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cntp.nxv2i1")] + fn _svcntp_b64(pg: svbool2_t, op: svbool2_t) -> i64; + } + unsafe { _svcntp_b64(pg.sve_into(), op.sve_into()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f32(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4f32" + )] + fn _svcompact_f32(pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svcompact_f32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_f64(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2f64" + )] + fn _svcompact_f64(pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svcompact_f64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s32(pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv4i32" + )] + fn _svcompact_s32(pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svcompact_s32(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_s64(pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.compact.nxv2i64" + )] + fn _svcompact_s64(pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svcompact_s64(pg.sve_into(), op) } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u32(pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svcompact_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Shuffle active elements of vector to the right and fill with zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcompact[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(compact))] +pub fn svcompact_u64(pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svcompact_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f32(x0: svfloat32_t, x1: svfloat32_t) -> svfloat32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_f64(x0: svfloat64_t, x1: svfloat64_t) -> svfloat64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s8(x0: svint8_t, x1: svint8_t) -> svint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s16(x0: svint16_t, x1: svint16_t) -> svint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s32(x0: svint32_t, x1: svint32_t) -> svint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_s64(x0: svint64_t, x1: svint64_t) -> svint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u8(x0: svuint8_t, x1: svuint8_t) -> svuint8x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u16(x0: svuint16_t, x1: svuint16_t) -> svuint16x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u32(x0: svuint32_t, x1: svuint32_t) -> svuint32x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate2_u64(x0: svuint64_t, x1: svuint64_t) -> svuint64x2_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create2(x0, x1) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f32(x0: svfloat32_t, x1: svfloat32_t, x2: svfloat32_t) -> svfloat32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_f64(x0: svfloat64_t, x1: svfloat64_t, x2: svfloat64_t) -> svfloat64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t) -> svint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t) -> svint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t) -> svint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t) -> svint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t) -> svuint8x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u16(x0: svuint16_t, x1: svuint16_t, x2: svuint16_t) -> svuint16x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u32(x0: svuint32_t, x1: svuint32_t, x2: svuint32_t) -> svuint32x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate3[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate3_u64(x0: svuint64_t, x1: svuint64_t, x2: svuint64_t) -> svuint64x3_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create3(x0, x1, x2) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f32( + x0: svfloat32_t, + x1: svfloat32_t, + x2: svfloat32_t, + x3: svfloat32_t, +) -> svfloat32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_f64( + x0: svfloat64_t, + x1: svfloat64_t, + x2: svfloat64_t, + x3: svfloat64_t, +) -> svfloat64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s8(x0: svint8_t, x1: svint8_t, x2: svint8_t, x3: svint8_t) -> svint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s16(x0: svint16_t, x1: svint16_t, x2: svint16_t, x3: svint16_t) -> svint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s32(x0: svint32_t, x1: svint32_t, x2: svint32_t, x3: svint32_t) -> svint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_s64(x0: svint64_t, x1: svint64_t, x2: svint64_t, x3: svint64_t) -> svint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u8(x0: svuint8_t, x1: svuint8_t, x2: svuint8_t, x3: svuint8_t) -> svuint8x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u16( + x0: svuint16_t, + x1: svuint16_t, + x2: svuint16_t, + x3: svuint16_t, +) -> svuint16x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u32( + x0: svuint32_t, + x1: svuint32_t, + x2: svuint32_t, + x3: svuint32_t, +) -> svuint32x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Create a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcreate4[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svcreate4_u64( + x0: svuint64_t, + x1: svuint64_t, + x2: svuint64_t, + x3: svuint64_t, +) -> svuint64x4_t { + unsafe { crate::intrinsics::simd::scalable::sve_tuple_create4(x0, x1, x2, x3) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f32f64")] + fn _svcvt_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvt_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvt_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvt.f64f32")] + fn _svcvt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvt_f64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvt))] +pub fn svcvt_f64_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + svcvt_f64_f32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i32")] + fn _svcvt_f32_s32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_x(pg: svbool_t, op: svint32_t) -> svfloat32_t { + unsafe { svcvt_f32_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s32_z(pg: svbool_t, op: svint32_t) -> svfloat32_t { + svcvt_f32_s32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f32i64")] + fn _svcvt_f32_s64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_x(pg: svbool_t, op: svint64_t) -> svfloat32_t { + unsafe { svcvt_f32_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f32_s64_z(pg: svbool_t, op: svint64_t) -> svfloat32_t { + svcvt_f32_s64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i32")] + fn _svcvt_f32_u32_m(inactive: svfloat32_t, pg: svbool4_t, op: svint32_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + unsafe { svcvt_f32_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat32_t { + svcvt_f32_u32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f32i64")] + fn _svcvt_f32_u64_m(inactive: svfloat32_t, pg: svbool2_t, op: svint64_t) -> svfloat32_t; + } + unsafe { _svcvt_f32_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + unsafe { svcvt_f32_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f32[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f32_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat32_t { + svcvt_f32_u64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i32")] + fn _svcvt_f64_s32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_x(pg: svbool_t, op: svint32_t) -> svfloat64_t { + unsafe { svcvt_f64_s32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s32_z(pg: svbool_t, op: svint32_t) -> svfloat64_t { + svcvt_f64_s32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.scvtf.f64i64")] + fn _svcvt_f64_s64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_x(pg: svbool_t, op: svint64_t) -> svfloat64_t { + unsafe { svcvt_f64_s64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(scvtf))] +pub fn svcvt_f64_s64_z(pg: svbool_t, op: svint64_t) -> svfloat64_t { + svcvt_f64_s64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i32")] + fn _svcvt_f64_u32_m(inactive: svfloat64_t, pg: svbool2_t, op: svint32_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u32_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_x(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + unsafe { svcvt_f64_u32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u32_z(pg: svbool_t, op: svuint32_t) -> svfloat64_t { + svcvt_f64_u32_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ucvtf.f64i64")] + fn _svcvt_f64_u64_m(inactive: svfloat64_t, pg: svbool2_t, op: svint64_t) -> svfloat64_t; + } + unsafe { _svcvt_f64_u64_m(inactive, pg.sve_into(), op.as_signed()) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_x(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + unsafe { svcvt_f64_u64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_f64[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ucvtf))] +pub fn svcvt_f64_u64_z(pg: svbool_t, op: svuint64_t) -> svfloat64_t { + svcvt_f64_u64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f32")] + fn _svcvt_s32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_s32_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svcvt_s32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svcvt_s32_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_m(inactive: svint32_t, pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i32f64")] + fn _svcvt_s32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_s32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_x(pg: svbool_t, op: svfloat64_t) -> svint32_t { + unsafe { svcvt_s32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s32[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s32_f64_z(pg: svbool_t, op: svfloat64_t) -> svint32_t { + svcvt_s32_f64_m(svdup_n_s32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_m(inactive: svint64_t, pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f32")] + fn _svcvt_s64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_s64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_x(pg: svbool_t, op: svfloat32_t) -> svint64_t { + unsafe { svcvt_s64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f32_z(pg: svbool_t, op: svfloat32_t) -> svint64_t { + svcvt_s64_f32_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzs.i64f64")] + fn _svcvt_s64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_s64_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svcvt_s64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_s64[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzs))] +pub fn svcvt_s64_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svcvt_s64_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_m(inactive: svuint32_t, pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f32")] + fn _svcvt_u32_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svcvt_u32_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + unsafe { svcvt_u32_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint32_t { + svcvt_u32_f32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_m(inactive: svuint32_t, pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i32f64")] + fn _svcvt_u32_f64_m(inactive: svint32_t, pg: svbool2_t, op: svfloat64_t) -> svint32_t; + } + unsafe { _svcvt_u32_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + unsafe { svcvt_u32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u32[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u32_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint32_t { + svcvt_u32_f64_m(svdup_n_u32(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_m(inactive: svuint64_t, pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f32")] + fn _svcvt_u64_f32_m(inactive: svint64_t, pg: svbool2_t, op: svfloat32_t) -> svint64_t; + } + unsafe { _svcvt_u64_f32_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_x(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + unsafe { svcvt_u64_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f32_z(pg: svbool_t, op: svfloat32_t) -> svuint64_t { + svcvt_u64_f32_m(svdup_n_u64(0), pg, op) +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_m(inactive: svuint64_t, pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtzu.i64f64")] + fn _svcvt_u64_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svcvt_u64_f64_m(inactive.as_signed(), pg.sve_into(), op).as_unsigned() } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_x(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + unsafe { svcvt_u64_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Floating-point convert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvt_u64[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtzu))] +pub fn svcvt_u64_f64_z(pg: svbool_t, op: svfloat64_t) -> svuint64_t { + svcvt_u64_f64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv4f32")] + fn _svdiv_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdiv_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdiv_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdiv_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdiv.nxv2f64")] + fn _svdiv_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdiv_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdiv_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdiv))] +pub fn svdiv_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdiv_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv4i32")] + fn _svdiv_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdiv_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdiv_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdiv.nxv2i64")] + fn _svdiv_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdiv_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdiv))] +pub fn svdiv_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdiv_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv4i32")] + fn _svdiv_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdiv_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdiv_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdiv_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udiv.nxv2i64")] + fn _svdiv_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdiv_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, op1, op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdiv_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdiv[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udiv))] +pub fn svdiv_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdiv_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv4f32")] + fn _svdivr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svdivr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svdivr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svdivr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fdivr.nxv2f64")] + fn _svdivr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svdivr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svdivr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fdivr))] +pub fn svdivr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svdivr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv4i32")] + fn _svdivr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svdivr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svdivr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdivr.nxv2i64")] + fn _svdivr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svdivr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdivr))] +pub fn svdivr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svdivr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv4i32")] + fn _svdivr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svdivr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svdivr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svdivr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udivr.nxv2i64")] + fn _svdivr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svdivr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, op1, op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svdivr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Divide reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdivr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udivr))] +pub fn svdivr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svdivr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv4i32" + )] + fn _svdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svdot_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot, IMM_INDEX = 0))] +pub fn svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sdot.lane.nxv2i64" + )] + fn _svdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { _svdot_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u32( + op1: svuint32_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv4i32" + )] + fn _svdot_lane_u32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { + _svdot_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot, IMM_INDEX = 0))] +pub fn svdot_lane_u64( + op1: svuint64_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.udot.lane.nxv2i64" + )] + fn _svdot_lane_u64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + ) -> svint64_t; + } + unsafe { + _svdot_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX).as_unsigned() + } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv4i32")] + fn _svdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_s32(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s32(op1: svint32_t, op2: svint8_t, op3: i8) -> svint32_t { + svdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sdot.nxv2i64")] + fn _svdot_s64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_s64(op1, op2, op3) } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sdot))] +pub fn svdot_n_s64(op1: svint64_t, op2: svint16_t, op3: i16) -> svint64_t { + svdot_s64(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv4i32")] + fn _svdot_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svdot_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u32(op1: svuint32_t, op2: svuint8_t, op3: u8) -> svuint32_t { + svdot_u32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_u64(op1: svuint64_t, op2: svuint16_t, op3: svuint16_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.udot.nxv2i64")] + fn _svdot_u64(op1: svint64_t, op2: svint16_t, op3: svint16_t) -> svint64_t; + } + unsafe { _svdot_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdot[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(udot))] +pub fn svdot_n_u64(op1: svuint64_t, op2: svuint16_t, op3: u16) -> svuint64_t { + svdot_u64(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f32(data: svfloat32_t, index: u32) -> svfloat32_t { + svtbl_f32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + svtbl_f64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s8(data: svint8_t, index: u8) -> svint8_t { + svtbl_s8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s16(data: svint16_t, index: u16) -> svint16_t { + svtbl_s16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s32(data: svint32_t, index: u32) -> svint32_t { + svtbl_s32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_s64(data: svint64_t, index: u64) -> svint64_t { + svtbl_s64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u8(data: svuint8_t, index: u8) -> svuint8_t { + svtbl_u8(data, svdup_n_u8(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u16(data: svuint16_t, index: u16) -> svuint16_t { + svtbl_u16(data, svdup_n_u16(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u32(data: svuint32_t, index: u32) -> svuint32_t { + svtbl_u32(data, svdup_n_u32(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdup_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + svtbl_u64(data, svdup_n_u64(index)) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b8(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i1")] + fn _svdup_n_b8(op: bool) -> svbool_t; + } + unsafe { _svdup_n_b8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b16(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i1")] + fn _svdup_n_b16(op: bool) -> svbool8_t; + } + unsafe { _svdup_n_b16(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b32(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i1")] + fn _svdup_n_b32(op: bool) -> svbool4_t; + } + unsafe { _svdup_n_b32(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbfx))] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svdup_n_b64(op: bool) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i1")] + fn _svdup_n_b64(op: bool) -> svbool2_t; + } + unsafe { _svdup_n_b64(op).sve_into() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32(op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4f32")] + fn _svdup_n_f32(op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64(op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2f64")] + fn _svdup_n_f64(op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8(op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv16i8")] + fn _svdup_n_s8(op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16(op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv8i16")] + fn _svdup_n_s16(op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32(op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i32")] + fn _svdup_n_s32(op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64(op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv2i64")] + fn _svdup_n_s64(op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64(op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8(op: u8) -> svuint8_t { + unsafe { svdup_n_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16(op: u16) -> svuint16_t { + unsafe { svdup_n_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32(op: u32) -> svuint32_t { + unsafe { svdup_n_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64(op: u64) -> svuint64_t { + unsafe { svdup_n_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_m(inactive: svfloat32_t, pg: svbool_t, op: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4f32")] + fn _svdup_n_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: f32) -> svfloat32_t; + } + unsafe { _svdup_n_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_x(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f32_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f32_z(pg: svbool_t, op: f32) -> svfloat32_t { + svdup_n_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_m(inactive: svfloat64_t, pg: svbool_t, op: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2f64")] + fn _svdup_n_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: f64) -> svfloat64_t; + } + unsafe { _svdup_n_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_x(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_f64_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_f64_z(pg: svbool_t, op: f64) -> svfloat64_t { + svdup_n_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv16i8")] + fn _svdup_n_s8_m(inactive: svint8_t, pg: svbool_t, op: i8) -> svint8_t; + } + unsafe { _svdup_n_s8_m(inactive, pg, op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_x(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s8_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s8_z(pg: svbool_t, op: i8) -> svint8_t { + svdup_n_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_m(inactive: svint16_t, pg: svbool_t, op: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv8i16")] + fn _svdup_n_s16_m(inactive: svint16_t, pg: svbool8_t, op: i16) -> svint16_t; + } + unsafe { _svdup_n_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_x(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s16_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s16_z(pg: svbool_t, op: i16) -> svint16_t { + svdup_n_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_m(inactive: svint32_t, pg: svbool_t, op: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv4i32")] + fn _svdup_n_s32_m(inactive: svint32_t, pg: svbool4_t, op: i32) -> svint32_t; + } + unsafe { _svdup_n_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_x(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s32_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s32_z(pg: svbool_t, op: i32) -> svint32_t { + svdup_n_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_m(inactive: svint64_t, pg: svbool_t, op: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.nxv2i64")] + fn _svdup_n_s64_m(inactive: svint64_t, pg: svbool2_t, op: i64) -> svint64_t; + } + unsafe { _svdup_n_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_x(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_s64_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_s64_z(pg: svbool_t, op: i64) -> svint64_t { + svdup_n_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_m(inactive: svuint8_t, pg: svbool_t, op: u8) -> svuint8_t { + unsafe { svdup_n_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_x(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u8_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u8_z(pg: svbool_t, op: u8) -> svuint8_t { + svdup_n_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_m(inactive: svuint16_t, pg: svbool_t, op: u16) -> svuint16_t { + unsafe { svdup_n_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_x(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u16_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u16_z(pg: svbool_t, op: u16) -> svuint16_t { + svdup_n_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_m(inactive: svuint32_t, pg: svbool_t, op: u32) -> svuint32_t { + unsafe { svdup_n_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_x(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u32_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u32_z(pg: svbool_t, op: u32) -> svuint32_t { + svdup_n_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_m(inactive: svuint64_t, pg: svbool_t, op: u64) -> svuint64_t { + unsafe { svdup_n_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_x(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a scalar value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdup[_n]_u64_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svdup_n_u64_z(pg: svbool_t, op: u64) -> svuint64_t { + svdup_n_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f32(data: svfloat32_t, index: u64) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4f32" + )] + fn _svdupq_lane_f32(data: svfloat32_t, index: i64) -> svfloat32_t; + } + unsafe { _svdupq_lane_f32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_f64(data: svfloat64_t, index: u64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2f64" + )] + fn _svdupq_lane_f64(data: svfloat64_t, index: i64) -> svfloat64_t; + } + unsafe { _svdupq_lane_f64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s8(data: svint8_t, index: u64) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv16i8" + )] + fn _svdupq_lane_s8(data: svint8_t, index: i64) -> svint8_t; + } + unsafe { _svdupq_lane_s8(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s16(data: svint16_t, index: u64) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv8i16" + )] + fn _svdupq_lane_s16(data: svint16_t, index: i64) -> svint16_t; + } + unsafe { _svdupq_lane_s16(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s32(data: svint32_t, index: u64) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv4i32" + )] + fn _svdupq_lane_s32(data: svint32_t, index: i64) -> svint32_t; + } + unsafe { _svdupq_lane_s32(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_s64(data: svint64_t, index: u64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.dupq.lane.nxv2i64" + )] + fn _svdupq_lane_s64(data: svint64_t, index: i64) -> svint64_t; + } + unsafe { _svdupq_lane_s64(data, index.as_signed()) } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u8(data: svuint8_t, index: u64) -> svuint8_t { + unsafe { svdupq_lane_s8(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u16(data: svuint16_t, index: u64) -> svuint16_t { + unsafe { svdupq_lane_s16(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u32(data: svuint32_t, index: u64) -> svuint32_t { + unsafe { svdupq_lane_s32(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svdupq_lane_u64(data: svuint64_t, index: u64) -> svuint64_t { + unsafe { svdupq_lane_s64(data.as_signed(), index).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b16( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, +) -> svbool_t { + let op1 = svdupq_n_s16( + x0 as i16, x1 as i16, x2 as i16, x3 as i16, x4 as i16, x5 as i16, x6 as i16, x7 as i16, + ); + svcmpne_wide_s16(svptrue_b16(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b32(x0: bool, x1: bool, x2: bool, x3: bool) -> svbool_t { + let op1 = svdupq_n_s32(x0 as i32, x1 as i32, x2 as i32, x3 as i32); + svcmpne_wide_s32(svptrue_b32(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b64(x0: bool, x1: bool) -> svbool_t { + let op1 = svdupq_n_s64(x0 as i64, x1 as i64); + svcmpne_s64(svptrue_b64(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_b8( + x0: bool, + x1: bool, + x2: bool, + x3: bool, + x4: bool, + x5: bool, + x6: bool, + x7: bool, + x8: bool, + x9: bool, + x10: bool, + x11: bool, + x12: bool, + x13: bool, + x14: bool, + x15: bool, +) -> svbool_t { + let op1 = svdupq_n_s8( + x0 as i8, x1 as i8, x2 as i8, x3 as i8, x4 as i8, x5 as i8, x6 as i8, x7 as i8, x8 as i8, + x9 as i8, x10 as i8, x11 as i8, x12 as i8, x13 as i8, x14 as i8, x15 as i8, + ); + svcmpne_wide_s8(svptrue_b8(), op1, svdup_n_s64(0)) +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv4f32.v4f32" + )] + fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t; + } + unsafe { + let op = _svdupq_n_f32(svundef_f32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_f32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv4i32.v4i32" + )] + fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t; + } + unsafe { + let op = _svdupq_n_s32(svundef_s32(), crate::mem::transmute([x0, x1, x2, x3]), 0); + svdupq_lane_s32(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t { + unsafe { + svdupq_n_s32( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv2f64.v2f64" + )] + fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t; + } + unsafe { + let op = _svdupq_n_f64(svundef_f64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_f64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv2i64.v2i64" + )] + fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t; + } + unsafe { + let op = _svdupq_n_s64(svundef_s64(), crate::mem::transmute([x0, x1]), 0); + svdupq_lane_s64(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t { + unsafe { svdupq_n_s64(x0.as_signed(), x1.as_signed()).as_unsigned() } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s16( + x0: i16, + x1: i16, + x2: i16, + x3: i16, + x4: i16, + x5: i16, + x6: i16, + x7: i16, +) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv8i16.v8i16" + )] + fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t; + } + unsafe { + let op = _svdupq_n_s16( + svundef_s16(), + crate::mem::transmute([x0, x1, x2, x3, x4, x5, x6, x7]), + 0, + ); + svdupq_lane_s16(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u16( + x0: u16, + x1: u16, + x2: u16, + x3: u16, + x4: u16, + x5: u16, + x6: u16, + x7: u16, +) -> svuint16_t { + unsafe { + svdupq_n_s16( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_s8( + x0: i8, + x1: i8, + x2: i8, + x3: i8, + x4: i8, + x5: i8, + x6: i8, + x7: i8, + x8: i8, + x9: i8, + x10: i8, + x11: i8, + x12: i8, + x13: i8, + x14: i8, + x15: i8, +) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.experimental.vector.insert.nxv16i8.v16i8" + )] + fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t; + } + unsafe { + let op = _svdupq_n_s8( + svundef_s8(), + crate::mem::transmute([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]), + 0, + ); + svdupq_lane_s8(op, 0) + } +} +#[doc = "Broadcast a quadword of scalars"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svdupq_n_u8( + x0: u8, + x1: u8, + x2: u8, + x3: u8, + x4: u8, + x5: u8, + x6: u8, + x7: u8, + x8: u8, + x9: u8, + x10: u8, + x11: u8, + x12: u8, + x13: u8, + x14: u8, + x15: u8, +) -> svuint8_t { + unsafe { + svdupq_n_s8( + x0.as_signed(), + x1.as_signed(), + x2.as_signed(), + x3.as_signed(), + x4.as_signed(), + x5.as_signed(), + x6.as_signed(), + x7.as_signed(), + x8.as_signed(), + x9.as_signed(), + x10.as_signed(), + x11.as_signed(), + x12.as_signed(), + x13.as_signed(), + x14.as_signed(), + x15.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nvx16i1")] + fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _sveor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv16i8")] + fn _sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveor_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + sveor_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + sveor_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv8i16")] + fn _sveor_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveor_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + sveor_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + sveor_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv4i32")] + fn _sveor_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveor_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + sveor_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + sveor_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv2i64")] + fn _sveor_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveor_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + sveor_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + sveor_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveor_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + sveor_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveor_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveor_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + sveor_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveor_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveor_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + sveor_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveor_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveor_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, op1, op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + sveor_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor))] +pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveor_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv16i8")] + fn _sveorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _sveorv_s8(pg, op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv8i16")] + fn _sveorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _sveorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv4i32")] + fn _sveorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _sveorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv2i64")] + fn _sveorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _sveorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { sveorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { sveorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { sveorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorv))] +pub fn sveorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { sveorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f32(op: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv4f32 " + )] + fn _svexpa_f32(op: svint32_t) -> svfloat32_t; + } + unsafe { _svexpa_f32(op.as_signed()) } +} +#[doc = "Floating-point exponential accelerator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexpa[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fexpa))] +pub fn svexpa_f64(op: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fexpa.x.nxv2f64 " + )] + fn _svexpa_f64(op: svint64_t) -> svfloat64_t; + } + unsafe { _svexpa_f64(op.as_signed()) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4f32")] + fn _svext_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svext_f32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2f64")] + fn _svext_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svext_f64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv16i8")] + fn _svext_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svext_s8(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv8i16")] + fn _svext_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svext_s16(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv4i32")] + fn _svext_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svext_s32(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ext.nxv2i64")] + fn _svext_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svext_s64(op1, op2, IMM3) } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=255); + unsafe { svext_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=127); + unsafe { svext_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svext_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svext[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ext, IMM3 = 1))] +pub fn svext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svext_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv8i16")] + fn _svextb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svextb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv4i32")] + fn _svextb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svextb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv4i32")] + fn _svexth_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svexth_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtb.nxv2i64")] + fn _svextb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtb))] +pub fn svextb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxth.nxv2i64")] + fn _svexth_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxth))] +pub fn svexth_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svexth_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sxtw.nxv2i64")] + fn _svextw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(op, pg, op) +} +#[doc = "Sign-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sxtw))] +pub fn svextw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svextw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv8i16")] + fn _svextb_u16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svextb_u16_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svextb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv4i32")] + fn _svextb_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svextb_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svextb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv4i32")] + fn _svexth_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svexth_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svexth_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtb.nxv2i64")] + fn _svextb_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextb_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 8 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextb[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtb))] +pub fn svextb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxth.nxv2i64")] + fn _svexth_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svexth_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 16 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svexth[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxth))] +pub fn svexth_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svexth_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uxtw.nxv2i64")] + fn _svextw_u64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svextw_u64_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(op, pg, op) +} +#[doc = "Zero-extend the low 32 bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svextw[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uxtw))] +pub fn svextw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svextw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f32(tuple: svfloat32x2_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_f64(tuple: svfloat64x2_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s8(tuple: svint8x2_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s16(tuple: svint16x2_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s32(tuple: svint32x2_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_s64(tuple: svint64x2_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u8(tuple: svuint8x2_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u16(tuple: svuint16x2_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u32(tuple: svuint32x2_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget2_u64(tuple: svuint64x2_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f32(tuple: svfloat32x3_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_f64(tuple: svfloat64x3_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s8(tuple: svint8x3_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s16(tuple: svint16x3_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s32(tuple: svint32x3_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_s64(tuple: svint64x3_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u8(tuple: svuint8x3_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u16(tuple: svuint16x3_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u32(tuple: svuint32x3_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget3[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget3_u64(tuple: svuint64x3_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f32(tuple: svfloat32x4_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_f64(tuple: svfloat64x4_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s8(tuple: svint8x4_t) -> svint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s16(tuple: svint16x4_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s32(tuple: svint32x4_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_s64(tuple: svint64x4_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u8(tuple: svuint8x4_t) -> svuint8_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u16(tuple: svuint16x4_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u32(tuple: svuint32x4_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Extract one vector from a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svget4[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svget4_u64(tuple: svuint64x4_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_get::<_, _, { IMM_INDEX }>(tuple) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s8(base: i8, step: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv16i8")] + fn _svindex_s8(base: i8, step: i8) -> svint8_t; + } + unsafe { _svindex_s8(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s16(base: i16, step: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv8i16")] + fn _svindex_s16(base: i16, step: i16) -> svint16_t; + } + unsafe { _svindex_s16(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s32(base: i32, step: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv4i32")] + fn _svindex_s32(base: i32, step: i32) -> svint32_t; + } + unsafe { _svindex_s32(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_s64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_s64(base: i64, step: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.index.nxv2i64")] + fn _svindex_s64(base: i64, step: i64) -> svint64_t; + } + unsafe { _svindex_s64(base, step) } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u8(base: u8, step: u8) -> svuint8_t { + unsafe { svindex_s8(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u16(base: u16, step: u16) -> svuint16_t { + unsafe { svindex_s16(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u32(base: u32, step: u32) -> svuint32_t { + unsafe { svindex_s32(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Create linear series"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svindex_u64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(index))] +pub fn svindex_u64(base: u64, step: u64) -> svuint64_t { + unsafe { svindex_s64(base.as_signed(), step.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4f32")] + fn _svinsr_n_f32(op1: svfloat32_t, op2: f32) -> svfloat32_t; + } + unsafe { _svinsr_n_f32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2f64")] + fn _svinsr_n_f64(op1: svfloat64_t, op2: f64) -> svfloat64_t; + } + unsafe { _svinsr_n_f64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv16i8")] + fn _svinsr_n_s8(op1: svint8_t, op2: i8) -> svint8_t; + } + unsafe { _svinsr_n_s8(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv8i16")] + fn _svinsr_n_s16(op1: svint16_t, op2: i16) -> svint16_t; + } + unsafe { _svinsr_n_s16(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv4i32")] + fn _svinsr_n_s32(op1: svint32_t, op2: i32) -> svint32_t; + } + unsafe { _svinsr_n_s32(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.insr.nxv2i64")] + fn _svinsr_n_s64(op1: svint64_t, op2: i64) -> svint64_t; + } + unsafe { _svinsr_n_s64(op1, op2) } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + unsafe { svinsr_n_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + unsafe { svinsr_n_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + unsafe { svinsr_n_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Insert scalar in shifted vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svinsr[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(insr))] +pub fn svinsr_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + unsafe { svinsr_n_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4f32")] + fn _svlasta_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlasta_f32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2f64")] + fn _svlasta_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlasta_f64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv16i8")] + fn _svlasta_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlasta_s8(pg, op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv8i16")] + fn _svlasta_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlasta_s16(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv4i32")] + fn _svlasta_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlasta_s32(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lasta.nxv2i64")] + fn _svlasta_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlasta_s64(pg.sve_into(), op) } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlasta_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlasta_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlasta_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract element after last"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlasta[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lasta))] +pub fn svlasta_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlasta_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4f32")] + fn _svlastb_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svlastb_f32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2f64")] + fn _svlastb_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svlastb_f64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv16i8")] + fn _svlastb_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svlastb_s8(pg, op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv8i16")] + fn _svlastb_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svlastb_s16(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv4i32")] + fn _svlastb_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svlastb_s32(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lastb.nxv2i64")] + fn _svlastb_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svlastb_s64(pg.sve_into(), op) } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svlastb_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svlastb_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svlastb_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Extract last element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlastb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lastb))] +pub fn svlastb_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svlastb_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4f32")] + fn _svld1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2f64")] + fn _svld1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv16i8")] + fn _svld1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1_s8(pg, base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i16")] + fn _svld1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i32")] + fn _svld1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i64")] + fn _svld1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4f32" + )] + fn _svld1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32" + )] + fn _svld1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svld1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2f64" + )] + fn _svld1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i64" + )] + fn _svld1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4f32" + )] + fn _svld1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32" + )] + fn _svld1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svld1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svld1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svld1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32" + )] + fn _svld1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32" + )] + fn _svld1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svld1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2f64" + )] + fn _svld1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svld1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i64" + )] + fn _svld1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svld1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32" + )] + fn _svld1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svld1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32" + )] + fn _svld1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svld1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svld1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svld1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svld1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svld1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svld1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svld1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svld1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svld1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svld1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svld1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svld1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svld1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svld1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svld1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svld1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svld1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svld1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svld1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svld1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svld1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svld1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1d))] +pub unsafe fn svld1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svld1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4f32")] + fn _svld1ro_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1ro_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2f64")] + fn _svld1ro_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1ro_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv16i8")] + fn _svld1ro_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1ro_s8(pg, base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv8i16")] + fn _svld1ro_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1ro_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv4i32")] + fn _svld1ro_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1ro_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1ro.nxv2i64")] + fn _svld1ro_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1ro_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rob))] +pub unsafe fn svld1ro_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1ro_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1roh))] +pub unsafe fn svld1ro_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1ro_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1row))] +pub unsafe fn svld1ro_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1ro_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 256 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ro[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rod))] +pub unsafe fn svld1ro_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1ro_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4f32")] + fn _svld1rq_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svld1rq_f32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2f64")] + fn _svld1rq_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svld1rq_f64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv16i8")] + fn _svld1rq_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svld1rq_s8(pg, base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv8i16")] + fn _svld1rq_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svld1rq_s16(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv4i32")] + fn _svld1rq_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svld1rq_s32(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1rq.nxv2i64")] + fn _svld1rq_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svld1rq_s64(pg.sve_into(), base) +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqb))] +pub unsafe fn svld1rq_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svld1rq_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqh))] +pub unsafe fn svld1rq_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svld1rq_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqw))] +pub unsafe fn svld1rq_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svld1rq_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load and replicate 128 bits of data"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1rq[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1rqd))] +pub unsafe fn svld1rq_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svld1rq_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32offset_s32(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svld1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64offset_s64(pg.sve_into(), base, offsets)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svld1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svld1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svld1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svld1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svld1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svld1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svld1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svld1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svld1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svld1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svld1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svld1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svld1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svld1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svld1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svld1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svld1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svld1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sb))] +pub unsafe fn svld1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svld1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svld1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svld1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svld1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svld1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svld1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svld1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svld1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svld1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sh))] +pub unsafe fn svld1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1sw))] +pub unsafe fn svld1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svld1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svld1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8" + )] + fn _svld1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16" + )] + fn _svld1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i8" + )] + fn _svld1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i16" + )] + fn _svld1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.nxv2i32" + )] + fn _svld1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svld1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8" + )] + fn _svld1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16" + )] + fn _svld1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svld1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svld1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svld1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svld1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svld1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svld1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv8i8")] + fn _svld1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i8")] + fn _svld1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv4i16")] + fn _svld1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i8")] + fn _svld1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svld1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i16")] + fn _svld1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ld1.nxv2i32")] + fn _svld1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svld1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svld1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svld1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svld1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svld1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svld1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svld1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svld1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svld1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svld1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svld1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svld1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svld1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svld1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svld1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1b))] +pub unsafe fn svld1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svld1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svld1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svld1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svld1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16" + )] + fn _svld1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i16" + )] + fn _svld1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.index.nxv2i32" + )] + fn _svld1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svld1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svld1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16" + )] + fn _svld1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svld1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svld1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svld1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svld1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svld1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svld1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1h))] +pub unsafe fn svld1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld1w))] +pub unsafe fn svld1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svld1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_f32(pg: svbool_t, base: *const f32) -> svfloat32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4f32" + )] + fn _svld2_f32(pg: svbool4_t, base: *const f32) -> svfloat32x2_t; + } + _svld2_f32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_f64(pg: svbool_t, base: *const f64) -> svfloat64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2f64" + )] + fn _svld2_f64(pg: svbool2_t, base: *const f64) -> svfloat64x2_t; + } + _svld2_f64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv16i8" + )] + fn _svld2_s8(pg: svbool_t, base: *const i8) -> svint8x2_t; + } + _svld2_s8(pg, base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_s16(pg: svbool_t, base: *const i16) -> svint16x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv8i16" + )] + fn _svld2_s16(pg: svbool8_t, base: *const i16) -> svint16x2_t; + } + _svld2_s16(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_s32(pg: svbool_t, base: *const i32) -> svint32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv4i32" + )] + fn _svld2_s32(pg: svbool4_t, base: *const i32) -> svint32x2_t; + } + _svld2_s32(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_s64(pg: svbool_t, base: *const i64) -> svint64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld2.sret.nxv2i64" + )] + fn _svld2_s64(pg: svbool2_t, base: *const i64) -> svint64x2_t; + } + _svld2_s64(pg.sve_into(), base) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_u8(pg: svbool_t, base: *const u8) -> svuint8x2_t { + svld2_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_u16(pg: svbool_t, base: *const u16) -> svuint16x2_t { + svld2_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_u32(pg: svbool_t, base: *const u32) -> svuint32x2_t { + svld2_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_u64(pg: svbool_t, base: *const u64) -> svuint64x2_t { + svld2_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x2_t { + svld2_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x2_t { + svld2_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x2_t { + svld2_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x2_t { + svld2_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x2_t { + svld2_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x2_t { + svld2_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2b))] +pub unsafe fn svld2_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x2_t { + svld2_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2h))] +pub unsafe fn svld2_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x2_t { + svld2_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2w))] +pub unsafe fn svld2_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x2_t { + svld2_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load two-element tuples into two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld2d))] +pub unsafe fn svld2_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x2_t { + svld2_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_f32(pg: svbool_t, base: *const f32) -> svfloat32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4f32" + )] + fn _svld3_f32(pg: svbool4_t, base: *const f32) -> svfloat32x3_t; + } + _svld3_f32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_f64(pg: svbool_t, base: *const f64) -> svfloat64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2f64" + )] + fn _svld3_f64(pg: svbool2_t, base: *const f64) -> svfloat64x3_t; + } + _svld3_f64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv16i8" + )] + fn _svld3_s8(pg: svbool_t, base: *const i8) -> svint8x3_t; + } + _svld3_s8(pg, base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_s16(pg: svbool_t, base: *const i16) -> svint16x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv8i16" + )] + fn _svld3_s16(pg: svbool8_t, base: *const i16) -> svint16x3_t; + } + _svld3_s16(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_s32(pg: svbool_t, base: *const i32) -> svint32x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv4i32" + )] + fn _svld3_s32(pg: svbool4_t, base: *const i32) -> svint32x3_t; + } + _svld3_s32(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_s64(pg: svbool_t, base: *const i64) -> svint64x3_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld3.sret.nxv2i64" + )] + fn _svld3_s64(pg: svbool2_t, base: *const i64) -> svint64x3_t; + } + _svld3_s64(pg.sve_into(), base) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_u8(pg: svbool_t, base: *const u8) -> svuint8x3_t { + svld3_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_u16(pg: svbool_t, base: *const u16) -> svuint16x3_t { + svld3_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_u32(pg: svbool_t, base: *const u32) -> svuint32x3_t { + svld3_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_u64(pg: svbool_t, base: *const u64) -> svuint64x3_t { + svld3_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x3_t { + svld3_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x3_t { + svld3_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x3_t { + svld3_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x3_t { + svld3_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x3_t { + svld3_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x3_t { + svld3_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3b))] +pub unsafe fn svld3_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x3_t { + svld3_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3h))] +pub unsafe fn svld3_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x3_t { + svld3_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3w))] +pub unsafe fn svld3_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x3_t { + svld3_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load three-element tuples into three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld3d))] +pub unsafe fn svld3_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x3_t { + svld3_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_f32(pg: svbool_t, base: *const f32) -> svfloat32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4f32" + )] + fn _svld4_f32(pg: svbool4_t, base: *const f32) -> svfloat32x4_t; + } + _svld4_f32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_f64(pg: svbool_t, base: *const f64) -> svfloat64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2f64" + )] + fn _svld4_f64(pg: svbool2_t, base: *const f64) -> svfloat64x4_t; + } + _svld4_f64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv16i8" + )] + fn _svld4_s8(pg: svbool_t, base: *const i8) -> svint8x4_t; + } + _svld4_s8(pg, base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_s16(pg: svbool_t, base: *const i16) -> svint16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv8i16" + )] + fn _svld4_s16(pg: svbool8_t, base: *const i16) -> svint16x4_t; + } + _svld4_s16(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_s32(pg: svbool_t, base: *const i32) -> svint32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv4i32" + )] + fn _svld4_s32(pg: svbool4_t, base: *const i32) -> svint32x4_t; + } + _svld4_s32(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_s64(pg: svbool_t, base: *const i64) -> svint64x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ld4.sret.nxv2i64" + )] + fn _svld4_s64(pg: svbool2_t, base: *const i64) -> svint64x4_t; + } + _svld4_s64(pg.sve_into(), base) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_u8(pg: svbool_t, base: *const u8) -> svuint8x4_t { + svld4_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_u16(pg: svbool_t, base: *const u16) -> svuint16x4_t { + svld4_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_u32(pg: svbool_t, base: *const u32) -> svuint32x4_t { + svld4_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_u64(pg: svbool_t, base: *const u64) -> svuint64x4_t { + svld4_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32x4_t { + svld4_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64x4_t { + svld4_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8x4_t { + svld4_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16x4_t { + svld4_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32x4_t { + svld4_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64x4_t { + svld4_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4b))] +pub unsafe fn svld4_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8x4_t { + svld4_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4h))] +pub unsafe fn svld4_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16x4_t { + svld4_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4w))] +pub unsafe fn svld4_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32x4_t { + svld4_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load four-element tuples into four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svld4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ld4d))] +pub unsafe fn svld4_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64x4_t { + svld4_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4f32")] + fn _svldff1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldff1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2f64")] + fn _svldff1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldff1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv16i8")] + fn _svldff1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldff1_s8(pg, base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i16")] + fn _svldff1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldff1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i32")] + fn _svldff1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldff1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i64")] + fn _svldff1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldff1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldff1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldff1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldff1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldff1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_f32( + pg: svbool_t, + base: *const f32, + indices: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32" + )] + fn _svldff1_gather_s32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32index_f32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_s32( + pg: svbool_t, + base: *const i32, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32" + )] + fn _svldff1_gather_s32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32index_s32(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32index_u32( + pg: svbool_t, + base: *const u32, + indices: svint32_t, +) -> svuint32_t { + svldff1_gather_s32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2f64" + )] + fn _svldff1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i64" + )] + fn _svldff1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_f32( + pg: svbool_t, + base: *const f32, + indices: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32" + )] + fn _svldff1_gather_u32index_f32( + pg: svbool4_t, + base: *const f32, + indices: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32index_f32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_s32( + pg: svbool_t, + base: *const i32, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32" + )] + fn _svldff1_gather_u32index_s32( + pg: svbool4_t, + base: *const i32, + indices: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32index_s32(pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32index_u32( + pg: svbool_t, + base: *const u32, + indices: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32index_s32(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldff1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4f32" + )] + fn _svldff1_gather_s32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_s32offset_f32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32" + )] + fn _svldff1_gather_s32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_s32offset_s32(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_s32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svint32_t, +) -> svuint32_t { + svldff1_gather_s32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2f64" + )] + fn _svldff1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldff1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i64" + )] + fn _svldff1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldff1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4f32" + )] + fn _svldff1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldff1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32" + )] + fn _svldff1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldff1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldff1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldff1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldff1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldff1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldff1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldff1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldff1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldff1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldff1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldff1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldff1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldff1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldff1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldff1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldff1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldff1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldff1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldff1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldff1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldff1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldff1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1d))] +pub unsafe fn svldff1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldff1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1sb_gather_s32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1sh_gather_s32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32offset_s32( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svint32_t, +) -> svuint32_t { + svldff1sb_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldff1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldff1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldff1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldff1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldff1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldff1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldff1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldff1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldff1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldff1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldff1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldff1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldff1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldff1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldff1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldff1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sb))] +pub unsafe fn svldff1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldff1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldff1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldff1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_s32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_s32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s32index_s32(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s32index_u32( + pg: svbool_t, + base: *const i16, + indices: svint32_t, +) -> svuint32_t { + svldff1sh_gather_s32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldff1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_s32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1sh_gather_u32index_s32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldff1sh_gather_u32index_s32( + pg.sve_into(), + base, + indices.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32index_u32( + pg: svbool_t, + base: *const i16, + indices: svuint32_t, +) -> svuint32_t { + svldff1sh_gather_u32index_s32(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldff1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldff1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sh))] +pub unsafe fn svldff1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1sw))] +pub unsafe fn svldff1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svint32_t { + svldff1ub_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8" + )] + fn _svldff1ub_gather_s32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16" + )] + fn _svldff1uh_gather_s32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32offset_u32(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i8" + )] + fn _svldff1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i16" + )] + fn _svldff1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.nxv2i32" + )] + fn _svldff1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldff1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8" + )] + fn _svldff1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16" + )] + fn _svldff1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldff1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldff1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldff1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldff1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldff1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldff1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv8i8")] + fn _svldff1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i8")] + fn _svldff1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv4i16")] + fn _svldff1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i8")] + fn _svldff1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldff1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i16")] + fn _svldff1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldff1.nxv2i32")] + fn _svldff1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldff1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldff1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldff1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldff1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldff1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldff1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldff1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldff1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldff1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldff1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldff1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldff1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldff1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldff1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldff1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1b))] +pub unsafe fn svldff1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldff1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldff1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldff1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_s32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svint32_t { + svldff1uh_gather_s32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s32index_u32( + pg: svbool_t, + base: *const u16, + indices: svint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_s32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s32index_u32(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i16" + )] + fn _svldff1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.index.nxv2i32" + )] + fn _svldff1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_s32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svint32_t { + svldff1uh_gather_u32index_u32(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u32]index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32index_u32( + pg: svbool_t, + base: *const u16, + indices: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16" + )] + fn _svldff1uh_gather_u32index_u32( + pg: svbool4_t, + base: *const i16, + indices: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldff1uh_gather_u32index_u32(pg.sve_into(), base.as_signed(), indices.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldff1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldff1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldff1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldff1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldff1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1h))] +pub unsafe fn svldff1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, first-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldff1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldff1w))] +pub unsafe fn svldff1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldff1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4f32")] + fn _svldnf1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnf1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2f64")] + fn _svldnf1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnf1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv16i8")] + fn _svldnf1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnf1_s8(pg, base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i16")] + fn _svldnf1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnf1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i32")] + fn _svldnf1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnf1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i64")] + fn _svldnf1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnf1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnf1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnf1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnf1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnf1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnf1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnf1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnf1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnf1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnf1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnf1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnf1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnf1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnf1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1d))] +pub unsafe fn svldnf1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnf1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s16(pg: svbool_t, base: *const i8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1sb_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s16(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s32(pg: svbool_t, base: *const i8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1sb_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s32(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s32(pg: svbool_t, base: *const i16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1sh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s32(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_s64(pg: svbool_t, base: *const i8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1sb_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnf1sb_s64(pg.sve_into(), base)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_s64(pg: svbool_t, base: *const i16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1sh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnf1sh_s64(pg.sve_into(), base)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_s64(pg: svbool_t, base: *const i32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1sw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnf1sw_s64(pg.sve_into(), base)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u16(pg: svbool_t, base: *const i8) -> svuint16_t { + svldnf1sb_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u32(pg: svbool_t, base: *const i8) -> svuint32_t { + svldnf1sb_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u32(pg: svbool_t, base: *const i16) -> svuint32_t { + svldnf1sh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_u64(pg: svbool_t, base: *const i8) -> svuint64_t { + svldnf1sb_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_u64(pg: svbool_t, base: *const i16) -> svuint64_t { + svldnf1sh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_u64(pg: svbool_t, base: *const i32) -> svuint64_t { + svldnf1sw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s16(pg: svbool_t, base: *const i8, vnum: i64) -> svint16_t { + svldnf1sb_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s32(pg: svbool_t, base: *const i8, vnum: i64) -> svint32_t { + svldnf1sb_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s32(pg: svbool_t, base: *const i16, vnum: i64) -> svint32_t { + svldnf1sh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_s64(pg: svbool_t, base: *const i8, vnum: i64) -> svint64_t { + svldnf1sb_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_s64(pg: svbool_t, base: *const i16, vnum: i64) -> svint64_t { + svldnf1sh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_s64(pg: svbool_t, base: *const i32, vnum: i64) -> svint64_t { + svldnf1sw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u16(pg: svbool_t, base: *const i8, vnum: i64) -> svuint16_t { + svldnf1sb_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u32(pg: svbool_t, base: *const i8, vnum: i64) -> svuint32_t { + svldnf1sb_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u32(pg: svbool_t, base: *const i16, vnum: i64) -> svuint32_t { + svldnf1sh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sb_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sb))] +pub unsafe fn svldnf1sb_vnum_u64(pg: svbool_t, base: *const i8, vnum: i64) -> svuint64_t { + svldnf1sb_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sh))] +pub unsafe fn svldnf1sh_vnum_u64(pg: svbool_t, base: *const i16, vnum: i64) -> svuint64_t { + svldnf1sh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and sign-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1sw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1sw))] +pub unsafe fn svldnf1sw_vnum_u64(pg: svbool_t, base: *const i32, vnum: i64) -> svuint64_t { + svldnf1sw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s16(pg: svbool_t, base: *const u8) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv8i8")] + fn _svldnf1ub_s16(pg: svbool8_t, base: *const i8) -> nxv8i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s16(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s32(pg: svbool_t, base: *const u8) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i8")] + fn _svldnf1ub_s32(pg: svbool4_t, base: *const i8) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s32(pg: svbool_t, base: *const u16) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv4i16")] + fn _svldnf1uh_s32(pg: svbool4_t, base: *const i16) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s32(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_s64(pg: svbool_t, base: *const u8) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i8")] + fn _svldnf1ub_s64(pg: svbool2_t, base: *const i8) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1ub_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_s64(pg: svbool_t, base: *const u16) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i16")] + fn _svldnf1uh_s64(pg: svbool2_t, base: *const i16) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uh_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_s64(pg: svbool_t, base: *const u32) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnf1.nxv2i32")] + fn _svldnf1uw_s64(pg: svbool2_t, base: *const i32) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnf1uw_s64(pg.sve_into(), base.as_signed()).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u16(pg: svbool_t, base: *const u8) -> svuint16_t { + svldnf1ub_s16(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u32(pg: svbool_t, base: *const u8) -> svuint32_t { + svldnf1ub_s32(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u32(pg: svbool_t, base: *const u16) -> svuint32_t { + svldnf1uh_s32(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_u64(pg: svbool_t, base: *const u8) -> svuint64_t { + svldnf1ub_s64(pg, base).as_unsigned() +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_u64(pg: svbool_t, base: *const u16) -> svuint64_t { + svldnf1uh_s64(pg, base).as_unsigned() +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_u64(pg: svbool_t, base: *const u32) -> svuint64_t { + svldnf1uw_s64(pg, base).as_unsigned() +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s16(pg: svbool_t, base: *const u8, vnum: i64) -> svint16_t { + svldnf1ub_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s32(pg: svbool_t, base: *const u8, vnum: i64) -> svint32_t { + svldnf1ub_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s32(pg: svbool_t, base: *const u16, vnum: i64) -> svint32_t { + svldnf1uh_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_s64(pg: svbool_t, base: *const u8, vnum: i64) -> svint64_t { + svldnf1ub_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_s64(pg: svbool_t, base: *const u16, vnum: i64) -> svint64_t { + svldnf1uh_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_s64(pg: svbool_t, base: *const u32, vnum: i64) -> svint64_t { + svldnf1uw_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u16)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u16(pg: svbool_t, base: *const u8, vnum: i64) -> svuint16_t { + svldnf1ub_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u32(pg: svbool_t, base: *const u8, vnum: i64) -> svuint32_t { + svldnf1ub_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u32(pg: svbool_t, base: *const u16, vnum: i64) -> svuint32_t { + svldnf1uh_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Load 8-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1ub_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1b))] +pub unsafe fn svldnf1ub_vnum_u64(pg: svbool_t, base: *const u8, vnum: i64) -> svuint64_t { + svldnf1ub_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 16-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uh_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1h))] +pub unsafe fn svldnf1uh_vnum_u64(pg: svbool_t, base: *const u16, vnum: i64) -> svuint64_t { + svldnf1uh_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Load 32-bit data and zero-extend, non-faulting"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnf1uw_vnum_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour)."] +#[doc = " * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of predication. Refer to architectural documentation for details."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnf1w))] +pub unsafe fn svldnf1uw_vnum_u64(pg: svbool_t, base: *const u32, vnum: i64) -> svuint64_t { + svldnf1uw_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_f32(pg: svbool_t, base: *const f32) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4f32")] + fn _svldnt1_f32(pg: svbool4_t, base: *const f32) -> svfloat32_t; + } + _svldnt1_f32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_f64(pg: svbool_t, base: *const f64) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2f64")] + fn _svldnt1_f64(pg: svbool2_t, base: *const f64) -> svfloat64_t; + } + _svldnt1_f64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv16i8")] + fn _svldnt1_s8(pg: svbool_t, base: *const i8) -> svint8_t; + } + _svldnt1_s8(pg, base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_s16(pg: svbool_t, base: *const i16) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv8i16")] + fn _svldnt1_s16(pg: svbool8_t, base: *const i16) -> svint16_t; + } + _svldnt1_s16(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_s32(pg: svbool_t, base: *const i32) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv4i32")] + fn _svldnt1_s32(pg: svbool4_t, base: *const i32) -> svint32_t; + } + _svldnt1_s32(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_s64(pg: svbool_t, base: *const i64) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ldnt1.nxv2i64")] + fn _svldnt1_s64(pg: svbool2_t, base: *const i64) -> svint64_t; + } + _svldnt1_s64(pg.sve_into(), base) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_u8(pg: svbool_t, base: *const u8) -> svuint8_t { + svldnt1_s8(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_u16(pg: svbool_t, base: *const u16) -> svuint16_t { + svldnt1_s16(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_u32(pg: svbool_t, base: *const u32) -> svuint32_t { + svldnt1_s32(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_u64(pg: svbool_t, base: *const u64) -> svuint64_t { + svldnt1_s64(pg, base.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_f32(pg: svbool_t, base: *const f32, vnum: i64) -> svfloat32_t { + svldnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_f64(pg: svbool_t, base: *const f64, vnum: i64) -> svfloat64_t { + svldnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_s8(pg: svbool_t, base: *const i8, vnum: i64) -> svint8_t { + svldnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_s16(pg: svbool_t, base: *const i16, vnum: i64) -> svint16_t { + svldnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_s32(pg: svbool_t, base: *const i32, vnum: i64) -> svint32_t { + svldnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_s64(pg: svbool_t, base: *const i64, vnum: i64) -> svint64_t { + svldnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1_vnum_u8(pg: svbool_t, base: *const u8, vnum: i64) -> svuint8_t { + svldnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1_vnum_u16(pg: svbool_t, base: *const u16, vnum: i64) -> svuint16_t { + svldnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_vnum_u32(pg: svbool_t, base: *const u32, vnum: i64) -> svuint32_t { + svldnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_vnum_u64(pg: svbool_t, base: *const u64, vnum: i64) -> svuint64_t { + svldnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_f32(_op: svfloat32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_f64(_op: svfloat64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_s8(_op: svint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_s16(_op: svint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_s32(_op: svint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_s64(_op: svint64_t) -> u64 { + svcntd() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdvl))] +pub fn svlen_u8(_op: svuint8_t) -> u64 { + svcntb() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cnth))] +pub fn svlen_u16(_op: svuint16_t) -> u64 { + svcnth() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntw))] +pub fn svlen_u32(_op: svuint32_t) -> u64 { + svcntw() +} +#[doc = "Count the number of elements in a full vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlen[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cntd))] +pub fn svlen_u64(_op: svuint64_t) -> u64 { + svcntd() +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv16i8")] + fn _svlsl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsl_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svlsl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svlsl_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv8i16")] + fn _svlsl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsl_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svlsl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svlsl_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv4i32")] + fn _svlsl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsl_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svlsl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svlsl_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsl.nxv2i64")] + fn _svlsl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsl_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svlsl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svlsl_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svlsl_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsl_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svlsl_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsl_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svlsl_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsl_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svlsl_s64_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsl_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv16i8" + )] + fn _svlsl_wide_s8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsl_wide_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint64_t) -> svint8_t { + svlsl_wide_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u64) -> svint8_t { + svlsl_wide_s8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv8i16" + )] + fn _svlsl_wide_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsl_wide_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint64_t) -> svint16_t { + svlsl_wide_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u64) -> svint16_t { + svlsl_wide_s16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsl.wide.nxv4i32" + )] + fn _svlsl_wide_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsl_wide_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint64_t) -> svint32_t { + svlsl_wide_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u64) -> svint32_t { + svlsl_wide_s32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe { svlsl_wide_s8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsl_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsl_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe { svlsl_wide_s16_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsl_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsl_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe { svlsl_wide_s32_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsl_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsl_wide[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsl))] +pub fn svlsl_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsl_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv16i8")] + fn _svlsr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svlsr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svlsr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svlsr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv8i16")] + fn _svlsr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svlsr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svlsr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svlsr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv4i32")] + fn _svlsr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svlsr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svlsr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svlsr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.lsr.nxv2i64")] + fn _svlsr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svlsr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svlsr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svlsr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv16i8" + )] + fn _svlsr_wide_u8_m(pg: svbool_t, op1: svint8_t, op2: svint64_t) -> svint8_t; + } + unsafe { _svlsr_wide_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint64_t) -> svuint8_t { + svlsr_wide_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u64) -> svuint8_t { + svlsr_wide_u8_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv8i16" + )] + fn _svlsr_wide_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint64_t) -> svint16_t; + } + unsafe { _svlsr_wide_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint64_t) -> svuint16_t { + svlsr_wide_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u64) -> svuint16_t { + svlsr_wide_u16_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.lsr.wide.nxv4i32" + )] + fn _svlsr_wide_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svlsr_wide_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, op1, op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint64_t) -> svuint32_t { + svlsr_wide_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Logical shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlsr_wide[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(lsr))] +pub fn svlsr_wide_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u64) -> svuint32_t { + svlsr_wide_u32_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv4f32")] + fn _svmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmad.nxv2f64")] + fn _svmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmad))] +pub fn svmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv16i8")] + fn _svmad_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmad_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmad_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmad_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv8i16")] + fn _svmad_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmad_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmad_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmad_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv4i32")] + fn _svmad_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmad_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmad_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmad_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mad.nxv2i64")] + fn _svmad_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmad_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmad_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmad_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmad_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmad_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmad_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmad_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmad_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmad_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmad_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmad_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmad_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmad_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmad_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mad))] +pub fn svmad_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmad_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv4f32")] + fn _svmax_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmax_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmax_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmax_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmax.nxv2f64")] + fn _svmax_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmax_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmax_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmax))] +pub fn svmax_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmax_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv16i8")] + fn _svmax_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_s8_m(pg, op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmax_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmax_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv8i16")] + fn _svmax_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmax_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmax_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv4i32")] + fn _svmax_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmax_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmax_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smax.nxv2i64")] + fn _svmax_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmax_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smax))] +pub fn svmax_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmax_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv16i8")] + fn _svmax_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmax_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmax_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmax_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv8i16")] + fn _svmax_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmax_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmax_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmax_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv4i32")] + fn _svmax_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmax_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmax_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmax_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umax.nxv2i64")] + fn _svmax_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmax_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, op1, op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmax_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmax[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umax))] +pub fn svmax_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmax_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv4f32")] + fn _svmaxnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmaxnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxnm.nxv2f64")] + fn _svmaxnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, op1, op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Maximum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnm[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnm))] +pub fn svmaxnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmaxnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv4f32" + )] + fn _svmaxnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxnmv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmv[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub fn svmaxnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmv.nxv2f64" + )] + fn _svmaxnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxnmv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv4f32")] + fn _svmaxv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svmaxv_f32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxv))] +pub fn svmaxv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxv.nxv2f64")] + fn _svmaxv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svmaxv_f64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv16i8")] + fn _svmaxv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_s8(pg, op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv8i16")] + fn _svmaxv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_s16(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv4i32")] + fn _svmaxv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_s32(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxv))] +pub fn svmaxv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxv.nxv2i64")] + fn _svmaxv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_s64(pg.sve_into(), op) } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv16i8")] + fn _svmaxv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svmaxv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv8i16")] + fn _svmaxv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svmaxv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv4i32")] + fn _svmaxv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svmaxv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Maximum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxv))] +pub fn svmaxv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxv.nxv2i64")] + fn _svmaxv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svmaxv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv4f32")] + fn _svmin_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmin_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmin_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmin_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmin.nxv2f64")] + fn _svmin_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmin_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmin_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmin))] +pub fn svmin_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmin_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv16i8")] + fn _svmin_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_s8_m(pg, op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmin_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmin_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv8i16")] + fn _svmin_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmin_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmin_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv4i32")] + fn _svmin_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmin_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmin_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smin.nxv2i64")] + fn _svmin_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmin_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smin))] +pub fn svmin_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmin_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv16i8")] + fn _svmin_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmin_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmin_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmin_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv8i16")] + fn _svmin_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmin_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmin_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmin_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv4i32")] + fn _svmin_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmin_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmin_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmin_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umin.nxv2i64")] + fn _svmin_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmin_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, op1, op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmin_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmin[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umin))] +pub fn svmin_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmin_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv4f32")] + fn _svminnm_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnm_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnm_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svminnm_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminnm.nxv2f64")] + fn _svminnm_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnm_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, op1, op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnm_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Minimum number"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnm[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnm))] +pub fn svminnm_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svminnm_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv4f32" + )] + fn _svminnmv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminnmv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum number reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmv[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmv))] +pub fn svminnmv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmv.nxv2f64" + )] + fn _svminnmv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminnmv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f32(pg: svbool_t, op: svfloat32_t) -> f32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv4f32")] + fn _svminv_f32(pg: svbool4_t, op: svfloat32_t) -> f32; + } + unsafe { _svminv_f32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminv))] +pub fn svminv_f64(pg: svbool_t, op: svfloat64_t) -> f64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminv.nxv2f64")] + fn _svminv_f64(pg: svbool2_t, op: svfloat64_t) -> f64; + } + unsafe { _svminv_f64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv16i8")] + fn _svminv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_s8(pg, op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv8i16")] + fn _svminv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_s16(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv4i32")] + fn _svminv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_s32(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminv))] +pub fn svminv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminv.nxv2i64")] + fn _svminv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_s64(pg.sve_into(), op) } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv16i8")] + fn _svminv_u8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svminv_u8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv8i16")] + fn _svminv_u16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svminv_u16(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv4i32")] + fn _svminv_u32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svminv_u32(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Minimum reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminv))] +pub fn svminv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminv.nxv2i64")] + fn _svminv_u64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svminv_u64(pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv4f32")] + fn _svmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmla.nxv2f64")] + fn _svmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla))] +pub fn svmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv16i8")] + fn _svmla_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmla_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmla_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmla_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv8i16")] + fn _svmla_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmla_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmla_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmla_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv4i32")] + fn _svmla_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmla_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmla_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmla_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mla.nxv2i64")] + fn _svmla_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmla_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmla_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmla_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmla_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmla_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmla_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmla_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmla_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmla_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmla_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmla_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmla_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmla_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmla_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla))] +pub fn svmla_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmla_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv4f32" + )] + fn _svmla_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmla_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmla, IMM_INDEX = 0))] +pub fn svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmla.lane.nxv2f64" + )] + fn _svmla_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmla_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv4f32")] + fn _svmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmls.nxv2f64")] + fn _svmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls))] +pub fn svmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv16i8")] + fn _svmls_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmls_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmls_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmls_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv8i16")] + fn _svmls_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmls_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmls_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmls_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv4i32")] + fn _svmls_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmls_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmls_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmls_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mls.nxv2i64")] + fn _svmls_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmls_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmls_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmls_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmls_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmls_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmls_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmls_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmls_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmls_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmls_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmls_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmls_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmls_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmls_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls))] +pub fn svmls_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmls_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv4f32" + )] + fn _svmls_lane_f32( + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + IMM_INDEX: i32, + ) -> svfloat32_t; + } + unsafe { _svmls_lane_f32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmls, IMM_INDEX = 0))] +pub fn svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmls.lane.nxv2f64" + )] + fn _svmls_lane_f64( + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + IMM_INDEX: i32, + ) -> svfloat64_t; + } + unsafe { _svmls_lane_f64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f32mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv4f32")] + fn _svmmla_f32(op1: svfloat32_t, op2: svfloat32_t, op3: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmmla_f32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmmla))] +pub fn svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmmla.nxv2f64")] + fn _svmmla_f64(op1: svfloat64_t, op2: svfloat64_t, op3: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmmla_f64(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smmla))] +pub fn svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smmla.nxv4i32")] + fn _svmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_s32(op1, op2, op3) } +} +#[doc = "Matrix multiply-accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmmla[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ummla))] +pub fn svmmla_u32(op1: svuint32_t, op2: svuint8_t, op3: svuint8_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ummla.nxv4i32")] + fn _svmmla_u32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svmmla_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmov[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mov))] +pub fn svmov_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + svand_b_z(pg, op, op) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv4f32")] + fn _svmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmsb.nxv2f64")] + fn _svmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmsb))] +pub fn svmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv16i8")] + fn _svmsb_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svmsb_s8_m(pg, op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_m(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_x(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + svmsb_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svmsb_s8_z(pg, op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv8i16")] + fn _svmsb_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) + -> svint16_t; + } + unsafe { _svmsb_s16_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_m(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_x(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + svmsb_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svmsb_s16_z(pg, op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv4i32")] + fn _svmsb_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) + -> svint32_t; + } + unsafe { _svmsb_s32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_m(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_x(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + svmsb_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svmsb_s32_z(pg, op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.msb.nxv2i64")] + fn _svmsb_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) + -> svint64_t; + } + unsafe { _svmsb_s64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_m(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_x(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + svmsb_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svmsb_s64_z(pg, op1, op2, svdup_n_s64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svmsb_s8_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_x(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + svmsb_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svmsb_u8_z(pg, op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svmsb_s16_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_x(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + svmsb_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svmsb_u16_z(pg, op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svmsb_s32_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_x(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + svmsb_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svmsb_u32_z(pg, op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svmsb_s64_m(pg, op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, op1, op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_x(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + svmsb_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2, op3) +} +#[doc = "Multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(msb))] +pub fn svmsb_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svmsb_u64_z(pg, op1, op2, svdup_n_u64(op3)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv4f32")] + fn _svmul_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmul_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmul_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmul_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmul.nxv2f64")] + fn _svmul_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmul_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmul_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul))] +pub fn svmul_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmul_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv16i8")] + fn _svmul_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmul_s8_m(pg, op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmul_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmul_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv8i16")] + fn _svmul_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmul_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmul_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmul_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv4i32")] + fn _svmul_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmul_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmul_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmul_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.mul.nxv2i64")] + fn _svmul_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmul_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmul_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmul_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svmul_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmul_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmul_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svmul_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmul_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmul_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svmul_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmul_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmul_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svmul_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, op1, op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmul_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul))] +pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmul_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv16i8")] + fn _svmulh_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_s8_m(pg, op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmulh_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svmulh_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv8i16")] + fn _svmulh_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmulh_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svmulh_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv4i32")] + fn _svmulh_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmulh_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svmulh_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smulh.nxv2i64")] + fn _svmulh_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmulh_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smulh))] +pub fn svmulh_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svmulh_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv16i8")] + fn _svmulh_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmulh_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmulh_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svmulh_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv8i16")] + fn _svmulh_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmulh_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmulh_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svmulh_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv4i32")] + fn _svmulh_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmulh_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmulh_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svmulh_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umulh.nxv2i64")] + fn _svmulh_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmulh_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, op1, op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmulh_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Multiply, returning high-half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulh[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umulh))] +pub fn svmulh_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svmulh_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv4f32")] + fn _svmulx_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmulx_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmulx_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svmulx_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmulx.nxv2f64")] + fn _svmulx_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmulx_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, op1, op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmulx_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Multiply extended (∞×0=2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmulx[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmulx))] +pub fn svmulx_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svmulx_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Bitwise NAND"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnand[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nand))] +pub fn svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nand.z.nxv16i1")] + fn _svnand_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnand_b_z(pg, op1, op2) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv4f32")] + fn _svneg_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svneg_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svneg_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fneg.nxv2f64")] + fn _svneg_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svneg_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fneg))] +pub fn svneg_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svneg_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv16i8")] + fn _svneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svneg_s8_m(inactive, pg, op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv8i16")] + fn _svneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv4i32")] + fn _svneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.neg.nxv2i64")] + fn _svneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(op, pg, op) +} +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svneg[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(neg))] +pub fn svneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv4f32")] + fn _svnmad_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmad_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmad_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmad_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmad.nxv2f64")] + fn _svnmad_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmad_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmad_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmad))] +pub fn svnmad_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmad_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv4f32")] + fn _svnmla_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmla_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmla_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmla_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmla.nxv2f64")] + fn _svnmla_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmla_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmla_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmla))] +pub fn svnmla_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmla_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv4f32")] + fn _svnmls_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmls_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmls_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmls_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmls.nxv2f64")] + fn _svnmls_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmls_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmls_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmls))] +pub fn svnmls_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmls_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_m( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv4f32")] + fn _svnmsb_f32_m( + pg: svbool4_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, + ) -> svfloat32_t; + } + unsafe { _svnmsb_f32_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_x( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_x(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f32_z( + pg: svbool_t, + op1: svfloat32_t, + op2: svfloat32_t, + op3: svfloat32_t, +) -> svfloat32_t { + svnmsb_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t, op3: f32) -> svfloat32_t { + svnmsb_f32_z(pg, op1, op2, svdup_n_f32(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_m( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fnmsb.nxv2f64")] + fn _svnmsb_f64_m( + pg: svbool2_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, + ) -> svfloat64_t; + } + unsafe { _svnmsb_f64_m(pg.sve_into(), op1, op2, op3) } +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_x( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, op1, op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_x(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_f64_z( + pg: svbool_t, + op1: svfloat64_t, + op2: svfloat64_t, + op3: svfloat64_t, +) -> svfloat64_t { + svnmsb_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2, op3) +} +#[doc = "Negated multiply-subtract, multiplicand first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fnmsb))] +pub fn svnmsb_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t, op3: f64) -> svfloat64_t { + svnmsb_f64_z(pg, op1, op2, svdup_n_f64(op3)) +} +#[doc = "Bitwise NOR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnor[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nor))] +pub fn svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nor.z.nxv16i1")] + fn _svnor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svnor_b_z(pg, op1, op2) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_b_z(pg: svbool_t, op: svbool_t) -> svbool_t { + sveor_b_z(pg, op, pg) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv16i8")] + fn _svnot_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svnot_s8_m(inactive, pg, op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svnot_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv8i16")] + fn _svnot_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svnot_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svnot_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv4i32")] + fn _svnot_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svnot_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svnot_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.not.nxv2i64")] + fn _svnot_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svnot_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svnot_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svnot_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svnot_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svnot_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svnot_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svnot_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svnot_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svnot_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(op, pg, op) +} +#[doc = "Bitwise invert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnot[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(not))] +pub fn svnot_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svnot_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Bitwise inclusive OR, inverting second argument"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorn[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orn))] +pub fn svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orn.z.nvx16i1")] + fn _svorn_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorn_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_b]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.z.nvx16i1")] + fn _svorr_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svorr_b_z(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv16i8")] + fn _svorr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svorr_s8_m(pg, op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svorr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svorr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv8i16")] + fn _svorr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svorr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svorr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svorr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv4i32")] + fn _svorr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svorr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svorr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svorr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orr.nxv2i64")] + fn _svorr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svorr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svorr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svorr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svorr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svorr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svorr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svorr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svorr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svorr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svorr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svorr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svorr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svorr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, op1, op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svorr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Bitwise inclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orr))] +pub fn svorr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svorr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s8(pg: svbool_t, op: svint8_t) -> i8 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv16i8")] + fn _svorv_s8(pg: svbool_t, op: svint8_t) -> i8; + } + unsafe { _svorv_s8(pg, op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s16(pg: svbool_t, op: svint16_t) -> i16 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv8i16")] + fn _svorv_s16(pg: svbool8_t, op: svint16_t) -> i16; + } + unsafe { _svorv_s16(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s32(pg: svbool_t, op: svint32_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv4i32")] + fn _svorv_s32(pg: svbool4_t, op: svint32_t) -> i32; + } + unsafe { _svorv_s32(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_s64(pg: svbool_t, op: svint64_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.orv.nxv2i64")] + fn _svorv_s64(pg: svbool2_t, op: svint64_t) -> i64; + } + unsafe { _svorv_s64(pg.sve_into(), op) } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u8(pg: svbool_t, op: svuint8_t) -> u8 { + unsafe { svorv_s8(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u16(pg: svbool_t, op: svuint16_t) -> u16 { + unsafe { svorv_s16(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u32(pg: svbool_t, op: svuint32_t) -> u32 { + unsafe { svorv_s32(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise inclusive OR reduction to scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorv[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(orv))] +pub fn svorv_u64(pg: svbool_t, op: svuint64_t) -> u64 { + unsafe { svorv_s64(pg, op.as_signed()).as_unsigned() } +} +#[doc = "Set all predicate elements to false"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfalse[_b])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svpfalse_b() -> svbool_t { + svdupq_n_b8( + false, false, false, false, false, false, false, false, false, false, false, false, false, + false, false, false, + ) +} +#[doc = "Set the first active predicate element to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpfirst[_b])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pfirst))] +pub fn svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pfirst.nxv16i1")] + fn _svpfirst_b(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpfirst_b(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv16i1")] + fn _svpnext_b8(pg: svbool_t, op: svbool_t) -> svbool_t; + } + unsafe { _svpnext_b8(pg, op) } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b16(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv8i1")] + fn _svpnext_b16(pg: svbool8_t, op: svbool8_t) -> svbool8_t; + } + unsafe { _svpnext_b16(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b32(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv4i1")] + fn _svpnext_b32(pg: svbool4_t, op: svbool4_t) -> svbool4_t; + } + unsafe { _svpnext_b32(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Find next active predicate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpnext_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pnext))] +pub fn svpnext_b64(pg: svbool_t, op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pnext.nxv2i1")] + fn _svpnext_b64(pg: svbool2_t, op: svbool2_t) -> svbool2_t; + } + unsafe { _svpnext_b64(pg.sve_into(), op.sve_into()).sve_into() } +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv16i1")] + fn _svprfb(pg: svbool_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfb(pg, base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv8i1")] + fn _svprfh(pg: svbool8_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfh(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv4i1")] + fn _svprfw(pg: svbool4_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfw(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd(pg: svbool_t, base: *const T) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.prf.nxv2i1")] + fn _svprfd(pg: svbool2_t, base: *const crate::ffi::c_void, op: svprfop); + } + _svprfd(pg.sve_into(), base as *const crate::ffi::c_void, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s32offset( + pg: svbool_t, + base: *const T, + offsets: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.sxtw.index.nxv4i32" + )] + fn _svprfb_gather_s32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_s32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.sxtw.index.nxv4i32" + )] + fn _svprfh_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.sxtw.index.nxv4i32" + )] + fn _svprfw_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s32index( + pg: svbool_t, + base: *const T, + indices: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.sxtw.index.nxv4i32" + )] + fn _svprfd_gather_s32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_s32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[s64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_s64offset( + pg: svbool_t, + base: *const T, + offsets: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.index.nxv2i64" + )] + fn _svprfb_gather_s64offset( + pg: svbool2_t, + base: *const crate::ffi::c_void, + offsets: svint64_t, + op: svprfop, + ); + } + _svprfb_gather_s64offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets, + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.index.nxv2i64" + )] + fn _svprfh_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfh_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.index.nxv2i64" + )] + fn _svprfw_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfw_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[s64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_s64index( + pg: svbool_t, + base: *const T, + indices: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.index.nxv2i64" + )] + fn _svprfd_gather_s64index( + pg: svbool2_t, + base: *const crate::ffi::c_void, + indices: svint64_t, + op: svprfop, + ); + } + _svprfd_gather_s64index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices, + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u32]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u32offset( + pg: svbool_t, + base: *const T, + offsets: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.uxtw.index.nxv4i32" + )] + fn _svprfb_gather_u32offset( + pg: svbool4_t, + base: *const crate::ffi::c_void, + offsets: svint32_t, + op: svprfop, + ); + } + _svprfb_gather_u32offset( + pg.sve_into(), + base as *const crate::ffi::c_void, + offsets.as_signed(), + OP, + ) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.uxtw.index.nxv4i32" + )] + fn _svprfh_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfh_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.uxtw.index.nxv4i32" + )] + fn _svprfw_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfw_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u32]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u32index( + pg: svbool_t, + base: *const T, + indices: svuint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.uxtw.index.nxv4i32" + )] + fn _svprfd_gather_u32index( + pg: svbool4_t, + base: *const crate::ffi::c_void, + indices: svint32_t, + op: svprfop, + ); + } + _svprfd_gather_u32index( + pg.sve_into(), + base as *const crate::ffi::c_void, + indices.as_signed(), + OP, + ) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather_[u64]offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_gather_u64offset( + pg: svbool_t, + base: *const T, + offsets: svuint64_t, +) { + svprfb_gather_s64offset::(pg, base, offsets.as_signed()) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfh_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfw_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather_[u64]index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_gather_u64index( + pg: svbool_t, + base: *const T, + indices: svuint64_t, +) { + svprfd_gather_s64index::(pg, base, indices.as_signed()) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfb_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base(pg: svbool_t, bases: svuint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfb_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base(pg: svbool_t, bases: svuint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base(pg.sve_into(), bases.as_signed(), 0, OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u32base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u32base_offset( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32" + )] + fn _svprfb_gather_u32base_offset(pg: svbool4_t, bases: svint32_t, offset: i64, op: svprfop); + } + _svprfb_gather_u32base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32" + )] + fn _svprfh_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfh_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32" + )] + fn _svprfw_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfw_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u32base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u32base_index( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32" + )] + fn _svprfd_gather_u32base_index(pg: svbool4_t, bases: svint32_t, index: i64, op: svprfop); + } + _svprfd_gather_u32base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_gather[_u64base]_offset)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfb_gather_u64base_offset( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64" + )] + fn _svprfb_gather_u64base_offset(pg: svbool2_t, bases: svint64_t, offset: i64, op: svprfop); + } + _svprfb_gather_u64base_offset(pg.sve_into(), bases.as_signed(), offset, OP) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfh_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfh.gather.scalar.offset.nxv2i64" + )] + fn _svprfh_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfh_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(1), OP) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfw_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfw.gather.scalar.offset.nxv2i64" + )] + fn _svprfw_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfw_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(2), OP) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_gather[_u64base]_index)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP }))] +pub unsafe fn svprfd_gather_u64base_index( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.prfd.gather.scalar.offset.nxv2i64" + )] + fn _svprfd_gather_u64base_index(pg: svbool2_t, bases: svint64_t, index: i64, op: svprfop); + } + _svprfd_gather_u64base_index(pg.sve_into(), bases.as_signed(), index.unchecked_shl(3), OP) +} +#[doc = "Prefetch bytes"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfb_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfb , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfb_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfb::(pg, base.offset(svcntb() as isize * vnum as isize)) +} +#[doc = "Prefetch halfwords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfh_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfh , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfh_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfh::(pg, base.offset(svcnth() as isize * vnum as isize)) +} +#[doc = "Prefetch words"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfw_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfw , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfw_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfw::(pg, base.offset(svcntw() as isize * vnum as isize)) +} +#[doc = "Prefetch doublewords"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svprfd_vnum)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (prfd , OP = { svprfop :: SV_PLDL1KEEP } , T = i64))] +pub unsafe fn svprfd_vnum(pg: svbool_t, base: *const T, vnum: i64) { + svprfd::(pg, base.offset(svcntd() as isize * vnum as isize)) +} +#[doc = "Test whether any active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_any)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_any(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.any.nxv16i1" + )] + fn _svptest_any(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_any(pg, op) } +} +#[doc = "Test whether first active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_first)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_first(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.first.nxv16i1" + )] + fn _svptest_first(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_first(pg, op) } +} +#[doc = "Test whether last active element is true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptest_last)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptest))] +pub fn svptest_last(pg: svbool_t, op: svbool_t) -> bool { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ptest.last.nxv16i1" + )] + fn _svptest_last(pg: svbool_t, op: svbool_t) -> bool; + } + unsafe { _svptest_last(pg, op) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b8() -> svbool_t { + svptrue_pat_b8::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b16() -> svbool_t { + svptrue_pat_b16::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b32() -> svbool_t { + svptrue_pat_b32::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ptrue))] +pub fn svptrue_b64() -> svbool_t { + svptrue_pat_b64::<{ svpattern::SV_ALL }>() +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b8() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv16i1")] + fn _svptrue_pat_b8(pattern: svpattern) -> svbool_t; + } + unsafe { _svptrue_pat_b8(PATTERN) } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b16() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv8i1")] + fn _svptrue_pat_b16(pattern: svpattern) -> svbool8_t; + } + unsafe { _svptrue_pat_b16(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b32() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv4i1")] + fn _svptrue_pat_b32(pattern: svpattern) -> svbool4_t; + } + unsafe { _svptrue_pat_b32(PATTERN).sve_into() } +} +#[doc = "Set predicate elements to true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svptrue_pat_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (ptrue , PATTERN = { svpattern :: SV_ALL }))] +pub fn svptrue_pat_b64() -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ptrue.nxv2i1")] + fn _svptrue_pat_b64(pattern: svpattern) -> svbool2_t; + } + unsafe { _svptrue_pat_b64(PATTERN).sve_into() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv16i8" + )] + fn _svqadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv8i16" + )] + fn _svqadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv4i32" + )] + fn _svqadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqadd.x.nxv2i64" + )] + fn _svqadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64(op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv16i8" + )] + fn _svqadd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv8i16" + )] + fn _svqadd_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv4i32" + )] + fn _svqadd_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqadd.x.nxv2i64" + )] + fn _svqadd_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s32(op: i32) -> i32 { + svqdecb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s32(op: i32) -> i32 { + svqdech_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s32(op: i32) -> i32 { + svqdecw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s32(op: i32) -> i32 { + svqdecd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_s64(op: i64) -> i64 { + svqdecb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_s64(op: i64) -> i64 { + svqdech_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_s64(op: i64) -> i64 { + svqdecw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_s64(op: i64) -> i64 { + svqdecd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u32(op: u32) -> u32 { + svqdecb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u32(op: u32) -> u32 { + svqdech_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u32(op: u32) -> u32 { + svqdecw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u32(op: u32) -> u32 { + svqdecd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecb, IMM_FACTOR = 1))] +pub fn svqdecb_n_u64(op: u64) -> u64 { + svqdecb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_n_u64(op: u64) -> u64 { + svqdech_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_n_u64(op: u64) -> u64 { + svqdecw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_n_u64(op: u64) -> u64 { + svqdecd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n32")] + fn _svqdecb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n32")] + fn _svqdech_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n32")] + fn _svqdecw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n32")] + fn _svqdecd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecb.n64")] + fn _svqdecb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.n64")] + fn _svqdech_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.n64")] + fn _svqdecw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.n64")] + fn _svqdecd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n32")] + fn _svqdecb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n32")] + fn _svqdech_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdech_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n32")] + fn _svqdecw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n32")] + fn _svqdecd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqdecd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecb_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecb.n64")] + fn _svqdecb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.n64")] + fn _svqdech_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdech_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.n64")] + fn _svqdecw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.n64")] + fn _svqdecd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqdecd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdech.nxv8i16")] + fn _svqdech_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecw.nxv4i32")] + fn _svqdecw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecd.nxv2i64")] + fn _svqdecd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech_pat[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdech , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdech_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdech.nxv8i16")] + fn _svqdech_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqdech_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw_pat[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecw.nxv4i32")] + fn _svqdecw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqdecw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd_pat[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqdecd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqdecd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecd.nxv2i64")] + fn _svqdecd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqdecd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdech, IMM_FACTOR = 1))] +pub fn svqdech_s16(op: svint16_t) -> svint16_t { + svqdech_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_s32(op: svint32_t) -> svint32_t { + svqdecw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_s64(op: svint64_t) -> svint64_t { + svqdecd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdech[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdech, IMM_FACTOR = 1))] +pub fn svqdech_u16(op: svuint16_t) -> svuint16_t { + svqdech_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecw[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecw, IMM_FACTOR = 1))] +pub fn svqdecw_u32(op: svuint32_t) -> svuint32_t { + svqdecw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecd[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecd, IMM_FACTOR = 1))] +pub fn svqdecd_u64(op: svuint64_t) -> svuint64_t { + svqdecd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_s32_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s32]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_s64_b8(op, pg) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_s64]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv16i1" + )] + fn _svqdecp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqdecp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv8i1" + )] + fn _svqdecp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqdecp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv4i1" + )] + fn _svqdecp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqdecp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u32]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n32.nxv2i1" + )] + fn _svqdecp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqdecp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv16i1" + )] + fn _svqdecp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqdecp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv8i1" + )] + fn _svqdecp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqdecp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv4i1" + )] + fn _svqdecp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqdecp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_n_u64]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqdecp.n64.nxv2i1" + )] + fn _svqdecp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqdecp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv8i16")] + fn _svqdecp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv4i32")] + fn _svqdecp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdecp))] +pub fn svqdecp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqdecp.nxv2i64")] + fn _svqdecp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv8i16")] + fn _svqdecp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqdecp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv4i32")] + fn _svqdecp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqdecp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating decrement by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdecp[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqdecp))] +pub fn svqdecp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqdecp.nxv2i64")] + fn _svqdecp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqdecp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s32(op: i32) -> i32 { + svqincb_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s32(op: i32) -> i32 { + svqinch_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s32(op: i32) -> i32 { + svqincw_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s32(op: i32) -> i32 { + svqincd_pat_n_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_s64(op: i64) -> i64 { + svqincb_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_s64(op: i64) -> i64 { + svqinch_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_s64(op: i64) -> i64 { + svqincw_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_s64(op: i64) -> i64 { + svqincd_pat_n_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u32(op: u32) -> u32 { + svqincb_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u32(op: u32) -> u32 { + svqinch_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u32(op: u32) -> u32 { + svqincw_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u32(op: u32) -> u32 { + svqincd_pat_n_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincb, IMM_FACTOR = 1))] +pub fn svqincb_n_u64(op: u64) -> u64 { + svqincb_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_n_u64(op: u64) -> u64 { + svqinch_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_n_u64(op: u64) -> u64 { + svqincw_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_n_u64(op: u64) -> u64 { + svqincd_pat_n_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n32")] + fn _svqincb_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n32")] + fn _svqinch_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n32")] + fn _svqincw_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s32(op: i32) -> i32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n32")] + fn _svqincd_pat_n_s32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincb.n64")] + fn _svqincb_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.n64")] + fn _svqinch_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.n64")] + fn _svqincw_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_s64(op: i64) -> i64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.n64")] + fn _svqincd_pat_n_s64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n32")] + fn _svqincb_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincb_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n32")] + fn _svqinch_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqinch_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n32")] + fn _svqincw_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincw_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u32(op: u32) -> u32 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n32")] + fn _svqincd_pat_n_u32(op: i32, pattern: svpattern, imm_factor: i32) -> i32; + } + unsafe { _svqincd_pat_n_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of byte elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincb_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincb , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincb_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincb.n64")] + fn _svqincb_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincb_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.n64")] + fn _svqinch_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqinch_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.n64")] + fn _svqincw_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincw_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_n_u64(op: u64) -> u64 { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.n64")] + fn _svqincd_pat_n_u64(op: i64, pattern: svpattern, imm_factor: i32) -> i64; + } + unsafe { _svqincd_pat_n_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_s16( + op: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqinch.nxv8i16")] + fn _svqinch_pat_s16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_s16(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_s32( + op: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincw.nxv4i32")] + fn _svqincw_pat_s32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_s32(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (sqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_s64( + op: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincd.nxv2i64")] + fn _svqincd_pat_s64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_s64(op, PATTERN, IMM_FACTOR) } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch_pat[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqinch , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqinch_pat_u16( + op: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqinch.nxv8i16")] + fn _svqinch_pat_u16(op: svint16_t, pattern: svpattern, imm_factor: i32) -> svint16_t; + } + unsafe { _svqinch_pat_u16(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw_pat[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincw , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincw_pat_u32( + op: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincw.nxv4i32")] + fn _svqincw_pat_u32(op: svint32_t, pattern: svpattern, imm_factor: i32) -> svint32_t; + } + unsafe { _svqincw_pat_u32(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd_pat[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +# [cfg_attr (test , assert_instr (uqincd , PATTERN = { svpattern :: SV_ALL } , IMM_FACTOR = 1))] +pub fn svqincd_pat_u64( + op: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_FACTOR, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincd.nxv2i64")] + fn _svqincd_pat_u64(op: svint64_t, pattern: svpattern, imm_factor: i32) -> svint64_t; + } + unsafe { _svqincd_pat_u64(op.as_signed(), PATTERN, IMM_FACTOR).as_unsigned() } +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqinch, IMM_FACTOR = 1))] +pub fn svqinch_s16(op: svint16_t) -> svint16_t { + svqinch_pat_s16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincw, IMM_FACTOR = 1))] +pub fn svqincw_s32(op: svint32_t) -> svint32_t { + svqincw_pat_s32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincd, IMM_FACTOR = 1))] +pub fn svqincd_s64(op: svint64_t) -> svint64_t { + svqincd_pat_s64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of halfword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqinch[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqinch, IMM_FACTOR = 1))] +pub fn svqinch_u16(op: svuint16_t) -> svuint16_t { + svqinch_pat_u16::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of word elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincw[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincw, IMM_FACTOR = 1))] +pub fn svqincw_u32(op: svuint32_t) -> svuint32_t { + svqincw_pat_u32::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by number of doubleword elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincd[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincd, IMM_FACTOR = 1))] +pub fn svqincd_u64(op: svuint64_t) -> svuint64_t { + svqincd_pat_u64::<{ svpattern::SV_ALL }, IMM_FACTOR>(op) +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv16i1" + )] + fn _svqincp_n_s32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_s32_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b16(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv8i1" + )] + fn _svqincp_n_s32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_s32_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b32(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv4i1" + )] + fn _svqincp_n_s32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_s32_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s32]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s32_b64(op: i32, pg: svbool_t) -> i32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n32.nxv2i1" + )] + fn _svqincp_n_s32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_s32_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv16i1" + )] + fn _svqincp_n_s64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_s64_b8(op, pg) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b16(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv8i1" + )] + fn _svqincp_n_s64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_s64_b16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b32(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv4i1" + )] + fn _svqincp_n_s64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_s64_b32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_s64]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_n_s64_b64(op: i64, pg: svbool_t) -> i64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqincp.n64.nxv2i1" + )] + fn _svqincp_n_s64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_s64_b64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b8(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv16i1" + )] + fn _svqincp_n_u32_b8(op: i32, pg: svbool_t) -> i32; + } + unsafe { _svqincp_n_u32_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b16(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv8i1" + )] + fn _svqincp_n_u32_b16(op: i32, pg: svbool8_t) -> i32; + } + unsafe { _svqincp_n_u32_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b32(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv4i1" + )] + fn _svqincp_n_u32_b32(op: i32, pg: svbool4_t) -> i32; + } + unsafe { _svqincp_n_u32_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u32]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u32_b64(op: u32, pg: svbool_t) -> u32 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n32.nxv2i1" + )] + fn _svqincp_n_u32_b64(op: i32, pg: svbool2_t) -> i32; + } + unsafe { _svqincp_n_u32_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b8(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv16i1" + )] + fn _svqincp_n_u64_b8(op: i64, pg: svbool_t) -> i64; + } + unsafe { _svqincp_n_u64_b8(op.as_signed(), pg).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b16(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv8i1" + )] + fn _svqincp_n_u64_b16(op: i64, pg: svbool8_t) -> i64; + } + unsafe { _svqincp_n_u64_b16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b32(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv4i1" + )] + fn _svqincp_n_u64_b32(op: i64, pg: svbool4_t) -> i64; + } + unsafe { _svqincp_n_u64_b32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_n_u64]_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_n_u64_b64(op: u64, pg: svbool_t) -> u64 { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqincp.n64.nxv2i1" + )] + fn _svqincp_n_u64_b64(op: i64, pg: svbool2_t) -> i64; + } + unsafe { _svqincp_n_u64_b64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s16(op: svint16_t, pg: svbool_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv8i16")] + fn _svqincp_s16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_s16(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s32(op: svint32_t, pg: svbool_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv4i32")] + fn _svqincp_s32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_s32(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqincp))] +pub fn svqincp_s64(op: svint64_t, pg: svbool_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqincp.nxv2i64")] + fn _svqincp_s64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_s64(op, pg.sve_into()) } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u16(op: svuint16_t, pg: svbool_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv8i16")] + fn _svqincp_u16(op: svint16_t, pg: svbool8_t) -> svint16_t; + } + unsafe { _svqincp_u16(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u32(op: svuint32_t, pg: svbool_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv4i32")] + fn _svqincp_u32(op: svint32_t, pg: svbool4_t) -> svint32_t; + } + unsafe { _svqincp_u32(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating increment by active element count"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqincp[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqincp))] +pub fn svqincp_u64(op: svuint64_t, pg: svbool_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqincp.nxv2i64")] + fn _svqincp_u64(op: svint64_t, pg: svbool2_t) -> svint64_t; + } + unsafe { _svqincp_u64(op.as_signed(), pg.sve_into()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv16i8" + )] + fn _svqsub_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv8i16" + )] + fn _svqsub_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv4i32" + )] + fn _svqsub_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqsub.x.nxv2i64" + )] + fn _svqsub_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64(op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv16i8" + )] + fn _svqsub_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv8i16" + )] + fn _svqsub_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv4i32" + )] + fn _svqsub_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqsub.x.nxv2i64" + )] + fn _svqsub_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv16i8")] + fn _svrbit_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svrbit_s8_m(inactive, pg, op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svrbit_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv8i16")] + fn _svrbit_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrbit_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrbit_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv4i32")] + fn _svrbit_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrbit_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrbit_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rbit.nxv2i64")] + fn _svrbit_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrbit_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrbit_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_m(inactive: svuint8_t, pg: svbool_t, op: svuint8_t) -> svuint8_t { + unsafe { svrbit_s8_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_x(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u8_z(pg: svbool_t, op: svuint8_t) -> svuint8_t { + svrbit_u8_m(svdup_n_u8(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrbit_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrbit_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrbit_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrbit_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrbit_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(op, pg, op) +} +#[doc = "Reverse bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrbit[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rbit))] +pub fn svrbit_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrbit_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr() -> svbool_t { + svrdffr_z(svptrue_b8()) +} +#[doc = "Read FFR, returning predicate of succesfully loaded elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrdffr_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rdffr))] +pub fn svrdffr_z(pg: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rdffr.z")] + fn _svrdffr_z(pg: svbool_t) -> svbool_t; + } + unsafe { _svrdffr_z(pg) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv4f32" + )] + fn _svrecpe_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpe_f32(op) } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpe))] +pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpe.x.nxv2f64" + )] + fn _svrecpe_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpe_f64(op) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv4f32" + )] + fn _svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecps_f32(op1, op2) } +} +#[doc = "Reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecps))] +pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecps.x.nxv2f64" + )] + fn _svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecps_f64(op1, op2) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpx.x.nxv4f32" + )] + fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrecpx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrecpx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frecpx.x.nxv2f64" + )] + fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrecpx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(op, pg, op) +} +#[doc = "Reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frecpx))] +pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrecpx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f32(op: svfloat32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_f64(op: svfloat64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s8(op: svint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s16(op: svint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s32(op: svint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_s64(op: svint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u8(op: svuint8_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u16(op: svuint16_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u32(op: svuint32_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f32_u64(op: svuint64_t) -> svfloat32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f32(op: svfloat32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_f64(op: svfloat64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s8(op: svint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s16(op: svint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s32(op: svint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_s64(op: svint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u8(op: svuint8_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u16(op: svuint16_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u32(op: svuint32_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_f64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_f64_u64(op: svuint64_t) -> svfloat64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f32(op: svfloat32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_f64(op: svfloat64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s8(op: svint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s16(op: svint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s32(op: svint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_s64(op: svint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u8(op: svuint8_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u16(op: svuint16_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u32(op: svuint32_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s8_u64(op: svuint64_t) -> svint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f32(op: svfloat32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_f64(op: svfloat64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s8(op: svint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s16(op: svint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s32(op: svint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_s64(op: svint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u8(op: svuint8_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u16(op: svuint16_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u32(op: svuint32_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s16_u64(op: svuint64_t) -> svint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f32(op: svfloat32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_f64(op: svfloat64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s8(op: svint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s16(op: svint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s32(op: svint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_s64(op: svint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u8(op: svuint8_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u16(op: svuint16_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u32(op: svuint32_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s32_u64(op: svuint64_t) -> svint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f32(op: svfloat32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_f64(op: svfloat64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s8(op: svint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s16(op: svint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s32(op: svint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_s64(op: svint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u8(op: svuint8_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u16(op: svuint16_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u32(op: svuint32_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_s64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_s64_u64(op: svuint64_t) -> svint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f32(op: svfloat32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_f64(op: svfloat64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s8(op: svint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s16(op: svint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s32(op: svint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_s64(op: svint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u8(op: svuint8_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u16(op: svuint16_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u32(op: svuint32_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u8_u64(op: svuint64_t) -> svuint8_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f32(op: svfloat32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_f64(op: svfloat64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s8(op: svint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s16(op: svint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s32(op: svint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_s64(op: svint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u8(op: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u16(op: svuint16_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u32(op: svuint32_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u16_u64(op: svuint64_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f32(op: svfloat32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_f64(op: svfloat64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s8(op: svint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s16(op: svint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s32(op: svint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_s64(op: svint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u8(op: svuint8_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u16(op: svuint16_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u32(op: svuint32_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u32_u64(op: svuint64_t) -> svuint32_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f32(op: svfloat32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_f64(op: svfloat64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s8(op: svint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s16(op: svint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s32(op: svint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_s64(op: svint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u8(op: svuint8_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u16(op: svuint16_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u32(op: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reinterpret vector contents"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svreinterpret_u64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svreinterpret_u64_u64(op: svuint64_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b8(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i1")] + fn _svrev_b8(op: svbool_t) -> svbool_t; + } + unsafe { _svrev_b8(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b16(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i1")] + fn _svrev_b16(op: svbool8_t) -> svbool8_t; + } + unsafe { _svrev_b16(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b32(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i1")] + fn _svrev_b32(op: svbool4_t) -> svbool4_t; + } + unsafe { _svrev_b32(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_b64(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i1")] + fn _svrev_b64(op: svbool2_t) -> svbool2_t; + } + unsafe { _svrev_b64(op.sve_into()).sve_into() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4f32")] + fn _svrev_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrev_f32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2f64")] + fn _svrev_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrev_f64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s8(op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv16i8")] + fn _svrev_s8(op: svint8_t) -> svint8_t; + } + unsafe { _svrev_s8(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s16(op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv8i16")] + fn _svrev_s16(op: svint16_t) -> svint16_t; + } + unsafe { _svrev_s16(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s32(op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv4i32")] + fn _svrev_s32(op: svint32_t) -> svint32_t; + } + unsafe { _svrev_s32(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_s64(op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rev.nxv2i64")] + fn _svrev_s64(op: svint64_t) -> svint64_t; + } + unsafe { _svrev_s64(op) } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u8(op: svuint8_t) -> svuint8_t { + unsafe { svrev_s8(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u16(op: svuint16_t) -> svuint16_t { + unsafe { svrev_s16(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u32(op: svuint32_t) -> svuint32_t { + unsafe { svrev_s32(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse all elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrev[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rev))] +pub fn svrev_u64(op: svuint64_t) -> svuint64_t { + unsafe { svrev_s64(op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv8i16")] + fn _svrevb_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svrevb_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svrevb_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv4i32")] + fn _svrevb_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevb_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevb_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revb.nxv2i64")] + fn _svrevb_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevb_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevb_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_m(inactive: svuint16_t, pg: svbool_t, op: svuint16_t) -> svuint16_t { + unsafe { svrevb_s16_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_x(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u16_z(pg: svbool_t, op: svuint16_t) -> svuint16_t { + svrevb_u16_m(svdup_n_u16(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevb_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevb_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevb_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(op, pg, op) +} +#[doc = "Reverse bytes within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevb[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revb))] +pub fn svrevb_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevb_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv4i32")] + fn _svrevh_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrevh_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svrevh_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revh.nxv2i64")] + fn _svrevh_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevh_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevh_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe { svrevh_s32_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrevh_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevh_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(op, pg, op) +} +#[doc = "Reverse halfwords within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevh[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revh))] +pub fn svrevh_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevh_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.revw.nxv2i64")] + fn _svrevw_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svrevw_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svrevw_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_m(inactive: svuint64_t, pg: svbool_t, op: svuint64_t) -> svuint64_t { + unsafe { svrevw_s64_m(inactive.as_signed(), pg, op.as_signed()).as_unsigned() } +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_x(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(op, pg, op) +} +#[doc = "Reverse words within elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrevw[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(revw))] +pub fn svrevw_u64_z(pg: svbool_t, op: svuint64_t) -> svuint64_t { + svrevw_u64_m(svdup_n_u64(0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv4f32")] + fn _svrinta_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinta_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinta_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinta.nxv2f64")] + fn _svrinta_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinta_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties away from zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinta[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinta))] +pub fn svrinta_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinta_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv4f32")] + fn _svrinti_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrinti_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrinti_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frinti.nxv2f64")] + fn _svrinti_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrinti_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (inexact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrinti[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frinti))] +pub fn svrinti_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrinti_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv4f32")] + fn _svrintm_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintm_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintm_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintm.nxv2f64")] + fn _svrintm_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintm_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(op, pg, op) +} +#[doc = "Round towards -∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintm[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintm))] +pub fn svrintm_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintm_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv4f32")] + fn _svrintn_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintn_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintn_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintn.nxv2f64")] + fn _svrintn_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintn_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(op, pg, op) +} +#[doc = "Round to nearest, ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintn[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintn))] +pub fn svrintn_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintn_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv4f32")] + fn _svrintp_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintp_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintp_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintp.nxv2f64")] + fn _svrintp_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintp_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(op, pg, op) +} +#[doc = "Round towards +∞"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintp[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintp))] +pub fn svrintp_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintp_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv4f32")] + fn _svrintx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintx_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintx_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintx.nxv2f64")] + fn _svrintx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintx_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(op, pg, op) +} +#[doc = "Round using current rounding mode (exact)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintx[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintx))] +pub fn svrintx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintx_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv4f32")] + fn _svrintz_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrintz_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svrintz_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.frintz.nxv2f64")] + fn _svrintz_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrintz_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(op, pg, op) +} +#[doc = "Round towards zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrintz[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frintz))] +pub fn svrintz_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svrintz_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv4f32" + )] + fn _svrsqrte_f32(op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrte_f32(op) } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrte))] +pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrte.x.nxv2f64" + )] + fn _svrsqrte_f64(op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrte_f64(op) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv4f32" + )] + fn _svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svrsqrts_f32(op1, op2) } +} +#[doc = "Reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(frsqrts))] +pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.frsqrts.x.nxv2f64" + )] + fn _svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svrsqrts_f64(op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv4f32")] + fn _svscale_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svscale_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svint32_t) -> svfloat32_t { + svscale_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: i32) -> svfloat32_t { + svscale_f32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fscale.nxv2f64")] + fn _svscale_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svscale_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, op1, op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svint64_t) -> svfloat64_t { + svscale_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svscale[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fscale))] +pub fn svscale_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: i64) -> svfloat64_t { + svscale_f64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_b])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_b(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe { simd_select(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { simd_select::(pg, op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Conditionally select elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsel[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sel))] +pub fn svsel_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { simd_select::(pg.sve_into(), op1, op2) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f32(tuple: svfloat32x2_t, x: svfloat32_t) -> svfloat32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_f64(tuple: svfloat64x2_t, x: svfloat64_t) -> svfloat64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s8(tuple: svint8x2_t, x: svint8_t) -> svint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s16(tuple: svint16x2_t, x: svint16_t) -> svint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s32(tuple: svint32x2_t, x: svint32_t) -> svint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_s64(tuple: svint64x2_t, x: svint64_t) -> svint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u8(tuple: svuint8x2_t, x: svuint8_t) -> svuint8x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u16(tuple: svuint16x2_t, x: svuint16_t) -> svuint16x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u32(tuple: svuint32x2_t, x: svuint32_t) -> svuint32x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset2_u64(tuple: svuint64x2_t, x: svuint64_t) -> svuint64x2_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f32(tuple: svfloat32x3_t, x: svfloat32_t) -> svfloat32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_f64(tuple: svfloat64x3_t, x: svfloat64_t) -> svfloat64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s8(tuple: svint8x3_t, x: svint8_t) -> svint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s16(tuple: svint16x3_t, x: svint16_t) -> svint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s32(tuple: svint32x3_t, x: svint32_t) -> svint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_s64(tuple: svint64x3_t, x: svint64_t) -> svint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u8(tuple: svuint8x3_t, x: svuint8_t) -> svuint8x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u16(tuple: svuint16x3_t, x: svuint16_t) -> svuint16x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u32(tuple: svuint32x3_t, x: svuint32_t) -> svuint32x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset3[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset3_u64(tuple: svuint64x3_t, x: svuint64_t) -> svuint64x3_t { + static_assert_range!(IMM_INDEX, 0..=2); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f32(tuple: svfloat32x4_t, x: svfloat32_t) -> svfloat32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_f64(tuple: svfloat64x4_t, x: svfloat64_t) -> svfloat64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s8(tuple: svint8x4_t, x: svint8_t) -> svint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s16(tuple: svint16x4_t, x: svint16_t) -> svint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s32(tuple: svint32x4_t, x: svint32_t) -> svint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_s64(tuple: svint64x4_t, x: svint64_t) -> svint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u8(tuple: svuint8x4_t, x: svuint8_t) -> svuint8x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u16(tuple: svuint16x4_t, x: svuint16_t) -> svuint16x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u32(tuple: svuint32x4_t, x: svuint32_t) -> svuint32x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Change one vector in a tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svset4[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub fn svset4_u64(tuple: svuint64x4_t, x: svuint64_t) -> svuint64x4_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { crate::intrinsics::simd::scalable::sve_tuple_set::<_, _, { IMM_INDEX }>(tuple, x) } +} +#[doc = "Initialize the first-fault register to all-true"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsetffr)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(setffr))] +pub fn svsetffr() { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.setffr")] + fn _svsetffr(); + } + unsafe { _svsetffr() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f32(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4f32")] + fn _svsplice_f32(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsplice_f32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_f64(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2f64")] + fn _svsplice_f64(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsplice_f64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv16i8")] + fn _svsplice_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsplice_s8(pg, op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv8i16")] + fn _svsplice_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsplice_s16(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s32(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv4i32")] + fn _svsplice_s32(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsplice_s32(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_s64(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.splice.nxv2i64")] + fn _svsplice_s64(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsplice_s64(pg.sve_into(), op1, op2) } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsplice_s8(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsplice_s16(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u32(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsplice_s32(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Splice two vectors under predicate control"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsplice[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(splice))] +pub fn svsplice_u64(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsplice_s64(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv4f32")] + fn _svsqrt_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsqrt_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t { + svsqrt_f32_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsqrt.nxv2f64")] + fn _svsqrt_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsqrt_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(op, pg, op) +} +#[doc = "Square root"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqrt[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsqrt))] +pub fn svsqrt_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t { + svsqrt_f64_m(svdup_n_f64(0.0), pg, op) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4f32")] + fn _svst1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2f64")] + fn _svst1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv16i8")] + fn _svst1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst1_s8(data, pg, base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i16")] + fn _svst1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i32")] + fn _svst1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i64")] + fn _svst1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svst1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svst1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svst1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svst1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32" + )] + fn _svst1_scatter_s32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_f32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32" + )] + fn _svst1_scatter_s32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_s32index_s32(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2f64" + )] + fn _svst1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i64" + )] + fn _svst1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svst1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_f32( + pg: svbool_t, + base: *mut f32, + indices: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32" + )] + fn _svst1_scatter_u32index_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_f32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_s32( + pg: svbool_t, + base: *mut i32, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32" + )] + fn _svst1_scatter_u32index_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + indices: svint32_t, + ); + } + _svst1_scatter_u32index_s32(data, pg.sve_into(), base, indices.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32index_u32( + pg: svbool_t, + base: *mut u32, + indices: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32" + )] + fn _svst1_scatter_s32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_f32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32" + )] + fn _svst1_scatter_s32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_s32offset_s32(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svint32_t, + data: svuint32_t, +) { + svst1_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2f64" + )] + fn _svst1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i64" + )] + fn _svst1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svst1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32" + )] + fn _svst1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32" + )] + fn _svst1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svst1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svst1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svst1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svst1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svst1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svst1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svst1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svst1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svst1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svst1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svst1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svst1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svst1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svst1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svst1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svst1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svst1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svst1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1d))] +pub unsafe fn svst1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svst1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s16(pg: svbool_t, base: *mut i8, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv8i8")] + fn _svst1b_s16(data: nxv8i8, pg: svbool8_t, ptr: *mut i8); + } + _svst1b_s16( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s32(pg: svbool_t, base: *mut i8, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i8")] + fn _svst1b_s32(data: nxv4i8, pg: svbool4_t, ptr: *mut i8); + } + _svst1b_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s32(pg: svbool_t, base: *mut i16, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv4i16")] + fn _svst1h_s32(data: nxv4i16, pg: svbool4_t, ptr: *mut i16); + } + _svst1h_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_s64(pg: svbool_t, base: *mut i8, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i8")] + fn _svst1b_s64(data: nxv2i8, pg: svbool2_t, ptr: *mut i8); + } + _svst1b_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_s64(pg: svbool_t, base: *mut i16, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i16")] + fn _svst1h_s64(data: nxv2i16, pg: svbool2_t, ptr: *mut i16); + } + _svst1h_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_s64(pg: svbool_t, base: *mut i32, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st1.nxv2i32")] + fn _svst1w_s64(data: nxv2i32, pg: svbool2_t, ptr: *mut i32); + } + _svst1w_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u16(pg: svbool_t, base: *mut u8, data: svuint16_t) { + svst1b_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u32(pg: svbool_t, base: *mut u8, data: svuint32_t) { + svst1b_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u32(pg: svbool_t, base: *mut u16, data: svuint32_t) { + svst1h_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_u64(pg: svbool_t, base: *mut u8, data: svuint64_t) { + svst1b_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_u64(pg: svbool_t, base: *mut u16, data: svuint64_t) { + svst1h_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_u64(pg: svbool_t, base: *mut u32, data: svuint64_t) { + svst1w_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8" + )] + fn _svst1b_scatter_s32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16" + )] + fn _svst1h_scatter_s32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_s32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svint32_t, + data: svuint32_t, +) { + svst1b_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i8" + )] + fn _svst1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svst1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i16" + )] + fn _svst1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svst1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.nxv2i32" + )] + fn _svst1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svst1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8" + )] + fn _svst1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svst1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16" + )] + fn _svst1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svst1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svst1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svst1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svst1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svst1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svst1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svst1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svst1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svst1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svst1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svst1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svst1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s16(pg: svbool_t, base: *mut i8, vnum: i64, data: svint16_t) { + svst1b_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s32(pg: svbool_t, base: *mut i8, vnum: i64, data: svint32_t) { + svst1b_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s32(pg: svbool_t, base: *mut i16, vnum: i64, data: svint32_t) { + svst1h_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_s64(pg: svbool_t, base: *mut i8, vnum: i64, data: svint64_t) { + svst1b_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_s64(pg: svbool_t, base: *mut i16, vnum: i64, data: svint64_t) { + svst1h_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_s64(pg: svbool_t, base: *mut i32, vnum: i64, data: svint64_t) { + svst1w_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u16(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint16_t) { + svst1b_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u32(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint32_t) { + svst1b_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u32(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint32_t) { + svst1h_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Truncate to 8 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1b_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1b))] +pub unsafe fn svst1b_vnum_u64(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint64_t) { + svst1b_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_vnum_u64(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint64_t) { + svst1h_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_vnum_u64(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint64_t) { + svst1w_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16" + )] + fn _svst1h_scatter_s32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_s32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svint32_t, + data: svuint32_t, +) { + svst1h_scatter_s32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i16" + )] + fn _svst1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svst1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.index.nxv2i32" + )] + fn _svst1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svst1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_s32( + pg: svbool_t, + base: *mut i16, + indices: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16" + )] + fn _svst1h_scatter_u32index_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + indices: svint32_t, + ); + } + _svst1h_scatter_u32index_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u32]index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32index_u32( + pg: svbool_t, + base: *mut u16, + indices: svuint32_t, + data: svuint32_t, +) { + svst1h_scatter_u32index_s32(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svst1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svst1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svst1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svst1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svst1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svst1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svst1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1h))] +pub unsafe fn svst1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st1w))] +pub unsafe fn svst1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svst1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_f32(pg: svbool_t, base: *mut f32, data: svfloat32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4f32")] + fn _svst2_f32(data0: svfloat32_t, data1: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svst2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_f64(pg: svbool_t, base: *mut f64, data: svfloat64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2f64")] + fn _svst2_f64(data0: svfloat64_t, data1: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svst2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_s8(pg: svbool_t, base: *mut i8, data: svint8x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv16i8")] + fn _svst2_s8(data0: svint8_t, data1: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst2_s8(svget2_s8::<0>(data), svget2_s8::<1>(data), pg, base) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_s16(pg: svbool_t, base: *mut i16, data: svint16x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv8i16")] + fn _svst2_s16(data0: svint16_t, data1: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svst2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_s32(pg: svbool_t, base: *mut i32, data: svint32x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv4i32")] + fn _svst2_s32(data0: svint32_t, data1: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svst2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_s64(pg: svbool_t, base: *mut i64, data: svint64x2_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st2.nxv2i64")] + fn _svst2_s64(data0: svint64_t, data1: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svst2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_u8(pg: svbool_t, base: *mut u8, data: svuint8x2_t) { + svst2_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_u16(pg: svbool_t, base: *mut u16, data: svuint16x2_t) { + svst2_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_u32(pg: svbool_t, base: *mut u32, data: svuint32x2_t) { + svst2_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_u64(pg: svbool_t, base: *mut u64, data: svuint64x2_t) { + svst2_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x2_t) { + svst2_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x2_t) { + svst2_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x2_t) { + svst2_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x2_t) { + svst2_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x2_t) { + svst2_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x2_t) { + svst2_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2b))] +pub unsafe fn svst2_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x2_t) { + svst2_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2h))] +pub unsafe fn svst2_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x2_t) { + svst2_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2w))] +pub unsafe fn svst2_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x2_t) { + svst2_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store two vectors into two-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst2_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st2d))] +pub unsafe fn svst2_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x2_t) { + svst2_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_f32(pg: svbool_t, base: *mut f32, data: svfloat32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4f32")] + fn _svst3_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst3_f32( + svget3_f32::<0>(data), + svget3_f32::<1>(data), + svget3_f32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_f64(pg: svbool_t, base: *mut f64, data: svfloat64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2f64")] + fn _svst3_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst3_f64( + svget3_f64::<0>(data), + svget3_f64::<1>(data), + svget3_f64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_s8(pg: svbool_t, base: *mut i8, data: svint8x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv16i8")] + fn _svst3_s8(data0: svint8_t, data1: svint8_t, data2: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svst3_s8( + svget3_s8::<0>(data), + svget3_s8::<1>(data), + svget3_s8::<2>(data), + pg, + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_s16(pg: svbool_t, base: *mut i16, data: svint16x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv8i16")] + fn _svst3_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst3_s16( + svget3_s16::<0>(data), + svget3_s16::<1>(data), + svget3_s16::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_s32(pg: svbool_t, base: *mut i32, data: svint32x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv4i32")] + fn _svst3_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst3_s32( + svget3_s32::<0>(data), + svget3_s32::<1>(data), + svget3_s32::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_s64(pg: svbool_t, base: *mut i64, data: svint64x3_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st3.nxv2i64")] + fn _svst3_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst3_s64( + svget3_s64::<0>(data), + svget3_s64::<1>(data), + svget3_s64::<2>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_u8(pg: svbool_t, base: *mut u8, data: svuint8x3_t) { + svst3_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_u16(pg: svbool_t, base: *mut u16, data: svuint16x3_t) { + svst3_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_u32(pg: svbool_t, base: *mut u32, data: svuint32x3_t) { + svst3_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_u64(pg: svbool_t, base: *mut u64, data: svuint64x3_t) { + svst3_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x3_t) { + svst3_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x3_t) { + svst3_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x3_t) { + svst3_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x3_t) { + svst3_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x3_t) { + svst3_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x3_t) { + svst3_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3b))] +pub unsafe fn svst3_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x3_t) { + svst3_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3h))] +pub unsafe fn svst3_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x3_t) { + svst3_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3w))] +pub unsafe fn svst3_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x3_t) { + svst3_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store three vectors into three-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst3_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st3d))] +pub unsafe fn svst3_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x3_t) { + svst3_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_f32(pg: svbool_t, base: *mut f32, data: svfloat32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4f32")] + fn _svst4_f32( + data0: svfloat32_t, + data1: svfloat32_t, + data2: svfloat32_t, + data3: svfloat32_t, + pg: svbool4_t, + ptr: *mut f32, + ); + } + _svst4_f32( + svget4_f32::<0>(data), + svget4_f32::<1>(data), + svget4_f32::<2>(data), + svget4_f32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_f64(pg: svbool_t, base: *mut f64, data: svfloat64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2f64")] + fn _svst4_f64( + data0: svfloat64_t, + data1: svfloat64_t, + data2: svfloat64_t, + data3: svfloat64_t, + pg: svbool2_t, + ptr: *mut f64, + ); + } + _svst4_f64( + svget4_f64::<0>(data), + svget4_f64::<1>(data), + svget4_f64::<2>(data), + svget4_f64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_s8(pg: svbool_t, base: *mut i8, data: svint8x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv16i8")] + fn _svst4_s8( + data0: svint8_t, + data1: svint8_t, + data2: svint8_t, + data3: svint8_t, + pg: svbool_t, + ptr: *mut i8, + ); + } + _svst4_s8( + svget4_s8::<0>(data), + svget4_s8::<1>(data), + svget4_s8::<2>(data), + svget4_s8::<3>(data), + pg, + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_s16(pg: svbool_t, base: *mut i16, data: svint16x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv8i16")] + fn _svst4_s16( + data0: svint16_t, + data1: svint16_t, + data2: svint16_t, + data3: svint16_t, + pg: svbool8_t, + ptr: *mut i16, + ); + } + _svst4_s16( + svget4_s16::<0>(data), + svget4_s16::<1>(data), + svget4_s16::<2>(data), + svget4_s16::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_s32(pg: svbool_t, base: *mut i32, data: svint32x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv4i32")] + fn _svst4_s32( + data0: svint32_t, + data1: svint32_t, + data2: svint32_t, + data3: svint32_t, + pg: svbool4_t, + ptr: *mut i32, + ); + } + _svst4_s32( + svget4_s32::<0>(data), + svget4_s32::<1>(data), + svget4_s32::<2>(data), + svget4_s32::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_s64(pg: svbool_t, base: *mut i64, data: svint64x4_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.st4.nxv2i64")] + fn _svst4_s64( + data0: svint64_t, + data1: svint64_t, + data2: svint64_t, + data3: svint64_t, + pg: svbool2_t, + ptr: *mut i64, + ); + } + _svst4_s64( + svget4_s64::<0>(data), + svget4_s64::<1>(data), + svget4_s64::<2>(data), + svget4_s64::<3>(data), + pg.sve_into(), + base, + ) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_u8(pg: svbool_t, base: *mut u8, data: svuint8x4_t) { + svst4_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_u16(pg: svbool_t, base: *mut u16, data: svuint16x4_t) { + svst4_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_u32(pg: svbool_t, base: *mut u32, data: svuint32x4_t) { + svst4_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_u64(pg: svbool_t, base: *mut u64, data: svuint64x4_t) { + svst4_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32x4_t) { + svst4_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64x4_t) { + svst4_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8x4_t) { + svst4_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16x4_t) { + svst4_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32x4_t) { + svst4_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64x4_t) { + svst4_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4b))] +pub unsafe fn svst4_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8x4_t) { + svst4_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4h))] +pub unsafe fn svst4_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16x4_t) { + svst4_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4w))] +pub unsafe fn svst4_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32x4_t) { + svst4_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Store four vectors into four-element tuples"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svst4_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(st4d))] +pub unsafe fn svst4_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64x4_t) { + svst4_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_f32(pg: svbool_t, base: *mut f32, data: svfloat32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4f32")] + fn _svstnt1_f32(data: svfloat32_t, pg: svbool4_t, ptr: *mut f32); + } + _svstnt1_f32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_f64(pg: svbool_t, base: *mut f64, data: svfloat64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2f64")] + fn _svstnt1_f64(data: svfloat64_t, pg: svbool2_t, ptr: *mut f64); + } + _svstnt1_f64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_s8(pg: svbool_t, base: *mut i8, data: svint8_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv16i8")] + fn _svstnt1_s8(data: svint8_t, pg: svbool_t, ptr: *mut i8); + } + _svstnt1_s8(data, pg, base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_s16(pg: svbool_t, base: *mut i16, data: svint16_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv8i16")] + fn _svstnt1_s16(data: svint16_t, pg: svbool8_t, ptr: *mut i16); + } + _svstnt1_s16(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_s32(pg: svbool_t, base: *mut i32, data: svint32_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv4i32")] + fn _svstnt1_s32(data: svint32_t, pg: svbool4_t, ptr: *mut i32); + } + _svstnt1_s32(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_s64(pg: svbool_t, base: *mut i64, data: svint64_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.stnt1.nxv2i64")] + fn _svstnt1_s64(data: svint64_t, pg: svbool2_t, ptr: *mut i64); + } + _svstnt1_s64(data, pg.sve_into(), base) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_u8(pg: svbool_t, base: *mut u8, data: svuint8_t) { + svstnt1_s8(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_u16(pg: svbool_t, base: *mut u16, data: svuint16_t) { + svstnt1_s16(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_u32(pg: svbool_t, base: *mut u32, data: svuint32_t) { + svstnt1_s32(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_u64(pg: svbool_t, base: *mut u64, data: svuint64_t) { + svstnt1_s64(pg, base.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_f32(pg: svbool_t, base: *mut f32, vnum: i64, data: svfloat32_t) { + svstnt1_f32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_f64(pg: svbool_t, base: *mut f64, vnum: i64, data: svfloat64_t) { + svstnt1_f64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_s8(pg: svbool_t, base: *mut i8, vnum: i64, data: svint8_t) { + svstnt1_s8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_s16(pg: svbool_t, base: *mut i16, vnum: i64, data: svint16_t) { + svstnt1_s16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_s32(pg: svbool_t, base: *mut i32, vnum: i64, data: svint32_t) { + svstnt1_s32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_s64(pg: svbool_t, base: *mut i64, vnum: i64, data: svint64_t) { + svstnt1_s64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1_vnum_u8(pg: svbool_t, base: *mut u8, vnum: i64, data: svuint8_t) { + svstnt1_u8(pg, base.offset(svcntb() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1_vnum_u16(pg: svbool_t, base: *mut u16, vnum: i64, data: svuint16_t) { + svstnt1_u16(pg, base.offset(svcnth() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_vnum_u32(pg: svbool_t, base: *mut u32, vnum: i64, data: svuint32_t) { + svstnt1_u32(pg, base.offset(svcntw() as isize * vnum as isize), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_vnum[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_vnum_u64(pg: svbool_t, base: *mut u64, vnum: i64, data: svuint64_t) { + svstnt1_u64(pg, base.offset(svcntd() as isize * vnum as isize), data) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv4f32")] + fn _svsub_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsub_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsub_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsub_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsub.nxv2f64")] + fn _svsub_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsub_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsub_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsub))] +pub fn svsub_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsub_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv16i8")] + fn _svsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsub_s8_m(pg, op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv8i16")] + fn _svsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv4i32")] + fn _svsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sub.nxv2i64")] + fn _svsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsub_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsub_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsub_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsub_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, op1, op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsub[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sub))] +pub fn svsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv4f32")] + fn _svsubr_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svsubr_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_m(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_m(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_x(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_x(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f32_z(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svsubr_f32_m(pg, svsel_f32(pg, op1, svdup_n_f32(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f32_z(pg: svbool_t, op1: svfloat32_t, op2: f32) -> svfloat32_t { + svsubr_f32_z(pg, op1, svdup_n_f32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fsubr.nxv2f64")] + fn _svsubr_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svsubr_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_m(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_m(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_x(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_x(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_f64_z(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svsubr_f64_m(pg, svsel_f64(pg, op1, svdup_n_f64(0.0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fsubr))] +pub fn svsubr_n_f64_z(pg: svbool_t, op1: svfloat64_t, op2: f64) -> svfloat64_t { + svsubr_f64_z(pg, op1, svdup_n_f64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv16i8")] + fn _svsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsubr_s8_m(pg, op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv8i16")] + fn _svsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv4i32")] + fn _svsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subr.nxv2i64")] + fn _svsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svsubr_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svsubr_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svsubr_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svsubr_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, op1, op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subr))] +pub fn svsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sudot, IMM_INDEX = 0))] +pub fn svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svuint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sudot.lane.nxv4i32" + )] + fn _svsudot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svsudot_lane_s32(op1, op2, op3.as_signed(), IMM_INDEX) } +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_s32(op1: svint32_t, op2: svint8_t, op3: svuint8_t) -> svint32_t { + svusdot_s32(op1, op3, op2) +} +#[doc = "Dot product (signed × unsigned)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsudot[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svsudot_n_s32(op1: svint32_t, op2: svint8_t, op3: u8) -> svint32_t { + svsudot_s32(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f32(data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4f32")] + fn _svtbl_f32(data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbl_f32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_f64(data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2f64")] + fn _svtbl_f64(data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbl_f64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s8(data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv16i8")] + fn _svtbl_s8(data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbl_s8(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s16(data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv8i16")] + fn _svtbl_s16(data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbl_s16(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s32(data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv4i32")] + fn _svtbl_s32(data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbl_s32(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_s64(data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl.nxv2i64")] + fn _svtbl_s64(data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbl_s64(data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u8(data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u16(data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u32(data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl_u64(data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv4f32" + )] + fn _svtmad_f32(op1: svfloat32_t, op2: svfloat32_t, imm3: i32) -> svfloat32_t; + } + unsafe { _svtmad_f32(op1, op2, IMM3) } +} +#[doc = "Trigonometric multiply-add coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtmad[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftmad, IMM3 = 0))] +pub fn svtmad_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftmad.x.nxv2f64" + )] + fn _svtmad_f64(op1: svfloat64_t, op2: svfloat64_t, imm3: i32) -> svfloat64_t; + } + unsafe { _svtmad_f64(op1, op2, IMM3) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")] + fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn1_b8(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i1")] + fn _svtrn1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i1")] + fn _svtrn1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i1")] + fn _svtrn1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4f32")] + fn _svtrn1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1_f32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2f64")] + fn _svtrn1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1_f64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i8")] + fn _svtrn1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1_s8(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i16")] + fn _svtrn1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1_s16(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i32")] + fn _svtrn1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1_s32(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i64")] + fn _svtrn1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1_s64(op1, op2) } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4f32")] + fn _svtrn1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn1q_f32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2f64")] + fn _svtrn1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn1q_f64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv16i8")] + fn _svtrn1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn1q_s8(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv8i16")] + fn _svtrn1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn1q_s16(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv4i32")] + fn _svtrn1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn1q_s32(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1q.nxv2i64")] + fn _svtrn1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn1q_s64(op1, op2) } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn1))] +pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")] + fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svtrn2_b8(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i1")] + fn _svtrn2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i1")] + fn _svtrn2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i1")] + fn _svtrn2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4f32")] + fn _svtrn2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2_f32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2f64")] + fn _svtrn2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2_f64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i8")] + fn _svtrn2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2_s8(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i16")] + fn _svtrn2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2_s16(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i32")] + fn _svtrn2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2_s32(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i64")] + fn _svtrn2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2_s64(op1, op2) } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4f32")] + fn _svtrn2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svtrn2q_f32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2f64")] + fn _svtrn2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svtrn2q_f64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv16i8")] + fn _svtrn2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svtrn2q_s8(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv8i16")] + fn _svtrn2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svtrn2q_s16(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv4i32")] + fn _svtrn2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svtrn2q_s32(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2q.nxv2i64")] + fn _svtrn2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svtrn2q_s64(op1, op2) } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svtrn2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svtrn2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svtrn2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(trn2))] +pub fn svtrn2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svtrn2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv4f32" + )] + fn _svtsmul_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtsmul_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric starting value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtsmul[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftsmul))] +pub fn svtsmul_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftsmul.x.nxv2f64" + )] + fn _svtsmul_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtsmul_f64(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f32(op1: svfloat32_t, op2: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv4f32" + )] + fn _svtssel_f32(op1: svfloat32_t, op2: svint32_t) -> svfloat32_t; + } + unsafe { _svtssel_f32(op1, op2.as_signed()) } +} +#[doc = "Trigonometric select coefficient"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtssel[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ftssel))] +pub fn svtssel_f64(op1: svfloat64_t, op2: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ftssel.x.nxv2f64" + )] + fn _svtssel_f64(op1: svfloat64_t, op2: svint64_t) -> svfloat64_t; + } + unsafe { _svtssel_f64(op1, op2.as_signed()) } +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f32() -> svfloat32x2_t { + svcreate2_f32(svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_f64() -> svfloat64x2_t { + svcreate2_f64(svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s8() -> svint8x2_t { + svcreate2_s8(svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s16() -> svint16x2_t { + svcreate2_s16(svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s32() -> svint32x2_t { + svcreate2_s32(svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_s64() -> svint64x2_t { + svcreate2_s64(svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u8() -> svuint8x2_t { + svcreate2_u8(svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u16() -> svuint16x2_t { + svcreate2_u16(svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u32() -> svuint32x2_t { + svcreate2_u32(svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of two vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef2_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef2_u64() -> svuint64x2_t { + svcreate2_u64(svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f32() -> svfloat32x3_t { + svcreate3_f32(svdup_n_f32(0f32), svdup_n_f32(0f32), svdup_n_f32(0f32)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_f64() -> svfloat64x3_t { + svcreate3_f64(svdup_n_f64(0f64), svdup_n_f64(0f64), svdup_n_f64(0f64)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s8() -> svint8x3_t { + svcreate3_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s16() -> svint16x3_t { + svcreate3_s16(svdup_n_s16(0), svdup_n_s16(0), svdup_n_s16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s32() -> svint32x3_t { + svcreate3_s32(svdup_n_s32(0), svdup_n_s32(0), svdup_n_s32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_s64() -> svint64x3_t { + svcreate3_s64(svdup_n_s64(0), svdup_n_s64(0), svdup_n_s64(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u8() -> svuint8x3_t { + svcreate3_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u16() -> svuint16x3_t { + svcreate3_u16(svdup_n_u16(0), svdup_n_u16(0), svdup_n_u16(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u32() -> svuint32x3_t { + svcreate3_u32(svdup_n_u32(0), svdup_n_u32(0), svdup_n_u32(0)) +} +#[doc = "Create an uninitialized tuple of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef3_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef3_u64() -> svuint64x3_t { + svcreate3_u64(svdup_n_u64(0), svdup_n_u64(0), svdup_n_u64(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f32() -> svfloat32x4_t { + svcreate4_f32( + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + svdup_n_f32(0f32), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_f64() -> svfloat64x4_t { + svcreate4_f64( + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + svdup_n_f64(0f64), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s8() -> svint8x4_t { + svcreate4_s8(svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0), svdup_n_s8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s16() -> svint16x4_t { + svcreate4_s16( + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + svdup_n_s16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s32() -> svint32x4_t { + svcreate4_s32( + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + svdup_n_s32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_s64() -> svint64x4_t { + svcreate4_s64( + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + svdup_n_s64(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u8() -> svuint8x4_t { + svcreate4_u8(svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0), svdup_n_u8(0)) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u16() -> svuint16x4_t { + svcreate4_u16( + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + svdup_n_u16(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u32() -> svuint32x4_t { + svcreate4_u32( + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + svdup_n_u32(0), + ) +} +#[doc = "Create an uninitialized tuple of four vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef4_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef4_u64() -> svuint64x4_t { + svcreate4_u64( + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + svdup_n_u64(0), + ) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f32() -> svfloat32_t { + svdup_n_f32(0f32) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_f64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_f64() -> svfloat64_t { + svdup_n_f64(0f64) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s8() -> svint8_t { + svdup_n_s8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s16() -> svint16_t { + svdup_n_s16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s32() -> svint32_t { + svdup_n_s32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_s64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_s64() -> svint64_t { + svdup_n_s64(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u8)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u8() -> svuint8_t { + svdup_n_u8(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u16)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u16() -> svuint16_t { + svdup_n_u16(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u32)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u32() -> svuint32_t { + svdup_n_u32(0) +} +#[doc = "Create an uninitialized vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svundef_u64)"] +#[doc = "## Safety"] +#[doc = " * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`])."] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub unsafe fn svundef_u64() -> svuint64_t { + svdup_n_u64(0) +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot, IMM_INDEX = 0))] +pub fn svusdot_lane_s32( + op1: svint32_t, + op2: svuint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.usdot.lane.nxv4i32" + )] + fn _svusdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + ) -> svint32_t; + } + unsafe { _svusdot_lane_s32(op1, op2.as_signed(), op3, IMM_INDEX) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usdot.nxv4i32")] + fn _svusdot_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusdot_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Dot product (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusdot[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usdot))] +pub fn svusdot_n_s32(op1: svint32_t, op2: svuint8_t, op3: i8) -> svint32_t { + svusdot_s32(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Matrix multiply-accumulate (unsigned × signed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svusmmla[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,i8mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usmmla))] +pub fn svusmmla_s32(op1: svint32_t, op2: svuint8_t, op3: svint8_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usmmla.nxv4i32")] + fn _svusmmla_s32(op1: svint32_t, op2: svint8_t, op3: svint8_t) -> svint32_t; + } + unsafe { _svusmmla_s32(op1, op2.as_signed(), op3) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i1")] + fn _svuzp1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp1_b8(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i1")] + fn _svuzp1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svuzp1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i1")] + fn _svuzp1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svuzp1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i1")] + fn _svuzp1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svuzp1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4f32")] + fn _svuzp1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1_f32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2f64")] + fn _svuzp1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1_f64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv16i8")] + fn _svuzp1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1_s8(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv8i16")] + fn _svuzp1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1_s16(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv4i32")] + fn _svuzp1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1_s32(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1.nxv2i64")] + fn _svuzp1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1_s64(op1, op2) } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4f32")] + fn _svuzp1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp1q_f32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2f64")] + fn _svuzp1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp1q_f64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv16i8")] + fn _svuzp1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp1q_s8(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv8i16")] + fn _svuzp1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp1q_s16(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv4i32")] + fn _svuzp1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp1q_s32(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp1q.nxv2i64")] + fn _svuzp1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp1q_s64(op1, op2) } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate even quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp1q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp1))] +pub fn svuzp1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i1")] + fn _svuzp2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svuzp2_b8(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i1")] + fn _svuzp2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svuzp2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i1")] + fn _svuzp2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svuzp2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i1")] + fn _svuzp2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svuzp2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4f32")] + fn _svuzp2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2_f32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2f64")] + fn _svuzp2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2_f64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv16i8")] + fn _svuzp2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2_s8(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv8i16")] + fn _svuzp2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2_s16(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv4i32")] + fn _svuzp2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2_s32(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2.nxv2i64")] + fn _svuzp2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2_s64(op1, op2) } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd elements from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4f32")] + fn _svuzp2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svuzp2q_f32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2f64")] + fn _svuzp2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svuzp2q_f64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv16i8")] + fn _svuzp2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuzp2q_s8(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv8i16")] + fn _svuzp2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuzp2q_s16(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv4i32")] + fn _svuzp2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuzp2q_s32(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uzp2q.nxv2i64")] + fn _svuzp2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuzp2q_s64(op1, op2) } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svuzp2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svuzp2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svuzp2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Concatenate odd quadwords from two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuzp2q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uzp2))] +pub fn svuzp2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svuzp2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i32" + )] + fn _svwhilele_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i32" + )] + fn _svwhilele_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i32" + )] + fn _svwhilele_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i32" + )] + fn _svwhilele_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv16i1.i64" + )] + fn _svwhilele_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv8i1.i64" + )] + fn _svwhilele_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv4i1.i64" + )] + fn _svwhilele_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilele))] +pub fn svwhilele_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilele.nxv2i1.i64" + )] + fn _svwhilele_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i32" + )] + fn _svwhilele_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilele_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i32" + )] + fn _svwhilele_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilele_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i32" + )] + fn _svwhilele_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilele_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i32" + )] + fn _svwhilele_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilele_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv16i1.i64" + )] + fn _svwhilele_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilele_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv8i1.i64" + )] + fn _svwhilele_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilele_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv4i1.i64" + )] + fn _svwhilele_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilele_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilele_b64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilels))] +pub fn svwhilele_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilels.nxv2i1.i64" + )] + fn _svwhilele_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilele_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i32" + )] + fn _svwhilelt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_s32(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i32" + )] + fn _svwhilelt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i32" + )] + fn _svwhilelt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i32" + )] + fn _svwhilelt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv16i1.i64" + )] + fn _svwhilelt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_s64(op1, op2) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv8i1.i64" + )] + fn _svwhilelt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv4i1.i64" + )] + fn _svwhilelt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelt))] +pub fn svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelt.nxv2i1.i64" + )] + fn _svwhilelt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i32" + )] + fn _svwhilelt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilelt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i32" + )] + fn _svwhilelt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i32" + )] + fn _svwhilelt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i32" + )] + fn _svwhilelt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv16i1.i64" + )] + fn _svwhilelt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilelt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv8i1.i64" + )] + fn _svwhilelt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilelt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv4i1.i64" + )] + fn _svwhilelt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilelt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While incrementing scalar is less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilelt_b64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilelo))] +pub fn svwhilelt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilelo.nxv2i1.i64" + )] + fn _svwhilelt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilelt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "Write to the first-fault register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwrffr)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(wrffr))] +pub fn svwrffr(op: svbool_t) { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.wrffr")] + fn _svwrffr(op: svbool_t); + } + unsafe { _svwrffr(op) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i1")] + fn _svzip1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip1_b8(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i1")] + fn _svzip1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svzip1_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i1")] + fn _svzip1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svzip1_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i1")] + fn _svzip1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svzip1_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4f32")] + fn _svzip1_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1_f32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2f64")] + fn _svzip1_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1_f64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv16i8")] + fn _svzip1_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1_s8(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv8i16")] + fn _svzip1_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1_s16(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv4i32")] + fn _svzip1_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1_s32(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1.nxv2i64")] + fn _svzip1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1_s64(op1, op2) } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4f32")] + fn _svzip1q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip1q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2f64")] + fn _svzip1q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip1q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv16i8")] + fn _svzip1q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip1q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv8i16")] + fn _svzip1q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip1q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv4i32")] + fn _svzip1q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip1q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip1q.nxv2i64")] + fn _svzip1q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip1q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip1q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip1q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip1q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from low halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip1q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip1))] +pub fn svzip1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b8)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i1")] + fn _svzip2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t; + } + unsafe { _svzip2_b8(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b16)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i1")] + fn _svzip2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t; + } + unsafe { _svzip2_b16(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b32)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i1")] + fn _svzip2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t; + } + unsafe { _svzip2_b32(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2_b64)"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i1")] + fn _svzip2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t; + } + unsafe { _svzip2_b64(op1.sve_into(), op2.sve_into()).sve_into() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4f32")] + fn _svzip2_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2_f32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2f64")] + fn _svzip2_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2_f64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv16i8")] + fn _svzip2_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2_s8(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv8i16")] + fn _svzip2_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2_s16(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv4i32")] + fn _svzip2_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2_s32(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2.nxv2i64")] + fn _svzip2_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2_s64(op1, op2) } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave elements from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4f32")] + fn _svzip2q_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svzip2q_f32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2f64")] + fn _svzip2q_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svzip2q_f64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv16i8")] + fn _svzip2q_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svzip2q_s8(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv8i16")] + fn _svzip2q_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svzip2q_s16(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv4i32")] + fn _svzip2q_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svzip2q_s32(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.zip2q.nxv2i64")] + fn _svzip2q_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svzip2q_s64(op1, op2) } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svzip2q_s8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svzip2q_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svzip2q_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleave quadwords from high halves of two inputs"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svzip2q[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,f64mm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(zip2))] +pub fn svzip2q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svzip2q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs new file mode 100644 index 000000000000..973b7e9fa35a --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/ld_st_tests_aarch64.rs @@ -0,0 +1,9345 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f32_with_svst1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_f64_with_svst1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svst1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s8_with_svst1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s16_with_svst1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s32_with_svst1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_s64_with_svst1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u8_with_svst1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u16_with_svst1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u32_with_svst1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_u64_with_svst1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_f32_with_svst1_scatter_s32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_s32_with_svst1_scatter_s32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32index_u32_with_svst1_scatter_s32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1_scatter_s32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_f64_with_svst1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_s64_with_svst1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64index_u64_with_svst1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_f32_with_svst1_scatter_u32index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_f32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32index_f32(svptrue_b32(), storage.as_ptr() as *const f32, indices); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_s32_with_svst1_scatter_u32index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_s32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32index_s32(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32index_u32_with_svst1_scatter_u32index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1_scatter_u32index_u32(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32index_u32(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_f64_with_svst1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_s64_with_svst1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64index_u64_with_svst1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_f32_with_svst1_scatter_s32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_s32_with_svst1_scatter_s32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s32offset_u32_with_svst1_scatter_s32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svst1_scatter_s32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_s32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_f64_with_svst1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_s64_with_svst1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_s64offset_u64_with_svst1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svst1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_f32_with_svst1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_s32_with_svst1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32offset_u32_with_svst1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_f64_with_svst1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_s64_with_svst1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64offset_u64_with_svst1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svst1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_f64_with_svst1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_f64(svptrue_b64(), bases); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_s64_with_svst1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_s64(svptrue_b64(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_u64_with_svst1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_u64(svptrue_b64(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_f32_with_svst1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_s32_with_svst1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_index_u32_with_svst1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_f64_with_svst1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_s64_with_svst1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_index_u64_with_svst1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_f32_with_svst1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_s32_with_svst1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u32base_offset_u32_with_svst1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svst1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_f64_with_svst1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_s64_with_svst1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_gather_u64base_offset_u64_with_svst1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svst1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f32_with_svst1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_f64_with_svst1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svst1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s8_with_svst1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s16_with_svst1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s32_with_svst1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_s64_with_svst1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u8_with_svst1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u16_with_svst1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u32_with_svst1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1_vnum_u64_with_svst1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svtrn1q_f32( + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + svdupq_n_f32(4usize as f32, 5usize as f32, 6usize as f32, 7usize as f32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_f64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_f64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svtrn1q_f64( + svdupq_n_f64(0usize as f64, 1usize as f64), + svdupq_n_f64(2usize as f64, 3usize as f64), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s8 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svtrn1q_s8( + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + svdupq_n_s8( + 16usize as i8, + 17usize as i8, + 18usize as i8, + 19usize as i8, + 20usize as i8, + 21usize as i8, + 22usize as i8, + 23usize as i8, + 24usize as i8, + 25usize as i8, + 26usize as i8, + 27usize as i8, + 28usize as i8, + 29usize as i8, + 30usize as i8, + 31usize as i8, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s16 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svtrn1q_s16( + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + svdupq_n_s16( + 8usize as i16, + 9usize as i16, + 10usize as i16, + 11usize as i16, + 12usize as i16, + 13usize as i16, + 14usize as i16, + 15usize as i16, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svtrn1q_s32( + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + svdupq_n_s32(4usize as i32, 5usize as i32, 6usize as i32, 7usize as i32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_s64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_s64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svtrn1q_s64( + svdupq_n_s64(0usize as i64, 1usize as i64), + svdupq_n_s64(2usize as i64, 3usize as i64), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u8() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u8 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svtrn1q_u8( + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + svdupq_n_u8( + 16usize as u8, + 17usize as u8, + 18usize as u8, + 19usize as u8, + 20usize as u8, + 21usize as u8, + 22usize as u8, + 23usize as u8, + 24usize as u8, + 25usize as u8, + 26usize as u8, + 27usize as u8, + 28usize as u8, + 29usize as u8, + 30usize as u8, + 31usize as u8, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u16() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u16 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svtrn1q_u16( + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + svdupq_n_u16( + 8usize as u16, + 9usize as u16, + 10usize as u16, + 11usize as u16, + 12usize as u16, + 13usize as u16, + 14usize as u16, + 15usize as u16, + ), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u32() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u32 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svtrn1q_u32( + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + svdupq_n_u32(4usize as u32, 5usize as u32, 6usize as u32, 7usize as u32), + ), + ); +} +#[simd_test(enable = "sve,f64mm")] +unsafe fn test_svld1ro_u64() { + if svcntb() < 32 { + println!("Skipping test_svld1ro_u64 due to SVE vector length"); + return; + } + svsetffr(); + let loaded = svld1ro_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svtrn1q_u64( + svdupq_n_u64(0usize as u64, 1usize as u64), + svdupq_n_u64(2usize as u64, 3usize as u64), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f32() { + svsetffr(); + let loaded = svld1rq_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_f64() { + svsetffr(); + let loaded = svld1rq_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64(loaded, svdupq_n_f64(0usize as f64, 1usize as f64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s8() { + svsetffr(); + let loaded = svld1rq_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svdupq_n_s8( + 0usize as i8, + 1usize as i8, + 2usize as i8, + 3usize as i8, + 4usize as i8, + 5usize as i8, + 6usize as i8, + 7usize as i8, + 8usize as i8, + 9usize as i8, + 10usize as i8, + 11usize as i8, + 12usize as i8, + 13usize as i8, + 14usize as i8, + 15usize as i8, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s16() { + svsetffr(); + let loaded = svld1rq_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svdupq_n_s16( + 0usize as i16, + 1usize as i16, + 2usize as i16, + 3usize as i16, + 4usize as i16, + 5usize as i16, + 6usize as i16, + 7usize as i16, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s32() { + svsetffr(); + let loaded = svld1rq_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_s64() { + svsetffr(); + let loaded = svld1rq_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64(loaded, svdupq_n_s64(0usize as i64, 1usize as i64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u8() { + svsetffr(); + let loaded = svld1rq_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svdupq_n_u8( + 0usize as u8, + 1usize as u8, + 2usize as u8, + 3usize as u8, + 4usize as u8, + 5usize as u8, + 6usize as u8, + 7usize as u8, + 8usize as u8, + 9usize as u8, + 10usize as u8, + 11usize as u8, + 12usize as u8, + 13usize as u8, + 14usize as u8, + 15usize as u8, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u16() { + svsetffr(); + let loaded = svld1rq_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svdupq_n_u16( + 0usize as u16, + 1usize as u16, + 2usize as u16, + 3usize as u16, + 4usize as u16, + 5usize as u16, + 6usize as u16, + 7usize as u16, + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u32() { + svsetffr(); + let loaded = svld1rq_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1rq_u64() { + svsetffr(); + let loaded = svld1rq_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64(loaded, svdupq_n_u64(0usize as u64, 1usize as u64)); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s16(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s32(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s32(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_s64(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_s64(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_s64(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u16(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u32(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u32(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_u64(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_u64(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_u64(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1sb_vnum_s64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u16(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u32(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sb_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1sb_vnum_u64(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1sh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1sw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1sw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 1u32.try_into().unwrap()); + svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s32(0, 2u32.try_into().unwrap()); + svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svst1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_s64_with_svst1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_offset_u64_with_svst1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_offset_u64_with_svst1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_offset_u64_with_svst1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_s64_with_svst1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_s64_with_svst1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_s64_with_svst1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_gather_u64base_u64_with_svst1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svst1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_u64_with_svst1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_u64_with_svst1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s16_with_svst1b_s16() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s16(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s32_with_svst1b_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s32(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s32_with_svst1h_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s32(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_s64_with_svst1b_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_s64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_s64(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_s64_with_svst1h_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_s64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_s64(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_s64_with_svst1w_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_s64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_s64(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u16_with_svst1b_u16() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u16(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u16(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u32_with_svst1b_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u32(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u32(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u32_with_svst1h_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u32(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u32(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_u64_with_svst1b_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1b_u64(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_u64(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_u64_with_svst1h_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1h_u64(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_u64(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_u64_with_svst1w_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svst1w_u64(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_u64(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s16_with_svst1b_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s32_with_svst1b_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s32_with_svst1h_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_s64_with_svst1b_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_s64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld1ub_vnum_s64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_s64_with_svst1h_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_s64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_vnum_s64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_s64_with_svst1w_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_s64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_vnum_s64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u16_with_svst1b_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u16(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u16(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u32_with_svst1b_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u32(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u32(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u32_with_svst1h_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u32(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u32(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1ub_vnum_u64_with_svst1b_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1b_vnum_u64(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld1ub_vnum_u64(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_vnum_u64_with_svst1h_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1h_vnum_u64(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld1uh_vnum_u64(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_vnum_u64_with_svst1w_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svst1w_vnum_u64(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld1uw_vnum_u64(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_s32_with_svst1h_scatter_s32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s32index_u32_with_svst1h_scatter_s32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s32(0, 1); + svst1h_scatter_s32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_s64_with_svst1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_s64_with_svst1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_s64index_u64_with_svst1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_s64index_u64_with_svst1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svst1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_s32_with_svst1h_scatter_u32index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_s32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_s32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32index_u32_with_svst1h_scatter_u32index_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u32(0, 1); + svst1h_scatter_u32index_u32(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u32index_u32(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_s64_with_svst1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_s64_with_svst1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64index_u64_with_svst1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svld1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64index_u64_with_svst1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svst1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svld1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_s32_with_svst1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u32base_index_u32_with_svst1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svst1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_s64_with_svst1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_s64_with_svst1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uh_gather_u64base_index_u64_with_svst1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svst1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld1uw_gather_u64base_index_u64_with_svst1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svst1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f32_with_svst2_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_f64_with_svst2_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + svst2_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s8_with_svst2_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s16_with_svst2_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s32_with_svst2_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_s64_with_svst2_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u8_with_svst2_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u16_with_svst2_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u32_with_svst2_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_u64_with_svst2_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + svst2_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 2usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f32_with_svst2_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate2_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld2_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget2_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget2_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_f64_with_svst2_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate2_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + svst2_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld2_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget2_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget2_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s8_with_svst2_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate2_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld2_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget2_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget2_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s16_with_svst2_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate2_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld2_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget2_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget2_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s32_with_svst2_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate2_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld2_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget2_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget2_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_s64_with_svst2_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate2_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld2_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget2_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget2_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u8_with_svst2_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate2_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld2_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget2_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget2_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u16_with_svst2_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate2_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld2_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget2_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget2_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u32_with_svst2_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate2_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld2_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget2_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget2_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld2_vnum_u64_with_svst2_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate2_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + svst2_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld2_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget2_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget2_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 2usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f32_with_svst3_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_f64_with_svst3_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + svst3_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s8_with_svst3_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s16_with_svst3_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s32_with_svst3_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_s64_with_svst3_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u8_with_svst3_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u16_with_svst3_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u32_with_svst3_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_u64_with_svst3_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + svst3_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 3usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f32_with_svst3_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate3_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld3_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget3_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget3_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_f64_with_svst3_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate3_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + svst3_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld3_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget3_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget3_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s8_with_svst3_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate3_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld3_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget3_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget3_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget3_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s16_with_svst3_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate3_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld3_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget3_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget3_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget3_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s32_with_svst3_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate3_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld3_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget3_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget3_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget3_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_s64_with_svst3_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate3_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld3_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget3_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget3_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget3_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u8_with_svst3_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate3_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld3_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget3_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget3_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget3_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u16_with_svst3_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate3_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld3_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget3_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget3_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget3_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u32_with_svst3_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate3_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld3_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget3_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget3_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget3_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld3_vnum_u64_with_svst3_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate3_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + svst3_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld3_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget3_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget3_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget3_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 3usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f32_with_svst4_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_f64_with_svst4_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + svst4_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s8_with_svst4_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s16_with_svst4_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s32_with_svst4_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_s64_with_svst4_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u8_with_svst4_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u16_with_svst4_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u32_with_svst4_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_u64_with_svst4_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + svst4_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64((0usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64((1usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64((2usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64((3usize).try_into().unwrap(), 4usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f32_with_svst4_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcreate4_f32( + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svld4_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + svget4_f32::<{ 0usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 1usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 2usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f32( + svget4_f32::<{ 3usize as i32 }>(loaded), + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_f64_with_svst4_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcreate4_f64( + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + svst4_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svld4_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + svget4_f64::<{ 0usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 1usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 2usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); + assert_vector_matches_f64( + svget4_f64::<{ 3usize as i32 }>(loaded), + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s8_with_svst4_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svcreate4_s8( + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svld4_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + svget4_s8::<{ 0usize as i32 }>(loaded), + svindex_s8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 1usize as i32 }>(loaded), + svindex_s8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 2usize as i32 }>(loaded), + svindex_s8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i8( + svget4_s8::<{ 3usize as i32 }>(loaded), + svindex_s8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s16_with_svst4_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svcreate4_s16( + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svld4_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + svget4_s16::<{ 0usize as i32 }>(loaded), + svindex_s16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 1usize as i32 }>(loaded), + svindex_s16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 2usize as i32 }>(loaded), + svindex_s16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i16( + svget4_s16::<{ 3usize as i32 }>(loaded), + svindex_s16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s32_with_svst4_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svcreate4_s32( + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svld4_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + svget4_s32::<{ 0usize as i32 }>(loaded), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 1usize as i32 }>(loaded), + svindex_s32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 2usize as i32 }>(loaded), + svindex_s32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i32( + svget4_s32::<{ 3usize as i32 }>(loaded), + svindex_s32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_s64_with_svst4_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svcreate4_s64( + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svld4_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + svget4_s64::<{ 0usize as i32 }>(loaded), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 1usize as i32 }>(loaded), + svindex_s64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 2usize as i32 }>(loaded), + svindex_s64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_i64( + svget4_s64::<{ 3usize as i32 }>(loaded), + svindex_s64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u8_with_svst4_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svcreate4_u8( + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svld4_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + svget4_u8::<{ 0usize as i32 }>(loaded), + svindex_u8( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 1usize as i32 }>(loaded), + svindex_u8( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 2usize as i32 }>(loaded), + svindex_u8( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u8( + svget4_u8::<{ 3usize as i32 }>(loaded), + svindex_u8( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u16_with_svst4_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svcreate4_u16( + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svld4_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + svget4_u16::<{ 0usize as i32 }>(loaded), + svindex_u16( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 1usize as i32 }>(loaded), + svindex_u16( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 2usize as i32 }>(loaded), + svindex_u16( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u16( + svget4_u16::<{ 3usize as i32 }>(loaded), + svindex_u16( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u32_with_svst4_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svcreate4_u32( + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svld4_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + svget4_u32::<{ 0usize as i32 }>(loaded), + svindex_u32( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 1usize as i32 }>(loaded), + svindex_u32( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 2usize as i32 }>(loaded), + svindex_u32( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u32( + svget4_u32::<{ 3usize as i32 }>(loaded), + svindex_u32( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svld4_vnum_u64_with_svst4_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svcreate4_u64( + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + svst4_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svld4_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + svget4_u64::<{ 0usize as i32 }>(loaded), + svindex_u64( + (len + 0usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 1usize as i32 }>(loaded), + svindex_u64( + (len + 1usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 2usize as i32 }>(loaded), + svindex_u64( + (len + 2usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); + assert_vector_matches_u64( + svget4_u64::<{ 3usize as i32 }>(loaded), + svindex_u64( + (len + 3usize).try_into().unwrap(), + 4usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f32() { + svsetffr(); + let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr()); + let loaded = svldff1_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_f64() { + svsetffr(); + let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr()); + let loaded = svldff1_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s8() { + svsetffr(); + let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s16() { + svsetffr(); + let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s32() { + svsetffr(); + let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_s64() { + svsetffr(); + let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr()); + let loaded = svldff1_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u8() { + svsetffr(); + let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u16() { + svsetffr(); + let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u32() { + svsetffr(); + let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_u64() { + svsetffr(); + let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr()); + let loaded = svldff1_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f32() { + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_f64() { + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s8() { + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s16() { + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s32() { + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_s64() { + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u8() { + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u16() { + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u32() { + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1_vnum_u64() { + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let loaded = svldff1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s16() { + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s32() { + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s32() { + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_s64() { + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_s64() { + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_s64() { + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u16() { + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u32() { + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u32() { + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_u64() { + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldff1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_u64() { + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldff1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_u64() { + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldff1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s16() { + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s32() { + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s32() { + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_s64() { + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_s64() { + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_s64() { + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u16() { + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u32() { + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u32() { + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sb_vnum_u64() { + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldff1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sh_vnum_u64() { + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldff1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1sw_vnum_u64() { + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldff1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s16() { + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s32() { + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s32() { + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_s64() { + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_s64() { + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_s64() { + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u16() { + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u32() { + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u32() { + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_u64() { + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldff1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_u64() { + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldff1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_u64() { + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldff1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s16() { + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s32() { + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s32() { + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_s64() { + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_s64() { + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_s64() { + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u16() { + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u32() { + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u32() { + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1ub_vnum_u64() { + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldff1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uh_vnum_u64() { + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldff1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldff1uw_vnum_u64() { + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldff1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f32() { + svsetffr(); + let _ = svld1_f32(svptrue_b32(), F32_DATA.as_ptr()); + let loaded = svldnf1_f32(svptrue_b32(), F32_DATA.as_ptr()); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_f64() { + svsetffr(); + let _ = svld1_f64(svptrue_b64(), F64_DATA.as_ptr()); + let loaded = svldnf1_f64(svptrue_b64(), F64_DATA.as_ptr()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s8() { + svsetffr(); + let _ = svld1_s8(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1_s8(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s16() { + svsetffr(); + let _ = svld1_s16(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1_s16(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s32() { + svsetffr(); + let _ = svld1_s32(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1_s32(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_s64() { + svsetffr(); + let _ = svld1_s64(svptrue_b64(), I64_DATA.as_ptr()); + let loaded = svldnf1_s64(svptrue_b64(), I64_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u8() { + svsetffr(); + let _ = svld1_u8(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1_u8(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u16() { + svsetffr(); + let _ = svld1_u16(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1_u16(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u32() { + svsetffr(); + let _ = svld1_u32(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1_u32(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_u64() { + svsetffr(); + let _ = svld1_u64(svptrue_b64(), U64_DATA.as_ptr()); + let loaded = svldnf1_u64(svptrue_b64(), U64_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f32() { + svsetffr(); + let _ = svld1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_f32(svptrue_b32(), F32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_f64() { + svsetffr(); + let _ = svld1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_f64(svptrue_b64(), F64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s8() { + svsetffr(); + let _ = svld1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s8(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s16() { + svsetffr(); + let _ = svld1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s16(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s32() { + svsetffr(); + let _ = svld1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s32(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_s64() { + svsetffr(); + let _ = svld1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_s64(svptrue_b64(), I64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u8() { + svsetffr(); + let _ = svld1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u8(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntb() as usize; + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u16() { + svsetffr(); + let _ = svld1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u16(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u32() { + svsetffr(); + let _ = svld1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u32(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1_vnum_u64() { + svsetffr(); + let _ = svld1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let loaded = svldnf1_vnum_u64(svptrue_b64(), U64_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s16() { + svsetffr(); + let _ = svld1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s32() { + svsetffr(); + let _ = svld1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s32() { + svsetffr(); + let _ = svld1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_s32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_s64() { + svsetffr(); + let _ = svld1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_s64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_s64() { + svsetffr(); + let _ = svld1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_s64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_s64() { + svsetffr(); + let _ = svld1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1sw_s64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u16() { + svsetffr(); + let _ = svld1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u16(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u32() { + svsetffr(); + let _ = svld1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u32(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u32() { + svsetffr(); + let _ = svld1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_u32(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_u64() { + svsetffr(); + let _ = svld1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + let loaded = svldnf1sb_u64(svptrue_b8(), I8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_u64() { + svsetffr(); + let _ = svld1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + let loaded = svldnf1sh_u64(svptrue_b16(), I16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_u64() { + svsetffr(); + let _ = svld1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + let loaded = svldnf1sw_u64(svptrue_b32(), I32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s16() { + svsetffr(); + let _ = svld1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s32() { + svsetffr(); + let _ = svld1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s32() { + svsetffr(); + let _ = svld1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_s32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_s64() { + svsetffr(); + let _ = svld1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_s64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_s64() { + svsetffr(); + let _ = svld1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_s64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_s64() { + svsetffr(); + let _ = svld1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1sw_vnum_s64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u16() { + svsetffr(); + let _ = svld1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u16(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u32() { + svsetffr(); + let _ = svld1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u32(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u32() { + svsetffr(); + let _ = svld1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_u32(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sb_vnum_u64() { + svsetffr(); + let _ = svld1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let loaded = svldnf1sb_vnum_u64(svptrue_b8(), I8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sh_vnum_u64() { + svsetffr(); + let _ = svld1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let loaded = svldnf1sh_vnum_u64(svptrue_b16(), I16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1sw_vnum_u64() { + svsetffr(); + let _ = svld1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let loaded = svldnf1sw_vnum_u64(svptrue_b32(), I32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s16() { + svsetffr(); + let _ = svld1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s32() { + svsetffr(); + let _ = svld1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s32() { + svsetffr(); + let _ = svld1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_s32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_s64() { + svsetffr(); + let _ = svld1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_s64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_s64() { + svsetffr(); + let _ = svld1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_s64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_s64() { + svsetffr(); + let _ = svld1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1uw_s64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u16() { + svsetffr(); + let _ = svld1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u16(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u32() { + svsetffr(); + let _ = svld1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u32(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u32() { + svsetffr(); + let _ = svld1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_u32(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_u64() { + svsetffr(); + let _ = svld1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + let loaded = svldnf1ub_u64(svptrue_b8(), U8_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_u64() { + svsetffr(); + let _ = svld1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + let loaded = svldnf1uh_u64(svptrue_b16(), U16_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_u64() { + svsetffr(); + let _ = svld1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + let loaded = svldnf1uw_u64(svptrue_b32(), U32_DATA.as_ptr()); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s16() { + svsetffr(); + let _ = svld1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s32() { + svsetffr(); + let _ = svld1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s32() { + svsetffr(); + let _ = svld1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_s32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_s64() { + svsetffr(); + let _ = svld1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_s64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_s64() { + svsetffr(); + let _ = svld1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_s64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_s64() { + svsetffr(); + let _ = svld1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1uw_vnum_s64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u16() { + svsetffr(); + let _ = svld1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u16(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcnth() as usize; + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u32() { + svsetffr(); + let _ = svld1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u32(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u32() { + svsetffr(); + let _ = svld1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_u32(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntw() as usize; + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1ub_vnum_u64() { + svsetffr(); + let _ = svld1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let loaded = svldnf1ub_vnum_u64(svptrue_b8(), U8_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uh_vnum_u64() { + svsetffr(); + let _ = svld1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let loaded = svldnf1uh_vnum_u64(svptrue_b16(), U16_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnf1uw_vnum_u64() { + svsetffr(); + let _ = svld1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let loaded = svldnf1uw_vnum_u64(svptrue_b32(), U32_DATA.as_ptr(), 1); + let len = svcntd() as usize; + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f32_with_svstnt1_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_f32(svptrue_b32(), storage.as_ptr() as *const f32); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_f64_with_svstnt1_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + svstnt1_f64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_f64(svptrue_b64(), storage.as_ptr() as *const f64); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s8_with_svstnt1_s8() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_s8(svptrue_b8(), storage.as_ptr() as *const i8); + assert_vector_matches_i8( + loaded, + svindex_s8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s16_with_svstnt1_s16() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_s16(svptrue_b16(), storage.as_ptr() as *const i16); + assert_vector_matches_i16( + loaded, + svindex_s16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s32_with_svstnt1_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_s32(svptrue_b32(), storage.as_ptr() as *const i32); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_s64_with_svstnt1_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_s64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_s64(svptrue_b64(), storage.as_ptr() as *const i64); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u8_with_svstnt1_u8() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u8(svptrue_b8(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_u8(svptrue_b8(), storage.as_ptr() as *const u8); + assert_vector_matches_u8( + loaded, + svindex_u8((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u16_with_svstnt1_u16() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u16(svptrue_b16(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_u16(svptrue_b16(), storage.as_ptr() as *const u16); + assert_vector_matches_u16( + loaded, + svindex_u16((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u32_with_svstnt1_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u32(svptrue_b32(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_u32(svptrue_b32(), storage.as_ptr() as *const u32); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_u64_with_svstnt1_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + svstnt1_u64(svptrue_b64(), storage.as_mut_ptr(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_u64(svptrue_b64(), storage.as_ptr() as *const u64); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f32_with_svstnt1_vnum_f32() { + let len = svcntw() as usize; + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_vnum_f32(svptrue_b32(), storage.as_ptr() as *const f32, 1); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_f64_with_svstnt1_vnum_f64() { + let len = svcntd() as usize; + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); + svstnt1_vnum_f64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_vnum_f64(svptrue_b64(), storage.as_ptr() as *const f64, 1); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s8_with_svstnt1_vnum_s8() { + let len = svcntb() as usize; + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1_vnum_s8(svptrue_b8(), storage.as_ptr() as *const i8, 1); + assert_vector_matches_i8( + loaded, + svindex_s8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s16_with_svstnt1_vnum_s16() { + let len = svcnth() as usize; + let mut storage = [0 as i16; 640usize]; + let data = svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1_vnum_s16(svptrue_b16(), storage.as_ptr() as *const i16, 1); + assert_vector_matches_i16( + loaded, + svindex_s16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s32_with_svstnt1_vnum_s32() { + let len = svcntw() as usize; + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_vnum_s32(svptrue_b32(), storage.as_ptr() as *const i32, 1); + assert_vector_matches_i32( + loaded, + svindex_s32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_s64_with_svstnt1_vnum_s64() { + let len = svcntd() as usize; + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_s64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_vnum_s64(svptrue_b64(), storage.as_ptr() as *const i64, 1); + assert_vector_matches_i64( + loaded, + svindex_s64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u8_with_svstnt1_vnum_u8() { + let len = svcntb() as usize; + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u8(svptrue_b8(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = svldnt1_vnum_u8(svptrue_b8(), storage.as_ptr() as *const u8, 1); + assert_vector_matches_u8( + loaded, + svindex_u8( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u16_with_svstnt1_vnum_u16() { + let len = svcnth() as usize; + let mut storage = [0 as u16; 640usize]; + let data = svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u16(svptrue_b16(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = svldnt1_vnum_u16(svptrue_b16(), storage.as_ptr() as *const u16, 1); + assert_vector_matches_u16( + loaded, + svindex_u16( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u32_with_svstnt1_vnum_u32() { + let len = svcntw() as usize; + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u32(svptrue_b32(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_vnum_u32(svptrue_b32(), storage.as_ptr() as *const u32, 1); + assert_vector_matches_u32( + loaded, + svindex_u32( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svldnt1_vnum_u64_with_svstnt1_vnum_u64() { + let len = svcntd() as usize; + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ); + svstnt1_vnum_u64(svptrue_b64(), storage.as_mut_ptr(), 1, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_vnum_u64(svptrue_b64(), storage.as_ptr() as *const u64, 1); + assert_vector_matches_u64( + loaded, + svindex_u64( + (len + 0usize).try_into().unwrap(), + 1usize.try_into().unwrap(), + ), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb() { + svsetffr(); + let loaded = svprfb::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh() { + svsetffr(); + let loaded = svprfh::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw() { + svsetffr(); + let loaded = svprfw::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd() { + svsetffr(); + let loaded = svprfd::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr()); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s32offset() { + let offsets = svindex_s32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_s32offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfh_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfw_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s32index() { + let indices = svindex_s32(0, 1); + svsetffr(); + let loaded = svprfd_gather_s32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_s64offset() { + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_s64offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfh_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfw_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_s64index() { + let indices = svindex_s64(0, 1); + svsetffr(); + let loaded = svprfd_gather_s64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32offset() { + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u32offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfh_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfw_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32index() { + let indices = svindex_u32(0, 1); + svsetffr(); + let loaded = svprfd_gather_u32index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b32(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64offset() { + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u64offset::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + offsets, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfh_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfw_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64index() { + let indices = svindex_u64(0, 1); + svsetffr(); + let loaded = svprfd_gather_u64index::<{ svprfop::SV_PLDL1KEEP }, i64>( + svptrue_b64(), + I64_DATA.as_ptr(), + indices, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base::<{ svprfop::SV_PLDL1KEEP }>(svptrue_b64(), bases); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u32base_offset() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfb_gather_u32base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 + 4u32 as i64, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfh_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfw_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u32base_index() { + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svsetffr(); + let loaded = svprfd_gather_u32base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b32(), + bases, + U32_DATA.as_ptr() as i64 / (4u32 as i64) + 1, + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_gather_u64base_offset() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfb_gather_u64base_offset::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 8u32.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfh_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfw_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_gather_u64base_index() { + let bases = svdup_n_u64(U64_DATA.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svsetffr(); + let loaded = svprfd_gather_u64base_index::<{ svprfop::SV_PLDL1KEEP }>( + svptrue_b64(), + bases, + 1.try_into().unwrap(), + ); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfb_vnum() { + svsetffr(); + let loaded = svprfb_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b8(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfh_vnum() { + svsetffr(); + let loaded = svprfh_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b16(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfw_vnum() { + svsetffr(); + let loaded = svprfw_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b32(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_svprfd_vnum() { + svsetffr(); + let loaded = svprfd_vnum::<{ svprfop::SV_PLDL1KEEP }, i64>(svptrue_b64(), I64_DATA.as_ptr(), 1); +} +#[simd_test(enable = "sve")] +unsafe fn test_ffr() { + svsetffr(); + let ffr = svrdffr(); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0)); + let pred = svdupq_n_b8( + true, false, true, false, true, false, true, false, true, false, true, false, true, false, + true, false, + ); + svwrffr(pred); + let ffr = svrdffr_z(svptrue_b8()); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1)); +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs new file mode 100644 index 000000000000..04a92359a022 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve/mod.rs @@ -0,0 +1,382 @@ +//! SVE intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use crate::intrinsics::{simd::*, *}; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +use crate::{marker::ConstParamTy, mem::transmute}; + +pub(super) trait AsUnsigned { + type Unsigned; + unsafe fn as_unsigned(self) -> Self::Unsigned; +} + +pub(super) trait AsSigned { + type Signed; + unsafe fn as_signed(self) -> Self::Signed; +} + +/// Same as `Into` but with into being unsafe so that it can have the required `target_feature` +pub(super) trait SveInto: Sized { + unsafe fn sve_into(self) -> T; +} + +macro_rules! impl_sve_type { + ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($( + #[doc = concat!("Scalable vector of type ", stringify!($elem_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector($elt)] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($elem_type); + )*) +} + +macro_rules! impl_sve_tuple_type { + ($(($v:vis, $vec_type:ty, $elt:tt, $name:ident))*) => ($( + impl_sve_tuple_type!(@ ($v, $vec_type, $elt, $name)); + )*); + (@ ($v:vis, $vec_type:ty, 2, $name:ident)) => ( + #[doc = concat!("Two-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 3, $name:ident)) => ( + #[doc = concat!("Three-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type); + ); + (@ ($v:vis, $vec_type:ty, 4, $name:ident)) => ( + #[doc = concat!("Four-element tuple of scalable vectors of type ", stringify!($vec_type))] + #[derive(Clone, Copy, Debug)] + #[rustc_scalable_vector] + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + $v struct $name($vec_type, $vec_type, $vec_type, $vec_type); + ); +} + +macro_rules! impl_sign_conversions_sv { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute_unchecked(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute_unchecked(self) + } + } + )*) +} + +macro_rules! impl_sign_conversions { + ($(($signed:ty, $unsigned:ty))*) => ($( + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_unsigned(self) -> $unsigned { + transmute(self) + } + } + + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + #[target_feature(enable = "sve")] + unsafe fn as_signed(self) -> $signed { + transmute(self) + } + } + )*) +} + +/// LLVM requires the predicate lane count to be the same as the lane count +/// it's working with. However the ACLE only defines one bool type and the +/// instruction set doesn't have this distinction. As a result we have to +/// create these internal types so we can match the LLVM signature. Each of +/// these internal types can be converted to the public `svbool_t` type and +/// the `svbool_t` type can be converted into these. +macro_rules! impl_internal_sve_predicate { + ($(($name:ident, $elt:literal))*) => ($( + impl_sve_type! { + (pub(super), bool, $name, $elt) + } + + impl SveInto for $name { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> svbool_t { + #[allow(improper_ctypes)] + unsafe extern "C" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.to.svbool.nxv", $elt, "i1") + )] + fn convert_to_svbool(b: $name) -> svbool_t; + } + unsafe { convert_to_svbool(self) } + } + } + + #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] + impl SveInto<$name> for svbool_t { + #[inline] + #[target_feature(enable = "sve")] + unsafe fn sve_into(self) -> $name { + #[allow(improper_ctypes)] + unsafe extern "C" { + #[cfg_attr( + target_arch = "aarch64", + link_name = concat!("llvm.aarch64.sve.convert.from.svbool.nxv", $elt, "i1") + )] + fn convert_from_svbool(b: svbool_t) -> $name; + } + unsafe { convert_from_svbool(self) } + } + } + )*) +} + +impl_sve_type! { + (pub, bool, svbool_t, 16) + + (pub, i8, svint8_t, 16) + (pub, u8, svuint8_t, 16) + + (pub, i16, svint16_t, 8) + (pub, u16, svuint16_t, 8) + (pub, f32, svfloat32_t, 4) + (pub, i32, svint32_t, 4) + (pub, u32, svuint32_t, 4) + (pub, f64, svfloat64_t, 2) + (pub, i64, svint64_t, 2) + (pub, u64, svuint64_t, 2) + + // Internal types: + (pub(super), i8, nxv2i8, 2) + (pub(super), i8, nxv4i8, 4) + (pub(super), i8, nxv8i8, 8) + + (pub(super), i16, nxv2i16, 2) + (pub(super), i16, nxv4i16, 4) + + (pub(super), i32, nxv2i32, 2) + + (pub(super), u8, nxv2u8, 2) + (pub(super), u8, nxv4u8, 4) + (pub(super), u8, nxv8u8, 8) + + (pub(super), u16, nxv2u16, 2) + (pub(super), u16, nxv4u16, 4) + + (pub(super), u32, nxv2u32, 2) +} + +impl_sve_tuple_type! { + (pub, svint8_t, 2, svint8x2_t) + (pub, svuint8_t, 2, svuint8x2_t) + (pub, svint16_t, 2, svint16x2_t) + (pub, svuint16_t, 2, svuint16x2_t) + (pub, svfloat32_t, 2, svfloat32x2_t) + (pub, svint32_t, 2, svint32x2_t) + (pub, svuint32_t, 2, svuint32x2_t) + (pub, svfloat64_t, 2, svfloat64x2_t) + (pub, svint64_t, 2, svint64x2_t) + (pub, svuint64_t, 2, svuint64x2_t) + + (pub, svint8_t, 3, svint8x3_t) + (pub, svuint8_t, 3, svuint8x3_t) + (pub, svint16_t, 3, svint16x3_t) + (pub, svuint16_t, 3, svuint16x3_t) + (pub, svfloat32_t, 3, svfloat32x3_t) + (pub, svint32_t, 3, svint32x3_t) + (pub, svuint32_t, 3, svuint32x3_t) + (pub, svfloat64_t, 3, svfloat64x3_t) + (pub, svint64_t, 3, svint64x3_t) + (pub, svuint64_t, 3, svuint64x3_t) + + (pub, svint8_t, 4, svint8x4_t) + (pub, svuint8_t, 4, svuint8x4_t) + (pub, svint16_t, 4, svint16x4_t) + (pub, svuint16_t, 4, svuint16x4_t) + (pub, svfloat32_t, 4, svfloat32x4_t) + (pub, svint32_t, 4, svint32x4_t) + (pub, svuint32_t, 4, svuint32x4_t) + (pub, svfloat64_t, 4, svfloat64x4_t) + (pub, svint64_t, 4, svint64x4_t) + (pub, svuint64_t, 4, svuint64x4_t) +} + +impl_sign_conversions! { + (i8, u8) + (i16, u16) + (i32, u32) + (i64, u64) + (*const i8, *const u8) + (*const i16, *const u16) + (*const i32, *const u32) + (*const i64, *const u64) + (*mut i8, *mut u8) + (*mut i16, *mut u16) + (*mut i32, *mut u32) + (*mut i64, *mut u64) +} + +impl_sign_conversions_sv! { + (svint8_t, svuint8_t) + (svint16_t, svuint16_t) + (svint32_t, svuint32_t) + (svint64_t, svuint64_t) + + (svint8x2_t, svuint8x2_t) + (svint16x2_t, svuint16x2_t) + (svint32x2_t, svuint32x2_t) + (svint64x2_t, svuint64x2_t) + + (svint8x3_t, svuint8x3_t) + (svint16x3_t, svuint16x3_t) + (svint32x3_t, svuint32x3_t) + (svint64x3_t, svuint64x3_t) + + (svint8x4_t, svuint8x4_t) + (svint16x4_t, svuint16x4_t) + (svint32x4_t, svuint32x4_t) + (svint64x4_t, svuint64x4_t) + + // Internal types: + (nxv2i8, nxv2u8) + (nxv4i8, nxv4u8) + (nxv8i8, nxv8u8) + + (nxv2i16, nxv2u16) + (nxv4i16, nxv4u16) + + (nxv2i32, nxv2u32) +} + +impl_internal_sve_predicate! { + (svbool2_t, 2) + (svbool4_t, 4) + (svbool8_t, 8) +} + +/// Patterns returned by a `PTRUE` +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svpattern { + /// Activate the largest power-of-two number of elements that is less than the vector length + SV_POW2 = 0, + /// Activate the first element + SV_VL1 = 1, + /// Activate the first two elements + SV_VL2 = 2, + /// Activate the first three elements + SV_VL3 = 3, + /// Activate the first four elements + SV_VL4 = 4, + /// Activate the first five elements + SV_VL5 = 5, + /// Activate the first six elements + SV_VL6 = 6, + /// Activate the first seven elements + SV_VL7 = 7, + /// Activate the first eight elements + SV_VL8 = 8, + /// Activate the first sixteen elements + SV_VL16 = 9, + /// Activate the first thirty-two elements + SV_VL32 = 10, + /// Activate the first sixty-four elements + SV_VL64 = 11, + /// Activate the first one-hundred-and-twenty-eight elements + SV_VL128 = 12, + /// Activate the first two-hundred-and-fifty-six elements + SV_VL256 = 13, + /// Activate the largest multiple-of-four number of elements that is less than the vector length + SV_MUL4 = 29, + /// Activate the largest multiple-of-three number of elements that is less than the vector + /// length + SV_MUL3 = 30, + /// Activate all elements + SV_ALL = 31, +} + +/// Addressing mode for prefetch intrinsics - allows the specification of the expected access +/// kind (read or write), the cache level to load the data, the data retention policy +/// (temporal or streaming) +#[repr(i32)] +#[allow(non_camel_case_types)] +#[derive(Clone, Copy, Debug, PartialEq, Eq, ConstParamTy)] +#[non_exhaustive] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub enum svprfop { + /// Temporal fetch of the addressed location for reading to the L1 cache (i.e. allocate in + /// cache normally) + SV_PLDL1KEEP = 0, + /// Streaming fetch of the addressed location for reading to the L1 cache (i.e. memory only + /// used once) + SV_PLDL1STRM = 1, + /// Temporal fetch of the addressed location for reading to the L2 cache (i.e. allocate in + /// cache normally) + SV_PLDL2KEEP = 2, + /// Streaming fetch of the addressed location for reading to the L2 cache (i.e. memory only + /// used once) + SV_PLDL2STRM = 3, + /// Temporal fetch of the addressed location for reading to the L3 cache (i.e. allocate in + /// cache normally) + SV_PLDL3KEEP = 4, + /// Streaming fetch of the addressed location for reading to the L3 cache (i.e. memory only + /// used once) + SV_PLDL3STRM = 5, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. allocate in + /// cache normally) + SV_PSTL1KEEP = 8, + /// Temporal fetch of the addressed location for writing to the L1 cache (i.e. memory only + /// used once) + SV_PSTL1STRM = 9, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. allocate in + /// cache normally) + SV_PSTL2KEEP = 10, + /// Temporal fetch of the addressed location for writing to the L2 cache (i.e. memory only + /// used once) + SV_PSTL2STRM = 11, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. allocate in + /// cache normally) + SV_PSTL3KEEP = 12, + /// Temporal fetch of the addressed location for writing to the L3 cache (i.e. memory only + /// used once) + SV_PSTL3STRM = 13, +} + +// FIXME(arm-maintainers): On MSVC targets, it seemed like spurious corruption of the FFR was being +// observed non-deterministically on CI. Disabling these tests out of caution on that platform until +// it is investigated. +#[cfg(all(test, not(target_env = "msvc")))] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs new file mode 100644 index 000000000000..c5b0149c9c30 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/generated.rs @@ -0,0 +1,23881 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*; + +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv16i8")] + fn _svaba_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_s8(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svaba_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv8i16")] + fn _svaba_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_s16(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svaba_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv4i32")] + fn _svaba_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_s32(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svaba_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saba.nxv2i64")] + fn _svaba_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_s64(op1, op2, op3) } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saba))] +pub fn svaba_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svaba_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv16i8")] + fn _svaba_u8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svaba_u8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svaba_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv8i16")] + fn _svaba_u16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svaba_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svaba_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv4i32")] + fn _svaba_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svaba_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svaba_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaba.nxv2i64")] + fn _svaba_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svaba_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaba[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaba))] +pub fn svaba_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svaba_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv8i16")] + fn _svabalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv4i32")] + fn _svabalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalb.nxv2i64")] + fn _svabalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalb))] +pub fn svabalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv8i16")] + fn _svabalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv4i32")] + fn _svabalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalb.nxv2i64")] + fn _svabalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalb))] +pub fn svabalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv8i16")] + fn _svabalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_s16(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svabalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv4i32")] + fn _svabalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_s32(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svabalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabalt.nxv2i64")] + fn _svabalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_s64(op1, op2, op3) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabalt))] +pub fn svabalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svabalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv8i16")] + fn _svabalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svabalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svabalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv4i32")] + fn _svabalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svabalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svabalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabalt.nxv2i64")] + fn _svabalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svabalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabalt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabalt))] +pub fn svabalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svabalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv8i16")] + fn _svabdlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_s16(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv4i32")] + fn _svabdlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_s32(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlb.nxv2i64")] + fn _svabdlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_s64(op1, op2) } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlb))] +pub fn svabdlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv8i16")] + fn _svabdlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv4i32")] + fn _svabdlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlb.nxv2i64")] + fn _svabdlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlb))] +pub fn svabdlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv8i16")] + fn _svabdlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_s16(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svabdlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv4i32")] + fn _svabdlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_s32(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svabdlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sabdlt.nxv2i64")] + fn _svabdlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_s64(op1, op2) } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sabdlt))] +pub fn svabdlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svabdlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv8i16")] + fn _svabdlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svabdlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svabdlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv4i32")] + fn _svabdlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svabdlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svabdlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uabdlt.nxv2i64")] + fn _svabdlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svabdlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Absolute difference long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svabdlt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uabdlt))] +pub fn svabdlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svabdlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv8i16")] + fn _svadalp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s16_z(pg: svbool_t, op1: svint16_t, op2: svint8_t) -> svint16_t { + svadalp_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv4i32")] + fn _svadalp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s32_z(pg: svbool_t, op1: svint32_t, op2: svint16_t) -> svint32_t { + svadalp_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sadalp.nxv2i64")] + fn _svadalp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sadalp))] +pub fn svadalp_s64_z(pg: svbool_t, op1: svint64_t, op2: svint32_t) -> svint64_t { + svadalp_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv8i16")] + fn _svadalp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svadalp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + svadalp_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv4i32")] + fn _svadalp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svadalp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + svadalp_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uadalp.nxv2i64")] + fn _svadalp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svadalp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, op1, op2) +} +#[doc = "Add and accumulate long pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadalp[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uadalp))] +pub fn svadalp_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + svadalp_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv4i32")] + fn _svadclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclb.nxv2i64")] + fn _svadclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclb))] +pub fn svadclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv4i32")] + fn _svadclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svadclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svadclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.adclt.nxv2i64")] + fn _svadclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svadclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Add with carry long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svadclt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(adclt))] +pub fn svadclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svadclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv8i16")] + fn _svaddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnb_s16(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svaddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv4i32")] + fn _svaddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnb_s32(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svaddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnb.nxv2i64")] + fn _svaddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnb_s64(op1, op2) } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svaddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnb))] +pub fn svaddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv8i16")] + fn _svaddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svaddhnt_s16(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svaddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv4i32")] + fn _svaddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svaddhnt_s32(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svaddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addhnt.nxv2i64")] + fn _svaddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svaddhnt_s64(even, op1, op2) } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svaddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svaddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svaddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svaddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svaddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svaddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddhnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addhnt))] +pub fn svaddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svaddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv8i16")] + fn _svaddlb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_s16(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv4i32")] + fn _svaddlb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_s32(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlb.nxv2i64")] + fn _svaddlb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_s64(op1, op2) } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlb))] +pub fn svaddlb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv8i16")] + fn _svaddlb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv4i32")] + fn _svaddlb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlb.nxv2i64")] + fn _svaddlb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlb))] +pub fn svaddlb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv8i16" + )] + fn _svaddlbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlbt_s16(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv4i32" + )] + fn _svaddlbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlbt_s32(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.saddlbt.nxv2i64" + )] + fn _svaddlbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlbt_s64(op1, op2) } +} +#[doc = "Add long (bottom + top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlbt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlbt))] +pub fn svaddlbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv8i16")] + fn _svaddlt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_s16(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svaddlt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv4i32")] + fn _svaddlt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_s32(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svaddlt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddlt.nxv2i64")] + fn _svaddlt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_s64(op1, op2) } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddlt))] +pub fn svaddlt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svaddlt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv8i16")] + fn _svaddlt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddlt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svaddlt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv4i32")] + fn _svaddlt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddlt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svaddlt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddlt.nxv2i64")] + fn _svaddlt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddlt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddlt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddlt))] +pub fn svaddlt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svaddlt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv4f32")] + fn _svaddp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svaddp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svaddp_f32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.faddp.nxv2f64")] + fn _svaddp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svaddp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(faddp))] +pub fn svaddp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svaddp_f64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv16i8")] + fn _svaddp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaddp_s8_m(pg, op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svaddp_s8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv8i16")] + fn _svaddp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svaddp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svaddp_s16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv4i32")] + fn _svaddp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svaddp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svaddp_s32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.addp.nxv2i64")] + fn _svaddp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svaddp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svaddp_s64_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svaddp_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svaddp_u8_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { svaddp_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svaddp_u16_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svaddp_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svaddp_u32_m(pg, op1, op2) +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svaddp_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddp[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(addp))] +pub fn svaddp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svaddp_u64_m(pg, op1, op2) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv8i16")] + fn _svaddwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_s16(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv4i32")] + fn _svaddwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_s32(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwb.nxv2i64")] + fn _svaddwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_s64(op1, op2) } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwb))] +pub fn svaddwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv8i16")] + fn _svaddwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv4i32")] + fn _svaddwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwb.nxv2i64")] + fn _svaddwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwb))] +pub fn svaddwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv8i16")] + fn _svaddwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_s16(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svaddwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv4i32")] + fn _svaddwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_s32(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svaddwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.saddwt.nxv2i64")] + fn _svaddwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_s64(op1, op2) } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(saddwt))] +pub fn svaddwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svaddwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv8i16")] + fn _svaddwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svaddwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svaddwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv4i32")] + fn _svaddwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svaddwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svaddwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uaddwt.nxv2i64")] + fn _svaddwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svaddwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Add wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaddwt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uaddwt))] +pub fn svaddwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svaddwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "AES single round decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesd[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesd))] +pub fn svaesd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesd")] + fn _svaesd_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaesd_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES single round encryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaese[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aese))] +pub fn svaese_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aese")] + fn _svaese_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svaese_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "AES inverse mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesimc[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesimc))] +pub fn svaesimc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesimc")] + fn _svaesimc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesimc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "AES mix columns"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svaesmc[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(aesmc))] +pub fn svaesmc_u8(op: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.aesmc")] + fn _svaesmc_u8(op: svint8_t) -> svint8_t; + } + unsafe { _svaesmc_u8(op.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv16i8")] + fn _svbcax_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbcax_s8(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbcax_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv8i16")] + fn _svbcax_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbcax_s16(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbcax_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv4i32")] + fn _svbcax_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbcax_s32(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbcax_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bcax.nxv2i64")] + fn _svbcax_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbcax_s64(op1, op2, op3) } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbcax_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbcax_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbcax_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbcax_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbcax_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbcax_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbcax_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbcax_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbcax[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bcax))] +pub fn svbcax_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbcax_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv16i8")] + fn _svbdep_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbdep_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbdep_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv8i16")] + fn _svbdep_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbdep_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbdep_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv4i32")] + fn _svbdep_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbdep_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbdep_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bdep.x.nxv2i64")] + fn _svbdep_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbdep_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Scatter lower bits into positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbdep[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bdep))] +pub fn svbdep_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbdep_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv16i8")] + fn _svbext_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbext_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbext_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv8i16")] + fn _svbext_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbext_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbext_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv4i32")] + fn _svbext_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbext_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbext_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bext.x.nxv2i64")] + fn _svbext_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbext_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Gather lower bits from positions selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbext[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bext))] +pub fn svbext_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbext_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv16i8")] + fn _svbgrp_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svbgrp_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svbgrp_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv8i16")] + fn _svbgrp_u16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svbgrp_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u16(op1: svuint16_t, op2: u16) -> svuint16_t { + svbgrp_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv4i32")] + fn _svbgrp_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svbgrp_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svbgrp_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bgrp.x.nxv2i64")] + fn _svbgrp_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svbgrp_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Group bits to right or left as selected by bitmask"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbgrp[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-bitperm")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bgrp))] +pub fn svbgrp_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svbgrp_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv16i8")] + fn _svbsl1n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl1n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl1n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv8i16")] + fn _svbsl1n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl1n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl1n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv4i32")] + fn _svbsl1n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl1n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl1n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl1n.nxv2i64")] + fn _svbsl1n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl1n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl1n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl1n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl1n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl1n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl1n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl1n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl1n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl1n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with first input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl1n[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl1n))] +pub fn svbsl1n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl1n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv16i8")] + fn _svbsl2n_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl2n_s8(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl2n_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv8i16")] + fn _svbsl2n_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl2n_s16(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl2n_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv4i32")] + fn _svbsl2n_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl2n_s32(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl2n_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl2n.nxv2i64")] + fn _svbsl2n_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl2n_s64(op1, op2, op3) } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl2n_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl2n_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl2n_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl2n_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl2n_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl2n_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl2n_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl2n_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select with second input inverted"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl2n[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl2n))] +pub fn svbsl2n_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl2n_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv16i8")] + fn _svbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv8i16")] + fn _svbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv4i32")] + fn _svbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.bsl.nxv2i64")] + fn _svbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svbsl[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(bsl))] +pub fn svbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv16i8")] + fn _svcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv8i16")] + fn _svcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv4i32")] + fn _svcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cadd.x.nxv2i64")] + fn _svcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcadd[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cadd, IMM_ROTATION = 90))] +pub fn svcadd_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe { svcadd_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv4i32" + )] + fn _svcdot_lane_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cdot.lane.nxv2i64" + )] + fn _svcdot_lane_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_lane_s64(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv4i32")] + fn _svcdot_s32( + op1: svint32_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcdot_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex dot product"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcdot[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cdot, IMM_ROTATION = 90))] +pub fn svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cdot.nxv2i64")] + fn _svcdot_s64( + op1: svint64_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcdot_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv8i16" + )] + fn _svcmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.cmla.lane.x.nxv4i32" + )] + fn _svcmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s16::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svcmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_lane_s32::( + op1.as_signed(), + op2.as_signed(), + op3.as_signed(), + ) + .as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv16i8")] + fn _svcmla_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svcmla_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv8i16")] + fn _svcmla_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svcmla_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv4i32")] + fn _svcmla_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svcmla_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.cmla.x.nxv2i64")] + fn _svcmla_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svcmla_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u8( + op1: svuint8_t, + op2: svuint8_t, + op3: svuint8_t, +) -> svuint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s8::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Complex multiply-add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcmla[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(cmla, IMM_ROTATION = 90))] +pub fn svcmla_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe { + svcmla_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtlt.f64f32")] + fn _svcvtlt_f64_f32_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat32_t) + -> svfloat64_t; + } + unsafe { _svcvtlt_f64_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Up convert long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtlt_f64[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtlt))] +pub fn svcvtlt_f64_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat64_t { + unsafe { svcvtlt_f64_f32_m(crate::intrinsics::transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtnt.f32f64")] + fn _svcvtnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert and narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtnt_f32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtnt))] +pub fn svcvtnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtnt_f32_f64_m(even, pg, op) +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtx.f32f64")] + fn _svcvtx_f32_f64_m(inactive: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtx_f32_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe { svcvtx_f32_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Down convert, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtx_f32[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtx))] +pub fn svcvtx_f32_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtx_f32_f64_m(svdup_n_f32(0.0), pg, op) +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fcvtxnt.f32f64")] + fn _svcvtxnt_f32_f64_m(even: svfloat32_t, pg: svbool2_t, op: svfloat64_t) -> svfloat32_t; + } + unsafe { _svcvtxnt_f32_f64_m(even, pg.sve_into(), op) } +} +#[doc = "Down convert, rounding to odd (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svcvtxnt_f32[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fcvtxnt))] +pub fn svcvtxnt_f32_f64_x(even: svfloat32_t, pg: svbool_t, op: svfloat64_t) -> svfloat32_t { + svcvtxnt_f32_f64_m(even, pg, op) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv16i8")] + fn _sveor3_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _sveor3_s8(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + sveor3_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv8i16")] + fn _sveor3_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _sveor3_s16(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + sveor3_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv4i32")] + fn _sveor3_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _sveor3_s32(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + sveor3_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor3.nxv2i64")] + fn _sveor3_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _sveor3_s64(op1, op2, op3) } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + sveor3_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { sveor3_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + sveor3_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { sveor3_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + sveor3_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { sveor3_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + sveor3_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { sveor3_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR of three vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor3[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eor3))] +pub fn sveor3_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + sveor3_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv16i8")] + fn _sveorbt_s8(odd: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveorbt_s8(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s8(odd: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveorbt_s8(odd, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv8i16")] + fn _sveorbt_s16(odd: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveorbt_s16(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s16(odd: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveorbt_s16(odd, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv4i32")] + fn _sveorbt_s32(odd: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveorbt_s32(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s32(odd: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveorbt_s32(odd, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorbt.nxv2i64")] + fn _sveorbt_s64(odd: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveorbt_s64(odd, op1, op2) } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_s64(odd: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveorbt_s64(odd, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u8(odd: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveorbt_s8(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u8(odd: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveorbt_u8(odd, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u16(odd: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveorbt_s16(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u16(odd: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveorbt_u16(odd, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u32(odd: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveorbt_s32(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u32(odd: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveorbt_u32(odd, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_u64(odd: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveorbt_s64(odd.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (bottom, top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorbt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eorbt))] +pub fn sveorbt_n_u64(odd: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveorbt_u64(odd, op1, svdup_n_u64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv16i8")] + fn _sveortb_s8(even: svint8_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _sveortb_s8(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s8(even: svint8_t, op1: svint8_t, op2: i8) -> svint8_t { + sveortb_s8(even, op1, svdup_n_s8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv8i16")] + fn _sveortb_s16(even: svint16_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _sveortb_s16(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s16(even: svint16_t, op1: svint16_t, op2: i16) -> svint16_t { + sveortb_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv4i32")] + fn _sveortb_s32(even: svint32_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _sveortb_s32(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s32(even: svint32_t, op1: svint32_t, op2: i32) -> svint32_t { + sveortb_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eortb.nxv2i64")] + fn _sveortb_s64(even: svint64_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _sveortb_s64(even, op1, op2) } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_s64(even: svint64_t, op1: svint64_t, op2: i64) -> svint64_t { + sveortb_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u8(even: svuint8_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { sveortb_s8(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u8(even: svuint8_t, op1: svuint8_t, op2: u8) -> svuint8_t { + sveortb_u8(even, op1, svdup_n_u8(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u16(even: svuint16_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe { sveortb_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u16(even: svuint16_t, op1: svuint16_t, op2: u16) -> svuint16_t { + sveortb_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u32(even: svuint32_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { sveortb_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u32(even: svuint32_t, op1: svuint32_t, op2: u32) -> svuint32_t { + sveortb_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_u64(even: svuint64_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { sveortb_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Interleaving exclusive OR (top, bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveortb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(eortb))] +pub fn sveortb_n_u64(even: svuint64_t, op1: svuint64_t, op2: u64) -> svuint64_t { + sveortb_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv16i8")] + fn _svhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_s8_m(pg, op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv8i16")] + fn _svhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv4i32")] + fn _svhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shadd.nxv2i64")] + fn _svhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shadd))] +pub fn svhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv16i8")] + fn _svhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv8i16")] + fn _svhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv4i32")] + fn _svhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhadd.nxv2i64")] + fn _svhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, op1, op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhadd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhadd))] +pub fn svhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv4i32" + )] + fn _svhistcnt_s32_z(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhistcnt_s32_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histcnt.nxv2i64" + )] + fn _svhistcnt_s64_z(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhistcnt_s64_z(pg.sve_into(), op1, op2).as_unsigned() } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe { svhistcnt_s32_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistcnt[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histcnt))] +pub fn svhistcnt_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svhistcnt_s64_z(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.histseg.nxv16i8" + )] + fn _svhistseg_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhistseg_s8(op1, op2).as_unsigned() } +} +#[doc = "Count matching elements in 128-bit segments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhistseg[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(histseg))] +pub fn svhistseg_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe { svhistseg_s8(op1.as_signed(), op2.as_signed()) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv16i8")] + fn _svhsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv8i16")] + fn _svhsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv4i32")] + fn _svhsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsub.nxv2i64")] + fn _svhsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv16i8")] + fn _svhsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv8i16")] + fn _svhsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv4i32")] + fn _svhsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsub.nxv2i64")] + fn _svhsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsub[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv16i8")] + fn _svhsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_s8_m(pg, op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svhsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svhsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv8i16")] + fn _svhsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svhsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svhsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv4i32")] + fn _svhsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svhsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svhsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shsubr.nxv2i64")] + fn _svhsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svhsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shsub))] +pub fn svhsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svhsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv16i8")] + fn _svhsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svhsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svhsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svhsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv8i16")] + fn _svhsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svhsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svhsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svhsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv4i32")] + fn _svhsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svhsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svhsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svhsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uhsubr.nxv2i64")] + fn _svhsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svhsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, op1, op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svhsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Halving subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svhsubr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uhsub))] +pub fn svhsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svhsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_f64( + pg: svbool_t, + base: *const f64, + indices: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2f64" + )] + fn _svldnt1_gather_s64index_f64( + pg: svbool2_t, + base: *const f64, + indices: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64index_f64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_s64( + pg: svbool_t, + base: *const i64, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i64" + )] + fn _svldnt1_gather_s64index_s64( + pg: svbool2_t, + base: *const i64, + indices: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64index_s64(pg.sve_into(), base, indices) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64index_u64( + pg: svbool_t, + base: *const u64, + indices: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_f64( + pg: svbool_t, + base: *const f64, + indices: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64index_f64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_s64( + pg: svbool_t, + base: *const i64, + indices: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64index_u64( + pg: svbool_t, + base: *const u64, + indices: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64index_s64(pg, base.as_signed(), indices.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svint64_t, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2f64" + )] + fn _svldnt1_gather_s64offset_f64( + pg: svbool2_t, + base: *const f64, + offsets: svint64_t, + ) -> svfloat64_t; + } + _svldnt1_gather_s64offset_f64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i64" + )] + fn _svldnt1_gather_s64offset_s64( + pg: svbool2_t, + base: *const i64, + offsets: svint64_t, + ) -> svint64_t; + } + _svldnt1_gather_s64offset_s64(pg.sve_into(), base, offsets) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_s64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_f32( + pg: svbool_t, + base: *const f32, + offsets: svuint32_t, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4f32" + )] + fn _svldnt1_gather_u32offset_f32( + pg: svbool4_t, + base: *const f32, + offsets: svint32_t, + ) -> svfloat32_t; + } + _svldnt1_gather_u32offset_f32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_s32( + pg: svbool_t, + base: *const i32, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32" + )] + fn _svldnt1_gather_u32offset_s32( + pg: svbool4_t, + base: *const i32, + offsets: svint32_t, + ) -> svint32_t; + } + _svldnt1_gather_u32offset_s32(pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32offset_u32( + pg: svbool_t, + base: *const u32, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1_gather_u32offset_s32(pg, base.as_signed(), offsets).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_f64( + pg: svbool_t, + base: *const f64, + offsets: svuint64_t, +) -> svfloat64_t { + svldnt1_gather_s64offset_f64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_s64( + pg: svbool_t, + base: *const i64, + offsets: svuint64_t, +) -> svint64_t { + svldnt1_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64offset_u64( + pg: svbool_t, + base: *const u64, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1_gather_s64offset_s64(pg, base.as_signed(), offsets.as_signed()).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_f32(pg: svbool_t, bases: svuint32_t) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_f64(pg: svbool_t, bases: svuint64_t) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svfloat32_t { + svldnt1_gather_u32base_offset_f32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svfloat64_t { + svldnt1_gather_u64base_offset_f64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(3)) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_f32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_f32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svfloat32_t; + } + _svldnt1_gather_u32base_offset_f32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svldnt1_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> svint32_t; + } + _svldnt1_gather_u32base_offset_s32(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_f64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_f64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svfloat64_t; + } + _svldnt1_gather_u64base_offset_f64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svldnt1_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> svint64_t; + } + _svldnt1_gather_u64base_offset_s64(pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Unextended load, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1d))] +pub unsafe fn svldnt1_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1sb_gather_s64offset_s64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1sh_gather_s64offset_s64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1sw_gather_s64offset_s64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64offset_s64( + pg.sve_into(), + base, + offsets, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_s64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_s32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1sb_gather_u32offset_s32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_s32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1sh_gather_u32offset_s32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32offset_s32( + pg.sve_into(), + base, + offsets.as_signed(), + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32offset_u32( + pg: svbool_t, + base: *const i8, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sb_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32offset_u32( + pg: svbool_t, + base: *const i16, + offsets: svuint32_t, +) -> svuint32_t { + svldnt1sh_gather_u32offset_s32(pg, base, offsets).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_s64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_s64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_s64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64offset_u64( + pg: svbool_t, + base: *const i8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sb_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64offset_u64( + pg: svbool_t, + base: *const i16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64offset_u64( + pg: svbool_t, + base: *const i32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64offset_s64(pg, base, offsets.as_signed()).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1sb_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1sh_gather_u32base_offset_s32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u32base_offset_s32( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1sb_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast(_svldnt1sb_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1sh_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1sw_gather_u64base_offset_s64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_u64base_offset_s64( + pg.sve_into(), + bases.as_signed(), + offset, + )) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, offset).as_unsigned() +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sb_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sb_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sb_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sb_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sb))] +pub unsafe fn svldnt1sb_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sb_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_s64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1sh_gather_s64index_s64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast(_svldnt1sh_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_s64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1sw_gather_s64index_s64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast(_svldnt1sw_gather_s64index_s64(pg.sve_into(), base, indices)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_s64index_u64( + pg: svbool_t, + base: *const i16, + indices: svint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_s64index_u64( + pg: svbool_t, + base: *const i32, + indices: svint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_s64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_s64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64index_u64( + pg: svbool_t, + base: *const i16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sh_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64index_u64( + pg: svbool_t, + base: *const i32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1sw_gather_s64index_s64(pg, base, indices.as_signed()).as_unsigned() +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1sh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1sh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1sw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sh))] +pub unsafe fn svldnt1sh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and sign-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1sw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1sw))] +pub unsafe fn svldnt1sw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1sw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_s64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i8" + )] + fn _svldnt1ub_gather_s64offset_u64( + pg: svbool2_t, + base: *const i8, + offsets: svint64_t, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i16" + )] + fn _svldnt1uh_gather_s64offset_u64( + pg: svbool2_t, + base: *const i16, + offsets: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.nxv2i32" + )] + fn _svldnt1uw_gather_s64offset_u64( + pg: svbool2_t, + base: *const i32, + offsets: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64offset_u64(pg.sve_into(), base.as_signed(), offsets).as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_s32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svint32_t { + svldnt1ub_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_s32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svint32_t { + svldnt1uh_gather_u32offset_u32(pg, base, offsets).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32offset_u32( + pg: svbool_t, + base: *const u8, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8" + )] + fn _svldnt1ub_gather_u32offset_u32( + pg: svbool4_t, + base: *const i8, + offsets: svint32_t, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u32]offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32offset_u32( + pg: svbool_t, + base: *const u16, + offsets: svuint32_t, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16" + )] + fn _svldnt1uh_gather_u32offset_u32( + pg: svbool4_t, + base: *const i16, + offsets: svint32_t, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32offset_u32(pg.sve_into(), base.as_signed(), offsets.as_signed()) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_s64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_s64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_s64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64offset_u64( + pg: svbool_t, + base: *const u8, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1ub_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64offset_u64( + pg: svbool_t, + base: *const u16, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64offset_u64( + pg: svbool_t, + base: *const u32, + offsets: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64offset_u64(pg, base, offsets.as_signed()) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svldnt1ub_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_offset_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, +) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svldnt1uh_gather_u32base_offset_u32( + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ) -> nxv4i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u32base_offset_u32(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, offset).as_signed() +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svldnt1ub_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i8; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1ub_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svldnt1uh_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_offset_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svldnt1uw_gather_u64base_offset_u64( + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_u64base_offset_u64(pg.sve_into(), bases.as_signed(), offset) + .as_unsigned(), + ) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1ub_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_s32(pg: svbool_t, bases: svuint32_t) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1ub_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_u32(pg: svbool_t, bases: svuint32_t) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1ub_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_s64(pg: svbool_t, bases: svuint64_t) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, 0) +} +#[doc = "Load 8-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1ub_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1b))] +pub unsafe fn svldnt1ub_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1ub_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_u64(pg: svbool_t, bases: svuint64_t) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, 0) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_s64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_s64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_s64index_u64( + pg: svbool_t, + base: *const u16, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i16" + )] + fn _svldnt1uh_gather_s64index_u64( + pg: svbool2_t, + base: *const i16, + indices: svint64_t, + ) -> nxv2i16; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uh_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[s64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_s64index_u64( + pg: svbool_t, + base: *const u32, + indices: svint64_t, +) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ldnt1.gather.index.nxv2i32" + )] + fn _svldnt1uw_gather_s64index_u64( + pg: svbool2_t, + base: *const i32, + indices: svint64_t, + ) -> nxv2i32; + } + crate::intrinsics::simd::simd_cast::( + _svldnt1uw_gather_s64index_u64(pg.sve_into(), base.as_signed(), indices).as_unsigned(), + ) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_s64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_s64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()).as_signed() +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64index_u64( + pg: svbool_t, + base: *const u16, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uh_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather_[u64]index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64index_u64( + pg: svbool_t, + base: *const u32, + indices: svuint64_t, +) -> svuint64_t { + svldnt1uw_gather_s64index_u64(pg, base, indices.as_signed()) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_s32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svint32_t { + svldnt1uh_gather_u32base_offset_s32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u32base]_index_u32)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, +) -> svuint32_t { + svldnt1uh_gather_u32base_offset_u32(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uh_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_s64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svint64_t { + svldnt1uw_gather_u64base_offset_s64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Load 16-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uh_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1h))] +pub unsafe fn svldnt1uh_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uh_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(1)) +} +#[doc = "Load 32-bit data and zero-extend, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svldnt1uw_gather[_u64base]_index_u64)"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ldnt1w))] +pub unsafe fn svldnt1uw_gather_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, +) -> svuint64_t { + svldnt1uw_gather_u64base_offset_u64(pg, bases, index.unchecked_shl(2)) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_m(inactive: svint32_t, pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv4f32")] + fn _svlogb_f32_m(inactive: svint32_t, pg: svbool4_t, op: svfloat32_t) -> svint32_t; + } + unsafe { _svlogb_f32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_x(pg: svbool_t, op: svfloat32_t) -> svint32_t { + unsafe { svlogb_f32_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f32_z(pg: svbool_t, op: svfloat32_t) -> svint32_t { + svlogb_f32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_m(inactive: svint64_t, pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.flogb.nxv2f64")] + fn _svlogb_f64_m(inactive: svint64_t, pg: svbool2_t, op: svfloat64_t) -> svint64_t; + } + unsafe { _svlogb_f64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_x(pg: svbool_t, op: svfloat64_t) -> svint64_t { + unsafe { svlogb_f64_m(transmute_unchecked(op), pg, op) } +} +#[doc = "Base 2 logarithm as integer"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svlogb[_f64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(flogb))] +pub fn svlogb_f64_z(pg: svbool_t, op: svfloat64_t) -> svint64_t { + svlogb_f64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv16i8")] + fn _svmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svmatch_s8(pg, op1, op2) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.match.nxv8i16")] + fn _svmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect any matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmatch[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(match))] +pub fn svmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv4f32" + )] + fn _svmaxnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxnmp_f32_m(pg, op1, op2) +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmaxnmp.nxv2f64" + )] + fn _svmaxnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxnmp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub fn svmaxnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxnmp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv4f32")] + fn _svmaxp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svmaxp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svmaxp_f32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fmaxp.nxv2f64")] + fn _svmaxp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svmaxp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmaxp))] +pub fn svmaxp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svmaxp_f64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv16i8")] + fn _svmaxp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_s8_m(pg, op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svmaxp_s8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv8i16")] + fn _svmaxp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svmaxp_s16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv4i32")] + fn _svmaxp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svmaxp_s32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smaxp.nxv2i64")] + fn _svmaxp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smaxp))] +pub fn svmaxp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svmaxp_s64_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv16i8")] + fn _svmaxp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svmaxp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svmaxp_u8_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv8i16")] + fn _svmaxp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svmaxp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svmaxp_u16_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv4i32")] + fn _svmaxp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svmaxp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svmaxp_u32_m(pg, op1, op2) +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umaxp.nxv2i64")] + fn _svmaxp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svmaxp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmaxp[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umaxp))] +pub fn svmaxp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svmaxp_u64_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv4f32" + )] + fn _svminnmp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminnmp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminnmp_f32_m(pg, op1, op2) +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fminnmp.nxv2f64" + )] + fn _svminnmp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminnmp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminnmp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminnmp))] +pub fn svminnmp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminnmp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_m(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv4f32")] + fn _svminp_f32_m(pg: svbool4_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t; + } + unsafe { _svminp_f32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f32_x(pg: svbool_t, op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + svminp_f32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_m(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.fminp.nxv2f64")] + fn _svminp_f64_m(pg: svbool2_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t; + } + unsafe { _svminp_f64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_f64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fminp))] +pub fn svminp_f64_x(pg: svbool_t, op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + svminp_f64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv16i8")] + fn _svminp_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_s8_m(pg, op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svminp_s8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv8i16")] + fn _svminp_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svminp_s16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv4i32")] + fn _svminp_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svminp_s32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sminp.nxv2i64")] + fn _svminp_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sminp))] +pub fn svminp_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svminp_s64_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv16i8")] + fn _svminp_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svminp_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svminp_u8_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv8i16")] + fn _svminp_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svminp_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svminp_u16_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv4i32")] + fn _svminp_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svminp_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svminp_u32_m(pg, op1, op2) +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uminp.nxv2i64")] + fn _svminp_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svminp_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svminp[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uminp))] +pub fn svminp_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svminp_u64_m(pg, op1, op2) +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv8i16" + )] + fn _svmla_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmla_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv4i32" + )] + fn _svmla_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmla_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mla.lane.nxv2i64" + )] + fn _svmla_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmla_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmla_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmla_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add, addend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mla, IMM_INDEX = 0))] +pub fn svmla_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmla_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv4i32" + )] + fn _svmlalb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb, IMM_INDEX = 0))] +pub fn svmlalb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalb.lane.nxv2i64" + )] + fn _svmlalb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv8i16")] + fn _svmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv4i32")] + fn _svmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalb.nxv2i64")] + fn _svmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalb))] +pub fn svmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv8i16")] + fn _svmlalb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv4i32")] + fn _svmlalb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalb.nxv2i64")] + fn _svmlalb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalb))] +pub fn svmlalb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv4i32" + )] + fn _svmlalt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlalt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt, IMM_INDEX = 0))] +pub fn svmlalt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlalt.lane.nxv2i64" + )] + fn _svmlalt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlalt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv8i16")] + fn _svmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_s16(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv4i32")] + fn _svmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_s32(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlalt.nxv2i64")] + fn _svmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_s64(op1, op2, op3) } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlalt))] +pub fn svmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv8i16")] + fn _svmlalt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlalt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlalt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv4i32")] + fn _svmlalt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlalt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlalt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlalt.nxv2i64")] + fn _svmlalt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlalt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlalt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlalt))] +pub fn svmlalt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlalt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv8i16" + )] + fn _svmls_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svmls_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv4i32" + )] + fn _svmls_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmls_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mls.lane.nxv2i64" + )] + fn _svmls_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmls_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u16( + op1: svuint16_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { + svmls_lane_s16::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u32( + op1: svuint32_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { + svmls_lane_s32::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract, minuend first"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mls, IMM_INDEX = 0))] +pub fn svmls_lane_u64( + op1: svuint64_t, + op2: svuint64_t, + op3: svuint64_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { + svmls_lane_s64::(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv4i32" + )] + fn _svmlslb_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslb_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb, IMM_INDEX = 0))] +pub fn svmlslb_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslb.lane.nxv2i64" + )] + fn _svmlslb_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslb_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv8i16")] + fn _svmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv4i32")] + fn _svmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslb.nxv2i64")] + fn _svmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslb))] +pub fn svmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv8i16")] + fn _svmlslb_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslb_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslb_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv4i32")] + fn _svmlslb_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslb_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslb.nxv2i64")] + fn _svmlslb_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslb))] +pub fn svmlslb_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslb_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u32( + op1: svuint32_t, + op2: svuint16_t, + op3: svuint16_t, +) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv4i32" + )] + fn _svmlslt_lane_u32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { + _svmlslt_lane_u32(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt, IMM_INDEX = 0))] +pub fn svmlslt_lane_u64( + op1: svuint64_t, + op2: svuint32_t, + op3: svuint32_t, +) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umlslt.lane.nxv2i64" + )] + fn _svmlslt_lane_u64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { + _svmlslt_lane_u64(op1.as_signed(), op2.as_signed(), op3.as_signed(), IMM_INDEX) + .as_unsigned() + } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv8i16")] + fn _svmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_s16(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv4i32")] + fn _svmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_s32(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smlslt.nxv2i64")] + fn _svmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_s64(op1, op2, op3) } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smlslt))] +pub fn svmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u16(op1: svuint16_t, op2: svuint8_t, op3: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv8i16")] + fn _svmlslt_u16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svmlslt_u16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u16(op1: svuint16_t, op2: svuint8_t, op3: u8) -> svuint16_t { + svmlslt_u16(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u32(op1: svuint32_t, op2: svuint16_t, op3: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv4i32")] + fn _svmlslt_u32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svmlslt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u32(op1: svuint32_t, op2: svuint16_t, op3: u16) -> svuint32_t { + svmlslt_u32(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_u64(op1: svuint64_t, op2: svuint32_t, op3: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umlslt.nxv2i64")] + fn _svmlslt_u64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svmlslt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmlslt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umlslt))] +pub fn svmlslt_n_u64(op1: svuint64_t, op2: svuint32_t, op3: u32) -> svuint64_t { + svmlslt_u64(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s16(op: svint8_t) -> svint16_t { + svshllb_n_s16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s32(op: svint16_t) -> svint32_t { + svshllb_n_s32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb))] +pub fn svmovlb_s64(op: svint32_t) -> svint64_t { + svshllb_n_s64::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u16(op: svuint8_t) -> svuint16_t { + svshllb_n_u16::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u32(op: svuint16_t) -> svuint32_t { + svshllb_n_u32::<0>(op) +} +#[doc = "Move long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb))] +pub fn svmovlb_u64(op: svuint32_t) -> svuint64_t { + svshllb_n_u64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s16(op: svint8_t) -> svint16_t { + svshllt_n_s16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s32(op: svint16_t) -> svint32_t { + svshllt_n_s32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt))] +pub fn svmovlt_s64(op: svint32_t) -> svint64_t { + svshllt_n_s64::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u16(op: svuint8_t) -> svuint16_t { + svshllt_n_u16::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u32(op: svuint16_t) -> svuint32_t { + svshllt_n_u32::<0>(op) +} +#[doc = "Move long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmovlt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt))] +pub fn svmovlt_u64(op: svuint32_t) -> svuint64_t { + svshllt_n_u64::<0>(op) +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv4f32" + )] + fn _svmul_lane_f32(op1: svfloat32_t, op2: svfloat32_t, imm_index: i32) -> svfloat32_t; + } + unsafe { _svmul_lane_f32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(fmul, IMM_INDEX = 0))] +pub fn svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.fmul.lane.nxv2f64" + )] + fn _svmul_lane_f64(op1: svfloat64_t, op2: svfloat64_t, imm_index: i32) -> svfloat64_t; + } + unsafe { _svmul_lane_f64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv8i16" + )] + fn _svmul_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svmul_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv4i32" + )] + fn _svmul_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmul_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.mul.lane.nxv2i64" + )] + fn _svmul_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmul_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe { svmul_lane_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe { svmul_lane_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmul_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(mul, IMM_INDEX = 0))] +pub fn svmul_lane_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe { svmul_lane_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv4i32" + )] + fn _svmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullb.lane.nxv2i64" + )] + fn _svmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv4i32" + )] + fn _svmullb_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullb_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullb, IMM_INDEX = 0) +)] +pub fn svmullb_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullb.lane.nxv2i64" + )] + fn _svmullb_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullb_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv8i16")] + fn _svmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_s16(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv4i32")] + fn _svmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_s32(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullb.nxv2i64")] + fn _svmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_s64(op1, op2) } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(smullb))] +pub fn svmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv8i16")] + fn _svmullb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv4i32")] + fn _svmullb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullb.nxv2i64")] + fn _svmullb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(umullb))] +pub fn svmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv4i32" + )] + fn _svmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(smullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.smullt.lane.nxv2i64" + )] + fn _svmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv4i32" + )] + fn _svmullt_lane_u32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svmullt_lane_u32(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt_lane[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr( + all(test, not(target_env = "msvc")), + assert_instr(umullt, IMM_INDEX = 0) +)] +pub fn svmullt_lane_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.umullt.lane.nxv2i64" + )] + fn _svmullt_lane_u64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svmullt_lane_u64(op1.as_signed(), op2.as_signed(), IMM_INDEX).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv8i16")] + fn _svmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_s16(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv4i32")] + fn _svmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_s32(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.smullt.nxv2i64")] + fn _svmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_s64(op1, op2) } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(smullt))] +pub fn svmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv8i16")] + fn _svmullt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svmullt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv4i32")] + fn _svmullt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svmullt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svmullt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.umullt.nxv2i64")] + fn _svmullt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svmullt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmullt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(umullt))] +pub fn svmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv16i8")] + fn _svnbsl_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svnbsl_s8(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svnbsl_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv8i16")] + fn _svnbsl_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svnbsl_s16(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svnbsl_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv4i32")] + fn _svnbsl_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svnbsl_s32(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svnbsl_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nbsl.nxv2i64")] + fn _svnbsl_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svnbsl_s64(op1, op2, op3) } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svnbsl_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u8(op1: svuint8_t, op2: svuint8_t, op3: svuint8_t) -> svuint8_t { + unsafe { svnbsl_s8(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u8(op1: svuint8_t, op2: svuint8_t, op3: u8) -> svuint8_t { + svnbsl_u8(op1, op2, svdup_n_u8(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u16(op1: svuint16_t, op2: svuint16_t, op3: svuint16_t) -> svuint16_t { + unsafe { svnbsl_s16(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u16(op1: svuint16_t, op2: svuint16_t, op3: u16) -> svuint16_t { + svnbsl_u16(op1, op2, svdup_n_u16(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe { svnbsl_s32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svnbsl_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe { svnbsl_s64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Bitwise select"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnbsl[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nbsl))] +pub fn svnbsl_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svnbsl_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv16i8")] + fn _svnmatch_s8(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svbool_t; + } + unsafe { _svnmatch_s8(pg, op1, op2) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_s16(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.nmatch.nxv8i16")] + fn _svnmatch_s16(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svbool8_t; + } + unsafe { _svnmatch_s16(pg.sve_into(), op1, op2).sve_into() } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u8(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svbool_t { + unsafe { svnmatch_s8(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Detect no matching elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmatch[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(nmatch))] +pub fn svnmatch_u16(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svbool_t { + unsafe { svnmatch_s16(pg, op1.as_signed(), op2.as_signed()) } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.pmul.nxv16i8")] + fn _svpmul_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmul_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmul[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmul))] +pub fn svpmul_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmul_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv16i8" + )] + fn _svpmullb_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullb_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullb_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv4i32" + )] + fn _svpmullb_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullb_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullb_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullb.pair.nxv2i64" + )] + fn _svpmullb_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullb_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb_pair[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullb_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullb_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullb))] +pub fn svpmullb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv16i8" + )] + fn _svpmullt_pair_u8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svpmullt_pair_u8(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u8(op1: svuint8_t, op2: u8) -> svuint8_t { + svpmullt_pair_u8(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv4i32" + )] + fn _svpmullt_pair_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svpmullt_pair_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u32(op1: svuint32_t, op2: u32) -> svuint32_t { + svpmullt_pair_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.pmullt.pair.nxv2i64" + )] + fn _svpmullt_pair_u64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svpmullt_pair_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt_pair[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_pair_n_u64(op1: svuint64_t, op2: u64) -> svuint64_t { + svpmullt_pair_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u8(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svpmullt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe { crate::intrinsics::transmute_unchecked(svpmullt_pair_u32(op1, op2)) } +} +#[doc = "Polynomial multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svpmullt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-aes")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(pmullt))] +pub fn svpmullt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svpmullt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv16i8")] + fn _svqabs_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqabs_s8_m(inactive, pg, op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqabs_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv8i16")] + fn _svqabs_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqabs_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqabs_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv4i32")] + fn _svqabs_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqabs_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqabs_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqabs.nxv2i64")] + fn _svqabs_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqabs_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(op, pg, op) +} +#[doc = "Saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqabs[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqabs))] +pub fn svqabs_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqabs_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv16i8")] + fn _svqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_s8_m(pg, op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv8i16")] + fn _svqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv4i32")] + fn _svqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqadd.nxv2i64")] + fn _svqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqadd))] +pub fn svqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv16i8")] + fn _svqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv8i16")] + fn _svqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv4i32")] + fn _svqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqadd.nxv2i64")] + fn _svqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqadd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqadd))] +pub fn svqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv16i8" + )] + fn _svqcadd_s8(op1: svint8_t, op2: svint8_t, imm_rotation: i32) -> svint8_t; + } + unsafe { _svqcadd_s8(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv8i16" + )] + fn _svqcadd_s16(op1: svint16_t, op2: svint16_t, imm_rotation: i32) -> svint16_t; + } + unsafe { _svqcadd_s16(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv4i32" + )] + fn _svqcadd_s32(op1: svint32_t, op2: svint32_t, imm_rotation: i32) -> svint32_t; + } + unsafe { _svqcadd_s32(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating complex add with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqcadd[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqcadd, IMM_ROTATION = 90))] +pub fn svqcadd_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert!(IMM_ROTATION == 90 || IMM_ROTATION == 270); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqcadd.x.nxv2i64" + )] + fn _svqcadd_s64(op1: svint64_t, op2: svint64_t, imm_rotation: i32) -> svint64_t; + } + unsafe { _svqcadd_s64(op1, op2, IMM_ROTATION) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv4i32" + )] + fn _svqdmlalb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb, IMM_INDEX = 0))] +pub fn svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.lane.nxv2i64" + )] + fn _svqdmlalb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv8i16" + )] + fn _svqdmlalb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv4i32" + )] + fn _svqdmlalb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalb.nxv2i64" + )] + fn _svqdmlalb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalb))] +pub fn svqdmlalb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv8i16" + )] + fn _svqdmlalbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv4i32" + )] + fn _svqdmlalbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalbt.nxv2i64" + )] + fn _svqdmlalbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalbt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalbt))] +pub fn svqdmlalbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv4i32" + )] + fn _svqdmlalt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlalt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt, IMM_INDEX = 0))] +pub fn svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.lane.nxv2i64" + )] + fn _svqdmlalt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlalt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv8i16" + )] + fn _svqdmlalt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlalt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlalt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv4i32" + )] + fn _svqdmlalt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlalt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlalt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlalt.nxv2i64" + )] + fn _svqdmlalt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlalt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-add long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlalt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlalt))] +pub fn svqdmlalt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlalt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv4i32" + )] + fn _svqdmlslb_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslb_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb, IMM_INDEX = 0))] +pub fn svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.lane.nxv2i64" + )] + fn _svqdmlslb_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslb_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv8i16" + )] + fn _svqdmlslb_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslb_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslb_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv4i32" + )] + fn _svqdmlslb_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslb_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslb_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslb.nxv2i64" + )] + fn _svqdmlslb_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslb_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslb))] +pub fn svqdmlslb_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslb_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv8i16" + )] + fn _svqdmlslbt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslbt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslbt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv4i32" + )] + fn _svqdmlslbt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslbt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslbt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslbt.nxv2i64" + )] + fn _svqdmlslbt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslbt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (bottom × top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslbt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslbt))] +pub fn svqdmlslbt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslbt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv4i32" + )] + fn _svqdmlslt_lane_s32( + op1: svint32_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqdmlslt_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt, IMM_INDEX = 0))] +pub fn svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.lane.nxv2i64" + )] + fn _svqdmlslt_lane_s64( + op1: svint64_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqdmlslt_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv8i16" + )] + fn _svqdmlslt_s16(op1: svint16_t, op2: svint8_t, op3: svint8_t) -> svint16_t; + } + unsafe { _svqdmlslt_s16(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s16(op1: svint16_t, op2: svint8_t, op3: i8) -> svint16_t { + svqdmlslt_s16(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv4i32" + )] + fn _svqdmlslt_s32(op1: svint32_t, op2: svint16_t, op3: svint16_t) -> svint32_t; + } + unsafe { _svqdmlslt_s32(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s32(op1: svint32_t, op2: svint16_t, op3: i16) -> svint32_t { + svqdmlslt_s32(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmlslt.nxv2i64" + )] + fn _svqdmlslt_s64(op1: svint64_t, op2: svint32_t, op3: svint32_t) -> svint64_t; + } + unsafe { _svqdmlslt_s64(op1, op2, op3) } +} +#[doc = "Saturating doubling multiply-subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmlslt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmlslt))] +pub fn svqdmlslt_n_s64(op1: svint64_t, op2: svint32_t, op3: i32) -> svint64_t { + svqdmlslt_s64(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv8i16" + )] + fn _svqdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv4i32" + )] + fn _svqdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh, IMM_INDEX = 0))] +pub fn svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.lane.nxv2i64" + )] + fn _svqdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv16i8" + )] + fn _svqdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqdmulh_s8(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv8i16" + )] + fn _svqdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqdmulh_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv4i32" + )] + fn _svqdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqdmulh_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmulh.nxv2i64" + )] + fn _svqdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqdmulh_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmulh[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmulh))] +pub fn svqdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv4i32" + )] + fn _svqdmullb_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullb_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb, IMM_INDEX = 0))] +pub fn svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.lane.nxv2i64" + )] + fn _svqdmullb_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullb_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv8i16" + )] + fn _svqdmullb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullb_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv4i32" + )] + fn _svqdmullb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullb_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullb.nxv2i64" + )] + fn _svqdmullb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullb_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullb))] +pub fn svqdmullb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv4i32" + )] + fn _svqdmullt_lane_s32(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqdmullt_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt, IMM_INDEX = 0))] +pub fn svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.lane.nxv2i64" + )] + fn _svqdmullt_lane_s64(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqdmullt_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv8i16" + )] + fn _svqdmullt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svqdmullt_s16(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svqdmullt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv4i32" + )] + fn _svqdmullt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svqdmullt_s32(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svqdmullt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqdmullt.nxv2i64" + )] + fn _svqdmullt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svqdmullt_s64(op1, op2) } +} +#[doc = "Saturating doubling multiply long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqdmullt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqdmullt))] +pub fn svqdmullt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svqdmullt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv16i8")] + fn _svqneg_s8_m(inactive: svint8_t, pg: svbool_t, op: svint8_t) -> svint8_t; + } + unsafe { _svqneg_s8_m(inactive, pg, op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_x(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s8_z(pg: svbool_t, op: svint8_t) -> svint8_t { + svqneg_s8_m(svdup_n_s8(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_m(inactive: svint16_t, pg: svbool_t, op: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv8i16")] + fn _svqneg_s16_m(inactive: svint16_t, pg: svbool8_t, op: svint16_t) -> svint16_t; + } + unsafe { _svqneg_s16_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_x(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s16_z(pg: svbool_t, op: svint16_t) -> svint16_t { + svqneg_s16_m(svdup_n_s16(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_m(inactive: svint32_t, pg: svbool_t, op: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv4i32")] + fn _svqneg_s32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svqneg_s32_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_x(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s32_z(pg: svbool_t, op: svint32_t) -> svint32_t { + svqneg_s32_m(svdup_n_s32(0), pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_m(inactive: svint64_t, pg: svbool_t, op: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqneg.nxv2i64")] + fn _svqneg_s64_m(inactive: svint64_t, pg: svbool2_t, op: svint64_t) -> svint64_t; + } + unsafe { _svqneg_s64_m(inactive, pg.sve_into(), op) } +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_x(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(op, pg, op) +} +#[doc = "Saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqneg[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqneg))] +pub fn svqneg_s64_z(pg: svbool_t, op: svint64_t) -> svint64_t { + svqneg_s64_m(svdup_n_s64(0), pg, op) +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=3); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16" + )] + fn _svqrdcmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_lane_s16(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_INDEX = 0, IMM_ROTATION = 90))] +pub fn svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=1); + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32" + )] + fn _svqrdcmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_index: i32, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_lane_s32(op1, op2, op3, IMM_INDEX, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, +) -> svint8_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv16i8" + )] + fn _svqrdcmlah_s8( + op1: svint8_t, + op2: svint8_t, + op3: svint8_t, + imm_rotation: i32, + ) -> svint8_t; + } + unsafe { _svqrdcmlah_s8(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv8i16" + )] + fn _svqrdcmlah_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + imm_rotation: i32, + ) -> svint16_t; + } + unsafe { _svqrdcmlah_s16(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv4i32" + )] + fn _svqrdcmlah_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + imm_rotation: i32, + ) -> svint32_t; + } + unsafe { _svqrdcmlah_s32(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling complex multiply-add high with rotate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdcmlah[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdcmlah, IMM_ROTATION = 90))] +pub fn svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert!( + IMM_ROTATION == 0 || IMM_ROTATION == 90 || IMM_ROTATION == 180 || IMM_ROTATION == 270 + ); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdcmlah.x.nxv2i64" + )] + fn _svqrdcmlah_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + imm_rotation: i32, + ) -> svint64_t; + } + unsafe { _svqrdcmlah_s64(op1, op2, op3, IMM_ROTATION) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv8i16" + )] + fn _svqrdmlah_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlah_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv4i32" + )] + fn _svqrdmlah_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlah_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah, IMM_INDEX = 0))] +pub fn svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.lane.nxv2i64" + )] + fn _svqrdmlah_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlah_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv16i8" + )] + fn _svqrdmlah_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlah_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlah_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv8i16" + )] + fn _svqrdmlah_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlah_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlah_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv4i32" + )] + fn _svqrdmlah_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlah_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlah_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlah.nxv2i64" + )] + fn _svqrdmlah_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlah_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-add high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlah[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +pub fn svqrdmlah_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlah_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, +) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16" + )] + fn _svqrdmlsh_lane_s16( + op1: svint16_t, + op2: svint16_t, + op3: svint16_t, + IMM_INDEX: i32, + ) -> svint16_t; + } + unsafe { _svqrdmlsh_lane_s16(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, +) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32" + )] + fn _svqrdmlsh_lane_s32( + op1: svint32_t, + op2: svint32_t, + op3: svint32_t, + IMM_INDEX: i32, + ) -> svint32_t; + } + unsafe { _svqrdmlsh_lane_s32(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh, IMM_INDEX = 0))] +pub fn svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, +) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64" + )] + fn _svqrdmlsh_lane_s64( + op1: svint64_t, + op2: svint64_t, + op3: svint64_t, + IMM_INDEX: i32, + ) -> svint64_t; + } + unsafe { _svqrdmlsh_lane_s64(op1, op2, op3, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv16i8" + )] + fn _svqrdmlsh_s8(op1: svint8_t, op2: svint8_t, op3: svint8_t) -> svint8_t; + } + unsafe { _svqrdmlsh_s8(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s8(op1: svint8_t, op2: svint8_t, op3: i8) -> svint8_t { + svqrdmlsh_s8(op1, op2, svdup_n_s8(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv8i16" + )] + fn _svqrdmlsh_s16(op1: svint16_t, op2: svint16_t, op3: svint16_t) -> svint16_t; + } + unsafe { _svqrdmlsh_s16(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s16(op1: svint16_t, op2: svint16_t, op3: i16) -> svint16_t { + svqrdmlsh_s16(op1, op2, svdup_n_s16(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv4i32" + )] + fn _svqrdmlsh_s32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svqrdmlsh_s32(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s32(op1: svint32_t, op2: svint32_t, op3: i32) -> svint32_t { + svqrdmlsh_s32(op1, op2, svdup_n_s32(op3)) +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmlsh.nxv2i64" + )] + fn _svqrdmlsh_s64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svqrdmlsh_s64(op1, op2, op3) } +} +#[doc = "Saturating rounding doubling multiply-subtract high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmlsh[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +pub fn svqrdmlsh_n_s64(op1: svint64_t, op2: svint64_t, op3: i64) -> svint64_t { + svqrdmlsh_s64(op1, op2, svdup_n_s64(op3)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM_INDEX, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv8i16" + )] + fn _svqrdmulh_lane_s16(op1: svint16_t, op2: svint16_t, imm_index: i32) -> svint16_t; + } + unsafe { _svqrdmulh_lane_s16(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM_INDEX, 0..=3); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv4i32" + )] + fn _svqrdmulh_lane_s32(op1: svint32_t, op2: svint32_t, imm_index: i32) -> svint32_t; + } + unsafe { _svqrdmulh_lane_s32(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh_lane[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh, IMM_INDEX = 0))] +pub fn svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM_INDEX, 0..=1); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.lane.nxv2i64" + )] + fn _svqrdmulh_lane_s64(op1: svint64_t, op2: svint64_t, imm_index: i32) -> svint64_t; + } + unsafe { _svqrdmulh_lane_s64(op1, op2, IMM_INDEX) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv16i8" + )] + fn _svqrdmulh_s8(op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrdmulh_s8(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s8(op1: svint8_t, op2: i8) -> svint8_t { + svqrdmulh_s8(op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv8i16" + )] + fn _svqrdmulh_s16(op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrdmulh_s16(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s16(op1: svint16_t, op2: i16) -> svint16_t { + svqrdmulh_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv4i32" + )] + fn _svqrdmulh_s32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrdmulh_s32(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s32(op1: svint32_t, op2: i32) -> svint32_t { + svqrdmulh_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrdmulh.nxv2i64" + )] + fn _svqrdmulh_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrdmulh_s64(op1, op2) } +} +#[doc = "Saturating rounding doubling multiply high"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrdmulh[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrdmulh))] +pub fn svqrdmulh_n_s64(op1: svint64_t, op2: i64) -> svint64_t { + svqrdmulh_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv16i8")] + fn _svqrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv8i16")] + fn _svqrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv4i32")] + fn _svqrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqrshl.nxv2i64")] + fn _svqrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshl))] +pub fn svqrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv16i8")] + fn _svqrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv8i16")] + fn _svqrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv4i32")] + fn _svqrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqrshl.nxv2i64")] + fn _svqrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshl[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshl))] +pub fn svqrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv8i16" + )] + fn _svqrshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv4i32" + )] + fn _svqrshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnb, IMM2 = 1))] +pub fn svqrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnb.nxv2i64" + )] + fn _svqrshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv8i16" + )] + fn _svqrshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv4i32" + )] + fn _svqrshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqrshrnt, IMM2 = 1))] +pub fn svqrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqrshrnt.nxv2i64" + )] + fn _svqrshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv8i16" + )] + fn _svqrshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv4i32" + )] + fn _svqrshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunb, IMM2 = 1))] +pub fn svqrshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunb.nxv2i64" + )] + fn _svqrshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv8i16" + )] + fn _svqrshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqrshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv4i32" + )] + fn _svqrshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqrshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating rounding shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqrshrunt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqrshrunt, IMM2 = 1))] +pub fn svqrshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqrshrunt.nxv2i64" + )] + fn _svqrshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqrshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv16i8")] + fn _svqshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_s8_m(pg, op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv8i16")] + fn _svqshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv4i32")] + fn _svqshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshl.nxv2i64")] + fn _svqshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshl))] +pub fn svqshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv16i8")] + fn _svqshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svqshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svqshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv8i16")] + fn _svqshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svqshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svqshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv4i32")] + fn _svqshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svqshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svqshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqshl.nxv2i64")] + fn _svqshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, op1, op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svqshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshl[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshl))] +pub fn svqshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svqshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t) -> svuint8_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv16i8")] + fn _svqshlu_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshlu_n_s8_m(pg, op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_x(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s8_z(pg: svbool_t, op1: svint8_t) -> svuint8_t { + svqshlu_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_m(pg: svbool_t, op1: svint16_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv8i16")] + fn _svqshlu_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshlu_n_s16_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_x(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s16_z(pg: svbool_t, op1: svint16_t) -> svuint16_t { + svqshlu_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_m(pg: svbool_t, op1: svint32_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv4i32")] + fn _svqshlu_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshlu_n_s32_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_x(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s32_z(pg: svbool_t, op1: svint32_t) -> svuint32_t { + svqshlu_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_m(pg: svbool_t, op1: svint64_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqshlu.nxv2i64")] + fn _svqshlu_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svqshlu_n_s64_m(pg.sve_into(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_x(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, op1) +} +#[doc = "Saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshlu[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshlu, IMM2 = 0))] +pub fn svqshlu_n_s64_z(pg: svbool_t, op1: svint64_t) -> svuint64_t { + svqshlu_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv8i16" + )] + fn _svqshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_s16(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv4i32" + )] + fn _svqshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_s32(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnb.nxv2i64" + )] + fn _svqshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_s64(op1, IMM2) } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv8i16" + )] + fn _svqshrnb_n_u16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv4i32" + )] + fn _svqshrnb_n_u32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnb, IMM2 = 1))] +pub fn svqshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnb.nxv2i64" + )] + fn _svqshrnb_n_u64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv8i16" + )] + fn _svqshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv4i32" + )] + fn _svqshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrnt.nxv2i64" + )] + fn _svqshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv8i16" + )] + fn _svqshrnt_n_u16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrnt_n_u16(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv4i32" + )] + fn _svqshrnt_n_u32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrnt_n_u32(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqshrnt, IMM2 = 1))] +pub fn svqshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uqshrnt.nxv2i64" + )] + fn _svqshrnt_n_u64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrnt_n_u64(even.as_signed(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s16(op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv8i16" + )] + fn _svqshrunb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunb_n_s16(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s32(op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv4i32" + )] + fn _svqshrunb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunb_n_s32(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunb, IMM2 = 1))] +pub fn svqshrunb_n_s64(op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunb.nxv2i64" + )] + fn _svqshrunb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunb_n_s64(op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s16(even: svuint8_t, op1: svint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv8i16" + )] + fn _svqshrunt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svqshrunt_n_s16(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s32(even: svuint16_t, op1: svint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv4i32" + )] + fn _svqshrunt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svqshrunt_n_s32(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating shift right unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqshrunt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqshrunt, IMM2 = 1))] +pub fn svqshrunt_n_s64(even: svuint32_t, op1: svint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqshrunt.nxv2i64" + )] + fn _svqshrunt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svqshrunt_n_s64(even.as_signed(), op1, IMM2).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv16i8")] + fn _svqsub_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsub_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsub_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv8i16")] + fn _svqsub_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsub_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsub_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv4i32")] + fn _svqsub_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsub_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsub_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsub.nxv2i64")] + fn _svqsub_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsub_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsub))] +pub fn svqsub_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsub_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv16i8")] + fn _svqsub_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsub_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsub_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsub_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv8i16")] + fn _svqsub_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsub_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsub_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsub_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv4i32")] + fn _svqsub_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsub_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsub_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsub_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsub.nxv2i64")] + fn _svqsub_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsub_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsub_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsub[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsub))] +pub fn svqsub_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsub_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv16i8")] + fn _svqsubr_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_s8_m(pg, op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svqsubr_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svqsubr_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv8i16")] + fn _svqsubr_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svqsubr_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svqsubr_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv4i32")] + fn _svqsubr_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svqsubr_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svqsubr_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqsubr.nxv2i64")] + fn _svqsubr_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svqsubr_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqsubr))] +pub fn svqsubr_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svqsubr_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv16i8")] + fn _svqsubr_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svqsubr_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svqsubr_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svqsubr_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv8i16")] + fn _svqsubr_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svqsubr_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svqsubr_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svqsubr_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv4i32")] + fn _svqsubr_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svqsubr_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svqsubr_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svqsubr_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqsubr.nxv2i64")] + fn _svqsubr_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svqsubr_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, op1, op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svqsubr_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating subtract reversed"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqsubr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqsubr))] +pub fn svqsubr_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svqsubr_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s16(op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv8i16")] + fn _svqxtnb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_s16(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s32(op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv4i32")] + fn _svqxtnb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_s32(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnb))] +pub fn svqxtnb_s64(op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnb.nxv2i64")] + fn _svqxtnb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_s64(op) } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u16(op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv8i16")] + fn _svqxtnb_u16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnb_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u32(op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv4i32")] + fn _svqxtnb_u32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnb_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnb))] +pub fn svqxtnb_u64(op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnb.nxv2i64")] + fn _svqxtnb_u64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnb_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv8i16")] + fn _svqxtnt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_s16(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv4i32")] + fn _svqxtnt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_s32(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtnt))] +pub fn svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sqxtnt.nxv2i64")] + fn _svqxtnt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_s64(even, op) } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u16(even: svuint8_t, op: svuint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv8i16")] + fn _svqxtnt_u16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtnt_u16(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u32(even: svuint16_t, op: svuint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv4i32")] + fn _svqxtnt_u32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtnt_u32(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtnt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uqxtnt))] +pub fn svqxtnt_u64(even: svuint32_t, op: svuint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.uqxtnt.nxv2i64")] + fn _svqxtnt_u64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtnt_u64(even.as_signed(), op.as_signed()).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s16(op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv8i16" + )] + fn _svqxtunb_s16(op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunb_s16(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s32(op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv4i32" + )] + fn _svqxtunb_s32(op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunb_s32(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunb))] +pub fn svqxtunb_s64(op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunb.nxv2i64" + )] + fn _svqxtunb_s64(op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunb_s64(op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s16(even: svuint8_t, op: svint16_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv8i16" + )] + fn _svqxtunt_s16(even: svint8_t, op: svint16_t) -> svint8_t; + } + unsafe { _svqxtunt_s16(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s32(even: svuint16_t, op: svint32_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv4i32" + )] + fn _svqxtunt_s32(even: svint16_t, op: svint32_t) -> svint16_t; + } + unsafe { _svqxtunt_s32(even.as_signed(), op).as_unsigned() } +} +#[doc = "Saturating extract unsigned narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svqxtunt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sqxtunt))] +pub fn svqxtunt_s64(even: svuint32_t, op: svint64_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sqxtunt.nxv2i64" + )] + fn _svqxtunt_s64(even: svint32_t, op: svint64_t) -> svint32_t; + } + unsafe { _svqxtunt_s64(even.as_signed(), op).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv8i16" + )] + fn _svraddhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnb_s16(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svraddhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv4i32" + )] + fn _svraddhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnb_s32(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svraddhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnb.nxv2i64" + )] + fn _svraddhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnb_s64(op1, op2) } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svraddhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnb))] +pub fn svraddhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv8i16" + )] + fn _svraddhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svraddhnt_s16(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svraddhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv4i32" + )] + fn _svraddhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svraddhnt_s32(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svraddhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.raddhnt.nxv2i64" + )] + fn _svraddhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svraddhnt_s64(even, op1, op2) } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svraddhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svraddhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svraddhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svraddhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svraddhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svraddhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding add narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svraddhnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(raddhnt))] +pub fn svraddhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svraddhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rax1")] + fn _svrax1_s64(op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrax1_s64(op1, op2) } +} +#[doc = "Bitwise rotate left by 1 and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrax1[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-sha3")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rax1))] +pub fn svrax1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe { svrax1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urecpe.nxv4i32")] + fn _svrecpe_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrecpe_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(op, pg, op) +} +#[doc = "Reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urecpe))] +pub fn svrecpe_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrecpe_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv16i8")] + fn _svrhadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_s8_m(pg, op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrhadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrhadd_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv8i16")] + fn _svrhadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrhadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrhadd_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv4i32")] + fn _svrhadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrhadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrhadd_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srhadd.nxv2i64")] + fn _svrhadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrhadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srhadd))] +pub fn svrhadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrhadd_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv16i8")] + fn _svrhadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrhadd_u8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + svrhadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t { + svrhadd_u8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv8i16")] + fn _svrhadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrhadd_u16_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + svrhadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t { + svrhadd_u16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv4i32")] + fn _svrhadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrhadd_u32_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + svrhadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t { + svrhadd_u32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urhadd.nxv2i64")] + fn _svrhadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrhadd_u64_m(pg.sve_into(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, op1, op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + svrhadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrhadd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urhadd))] +pub fn svrhadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t { + svrhadd_u64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv16i8")] + fn _svrshl_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_s8_m(pg, op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t { + svrshl_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t { + svrshl_s8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv8i16")] + fn _svrshl_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_s16_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t { + svrshl_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t { + svrshl_s16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv4i32")] + fn _svrshl_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_s32_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t { + svrshl_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t { + svrshl_s32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshl.nxv2i64")] + fn _svrshl_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_s64_m(pg.sve_into(), op1, op2) } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t { + svrshl_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshl))] +pub fn svrshl_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t { + svrshl_s64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv16i8")] + fn _svrshl_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svrshl_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svrshl_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svrshl_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv8i16")] + fn _svrshl_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svrshl_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svrshl_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svrshl_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv4i32")] + fn _svrshl_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svrshl_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svrshl_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svrshl_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshl.nxv2i64")] + fn _svrshl_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svrshl_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, op1, op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svrshl_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshl[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshl))] +pub fn svrshl_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svrshl_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_m(pg: svbool_t, op1: svint8_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv16i8")] + fn _svrshr_n_s8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_s8_m(pg, op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_x(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s8_z(pg: svbool_t, op1: svint8_t) -> svint8_t { + svrshr_n_s8_m::(pg, svsel_s8(pg, op1, svdup_n_s8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_m(pg: svbool_t, op1: svint16_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv8i16")] + fn _svrshr_n_s16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_s16_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_x(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s16_z(pg: svbool_t, op1: svint16_t) -> svint16_t { + svrshr_n_s16_m::(pg, svsel_s16(pg, op1, svdup_n_s16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_m(pg: svbool_t, op1: svint32_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv4i32")] + fn _svrshr_n_s32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_s32_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_x(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s32_z(pg: svbool_t, op1: svint32_t) -> svint32_t { + svrshr_n_s32_m::(pg, svsel_s32(pg, op1, svdup_n_s32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_m(pg: svbool_t, op1: svint64_t) -> svint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srshr.nxv2i64")] + fn _svrshr_n_s64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_s64_m(pg.sve_into(), op1, IMM2) } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_x(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srshr, IMM2 = 1))] +pub fn svrshr_n_s64_z(pg: svbool_t, op1: svint64_t) -> svint64_t { + svrshr_n_s64_m::(pg, svsel_s64(pg, op1, svdup_n_s64(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_m(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv16i8")] + fn _svrshr_n_u8_m(pg: svbool_t, op1: svint8_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshr_n_u8_m(pg, op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_x(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u8_z(pg: svbool_t, op1: svuint8_t) -> svuint8_t { + svrshr_n_u8_m::(pg, svsel_u8(pg, op1, svdup_n_u8(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_m(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv8i16")] + fn _svrshr_n_u16_m(pg: svbool8_t, op1: svint16_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshr_n_u16_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_x(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u16_z(pg: svbool_t, op1: svuint16_t) -> svuint16_t { + svrshr_n_u16_m::(pg, svsel_u16(pg, op1, svdup_n_u16(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_m(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv4i32")] + fn _svrshr_n_u32_m(pg: svbool4_t, op1: svint32_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshr_n_u32_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_x(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u32_z(pg: svbool_t, op1: svuint32_t) -> svuint32_t { + svrshr_n_u32_m::(pg, svsel_u32(pg, op1, svdup_n_u32(0))) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_m(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + static_assert_range!(IMM2, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.urshr.nxv2i64")] + fn _svrshr_n_u64_m(pg: svbool2_t, op1: svint64_t, imm2: i32) -> svint64_t; + } + unsafe { _svrshr_n_u64_m(pg.sve_into(), op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_x(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, op1) +} +#[doc = "Rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshr[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(urshr, IMM2 = 1))] +pub fn svrshr_n_u64_z(pg: svbool_t, op1: svuint64_t) -> svuint64_t { + svrshr_n_u64_m::(pg, svsel_u64(pg, op1, svdup_n_u64(0))) +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv8i16")] + fn _svrshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnb_n_s16(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv4i32")] + fn _svrshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnb_n_s32(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnb.nxv2i64")] + fn _svrshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnb_n_s64(op1, IMM2) } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnb, IMM2 = 1))] +pub fn svrshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv8i16")] + fn _svrshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svrshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv4i32")] + fn _svrshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svrshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.rshrnt.nxv2i64")] + fn _svrshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svrshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svrshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svrshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Rounding shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrshrnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rshrnt, IMM2 = 1))] +pub fn svrshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svrshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_m(inactive: svuint32_t, pg: svbool_t, op: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ursqrte.nxv4i32" + )] + fn _svrsqrte_u32_m(inactive: svint32_t, pg: svbool4_t, op: svint32_t) -> svint32_t; + } + unsafe { _svrsqrte_u32_m(inactive.as_signed(), pg.sve_into(), op.as_signed()).as_unsigned() } +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_x(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(op, pg, op) +} +#[doc = "Reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursqrte))] +pub fn svrsqrte_u32_z(pg: svbool_t, op: svuint32_t) -> svuint32_t { + svrsqrte_u32_m(svdup_n_u32(0), pg, op) +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv16i8")] + fn _svrsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv8i16")] + fn _svrsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv4i32")] + fn _svrsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(srsra, IMM3 = 1))] +pub fn svrsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.srsra.nxv2i64")] + fn _svrsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv16i8")] + fn _svrsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svrsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv8i16")] + fn _svrsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svrsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv4i32")] + fn _svrsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svrsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsra[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ursra, IMM3 = 1))] +pub fn svrsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ursra.nxv2i64")] + fn _svrsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svrsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv8i16" + )] + fn _svrsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnb_s16(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv4i32" + )] + fn _svrsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnb_s32(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnb.nxv2i64" + )] + fn _svrsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnb_s64(op1, op2) } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnb))] +pub fn svrsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv8i16" + )] + fn _svrsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svrsubhnt_s16(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svrsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv4i32" + )] + fn _svrsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svrsubhnt_s32(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svrsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.rsubhnt.nxv2i64" + )] + fn _svrsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svrsubhnt_s64(even, op1, op2) } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svrsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svrsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svrsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svrsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svrsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svrsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Rounding subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsubhnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(rsubhnt))] +pub fn svrsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svrsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv4i32")] + fn _svsbclb_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclb_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclb_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclb.nxv2i64")] + fn _svsbclb_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclb_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclb))] +pub fn svsbclb_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclb_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u32(op1: svuint32_t, op2: svuint32_t, op3: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv4i32")] + fn _svsbclt_u32(op1: svint32_t, op2: svint32_t, op3: svint32_t) -> svint32_t; + } + unsafe { _svsbclt_u32(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u32(op1: svuint32_t, op2: svuint32_t, op3: u32) -> svuint32_t { + svsbclt_u32(op1, op2, svdup_n_u32(op3)) +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_u64(op1: svuint64_t, op2: svuint64_t, op3: svuint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sbclt.nxv2i64")] + fn _svsbclt_u64(op1: svint64_t, op2: svint64_t, op3: svint64_t) -> svint64_t; + } + unsafe { _svsbclt_u64(op1.as_signed(), op2.as_signed(), op3.as_signed()).as_unsigned() } +} +#[doc = "Subtract with borrow long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsbclt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sbclt))] +pub fn svsbclt_n_u64(op1: svuint64_t, op2: svuint64_t, op3: u64) -> svuint64_t { + svsbclt_u64(op1, op2, svdup_n_u64(op3)) +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv8i16")] + fn _svshllb_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv4i32")] + fn _svshllb_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllb, IMM2 = 0))] +pub fn svshllb_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllb.nxv2i64")] + fn _svshllb_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv8i16")] + fn _svshllb_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllb_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv4i32")] + fn _svshllb_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllb_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllb, IMM2 = 0))] +pub fn svshllb_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllb.nxv2i64")] + fn _svshllb_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllb_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s16(op1: svint8_t) -> svint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv8i16")] + fn _svshllt_n_s16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_s16(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s32(op1: svint16_t) -> svint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv4i32")] + fn _svshllt_n_s32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_s32(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sshllt, IMM2 = 0))] +pub fn svshllt_n_s64(op1: svint32_t) -> svint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sshllt.nxv2i64")] + fn _svshllt_n_s64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_s64(op1, IMM2) } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u16(op1: svuint8_t) -> svuint16_t { + static_assert_range!(IMM2, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv8i16")] + fn _svshllt_n_u16(op1: svint8_t, imm2: i32) -> svint16_t; + } + unsafe { _svshllt_n_u16(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u32(op1: svuint16_t) -> svuint32_t { + static_assert_range!(IMM2, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv4i32")] + fn _svshllt_n_u32(op1: svint16_t, imm2: i32) -> svint32_t; + } + unsafe { _svshllt_n_u32(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift left long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshllt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ushllt, IMM2 = 0))] +pub fn svshllt_n_u64(op1: svuint32_t) -> svuint64_t { + static_assert_range!(IMM2, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ushllt.nxv2i64")] + fn _svshllt_n_u64(op1: svint32_t, imm2: i32) -> svint64_t; + } + unsafe { _svshllt_n_u64(op1.as_signed(), IMM2).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s16(op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv8i16")] + fn _svshrnb_n_s16(op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnb_n_s16(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s32(op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv4i32")] + fn _svshrnb_n_s32(op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnb_n_s32(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_s64(op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnb.nxv2i64")] + fn _svshrnb_n_s64(op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnb_n_s64(op1, IMM2) } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u16(op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnb_n_s16::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u32(op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnb_n_s32::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnb, IMM2 = 1))] +pub fn svshrnb_n_u64(op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnb_n_s64::(op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s16(even: svint8_t, op1: svint16_t) -> svint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv8i16")] + fn _svshrnt_n_s16(even: svint8_t, op1: svint16_t, imm2: i32) -> svint8_t; + } + unsafe { _svshrnt_n_s16(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s32(even: svint16_t, op1: svint32_t) -> svint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv4i32")] + fn _svshrnt_n_s32(even: svint16_t, op1: svint32_t, imm2: i32) -> svint16_t; + } + unsafe { _svshrnt_n_s32(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_s64(even: svint32_t, op1: svint64_t) -> svint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.shrnt.nxv2i64")] + fn _svshrnt_n_s64(even: svint32_t, op1: svint64_t, imm2: i32) -> svint32_t; + } + unsafe { _svshrnt_n_s64(even, op1, IMM2) } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u16(even: svuint8_t, op1: svuint16_t) -> svuint8_t { + static_assert_range!(IMM2, 1..=8); + unsafe { svshrnt_n_s16::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u32(even: svuint16_t, op1: svuint32_t) -> svuint16_t { + static_assert_range!(IMM2, 1..=16); + unsafe { svshrnt_n_s32::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift right narrow (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svshrnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(shrnt, IMM2 = 1))] +pub fn svshrnt_n_u64(even: svuint32_t, op1: svuint64_t) -> svuint32_t { + static_assert_range!(IMM2, 1..=32); + unsafe { svshrnt_n_s64::(even.as_signed(), op1.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv16i8")] + fn _svsli_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsli_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv8i16")] + fn _svsli_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsli_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv4i32")] + fn _svsli_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsli_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sli.nxv2i64")] + fn _svsli_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsli_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 0..=7); + unsafe { svsli_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 0..=15); + unsafe { svsli_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 0..=31); + unsafe { svsli_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsli[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sli, IMM3 = 0))] +pub fn svsli_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 0..=63); + unsafe { svsli_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 encryption and decryption"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4e[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4e))] +pub fn svsm4e_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4e")] + fn _svsm4e_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4e_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "SM4 key updates"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsm4ekey[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2,sve2-sm4")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sm4ekey))] +pub fn svsm4ekey_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sm4ekey")] + fn _svsm4ekey_u32(op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsm4ekey_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_m(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv16i8")] + fn _svsqadd_u8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svsqadd_u8_m(pg, op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_m(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_x(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_x(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u8_z(pg: svbool_t, op1: svuint8_t, op2: svint8_t) -> svuint8_t { + svsqadd_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: i8) -> svuint8_t { + svsqadd_u8_z(pg, op1, svdup_n_s8(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_m(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv8i16")] + fn _svsqadd_u16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svsqadd_u16_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_m(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_x(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_x(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u16_z(pg: svbool_t, op1: svuint16_t, op2: svint16_t) -> svuint16_t { + svsqadd_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: i16) -> svuint16_t { + svsqadd_u16_z(pg, op1, svdup_n_s16(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_m(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv4i32")] + fn _svsqadd_u32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svsqadd_u32_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_m(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_x(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_x(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u32_z(pg: svbool_t, op1: svuint32_t, op2: svint32_t) -> svuint32_t { + svsqadd_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: i32) -> svuint32_t { + svsqadd_u32_z(pg, op1, svdup_n_s32(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_m(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usqadd.nxv2i64")] + fn _svsqadd_u64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svsqadd_u64_m(pg.sve_into(), op1.as_signed(), op2).as_unsigned() } +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_m(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_x(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, op1, op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_x(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_u64_z(pg: svbool_t, op1: svuint64_t, op2: svint64_t) -> svuint64_t { + svsqadd_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2) +} +#[doc = "Saturating add with signed addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsqadd[_n_u64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usqadd))] +pub fn svsqadd_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: i64) -> svuint64_t { + svsqadd_u64_z(pg, op1, svdup_n_s64(op2)) +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv16i8")] + fn _svsra_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv8i16")] + fn _svsra_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv4i32")] + fn _svsra_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssra, IMM3 = 1))] +pub fn svsra_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssra.nxv2i64")] + fn _svsra_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv16i8")] + fn _svsra_n_u8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsra_n_u8(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv8i16")] + fn _svsra_n_u16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsra_n_u16(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv4i32")] + fn _svsra_n_u32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsra_n_u32(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsra[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usra, IMM3 = 1))] +pub fn svsra_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usra.nxv2i64")] + fn _svsra_n_u64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsra_n_u64(op1.as_signed(), op2.as_signed(), IMM3).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv16i8")] + fn _svsri_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svsri_n_s8(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv8i16")] + fn _svsri_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svsri_n_s16(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv4i32")] + fn _svsri_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svsri_n_s32(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.sri.nxv2i64")] + fn _svsri_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svsri_n_s64(op1, op2, IMM3) } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svsri_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svsri_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svsri_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsri[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sri, IMM3 = 1))] +pub fn svsri_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svsri_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2f64" + )] + fn _svstnt1_scatter_s64index_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_f64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i64" + )] + fn _svstnt1_scatter_s64index_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + indices: svint64_t, + ); + } + _svstnt1_scatter_s64index_s64(data, pg.sve_into(), base, indices) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_f64( + pg: svbool_t, + base: *mut f64, + indices: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64index_f64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_s64( + pg: svbool_t, + base: *mut i64, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64index_u64( + pg: svbool_t, + base: *mut u64, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svint64_t, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2f64" + )] + fn _svstnt1_scatter_s64offset_f64( + data: svfloat64_t, + pg: svbool2_t, + base: *mut f64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_f64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i64" + )] + fn _svstnt1_scatter_s64offset_s64( + data: svint64_t, + pg: svbool2_t, + base: *mut i64, + offsets: svint64_t, + ); + } + _svstnt1_scatter_s64offset_s64(data, pg.sve_into(), base, offsets) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_f32( + pg: svbool_t, + base: *mut f32, + offsets: svuint32_t, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4f32" + )] + fn _svstnt1_scatter_u32offset_f32( + data: svfloat32_t, + pg: svbool4_t, + base: *mut f32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_f32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i32, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32" + )] + fn _svstnt1_scatter_u32offset_s32( + data: svint32_t, + pg: svbool4_t, + base: *mut i32, + offsets: svint32_t, + ); + } + _svstnt1_scatter_u32offset_s32(data, pg.sve_into(), base, offsets.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u32, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_f64( + pg: svbool_t, + base: *mut f64, + offsets: svuint64_t, + data: svfloat64_t, +) { + svstnt1_scatter_s64offset_f64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i64, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u64, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_f32(pg: svbool_t, bases: svuint32_t, data: svfloat32_t) { + svstnt1_scatter_u32base_offset_f32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_f64(pg: svbool_t, bases: svuint64_t, data: svfloat64_t) { + svstnt1_scatter_u64base_offset_f64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_f32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svfloat32_t, +) { + svstnt1_scatter_u32base_offset_f32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_f64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svfloat64_t, +) { + svstnt1_scatter_u64base_offset_f64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(3), data) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_f32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svfloat32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_f32( + data: svfloat32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_f32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32" + )] + fn _svstnt1_scatter_u32base_offset_s32( + data: svint32_t, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1_scatter_u32base_offset_s32(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_f64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svfloat64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_f64( + data: svfloat64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_f64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64" + )] + fn _svstnt1_scatter_u64base_offset_s64( + data: svint64_t, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1_scatter_u64base_offset_s64(data, pg.sve_into(), bases.as_signed(), offset) +} +#[doc = "Non-truncating store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1d))] +pub unsafe fn svstnt1_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i8" + )] + fn _svstnt1b_scatter_s64offset_s64( + data: nxv2i8, + pg: svbool2_t, + base: *mut i8, + offsets: svint64_t, + ); + } + _svstnt1b_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i16" + )] + fn _svstnt1h_scatter_s64offset_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + offsets: svint64_t, + ); + } + _svstnt1h_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.nxv2i32" + )] + fn _svstnt1w_scatter_s64offset_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + offsets: svint64_t, + ); + } + _svstnt1w_scatter_s64offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i8, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8" + )] + fn _svstnt1b_scatter_u32offset_s32( + data: nxv4i8, + pg: svbool4_t, + base: *mut i8, + offsets: svint32_t, + ); + } + _svstnt1b_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_s32( + pg: svbool_t, + base: *mut i16, + offsets: svuint32_t, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16" + )] + fn _svstnt1h_scatter_u32offset_s32( + data: nxv4i16, + pg: svbool4_t, + base: *mut i16, + offsets: svint32_t, + ); + } + _svstnt1h_scatter_u32offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + offsets.as_signed(), + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u8, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1b_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u32]offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32offset_u32( + pg: svbool_t, + base: *mut u16, + offsets: svuint32_t, + data: svuint32_t, +) { + svstnt1h_scatter_u32offset_s32(pg, base.as_signed(), offsets, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i8, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i16, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_s64( + pg: svbool_t, + base: *mut i32, + offsets: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base, offsets.as_signed(), data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u8, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1b_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u16, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64offset_u64( + pg: svbool_t, + base: *mut u32, + offsets: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64offset_s64(pg, base.as_signed(), offsets.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32" + )] + fn _svstnt1b_scatter_u32base_offset_s32( + data: nxv4i8, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1b_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_s32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svint32_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32" + )] + fn _svstnt1h_scatter_u32base_offset_s32( + data: nxv4i16, + pg: svbool4_t, + bases: svint32_t, + offset: i64, + ); + } + _svstnt1h_scatter_u32base_offset_s32( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_offset[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_offset_u32( + pg: svbool_t, + bases: svuint32_t, + offset: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64" + )] + fn _svstnt1b_scatter_u64base_offset_s64( + data: nxv2i8, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1b_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64" + )] + fn _svstnt1h_scatter_u64base_offset_s64( + data: nxv2i16, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1h_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_s64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64" + )] + fn _svstnt1w_scatter_u64base_offset_s64( + data: nxv2i32, + pg: svbool2_t, + bases: svint64_t, + offset: i64, + ); + } + _svstnt1w_scatter_u64base_offset_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + bases.as_signed(), + offset, + ) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_offset[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_offset_u64( + pg: svbool_t, + bases: svuint64_t, + offset: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, offset, data.as_signed()) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1b_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_s32(pg: svbool_t, bases: svuint32_t, data: svint32_t) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1b_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_u32(pg: svbool_t, bases: svuint32_t, data: svuint32_t) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1b_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_s64(pg: svbool_t, bases: svuint64_t, data: svint64_t) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, 0, data) +} +#[doc = "Truncate to 8 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1b_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1b))] +pub unsafe fn svstnt1b_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1b_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_u64(pg: svbool_t, bases: svuint64_t, data: svuint64_t) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, 0, data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i16" + )] + fn _svstnt1h_scatter_s64index_s64( + data: nxv2i16, + pg: svbool2_t, + base: *mut i16, + indices: svint64_t, + ); + } + _svstnt1h_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svint64_t, + data: svint64_t, +) { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.stnt1.scatter.index.nxv2i32" + )] + fn _svstnt1w_scatter_s64index_s64( + data: nxv2i32, + pg: svbool2_t, + base: *mut i32, + indices: svint64_t, + ); + } + _svstnt1w_scatter_s64index_s64( + crate::intrinsics::simd::simd_cast(data), + pg.sve_into(), + base, + indices, + ) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_s64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[s64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_s64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices, data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_s64( + pg: svbool_t, + base: *mut i16, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_s64( + pg: svbool_t, + base: *mut i32, + indices: svuint64_t, + data: svint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base, indices.as_signed(), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64index_u64( + pg: svbool_t, + base: *mut u16, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1h_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter_[u64]index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64index_u64( + pg: svbool_t, + base: *mut u32, + indices: svuint64_t, + data: svuint64_t, +) { + svstnt1w_scatter_s64index_s64(pg, base.as_signed(), indices.as_signed(), data.as_signed()) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_s32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svint32_t, +) { + svstnt1h_scatter_u32base_offset_s32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u32base]_index[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u32base_index_u32( + pg: svbool_t, + bases: svuint32_t, + index: i64, + data: svuint32_t, +) { + svstnt1h_scatter_u32base_offset_u32(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1h_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_s64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svint64_t, +) { + svstnt1w_scatter_u64base_offset_s64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Truncate to 16 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1h_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1h))] +pub unsafe fn svstnt1h_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1h_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(1), data) +} +#[doc = "Truncate to 32 bits and store, non-temporal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svstnt1w_scatter[_u64base]_index[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`)."] +#[doc = " * This dereferences and accesses the calculated address for each active element (governed by `pg`)."] +#[doc = " * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it."] +#[doc = " * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(stnt1w))] +pub unsafe fn svstnt1w_scatter_u64base_index_u64( + pg: svbool_t, + bases: svuint64_t, + index: i64, + data: svuint64_t, +) { + svstnt1w_scatter_u64base_offset_u64(pg, bases, index.unchecked_shl(2), data) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv8i16")] + fn _svsubhnb_s16(op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnb_s16(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s16(op1: svint16_t, op2: i16) -> svint8_t { + svsubhnb_s16(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv4i32")] + fn _svsubhnb_s32(op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnb_s32(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s32(op1: svint32_t, op2: i32) -> svint16_t { + svsubhnb_s32(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnb.nxv2i64")] + fn _svsubhnb_s64(op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnb_s64(op1, op2) } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_s64(op1: svint64_t, op2: i64) -> svint32_t { + svsubhnb_s64(op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u16(op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnb_s16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u16(op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnb_u16(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u32(op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnb_s32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u32(op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnb_u32(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_u64(op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnb_s64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnb))] +pub fn svsubhnb_n_u64(op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnb_u64(op1, svdup_n_u64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv8i16")] + fn _svsubhnt_s16(even: svint8_t, op1: svint16_t, op2: svint16_t) -> svint8_t; + } + unsafe { _svsubhnt_s16(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s16(even: svint8_t, op1: svint16_t, op2: i16) -> svint8_t { + svsubhnt_s16(even, op1, svdup_n_s16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv4i32")] + fn _svsubhnt_s32(even: svint16_t, op1: svint32_t, op2: svint32_t) -> svint16_t; + } + unsafe { _svsubhnt_s32(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s32(even: svint16_t, op1: svint32_t, op2: i32) -> svint16_t { + svsubhnt_s32(even, op1, svdup_n_s32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.subhnt.nxv2i64")] + fn _svsubhnt_s64(even: svint32_t, op1: svint64_t, op2: svint64_t) -> svint32_t; + } + unsafe { _svsubhnt_s64(even, op1, op2) } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_s64(even: svint32_t, op1: svint64_t, op2: i64) -> svint32_t { + svsubhnt_s64(even, op1, svdup_n_s64(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u16(even: svuint8_t, op1: svuint16_t, op2: svuint16_t) -> svuint8_t { + unsafe { svsubhnt_s16(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u16(even: svuint8_t, op1: svuint16_t, op2: u16) -> svuint8_t { + svsubhnt_u16(even, op1, svdup_n_u16(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u32(even: svuint16_t, op1: svuint32_t, op2: svuint32_t) -> svuint16_t { + unsafe { svsubhnt_s32(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u32(even: svuint16_t, op1: svuint32_t, op2: u32) -> svuint16_t { + svsubhnt_u32(even, op1, svdup_n_u32(op2)) +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_u64(even: svuint32_t, op1: svuint64_t, op2: svuint64_t) -> svuint32_t { + unsafe { svsubhnt_s64(even.as_signed(), op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract narrow high part (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubhnt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(subhnt))] +pub fn svsubhnt_n_u64(even: svuint32_t, op1: svuint64_t, op2: u64) -> svuint32_t { + svsubhnt_u64(even, op1, svdup_n_u64(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv8i16")] + fn _svsublb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_s16(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv4i32")] + fn _svsublb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_s32(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublb.nxv2i64")] + fn _svsublb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_s64(op1, op2) } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublb))] +pub fn svsublb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv8i16")] + fn _svsublb_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv4i32")] + fn _svsublb_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublb.nxv2i64")] + fn _svsublb_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublb))] +pub fn svsublb_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv8i16" + )] + fn _svsublbt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublbt_s16(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublbt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv4i32" + )] + fn _svsublbt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublbt_s32(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublbt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssublbt.nxv2i64" + )] + fn _svsublbt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublbt_s64(op1, op2) } +} +#[doc = "Subtract long (bottom - top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublbt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublbt))] +pub fn svsublbt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublbt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv8i16")] + fn _svsublt_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_s16(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsublt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv4i32")] + fn _svsublt_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_s32(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsublt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssublt.nxv2i64")] + fn _svsublt_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_s64(op1, op2) } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssublt))] +pub fn svsublt_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsublt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u16(op1: svuint8_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv8i16")] + fn _svsublt_u16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsublt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u16(op1: svuint8_t, op2: u8) -> svuint16_t { + svsublt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u32(op1: svuint16_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv4i32")] + fn _svsublt_u32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsublt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u32(op1: svuint16_t, op2: u16) -> svuint32_t { + svsublt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_u64(op1: svuint32_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usublt.nxv2i64")] + fn _svsublt_u64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsublt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract long (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsublt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usublt))] +pub fn svsublt_n_u64(op1: svuint32_t, op2: u32) -> svuint64_t { + svsublt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv8i16" + )] + fn _svsubltb_s16(op1: svint8_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubltb_s16(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s16(op1: svint8_t, op2: i8) -> svint16_t { + svsubltb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv4i32" + )] + fn _svsubltb_s32(op1: svint16_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubltb_s32(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s32(op1: svint16_t, op2: i16) -> svint32_t { + svsubltb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.ssubltb.nxv2i64" + )] + fn _svsubltb_s64(op1: svint32_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubltb_s64(op1, op2) } +} +#[doc = "Subtract long (top - bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubltb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubltb))] +pub fn svsubltb_n_s64(op1: svint32_t, op2: i32) -> svint64_t { + svsubltb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv8i16")] + fn _svsubwb_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_s16(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwb_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv4i32")] + fn _svsubwb_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_s32(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwb_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwb.nxv2i64")] + fn _svsubwb_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_s64(op1, op2) } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwb))] +pub fn svsubwb_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwb_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv8i16")] + fn _svsubwb_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwb_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwb_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv4i32")] + fn _svsubwb_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwb_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwb_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwb.nxv2i64")] + fn _svsubwb_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwb_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (bottom)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwb[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwb))] +pub fn svsubwb_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwb_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv8i16")] + fn _svsubwt_s16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_s16(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s16(op1: svint16_t, op2: i8) -> svint16_t { + svsubwt_s16(op1, svdup_n_s8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv4i32")] + fn _svsubwt_s32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_s32(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s32(op1: svint32_t, op2: i16) -> svint32_t { + svsubwt_s32(op1, svdup_n_s16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.ssubwt.nxv2i64")] + fn _svsubwt_s64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_s64(op1, op2) } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(ssubwt))] +pub fn svsubwt_n_s64(op1: svint64_t, op2: i32) -> svint64_t { + svsubwt_s64(op1, svdup_n_s32(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u16(op1: svuint16_t, op2: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv8i16")] + fn _svsubwt_u16(op1: svint16_t, op2: svint8_t) -> svint16_t; + } + unsafe { _svsubwt_u16(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u16(op1: svuint16_t, op2: u8) -> svuint16_t { + svsubwt_u16(op1, svdup_n_u8(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u32(op1: svuint32_t, op2: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv4i32")] + fn _svsubwt_u32(op1: svint32_t, op2: svint16_t) -> svint32_t; + } + unsafe { _svsubwt_u32(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u32(op1: svuint32_t, op2: u16) -> svuint32_t { + svsubwt_u32(op1, svdup_n_u16(op2)) +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_u64(op1: svuint64_t, op2: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.usubwt.nxv2i64")] + fn _svsubwt_u64(op1: svint64_t, op2: svint32_t) -> svint64_t; + } + unsafe { _svsubwt_u64(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Subtract wide (top)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svsubwt[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(usubwt))] +pub fn svsubwt_n_u64(op1: svuint64_t, op2: u32) -> svuint64_t { + svsubwt_u64(op1, svdup_n_u32(op2)) +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f32(data: svfloat32x2_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4f32")] + fn _svtbl2_f32(data0: svfloat32_t, data1: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { + _svtbl2_f32( + svget2_f32::<0>(data), + svget2_f32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_f64(data: svfloat64x2_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2f64")] + fn _svtbl2_f64(data0: svfloat64_t, data1: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { + _svtbl2_f64( + svget2_f64::<0>(data), + svget2_f64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s8(data: svint8x2_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv16i8")] + fn _svtbl2_s8(data0: svint8_t, data1: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { + _svtbl2_s8( + svget2_s8::<0>(data), + svget2_s8::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s16(data: svint16x2_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv8i16")] + fn _svtbl2_s16(data0: svint16_t, data1: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { + _svtbl2_s16( + svget2_s16::<0>(data), + svget2_s16::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s32(data: svint32x2_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv4i32")] + fn _svtbl2_s32(data0: svint32_t, data1: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { + _svtbl2_s32( + svget2_s32::<0>(data), + svget2_s32::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_s64(data: svint64x2_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbl2.nxv2i64")] + fn _svtbl2_s64(data0: svint64_t, data1: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { + _svtbl2_s64( + svget2_s64::<0>(data), + svget2_s64::<1>(data), + indices.as_signed(), + ) + } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u8(data: svuint8x2_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbl2_s8(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u16(data: svuint16x2_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbl2_s16(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u32(data: svuint32x2_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbl2_s32(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in two-vector table"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbl2[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbl))] +pub fn svtbl2_u64(data: svuint64x2_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbl2_s64(data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svuint32_t) -> svfloat32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4f32")] + fn _svtbx_f32(fallback: svfloat32_t, data: svfloat32_t, indices: svint32_t) -> svfloat32_t; + } + unsafe { _svtbx_f32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_f64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svuint64_t) -> svfloat64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2f64")] + fn _svtbx_f64(fallback: svfloat64_t, data: svfloat64_t, indices: svint64_t) -> svfloat64_t; + } + unsafe { _svtbx_f64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv16i8")] + fn _svtbx_s8(fallback: svint8_t, data: svint8_t, indices: svint8_t) -> svint8_t; + } + unsafe { _svtbx_s8(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv8i16")] + fn _svtbx_s16(fallback: svint16_t, data: svint16_t, indices: svint16_t) -> svint16_t; + } + unsafe { _svtbx_s16(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv4i32")] + fn _svtbx_s32(fallback: svint32_t, data: svint32_t, indices: svint32_t) -> svint32_t; + } + unsafe { _svtbx_s32(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.tbx.nxv2i64")] + fn _svtbx_s64(fallback: svint64_t, data: svint64_t, indices: svint64_t) -> svint64_t; + } + unsafe { _svtbx_s64(fallback, data, indices.as_signed()) } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u8(fallback: svuint8_t, data: svuint8_t, indices: svuint8_t) -> svuint8_t { + unsafe { svtbx_s8(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u16(fallback: svuint16_t, data: svuint16_t, indices: svuint16_t) -> svuint16_t { + unsafe { svtbx_s16(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u32(fallback: svuint32_t, data: svuint32_t, indices: svuint32_t) -> svuint32_t { + unsafe { svtbx_s32(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Table lookup in single-vector table (merging)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtbx[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(tbx))] +pub fn svtbx_u64(fallback: svuint64_t, data: svuint64_t, indices: svuint64_t) -> svuint64_t { + unsafe { svtbx_s64(fallback.as_signed(), data.as_signed(), indices).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_b])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpkhi))] +pub fn svunpkhi_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpkhi.nxv16i1" + )] + fn _svunpkhi_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpkhi_b(op).sve_into() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv8i16" + )] + fn _svunpkhi_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_s16(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv4i32" + )] + fn _svunpkhi_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_s32(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpkhi))] +pub fn svunpkhi_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpkhi.nxv2i64" + )] + fn _svunpkhi_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_s64(op) } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv8i16" + )] + fn _svunpkhi_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpkhi_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv4i32" + )] + fn _svunpkhi_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpkhi_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpkhi[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpkhi))] +pub fn svunpkhi_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpkhi.nxv2i64" + )] + fn _svunpkhi_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpkhi_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_b])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(punpklo))] +pub fn svunpklo_b(op: svbool_t) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.punpklo.nxv16i1" + )] + fn _svunpklo_b(op: svbool_t) -> svbool8_t; + } + unsafe { _svunpklo_b(op).sve_into() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s16(op: svint8_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv8i16" + )] + fn _svunpklo_s16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_s16(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s32(op: svint16_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv4i32" + )] + fn _svunpklo_s32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_s32(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(sunpklo))] +pub fn svunpklo_s64(op: svint32_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.sunpklo.nxv2i64" + )] + fn _svunpklo_s64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_s64(op) } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u16(op: svuint8_t) -> svuint16_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv8i16" + )] + fn _svunpklo_u16(op: svint8_t) -> svint16_t; + } + unsafe { _svunpklo_u16(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u32(op: svuint16_t) -> svuint32_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv4i32" + )] + fn _svunpklo_u32(op: svint16_t) -> svint32_t; + } + unsafe { _svunpklo_u32(op.as_signed()).as_unsigned() } +} +#[doc = "Unpack and extend low half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svunpklo[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(uunpklo))] +pub fn svunpklo_u64(op: svuint32_t) -> svuint64_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.uunpklo.nxv2i64" + )] + fn _svunpklo_u64(op: svint32_t) -> svint64_t; + } + unsafe { _svunpklo_u64(op.as_signed()).as_unsigned() } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv16i8")] + fn _svuqadd_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t; + } + unsafe { _svuqadd_s8_m(pg, op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_m(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_m(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_x(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_x(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_x(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s8_z(pg: svbool_t, op1: svint8_t, op2: svuint8_t) -> svint8_t { + svuqadd_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s8]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s8_z(pg: svbool_t, op1: svint8_t, op2: u8) -> svint8_t { + svuqadd_s8_z(pg, op1, svdup_n_u8(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_m(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv8i16")] + fn _svuqadd_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t; + } + unsafe { _svuqadd_s16_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_m(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_m(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_x(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_x(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_x(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s16_z(pg: svbool_t, op1: svint16_t, op2: svuint16_t) -> svint16_t { + svuqadd_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s16]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s16_z(pg: svbool_t, op1: svint16_t, op2: u16) -> svint16_t { + svuqadd_s16_z(pg, op1, svdup_n_u16(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_m(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv4i32")] + fn _svuqadd_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t; + } + unsafe { _svuqadd_s32_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_m(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_m(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_x(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_x(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_x(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s32_z(pg: svbool_t, op1: svint32_t, op2: svuint32_t) -> svint32_t { + svuqadd_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s32]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s32_z(pg: svbool_t, op1: svint32_t, op2: u32) -> svint32_t { + svuqadd_s32_z(pg, op1, svdup_n_u32(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_m(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.suqadd.nxv2i64")] + fn _svuqadd_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t; + } + unsafe { _svuqadd_s64_m(pg.sve_into(), op1, op2.as_signed()) } +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_m)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_m(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_m(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_x(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, op1, op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_x)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_x(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_x(pg, op1, svdup_n_u64(op2)) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_s64_z(pg: svbool_t, op1: svint64_t, op2: svuint64_t) -> svint64_t { + svuqadd_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2) +} +#[doc = "Saturating add with unsigned addend"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svuqadd[_n_s64]_z)"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(suqadd))] +pub fn svuqadd_n_s64_z(pg: svbool_t, op1: svint64_t, op2: u64) -> svint64_t { + svuqadd_s64_z(pg, op1, svdup_n_u64(op2)) +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i32" + )] + fn _svwhilege_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i32" + )] + fn _svwhilege_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i32" + )] + fn _svwhilege_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i32" + )] + fn _svwhilege_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv16i1.i64" + )] + fn _svwhilege_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv8i1.i64" + )] + fn _svwhilege_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv4i1.i64" + )] + fn _svwhilege_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilege))] +pub fn svwhilege_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilege.nxv2i1.i64" + )] + fn _svwhilege_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i32" + )] + fn _svwhilege_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilege_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i32" + )] + fn _svwhilege_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilege_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i32" + )] + fn _svwhilege_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilege_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i32" + )] + fn _svwhilege_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilege_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv16i1.i64" + )] + fn _svwhilege_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilege_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv8i1.i64" + )] + fn _svwhilege_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilege_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv4i1.i64" + )] + fn _svwhilege_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilege_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than or equal to"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilege_b64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehs))] +pub fn svwhilege_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehs.nxv2i1.i64" + )] + fn _svwhilege_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilege_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i32" + )] + fn _svwhilegt_b8_s32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_s32(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i32" + )] + fn _svwhilegt_b16_s32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i32" + )] + fn _svwhilegt_b32_s32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i32" + )] + fn _svwhilegt_b64_s32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s32(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv16i1.i64" + )] + fn _svwhilegt_b8_s64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_s64(op1, op2) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv8i1.i64" + )] + fn _svwhilegt_b16_s64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv4i1.i64" + )] + fn _svwhilegt_b32_s64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilegt))] +pub fn svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilegt.nxv2i1.i64" + )] + fn _svwhilegt_b64_s64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_s64(op1, op2).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i32" + )] + fn _svwhilegt_b8_u32(op1: i32, op2: i32) -> svbool_t; + } + unsafe { _svwhilegt_b8_u32(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i32" + )] + fn _svwhilegt_b16_u32(op1: i32, op2: i32) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i32" + )] + fn _svwhilegt_b32_u32(op1: i32, op2: i32) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u32(op1: u32, op2: u32) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i32" + )] + fn _svwhilegt_b64_u32(op1: i32, op2: i32) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u32(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b8[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b8_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv16i1.i64" + )] + fn _svwhilegt_b8_u64(op1: i64, op2: i64) -> svbool_t; + } + unsafe { _svwhilegt_b8_u64(op1.as_signed(), op2.as_signed()) } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b16[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b16_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv8i1.i64" + )] + fn _svwhilegt_b16_u64(op1: i64, op2: i64) -> svbool8_t; + } + unsafe { _svwhilegt_b16_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b32[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b32_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv4i1.i64" + )] + fn _svwhilegt_b32_u64(op1: i64, op2: i64) -> svbool4_t; + } + unsafe { _svwhilegt_b32_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[doc = "While decrementing scalar is greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilegt_b64[_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilehi))] +pub fn svwhilegt_b64_u64(op1: u64, op2: u64) -> svbool_t { + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilehi.nxv2i1.i64" + )] + fn _svwhilegt_b64_u64(op1: i64, op2: i64) -> svbool2_t; + } + unsafe { _svwhilegt_b64_u64(op1.as_signed(), op2.as_signed()).sve_into() } +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.b.nxv16i1.p0" + )] + fn _svwhilerw_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilerw_8ptr(op1, op2) +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.h.nxv8i1.p0" + )] + fn _svwhilerw_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilerw_16ptr(op1, op2).sve_into() +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.s.nxv4i1.p0" + )] + fn _svwhilerw_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilerw_32ptr(op1, op2).sve_into() +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilerw_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilerw.d.nxv2i1.p0" + )] + fn _svwhilerw_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilerw_64ptr(op1, op2).sve_into() +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilerw_8ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilerw_16ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilerw_32ptr::(op1, op2) +} +#[doc = "While free of read-after-write conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilerw[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilerw))] +pub unsafe fn svwhilerw_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilerw_64ptr::(op1, op2) +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_8ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.b.nxv16i1.p0" + )] + fn _svwhilewr_8ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool_t; + } + _svwhilewr_8ptr(op1, op2) +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_16ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.h.nxv8i1.p0" + )] + fn _svwhilewr_16ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool8_t; + } + _svwhilewr_16ptr(op1, op2).sve_into() +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_32ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.s.nxv4i1.p0" + )] + fn _svwhilewr_32ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool4_t; + } + _svwhilewr_32ptr(op1, op2).sve_into() +} +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +unsafe fn svwhilewr_64ptr(op1: *const T, op2: *const T) -> svbool_t { + let op1 = op1 as *const crate::ffi::c_void; + let op2 = op2 as *const crate::ffi::c_void; + unsafe extern "unadjusted" { + #[cfg_attr( + target_arch = "aarch64", + link_name = "llvm.aarch64.sve.whilewr.d.nxv2i1.p0" + )] + fn _svwhilewr_64ptr( + op1: *const crate::ffi::c_void, + op2: *const crate::ffi::c_void, + ) -> svbool2_t; + } + _svwhilewr_64ptr(op1, op2).sve_into() +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f32(op1: *const f32, op2: *const f32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_f64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_f64(op1: *const f64, op2: *const f64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s8(op1: *const i8, op2: *const i8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s16(op1: *const i16, op2: *const i16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s32(op1: *const i32, op2: *const i32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_s64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_s64(op1: *const i64, op2: *const i64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u8])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u8(op1: *const u8, op2: *const u8) -> svbool_t { + svwhilewr_8ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u16])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u16(op1: *const u16, op2: *const u16) -> svbool_t { + svwhilewr_16ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u32])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u32(op1: *const u32, op2: *const u32) -> svbool_t { + svwhilewr_32ptr::(op1, op2) +} +#[doc = "While free of write-after-read conflicts"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svwhilewr[_u64])"] +#[doc = "## Safety"] +#[doc = " * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`."] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(whilewr))] +pub unsafe fn svwhilewr_u64(op1: *const u64, op2: *const u64) -> svbool_t { + svwhilewr_64ptr::(op1, op2) +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s8(op1: svint8_t, op2: svint8_t) -> svint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv16i8")] + fn _svxar_n_s8(op1: svint8_t, op2: svint8_t, imm3: i32) -> svint8_t; + } + unsafe { _svxar_n_s8(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s16(op1: svint16_t, op2: svint16_t) -> svint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv8i16")] + fn _svxar_n_s16(op1: svint16_t, op2: svint16_t, imm3: i32) -> svint16_t; + } + unsafe { _svxar_n_s16(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s32(op1: svint32_t, op2: svint32_t) -> svint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv4i32")] + fn _svxar_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t; + } + unsafe { _svxar_n_s32(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_s64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_s64(op1: svint64_t, op2: svint64_t) -> svint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv2i64")] + fn _svxar_n_s64(op1: svint64_t, op2: svint64_t, imm3: i32) -> svint64_t; + } + unsafe { _svxar_n_s64(op1, op2, IMM3) } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u8])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u8(op1: svuint8_t, op2: svuint8_t) -> svuint8_t { + static_assert_range!(IMM3, 1..=8); + unsafe { svxar_n_s8::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u16])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u16(op1: svuint16_t, op2: svuint16_t) -> svuint16_t { + static_assert_range!(IMM3, 1..=16); + unsafe { svxar_n_s16::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u32])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t { + static_assert_range!(IMM3, 1..=32); + unsafe { svxar_n_s32::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} +#[doc = "Bitwise exclusive OR and rotate right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svxar[_n_u64])"] +#[inline(always)] +#[target_feature(enable = "sve,sve2")] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +#[cfg_attr(test, assert_instr(xar, IMM3 = 1))] +pub fn svxar_n_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t { + static_assert_range!(IMM3, 1..=64); + unsafe { svxar_n_s64::(op1.as_signed(), op2.as_signed()).as_unsigned() } +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs new file mode 100644 index 000000000000..2ec3ad6a5d04 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/ld_st_tests_aarch64.rs @@ -0,0 +1,2482 @@ +// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen-arm/spec/sve` and run the following command to re-generate +// this file: +// +// ``` +// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec +// ``` +#![allow(unused)] +use super::*; +use std::boxed::Box; +use std::convert::{TryFrom, TryInto}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; +static F32_DATA: LazyLock<[f32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}); +static F64_DATA: LazyLock<[f64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}); +static I8_DATA: LazyLock<[i8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}); +static I16_DATA: LazyLock<[i16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}); +static I32_DATA: LazyLock<[i32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}); +static I64_DATA: LazyLock<[i64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}); +static U8_DATA: LazyLock<[u8; 256 * 5]> = LazyLock::new(|| { + (0..256 * 5) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}); +static U16_DATA: LazyLock<[u16; 128 * 5]> = LazyLock::new(|| { + (0..128 * 5) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}); +static U32_DATA: LazyLock<[u32; 64 * 5]> = LazyLock::new(|| { + (0..64 * 5) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}); +static U64_DATA: LazyLock<[u64; 32 * 5]> = LazyLock::new(|| { + (0..32 * 5) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}); +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) { + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_f64_with_svstnt1_scatter_s64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_s64_with_svstnt1_scatter_s64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64index_u64_with_svstnt1_scatter_s64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1_scatter_s64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_f64_with_svstnt1_scatter_u64index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_f64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_f64(svptrue_b64(), storage.as_ptr() as *const f64, indices); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_s64_with_svstnt1_scatter_u64index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_s64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_s64(svptrue_b64(), storage.as_ptr() as *const i64, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64index_u64_with_svstnt1_scatter_u64index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1_scatter_u64index_u64(svptrue_b64(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64index_u64(svptrue_b64(), storage.as_ptr() as *const u64, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_f64_with_svstnt1_scatter_s64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_s64_with_svstnt1_scatter_s64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_s64offset_u64_with_svstnt1_scatter_s64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_s64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_s64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_f32_with_svstnt1_scatter_u32offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_f32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_f32(svptrue_b32(), storage.as_ptr() as *const f32, offsets); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_s32_with_svstnt1_scatter_u32offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_s32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_s32(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32offset_u32_with_svstnt1_scatter_u32offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32offset_u32(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1_gather_u32offset_u32(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_f64_with_svstnt1_scatter_u64offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_f64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_f64(svptrue_b64(), storage.as_ptr() as *const f64, offsets); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_s64_with_svstnt1_scatter_u64offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_s64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_s64(svptrue_b64(), storage.as_ptr() as *const i64, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64offset_u64_with_svstnt1_scatter_u64offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + svstnt1_scatter_u64offset_u64(svptrue_b64(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = + svldnt1_gather_u64offset_u64(svptrue_b64(), storage.as_ptr() as *const u64, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_f64_with_svstnt1_scatter_u64base_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_f64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_f64(svptrue_b64(), bases); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_s64_with_svstnt1_scatter_u64base_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_s64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_s64(svptrue_b64(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_u64_with_svstnt1_scatter_u64base_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_u64(svptrue_b64(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_u64(svptrue_b64(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_f32_with_svstnt1_scatter_u32base_index_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_s32_with_svstnt1_scatter_u32base_index_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_index_u32_with_svstnt1_scatter_u32base_index_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_index_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 / (4u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_f64_with_svstnt1_scatter_u64base_index_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_f64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_s64_with_svstnt1_scatter_u64base_index_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_s64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_index_u64_with_svstnt1_scatter_u64base_index_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_index_u64(svptrue_b64(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_f32_with_svstnt1_scatter_u32base_offset_f32() { + let mut storage = [0 as f32; 320usize]; + let data = svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f32 || val == i as f32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_f32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_f32( + loaded, + svcvt_f32_s32_x( + svptrue_b32(), + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_s32_with_svstnt1_scatter_u32base_offset_s32() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_s32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u32base_offset_u32_with_svstnt1_scatter_u32base_offset_u32() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 4u32.try_into().unwrap()); + svstnt1_scatter_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = svldnt1_gather_u32base_offset_u32( + svptrue_b32(), + bases, + storage.as_ptr() as i64 + 4u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_f64_with_svstnt1_scatter_u64base_offset_f64() { + let mut storage = [0 as f64; 160usize]; + let data = svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as f64 || val == i as f64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_f64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_f64( + loaded, + svcvt_f64_s64_x( + svptrue_b64(), + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_s64_with_svstnt1_scatter_u64base_offset_s64() { + let mut storage = [0 as i64; 160usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i64 || val == i as i64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_s64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1_gather_u64base_offset_u64_with_svstnt1_scatter_u64base_offset_u64() { + let mut storage = [0 as u64; 160usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 8u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b64(), bases, offsets); + svstnt1_scatter_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u64 || val == i as u64); + } + svsetffr(); + let loaded = svldnt1_gather_u64base_offset_u64(svptrue_b64(), bases, 8u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sb_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1sb_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1sh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const i16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1sw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const i32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1sh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1sw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1sw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_s64_with_svstnt1b_scatter_s64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_s64_with_svstnt1h_scatter_s64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_s64_with_svstnt1w_scatter_s64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_s64offset_u64_with_svstnt1b_scatter_s64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64offset_u64_with_svstnt1h_scatter_s64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64offset_u64_with_svstnt1w_scatter_s64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_s64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_s32_with_svstnt1b_scatter_u32offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_s32_with_svstnt1h_scatter_u32offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i32( + loaded, + svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32offset_u32_with_svstnt1b_scatter_u32offset_u32() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32offset_u32_with_svstnt1h_scatter_u32offset_u32() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u32( + loaded, + svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_s64_with_svstnt1b_scatter_u64offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_s64_with_svstnt1h_scatter_u64offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_s64_with_svstnt1w_scatter_u64offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64offset_u64_with_svstnt1b_scatter_u64offset_u64() { + let mut storage = [0 as u8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u8 || val == i as u8); + } + svsetffr(); + let loaded = + svldnt1ub_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const u8, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64offset_u64_with_svstnt1h_scatter_u64offset_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const u16, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64offset_u64_with_svstnt1w_scatter_u64offset_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + svstnt1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const u32, offsets); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_s32_with_svstnt1b_scatter_u32base_offset_s32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_s32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_s32_with_svstnt1h_scatter_u32base_offset_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u32base_offset_u32_with_svstnt1b_scatter_u32base_offset_u32() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 1u32.try_into().unwrap()); + svstnt1b_scatter_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u32base_offset_u32( + svptrue_b8(), + bases, + storage.as_ptr() as i64 + 1u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_offset_u32_with_svstnt1h_scatter_u32base_offset_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_offset_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 + 2u32 as i64, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_s64_with_svstnt1b_scatter_u64base_offset_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_s64_with_svstnt1h_scatter_u64base_offset_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_s64_with_svstnt1w_scatter_u64base_offset_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_s64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_offset_u64_with_svstnt1b_scatter_u64base_offset_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_offset_u64(svptrue_b8(), bases, 1u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_offset_u64_with_svstnt1h_scatter_u64base_offset_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64base_offset_u64(svptrue_b16(), bases, 2u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_offset_u64_with_svstnt1w_scatter_u64base_offset_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64base_offset_u64(svptrue_b32(), bases, 4u32.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_s64_with_svstnt1b_scatter_u64base_s64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_s64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_s64(svptrue_b8(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_s64_with_svstnt1h_scatter_u64base_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_s64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_s64(svptrue_b16(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_s64_with_svstnt1w_scatter_u64base_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_s64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_s64(svptrue_b32(), bases); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1ub_gather_u64base_u64_with_svstnt1b_scatter_u64base_u64() { + let mut storage = [0 as i8; 1280usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 1u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b8(), bases, offsets); + svstnt1b_scatter_u64base_u64(svptrue_b8(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i8 || val == i as i8); + } + svsetffr(); + let loaded = svldnt1ub_gather_u64base_u64(svptrue_b8(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_u64_with_svstnt1h_scatter_u64base_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_u64(svptrue_b16(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_u64(svptrue_b16(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_u64_with_svstnt1w_scatter_u64base_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_u64(svptrue_b32(), bases, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_u64(svptrue_b32(), bases); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_s64_with_svstnt1h_scatter_s64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_s64_with_svstnt1w_scatter_s64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_s64index_u64_with_svstnt1h_scatter_s64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1h_scatter_s64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_s64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_s64index_u64_with_svstnt1w_scatter_s64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_s64(0, 1); + svstnt1w_scatter_s64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_s64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_s64_with_svstnt1h_scatter_u64index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_s64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_s64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_s64_with_svstnt1w_scatter_u64index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_s64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_s64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_i64( + loaded, + svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64index_u64_with_svstnt1h_scatter_u64index_u64() { + let mut storage = [0 as u16; 640usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1h_scatter_u64index_u64(svptrue_b16(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u16 || val == i as u16); + } + svsetffr(); + let loaded = + svldnt1uh_gather_u64index_u64(svptrue_b16(), storage.as_ptr() as *const u16, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64index_u64_with_svstnt1w_scatter_u64index_u64() { + let mut storage = [0 as u32; 320usize]; + let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let indices = svindex_u64(0, 1); + svstnt1w_scatter_u64index_u64(svptrue_b32(), storage.as_mut_ptr(), indices, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as u32 || val == i as u32); + } + svsetffr(); + let loaded = + svldnt1uw_gather_u64index_u64(svptrue_b32(), storage.as_ptr() as *const u32, indices); + assert_vector_matches_u64( + loaded, + svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_s32_with_svstnt1h_scatter_u32base_index_s32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_s32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_i32( + loaded, + svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u32base_index_u32_with_svstnt1h_scatter_u32base_index_u32() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svindex_u32(0, 2u32.try_into().unwrap()); + svstnt1h_scatter_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + data, + ); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u32base_index_u32( + svptrue_b16(), + bases, + storage.as_ptr() as i64 / (2u32 as i64) + 1, + ); + assert_vector_matches_u32( + loaded, + svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_s64_with_svstnt1h_scatter_u64base_index_s64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_s64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_s64_with_svstnt1w_scatter_u64base_index_s64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_s64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_i64( + loaded, + svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uh_gather_u64base_index_u64_with_svstnt1h_scatter_u64base_index_u64() { + let mut storage = [0 as i16; 640usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 2u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b16(), bases, offsets); + svstnt1h_scatter_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i16 || val == i as i16); + } + svsetffr(); + let loaded = svldnt1uh_gather_u64base_index_u64(svptrue_b16(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} +#[simd_test(enable = "sve,sve2")] +unsafe fn test_svldnt1uw_gather_u64base_index_u64_with_svstnt1w_scatter_u64base_index_u64() { + let mut storage = [0 as i32; 320usize]; + let data = svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()); + let bases = svdup_n_u64(storage.as_ptr() as u64); + let offsets = svindex_u64(0, 4u32.try_into().unwrap()); + let bases = svadd_u64_x(svptrue_b32(), bases, offsets); + svstnt1w_scatter_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap(), data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as i32 || val == i as i32); + } + svsetffr(); + let loaded = svldnt1uw_gather_u64base_index_u64(svptrue_b32(), bases, 1.try_into().unwrap()); + assert_vector_matches_u64( + loaded, + svindex_u64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()), + ); +} diff --git a/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs b/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs new file mode 100644 index 000000000000..acf907021457 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/aarch64/sve2/mod.rs @@ -0,0 +1,17 @@ +//! SVE2 intrinsics + +#![allow(non_camel_case_types)] + +// `generated.rs` has a `super::*` and this import is for that +use super::sve::*; +use crate::intrinsics::*; + +#[rustfmt::skip] +mod generated; +#[rustfmt::skip] +#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")] +pub use self::generated::*; + +#[cfg(test)] +#[path = "ld_st_tests_aarch64.rs"] +mod ld_st_tests; diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 4a846e287746..cf4d10162ec9 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -67158,14 +67158,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2f32.p0" - )] - fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8); - } - _vst3_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] @@ -67177,14 +67170,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4f32.p0" - )] - fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8); - } - _vst3q_f32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] @@ -67196,14 +67182,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i8.p0" - )] - fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); - } - _vst3_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] @@ -67215,14 +67194,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v16i8.p0" - )] - fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); - } - _vst3q_s8(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] @@ -67234,14 +67206,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i16.p0" - )] - fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8); - } - _vst3_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] @@ -67253,14 +67218,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v8i16.p0" - )] - fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8); - } - _vst3q_s16(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] @@ -67272,14 +67230,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2i32.p0" - )] - fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8); - } - _vst3_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] @@ -67291,14 +67242,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v4i32.p0" - )] - fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8); - } - _vst3q_s32(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] diff --git a/library/stdarch/crates/core_arch/src/hexagon/v128.rs b/library/stdarch/crates/core_arch/src/hexagon/v128.rs index ef7ff4205c71..10263382938b 100644 --- a/library/stdarch/crates/core_arch/src/hexagon/v128.rs +++ b/library/stdarch/crates/core_arch/src/hexagon/v128.rs @@ -15,6 +15,18 @@ //! //! To use this module, compile with `-C target-feature=+hvx-length128b`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -31,6 +43,7 @@ //! Each version includes all features from previous versions. #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1034,7 +1047,7 @@ fn v6mpyvubs10_vxx( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(extractw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { extractw(vu, rs) } @@ -1046,7 +1059,7 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(hi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { hi(vss) } @@ -1058,7 +1071,7 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lo))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { lo(vss) } @@ -1070,7 +1083,7 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lvsplatw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { lvsplatw(rt) } @@ -1082,7 +1095,7 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffh(vu, vv) } @@ -1094,7 +1107,7 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffub(vu, vv) } @@ -1106,7 +1119,7 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffuh(vu, vv) } @@ -1118,7 +1131,7 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffw(vu, vv) } @@ -1130,7 +1143,7 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { vabsh(vu) } @@ -1142,7 +1155,7 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { vabsh_sat(vu) } @@ -1154,7 +1167,7 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { vabsw(vu) } @@ -1166,7 +1179,7 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { vabsw_sat(vu) } @@ -1178,7 +1191,7 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddb(vu, vv) } @@ -1190,7 +1203,7 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddb_dv(vuu, vvv) } @@ -1202,7 +1215,7 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddh(vu, vv) } @@ -1214,7 +1227,7 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddh_dv(vuu, vvv) } @@ -1226,7 +1239,7 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddhsat(vu, vv) } @@ -1238,7 +1251,7 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddhsat_dv(vuu, vvv) } @@ -1250,7 +1263,7 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddhw(vu, vv) } @@ -1262,7 +1275,7 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddubh(vu, vv) } @@ -1274,7 +1287,7 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddubsat(vu, vv) } @@ -1286,7 +1299,7 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddubsat_dv(vuu, vvv) } @@ -1298,7 +1311,7 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduhsat(vu, vv) } @@ -1310,7 +1323,7 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduhsat_dv(vuu, vvv) } @@ -1322,7 +1335,7 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadduhw(vu, vv) } @@ -1334,7 +1347,7 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_add(vu, vv) } @@ -1346,7 +1359,7 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddw_dv(vuu, vvv) } @@ -1358,7 +1371,7 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddwsat(vu, vv) } @@ -1370,7 +1383,7 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddwsat_dv(vuu, vvv) } @@ -1382,7 +1395,7 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { valignb(vu, vv, rt) } @@ -1394,7 +1407,7 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { valignbi(vu, vv, iu3) } @@ -1406,7 +1419,7 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vand))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_and(vu, vv) } @@ -1418,7 +1431,7 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { vaslh(vu, rt) } @@ -1430,7 +1443,7 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslhv(vu, vv) } @@ -1442,7 +1455,7 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { vaslw(vu, rt) } @@ -1454,7 +1467,7 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslw_acc(vx, vu, rt) } @@ -1466,7 +1479,7 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslwv(vu, vv) } @@ -1478,7 +1491,7 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { vasrh(vu, rt) } @@ -1490,7 +1503,7 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhbrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbrndsat(vu, vv, rt) } @@ -1502,7 +1515,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubrndsat(vu, vv, rt) } @@ -1514,7 +1527,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubsat(vu, vv, rt) } @@ -1526,7 +1539,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrhv(vu, vv) } @@ -1538,7 +1551,7 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { vasrw(vu, rt) } @@ -1550,7 +1563,7 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrw_acc(vx, vu, rt) } @@ -1562,7 +1575,7 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwh(vu, vv, rt) } @@ -1574,7 +1587,7 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhrndsat(vu, vv, rt) } @@ -1586,7 +1599,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhsat(vu, vv, rt) } @@ -1598,7 +1611,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhsat(vu, vv, rt) } @@ -1610,7 +1623,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrwv(vu, vv) } @@ -1622,7 +1635,7 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassign))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { vassign(vu) } @@ -1634,7 +1647,7 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassignp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { vassignp(vuu) } @@ -1646,7 +1659,7 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgh(vu, vv) } @@ -1658,7 +1671,7 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavghrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavghrnd(vu, vv) } @@ -1670,7 +1683,7 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgub(vu, vv) } @@ -1682,7 +1695,7 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgubrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgubrnd(vu, vv) } @@ -1694,7 +1707,7 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguh(vu, vv) } @@ -1706,7 +1719,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguhrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguhrnd(vu, vv) } @@ -1718,7 +1731,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgw(vu, vv) } @@ -1730,7 +1743,7 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgwrnd(vu, vv) } @@ -1742,7 +1755,7 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { vcl0h(vu) } @@ -1754,7 +1767,7 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { vcl0w(vu) } @@ -1766,7 +1779,7 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcombine))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vcombine(vu, vv) } @@ -1778,7 +1791,7 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vzero() -> HvxVector { +pub unsafe fn Q6_V_vzero() -> HvxVector { vd0() } @@ -1790,7 +1803,7 @@ pub unsafe fn q6_v_vzero() -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { vdealb(vu) } @@ -1802,7 +1815,7 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb4w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vdealb4w(vu, vv) } @@ -1814,7 +1827,7 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { vdealh(vu) } @@ -1826,7 +1839,7 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vdealvdd(vu, vv, rt) } @@ -1838,7 +1851,7 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vdelta(vu, vv) } @@ -1850,7 +1863,7 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpybus(vu, rt) } @@ -1862,7 +1875,7 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpybus_acc(vx, vu, rt) } @@ -1874,7 +1887,7 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpybus_dv(vuu, rt) } @@ -1886,7 +1899,7 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1902,7 +1915,7 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb(vu, rt) } @@ -1914,7 +1927,7 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb_acc(vx, vu, rt) } @@ -1926,7 +1939,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpyhb_dv(vuu, rt) } @@ -1938,7 +1951,7 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1954,7 +1967,7 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat(vuu, rt) } @@ -1966,7 +1979,7 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat_acc(vx, vuu, rt) } @@ -1978,7 +1991,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat(vu, rt) } @@ -1990,7 +2003,7 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat_acc(vx, vu, rt) } @@ -2002,7 +2015,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat(vuu, rt) } @@ -2014,7 +2027,7 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat_acc(vx, vuu, rt) } @@ -2026,7 +2039,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat(vu, rt) } @@ -2038,7 +2051,7 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat_acc(vx, vu, rt) } @@ -2050,7 +2063,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat(vu, vv) } @@ -2062,7 +2075,7 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat_acc(vx, vu, vv) } @@ -2074,7 +2087,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdsaduh(vuu, rt) } @@ -2086,7 +2099,7 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2102,7 +2115,7 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vinsertwr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { vinsertwr(vx, rt) } @@ -2114,7 +2127,7 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlalignb(vu, vv, rt) } @@ -2126,7 +2139,7 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlalignbi(vu, vv, iu3) } @@ -2138,7 +2151,7 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { vlsrh(vu, rt) } @@ -2150,7 +2163,7 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrhv(vu, vv) } @@ -2162,7 +2175,7 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { vlsrw(vu, rt) } @@ -2174,7 +2187,7 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrwv(vu, vv) } @@ -2186,7 +2199,7 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb(vu, vv, rt) } @@ -2198,7 +2211,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbr( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2215,7 +2228,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh(vu, vv, rt) } @@ -2227,7 +2240,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhr( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2244,7 +2257,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxh(vu, vv) } @@ -2256,7 +2269,7 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxub(vu, vv) } @@ -2268,7 +2281,7 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxuh(vu, vv) } @@ -2280,7 +2293,7 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxw(vu, vv) } @@ -2292,7 +2305,7 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminh(vu, vv) } @@ -2304,7 +2317,7 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vminub(vu, vv) } @@ -2316,7 +2329,7 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminuh(vu, vv) } @@ -2328,7 +2341,7 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vminw(vu, vv) } @@ -2340,7 +2353,7 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabus(vuu, rt) } @@ -2352,7 +2365,7 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrb( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2368,7 +2381,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabusv(vuu, vvv) } @@ -2380,7 +2393,7 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabuuv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabuuv(vuu, vvv) } @@ -2392,7 +2405,7 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpahb(vuu, rt) } @@ -2404,7 +2417,7 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2420,7 +2433,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus(vu, rt) } @@ -2432,7 +2445,7 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus_acc(vxx, vu, rt) } @@ -2444,7 +2457,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybusv(vu, vv) } @@ -2456,7 +2469,7 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2472,7 +2485,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybv(vu, vv) } @@ -2484,7 +2497,7 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvbvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2500,7 +2513,7 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyewuh(vu, vv) } @@ -2512,7 +2525,7 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh(vu, rt) } @@ -2524,7 +2537,7 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2540,7 +2553,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhsrs(vu, rt) } @@ -2552,7 +2565,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhss))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhss(vu, rt) } @@ -2564,7 +2577,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhus(vu, vv) } @@ -2576,7 +2589,7 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvuh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2592,7 +2605,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhv(vu, vv) } @@ -2604,7 +2617,7 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2620,7 +2633,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhvsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyhvsrs(vu, vv) } @@ -2632,7 +2645,7 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyieoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyieoh(vu, vv) } @@ -2644,7 +2657,7 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewh_acc(vx, vu, vv) } @@ -2656,7 +2669,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh(vu, vv) } @@ -2668,7 +2681,7 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh_acc(vx, vu, vv) } @@ -2680,7 +2693,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih(vu, vv) } @@ -2692,7 +2705,7 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih_acc(vx, vu, vv) } @@ -2704,7 +2717,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyihb(vu, rt) } @@ -2716,7 +2729,7 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyihb_acc(vx, vu, rt) } @@ -2728,7 +2741,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiowh(vu, vv) } @@ -2740,7 +2753,7 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb(vu, rt) } @@ -2752,7 +2765,7 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb_acc(vx, vu, rt) } @@ -2764,7 +2777,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh(vu, rt) } @@ -2776,7 +2789,7 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh_acc(vx, vu, rt) } @@ -2788,7 +2801,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh(vu, vv) } @@ -2800,7 +2813,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh_rnd(vu, vv) } @@ -2812,7 +2825,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2828,7 +2841,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2844,7 +2857,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyub(vu, rt) } @@ -2856,7 +2869,7 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2872,7 +2885,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyubv(vu, vv) } @@ -2884,7 +2897,7 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2900,7 +2913,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyuh(vu, rt) } @@ -2912,7 +2925,7 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2928,7 +2941,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyuhv(vu, vv) } @@ -2940,7 +2953,7 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2956,7 +2969,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgh(vu, vv) } @@ -2968,7 +2981,7 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgub(vu, vv) } @@ -2980,7 +2993,7 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgw(vu, vv) } @@ -2992,7 +3005,7 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { vnormamth(vu) } @@ -3004,7 +3017,7 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamtw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { vnormamtw(vu) } @@ -3016,7 +3029,7 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnot))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { vnot(vu) } @@ -3028,7 +3041,7 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_or(vu, vv) } @@ -3040,7 +3053,7 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeb(vu, vv) } @@ -3052,7 +3065,7 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeh(vu, vv) } @@ -3064,7 +3077,7 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhb_sat(vu, vv) } @@ -3076,7 +3089,7 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhub_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhub_sat(vu, vv) } @@ -3088,7 +3101,7 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackob(vu, vv) } @@ -3100,7 +3113,7 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackoh(vu, vv) } @@ -3112,7 +3125,7 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwh_sat(vu, vv) } @@ -3124,7 +3137,7 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwuh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwuh_sat(vu, vv) } @@ -3136,7 +3149,7 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpopcounth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { vpopcounth(vu) } @@ -3148,7 +3161,7 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vrdelta(vu, vv) } @@ -3160,7 +3173,7 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vrmpybus(vu, rt) } @@ -3172,7 +3185,7 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpybus_acc(vx, vu, rt) } @@ -3184,7 +3197,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpybusi(vuu, rt, iu1) } @@ -3196,7 +3209,7 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3213,7 +3226,7 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv(vu, vv) } @@ -3225,7 +3238,7 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv_acc(vx, vu, vv) } @@ -3237,7 +3250,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv(vu, vv) } @@ -3249,7 +3262,7 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv_acc(vx, vu, vv) } @@ -3261,7 +3274,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { vrmpyub(vu, rt) } @@ -3273,7 +3286,7 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpyub_acc(vx, vu, rt) } @@ -3285,7 +3298,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpyubi(vuu, rt, iu1) } @@ -3297,7 +3310,7 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3314,7 +3327,7 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv(vu, vv) } @@ -3326,7 +3339,7 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv_acc(vx, vu, vv) } @@ -3338,7 +3351,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vror))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { vror(vu, rt) } @@ -3350,7 +3363,7 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhb(vu, vv) } @@ -3362,7 +3375,7 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhub(vu, vv) } @@ -3374,7 +3387,7 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwh(vu, vv) } @@ -3386,7 +3399,7 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwuh(vu, vv) } @@ -3398,7 +3411,7 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrsadubi(vuu, rt, iu1) } @@ -3410,7 +3423,7 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3427,7 +3440,7 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsathub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsathub(vu, vv) } @@ -3439,7 +3452,7 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsatwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatwh(vu, vv) } @@ -3451,7 +3464,7 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { vsb(vu) } @@ -3463,7 +3476,7 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { vsh(vu) } @@ -3475,7 +3488,7 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufeh(vu, vv) } @@ -3487,7 +3500,7 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { vshuffb(vu) } @@ -3499,7 +3512,7 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffeb(vu, vv) } @@ -3511,7 +3524,7 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { vshuffh(vu) } @@ -3523,7 +3536,7 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffob(vu, vv) } @@ -3535,7 +3548,7 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vshuffvdd(vu, vv, rt) } @@ -3547,7 +3560,7 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeb(vu, vv) } @@ -3559,7 +3572,7 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeh(vu, vv) } @@ -3571,7 +3584,7 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufoh(vu, vv) } @@ -3583,7 +3596,7 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubb(vu, vv) } @@ -3595,7 +3608,7 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubb_dv(vuu, vvv) } @@ -3607,7 +3620,7 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubh(vu, vv) } @@ -3619,7 +3632,7 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubh_dv(vuu, vvv) } @@ -3631,7 +3644,7 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubhsat(vu, vv) } @@ -3643,7 +3656,7 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubhsat_dv(vuu, vvv) } @@ -3655,7 +3668,7 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubhw(vu, vv) } @@ -3667,7 +3680,7 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsububh(vu, vv) } @@ -3679,7 +3692,7 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsububsat(vu, vv) } @@ -3691,7 +3704,7 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsububsat_dv(vuu, vvv) } @@ -3703,7 +3716,7 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuhsat(vu, vv) } @@ -3715,7 +3728,7 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuhsat_dv(vuu, vvv) } @@ -3727,7 +3740,7 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubuhw(vu, vv) } @@ -3739,7 +3752,7 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_sub(vu, vv) } @@ -3751,7 +3764,7 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubw_dv(vuu, vvv) } @@ -3763,7 +3776,7 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubwsat(vu, vv) } @@ -3775,7 +3788,7 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubwsat_dv(vuu, vvv) } @@ -3787,7 +3800,7 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyb(vuu, rt) } @@ -3799,7 +3812,7 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwbrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3815,7 +3828,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpybus(vuu, rt) } @@ -3827,7 +3840,7 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3843,7 +3856,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyhb(vuu, rt) } @@ -3855,7 +3868,7 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3871,7 +3884,7 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { vunpackb(vu) } @@ -3883,7 +3896,7 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { vunpackh(vu) } @@ -3895,7 +3908,7 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackob(vxx, vu) } @@ -3907,7 +3920,7 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackoh(vxx, vu) } @@ -3919,7 +3932,7 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { vunpackub(vu) } @@ -3931,7 +3944,7 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { vunpackuh(vu) } @@ -3943,7 +3956,7 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vxor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_xor(vu, vv) } @@ -3955,7 +3968,7 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { vzb(vu) } @@ -3967,7 +3980,7 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { vzh(vu) } @@ -3979,7 +3992,7 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplatb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { lvsplatb(rt) } @@ -3991,7 +4004,7 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplath))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { lvsplath(rt) } @@ -4003,7 +4016,7 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddbsat(vu, vv) } @@ -4015,7 +4028,7 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddbsat_dv(vuu, vvv) } @@ -4027,7 +4040,7 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbh(vu, vv) } @@ -4039,7 +4052,7 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbw(vu, vv) } @@ -4051,7 +4064,7 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvhvh( +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4067,7 +4080,7 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddubh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vaddacc_whvubvub( +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4083,7 +4096,7 @@ pub unsafe fn q6_wh_vaddacc_whvubvub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddububb_sat(vu, vv) } @@ -4095,7 +4108,7 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvuhvuh( +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4111,7 +4124,7 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduwsat(vu, vv) } @@ -4123,7 +4136,7 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduwsat_dv(vuu, vvv) } @@ -4135,7 +4148,7 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrhbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbsat(vu, vv, rt) } @@ -4147,7 +4160,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasruwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhrndsat(vu, vv, rt) } @@ -4159,7 +4172,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhrndsat(vu, vv, rt) } @@ -4171,7 +4184,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlsrb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { vlsrb(vu, rt) } @@ -4183,7 +4196,7 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb_nm(vu, vv, rt) } @@ -4195,7 +4208,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbi( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -4212,7 +4225,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlutvvbi(vu, vv, iu3) } @@ -4224,7 +4237,7 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh_nm(vu, vv, rt) } @@ -4236,7 +4249,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhi( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4253,7 +4266,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwhi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { vlutvwhi(vu, vv, iu3) } @@ -4265,7 +4278,7 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmaxb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxb(vu, vv) } @@ -4277,7 +4290,7 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vminb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vminb(vu, vv) } @@ -4289,7 +4302,7 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpauhb(vuu, rt) } @@ -4301,7 +4314,7 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwuhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4317,7 +4330,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyewuh_64))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyewuh_64(vu, vv) } @@ -4329,7 +4342,7 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub(vu, rt) } @@ -4341,7 +4354,7 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub_acc(vx, vu, rt) } @@ -4353,7 +4366,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyowh_64_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpyoacc_wvwvh( +pub unsafe fn Q6_W_vmpyoacc_WVwVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4369,7 +4382,7 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduhub(vu, vv) } @@ -4381,7 +4394,7 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduwuh(vu, vv) } @@ -4393,7 +4406,7 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsatuwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatuwuh(vu, vv) } @@ -4405,7 +4418,7 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubbsat(vu, vv) } @@ -4417,7 +4430,7 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubbsat_dv(vuu, vvv) } @@ -4429,7 +4442,7 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubububb_sat(vu, vv) } @@ -4441,7 +4454,7 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuwsat(vu, vv) } @@ -4453,7 +4466,7 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuwsat_dv(vuu, vvv) } @@ -4465,7 +4478,7 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { vabsb(vu) } @@ -4477,7 +4490,7 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { vabsb_sat(vu) } @@ -4489,7 +4502,7 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vaslh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslh_acc(vx, vu, rt) } @@ -4501,7 +4514,7 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasrh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrh_acc(vx, vu, rt) } @@ -4513,7 +4526,7 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubrndsat(vu, vv, rt) } @@ -4525,7 +4538,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubsat(vu, vv, rt) } @@ -4537,7 +4550,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhsat(vu, vv, rt) } @@ -4549,7 +4562,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgb(vu, vv) } @@ -4561,7 +4574,7 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgbrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgbrnd(vu, vv) } @@ -4573,7 +4586,7 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguw(vu, vv) } @@ -4585,7 +4598,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguwrnd(vu, vv) } @@ -4597,7 +4610,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vdd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vzero() -> HvxVectorPair { +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { vdd0() } @@ -4609,7 +4622,7 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermh(rs, rt, mu, vv) } @@ -4621,7 +4634,7 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { vgathermhw(rs, rt, mu, vvv) } @@ -4633,7 +4646,7 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermw(rs, rt, mu, vv) } @@ -4645,7 +4658,7 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabuu(vuu, rt) } @@ -4657,7 +4670,7 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrub( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4673,7 +4686,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh_acc(vxx, vu, rt) } @@ -4685,7 +4698,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe(vu, rt) } @@ -4697,7 +4710,7 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe_acc(vx, vu, rt) } @@ -4709,7 +4722,7 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vnavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgb(vu, vv) } @@ -4721,7 +4734,7 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh(rt, mu, vv, vw) } @@ -4733,7 +4746,7 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh_add(rt, mu, vv, vw) } @@ -4745,7 +4758,7 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw(rt, mu, vvv, vw) } @@ -4757,7 +4770,7 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw_add(rt, mu, vvv, vw) } @@ -4769,7 +4782,7 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw(rt, mu, vv, vw) } @@ -4781,7 +4794,7 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw_add(rt, mu, vv, vw) } @@ -4793,7 +4806,7 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vasr_into))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vasrinto_wwvwvw( +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4809,7 +4822,7 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vrotr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vrotr(vu, vv) } @@ -4821,7 +4834,7 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vsatdw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatdw(vu, vv) } @@ -4833,7 +4846,7 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_h( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4849,7 +4862,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4866,7 +4879,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_v( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4882,7 +4895,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4899,7 +4912,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { vabs_hf(vu) } @@ -4911,7 +4924,7 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { vabs_sf(vu) } @@ -4923,7 +4936,7 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf(vu, vv) } @@ -4935,7 +4948,7 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf_hf(vu, vv) } @@ -4947,7 +4960,7 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16(vu, vv) } @@ -4959,7 +4972,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16_mix(vu, vv) } @@ -4971,7 +4984,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32(vu, vv) } @@ -4983,7 +4996,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32_mix(vu, vv) } @@ -4995,7 +5008,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf(vu, vv) } @@ -5007,7 +5020,7 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadd_sf_hf(vu, vv) } @@ -5019,7 +5032,7 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf_sf(vu, vv) } @@ -5031,7 +5044,7 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vassign_fp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { vassign_fp(vu) } @@ -5043,7 +5056,7 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { vconv_hf_qf16(vu) } @@ -5055,7 +5068,7 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { vconv_hf_qf32(vuu) } @@ -5067,7 +5080,7 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_sf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { vconv_sf_qf32(vu) } @@ -5079,7 +5092,7 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_b_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_b_hf(vu, vv) } @@ -5091,7 +5104,7 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_h_hf(vu) } @@ -5103,7 +5116,7 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { vcvt_hf_b(vu) } @@ -5115,7 +5128,7 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { vcvt_hf_h(vu) } @@ -5127,7 +5140,7 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_hf_sf(vu, vv) } @@ -5139,7 +5152,7 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { vcvt_hf_ub(vu) } @@ -5151,7 +5164,7 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_uh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { vcvt_hf_uh(vu) } @@ -5163,7 +5176,7 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { vcvt_sf_hf(vu) } @@ -5175,7 +5188,7 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_ub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_ub_hf(vu, vv) } @@ -5187,7 +5200,7 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_uh_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_uh_hf(vu) } @@ -5199,7 +5212,7 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf(vu, vv) } @@ -5211,7 +5224,7 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf_acc(vx, vu, vv) } @@ -5223,7 +5236,7 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_hf(vu, vv) } @@ -5235,7 +5248,7 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_sf(vu, vv) } @@ -5247,7 +5260,7 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_hf(vu, vv) } @@ -5259,7 +5272,7 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_sf(vu, vv) } @@ -5271,7 +5284,7 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { vfneg_hf(vu) } @@ -5283,7 +5296,7 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { vfneg_sf(vu) } @@ -5295,7 +5308,7 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_hf(vu, vv) } @@ -5307,7 +5320,7 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_sf(vu, vv) } @@ -5319,7 +5332,7 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_hf(vu, vv) } @@ -5331,7 +5344,7 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_sf(vu, vv) } @@ -5343,7 +5356,7 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf(vu, vv) } @@ -5355,7 +5368,7 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf_acc(vx, vu, vv) } @@ -5367,7 +5380,7 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16(vu, vv) } @@ -5379,7 +5392,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_hf(vu, vv) } @@ -5391,7 +5404,7 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_mix_hf(vu, vv) } @@ -5403,7 +5416,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32(vu, vv) } @@ -5415,7 +5428,7 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_hf(vu, vv) } @@ -5427,7 +5440,7 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_mix_hf(vu, vv) } @@ -5439,7 +5452,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_qf16(vu, vv) } @@ -5451,7 +5464,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32_sf(vu, vv) } @@ -5463,7 +5476,7 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_sf_hf(vu, vv) } @@ -5475,7 +5488,7 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -5491,7 +5504,7 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_sf_sf(vu, vv) } @@ -5503,7 +5516,7 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf(vu, vv) } @@ -5515,7 +5528,7 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf_hf(vu, vv) } @@ -5527,7 +5540,7 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16(vu, vv) } @@ -5539,7 +5552,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16_mix(vu, vv) } @@ -5551,7 +5564,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32(vu, vv) } @@ -5563,7 +5576,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32_mix(vu, vv) } @@ -5575,7 +5588,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf(vu, vv) } @@ -5587,7 +5600,7 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsub_sf_hf(vu, vv) } @@ -5599,7 +5612,7 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf_sf(vu, vv) } @@ -5611,7 +5624,7 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubrndsat(vuu, vv) } @@ -5623,7 +5636,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubsat(vuu, vv) } @@ -5635,7 +5648,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhrndsat(vuu, vv) } @@ -5647,7 +5660,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhsat(vuu, vv) } @@ -5659,7 +5672,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vmpyuhvs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyuhvs(vu, vv) } @@ -5671,7 +5684,7 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { vconv_h_hf(vu) } @@ -5683,7 +5696,7 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { vconv_hf_h(vu) } @@ -5695,7 +5708,7 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_sf_w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { vconv_sf_w(vu) } @@ -5707,7 +5720,7 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_w_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { vconv_w_sf(vu) } @@ -5719,7 +5732,7 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(get_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { get_qfext(vu, rt) } @@ -5731,7 +5744,7 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(set_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { set_qfext(vu, rt) } @@ -5743,7 +5756,7 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vabs_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { vabs_f8(vu) } @@ -5755,7 +5768,7 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_b(vu) } @@ -5767,7 +5780,7 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_ub(vu) } @@ -5779,7 +5792,7 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt_hf_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { vcvt_hf_f8(vu) } @@ -5791,7 +5804,7 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmax_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_f8(vu, vv) } @@ -5803,7 +5816,7 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmin_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_f8(vu, vv) } @@ -5815,7 +5828,7 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfneg_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { vfneg_f8(vu) } @@ -5827,7 +5840,7 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and( vandvrt(core::mem::transmute::(qs), -1), @@ -5845,7 +5858,7 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5863,7 +5876,7 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_not(vandvrt( core::mem::transmute::(qs), @@ -5881,7 +5894,7 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or( vandvrt(core::mem::transmute::(qs), -1), @@ -5899,7 +5912,7 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5917,7 +5930,7 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) } @@ -5929,7 +5942,7 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_xor( vandvrt(core::mem::transmute::(qs), -1), @@ -5947,7 +5960,7 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5963,7 +5976,7 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5979,7 +5992,7 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5995,7 +6008,7 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -6011,7 +6024,7 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6027,7 +6040,7 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6043,7 +6056,7 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6059,7 +6072,7 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6075,7 +6088,7 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6091,7 +6104,7 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6107,7 +6120,7 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt(core::mem::transmute::(qu), rt) } @@ -6119,7 +6132,7 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt_acc(vx, core::mem::transmute::(qu), rt) } @@ -6131,7 +6144,7 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(vu, rt)) } @@ -6143,7 +6156,7 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt_acc( core::mem::transmute::(qx), vu, @@ -6159,7 +6172,7 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) } @@ -6171,7 +6184,7 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6194,7 +6207,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6217,7 +6230,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6240,7 +6253,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) } @@ -6252,7 +6265,7 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6275,7 +6288,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6298,7 +6311,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6321,7 +6334,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) } @@ -6333,7 +6346,7 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6356,7 +6369,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6379,7 +6392,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6402,7 +6415,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) } @@ -6414,7 +6427,7 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6437,7 +6450,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6460,7 +6473,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6483,7 +6496,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) } @@ -6495,7 +6508,7 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6518,7 +6531,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6541,7 +6554,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6564,7 +6577,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) } @@ -6576,7 +6589,7 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6599,7 +6612,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6622,7 +6635,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6645,7 +6658,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) } @@ -6657,7 +6670,7 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6680,7 +6693,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6703,7 +6716,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6726,7 +6739,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) } @@ -6738,7 +6751,7 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6761,7 +6774,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6784,7 +6797,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6807,7 +6820,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) } @@ -6819,7 +6832,7 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6842,7 +6855,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6865,7 +6878,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6888,7 +6901,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { vmux( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -6904,7 +6917,7 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6920,7 +6933,7 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6936,7 +6949,7 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6952,7 +6965,7 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6968,7 +6981,7 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6984,7 +6997,7 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -7000,7 +7013,7 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vswap( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -7016,7 +7029,7 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) } @@ -7028,7 +7041,7 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqh( vandvrt(core::mem::transmute::(qs), -1), @@ -7046,7 +7059,7 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqw( vandvrt(core::mem::transmute::(qs), -1), @@ -7064,7 +7077,7 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt( vandvrt(core::mem::transmute::(qu), -1), rt, @@ -7079,7 +7092,7 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt_acc( vx, vandvrt(core::mem::transmute::(qu), -1), @@ -7095,7 +7108,7 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvnqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7110,7 +7123,7 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7125,7 +7138,7 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvh( +pub unsafe fn Q6_vgather_AQRMVh( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7149,7 +7162,7 @@ pub unsafe fn q6_vgather_aqrmvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmww( +pub unsafe fn Q6_vgather_AQRMWw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7173,7 +7186,7 @@ pub unsafe fn q6_vgather_aqrmww( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvw( +pub unsafe fn Q6_vgather_AQRMVw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7197,7 +7210,7 @@ pub unsafe fn q6_vgather_aqrmvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqb(vandvrt( core::mem::transmute::(qv), -1, @@ -7212,7 +7225,7 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqh(vandvrt( core::mem::transmute::(qv), -1, @@ -7227,7 +7240,7 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqw(vandvrt( core::mem::transmute::(qv), -1, @@ -7242,7 +7255,7 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvhv( +pub unsafe fn Q6_vscatter_QRMVhV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7266,7 +7279,7 @@ pub unsafe fn q6_vscatter_qrmvhv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmwwv( +pub unsafe fn Q6_vscatter_QRMWwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7290,7 +7303,7 @@ pub unsafe fn q6_vscatter_qrmwwv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvwv( +pub unsafe fn Q6_vscatter_QRMVwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7314,7 +7327,7 @@ pub unsafe fn q6_vscatter_qrmvwv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( vu: HvxVector, vv: HvxVector, qs: HvxVectorPred, @@ -7334,7 +7347,7 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) } @@ -7346,7 +7359,7 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7369,7 +7382,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7392,7 +7405,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7415,7 +7428,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) } @@ -7427,7 +7440,7 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7450,7 +7463,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7473,7 +7486,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, diff --git a/library/stdarch/crates/core_arch/src/hexagon/v64.rs b/library/stdarch/crates/core_arch/src/hexagon/v64.rs index 023a8711d21f..517a807db4ae 100644 --- a/library/stdarch/crates/core_arch/src/hexagon/v64.rs +++ b/library/stdarch/crates/core_arch/src/hexagon/v64.rs @@ -15,6 +15,18 @@ //! //! To use this module, compile with `-C target-feature=+hvx-length64b`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -31,6 +43,7 @@ //! Each version includes all features from previous versions. #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1034,7 +1047,7 @@ fn v6mpyvubs10_vxx( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(extractw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { +pub unsafe fn Q6_R_vextract_VR(vu: HvxVector, rs: i32) -> i32 { extractw(vu, rs) } @@ -1046,7 +1059,7 @@ pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(hi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_hi_W(vss: HvxVectorPair) -> HvxVector { hi(vss) } @@ -1058,7 +1071,7 @@ pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lo))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_V_lo_W(vss: HvxVectorPair) -> HvxVector { lo(vss) } @@ -1070,7 +1083,7 @@ pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(lvsplatw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsplat_R(rt: i32) -> HvxVector { lvsplatw(rt) } @@ -1082,7 +1095,7 @@ pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffh(vu, vv) } @@ -1094,7 +1107,7 @@ pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vabsdiff_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffub(vu, vv) } @@ -1106,7 +1119,7 @@ pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vabsdiff_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffuh(vu, vv) } @@ -1118,7 +1131,7 @@ pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsdiffw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vabsdiff_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vabsdiffw(vu, vv) } @@ -1130,7 +1143,7 @@ pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh(vu: HvxVector) -> HvxVector { vabsh(vu) } @@ -1142,7 +1155,7 @@ pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vabs_Vh_sat(vu: HvxVector) -> HvxVector { vabsh_sat(vu) } @@ -1154,7 +1167,7 @@ pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw(vu: HvxVector) -> HvxVector { vabsw(vu) } @@ -1166,7 +1179,7 @@ pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vabsw_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vabs_Vw_sat(vu: HvxVector) -> HvxVector { vabsw_sat(vu) } @@ -1178,7 +1191,7 @@ pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddb(vu, vv) } @@ -1190,7 +1203,7 @@ pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddb_dv(vuu, vvv) } @@ -1202,7 +1215,7 @@ pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddh(vu, vv) } @@ -1214,7 +1227,7 @@ pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddh_dv(vuu, vvv) } @@ -1226,7 +1239,7 @@ pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddhsat(vu, vv) } @@ -1238,7 +1251,7 @@ pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddhsat_dv(vuu, vvv) } @@ -1250,7 +1263,7 @@ pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddhw(vu, vv) } @@ -1262,7 +1275,7 @@ pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vadd_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vaddubh(vu, vv) } @@ -1274,7 +1287,7 @@ pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddubsat(vu, vv) } @@ -1286,7 +1299,7 @@ pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddubsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vadd_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddubsat_dv(vuu, vvv) } @@ -1298,7 +1311,7 @@ pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vadd_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduhsat(vu, vv) } @@ -1310,7 +1323,7 @@ pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vadd_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduhsat_dv(vuu, vvv) } @@ -1322,7 +1335,7 @@ pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vadduhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadduhw(vu, vv) } @@ -1334,7 +1347,7 @@ pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_add(vu, vv) } @@ -1346,7 +1359,7 @@ pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddw_dv(vuu, vvv) } @@ -1358,7 +1371,7 @@ pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddwsat(vu, vv) } @@ -1370,7 +1383,7 @@ pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaddwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vadd_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddwsat_dv(vuu, vvv) } @@ -1382,7 +1395,7 @@ pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { valignb(vu, vv, rt) } @@ -1394,7 +1407,7 @@ pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(valignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_valign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { valignbi(vu, vv, iu3) } @@ -1406,7 +1419,7 @@ pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vand))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_and(vu, vv) } @@ -1418,7 +1431,7 @@ pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhR(vu: HvxVector, rt: i32) -> HvxVector { vaslh(vu, rt) } @@ -1430,7 +1443,7 @@ pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasl_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslhv(vu, vv) } @@ -1442,7 +1455,7 @@ pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwR(vu: HvxVector, rt: i32) -> HvxVector { vaslw(vu, rt) } @@ -1454,7 +1467,7 @@ pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vaslacc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslw_acc(vx, vu, rt) } @@ -1466,7 +1479,7 @@ pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vaslwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasl_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaslwv(vu, vv) } @@ -1478,7 +1491,7 @@ pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhR(vu: HvxVector, rt: i32) -> HvxVector { vasrh(vu, rt) } @@ -1490,7 +1503,7 @@ pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhbrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbrndsat(vu, vv, rt) } @@ -1502,7 +1515,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubrndsat(vu, vv, rt) } @@ -1514,7 +1527,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhubsat(vu, vv, rt) } @@ -1526,7 +1539,7 @@ pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrhv(vu, vv) } @@ -1538,7 +1551,7 @@ pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwR(vu: HvxVector, rt: i32) -> HvxVector { vasrw(vu, rt) } @@ -1550,7 +1563,7 @@ pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vasracc_VwVwR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrw_acc(vx, vu, rt) } @@ -1562,7 +1575,7 @@ pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwh(vu, vv, rt) } @@ -1574,7 +1587,7 @@ pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhrndsat(vu, vv, rt) } @@ -1586,7 +1599,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwhsat(vu, vv, rt) } @@ -1598,7 +1611,7 @@ pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhsat(vu, vv, rt) } @@ -1610,7 +1623,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vasrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vasr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vasrwv(vu, vv) } @@ -1622,7 +1635,7 @@ pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassign))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_equals_V(vu: HvxVector) -> HvxVector { vassign(vu) } @@ -1634,7 +1647,7 @@ pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vassignp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_W_equals_W(vuu: HvxVectorPair) -> HvxVectorPair { vassignp(vuu) } @@ -1646,7 +1659,7 @@ pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgh(vu, vv) } @@ -1658,7 +1671,7 @@ pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavghrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vavg_VhVh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavghrnd(vu, vv) } @@ -1670,7 +1683,7 @@ pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgub(vu, vv) } @@ -1682,7 +1695,7 @@ pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgubrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vavg_VubVub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgubrnd(vu, vv) } @@ -1694,7 +1707,7 @@ pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguh(vu, vv) } @@ -1706,7 +1719,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavguhrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vavg_VuhVuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguhrnd(vu, vv) } @@ -1718,7 +1731,7 @@ pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgw(vu, vv) } @@ -1730,7 +1743,7 @@ pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vavgwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vavg_VwVw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgwrnd(vu, vv) } @@ -1742,7 +1755,7 @@ pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcl0_Vuh(vu: HvxVector) -> HvxVector { vcl0h(vu) } @@ -1754,7 +1767,7 @@ pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcl0w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vcl0_Vuw(vu: HvxVector) -> HvxVector { vcl0w(vu) } @@ -1766,7 +1779,7 @@ pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vcombine))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vcombine_VV(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vcombine(vu, vv) } @@ -1778,7 +1791,7 @@ pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vzero() -> HvxVector { +pub unsafe fn Q6_V_vzero() -> HvxVector { vd0() } @@ -1790,7 +1803,7 @@ pub unsafe fn q6_v_vzero() -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeal_Vb(vu: HvxVector) -> HvxVector { vdealb(vu) } @@ -1802,7 +1815,7 @@ pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealb4w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vdeale_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vdealb4w(vu, vv) } @@ -1814,7 +1827,7 @@ pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vdeal_Vh(vu: HvxVector) -> HvxVector { vdealh(vu) } @@ -1826,7 +1839,7 @@ pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdealvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vdeal_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vdealvdd(vu, vv, rt) } @@ -1838,7 +1851,7 @@ pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vdelta(vu, vv) } @@ -1850,7 +1863,7 @@ pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpybus(vu, rt) } @@ -1862,7 +1875,7 @@ pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vdmpyacc_VhVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpybus_acc(vx, vu, rt) } @@ -1874,7 +1887,7 @@ pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vdmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpybus_dv(vuu, rt) } @@ -1886,7 +1899,7 @@ pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vdmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vdmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1902,7 +1915,7 @@ pub unsafe fn q6_wh_vdmpyacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb(vu, rt) } @@ -1914,7 +1927,7 @@ pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhb_acc(vx, vu, rt) } @@ -1926,7 +1939,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vdmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdmpyhb_dv(vuu, rt) } @@ -1938,7 +1951,7 @@ pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vdmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vdmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -1954,7 +1967,7 @@ pub unsafe fn q6_ww_vdmpyacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat(vuu, rt) } @@ -1966,7 +1979,7 @@ pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhisat_acc(vx, vuu, rt) } @@ -1978,7 +1991,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat(vu, rt) } @@ -1990,7 +2003,7 @@ pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsat_acc(vx, vu, rt) } @@ -2002,7 +2015,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_WhRuh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat(vuu, rt) } @@ -2014,7 +2027,7 @@ pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwWhRuh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { vdmpyhsuisat_acc(vx, vuu, rt) } @@ -2026,7 +2039,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhRuh_sat(vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat(vu, rt) } @@ -2038,7 +2051,7 @@ pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhRuh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vdmpyhsusat_acc(vx, vu, rt) } @@ -2050,7 +2063,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpy_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat(vu, vv) } @@ -2062,7 +2075,7 @@ pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vdmpyacc_VwVhVh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpyhvsat_acc(vx, vu, vv) } @@ -2074,7 +2087,7 @@ pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vdsad_WuhRuh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vdsaduh(vuu, rt) } @@ -2086,7 +2099,7 @@ pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vdsaduh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( +pub unsafe fn Q6_Wuw_vdsadacc_WuwWuhRuh( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2102,7 +2115,7 @@ pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vinsertwr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vinsert_VwR(vx: HvxVector, rt: i32) -> HvxVector { vinsertwr(vx, rt) } @@ -2114,7 +2127,7 @@ pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlalignb(vu, vv, rt) } @@ -2126,7 +2139,7 @@ pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlalignbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_V_vlalign_VVI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlalignbi(vu, vv, iu3) } @@ -2138,7 +2151,7 @@ pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vlsr_VuhR(vu: HvxVector, rt: i32) -> HvxVector { vlsrh(vu, rt) } @@ -2150,7 +2163,7 @@ pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vlsr_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrhv(vu, vv) } @@ -2162,7 +2175,7 @@ pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vlsr_VuwR(vu: HvxVector, rt: i32) -> HvxVector { vlsrw(vu, rt) } @@ -2174,7 +2187,7 @@ pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlsrwv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vlsr_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vlsrwv(vu, vv) } @@ -2186,7 +2199,7 @@ pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb(vu, vv, rt) } @@ -2198,7 +2211,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvvb_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbr( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbR( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2215,7 +2228,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbr( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh(vu, vv, rt) } @@ -2227,7 +2240,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vlutvwh_oracc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhr( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhR( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2244,7 +2257,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhr( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmax_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxh(vu, vv) } @@ -2256,7 +2269,7 @@ pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmax_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxub(vu, vv) } @@ -2268,7 +2281,7 @@ pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmax_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxuh(vu, vv) } @@ -2280,7 +2293,7 @@ pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmaxw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmax_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxw(vu, vv) } @@ -2292,7 +2305,7 @@ pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmin_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminh(vu, vv) } @@ -2304,7 +2317,7 @@ pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vmin_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vminub(vu, vv) } @@ -2316,7 +2329,7 @@ pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmin_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vminuh(vu, vv) } @@ -2328,7 +2341,7 @@ pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vminw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmin_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vminw(vu, vv) } @@ -2340,7 +2353,7 @@ pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabus(vuu, rt) } @@ -2352,7 +2365,7 @@ pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrb( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2368,7 +2381,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabusv(vuu, vvv) } @@ -2380,7 +2393,7 @@ pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpabuuv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubWub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vmpabuuv(vuu, vvv) } @@ -2392,7 +2405,7 @@ pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpahb(vuu, rt) } @@ -2404,7 +2417,7 @@ pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpahb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -2420,7 +2433,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus(vu, rt) } @@ -2432,7 +2445,7 @@ pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpyacc_WhVubRb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpybus_acc(vxx, vu, rt) } @@ -2444,7 +2457,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybusv(vu, vv) } @@ -2456,7 +2469,7 @@ pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvubvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVubVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2472,7 +2485,7 @@ pub unsafe fn q6_wh_vmpyacc_whvubvb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpybv(vu, vv) } @@ -2484,7 +2497,7 @@ pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpyacc_whvbvb( +pub unsafe fn Q6_Wh_vmpyacc_WhVbVb( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2500,7 +2513,7 @@ pub unsafe fn q6_wh_vmpyacc_whvbvb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyewuh(vu, vv) } @@ -2512,7 +2525,7 @@ pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhRh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh(vu, rt) } @@ -2524,7 +2537,7 @@ pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsat_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh_sat( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2540,7 +2553,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhsrs(vu, rt) } @@ -2552,7 +2565,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhss))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhRh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { vmpyhss(vu, rt) } @@ -2564,7 +2577,7 @@ pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhus(vu, vv) } @@ -2576,7 +2589,7 @@ pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvuh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2592,7 +2605,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpy_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyhv(vu, vv) } @@ -2604,7 +2617,7 @@ pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhvh( +pub unsafe fn Q6_Ww_vmpyacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2620,7 +2633,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyhvsrs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpy_VhVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyhvsrs(vu, vv) } @@ -2632,7 +2645,7 @@ pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyieoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyieoh(vu, vv) } @@ -2644,7 +2657,7 @@ pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewh_acc(vx, vu, vv) } @@ -2656,7 +2669,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyie_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh(vu, vv) } @@ -2668,7 +2681,7 @@ pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiewuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyieacc_VwVwVuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiewuh_acc(vx, vu, vv) } @@ -2680,7 +2693,7 @@ pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih(vu, vv) } @@ -2692,7 +2705,7 @@ pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyih_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhVh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyih_acc(vx, vu, vv) } @@ -2704,7 +2717,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyi_VhRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyihb(vu, rt) } @@ -2716,7 +2729,7 @@ pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyihb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vmpyiacc_VhVhRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyihb_acc(vx, vu, rt) } @@ -2728,7 +2741,7 @@ pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyio_VwVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyiowh(vu, vv) } @@ -2740,7 +2753,7 @@ pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRb(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb(vu, rt) } @@ -2752,7 +2765,7 @@ pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwb_acc(vx, vu, rt) } @@ -2764,7 +2777,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRh(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh(vu, rt) } @@ -2776,7 +2789,7 @@ pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyiwh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwh_acc(vx, vu, rt) } @@ -2788,7 +2801,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh(vu, vv) } @@ -2800,7 +2813,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyo_VwVh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyowh_rnd(vu, vv) } @@ -2812,7 +2825,7 @@ pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2828,7 +2841,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyowh_sacc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( +pub unsafe fn Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -2844,7 +2857,7 @@ pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyub(vu, rt) } @@ -2856,7 +2869,7 @@ pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubRub( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2872,7 +2885,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyubv(vu, vv) } @@ -2884,7 +2897,7 @@ pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( +pub unsafe fn Q6_Wuh_vmpyacc_WuhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2900,7 +2913,7 @@ pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhRuh(vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyuh(vu, rt) } @@ -2912,7 +2925,7 @@ pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhRuh( vxx: HvxVectorPair, vu: HvxVector, rt: i32, @@ -2928,7 +2941,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vmpy_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyuhv(vu, vv) } @@ -2940,7 +2953,7 @@ pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vmpyuhv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( +pub unsafe fn Q6_Wuw_vmpyacc_WuwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -2956,7 +2969,7 @@ pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnavg_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgh(vu, vv) } @@ -2968,7 +2981,7 @@ pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgub(vu, vv) } @@ -2980,7 +2993,7 @@ pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnavgw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnavg_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgw(vu, vv) } @@ -2992,7 +3005,7 @@ pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vnormamt_Vh(vu: HvxVector) -> HvxVector { vnormamth(vu) } @@ -3004,7 +3017,7 @@ pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnormamtw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vnormamt_Vw(vu: HvxVector) -> HvxVector { vnormamtw(vu) } @@ -3016,7 +3029,7 @@ pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vnot))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vnot_V(vu: HvxVector) -> HvxVector { vnot(vu) } @@ -3028,7 +3041,7 @@ pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_or(vu, vv) } @@ -3040,7 +3053,7 @@ pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacke_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeb(vu, vv) } @@ -3052,7 +3065,7 @@ pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacke_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackeh(vu, vv) } @@ -3064,7 +3077,7 @@ pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhb_sat(vu, vv) } @@ -3076,7 +3089,7 @@ pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackhub_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vpack_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackhub_sat(vu, vv) } @@ -3088,7 +3101,7 @@ pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vpacko_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackob(vu, vv) } @@ -3100,7 +3113,7 @@ pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpacko_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackoh(vu, vv) } @@ -3112,7 +3125,7 @@ pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwh_sat(vu, vv) } @@ -3124,7 +3137,7 @@ pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpackwuh_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vpack_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vpackwuh_sat(vu, vv) } @@ -3136,7 +3149,7 @@ pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vpopcounth))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vpopcount_Vh(vu: HvxVector) -> HvxVector { vpopcounth(vu) } @@ -3148,7 +3161,7 @@ pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrdelta))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vrdelta_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vrdelta(vu, vv) } @@ -3160,7 +3173,7 @@ pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubRb(vu: HvxVector, rt: i32) -> HvxVector { vrmpybus(vu, rt) } @@ -3172,7 +3185,7 @@ pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubRb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpybus_acc(vx, vu, rt) } @@ -3184,7 +3197,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vrmpy_WubRbI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpybusi(vuu, rt, iu1) } @@ -3196,7 +3209,7 @@ pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( +pub unsafe fn Q6_Ww_vrmpyacc_WwWubRbI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3213,7 +3226,7 @@ pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VubVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv(vu, vv) } @@ -3225,7 +3238,7 @@ pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybusv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVubVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybusv_acc(vx, vu, vv) } @@ -3237,7 +3250,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpy_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv(vu, vv) } @@ -3249,7 +3262,7 @@ pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpybv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vrmpyacc_VwVbVb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpybv_acc(vx, vu, vv) } @@ -3261,7 +3274,7 @@ pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubRub(vu: HvxVector, rt: i32) -> HvxVector { vrmpyub(vu, rt) } @@ -3273,7 +3286,7 @@ pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vrmpyub_acc(vx, vu, rt) } @@ -3285,7 +3298,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrmpy_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrmpyubi(vuu, rt, iu1) } @@ -3297,7 +3310,7 @@ pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrmpyacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3314,7 +3327,7 @@ pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpy_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv(vu, vv) } @@ -3326,7 +3339,7 @@ pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrmpyubv_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrmpyacc_VuwVubVub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vrmpyubv_acc(vx, vu, vv) } @@ -3338,7 +3351,7 @@ pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vror))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vror_VR(vu: HvxVector, rt: i32) -> HvxVector { vror(vu, rt) } @@ -3350,7 +3363,7 @@ pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhb(vu, vv) } @@ -3362,7 +3375,7 @@ pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundhub(vu, vv) } @@ -3374,7 +3387,7 @@ pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwh(vu, vv) } @@ -3386,7 +3399,7 @@ pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vroundwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vroundwuh(vu, vv) } @@ -3398,7 +3411,7 @@ pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vrsad_WubRubI(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { vrsadubi(vuu, rt, iu1) } @@ -3410,7 +3423,7 @@ pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vrsadubi_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( +pub unsafe fn Q6_Wuw_vrsadacc_WuwWubRubI( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3427,7 +3440,7 @@ pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsathub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsat_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsathub(vu, vv) } @@ -3439,7 +3452,7 @@ pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsatwh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsat_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatwh(vu, vv) } @@ -3451,7 +3464,7 @@ pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsxt_Vb(vu: HvxVector) -> HvxVectorPair { vsb(vu) } @@ -3463,7 +3476,7 @@ pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsxt_Vh(vu: HvxVector) -> HvxVectorPair { vsh(vu) } @@ -3475,7 +3488,7 @@ pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufeh(vu, vv) } @@ -3487,7 +3500,7 @@ pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuff_Vb(vu: HvxVector) -> HvxVector { vshuffb(vu) } @@ -3499,7 +3512,7 @@ pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffeb(vu, vv) } @@ -3511,7 +3524,7 @@ pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuff_Vh(vu: HvxVector) -> HvxVector { vshuffh(vu) } @@ -3523,7 +3536,7 @@ pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vshuffo_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vshuffob(vu, vv) } @@ -3535,7 +3548,7 @@ pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshuffvdd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_W_vshuff_VVR(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vshuffvdd(vu, vv, rt) } @@ -3547,7 +3560,7 @@ pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vshuffoe_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeb(vu, vv) } @@ -3559,7 +3572,7 @@ pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoeh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vshuffoe_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vshufoeh(vu, vv) } @@ -3571,7 +3584,7 @@ pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vshufoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vshuffo_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vshufoh(vu, vv) } @@ -3583,7 +3596,7 @@ pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubb(vu, vv) } @@ -3595,7 +3608,7 @@ pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubb_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubb_dv(vuu, vvv) } @@ -3607,7 +3620,7 @@ pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubh(vu, vv) } @@ -3619,7 +3632,7 @@ pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubh_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubh_dv(vuu, vvv) } @@ -3631,7 +3644,7 @@ pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vsub_VhVh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubhsat(vu, vv) } @@ -3643,7 +3656,7 @@ pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_WhWh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubhsat_dv(vuu, vvv) } @@ -3655,7 +3668,7 @@ pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubhw(vu, vv) } @@ -3667,7 +3680,7 @@ pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vsub_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsububh(vu, vv) } @@ -3679,7 +3692,7 @@ pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsububsat(vu, vv) } @@ -3691,7 +3704,7 @@ pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsububsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wub_vsub_WubWub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsububsat_dv(vuu, vvv) } @@ -3703,7 +3716,7 @@ pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsub_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuhsat(vu, vv) } @@ -3715,7 +3728,7 @@ pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vsub_WuhWuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuhsat_dv(vuu, vvv) } @@ -3727,7 +3740,7 @@ pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubuhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsubuhw(vu, vv) } @@ -3739,7 +3752,7 @@ pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_sub(vu, vv) } @@ -3751,7 +3764,7 @@ pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubw_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubw_dv(vuu, vvv) } @@ -3763,7 +3776,7 @@ pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsub_VwVw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubwsat(vu, vv) } @@ -3775,7 +3788,7 @@ pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vsubwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vsub_WwWw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubwsat_dv(vuu, vvv) } @@ -3787,7 +3800,7 @@ pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WbRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyb(vuu, rt) } @@ -3799,7 +3812,7 @@ pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwbrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWbRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3815,7 +3828,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwbrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vtmpy_WubRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpybus(vuu, rt) } @@ -3827,7 +3840,7 @@ pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpybus_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vtmpyacc_whwubrb( +pub unsafe fn Q6_Wh_vtmpyacc_WhWubRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3843,7 +3856,7 @@ pub unsafe fn q6_wh_vtmpyacc_whwubrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vtmpy_WhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vtmpyhb(vuu, rt) } @@ -3855,7 +3868,7 @@ pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vtmpyhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vtmpyacc_wwwhrb( +pub unsafe fn Q6_Ww_vtmpyacc_WwWhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -3871,7 +3884,7 @@ pub unsafe fn q6_ww_vtmpyacc_wwwhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpack_Vb(vu: HvxVector) -> HvxVectorPair { vunpackb(vu) } @@ -3883,7 +3896,7 @@ pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpack_Vh(vu: HvxVector) -> HvxVectorPair { vunpackh(vu) } @@ -3895,7 +3908,7 @@ pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackob))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vunpackoor_WhVb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackob(vxx, vu) } @@ -3907,7 +3920,7 @@ pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackoh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vunpackoor_WwVh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { vunpackoh(vxx, vu) } @@ -3919,7 +3932,7 @@ pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vunpack_Vub(vu: HvxVector) -> HvxVectorPair { vunpackub(vu) } @@ -3931,7 +3944,7 @@ pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vunpackuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vunpack_Vuh(vu: HvxVector) -> HvxVectorPair { vunpackuh(vu) } @@ -3943,7 +3956,7 @@ pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vxor))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vxor_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { simd_xor(vu, vv) } @@ -3955,7 +3968,7 @@ pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuh_vzxt_Vub(vu: HvxVector) -> HvxVectorPair { vzb(vu) } @@ -3967,7 +3980,7 @@ pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[cfg_attr(test, assert_instr(vzh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vzxt_Vuh(vu: HvxVector) -> HvxVectorPair { vzh(vu) } @@ -3979,7 +3992,7 @@ pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplatb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vsplat_R(rt: i32) -> HvxVector { lvsplatb(rt) } @@ -3991,7 +4004,7 @@ pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(lvsplath))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vsplat_R(rt: i32) -> HvxVector { lvsplath(rt) } @@ -4003,7 +4016,7 @@ pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vadd_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddbsat(vu, vv) } @@ -4015,7 +4028,7 @@ pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vadd_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vaddbsat_dv(vuu, vvv) } @@ -4027,7 +4040,7 @@ pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vadd_vclb_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbh(vu, vv) } @@ -4039,7 +4052,7 @@ pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddclbw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vadd_vclb_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddclbw(vu, vv) } @@ -4051,7 +4064,7 @@ pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvhvh( +pub unsafe fn Q6_Ww_vaddacc_WwVhVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4067,7 +4080,7 @@ pub unsafe fn q6_ww_vaddacc_wwvhvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddubh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vaddacc_whvubvub( +pub unsafe fn Q6_Wh_vaddacc_WhVubVub( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4083,7 +4096,7 @@ pub unsafe fn q6_wh_vaddacc_whvubvub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vaddububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vadd_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vaddububb_sat(vu, vv) } @@ -4095,7 +4108,7 @@ pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduhw_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vaddacc_wwvuhvuh( +pub unsafe fn Q6_Ww_vaddacc_WwVuhVuh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4111,7 +4124,7 @@ pub unsafe fn q6_ww_vaddacc_wwvuhvuh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vadd_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vadduwsat(vu, vv) } @@ -4123,7 +4136,7 @@ pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vadduwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vadd_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vadduwsat_dv(vuu, vvv) } @@ -4135,7 +4148,7 @@ pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrhbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vasr_VhVhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrhbsat(vu, vv, rt) } @@ -4147,7 +4160,7 @@ pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasruwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhrndsat(vu, vv, rt) } @@ -4159,7 +4172,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vasrwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VwVwR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasrwuhrndsat(vu, vv, rt) } @@ -4171,7 +4184,7 @@ pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlsrb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vlsr_VubR(vu: HvxVector, rt: i32) -> HvxVector { vlsrb(vu, rt) } @@ -4183,7 +4196,7 @@ pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vlutvvb_nm(vu, vv, rt) } @@ -4195,7 +4208,7 @@ pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvb_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32or_vbvbvbi( +pub unsafe fn Q6_Vb_vlut32or_VbVbVbI( vx: HvxVector, vu: HvxVector, vv: HvxVector, @@ -4212,7 +4225,7 @@ pub unsafe fn q6_vb_vlut32or_vbvbvbi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvvbi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { +pub unsafe fn Q6_Vb_vlut32_VbVbI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { vlutvvbi(vu, vv, iu3) } @@ -4224,7 +4237,7 @@ pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_nm))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhR_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { vlutvwh_nm(vu, vv, rt) } @@ -4236,7 +4249,7 @@ pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwh_oracci))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16or_whvbvhi( +pub unsafe fn Q6_Wh_vlut16or_WhVbVhI( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4253,7 +4266,7 @@ pub unsafe fn q6_wh_vlut16or_whvbvhi( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vlutvwhi))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vlut16_VbVhI(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { vlutvwhi(vu, vv, iu3) } @@ -4265,7 +4278,7 @@ pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmaxb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmax_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vmaxb(vu, vv) } @@ -4277,7 +4290,7 @@ pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vminb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vmin_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vminb(vu, vv) } @@ -4289,7 +4302,7 @@ pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpa_WuhRb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpauhb(vuu, rt) } @@ -4301,7 +4314,7 @@ pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpauhb_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpaacc_wwwuhrb( +pub unsafe fn Q6_Ww_vmpaacc_WwWuhRb( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4317,7 +4330,7 @@ pub unsafe fn q6_ww_vmpaacc_wwwuhrb( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyewuh_64))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vmpye_VwVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpyewuh_64(vu, vv) } @@ -4329,7 +4342,7 @@ pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyi_VwRub(vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub(vu, rt) } @@ -4341,7 +4354,7 @@ pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyiwub_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vw_vmpyiacc_VwVwRub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyiwub_acc(vx, vu, rt) } @@ -4353,7 +4366,7 @@ pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vmpyowh_64_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vmpyoacc_wvwvh( +pub unsafe fn Q6_W_vmpyoacc_WVwVh( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4369,7 +4382,7 @@ pub unsafe fn q6_w_vmpyoacc_wvwvh( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduhub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vround_VuhVuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduhub(vu, vv) } @@ -4381,7 +4394,7 @@ pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vrounduwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vround_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vrounduwuh(vu, vv) } @@ -4393,7 +4406,7 @@ pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsatuwuh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vsat_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatuwuh(vu, vv) } @@ -4405,7 +4418,7 @@ pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vsub_VbVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubbsat(vu, vv) } @@ -4417,7 +4430,7 @@ pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubbsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wb_vsub_WbWb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubbsat_dv(vuu, vvv) } @@ -4429,7 +4442,7 @@ pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubububb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vsub_VubVb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubububb_sat(vu, vv) } @@ -4441,7 +4454,7 @@ pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vsub_VuwVuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { vsubuwsat(vu, vv) } @@ -4453,7 +4466,7 @@ pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[cfg_attr(test, assert_instr(vsubuwsat_dv))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { +pub unsafe fn Q6_Wuw_vsub_WuwWuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { vsubuwsat_dv(vuu, vvv) } @@ -4465,7 +4478,7 @@ pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb(vu: HvxVector) -> HvxVector { vabsb(vu) } @@ -4477,7 +4490,7 @@ pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vabsb_sat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vabs_Vb_sat(vu: HvxVector) -> HvxVector { vabsb_sat(vu) } @@ -4489,7 +4502,7 @@ pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vaslh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vaslacc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vaslh_acc(vx, vu, rt) } @@ -4501,7 +4514,7 @@ pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasrh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vh_vasracc_VhVhR(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vasrh_acc(vx, vu, rt) } @@ -4513,7 +4526,7 @@ pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxV #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubrndsat(vu, vv, rt) } @@ -4525,7 +4538,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_VuhVuhR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruhubsat(vu, vv, rt) } @@ -4537,7 +4550,7 @@ pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vasruwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_VuwVuwR_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { vasruwuhsat(vu, vv, rt) } @@ -4549,7 +4562,7 @@ pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgb(vu, vv) } @@ -4561,7 +4574,7 @@ pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavgbrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vavg_VbVb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavgbrnd(vu, vv) } @@ -4573,7 +4586,7 @@ pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguw(vu, vv) } @@ -4585,7 +4598,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vavguwrnd))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vavg_VuwVuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { vavguwrnd(vu, vv) } @@ -4597,7 +4610,7 @@ pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vdd0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vzero() -> HvxVectorPair { +pub unsafe fn Q6_W_vzero() -> HvxVectorPair { vdd0() } @@ -4609,7 +4622,7 @@ pub unsafe fn q6_w_vzero() -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermh(rs, rt, mu, vv) } @@ -4621,7 +4634,7 @@ pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { +pub unsafe fn Q6_vgather_ARMWw(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { vgathermhw(rs, rt, mu, vvv) } @@ -4633,7 +4646,7 @@ pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vgathermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { +pub unsafe fn Q6_vgather_ARMVw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { vgathermw(rs, rt, mu, vv) } @@ -4645,7 +4658,7 @@ pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Wh_vmpa_WubRub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { vmpabuu(vuu, rt) } @@ -4657,7 +4670,7 @@ pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpabuu_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wh_vmpaacc_whwubrub( +pub unsafe fn Q6_Wh_vmpaacc_WhWubRub( vxx: HvxVectorPair, vuu: HvxVectorPair, rt: i32, @@ -4673,7 +4686,7 @@ pub unsafe fn q6_wh_vmpaacc_whwubrub( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyh_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { +pub unsafe fn Q6_Ww_vmpyacc_WwVhRh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { vmpyh_acc(vxx, vu, rt) } @@ -4685,7 +4698,7 @@ pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpye_VuhRuh(vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe(vu, rt) } @@ -4697,7 +4710,7 @@ pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vmpyuhe_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_Vuw_vmpyeacc_VuwVuhRuh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { vmpyuhe_acc(vx, vu, rt) } @@ -4709,7 +4722,7 @@ pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) - #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vnavgb))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vnavg_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVector { vnavgb(vu, vv) } @@ -4721,7 +4734,7 @@ pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh(rt, mu, vv, vw) } @@ -4733,7 +4746,7 @@ pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermh_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVhV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermh_add(rt, mu, vv, vw) } @@ -4745,7 +4758,7 @@ pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw(rt, mu, vvv, vw) } @@ -4757,7 +4770,7 @@ pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermhw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMWwV(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { vscattermhw_add(rt, mu, vvv, vw) } @@ -4769,7 +4782,7 @@ pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: Hvx #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatter_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw(rt, mu, vv, vw) } @@ -4781,7 +4794,7 @@ pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[cfg_attr(test, assert_instr(vscattermw_add))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { +pub unsafe fn Q6_vscatteracc_RMVwV(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { vscattermw_add(rt, mu, vv, vw) } @@ -4793,7 +4806,7 @@ pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vasr_into))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_vasrinto_wwvwvw( +pub unsafe fn Q6_Ww_vasrinto_WwVwVw( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -4809,7 +4822,7 @@ pub unsafe fn q6_ww_vasrinto_wwvwvw( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vrotr))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuw_vrotr_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVector { vrotr(vu, vv) } @@ -4821,7 +4834,7 @@ pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[cfg_attr(test, assert_instr(vsatdw))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vsatdw_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVector { vsatdw(vu, vv) } @@ -4833,7 +4846,7 @@ pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_h( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_h( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4849,7 +4862,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_h( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_h( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4866,7 +4879,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpy_wubwbi_v( +pub unsafe fn Q6_Ww_v6mpy_WubWbI_v( vuu: HvxVectorPair, vvv: HvxVectorPair, iu2: i32, @@ -4882,7 +4895,7 @@ pub unsafe fn q6_ww_v6mpy_wubwbi_v( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( +pub unsafe fn Q6_Ww_v6mpyacc_WwWubWbI_v( vxx: HvxVectorPair, vuu: HvxVectorPair, vvv: HvxVectorPair, @@ -4899,7 +4912,7 @@ pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vabs_Vhf(vu: HvxVector) -> HvxVector { vabs_hf(vu) } @@ -4911,7 +4924,7 @@ pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vabs_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vabs_Vsf(vu: HvxVector) -> HvxVector { vabs_sf(vu) } @@ -4923,7 +4936,7 @@ pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf(vu, vv) } @@ -4935,7 +4948,7 @@ pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_hf_hf(vu, vv) } @@ -4947,7 +4960,7 @@ pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16(vu, vv) } @@ -4959,7 +4972,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vadd_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf16_mix(vu, vv) } @@ -4971,7 +4984,7 @@ pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32(vu, vv) } @@ -4983,7 +4996,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_qf32_mix(vu, vv) } @@ -4995,7 +5008,7 @@ pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf(vu, vv) } @@ -5007,7 +5020,7 @@ pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vadd_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vadd_sf_hf(vu, vv) } @@ -5019,7 +5032,7 @@ pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vadd_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vadd_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vadd_sf_sf(vu, vv) } @@ -5031,7 +5044,7 @@ pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vassign_fp))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_vfmv_Vw(vu: HvxVector) -> HvxVector { vassign_fp(vu) } @@ -5043,7 +5056,7 @@ pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vqf16(vu: HvxVector) -> HvxVector { vconv_hf_qf16(vu) } @@ -5055,7 +5068,7 @@ pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_hf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Wqf32(vuu: HvxVectorPair) -> HvxVector { vconv_hf_qf32(vuu) } @@ -5067,7 +5080,7 @@ pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vconv_sf_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vqf32(vu: HvxVector) -> HvxVector { vconv_sf_qf32(vu) } @@ -5079,7 +5092,7 @@ pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_b_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_b_hf(vu, vv) } @@ -5091,7 +5104,7 @@ pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_h_hf(vu) } @@ -5103,7 +5116,7 @@ pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vb(vu: HvxVector) -> HvxVectorPair { vcvt_hf_b(vu) } @@ -5115,7 +5128,7 @@ pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vh(vu: HvxVector) -> HvxVector { vcvt_hf_h(vu) } @@ -5127,7 +5140,7 @@ pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_hf_sf(vu, vv) } @@ -5139,7 +5152,7 @@ pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_Vub(vu: HvxVector) -> HvxVectorPair { vcvt_hf_ub(vu) } @@ -5151,7 +5164,7 @@ pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_hf_uh))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vcvt_Vuh(vu: HvxVector) -> HvxVector { vcvt_hf_uh(vu) } @@ -5163,7 +5176,7 @@ pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vcvt_Vhf(vu: HvxVector) -> HvxVectorPair { vcvt_sf_hf(vu) } @@ -5175,7 +5188,7 @@ pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_ub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vcvt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vcvt_ub_hf(vu, vv) } @@ -5187,7 +5200,7 @@ pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vcvt_uh_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vcvt_Vhf(vu: HvxVector) -> HvxVector { vcvt_uh_hf(vu) } @@ -5199,7 +5212,7 @@ pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf(vu, vv) } @@ -5211,7 +5224,7 @@ pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vdmpyacc_VsfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vdmpy_sf_hf_acc(vx, vu, vv) } @@ -5223,7 +5236,7 @@ pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_hf(vu, vv) } @@ -5235,7 +5248,7 @@ pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_sf(vu, vv) } @@ -5247,7 +5260,7 @@ pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_hf(vu, vv) } @@ -5259,7 +5272,7 @@ pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_sf(vu, vv) } @@ -5271,7 +5284,7 @@ pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vfneg_Vhf(vu: HvxVector) -> HvxVector { vfneg_hf(vu) } @@ -5283,7 +5296,7 @@ pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vfneg_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vfneg_Vsf(vu: HvxVector) -> HvxVector { vfneg_sf(vu) } @@ -5295,7 +5308,7 @@ pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmax_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_hf(vu, vv) } @@ -5307,7 +5320,7 @@ pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmax_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmax_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmax_sf(vu, vv) } @@ -5319,7 +5332,7 @@ pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmin_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_hf(vu, vv) } @@ -5331,7 +5344,7 @@ pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmin_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmin_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmin_sf(vu, vv) } @@ -5343,7 +5356,7 @@ pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf(vu, vv) } @@ -5355,7 +5368,7 @@ pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vmpyacc_VhfVhfVhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_hf_hf_acc(vx, vu, vv) } @@ -5367,7 +5380,7 @@ pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVect #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16(vu, vv) } @@ -5379,7 +5392,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_hf(vu, vv) } @@ -5391,7 +5404,7 @@ pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf16_mix_hf(vu, vv) } @@ -5403,7 +5416,7 @@ pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32(vu, vv) } @@ -5415,7 +5428,7 @@ pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_hf(vu, vv) } @@ -5427,7 +5440,7 @@ pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPai #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_mix_hf(vu, vv) } @@ -5439,7 +5452,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorP #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wqf32_vmpy_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_qf32_qf16(vu, vv) } @@ -5451,7 +5464,7 @@ pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_qf32_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_qf32_sf(vu, vv) } @@ -5463,7 +5476,7 @@ pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vmpy_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vmpy_sf_hf(vu, vv) } @@ -5475,7 +5488,7 @@ pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( +pub unsafe fn Q6_Wsf_vmpyacc_WsfVhfVhf( vxx: HvxVectorPair, vu: HvxVector, vv: HvxVector, @@ -5491,7 +5504,7 @@ pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vmpy_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vmpy_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpy_sf_sf(vu, vv) } @@ -5503,7 +5516,7 @@ pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf(vu, vv) } @@ -5515,7 +5528,7 @@ pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_hf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_hf_hf(vu, vv) } @@ -5527,7 +5540,7 @@ pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16(vu, vv) } @@ -5539,7 +5552,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf16_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf16_vsub_Vqf16Vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf16_mix(vu, vv) } @@ -5551,7 +5564,7 @@ pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32(vu, vv) } @@ -5563,7 +5576,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVecto #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_qf32_mix))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_Vqf32Vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_qf32_mix(vu, vv) } @@ -5575,7 +5588,7 @@ pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vqf32_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf(vu, vv) } @@ -5587,7 +5600,7 @@ pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Wsf_vsub_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vsub_sf_hf(vu, vv) } @@ -5599,7 +5612,7 @@ pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[cfg_attr(test, assert_instr(vsub_sf_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_vsub_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVector { vsub_sf_sf(vu, vv) } @@ -5611,7 +5624,7 @@ pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubrndsat(vuu, vv) } @@ -5623,7 +5636,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> H #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvuhubsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vub_vasr_WuhVub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvuhubsat(vuu, vv) } @@ -5635,7 +5648,7 @@ pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVe #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhrndsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhrndsat(vuu, vv) } @@ -5647,7 +5660,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> Hv #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vasrvwuhsat))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vasr_WwVuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { vasrvwuhsat(vuu, vv) } @@ -5659,7 +5672,7 @@ pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVec #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] #[cfg_attr(test, assert_instr(vmpyuhvs))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vuh_vmpy_VuhVuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { vmpyuhvs(vu, vv) } @@ -5671,7 +5684,7 @@ pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_h_hf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_equals_Vhf(vu: HvxVector) -> HvxVector { vconv_h_hf(vu) } @@ -5683,7 +5696,7 @@ pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_hf_h))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vhf_equals_Vh(vu: HvxVector) -> HvxVector { vconv_hf_h(vu) } @@ -5695,7 +5708,7 @@ pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_sf_w))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vsf_equals_Vw(vu: HvxVector) -> HvxVector { vconv_sf_w(vu) } @@ -5707,7 +5720,7 @@ pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] #[cfg_attr(test, assert_instr(vconv_w_sf))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_equals_Vsf(vu: HvxVector) -> HvxVector { vconv_w_sf(vu) } @@ -5719,7 +5732,7 @@ pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(get_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vgetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { get_qfext(vu, rt) } @@ -5731,7 +5744,7 @@ pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(set_qfext))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vsetqfext_VR(vu: HvxVector, rt: i32) -> HvxVector { set_qfext(vu, rt) } @@ -5743,7 +5756,7 @@ pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vabs_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vabs_V(vu: HvxVector) -> HvxVector { vabs_f8(vu) } @@ -5755,7 +5768,7 @@ pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_b))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vb(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_b(vu) } @@ -5767,7 +5780,7 @@ pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt2_hf_ub))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt2_Vub(vu: HvxVector) -> HvxVectorPair { vcvt2_hf_ub(vu) } @@ -5779,7 +5792,7 @@ pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vcvt_hf_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_Whf_vcvt_V(vu: HvxVector) -> HvxVectorPair { vcvt_hf_f8(vu) } @@ -5791,7 +5804,7 @@ pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmax_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmax_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmax_f8(vu, vv) } @@ -5803,7 +5816,7 @@ pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfmin_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfmin_VV(vu: HvxVector, vv: HvxVector) -> HvxVector { vfmin_f8(vu, vv) } @@ -5815,7 +5828,7 @@ pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] #[cfg_attr(test, assert_instr(vfneg_f8))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vfneg_V(vu: HvxVector) -> HvxVector { vfneg_f8(vu) } @@ -5827,7 +5840,7 @@ pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and( vandvrt(core::mem::transmute::(qs), -1), @@ -5845,7 +5858,7 @@ pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_and_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_and_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5863,7 +5876,7 @@ pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPre #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_not_Q(qs: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_not(vandvrt( core::mem::transmute::(qs), @@ -5881,7 +5894,7 @@ pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or( vandvrt(core::mem::transmute::(qs), -1), @@ -5899,7 +5912,7 @@ pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_or_QQn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_or_n( vandvrt(core::mem::transmute::(qs), -1), @@ -5917,7 +5930,7 @@ pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) } @@ -5929,7 +5942,7 @@ pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Q_xor_QQ(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( pred_xor( vandvrt(core::mem::transmute::(qs), -1), @@ -5947,7 +5960,7 @@ pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5963,7 +5976,7 @@ pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QnRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_nqpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5979,7 +5992,7 @@ pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_nt_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -5995,7 +6008,7 @@ pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { +pub unsafe fn Q6_vmem_QRIV(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { vS32b_qpred_ai( vandvrt(core::mem::transmute::(qv), -1), rt, @@ -6011,7 +6024,7 @@ pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6027,7 +6040,7 @@ pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condacc_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6043,7 +6056,7 @@ pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6059,7 +6072,7 @@ pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condacc_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6075,7 +6088,7 @@ pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6091,7 +6104,7 @@ pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condacc_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vaddwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6107,7 +6120,7 @@ pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt(core::mem::transmute::(qu), rt) } @@ -6119,7 +6132,7 @@ pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandvrt_acc(vx, core::mem::transmute::(qu), rt) } @@ -6131,7 +6144,7 @@ pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxV #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vand_VR(vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(vu, rt)) } @@ -6143,7 +6156,7 @@ pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vandor_QVR(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt_acc( core::mem::transmute::(qx), vu, @@ -6159,7 +6172,7 @@ pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxV #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) } @@ -6171,7 +6184,7 @@ pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6194,7 +6207,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6217,7 +6230,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6240,7 +6253,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) } @@ -6252,7 +6265,7 @@ pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6275,7 +6288,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6298,7 +6311,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6321,7 +6334,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_eq_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) } @@ -6333,7 +6346,7 @@ pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqand_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6356,7 +6369,7 @@ pub unsafe fn q6_q_vcmp_eqand_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqor_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6379,7 +6392,7 @@ pub unsafe fn q6_q_vcmp_eqor_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_eqxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6402,7 +6415,7 @@ pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VbVb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) } @@ -6414,7 +6427,7 @@ pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtand_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6437,7 +6450,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtor_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6460,7 +6473,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVbVb( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6483,7 +6496,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhVh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) } @@ -6495,7 +6508,7 @@ pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtand_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6518,7 +6531,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtor_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6541,7 +6554,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhVh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6564,7 +6577,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VubVub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) } @@ -6576,7 +6589,7 @@ pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtand_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6599,7 +6612,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtor_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6622,7 +6635,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVubVub( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6645,7 +6658,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuhVuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) } @@ -6657,7 +6670,7 @@ pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtand_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6680,7 +6693,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtor_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6703,7 +6716,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuhVuh( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6726,7 +6739,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VuwVuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) } @@ -6738,7 +6751,7 @@ pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtand_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6761,7 +6774,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtor_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6784,7 +6797,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVuwVuw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6807,7 +6820,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VwVw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) } @@ -6819,7 +6832,7 @@ pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtand_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6842,7 +6855,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtor_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6865,7 +6878,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVwVw( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -6888,7 +6901,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vmux_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { vmux( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -6904,7 +6917,7 @@ pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QnVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6920,7 +6933,7 @@ pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vb_condnac_QVbVb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubbq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6936,7 +6949,7 @@ pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QnVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6952,7 +6965,7 @@ pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vh_condnac_QVhVh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubhq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6968,7 +6981,7 @@ pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QnVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwnq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -6984,7 +6997,7 @@ pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVect #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_Vw_condnac_QVwVw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { vsubwq( vandvrt(core::mem::transmute::(qv), -1), vx, @@ -7000,7 +7013,7 @@ pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVecto #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { +pub unsafe fn Q6_W_vswap_QVV(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { vswap( vandvrt(core::mem::transmute::(qt), -1), vu, @@ -7016,7 +7029,7 @@ pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { +pub unsafe fn Q6_Q_vsetq2_R(rt: i32) -> HvxVectorPred { core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) } @@ -7028,7 +7041,7 @@ pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qb_vshuffe_QhQh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqh( vandvrt(core::mem::transmute::(qs), -1), @@ -7046,7 +7059,7 @@ pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { +pub unsafe fn Q6_Qh_vshuffe_QwQw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { core::mem::transmute::(vandqrt( shuffeqw( vandvrt(core::mem::transmute::(qs), -1), @@ -7064,7 +7077,7 @@ pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVec #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vand_QnR(qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt( vandvrt(core::mem::transmute::(qu), -1), rt, @@ -7079,7 +7092,7 @@ pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { +pub unsafe fn Q6_V_vandor_VQnR(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { vandnqrt_acc( vx, vandvrt(core::mem::transmute::(qu), -1), @@ -7095,7 +7108,7 @@ pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> Hvx #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QnV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvnqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7110,7 +7123,7 @@ pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { +pub unsafe fn Q6_V_vand_QV(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { vandvqv( vandvrt(core::mem::transmute::(qv), -1), vu, @@ -7125,7 +7138,7 @@ pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvh( +pub unsafe fn Q6_vgather_AQRMVh( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7149,7 +7162,7 @@ pub unsafe fn q6_vgather_aqrmvh( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmww( +pub unsafe fn Q6_vgather_AQRMWw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7173,7 +7186,7 @@ pub unsafe fn q6_vgather_aqrmww( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vgather_aqrmvw( +pub unsafe fn Q6_vgather_AQRMVw( rs: *mut HvxVector, qs: HvxVectorPred, rt: i32, @@ -7197,7 +7210,7 @@ pub unsafe fn q6_vgather_aqrmvw( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vb_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqb(vandvrt( core::mem::transmute::(qv), -1, @@ -7212,7 +7225,7 @@ pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vh_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqh(vandvrt( core::mem::transmute::(qv), -1, @@ -7227,7 +7240,7 @@ pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { +pub unsafe fn Q6_Vw_prefixsum_Q(qv: HvxVectorPred) -> HvxVector { vprefixqw(vandvrt( core::mem::transmute::(qv), -1, @@ -7242,7 +7255,7 @@ pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvhv( +pub unsafe fn Q6_vscatter_QRMVhV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7266,7 +7279,7 @@ pub unsafe fn q6_vscatter_qrmvhv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmwwv( +pub unsafe fn Q6_vscatter_QRMWwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7290,7 +7303,7 @@ pub unsafe fn q6_vscatter_qrmwwv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vscatter_qrmvwv( +pub unsafe fn Q6_vscatter_QRMVwV( qs: HvxVectorPred, rt: i32, mu: i32, @@ -7314,7 +7327,7 @@ pub unsafe fn q6_vscatter_qrmvwv( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( +pub unsafe fn Q6_Vw_vadd_VwVwQ_carry_sat( vu: HvxVector, vv: HvxVector, qs: HvxVectorPred, @@ -7334,7 +7347,7 @@ pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VhfVhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) } @@ -7346,7 +7359,7 @@ pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtand_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7369,7 +7382,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtor_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7392,7 +7405,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVhfVhf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7415,7 +7428,7 @@ pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { +pub unsafe fn Q6_Q_vcmp_gt_VsfVsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) } @@ -7427,7 +7440,7 @@ pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtand_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7450,7 +7463,7 @@ pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtor_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, @@ -7473,7 +7486,7 @@ pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( #[inline(always)] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] -pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( +pub unsafe fn Q6_Q_vcmp_gtxacc_QVsfVsf( qx: HvxVectorPred, vu: HvxVector, vv: HvxVector, diff --git a/library/stdarch/crates/core_arch/src/lib.rs b/library/stdarch/crates/core_arch/src/lib.rs index 9255994e5ee8..58a6849ad55d 100644 --- a/library/stdarch/crates/core_arch/src/lib.rs +++ b/library/stdarch/crates/core_arch/src/lib.rs @@ -40,7 +40,8 @@ const_cmp, const_eval_select, maybe_uninit_as_bytes, - movrs_target_feature + movrs_target_feature, + min_adt_const_params )] #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))] #![deny(clippy::missing_inline_in_public_items)] @@ -70,7 +71,11 @@ )] #![cfg_attr( test, - feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection,) + feature( + stdarch_arm_feature_detection, + stdarch_mips_feature_detection, + stdarch_powerpc_feature_detection, + ) )] #[cfg(test)] diff --git a/library/stdarch/crates/core_arch/src/loongarch32/mod.rs b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs index 4e3f3d27182e..6cc1116113e1 100644 --- a/library/stdarch/crates/core_arch/src/loongarch32/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs @@ -15,7 +15,7 @@ } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i32) { static_assert_uimm_bits!(IMM5, 5); @@ -24,7 +24,7 @@ pub unsafe fn cacop(b: i32) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -32,7 +32,7 @@ pub unsafe fn csrrd() -> i32 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); @@ -40,7 +40,7 @@ pub unsafe fn csrwr(a: i32) -> i32 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i32, b: i32) -> i32 { static_assert_uimm_bits!(IMM14, 14); diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs index 1d9d4e8248e6..5559c6ad4d0e 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs @@ -1529,35 +1529,35 @@ fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64; } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsll_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsll_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsll_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsll_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsll_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsll_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsll_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsll_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1566,7 +1566,7 @@ pub fn lasx_xvslli_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslli_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1575,7 +1575,7 @@ pub fn lasx_xvslli_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslli_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1584,7 +1584,7 @@ pub fn lasx_xvslli_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslli_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1593,35 +1593,35 @@ pub fn lasx_xvslli_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslli_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsra_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsra_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsra_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsra_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsra_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsra_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsra_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsra_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1630,7 +1630,7 @@ pub fn lasx_xvsrai_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrai_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1639,7 +1639,7 @@ pub fn lasx_xvsrai_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrai_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1648,7 +1648,7 @@ pub fn lasx_xvsrai_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrai_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1657,35 +1657,35 @@ pub fn lasx_xvsrai_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrai_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrar_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrar_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrar_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrar_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrar_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrar_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrar_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrar_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1694,7 +1694,7 @@ pub fn lasx_xvsrari_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrari_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1703,7 +1703,7 @@ pub fn lasx_xvsrari_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrari_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1712,7 +1712,7 @@ pub fn lasx_xvsrari_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrari_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1721,35 +1721,35 @@ pub fn lasx_xvsrari_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrari_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrl_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrl_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrl_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrl_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrl_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrl_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrl_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrl_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1758,7 +1758,7 @@ pub fn lasx_xvsrli_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrli_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1767,7 +1767,7 @@ pub fn lasx_xvsrli_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrli_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1776,7 +1776,7 @@ pub fn lasx_xvsrli_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrli_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1785,35 +1785,35 @@ pub fn lasx_xvsrli_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrli_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlr_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlr_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlr_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlr_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1822,7 +1822,7 @@ pub fn lasx_xvsrlri_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1831,7 +1831,7 @@ pub fn lasx_xvsrlri_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1840,7 +1840,7 @@ pub fn lasx_xvsrlri_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1849,35 +1849,35 @@ pub fn lasx_xvsrlri_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitclr_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitclr_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitclr_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitclr_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1886,7 +1886,7 @@ pub fn lasx_xvbitclri_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1895,7 +1895,7 @@ pub fn lasx_xvbitclri_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1904,7 +1904,7 @@ pub fn lasx_xvbitclri_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1913,35 +1913,35 @@ pub fn lasx_xvbitclri_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitclri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitset_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitset_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitset_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitset_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitset_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitset_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitset_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitset_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1950,7 +1950,7 @@ pub fn lasx_xvbitseti_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseti_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1959,7 +1959,7 @@ pub fn lasx_xvbitseti_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseti_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1968,7 +1968,7 @@ pub fn lasx_xvbitseti_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseti_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1977,35 +1977,35 @@ pub fn lasx_xvbitseti_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseti_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitrev_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitrev_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitrev_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitrev_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2014,7 +2014,7 @@ pub fn lasx_xvbitrevi_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrevi_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2023,7 +2023,7 @@ pub fn lasx_xvbitrevi_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrevi_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2032,7 +2032,7 @@ pub fn lasx_xvbitrevi_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrevi_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2041,35 +2041,35 @@ pub fn lasx_xvbitrevi_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbitrevi_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadd_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadd_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadd_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadd_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2078,7 +2078,7 @@ pub fn lasx_xvaddi_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvaddi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2087,7 +2087,7 @@ pub fn lasx_xvaddi_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvaddi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2096,7 +2096,7 @@ pub fn lasx_xvaddi_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvaddi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2105,35 +2105,35 @@ pub fn lasx_xvaddi_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvaddi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsub_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsub_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsub_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsub_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsub_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsub_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsub_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2142,7 +2142,7 @@ pub fn lasx_xvsubi_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsubi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2151,7 +2151,7 @@ pub fn lasx_xvsubi_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsubi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2160,7 +2160,7 @@ pub fn lasx_xvsubi_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsubi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2169,35 +2169,35 @@ pub fn lasx_xvsubi_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsubi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2206,7 +2206,7 @@ pub fn lasx_xvmaxi_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2215,7 +2215,7 @@ pub fn lasx_xvmaxi_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2224,7 +2224,7 @@ pub fn lasx_xvmaxi_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2233,35 +2233,35 @@ pub fn lasx_xvmaxi_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmax_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmax_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2270,7 +2270,7 @@ pub fn lasx_xvmaxi_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2279,7 +2279,7 @@ pub fn lasx_xvmaxi_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2288,7 +2288,7 @@ pub fn lasx_xvmaxi_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2297,35 +2297,35 @@ pub fn lasx_xvmaxi_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmaxi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2334,7 +2334,7 @@ pub fn lasx_xvmini_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2343,7 +2343,7 @@ pub fn lasx_xvmini_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2352,7 +2352,7 @@ pub fn lasx_xvmini_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2361,35 +2361,35 @@ pub fn lasx_xvmini_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmin_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmin_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2398,7 +2398,7 @@ pub fn lasx_xvmini_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2407,7 +2407,7 @@ pub fn lasx_xvmini_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2416,7 +2416,7 @@ pub fn lasx_xvmini_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2425,35 +2425,35 @@ pub fn lasx_xvmini_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmini_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvseq_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvseq_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvseq_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvseq_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvseq_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvseq_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvseq_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvseq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2462,7 +2462,7 @@ pub fn lasx_xvseqi_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvseqi_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2471,7 +2471,7 @@ pub fn lasx_xvseqi_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvseqi_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2480,7 +2480,7 @@ pub fn lasx_xvseqi_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvseqi_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2489,35 +2489,35 @@ pub fn lasx_xvseqi_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvseqi_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2526,7 +2526,7 @@ pub fn lasx_xvslti_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2535,7 +2535,7 @@ pub fn lasx_xvslti_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2544,7 +2544,7 @@ pub fn lasx_xvslti_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2553,35 +2553,35 @@ pub fn lasx_xvslti_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvslt_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvslt_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2590,7 +2590,7 @@ pub fn lasx_xvslti_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2599,7 +2599,7 @@ pub fn lasx_xvslti_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2608,7 +2608,7 @@ pub fn lasx_xvslti_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2617,35 +2617,35 @@ pub fn lasx_xvslti_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslti_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2654,7 +2654,7 @@ pub fn lasx_xvslei_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2663,7 +2663,7 @@ pub fn lasx_xvslei_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2672,7 +2672,7 @@ pub fn lasx_xvslei_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2681,35 +2681,35 @@ pub fn lasx_xvslei_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsle_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsle_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2718,7 +2718,7 @@ pub fn lasx_xvslei_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2727,7 +2727,7 @@ pub fn lasx_xvslei_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2736,7 +2736,7 @@ pub fn lasx_xvslei_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2745,7 +2745,7 @@ pub fn lasx_xvslei_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvslei_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2754,7 +2754,7 @@ pub fn lasx_xvsat_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2763,7 +2763,7 @@ pub fn lasx_xvsat_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2772,7 +2772,7 @@ pub fn lasx_xvsat_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2781,7 +2781,7 @@ pub fn lasx_xvsat_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2790,7 +2790,7 @@ pub fn lasx_xvsat_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_bu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2799,7 +2799,7 @@ pub fn lasx_xvsat_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_hu(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2808,7 +2808,7 @@ pub fn lasx_xvsat_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2817,595 +2817,595 @@ pub fn lasx_xvsat_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsat_du(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadda_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadda_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadda_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadda_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadda_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadda_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadda_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadda_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsadd_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsadd_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavg_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavg_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvavgr_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvavgr_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssub_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssub_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvabsd_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvabsd_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmul_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmul_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmul_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmul_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmul_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmul_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmul_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmul_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmadd_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmadd_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmadd_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmadd_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmsub_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmsub_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmsub_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmsub_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvdiv_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvdiv_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_hu_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_hu_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_wu_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_wu_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_du_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_du_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_hu_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_hu_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_wu_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_wu_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_du_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_du_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmod_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmod_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3414,7 +3414,7 @@ pub fn lasx_xvrepl128vei_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrepl128vei_b(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3423,7 +3423,7 @@ pub fn lasx_xvrepl128vei_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrepl128vei_h(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3432,7 +3432,7 @@ pub fn lasx_xvrepl128vei_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrepl128vei_w(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3441,210 +3441,210 @@ pub fn lasx_xvrepl128vei_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrepl128vei_d(transmute(a), IMM1)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickev_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickev_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickev_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickev_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickod_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickod_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickod_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpickod_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpickod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvh_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvh_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvh_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvh_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvh_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvh_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvh_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvh_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvl_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvl_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvl_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvl_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvl_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvl_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvilvl_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvilvl_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackev_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackev_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackev_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackev_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackod_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackod_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackod_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpackod_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpackod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvshuf_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvshuf_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvshuf_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvshuf_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvand_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvand_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3653,14 +3653,14 @@ pub fn lasx_xvandi_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvandi_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvor_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3669,14 +3669,14 @@ pub fn lasx_xvori_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvnor_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvnor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3685,14 +3685,14 @@ pub fn lasx_xvnori_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvnori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvxor_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvxor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3701,14 +3701,14 @@ pub fn lasx_xvxori_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvxori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvbitsel_v(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3717,7 +3717,7 @@ pub fn lasx_xvbitseli_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvbitseli_b(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3726,7 +3726,7 @@ pub fn lasx_xvshuf4i_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf4i_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3735,7 +3735,7 @@ pub fn lasx_xvshuf4i_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf4i_h(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3744,497 +3744,497 @@ pub fn lasx_xvshuf4i_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf4i_w(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplgr2vr_b(a: i32) -> m256i { unsafe { transmute(__lasx_xvreplgr2vr_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplgr2vr_h(a: i32) -> m256i { unsafe { transmute(__lasx_xvreplgr2vr_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplgr2vr_w(a: i32) -> m256i { unsafe { transmute(__lasx_xvreplgr2vr_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplgr2vr_d(a: i64) -> m256i { unsafe { transmute(__lasx_xvreplgr2vr_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpcnt_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpcnt_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpcnt_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpcnt_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpcnt_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpcnt_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvpcnt_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpcnt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclo_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclo_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclo_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclo_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclo_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclo_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclo_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclo_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclz_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclz_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclz_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvclz_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvclz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfadd_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfadd_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfadd_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfsub_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfsub_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfsub_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfsub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmul_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfmul_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmul_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfmul_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfdiv_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfdiv_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfdiv_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfdiv_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvt_h_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcvt_h_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvt_s_d(a: m256d, b: m256d) -> m256 { unsafe { transmute(__lasx_xvfcvt_s_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmin_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfmin_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmin_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfmin_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmina_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfmina_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmina_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfmina_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmax_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfmax_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmax_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfmax_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmaxa_s(a: m256, b: m256) -> m256 { unsafe { transmute(__lasx_xvfmaxa_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmaxa_d(a: m256d, b: m256d) -> m256d { unsafe { transmute(__lasx_xvfmaxa_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfclass_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvfclass_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfclass_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvfclass_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfsqrt_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfsqrt_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfsqrt_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfsqrt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrecip_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrecip_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrecip_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrecip_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrecipe_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrecipe_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrecipe_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrecipe_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrsqrte_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrsqrte_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrsqrte_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrsqrte_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrint_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrint_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrint_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrint_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrsqrt_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrsqrt_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrsqrt_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrsqrt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvflogb_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvflogb_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvflogb_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvflogb_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvth_s_h(a: m256i) -> m256 { unsafe { transmute(__lasx_xvfcvth_s_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvth_d_s(a: m256) -> m256d { unsafe { transmute(__lasx_xvfcvth_d_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvtl_s_h(a: m256i) -> m256 { unsafe { transmute(__lasx_xvfcvtl_s_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcvtl_d_s(a: m256) -> m256d { unsafe { transmute(__lasx_xvfcvtl_d_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftint_w_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftint_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftint_l_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftint_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftint_wu_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftint_wu_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftint_lu_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftint_lu_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrz_w_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrz_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrz_l_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrz_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrz_wu_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrz_wu_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrz_lu_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrz_lu_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffint_s_w(a: m256i) -> m256 { unsafe { transmute(__lasx_xvffint_s_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffint_d_l(a: m256i) -> m256d { unsafe { transmute(__lasx_xvffint_d_l(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffint_s_wu(a: m256i) -> m256 { unsafe { transmute(__lasx_xvffint_s_wu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffint_d_lu(a: m256i) -> m256d { unsafe { transmute(__lasx_xvffint_d_lu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve_b(a: m256i, b: i32) -> m256i { unsafe { transmute(__lasx_xvreplve_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve_h(a: m256i, b: i32) -> m256i { unsafe { transmute(__lasx_xvreplve_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve_w(a: m256i, b: i32) -> m256i { unsafe { transmute(__lasx_xvreplve_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve_d(a: m256i, b: i32) -> m256i { unsafe { transmute(__lasx_xvreplve_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4243,98 +4243,98 @@ pub fn lasx_xvpermi_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpermi_w(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvandn_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvandn_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvneg_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvneg_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvneg_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvneg_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvneg_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvneg_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvneg_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvneg_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmuh_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmuh_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4343,7 +4343,7 @@ pub fn lasx_xvsllwil_h_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_h_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4352,7 +4352,7 @@ pub fn lasx_xvsllwil_w_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_w_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4361,7 +4361,7 @@ pub fn lasx_xvsllwil_d_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_d_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4370,7 +4370,7 @@ pub fn lasx_xvsllwil_hu_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_hu_bu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4379,7 +4379,7 @@ pub fn lasx_xvsllwil_wu_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_wu_hu(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4388,217 +4388,217 @@ pub fn lasx_xvsllwil_du_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvsllwil_du_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsran_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsran_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsran_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsran_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsran_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsran_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssran_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssran_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrarn_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrarn_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrarn_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrarn_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarn_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrln_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrln_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrln_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrln_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrln_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrln_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlrn_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlrn_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsrlrn_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4607,7 +4607,7 @@ pub fn lasx_xvfrstpi_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvfrstpi_b(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4616,21 +4616,21 @@ pub fn lasx_xvfrstpi_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvfrstpi_h(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrstp_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrstp_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4639,7 +4639,7 @@ pub fn lasx_xvshuf4i_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvshuf4i_d(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4648,7 +4648,7 @@ pub fn lasx_xvbsrl_v(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbsrl_v(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4657,7 +4657,7 @@ pub fn lasx_xvbsll_v(a: m256i) -> m256i { unsafe { transmute(__lasx_xvbsll_v(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4666,7 +4666,7 @@ pub fn lasx_xvextrins_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvextrins_b(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4675,7 +4675,7 @@ pub fn lasx_xvextrins_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvextrins_h(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4684,7 +4684,7 @@ pub fn lasx_xvextrins_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvextrins_w(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4693,343 +4693,343 @@ pub fn lasx_xvextrins_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvextrins_d(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmskltz_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmskltz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmskltz_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmskltz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmskltz_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmskltz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmskltz_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmskltz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsigncov_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsigncov_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsigncov_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsigncov_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsigncov_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsigncov_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsigncov_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsigncov_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmadd_s(a: m256, b: m256, c: m256) -> m256 { unsafe { transmute(__lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { unsafe { transmute(__lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmsub_s(a: m256, b: m256, c: m256) -> m256 { unsafe { transmute(__lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { unsafe { transmute(__lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfnmadd_s(a: m256, b: m256, c: m256) -> m256 { unsafe { transmute(__lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfnmadd_d(a: m256d, b: m256d, c: m256d) -> m256d { unsafe { transmute(__lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfnmsub_s(a: m256, b: m256, c: m256) -> m256 { unsafe { transmute(__lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfnmsub_d(a: m256d, b: m256d, c: m256d) -> m256d { unsafe { transmute(__lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrne_w_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrne_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrne_l_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrne_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrp_w_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrp_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrp_l_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrp_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrm_w_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrm_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrm_l_d(a: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrm_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftint_w_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvftint_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffint_s_l(a: m256i, b: m256i) -> m256 { unsafe { transmute(__lasx_xvffint_s_l(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrz_w_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrz_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrp_w_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrp_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrm_w_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrm_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrne_w_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvftintrne_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftinth_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftinth_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintl_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffinth_d_w(a: m256i) -> m256d { unsafe { transmute(__lasx_xvffinth_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvffintl_d_w(a: m256i) -> m256d { unsafe { transmute(__lasx_xvffintl_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrzh_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrzh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrzl_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrzl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrph_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrph_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrpl_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrpl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrmh_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrmh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrml_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrml_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrneh_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrneh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvftintrnel_l_s(a: m256) -> m256i { unsafe { transmute(__lasx_xvftintrnel_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrne_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrintrne_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrne_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrintrne_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrz_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrintrz_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrz_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrintrz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrp_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrintrp_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrp_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrintrp_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrm_s(a: m256) -> m256 { unsafe { transmute(__lasx_xvfrintrm_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfrintrm_d(a: m256d) -> m256d { unsafe { transmute(__lasx_xvfrintrm_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5038,56 +5038,56 @@ pub unsafe fn lasx_xvld(mem_addr: *const i8) -> m256i { transmute(__lasx_xvld(mem_addr, IMM_S12)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvst(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S12, 12); - transmute(__lasx_xvst(transmute(a), mem_addr, IMM_S12)) + __lasx_xvst(transmute(a), mem_addr, IMM_S12) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstelm_b(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lasx_xvstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstelm_h(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lasx_xvstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstelm_w(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lasx_xvstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstelm_d(a: m256i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lasx_xvstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5096,7 +5096,7 @@ pub fn lasx_xvinsve0_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvinsve0_w(transmute(a), transmute(b), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5105,7 +5105,7 @@ pub fn lasx_xvinsve0_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvinsve0_d(transmute(a), transmute(b), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5114,7 +5114,7 @@ pub fn lasx_xvpickve_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpickve_w(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5123,56 +5123,56 @@ pub fn lasx_xvpickve_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpickve_d(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrlrn_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvssrln_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrln_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvorn_v(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvorn_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5181,28 +5181,28 @@ pub fn lasx_xvldi() -> m256i { unsafe { transmute(__lasx_xvldi(IMM_S13)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvldx(mem_addr: *const i8, b: i64) -> m256i { transmute(__lasx_xvldx(mem_addr, transmute(b))) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lasx_xvstx(a: m256i, mem_addr: *mut i8, b: i64) { - transmute(__lasx_xvstx(transmute(a), mem_addr, transmute(b))) + __lasx_xvstx(transmute(a), mem_addr, transmute(b)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvextl_qu_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvextl_qu_du(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5211,7 +5211,7 @@ pub fn lasx_xvinsgr2vr_w(a: m256i, b: i32) -> m256i { unsafe { transmute(__lasx_xvinsgr2vr_w(transmute(a), transmute(b), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5220,126 +5220,126 @@ pub fn lasx_xvinsgr2vr_d(a: m256i, b: i64) -> m256i { unsafe { transmute(__lasx_xvinsgr2vr_d(transmute(a), transmute(b), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve0_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvreplve0_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve0_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvreplve0_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve0_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvreplve0_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve0_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvreplve0_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvreplve0_q(a: m256i) -> m256i { unsafe { transmute(__lasx_xvreplve0_q(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_h_b(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_h_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_w_h(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_w_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_d_w(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_w_b(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_w_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_d_h(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_d_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_d_b(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_d_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_hu_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_hu_bu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_wu_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_wu_hu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_du_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_du_wu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_wu_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_wu_bu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_du_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_du_hu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_vext2xv_du_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_vext2xv_du_bu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5348,7 +5348,7 @@ pub fn lasx_xvpermi_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvpermi_q(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5357,14 +5357,14 @@ pub fn lasx_xvpermi_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvpermi_d(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvperm_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvperm_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5373,7 +5373,7 @@ pub unsafe fn lasx_xvldrepl_b(mem_addr: *const i8) -> m256i transmute(__lasx_xvldrepl_b(mem_addr, IMM_S12)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5382,7 +5382,7 @@ pub unsafe fn lasx_xvldrepl_h(mem_addr: *const i8) -> m256i transmute(__lasx_xvldrepl_h(mem_addr, IMM_S11)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5391,7 +5391,7 @@ pub unsafe fn lasx_xvldrepl_w(mem_addr: *const i8) -> m256i transmute(__lasx_xvldrepl_w(mem_addr, IMM_S10)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5400,7 +5400,7 @@ pub unsafe fn lasx_xvldrepl_d(mem_addr: *const i8) -> m256i { transmute(__lasx_xvldrepl_d(mem_addr, IMM_S9)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5409,7 +5409,7 @@ pub fn lasx_xvpickve2gr_w(a: m256i) -> i32 { unsafe { transmute(__lasx_xvpickve2gr_w(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5418,7 +5418,7 @@ pub fn lasx_xvpickve2gr_wu(a: m256i) -> u32 { unsafe { transmute(__lasx_xvpickve2gr_wu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5427,7 +5427,7 @@ pub fn lasx_xvpickve2gr_d(a: m256i) -> i64 { unsafe { transmute(__lasx_xvpickve2gr_d(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5436,763 +5436,763 @@ pub fn lasx_xvpickve2gr_du(a: m256i) -> u64 { unsafe { transmute(__lasx_xvpickve2gr_du(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwev_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsubwod_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsubwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_d_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_w_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_h_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_q_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_d_wu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_w_hu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_h_bu(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_d_wu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_w_hu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_h_bu_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_d_wu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_w_hu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_h_bu_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_d_wu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_w_hu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_h_bu_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_d_wu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_w_hu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_h_bu_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhaddw_qu_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhaddw_qu_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_q_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvhsubw_qu_du(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvhsubw_qu_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_q_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_d_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_w_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_h_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_q_du(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_q_du(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_d_wu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_w_hu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_h_bu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_q_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_d_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_w_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_h_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_q_du(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_q_du(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_d_wu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_w_hu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_h_bu(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwev_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_q_du_d(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_d_wu_w(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_w_hu_h(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmaddwod_h_bu_b(a: m256i, b: m256i, c: m256i) -> m256i { unsafe { transmute(__lasx_xvmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvrotr_b(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvrotr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvrotr_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvrotr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvrotr_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvrotr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvrotr_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvrotr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvadd_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvadd_q(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvsub_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsub_q(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwev_q_du_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvaddwod_q_du_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwev_q_du_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmulwod_q_du_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmskgez_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmskgez_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvmsknz_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvmsknz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_h_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_h_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_w_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_w_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_d_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_q_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_q_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_hu_bu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_hu_bu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_wu_hu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_wu_hu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_du_wu(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_du_wu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvexth_qu_du(a: m256i) -> m256i { unsafe { transmute(__lasx_xvexth_qu_du(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6201,7 +6201,7 @@ pub fn lasx_xvrotri_b(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrotri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6210,7 +6210,7 @@ pub fn lasx_xvrotri_h(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrotri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6219,7 +6219,7 @@ pub fn lasx_xvrotri_w(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrotri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6228,14 +6228,14 @@ pub fn lasx_xvrotri_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvrotri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvextl_q_d(a: m256i) -> m256i { unsafe { transmute(__lasx_xvextl_q_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6244,7 +6244,7 @@ pub fn lasx_xvsrlni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6253,7 +6253,7 @@ pub fn lasx_xvsrlni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6262,7 +6262,7 @@ pub fn lasx_xvsrlni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6271,7 +6271,7 @@ pub fn lasx_xvsrlni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6280,7 +6280,7 @@ pub fn lasx_xvsrlrni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6289,7 +6289,7 @@ pub fn lasx_xvsrlrni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6298,7 +6298,7 @@ pub fn lasx_xvsrlrni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6307,7 +6307,7 @@ pub fn lasx_xvsrlrni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrlrni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6316,7 +6316,7 @@ pub fn lasx_xvssrlni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6325,7 +6325,7 @@ pub fn lasx_xvssrlni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6334,7 +6334,7 @@ pub fn lasx_xvssrlni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6343,7 +6343,7 @@ pub fn lasx_xvssrlni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6352,7 +6352,7 @@ pub fn lasx_xvssrlni_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6361,7 +6361,7 @@ pub fn lasx_xvssrlni_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6370,7 +6370,7 @@ pub fn lasx_xvssrlni_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6379,7 +6379,7 @@ pub fn lasx_xvssrlni_du_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6388,7 +6388,7 @@ pub fn lasx_xvssrlrni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6397,7 +6397,7 @@ pub fn lasx_xvssrlrni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6406,7 +6406,7 @@ pub fn lasx_xvssrlrni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6415,7 +6415,7 @@ pub fn lasx_xvssrlrni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6424,7 +6424,7 @@ pub fn lasx_xvssrlrni_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6433,7 +6433,7 @@ pub fn lasx_xvssrlrni_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6442,7 +6442,7 @@ pub fn lasx_xvssrlrni_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6451,7 +6451,7 @@ pub fn lasx_xvssrlrni_du_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrlrni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6460,7 +6460,7 @@ pub fn lasx_xvsrani_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrani_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6469,7 +6469,7 @@ pub fn lasx_xvsrani_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrani_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6478,7 +6478,7 @@ pub fn lasx_xvsrani_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrani_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6487,7 +6487,7 @@ pub fn lasx_xvsrani_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrani_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6496,7 +6496,7 @@ pub fn lasx_xvsrarni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6505,7 +6505,7 @@ pub fn lasx_xvsrarni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6514,7 +6514,7 @@ pub fn lasx_xvsrarni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6523,7 +6523,7 @@ pub fn lasx_xvsrarni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvsrarni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6532,7 +6532,7 @@ pub fn lasx_xvssrani_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6541,7 +6541,7 @@ pub fn lasx_xvssrani_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6550,7 +6550,7 @@ pub fn lasx_xvssrani_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6559,7 +6559,7 @@ pub fn lasx_xvssrani_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6568,7 +6568,7 @@ pub fn lasx_xvssrani_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6577,7 +6577,7 @@ pub fn lasx_xvssrani_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6586,7 +6586,7 @@ pub fn lasx_xvssrani_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6595,7 +6595,7 @@ pub fn lasx_xvssrani_du_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrani_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6604,7 +6604,7 @@ pub fn lasx_xvssrarni_b_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6613,7 +6613,7 @@ pub fn lasx_xvssrarni_h_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6622,7 +6622,7 @@ pub fn lasx_xvssrarni_w_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6631,7 +6631,7 @@ pub fn lasx_xvssrarni_d_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6640,7 +6640,7 @@ pub fn lasx_xvssrarni_bu_h(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6649,7 +6649,7 @@ pub fn lasx_xvssrarni_hu_w(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6658,7 +6658,7 @@ pub fn lasx_xvssrarni_wu_d(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6667,385 +6667,385 @@ pub fn lasx_xvssrarni_du_q(a: m256i, b: m256i) -> m256i { unsafe { transmute(__lasx_xvssrarni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbnz_b(a: m256i) -> i32 { unsafe { transmute(__lasx_xbnz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbnz_d(a: m256i) -> i32 { unsafe { transmute(__lasx_xbnz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbnz_h(a: m256i) -> i32 { unsafe { transmute(__lasx_xbnz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbnz_v(a: m256i) -> i32 { unsafe { transmute(__lasx_xbnz_v(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbnz_w(a: m256i) -> i32 { unsafe { transmute(__lasx_xbnz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbz_b(a: m256i) -> i32 { unsafe { transmute(__lasx_xbz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbz_d(a: m256i) -> i32 { unsafe { transmute(__lasx_xbz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbz_h(a: m256i) -> i32 { unsafe { transmute(__lasx_xbz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbz_v(a: m256i) -> i32 { unsafe { transmute(__lasx_xbz_v(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xbz_w(a: m256i) -> i32 { unsafe { transmute(__lasx_xbz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_caf_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_caf_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_caf_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_caf_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_ceq_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_ceq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_ceq_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_ceq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cle_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cle_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cle_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_clt_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_clt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_clt_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_clt_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cne_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cne_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cne_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cne_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cor_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cor_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cor_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cor_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cueq_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cueq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cueq_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cueq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cule_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cule_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cule_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cule_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cult_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cult_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cult_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cult_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cun_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cun_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cune_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_cune_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cune_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cune_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_cun_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_cun_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_saf_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_saf_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_saf_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_saf_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_seq_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_seq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_seq_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_seq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sle_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sle_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sle_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_slt_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_slt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_slt_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_slt_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sne_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sne_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sne_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sne_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sor_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sor_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sor_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sor_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sueq_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sueq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sueq_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sueq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sule_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sule_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sule_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sule_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sult_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sult_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sult_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sult_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sun_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sun_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sune_d(a: m256d, b: m256d) -> m256i { unsafe { transmute(__lasx_xvfcmp_sune_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sune_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sune_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_xvfcmp_sun_s(a: m256, b: m256) -> m256i { unsafe { transmute(__lasx_xvfcmp_sun_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7054,7 +7054,7 @@ pub fn lasx_xvpickve_d_f(a: m256d) -> m256d { unsafe { transmute(__lasx_xvpickve_d_f(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7063,7 +7063,7 @@ pub fn lasx_xvpickve_w_f(a: m256) -> m256 { unsafe { transmute(__lasx_xvpickve_w_f(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7072,7 +7072,7 @@ pub fn lasx_xvrepli_b() -> m256i { unsafe { transmute(__lasx_xvrepli_b(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7081,7 +7081,7 @@ pub fn lasx_xvrepli_d() -> m256i { unsafe { transmute(__lasx_xvrepli_d(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7090,7 +7090,7 @@ pub fn lasx_xvrepli_h() -> m256i { unsafe { transmute(__lasx_xvrepli_h(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -7099,126 +7099,126 @@ pub fn lasx_xvrepli_w() -> m256i { unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_cast_128_s(a: m128) -> m256 { unsafe { transmute(__lasx_cast_128_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_cast_128_d(a: m128d) -> m256d { unsafe { transmute(__lasx_cast_128_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_cast_128(a: m128i) -> m256i { unsafe { transmute(__lasx_cast_128(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 { unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d { unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i { unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_lo_s(a: m256) -> m128 { unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_hi_s(a: m256) -> m128 { unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_lo_d(a: m256d) -> m128d { unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_hi_d(a: m256d) -> m128d { unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_lo(a: m256i) -> m128i { unsafe { transmute(__lasx_extract_128_lo(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_extract_128_hi(a: m256i) -> m128i { unsafe { transmute(__lasx_extract_128_hi(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 { unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 { unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d { unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d { unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i { unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lasx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i { diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs b/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs index 319ce7cf9819..bd22d2577194 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs @@ -5,6 +5,7 @@ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lasx")] @@ -24,7 +25,13 @@ unsafe fn test_lasx_xvsll_b() { 2882304449461665880, ); - assert_eq!(r, transmute(lasx_xvsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -44,7 +51,13 @@ unsafe fn test_lasx_xvsll_h() { 7061899947028838480, ); - assert_eq!(r, transmute(lasx_xvsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -76,7 +89,13 @@ unsafe fn test_lasx_xvsll_w() { 3598939055443673088, ); - assert_eq!(r, transmute(lasx_xvsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -100,7 +119,13 @@ unsafe fn test_lasx_xvsll_d() { -289787284616642560, ); - assert_eq!(r, transmute(lasx_xvsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsll_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -116,7 +141,7 @@ unsafe fn test_lasx_xvslli_b() { 5775955139904200724, ); - assert_eq!(r, transmute(lasx_xvslli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -132,7 +157,7 @@ unsafe fn test_lasx_xvslli_h() { -9223160928474759168, ); - assert_eq!(r, transmute(lasx_xvslli_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -154,7 +179,7 @@ unsafe fn test_lasx_xvslli_w() { -1585267064908546048, ); - assert_eq!(r, transmute(lasx_xvslli_w::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_w::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -172,7 +197,7 @@ unsafe fn test_lasx_xvslli_d() { -2305843009213693952, ); - assert_eq!(r, transmute(lasx_xvslli_d::<61>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslli_d::<61>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -192,7 +217,13 @@ unsafe fn test_lasx_xvsra_b() { -505532365968836077, ); - assert_eq!(r, transmute(lasx_xvsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -212,7 +243,13 @@ unsafe fn test_lasx_xvsra_h() { 8725659825471543, ); - assert_eq!(r, transmute(lasx_xvsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -244,7 +281,13 @@ unsafe fn test_lasx_xvsra_w() { -36696200575105, ); - assert_eq!(r, transmute(lasx_xvsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -263,7 +306,13 @@ unsafe fn test_lasx_xvsra_d() { ); let r = i64x4::new(1, -129761412875, -1, 8464978396185); - assert_eq!(r, transmute(lasx_xvsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsra_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -279,7 +328,7 @@ unsafe fn test_lasx_xvsrai_b() { -218421283493247239, ); - assert_eq!(r, transmute(lasx_xvsrai_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -290,7 +339,7 @@ unsafe fn test_lasx_xvsrai_h() { ); let r = i64x4::new(-281474976710658, 8589803520, -4295098367, 562941363552256); - assert_eq!(r, transmute(lasx_xvsrai_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -307,7 +356,7 @@ unsafe fn test_lasx_xvsrai_w() { ); let r = i64x4::new(68719476730, -16, 17179869169, -25769803773); - assert_eq!(r, transmute(lasx_xvsrai_w::<27>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_w::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -320,7 +369,7 @@ unsafe fn test_lasx_xvsrai_d() { ); let r = i64x4::new(-2, 2, -6, -8); - assert_eq!(r, transmute(lasx_xvsrai_d::<60>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrai_d::<60>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -340,7 +389,13 @@ unsafe fn test_lasx_xvsrar_b() { 302862676776648704, ); - assert_eq!(r, transmute(lasx_xvsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -360,7 +415,13 @@ unsafe fn test_lasx_xvsrar_h() { -2251658079567874, ); - assert_eq!(r, transmute(lasx_xvsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -392,7 +453,13 @@ unsafe fn test_lasx_xvsrar_w() { -1668156707832192, ); - assert_eq!(r, transmute(lasx_xvsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -411,7 +478,13 @@ unsafe fn test_lasx_xvsrar_d() { ); let r = i64x4::new(19951225, 505, -1907248091287715676, 362); - assert_eq!(r, transmute(lasx_xvsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -427,7 +500,7 @@ unsafe fn test_lasx_xvsrari_b() { 790117907428411639, ); - assert_eq!(r, transmute(lasx_xvsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -443,7 +516,7 @@ unsafe fn test_lasx_xvsrari_h() { -24488623625338826, ); - assert_eq!(r, transmute(lasx_xvsrari_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -460,7 +533,7 @@ unsafe fn test_lasx_xvsrari_w() { ); let r = i64x4::new(-1, 4294967294, -2, -1); - assert_eq!(r, transmute(lasx_xvsrari_w::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_w::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -473,7 +546,7 @@ unsafe fn test_lasx_xvsrari_d() { ); let r = i64x4::new(-3228, 4782, -4328, -2120); - assert_eq!(r, transmute(lasx_xvsrari_d::<50>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrari_d::<50>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -493,7 +566,13 @@ unsafe fn test_lasx_xvsrl_b() { 3996105849293766692, ); - assert_eq!(r, transmute(lasx_xvsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -513,7 +592,13 @@ unsafe fn test_lasx_xvsrl_h() { 12385032119328029, ); - assert_eq!(r, transmute(lasx_xvsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -540,7 +625,13 @@ unsafe fn test_lasx_xvsrl_w() { ); let r = i64x4::new(3152506611213, 910538585043, 150899, 25769803779); - assert_eq!(r, transmute(lasx_xvsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -559,7 +650,13 @@ unsafe fn test_lasx_xvsrl_d() { ); let r = i64x4::new(22, 8215, 774027732, 338970735904462); - assert_eq!(r, transmute(lasx_xvsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -575,7 +672,7 @@ unsafe fn test_lasx_xvsrli_b() { 3694315145030590091, ); - assert_eq!(r, transmute(lasx_xvsrli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -586,7 +683,7 @@ unsafe fn test_lasx_xvsrli_h() { ); let r = i64x4::new(7036883009470493, 73014771737, 38655688722, 3096241924866048); - assert_eq!(r, transmute(lasx_xvsrli_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -608,7 +705,7 @@ unsafe fn test_lasx_xvsrli_w() { 11669426172998, ); - assert_eq!(r, transmute(lasx_xvsrli_w::<17>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_w::<17>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -621,7 +718,7 @@ unsafe fn test_lasx_xvsrli_d() { ); let r = i64x4::new(16617962184, 1898365962, 5054169972, 27969530398); - assert_eq!(r, transmute(lasx_xvsrli_d::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrli_d::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -641,7 +738,13 @@ unsafe fn test_lasx_xvsrlr_b() { 150872911094481483, ); - assert_eq!(r, transmute(lasx_xvsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -661,7 +764,13 @@ unsafe fn test_lasx_xvsrlr_h() { 565118914199555, ); - assert_eq!(r, transmute(lasx_xvsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -693,7 +802,13 @@ unsafe fn test_lasx_xvsrlr_w() { 7085854838990307330, ); - assert_eq!(r, transmute(lasx_xvsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -712,7 +827,13 @@ unsafe fn test_lasx_xvsrlr_d() { ); let r = i64x4::new(1801, 481878, 1923591164085, 6280495597); - assert_eq!(r, transmute(lasx_xvsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -728,7 +849,7 @@ unsafe fn test_lasx_xvsrlri_b() { 2893318883870770962, ); - assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -744,7 +865,7 @@ unsafe fn test_lasx_xvsrlri_h() { 32932658182619167, ); - assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -761,7 +882,7 @@ unsafe fn test_lasx_xvsrlri_w() { ); let r = i64x4::new(8589934592, 8589934594, 4294967296, 8589934593); - assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_w::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -779,7 +900,7 @@ unsafe fn test_lasx_xvsrlri_d() { 197693428197319479, ); - assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsrlri_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -799,7 +920,13 @@ unsafe fn test_lasx_xvbitclr_b() { 2031321085346416701, ); - assert_eq!(r, transmute(lasx_xvbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -819,7 +946,13 @@ unsafe fn test_lasx_xvbitclr_h() { -8417099780160452424, ); - assert_eq!(r, transmute(lasx_xvbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -839,7 +972,13 @@ unsafe fn test_lasx_xvbitclr_w() { 436221668492520778, ); - assert_eq!(r, transmute(lasx_xvbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -863,7 +1002,13 @@ unsafe fn test_lasx_xvbitclr_d() { 3668272799860684125, ); - assert_eq!(r, transmute(lasx_xvbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -879,7 +1024,7 @@ unsafe fn test_lasx_xvbitclri_b() { 3065582154070828979, ); - assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -895,7 +1040,7 @@ unsafe fn test_lasx_xvbitclri_h() { 7727381349517352021, ); - assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitclri_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -911,7 +1056,10 @@ unsafe fn test_lasx_xvbitclri_w() { -5611395396043530126, ); - assert_eq!(r, transmute(lasx_xvbitclri_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -929,7 +1077,10 @@ unsafe fn test_lasx_xvbitclri_d() { -63139220754952887, ); - assert_eq!(r, transmute(lasx_xvbitclri_d::<46>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitclri_d::<46>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -949,7 +1100,13 @@ unsafe fn test_lasx_xvbitset_b() { -7702318388235109826, ); - assert_eq!(r, transmute(lasx_xvbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -969,7 +1126,13 @@ unsafe fn test_lasx_xvbitset_h() { 1674099372676878223, ); - assert_eq!(r, transmute(lasx_xvbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -989,7 +1152,13 @@ unsafe fn test_lasx_xvbitset_w() { -4953617511697867204, ); - assert_eq!(r, transmute(lasx_xvbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1013,7 +1182,13 @@ unsafe fn test_lasx_xvbitset_d() { 8641001130845153939, ); - assert_eq!(r, transmute(lasx_xvbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1029,7 +1204,7 @@ unsafe fn test_lasx_xvbitseti_b() { -3539275497407339017, ); - assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitseti_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1045,7 +1220,10 @@ unsafe fn test_lasx_xvbitseti_h() { -1050847327214912781, ); - assert_eq!(r, transmute(lasx_xvbitseti_h::<13>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_h::<13>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1061,7 +1239,10 @@ unsafe fn test_lasx_xvbitseti_w() { -1933536090599238411, ); - assert_eq!(r, transmute(lasx_xvbitseti_w::<29>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_w::<29>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1079,7 +1260,10 @@ unsafe fn test_lasx_xvbitseti_d() { 7640056937583456779, ); - assert_eq!(r, transmute(lasx_xvbitseti_d::<17>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitseti_d::<17>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1099,7 +1283,13 @@ unsafe fn test_lasx_xvbitrev_b() { 8353346322052154032, ); - assert_eq!(r, transmute(lasx_xvbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1119,7 +1309,13 @@ unsafe fn test_lasx_xvbitrev_h() { 1161012008856358603, ); - assert_eq!(r, transmute(lasx_xvbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1139,7 +1335,13 @@ unsafe fn test_lasx_xvbitrev_w() { 2239715596821320928, ); - assert_eq!(r, transmute(lasx_xvbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1163,7 +1365,13 @@ unsafe fn test_lasx_xvbitrev_d() { -7824300689033275105, ); - assert_eq!(r, transmute(lasx_xvbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1179,7 +1387,7 @@ unsafe fn test_lasx_xvbitrevi_b() { -468434338938596352, ); - assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbitrevi_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1195,7 +1403,10 @@ unsafe fn test_lasx_xvbitrevi_h() { 4180481285432101679, ); - assert_eq!(r, transmute(lasx_xvbitrevi_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1211,7 +1422,10 @@ unsafe fn test_lasx_xvbitrevi_w() { -7201777846932221130, ); - assert_eq!(r, transmute(lasx_xvbitrevi_w::<30>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_w::<30>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1229,7 +1443,10 @@ unsafe fn test_lasx_xvbitrevi_d() { -1340750007927221124, ); - assert_eq!(r, transmute(lasx_xvbitrevi_d::<25>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvbitrevi_d::<25>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -1249,7 +1466,13 @@ unsafe fn test_lasx_xvadd_b() { 39834845715162790, ); - assert_eq!(r, transmute(lasx_xvadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1269,7 +1492,13 @@ unsafe fn test_lasx_xvadd_h() { 3485514723534807729, ); - assert_eq!(r, transmute(lasx_xvadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1301,7 +1530,13 @@ unsafe fn test_lasx_xvadd_w() { 449408456544649458, ); - assert_eq!(r, transmute(lasx_xvadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1325,7 +1560,13 @@ unsafe fn test_lasx_xvadd_d() { -3333036084724254699, ); - assert_eq!(r, transmute(lasx_xvadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1341,7 +1582,7 @@ unsafe fn test_lasx_xvaddi_bu() { 1765491911008659808, ); - assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_bu::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1357,7 +1598,7 @@ unsafe fn test_lasx_xvaddi_hu() { 4257614802810591100, ); - assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_hu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1379,7 +1620,7 @@ unsafe fn test_lasx_xvaddi_wu() { 8831113348648816385, ); - assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1397,7 +1638,7 @@ unsafe fn test_lasx_xvaddi_du() { -4546559236496052074, ); - assert_eq!(r, transmute(lasx_xvaddi_du::<24>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvaddi_du::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1417,7 +1658,13 @@ unsafe fn test_lasx_xvsub_b() { -7947080804470620196, ); - assert_eq!(r, transmute(lasx_xvsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1437,7 +1684,13 @@ unsafe fn test_lasx_xvsub_h() { -2694318201466204009, ); - assert_eq!(r, transmute(lasx_xvsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1469,7 +1722,13 @@ unsafe fn test_lasx_xvsub_w() { -4928352995773315889, ); - assert_eq!(r, transmute(lasx_xvsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1493,7 +1752,13 @@ unsafe fn test_lasx_xvsub_d() { -1297126209654251318, ); - assert_eq!(r, transmute(lasx_xvsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1509,7 +1774,7 @@ unsafe fn test_lasx_xvsubi_bu() { 6185872108420092159, ); - assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_bu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1525,7 +1790,7 @@ unsafe fn test_lasx_xvsubi_hu() { 1522443898558080492, ); - assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_hu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1547,7 +1812,7 @@ unsafe fn test_lasx_xvsubi_wu() { 1285045436848317605, ); - assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_wu::<26>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1565,7 +1830,7 @@ unsafe fn test_lasx_xvsubi_du() { 4145748346670499010, ); - assert_eq!(r, transmute(lasx_xvsubi_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsubi_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1585,7 +1850,13 @@ unsafe fn test_lasx_xvmax_b() { 8535488153625188193, ); - assert_eq!(r, transmute(lasx_xvmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1605,7 +1876,13 @@ unsafe fn test_lasx_xvmax_h() { -4332902052436023459, ); - assert_eq!(r, transmute(lasx_xvmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1637,7 +1914,13 @@ unsafe fn test_lasx_xvmax_w() { 6702174376295843649, ); - assert_eq!(r, transmute(lasx_xvmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1661,7 +1944,13 @@ unsafe fn test_lasx_xvmax_d() { -880822478913123851, ); - assert_eq!(r, transmute(lasx_xvmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1677,7 +1966,7 @@ unsafe fn test_lasx_xvmaxi_b() { 5914634738497113077, ); - assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_b::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1693,7 +1982,7 @@ unsafe fn test_lasx_xvmaxi_h() { 4406209242478280693, ); - assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_h::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1715,7 +2004,7 @@ unsafe fn test_lasx_xvmaxi_w() { 22981864337, ); - assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1733,7 +2022,7 @@ unsafe fn test_lasx_xvmaxi_d() { 2429249725865673045, ); - assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_d::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1753,7 +2042,13 @@ unsafe fn test_lasx_xvmax_bu() { 4233495576175936231, ); - assert_eq!(r, transmute(lasx_xvmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1773,7 +2068,13 @@ unsafe fn test_lasx_xvmax_hu() { -1573457187787184228, ); - assert_eq!(r, transmute(lasx_xvmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1793,7 +2094,13 @@ unsafe fn test_lasx_xvmax_wu() { -7315994376096540525, ); - assert_eq!(r, transmute(lasx_xvmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1817,7 +2124,13 @@ unsafe fn test_lasx_xvmax_du() { 5141420152487342561, ); - assert_eq!(r, transmute(lasx_xvmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1833,7 +2146,7 @@ unsafe fn test_lasx_xvmaxi_bu() { -8478920119441971628, ); - assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1849,7 +2162,7 @@ unsafe fn test_lasx_xvmaxi_hu() { 2580949584734723198, ); - assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_hu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1865,7 +2178,7 @@ unsafe fn test_lasx_xvmaxi_wu() { 6328395255824707620, ); - assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_wu::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1883,7 +2196,7 @@ unsafe fn test_lasx_xvmaxi_du() { 3280369825537805033, ); - assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmaxi_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -1903,7 +2216,13 @@ unsafe fn test_lasx_xvmin_b() { -433018640497265418, ); - assert_eq!(r, transmute(lasx_xvmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1923,7 +2242,13 @@ unsafe fn test_lasx_xvmin_h() { -1753422264687927210, ); - assert_eq!(r, transmute(lasx_xvmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1949,7 +2274,13 @@ unsafe fn test_lasx_xvmin_w() { -710046880263550629, ); - assert_eq!(r, transmute(lasx_xvmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1973,7 +2304,13 @@ unsafe fn test_lasx_xvmin_d() { -3792381296290037631, ); - assert_eq!(r, transmute(lasx_xvmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -1989,7 +2326,7 @@ unsafe fn test_lasx_xvmini_b() { -1088282380739546975, ); - assert_eq!(r, transmute(lasx_xvmini_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2005,7 +2342,7 @@ unsafe fn test_lasx_xvmini_h() { 2439077560844296, ); - assert_eq!(r, transmute(lasx_xvmini_h::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_h::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2027,7 +2364,7 @@ unsafe fn test_lasx_xvmini_w() { -3162971646443594334, ); - assert_eq!(r, transmute(lasx_xvmini_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2040,7 +2377,7 @@ unsafe fn test_lasx_xvmini_d() { ); let r = i64x4::new(-8, -8, -8, -8); - assert_eq!(r, transmute(lasx_xvmini_d::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_d::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2060,7 +2397,13 @@ unsafe fn test_lasx_xvmin_bu() { 481055128827070653, ); - assert_eq!(r, transmute(lasx_xvmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2080,7 +2423,13 @@ unsafe fn test_lasx_xvmin_hu() { 4690886800975071114, ); - assert_eq!(r, transmute(lasx_xvmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2100,7 +2449,13 @@ unsafe fn test_lasx_xvmin_wu() { 841320412252129092, ); - assert_eq!(r, transmute(lasx_xvmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2124,7 +2479,13 @@ unsafe fn test_lasx_xvmin_du() { 168959420679376173, ); - assert_eq!(r, transmute(lasx_xvmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2140,7 +2501,7 @@ unsafe fn test_lasx_xvmini_bu() { 1803156197610166553, ); - assert_eq!(r, transmute(lasx_xvmini_bu::<25>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_bu::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2156,7 +2517,7 @@ unsafe fn test_lasx_xvmini_hu() { 7881419608817692, ); - assert_eq!(r, transmute(lasx_xvmini_hu::<28>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_hu::<28>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2167,7 +2528,7 @@ unsafe fn test_lasx_xvmini_wu() { ); let r = i64x4::new(94489280534, 94489280534, 94489280534, 94489280534); - assert_eq!(r, transmute(lasx_xvmini_wu::<22>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_wu::<22>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2180,7 +2541,7 @@ unsafe fn test_lasx_xvmini_du() { ); let r = i64x4::new(18, 18, 18, 18); - assert_eq!(r, transmute(lasx_xvmini_du::<18>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmini_du::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2195,7 +2556,13 @@ unsafe fn test_lasx_xvseq_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2210,7 +2577,13 @@ unsafe fn test_lasx_xvseq_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2237,7 +2610,13 @@ unsafe fn test_lasx_xvseq_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2256,7 +2635,13 @@ unsafe fn test_lasx_xvseq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvseq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2267,7 +2652,7 @@ unsafe fn test_lasx_xvseqi_b() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2278,7 +2663,7 @@ unsafe fn test_lasx_xvseqi_h() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_h::<-8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2295,7 +2680,7 @@ unsafe fn test_lasx_xvseqi_w() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_w::<-11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2308,7 +2693,7 @@ unsafe fn test_lasx_xvseqi_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvseqi_d::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2328,7 +2713,13 @@ unsafe fn test_lasx_xvslt_b() { 71776119077994495, ); - assert_eq!(r, transmute(lasx_xvslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2348,7 +2739,13 @@ unsafe fn test_lasx_xvslt_h() { -281470681743361, ); - assert_eq!(r, transmute(lasx_xvslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2375,7 +2772,13 @@ unsafe fn test_lasx_xvslt_w() { ); let r = i64x4::new(4294967295, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2394,7 +2797,13 @@ unsafe fn test_lasx_xvslt_d() { ); let r = i64x4::new(0, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2410,7 +2819,7 @@ unsafe fn test_lasx_xvslti_b() { 71777218556067840, ); - assert_eq!(r, transmute(lasx_xvslti_b::<-16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_b::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2421,7 +2830,7 @@ unsafe fn test_lasx_xvslti_h() { ); let r = i64x4::new(4294967295, -1, -281470681743361, 65535); - assert_eq!(r, transmute(lasx_xvslti_h::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_h::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2438,7 +2847,7 @@ unsafe fn test_lasx_xvslti_w() { ); let r = i64x4::new(-1, 0, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslti_w::<-4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_w::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2451,7 +2860,7 @@ unsafe fn test_lasx_xvslti_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2466,7 +2875,13 @@ unsafe fn test_lasx_xvslt_bu() { ); let r = i64x4::new(-1095216660481, 280375465083135, -1099494915841, 16711680); - assert_eq!(r, transmute(lasx_xvslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2481,7 +2896,13 @@ unsafe fn test_lasx_xvslt_hu() { ); let r = i64x4::new(-281470681808896, 4294901760, -65536, 281470681808895); - assert_eq!(r, transmute(lasx_xvslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2496,7 +2917,13 @@ unsafe fn test_lasx_xvslt_wu() { ); let r = i64x4::new(-1, -1, -4294967296, -1); - assert_eq!(r, transmute(lasx_xvslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2515,7 +2942,13 @@ unsafe fn test_lasx_xvslt_du() { ); let r = i64x4::new(-1, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2526,7 +2959,7 @@ unsafe fn test_lasx_xvslti_bu() { ); let r = i64x4::new(16711680, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2537,7 +2970,7 @@ unsafe fn test_lasx_xvslti_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_hu::<13>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_hu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2548,7 +2981,7 @@ unsafe fn test_lasx_xvslti_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2561,7 +2994,7 @@ unsafe fn test_lasx_xvslti_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslti_du::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslti_du::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2581,7 +3014,13 @@ unsafe fn test_lasx_xvsle_b() { 1095216726015, ); - assert_eq!(r, transmute(lasx_xvsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2596,7 +3035,13 @@ unsafe fn test_lasx_xvsle_h() { ); let r = i64x4::new(-1, 4294901760, 4294901760, -281470681743361); - assert_eq!(r, transmute(lasx_xvsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2623,7 +3068,13 @@ unsafe fn test_lasx_xvsle_w() { ); let r = i64x4::new(-4294967296, 0, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2642,7 +3093,13 @@ unsafe fn test_lasx_xvsle_d() { ); let r = i64x4::new(-1, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2658,7 +3115,7 @@ unsafe fn test_lasx_xvslei_b() { 280375465148415, ); - assert_eq!(r, transmute(lasx_xvslei_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2669,7 +3126,7 @@ unsafe fn test_lasx_xvslei_h() { ); let r = i64x4::new(-65536, -4294901761, 281474976710655, -65536); - assert_eq!(r, transmute(lasx_xvslei_h::<-15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_h::<-15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2680,7 +3137,7 @@ unsafe fn test_lasx_xvslei_w() { ); let r = i64x4::new(-4294967296, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvslei_w::<-3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_w::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2693,7 +3150,7 @@ unsafe fn test_lasx_xvslei_d() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvslei_d::<6>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_d::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2713,7 +3170,13 @@ unsafe fn test_lasx_xvsle_bu() { 281474976710655, ); - assert_eq!(r, transmute(lasx_xvsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2728,7 +3191,13 @@ unsafe fn test_lasx_xvsle_hu() { ); let r = i64x4::new(281474976645120, -4294967296, 281470681808895, 0); - assert_eq!(r, transmute(lasx_xvsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2743,7 +3212,13 @@ unsafe fn test_lasx_xvsle_wu() { ); let r = i64x4::new(-4294967296, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2762,7 +3237,13 @@ unsafe fn test_lasx_xvsle_du() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2773,7 +3254,7 @@ unsafe fn test_lasx_xvslei_bu() { ); let r = i64x4::new(72056494526365440, 280375465082880, 71776119077928960, 0); - assert_eq!(r, transmute(lasx_xvslei_bu::<29>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_bu::<29>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2784,7 +3265,7 @@ unsafe fn test_lasx_xvslei_hu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_hu::<30>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_hu::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2795,7 +3276,7 @@ unsafe fn test_lasx_xvslei_wu() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_wu::<31>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_wu::<31>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2808,7 +3289,7 @@ unsafe fn test_lasx_xvslei_du() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvslei_du::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvslei_du::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2824,7 +3305,7 @@ unsafe fn test_lasx_xvsat_b() { 1985954429852520914, ); - assert_eq!(r, transmute(lasx_xvsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2840,7 +3321,7 @@ unsafe fn test_lasx_xvsat_h() { 1152903912689234618, ); - assert_eq!(r, transmute(lasx_xvsat_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2857,7 +3338,7 @@ unsafe fn test_lasx_xvsat_w() { ); let r = i64x4::new(-34359738361, 34359738360, -30064771080, -34359738361); - assert_eq!(r, transmute(lasx_xvsat_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2875,7 +3356,7 @@ unsafe fn test_lasx_xvsat_d() { 6102033771404793023, ); - assert_eq!(r, transmute(lasx_xvsat_d::<63>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_d::<63>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2891,7 +3372,7 @@ unsafe fn test_lasx_xvsat_bu() { 2539795165049929535, ); - assert_eq!(r, transmute(lasx_xvsat_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2907,7 +3388,7 @@ unsafe fn test_lasx_xvsat_hu() { 1970354902204423, ); - assert_eq!(r, transmute(lasx_xvsat_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2918,7 +3399,7 @@ unsafe fn test_lasx_xvsat_wu() { ); let r = i64x4::new(270582939711, 270582939711, 270582939711, 270582939711); - assert_eq!(r, transmute(lasx_xvsat_wu::<5>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_wu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2931,7 +3412,7 @@ unsafe fn test_lasx_xvsat_du() { ); let r = i64x4::new(8796093022207, 8796093022207, 8796093022207, 8796093022207); - assert_eq!(r, transmute(lasx_xvsat_du::<42>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvsat_du::<42>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -2951,7 +3432,13 @@ unsafe fn test_lasx_xvadda_b() { -6512388827583513148, ); - assert_eq!(r, transmute(lasx_xvadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2971,7 +3458,13 @@ unsafe fn test_lasx_xvadda_h() { 4288196905584441792, ); - assert_eq!(r, transmute(lasx_xvadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -2997,7 +3490,13 @@ unsafe fn test_lasx_xvadda_w() { 7114837115730115925, ); - assert_eq!(r, transmute(lasx_xvadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3021,7 +3520,13 @@ unsafe fn test_lasx_xvadda_d() { -3532969990801796507, ); - assert_eq!(r, transmute(lasx_xvadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3041,7 +3546,13 @@ unsafe fn test_lasx_xvsadd_b() { 3530119333939728429, ); - assert_eq!(r, transmute(lasx_xvsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3061,7 +3572,13 @@ unsafe fn test_lasx_xvsadd_h() { -5137195089227040637, ); - assert_eq!(r, transmute(lasx_xvsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3093,7 +3610,13 @@ unsafe fn test_lasx_xvsadd_w() { 6493388403303310332, ); - assert_eq!(r, transmute(lasx_xvsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3117,7 +3640,13 @@ unsafe fn test_lasx_xvsadd_d() { -1670245304326307655, ); - assert_eq!(r, transmute(lasx_xvsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3137,7 +3666,13 @@ unsafe fn test_lasx_xvsadd_bu() { -380207497217, ); - assert_eq!(r, transmute(lasx_xvsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3157,7 +3692,13 @@ unsafe fn test_lasx_xvsadd_hu() { -2766274561, ); - assert_eq!(r, transmute(lasx_xvsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3177,7 +3718,13 @@ unsafe fn test_lasx_xvsadd_wu() { 9110967605937569791, ); - assert_eq!(r, transmute(lasx_xvsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3196,7 +3743,13 @@ unsafe fn test_lasx_xvsadd_du() { ); let r = i64x4::new(-1, -7683287700352967836, -3264735658191843562, -1); - assert_eq!(r, transmute(lasx_xvsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3216,7 +3769,13 @@ unsafe fn test_lasx_xvavg_b() { -2451086284962613015, ); - assert_eq!(r, transmute(lasx_xvavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3236,7 +3795,13 @@ unsafe fn test_lasx_xvavg_h() { -6082277202109387491, ); - assert_eq!(r, transmute(lasx_xvavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3268,7 +3833,13 @@ unsafe fn test_lasx_xvavg_w() { -97541447405991454, ); - assert_eq!(r, transmute(lasx_xvavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3292,7 +3863,13 @@ unsafe fn test_lasx_xvavg_d() { 743619511763122382, ); - assert_eq!(r, transmute(lasx_xvavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3312,7 +3889,13 @@ unsafe fn test_lasx_xvavg_bu() { 5794025379951354001, ); - assert_eq!(r, transmute(lasx_xvavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3332,7 +3915,13 @@ unsafe fn test_lasx_xvavg_hu() { -3939723307751543404, ); - assert_eq!(r, transmute(lasx_xvavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3351,7 +3940,13 @@ unsafe fn test_lasx_xvavg_wu() { 6180173283312674740, ); - assert_eq!(r, transmute(lasx_xvavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3375,7 +3970,13 @@ unsafe fn test_lasx_xvavg_du() { -9048945872629561085, ); - assert_eq!(r, transmute(lasx_xvavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3395,7 +3996,13 @@ unsafe fn test_lasx_xvavgr_b() { -1577916506278329386, ); - assert_eq!(r, transmute(lasx_xvavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3415,7 +4022,13 @@ unsafe fn test_lasx_xvavgr_h() { 1044782302812228671, ); - assert_eq!(r, transmute(lasx_xvavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3447,7 +4060,13 @@ unsafe fn test_lasx_xvavgr_w() { 4983380877656540978, ); - assert_eq!(r, transmute(lasx_xvavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3471,7 +4090,13 @@ unsafe fn test_lasx_xvavgr_d() { 229317404291257478, ); - assert_eq!(r, transmute(lasx_xvavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3491,7 +4116,13 @@ unsafe fn test_lasx_xvavgr_bu() { 8511681618342279077, ); - assert_eq!(r, transmute(lasx_xvavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3511,7 +4142,13 @@ unsafe fn test_lasx_xvavgr_hu() { -4835281559523879916, ); - assert_eq!(r, transmute(lasx_xvavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3531,7 +4168,13 @@ unsafe fn test_lasx_xvavgr_wu() { 2489338192049926342, ); - assert_eq!(r, transmute(lasx_xvavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3555,7 +4198,13 @@ unsafe fn test_lasx_xvavgr_du() { 6414723233875186966, ); - assert_eq!(r, transmute(lasx_xvavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3575,7 +4224,13 @@ unsafe fn test_lasx_xvssub_b() { -4561472970538678093, ); - assert_eq!(r, transmute(lasx_xvssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3595,7 +4250,13 @@ unsafe fn test_lasx_xvssub_h() { 8048307602867637285, ); - assert_eq!(r, transmute(lasx_xvssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3627,7 +4288,13 @@ unsafe fn test_lasx_xvssub_w() { 4655436811119524629, ); - assert_eq!(r, transmute(lasx_xvssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3651,7 +4318,13 @@ unsafe fn test_lasx_xvssub_d() { -9223372036854775808, ); - assert_eq!(r, transmute(lasx_xvssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3671,7 +4344,13 @@ unsafe fn test_lasx_xvssub_bu() { 864691185841012929, ); - assert_eq!(r, transmute(lasx_xvssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3691,7 +4370,13 @@ unsafe fn test_lasx_xvssub_hu() { 188750927758467, ); - assert_eq!(r, transmute(lasx_xvssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3711,7 +4396,13 @@ unsafe fn test_lasx_xvssub_wu() { 3974517532346153551, ); - assert_eq!(r, transmute(lasx_xvssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3730,7 +4421,13 @@ unsafe fn test_lasx_xvssub_du() { ); let r = i64x4::new(1075384133325788465, 0, 8236940487074099359, 0); - assert_eq!(r, transmute(lasx_xvssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3750,7 +4447,13 @@ unsafe fn test_lasx_xvabsd_b() { 4109603046844106624, ); - assert_eq!(r, transmute(lasx_xvabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3770,7 +4473,13 @@ unsafe fn test_lasx_xvabsd_h() { 5513891007581016946, ); - assert_eq!(r, transmute(lasx_xvabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3802,7 +4511,13 @@ unsafe fn test_lasx_xvabsd_w() { -7014776540975538355, ); - assert_eq!(r, transmute(lasx_xvabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3826,7 +4541,13 @@ unsafe fn test_lasx_xvabsd_d() { 4722306005291245989, ); - assert_eq!(r, transmute(lasx_xvabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3846,7 +4567,13 @@ unsafe fn test_lasx_xvabsd_bu() { 1887319547440621943, ); - assert_eq!(r, transmute(lasx_xvabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3866,7 +4593,13 @@ unsafe fn test_lasx_xvabsd_hu() { 1864011964690965056, ); - assert_eq!(r, transmute(lasx_xvabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3886,7 +4619,13 @@ unsafe fn test_lasx_xvabsd_wu() { 1525979489064328670, ); - assert_eq!(r, transmute(lasx_xvabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3910,7 +4649,13 @@ unsafe fn test_lasx_xvabsd_du() { 2127486190004927946, ); - assert_eq!(r, transmute(lasx_xvabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3930,7 +4675,13 @@ unsafe fn test_lasx_xvmul_b() { -9159357540886189840, ); - assert_eq!(r, transmute(lasx_xvmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3950,7 +4701,13 @@ unsafe fn test_lasx_xvmul_h() { -7534790044979024262, ); - assert_eq!(r, transmute(lasx_xvmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -3982,7 +4739,13 @@ unsafe fn test_lasx_xvmul_w() { 1142495638330554240, ); - assert_eq!(r, transmute(lasx_xvmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4006,7 +4769,13 @@ unsafe fn test_lasx_xvmul_d() { -3668010491661410128, ); - assert_eq!(r, transmute(lasx_xvmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4032,7 +4801,11 @@ unsafe fn test_lasx_xvmadd_b() { assert_eq!( r, - transmute(lasx_xvmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4059,7 +4832,11 @@ unsafe fn test_lasx_xvmadd_h() { assert_eq!( r, - transmute(lasx_xvmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4104,7 +4881,11 @@ unsafe fn test_lasx_xvmadd_w() { assert_eq!( r, - transmute(lasx_xvmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4137,7 +4918,11 @@ unsafe fn test_lasx_xvmadd_d() { assert_eq!( r, - transmute(lasx_xvmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4164,7 +4949,11 @@ unsafe fn test_lasx_xvmsub_b() { assert_eq!( r, - transmute(lasx_xvmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4191,7 +4980,11 @@ unsafe fn test_lasx_xvmsub_h() { assert_eq!( r, - transmute(lasx_xvmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4236,7 +5029,11 @@ unsafe fn test_lasx_xvmsub_w() { assert_eq!( r, - transmute(lasx_xvmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4269,7 +5066,11 @@ unsafe fn test_lasx_xvmsub_d() { assert_eq!( r, - transmute(lasx_xvmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4285,7 +5086,13 @@ unsafe fn test_lasx_xvdiv_b() { ); let r = i64x4::new(67174400, 843334041468931, 16515072, 1090921824000); - assert_eq!(r, transmute(lasx_xvdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4305,7 +5112,13 @@ unsafe fn test_lasx_xvdiv_h() { -281470681939967, ); - assert_eq!(r, transmute(lasx_xvdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4332,7 +5145,13 @@ unsafe fn test_lasx_xvdiv_w() { ); let r = i64x4::new(-25769803778, 4294967295, 34359738365, 1); - assert_eq!(r, transmute(lasx_xvdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4351,7 +5170,13 @@ unsafe fn test_lasx_xvdiv_d() { ); let r = i64x4::new(-3, 0, -3, 0); - assert_eq!(r, transmute(lasx_xvdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4371,7 +5196,13 @@ unsafe fn test_lasx_xvdiv_bu() { 144118486677848127, ); - assert_eq!(r, transmute(lasx_xvdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4386,7 +5217,13 @@ unsafe fn test_lasx_xvdiv_hu() { ); let r = i64x4::new(4295098372, 38654705665, 281474976776212, 283467841601537); - assert_eq!(r, transmute(lasx_xvdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4401,7 +5238,13 @@ unsafe fn test_lasx_xvdiv_wu() { ); let r = i64x4::new(0, 1, 46, 4294967299); - assert_eq!(r, transmute(lasx_xvdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4420,7 +5263,13 @@ unsafe fn test_lasx_xvdiv_du() { ); let r = i64x4::new(0, 0, 1, 6); - assert_eq!(r, transmute(lasx_xvdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4440,7 +5289,13 @@ unsafe fn test_lasx_xvhaddw_h_b() { -18859072538017839, ); - assert_eq!(r, transmute(lasx_xvhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4460,7 +5315,13 @@ unsafe fn test_lasx_xvhaddw_w_h() { -36597416302335, ); - assert_eq!(r, transmute(lasx_xvhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4487,7 +5348,13 @@ unsafe fn test_lasx_xvhaddw_d_w() { ); let r = i64x4::new(1043954543, 64421064, -1003667433, -119821715); - assert_eq!(r, transmute(lasx_xvhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4507,7 +5374,13 @@ unsafe fn test_lasx_xvhaddw_hu_bu() { 56014362196705476, ); - assert_eq!(r, transmute(lasx_xvhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4527,7 +5400,13 @@ unsafe fn test_lasx_xvhaddw_wu_hu() { 392255068231306, ); - assert_eq!(r, transmute(lasx_xvhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4542,7 +5421,13 @@ unsafe fn test_lasx_xvhaddw_du_wu() { ); let r = i64x4::new(2983569336, 4514288382, 2479696956, 1680431840); - assert_eq!(r, transmute(lasx_xvhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4562,7 +5447,13 @@ unsafe fn test_lasx_xvhsubw_h_b() { -21955597927907350, ); - assert_eq!(r, transmute(lasx_xvhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4582,7 +5473,13 @@ unsafe fn test_lasx_xvhsubw_w_h() { -108800111503156, ); - assert_eq!(r, transmute(lasx_xvhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4603,7 +5500,13 @@ unsafe fn test_lasx_xvhsubw_d_w() { ); let r = i64x4::new(2748898148, -45146293, 958916832, 1285325893); - assert_eq!(r, transmute(lasx_xvhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4623,7 +5526,13 @@ unsafe fn test_lasx_xvhsubw_hu_bu() { 9289103727198239, ); - assert_eq!(r, transmute(lasx_xvhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4643,7 +5552,13 @@ unsafe fn test_lasx_xvhsubw_wu_hu() { 32018981198856, ); - assert_eq!(r, transmute(lasx_xvhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4658,7 +5573,13 @@ unsafe fn test_lasx_xvhsubw_du_wu() { ); let r = i64x4::new(-1056733131, -2613149992, 384615677, -1588276541); - assert_eq!(r, transmute(lasx_xvhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4678,7 +5599,13 @@ unsafe fn test_lasx_xvmod_b() { -48385121157714142, ); - assert_eq!(r, transmute(lasx_xvmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4698,7 +5625,13 @@ unsafe fn test_lasx_xvmod_h() { -194216204870745003, ); - assert_eq!(r, transmute(lasx_xvmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4724,7 +5657,13 @@ unsafe fn test_lasx_xvmod_w() { 807808928635455307, ); - assert_eq!(r, transmute(lasx_xvmod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4748,7 +5687,13 @@ unsafe fn test_lasx_xvmod_d() { -3048989907394276239, ); - assert_eq!(r, transmute(lasx_xvmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4768,7 +5713,13 @@ unsafe fn test_lasx_xvmod_bu() { 5417620637589803790, ); - assert_eq!(r, transmute(lasx_xvmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4788,7 +5739,13 @@ unsafe fn test_lasx_xvmod_hu() { 129490854556368167, ); - assert_eq!(r, transmute(lasx_xvmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4808,7 +5765,13 @@ unsafe fn test_lasx_xvmod_wu() { 480682694340619302, ); - assert_eq!(r, transmute(lasx_xvmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4832,7 +5795,13 @@ unsafe fn test_lasx_xvmod_du() { 150087784552479859, ); - assert_eq!(r, transmute(lasx_xvmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4848,7 +5817,10 @@ unsafe fn test_lasx_xvrepl128vei_b() { 8970181431921507452, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_b::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_b::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4864,7 +5836,10 @@ unsafe fn test_lasx_xvrepl128vei_h() { -3904680457625679409, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_h::<3>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_h::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4886,7 +5861,10 @@ unsafe fn test_lasx_xvrepl128vei_w() { -1327396365108239351, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_w::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_w::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4904,7 +5882,10 @@ unsafe fn test_lasx_xvrepl128vei_d() { 4427502889722976813, ); - assert_eq!(r, transmute(lasx_xvrepl128vei_d::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvrepl128vei_d::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -4924,7 +5905,13 @@ unsafe fn test_lasx_xvpickev_b() { 4502896606534087725, ); - assert_eq!(r, transmute(lasx_xvpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4944,7 +5931,13 @@ unsafe fn test_lasx_xvpickev_h() { -2117051360895385090, ); - assert_eq!(r, transmute(lasx_xvpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -4976,7 +5969,13 @@ unsafe fn test_lasx_xvpickev_w() { -4454806063744691677, ); - assert_eq!(r, transmute(lasx_xvpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5000,7 +5999,13 @@ unsafe fn test_lasx_xvpickev_d() { 1952973857169882715, ); - assert_eq!(r, transmute(lasx_xvpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5020,7 +6025,13 @@ unsafe fn test_lasx_xvpickod_b() { 4092165317489988560, ); - assert_eq!(r, transmute(lasx_xvpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5040,7 +6051,13 @@ unsafe fn test_lasx_xvpickod_h() { 5912677724127371711, ); - assert_eq!(r, transmute(lasx_xvpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5072,7 +6089,13 @@ unsafe fn test_lasx_xvpickod_w() { 14200989743342145, ); - assert_eq!(r, transmute(lasx_xvpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5096,7 +6119,13 @@ unsafe fn test_lasx_xvpickod_d() { 3923084493864153244, ); - assert_eq!(r, transmute(lasx_xvpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5116,7 +6145,13 @@ unsafe fn test_lasx_xvilvh_b() { 6070396101995813657, ); - assert_eq!(r, transmute(lasx_xvilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5136,7 +6171,13 @@ unsafe fn test_lasx_xvilvh_h() { 6944594579025051980, ); - assert_eq!(r, transmute(lasx_xvilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5168,7 +6209,13 @@ unsafe fn test_lasx_xvilvh_w() { 2557948893958412086, ); - assert_eq!(r, transmute(lasx_xvilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5192,7 +6239,13 @@ unsafe fn test_lasx_xvilvh_d() { -1576924492614617443, ); - assert_eq!(r, transmute(lasx_xvilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5212,7 +6265,13 @@ unsafe fn test_lasx_xvilvl_b() { -1661662459983806644, ); - assert_eq!(r, transmute(lasx_xvilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5232,7 +6291,13 @@ unsafe fn test_lasx_xvilvl_h() { -894657396213105965, ); - assert_eq!(r, transmute(lasx_xvilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5264,7 +6329,13 @@ unsafe fn test_lasx_xvilvl_w() { 6940426927105417163, ); - assert_eq!(r, transmute(lasx_xvilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5288,7 +6359,13 @@ unsafe fn test_lasx_xvilvl_d() { -2688716944239585727, ); - assert_eq!(r, transmute(lasx_xvilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5308,7 +6385,13 @@ unsafe fn test_lasx_xvpackev_b() { -9004682544879989266, ); - assert_eq!(r, transmute(lasx_xvpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5328,7 +6411,13 @@ unsafe fn test_lasx_xvpackev_h() { -5280992525495869891, ); - assert_eq!(r, transmute(lasx_xvpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5360,7 +6449,13 @@ unsafe fn test_lasx_xvpackev_w() { 338692385926626324, ); - assert_eq!(r, transmute(lasx_xvpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5384,7 +6479,13 @@ unsafe fn test_lasx_xvpackev_d() { -3601691172781761847, ); - assert_eq!(r, transmute(lasx_xvpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5404,7 +6505,13 @@ unsafe fn test_lasx_xvpackod_b() { 3700670962761760653, ); - assert_eq!(r, transmute(lasx_xvpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5424,7 +6531,13 @@ unsafe fn test_lasx_xvpackod_h() { -5523279134117035742, ); - assert_eq!(r, transmute(lasx_xvpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5456,7 +6569,13 @@ unsafe fn test_lasx_xvpackod_w() { -7292079267755798519, ); - assert_eq!(r, transmute(lasx_xvpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5480,7 +6599,13 @@ unsafe fn test_lasx_xvpackod_d() { -8628096693516187272, ); - assert_eq!(r, transmute(lasx_xvpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5506,7 +6631,11 @@ unsafe fn test_lasx_xvshuf_b() { assert_eq!( r, - transmute(lasx_xvshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5530,7 +6659,11 @@ unsafe fn test_lasx_xvshuf_h() { assert_eq!( r, - transmute(lasx_xvshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5566,7 +6699,11 @@ unsafe fn test_lasx_xvshuf_w() { assert_eq!( r, - transmute(lasx_xvshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5594,7 +6731,11 @@ unsafe fn test_lasx_xvshuf_d() { assert_eq!( r, - transmute(lasx_xvshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5615,7 +6756,13 @@ unsafe fn test_lasx_xvand_v() { -7998109804568426495, ); - assert_eq!(r, transmute(lasx_xvand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvand_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5631,7 +6778,7 @@ unsafe fn test_lasx_xvandi_b() { 793492300495455493, ); - assert_eq!(r, transmute(lasx_xvandi_b::<47>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvandi_b::<47>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5651,7 +6798,13 @@ unsafe fn test_lasx_xvor_v() { -198266276987019378, ); - assert_eq!(r, transmute(lasx_xvor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5667,7 +6820,7 @@ unsafe fn test_lasx_xvori_b() { 8466485259632311926, ); - assert_eq!(r, transmute(lasx_xvori_b::<116>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvori_b::<116>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5687,7 +6840,13 @@ unsafe fn test_lasx_xvnor_v() { -8601510250130767824, ); - assert_eq!(r, transmute(lasx_xvnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvnor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5703,7 +6862,7 @@ unsafe fn test_lasx_xvnori_b() { 6053994920729270286, ); - assert_eq!(r, transmute(lasx_xvnori_b::<161>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvnori_b::<161>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5723,7 +6882,13 @@ unsafe fn test_lasx_xvxor_v() { 4786489823605581252, ); - assert_eq!(r, transmute(lasx_xvxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvxor_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -5739,7 +6904,7 @@ unsafe fn test_lasx_xvxori_b() { 1979210996964535887, ); - assert_eq!(r, transmute(lasx_xvxori_b::<179>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvxori_b::<179>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5765,7 +6930,11 @@ unsafe fn test_lasx_xvbitsel_v() { assert_eq!( r, - transmute(lasx_xvbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5788,7 +6957,10 @@ unsafe fn test_lasx_xvbitseli_b() { assert_eq!( r, - transmute(lasx_xvbitseli_b::<156>(transmute(a), transmute(b))) + transmute(lasx_xvbitseli_b::<156>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5805,7 +6977,10 @@ unsafe fn test_lasx_xvshuf4i_b() { 1357573681433480718, ); - assert_eq!(r, transmute(lasx_xvshuf4i_b::<117>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_b::<117>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5821,7 +6996,10 @@ unsafe fn test_lasx_xvshuf4i_h() { 4406041774853078309, ); - assert_eq!(r, transmute(lasx_xvshuf4i_h::<125>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvshuf4i_h::<125>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -5843,7 +7021,7 @@ unsafe fn test_lasx_xvshuf4i_w() { -206225345846487261, ); - assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvshuf4i_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5855,7 +7033,7 @@ unsafe fn test_lasx_xvreplgr2vr_b() { 8463800222054970741, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_b(-139770763))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_b(black_box(-139770763)))); } #[simd_test(enable = "lasx")] @@ -5867,7 +7045,7 @@ unsafe fn test_lasx_xvreplgr2vr_h() { -1100020993973555013, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_h(-111546181))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_h(black_box(-111546181)))); } #[simd_test(enable = "lasx")] @@ -5879,7 +7057,7 @@ unsafe fn test_lasx_xvreplgr2vr_w() { -8112237653938959659, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_w(-1888777515))); + assert_eq!(r, transmute(lasx_xvreplgr2vr_w(black_box(-1888777515)))); } #[simd_test(enable = "lasx")] @@ -5891,7 +7069,10 @@ unsafe fn test_lasx_xvreplgr2vr_d() { -1472556476011894783, ); - assert_eq!(r, transmute(lasx_xvreplgr2vr_d(-1472556476011894783))); + assert_eq!( + r, + transmute(lasx_xvreplgr2vr_d(black_box(-1472556476011894783))) + ); } #[simd_test(enable = "lasx")] @@ -5907,7 +7088,7 @@ unsafe fn test_lasx_xvpcnt_b() { 288795538114413315, ); - assert_eq!(r, transmute(lasx_xvpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5923,7 +7104,7 @@ unsafe fn test_lasx_xvpcnt_h() { 2251829878980617, ); - assert_eq!(r, transmute(lasx_xvpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5940,7 +7121,7 @@ unsafe fn test_lasx_xvpcnt_w() { ); let r = i64x4::new(77309411341, 60129542155, 73014444046, 55834574863); - assert_eq!(r, transmute(lasx_xvpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5953,7 +7134,7 @@ unsafe fn test_lasx_xvpcnt_d() { ); let r = i64x4::new(33, 31, 29, 33); - assert_eq!(r, transmute(lasx_xvpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5964,7 +7145,7 @@ unsafe fn test_lasx_xvclo_b() { ); let r = i64x4::new(2207613190657, 8589934592, 1103806726660, 3298568503554); - assert_eq!(r, transmute(lasx_xvclo_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5980,7 +7161,7 @@ unsafe fn test_lasx_xvclo_h() { 281479271677953, ); - assert_eq!(r, transmute(lasx_xvclo_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -5997,7 +7178,7 @@ unsafe fn test_lasx_xvclo_w() { ); let r = i64x4::new(4294967299, 1, 1, 8589934593); - assert_eq!(r, transmute(lasx_xvclo_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6010,7 +7191,7 @@ unsafe fn test_lasx_xvclo_d() { ); let r = i64x4::new(2, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvclo_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6021,7 +7202,7 @@ unsafe fn test_lasx_xvclz_b() { ); let r = i64x4::new(65538, 72621643502977024, 216173885920575744, 3302846693380); - assert_eq!(r, transmute(lasx_xvclz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6037,7 +7218,7 @@ unsafe fn test_lasx_xvclz_h() { 17179934721, ); - assert_eq!(r, transmute(lasx_xvclz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6054,7 +7235,7 @@ unsafe fn test_lasx_xvclz_w() { ); let r = i64x4::new(8589934592, 0, 3, 4294967296); - assert_eq!(r, transmute(lasx_xvclz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6067,7 +7248,7 @@ unsafe fn test_lasx_xvclz_d() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvclz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6087,7 +7268,13 @@ unsafe fn test_lasx_xvfadd_s() { 4545553165339792015, ); - assert_eq!(r, transmute(lasx_xvfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6111,7 +7298,13 @@ unsafe fn test_lasx_xvfadd_d() { 4607242424158867483, ); - assert_eq!(r, transmute(lasx_xvfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6131,7 +7324,13 @@ unsafe fn test_lasx_xvfsub_s() { -4716328899074058446, ); - assert_eq!(r, transmute(lasx_xvfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6155,7 +7354,13 @@ unsafe fn test_lasx_xvfsub_d() { 4602885236169716939, ); - assert_eq!(r, transmute(lasx_xvfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6175,7 +7380,13 @@ unsafe fn test_lasx_xvfmul_s() { 4412217640780718091, ); - assert_eq!(r, transmute(lasx_xvfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6199,7 +7410,13 @@ unsafe fn test_lasx_xvfmul_d() { 4604645288864682176, ); - assert_eq!(r, transmute(lasx_xvfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6219,7 +7436,13 @@ unsafe fn test_lasx_xvfdiv_s() { 4544549637634302505, ); - assert_eq!(r, transmute(lasx_xvfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6243,7 +7466,13 @@ unsafe fn test_lasx_xvfdiv_d() { 4608170208670026319, ); - assert_eq!(r, transmute(lasx_xvfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6263,7 +7492,13 @@ unsafe fn test_lasx_xvfcvt_h_s() { 4182498428240214789, ); - assert_eq!(r, transmute(lasx_xvfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6287,7 +7522,13 @@ unsafe fn test_lasx_xvfcvt_s_d() { 4509540616169896248, ); - assert_eq!(r, transmute(lasx_xvfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6307,7 +7548,13 @@ unsafe fn test_lasx_xvfmin_s() { 4470137692837414470, ); - assert_eq!(r, transmute(lasx_xvfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6331,7 +7578,13 @@ unsafe fn test_lasx_xvfmin_d() { 4596668800324369880, ); - assert_eq!(r, transmute(lasx_xvfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6351,7 +7604,13 @@ unsafe fn test_lasx_xvfmina_s() { 4561809912873379512, ); - assert_eq!(r, transmute(lasx_xvfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6375,7 +7634,13 @@ unsafe fn test_lasx_xvfmina_d() { 4597161583916257152, ); - assert_eq!(r, transmute(lasx_xvfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6395,7 +7660,13 @@ unsafe fn test_lasx_xvfmax_s() { 4574742780979947531, ); - assert_eq!(r, transmute(lasx_xvfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6419,7 +7690,13 @@ unsafe fn test_lasx_xvfmax_d() { 4602928137069840177, ); - assert_eq!(r, transmute(lasx_xvfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6439,7 +7716,13 @@ unsafe fn test_lasx_xvfmaxa_s() { 4527767521076114844, ); - assert_eq!(r, transmute(lasx_xvfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6463,7 +7746,13 @@ unsafe fn test_lasx_xvfmaxa_d() { 4596362093665607644, ); - assert_eq!(r, transmute(lasx_xvfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -6474,7 +7763,7 @@ unsafe fn test_lasx_xvfclass_s() { ); let r = i64x4::new(549755814016, 549755814016, 549755814016, 549755814016); - assert_eq!(r, transmute(lasx_xvfclass_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6487,7 +7776,7 @@ unsafe fn test_lasx_xvfclass_d() { ); let r = i64x4::new(128, 128, 128, 128); - assert_eq!(r, transmute(lasx_xvfclass_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6503,7 +7792,7 @@ unsafe fn test_lasx_xvfsqrt_s() { 4566109703441416989, ); - assert_eq!(r, transmute(lasx_xvfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6521,7 +7810,7 @@ unsafe fn test_lasx_xvfsqrt_d() { 4601138545884238765, ); - assert_eq!(r, transmute(lasx_xvfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6537,7 +7826,7 @@ unsafe fn test_lasx_xvfrecip_s() { 4585242601638738136, ); - assert_eq!(r, transmute(lasx_xvfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6555,7 +7844,7 @@ unsafe fn test_lasx_xvfrecip_d() { 4611482062367896141, ); - assert_eq!(r, transmute(lasx_xvfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6571,7 +7860,7 @@ unsafe fn test_lasx_xvfrecipe_s() { 4728509413412007938, ); - assert_eq!(r, transmute(lasx_xvfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6589,7 +7878,7 @@ unsafe fn test_lasx_xvfrecipe_d() { 4611499011256352768, ); - assert_eq!(r, transmute(lasx_xvfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6605,7 +7894,7 @@ unsafe fn test_lasx_xvfrsqrte_s() { 4612427253546066334, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx,frecipe")] @@ -6623,7 +7912,7 @@ unsafe fn test_lasx_xvfrsqrte_d() { 4612346183891812352, ); - assert_eq!(r, transmute(lasx_xvfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6634,7 +7923,7 @@ unsafe fn test_lasx_xvfrint_s() { ); let r = i64x4::new(0, 4575657222473777152, 1065353216, 4575657222473777152); - assert_eq!(r, transmute(lasx_xvfrint_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6652,7 +7941,7 @@ unsafe fn test_lasx_xvfrint_d() { 0, ); - assert_eq!(r, transmute(lasx_xvfrint_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6668,7 +7957,7 @@ unsafe fn test_lasx_xvfrsqrt_s() { 4651901116840286347, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6686,7 +7975,7 @@ unsafe fn test_lasx_xvfrsqrt_d() { 4612495411087822923, ); - assert_eq!(r, transmute(lasx_xvfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6702,7 +7991,7 @@ unsafe fn test_lasx_xvflogb_s() { -4575657218195587072, ); - assert_eq!(r, transmute(lasx_xvflogb_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6720,7 +8009,7 @@ unsafe fn test_lasx_xvflogb_d() { -4616189618054758400, ); - assert_eq!(r, transmute(lasx_xvflogb_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6736,7 +8025,7 @@ unsafe fn test_lasx_xvfcvth_s_h() { 4931511963987271680, ); - assert_eq!(r, transmute(lasx_xvfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6752,7 +8041,7 @@ unsafe fn test_lasx_xvfcvth_d_s() { 4605684912954015744, ); - assert_eq!(r, transmute(lasx_xvfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6768,7 +8057,7 @@ unsafe fn test_lasx_xvfcvtl_s_h() { 4719033540912152576, ); - assert_eq!(r, transmute(lasx_xvfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6784,7 +8073,7 @@ unsafe fn test_lasx_xvfcvtl_d_s() { 4598772185639682048, ); - assert_eq!(r, transmute(lasx_xvfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6795,7 +8084,7 @@ unsafe fn test_lasx_xvftint_w_s() { ); let r = i64x4::new(0, 0, 1, 0); - assert_eq!(r, transmute(lasx_xvftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6808,7 +8097,7 @@ unsafe fn test_lasx_xvftint_l_d() { ); let r = i64x4::new(0, 0, 1, 1); - assert_eq!(r, transmute(lasx_xvftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6819,7 +8108,7 @@ unsafe fn test_lasx_xvftint_wu_s() { ); let r = i64x4::new(1, 4294967297, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6832,7 +8121,7 @@ unsafe fn test_lasx_xvftint_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6843,7 +8132,7 @@ unsafe fn test_lasx_xvftintrz_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6856,7 +8145,7 @@ unsafe fn test_lasx_xvftintrz_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6867,7 +8156,7 @@ unsafe fn test_lasx_xvftintrz_wu_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6880,7 +8169,7 @@ unsafe fn test_lasx_xvftintrz_lu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6902,7 +8191,7 @@ unsafe fn test_lasx_xvffint_s_w() { 5669248528000103797, ); - assert_eq!(r, transmute(lasx_xvffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6920,7 +8209,7 @@ unsafe fn test_lasx_xvffint_d_l() { -4362160337941248997, ); - assert_eq!(r, transmute(lasx_xvffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6936,7 +8225,7 @@ unsafe fn test_lasx_xvffint_s_wu() { 5723492283472660471, ); - assert_eq!(r, transmute(lasx_xvffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6954,7 +8243,7 @@ unsafe fn test_lasx_xvffint_d_lu() { 4892265567869239358, ); - assert_eq!(r, transmute(lasx_xvffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -6970,7 +8259,7 @@ unsafe fn test_lasx_xvreplve_b() { -5280832617179597130, ); - assert_eq!(r, transmute(lasx_xvreplve_b(transmute(a), 5))); + assert_eq!(r, transmute(lasx_xvreplve_b(black_box(transmute(a)), 5))); } #[simd_test(enable = "lasx")] @@ -6986,7 +8275,7 @@ unsafe fn test_lasx_xvreplve_h() { -8907411554322709406, ); - assert_eq!(r, transmute(lasx_xvreplve_h(transmute(a), -5))); + assert_eq!(r, transmute(lasx_xvreplve_h(black_box(transmute(a)), -5))); } #[simd_test(enable = "lasx")] @@ -7008,7 +8297,7 @@ unsafe fn test_lasx_xvreplve_w() { -2569718735257041300, ); - assert_eq!(r, transmute(lasx_xvreplve_w(transmute(a), 1))); + assert_eq!(r, transmute(lasx_xvreplve_w(black_box(transmute(a)), 1))); } #[simd_test(enable = "lasx")] @@ -7026,7 +8315,7 @@ unsafe fn test_lasx_xvreplve_d() { -7945890434069746992, ); - assert_eq!(r, transmute(lasx_xvreplve_d(transmute(a), -6))); + assert_eq!(r, transmute(lasx_xvreplve_d(black_box(transmute(a)), -6))); } #[simd_test(enable = "lasx")] @@ -7060,7 +8349,10 @@ unsafe fn test_lasx_xvpermi_w() { assert_eq!( r, - transmute(lasx_xvpermi_w::<217>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_w::<217>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -7081,7 +8373,13 @@ unsafe fn test_lasx_xvandn_v() { 5350223724150917, ); - assert_eq!(r, transmute(lasx_xvandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7097,7 +8395,7 @@ unsafe fn test_lasx_xvneg_b() { -5388239603749330053, ); - assert_eq!(r, transmute(lasx_xvneg_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7113,7 +8411,7 @@ unsafe fn test_lasx_xvneg_h() { 5510114370614593991, ); - assert_eq!(r, transmute(lasx_xvneg_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7135,7 +8433,7 @@ unsafe fn test_lasx_xvneg_w() { -6240794077010148150, ); - assert_eq!(r, transmute(lasx_xvneg_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7153,7 +8451,7 @@ unsafe fn test_lasx_xvneg_d() { -906750919774206543, ); - assert_eq!(r, transmute(lasx_xvneg_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -7173,7 +8471,13 @@ unsafe fn test_lasx_xvmuh_b() { 131228860074087168, ); - assert_eq!(r, transmute(lasx_xvmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7193,7 +8497,13 @@ unsafe fn test_lasx_xvmuh_h() { -14890625691814142, ); - assert_eq!(r, transmute(lasx_xvmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7225,7 +8535,13 @@ unsafe fn test_lasx_xvmuh_w() { 15710306989437773, ); - assert_eq!(r, transmute(lasx_xvmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7249,7 +8565,13 @@ unsafe fn test_lasx_xvmuh_d() { 273863514955286020, ); - assert_eq!(r, transmute(lasx_xvmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7269,7 +8591,13 @@ unsafe fn test_lasx_xvmuh_bu() { 442221464076014683, ); - assert_eq!(r, transmute(lasx_xvmuh_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7289,7 +8617,13 @@ unsafe fn test_lasx_xvmuh_hu() { 108786773599653576, ); - assert_eq!(r, transmute(lasx_xvmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7309,7 +8643,13 @@ unsafe fn test_lasx_xvmuh_wu() { 3278999485098399815, ); - assert_eq!(r, transmute(lasx_xvmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7333,7 +8673,13 @@ unsafe fn test_lasx_xvmuh_du() { 1569823798457591419, ); - assert_eq!(r, transmute(lasx_xvmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7349,7 +8695,10 @@ unsafe fn test_lasx_xvsllwil_h_b() { 283732621893107440, ); - assert_eq!(r, transmute(lasx_xvsllwil_h_b::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_h_b::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7365,7 +8714,10 @@ unsafe fn test_lasx_xvsllwil_w_h() { -19087521822982144, ); - assert_eq!(r, transmute(lasx_xvsllwil_w_h::<11>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_w_h::<11>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7387,7 +8739,10 @@ unsafe fn test_lasx_xvsllwil_d_w() { -21769464725504, ); - assert_eq!(r, transmute(lasx_xvsllwil_d_w::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_d_w::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7403,7 +8758,10 @@ unsafe fn test_lasx_xvsllwil_hu_bu() { 180156217344131904, ); - assert_eq!(r, transmute(lasx_xvsllwil_hu_bu::<5>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_hu_bu::<5>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7419,7 +8777,10 @@ unsafe fn test_lasx_xvsllwil_wu_hu() { 3493526673607606272, ); - assert_eq!(r, transmute(lasx_xvsllwil_wu_hu::<14>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_wu_hu::<14>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7435,7 +8796,10 @@ unsafe fn test_lasx_xvsllwil_du_wu() { 147522340803051520, ); - assert_eq!(r, transmute(lasx_xvsllwil_du_wu::<28>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvsllwil_du_wu::<28>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -7450,7 +8814,13 @@ unsafe fn test_lasx_xvsran_b_h() { ); let r = i64x4::new(-5107013816536599300, 0, -576745268203292981, 0); - assert_eq!(r, transmute(lasx_xvsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7477,7 +8847,13 @@ unsafe fn test_lasx_xvsran_h_w() { ); let r = i64x4::new(-7492863874014043255, 0, -5145548381371170633, 0); - assert_eq!(r, transmute(lasx_xvsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7496,7 +8872,13 @@ unsafe fn test_lasx_xvsran_w_d() { ); let r = i64x4::new(58054624080, 0, 1863787881113495402, 0); - assert_eq!(r, transmute(lasx_xvsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7511,7 +8893,13 @@ unsafe fn test_lasx_xvssran_b_h() { ); let r = i64x4::new(179865806513864501, 0, -9222296776751415043, 0); - assert_eq!(r, transmute(lasx_xvssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7538,7 +8926,13 @@ unsafe fn test_lasx_xvssran_h_w() { ); let r = i64x4::new(281015415144451, 0, 281472829161978, 0); - assert_eq!(r, transmute(lasx_xvssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7557,7 +8951,13 @@ unsafe fn test_lasx_xvssran_w_d() { ); let r = i64x4::new(-109363692856335914, 0, -713658208354305, 0); - assert_eq!(r, transmute(lasx_xvssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7572,7 +8972,13 @@ unsafe fn test_lasx_xvssran_bu_h() { ); let r = i64x4::new(144116287595479055, 0, 71776131929997312, 0); - assert_eq!(r, transmute(lasx_xvssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7587,7 +8993,13 @@ unsafe fn test_lasx_xvssran_hu_w() { ); let r = i64x4::new(254837589540863, 0, 281470681765343, 0); - assert_eq!(r, transmute(lasx_xvssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7606,7 +9018,13 @@ unsafe fn test_lasx_xvssran_wu_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7621,7 +9039,13 @@ unsafe fn test_lasx_xvsrarn_b_h() { ); let r = i64x4::new(-7204067930850651184, 0, -5909457163402939758, 0); - assert_eq!(r, transmute(lasx_xvsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7648,7 +9072,13 @@ unsafe fn test_lasx_xvsrarn_h_w() { ); let r = i64x4::new(4021320339558432771, 0, -5499970420202995712, 0); - assert_eq!(r, transmute(lasx_xvsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7667,7 +9097,13 @@ unsafe fn test_lasx_xvsrarn_w_d() { ); let r = i64x4::new(-69752906595470, 0, -7240468610764767136, 0); - assert_eq!(r, transmute(lasx_xvsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7682,7 +9118,13 @@ unsafe fn test_lasx_xvssrarn_b_h() { ); let r = i64x4::new(142413695971000447, 0, -141179869986524, 0); - assert_eq!(r, transmute(lasx_xvssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7709,7 +9151,13 @@ unsafe fn test_lasx_xvssrarn_h_w() { ); let r = i64x4::new(-10414028872220672, 0, 9223104806137135104, 0); - assert_eq!(r, transmute(lasx_xvssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7728,7 +9176,13 @@ unsafe fn test_lasx_xvssrarn_w_d() { ); let r = i64x4::new(2147483648, 0, 326062786704572415, 0); - assert_eq!(r, transmute(lasx_xvssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7743,7 +9197,13 @@ unsafe fn test_lasx_xvssrarn_bu_h() { ); let r = i64x4::new(4286578689, 0, 8163878114427135, 0); - assert_eq!(r, transmute(lasx_xvssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7758,7 +9218,13 @@ unsafe fn test_lasx_xvssrarn_hu_w() { ); let r = i64x4::new(-281474976710656, 0, 2199023255552, 0); - assert_eq!(r, transmute(lasx_xvssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7777,7 +9243,13 @@ unsafe fn test_lasx_xvssrarn_wu_d() { ); let r = i64x4::new(-3539373509, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7792,7 +9264,13 @@ unsafe fn test_lasx_xvsrln_b_h() { ); let r = i64x4::new(776589499955319005, 0, 285495199351976, 0); - assert_eq!(r, transmute(lasx_xvsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7819,7 +9297,13 @@ unsafe fn test_lasx_xvsrln_h_w() { ); let r = i64x4::new(-6090306652816735409, 0, -1175228277373752196, 0); - assert_eq!(r, transmute(lasx_xvsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7838,7 +9322,13 @@ unsafe fn test_lasx_xvsrln_w_d() { ); let r = i64x4::new(262796920316080678, 0, 1866060245111069, 0); - assert_eq!(r, transmute(lasx_xvsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7853,7 +9343,13 @@ unsafe fn test_lasx_xvssrln_bu_h() { ); let r = i64x4::new(-996419305685, 0, -71773920038018305, 0); - assert_eq!(r, transmute(lasx_xvssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7867,7 +9363,13 @@ unsafe fn test_lasx_xvssrln_hu_w() { ); let r = i64x4::new(2319476961249468, 0, 208855326080470286, 0); - assert_eq!(r, transmute(lasx_xvssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7886,7 +9388,13 @@ unsafe fn test_lasx_xvssrln_wu_d() { ); let r = i64x4::new(-1, 0, -1, 0); - assert_eq!(r, transmute(lasx_xvssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7901,7 +9409,13 @@ unsafe fn test_lasx_xvsrlrn_b_h() { ); let r = i64x4::new(-6693460433276960310, 0, -6122543899663285619, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7928,7 +9442,13 @@ unsafe fn test_lasx_xvsrlrn_h_w() { ); let r = i64x4::new(390723813551243448, 0, 6015496732136052023, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7947,7 +9467,13 @@ unsafe fn test_lasx_xvsrlrn_w_d() { ); let r = i64x4::new(4295025675, 0, -3281590872273059757, 0); - assert_eq!(r, transmute(lasx_xvsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7962,7 +9488,13 @@ unsafe fn test_lasx_xvssrlrn_bu_h() { ); let r = i64x4::new(-258385232527491, 0, 4034951496335359804, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7977,7 +9509,13 @@ unsafe fn test_lasx_xvssrlrn_hu_w() { ); let r = i64x4::new(-3854303052, 0, -4029743103, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -7996,7 +9534,13 @@ unsafe fn test_lasx_xvssrlrn_wu_d() { ); let r = i64x4::new(-3223981555, 0, 35952127557763071, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8018,7 +9562,10 @@ unsafe fn test_lasx_xvfrstpi_b() { assert_eq!( r, - transmute(lasx_xvfrstpi_b::<24>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_b::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8041,7 +9588,10 @@ unsafe fn test_lasx_xvfrstpi_h() { assert_eq!( r, - transmute(lasx_xvfrstpi_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvfrstpi_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8068,7 +9618,11 @@ unsafe fn test_lasx_xvfrstp_b() { assert_eq!( r, - transmute(lasx_xvfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8095,7 +9649,11 @@ unsafe fn test_lasx_xvfrstp_h() { assert_eq!( r, - transmute(lasx_xvfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8122,7 +9680,10 @@ unsafe fn test_lasx_xvshuf4i_d() { assert_eq!( r, - transmute(lasx_xvshuf4i_d::<115>(transmute(a), transmute(b))) + transmute(lasx_xvshuf4i_d::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8139,7 +9700,7 @@ unsafe fn test_lasx_xvbsrl_v() { 8842437361645499941, ); - assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsrl_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8155,7 +9716,7 @@ unsafe fn test_lasx_xvbsll_v() { 5030360181484275352, ); - assert_eq!(r, transmute(lasx_xvbsll_v::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvbsll_v::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8177,7 +9738,10 @@ unsafe fn test_lasx_xvextrins_b() { assert_eq!( r, - transmute(lasx_xvextrins_b::<69>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_b::<69>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8200,7 +9764,10 @@ unsafe fn test_lasx_xvextrins_h() { assert_eq!( r, - transmute(lasx_xvextrins_h::<190>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_h::<190>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8235,7 +9802,10 @@ unsafe fn test_lasx_xvextrins_w() { assert_eq!( r, - transmute(lasx_xvextrins_w::<133>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_w::<133>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8262,7 +9832,10 @@ unsafe fn test_lasx_xvextrins_d() { assert_eq!( r, - transmute(lasx_xvextrins_d::<210>(transmute(a), transmute(b))) + transmute(lasx_xvextrins_d::<210>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8274,7 +9847,7 @@ unsafe fn test_lasx_xvmskltz_b() { ); let r = i64x4::new(5684, 0, 36244, 0); - assert_eq!(r, transmute(lasx_xvmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8285,7 +9858,7 @@ unsafe fn test_lasx_xvmskltz_h() { ); let r = i64x4::new(225, 0, 96, 0); - assert_eq!(r, transmute(lasx_xvmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8302,7 +9875,7 @@ unsafe fn test_lasx_xvmskltz_w() { ); let r = i64x4::new(13, 0, 10, 0); - assert_eq!(r, transmute(lasx_xvmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8315,7 +9888,7 @@ unsafe fn test_lasx_xvmskltz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8335,7 +9908,13 @@ unsafe fn test_lasx_xvsigncov_b() { -6215157037026399088, ); - assert_eq!(r, transmute(lasx_xvsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8355,7 +9934,13 @@ unsafe fn test_lasx_xvsigncov_h() { 2866604565619890601, ); - assert_eq!(r, transmute(lasx_xvsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8387,7 +9972,13 @@ unsafe fn test_lasx_xvsigncov_w() { -180354238538399451, ); - assert_eq!(r, transmute(lasx_xvsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8411,7 +10002,13 @@ unsafe fn test_lasx_xvsigncov_d() { 293290471183495768, ); - assert_eq!(r, transmute(lasx_xvsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8437,7 +10034,11 @@ unsafe fn test_lasx_xvfmadd_s() { assert_eq!( r, - transmute(lasx_xvfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8470,7 +10071,11 @@ unsafe fn test_lasx_xvfmadd_d() { assert_eq!( r, - transmute(lasx_xvfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8497,7 +10102,11 @@ unsafe fn test_lasx_xvfmsub_s() { assert_eq!( r, - transmute(lasx_xvfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8530,7 +10139,11 @@ unsafe fn test_lasx_xvfmsub_d() { assert_eq!( r, - transmute(lasx_xvfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8557,7 +10170,11 @@ unsafe fn test_lasx_xvfnmadd_s() { assert_eq!( r, - transmute(lasx_xvfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8590,7 +10207,11 @@ unsafe fn test_lasx_xvfnmadd_d() { assert_eq!( r, - transmute(lasx_xvfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8617,7 +10238,11 @@ unsafe fn test_lasx_xvfnmsub_s() { assert_eq!( r, - transmute(lasx_xvfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8650,7 +10275,11 @@ unsafe fn test_lasx_xvfnmsub_d() { assert_eq!( r, - transmute(lasx_xvfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -8662,7 +10291,7 @@ unsafe fn test_lasx_xvftintrne_w_s() { ); let r = i64x4::new(1, 0, 1, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8675,7 +10304,7 @@ unsafe fn test_lasx_xvftintrne_l_d() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8686,7 +10315,7 @@ unsafe fn test_lasx_xvftintrp_w_s() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8699,7 +10328,7 @@ unsafe fn test_lasx_xvftintrp_l_d() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8710,7 +10339,7 @@ unsafe fn test_lasx_xvftintrm_w_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8723,7 +10352,7 @@ unsafe fn test_lasx_xvftintrm_l_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8742,7 +10371,13 @@ unsafe fn test_lasx_xvftint_w_d() { ); let r = i64x4::new(0, 0, 4294967297, 4294967296); - assert_eq!(r, transmute(lasx_xvftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8766,7 +10401,13 @@ unsafe fn test_lasx_xvffint_s_l() { -2383622820954443903, ); - assert_eq!(r, transmute(lasx_xvffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8785,7 +10426,13 @@ unsafe fn test_lasx_xvftintrz_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8804,7 +10451,13 @@ unsafe fn test_lasx_xvftintrp_w_d() { ); let r = i64x4::new(4294967297, 4294967297, 4294967297, 4294967297); - assert_eq!(r, transmute(lasx_xvftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8823,7 +10476,13 @@ unsafe fn test_lasx_xvftintrm_w_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -8844,7 +10503,10 @@ unsafe fn test_lasx_xvftintrne_w_d() { assert_eq!( r, - transmute(lasx_xvftintrne_w_d(transmute(a), transmute(b))) + transmute(lasx_xvftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -8856,7 +10518,7 @@ unsafe fn test_lasx_xvftinth_l_s() { ); let r = i64x4::new(0, 1, 0, 1); - assert_eq!(r, transmute(lasx_xvftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8867,7 +10529,7 @@ unsafe fn test_lasx_xvftintl_l_s() { ); let r = i64x4::new(0, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8889,7 +10551,7 @@ unsafe fn test_lasx_xvffinth_d_w() { -4485741486683455488, ); - assert_eq!(r, transmute(lasx_xvffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8911,7 +10573,7 @@ unsafe fn test_lasx_xvffintl_d_w() { -4489746915386195968, ); - assert_eq!(r, transmute(lasx_xvffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8922,7 +10584,7 @@ unsafe fn test_lasx_xvftintrzh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8933,7 +10595,7 @@ unsafe fn test_lasx_xvftintrzl_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8944,7 +10606,7 @@ unsafe fn test_lasx_xvftintrph_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8955,7 +10617,7 @@ unsafe fn test_lasx_xvftintrpl_l_s() { ); let r = i64x4::new(1, 1, 1, 1); - assert_eq!(r, transmute(lasx_xvftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8966,7 +10628,7 @@ unsafe fn test_lasx_xvftintrmh_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8977,7 +10639,7 @@ unsafe fn test_lasx_xvftintrml_l_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8988,7 +10650,7 @@ unsafe fn test_lasx_xvftintrneh_l_s() { ); let r = i64x4::new(1, 0, 0, 1); - assert_eq!(r, transmute(lasx_xvftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -8999,7 +10661,7 @@ unsafe fn test_lasx_xvftintrnel_l_s() { ); let r = i64x4::new(0, 1, 1, 0); - assert_eq!(r, transmute(lasx_xvftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9015,7 +10677,7 @@ unsafe fn test_lasx_xvfrintrne_s() { 1065353216, ); - assert_eq!(r, transmute(lasx_xvfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9028,7 +10690,7 @@ unsafe fn test_lasx_xvfrintrne_d() { ); let r = i64x4::new(0, 0, 4607182418800017408, 0); - assert_eq!(r, transmute(lasx_xvfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9039,7 +10701,7 @@ unsafe fn test_lasx_xvfrintrz_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9052,7 +10714,7 @@ unsafe fn test_lasx_xvfrintrz_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9068,7 +10730,7 @@ unsafe fn test_lasx_xvfrintrp_s() { 4575657222473777152, ); - assert_eq!(r, transmute(lasx_xvfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9086,7 +10748,7 @@ unsafe fn test_lasx_xvfrintrp_d() { 4607182418800017408, ); - assert_eq!(r, transmute(lasx_xvfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9097,7 +10759,7 @@ unsafe fn test_lasx_xvfrintrm_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9110,7 +10772,7 @@ unsafe fn test_lasx_xvfrintrm_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9146,7 +10808,7 @@ unsafe fn test_lasx_xvst() { -1239470096778490055, ); - lasx_xvst::<0>(transmute(a), o.as_mut_ptr()); + lasx_xvst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9167,7 +10829,7 @@ unsafe fn test_lasx_xvstelm_b() { -1243134694581333281, ); - lasx_xvstelm_b::<0, 9>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_b::<0, 9>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9188,7 +10850,7 @@ unsafe fn test_lasx_xvstelm_h() { 4649151313692342074, ); - lasx_xvstelm_h::<0, 6>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_h::<0, 6>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9215,7 +10877,7 @@ unsafe fn test_lasx_xvstelm_w() { 5471549130760739388, ); - lasx_xvstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9238,7 +10900,7 @@ unsafe fn test_lasx_xvstelm_d() { -4006899083251152793, ); - lasx_xvstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lasx_xvstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -9273,7 +10935,10 @@ unsafe fn test_lasx_xvinsve0_w() { assert_eq!( r, - transmute(lasx_xvinsve0_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9300,7 +10965,10 @@ unsafe fn test_lasx_xvinsve0_d() { assert_eq!( r, - transmute(lasx_xvinsve0_d::<3>(transmute(a), transmute(b))) + transmute(lasx_xvinsve0_d::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9318,7 +10986,7 @@ unsafe fn test_lasx_xvpickve_w() { ); let r = i64x4::new(1138467779, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9331,7 +10999,7 @@ unsafe fn test_lasx_xvpickve_d() { ); let r = i64x4::new(8402618222187512066, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpickve_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9346,7 +11014,13 @@ unsafe fn test_lasx_xvssrlrn_b_h() { ); let r = i64x4::new(3463408299017240959, 0, 35748968851799935, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9373,7 +11047,13 @@ unsafe fn test_lasx_xvssrlrn_h_w() { ); let r = i64x4::new(422210317549567, 0, 11259106657337343, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9392,7 +11072,13 @@ unsafe fn test_lasx_xvssrlrn_w_d() { ); let r = i64x4::new(33428474336875, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9407,7 +11093,13 @@ unsafe fn test_lasx_xvssrln_b_h() { ); let r = i64x4::new(657383790217428863, 0, 941881790371430152, 0); - assert_eq!(r, transmute(lasx_xvssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9434,7 +11126,13 @@ unsafe fn test_lasx_xvssrln_h_w() { ); let r = i64x4::new(9223103287866884105, 0, 1696871892814295669, 0); - assert_eq!(r, transmute(lasx_xvssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9453,7 +11151,13 @@ unsafe fn test_lasx_xvssrln_w_d() { ); let r = i64x4::new(3937140138060021759, 0, 9223372034707292159, 0); - assert_eq!(r, transmute(lasx_xvssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9473,7 +11177,13 @@ unsafe fn test_lasx_xvorn_v() { -126121887133672977, ); - assert_eq!(r, transmute(lasx_xvorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvorn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9521,7 +11231,7 @@ unsafe fn test_lasx_xvstx() { -4162173646616256791, ); - lasx_xvstx(transmute(a), o.as_mut_ptr(), 0); + lasx_xvstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -9535,7 +11245,7 @@ unsafe fn test_lasx_xvextl_qu_du() { ); let r = i64x4::new(-5083351180651141737, 0, 4121325568380818738, 0); - assert_eq!(r, transmute(lasx_xvextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9559,7 +11269,7 @@ unsafe fn test_lasx_xvinsgr2vr_w() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_w::<4>(transmute(a), -596457645)) + transmute(lasx_xvinsgr2vr_w::<4>(black_box(transmute(a)), -596457645)) ); } @@ -9580,7 +11290,7 @@ unsafe fn test_lasx_xvinsgr2vr_d() { assert_eq!( r, - transmute(lasx_xvinsgr2vr_d::<3>(transmute(a), -1262509914)) + transmute(lasx_xvinsgr2vr_d::<3>(black_box(transmute(a)), -1262509914)) ); } @@ -9597,7 +11307,7 @@ unsafe fn test_lasx_xvreplve0_b() { 3472328296227680304, ); - assert_eq!(r, transmute(lasx_xvreplve0_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9613,7 +11323,7 @@ unsafe fn test_lasx_xvreplve0_h() { 115969459958317468, ); - assert_eq!(r, transmute(lasx_xvreplve0_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9635,7 +11345,7 @@ unsafe fn test_lasx_xvreplve0_w() { 5341799334363128369, ); - assert_eq!(r, transmute(lasx_xvreplve0_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9653,7 +11363,7 @@ unsafe fn test_lasx_xvreplve0_d() { -7669512117913941619, ); - assert_eq!(r, transmute(lasx_xvreplve0_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9669,7 +11379,7 @@ unsafe fn test_lasx_xvreplve0_q() { -7451765666000961269, ); - assert_eq!(r, transmute(lasx_xvreplve0_q(transmute(a)))); + assert_eq!(r, transmute(lasx_xvreplve0_q(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9685,7 +11395,7 @@ unsafe fn test_lasx_vext2xv_h_b() { 24207148650070059, ); - assert_eq!(r, transmute(lasx_vext2xv_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9701,7 +11411,7 @@ unsafe fn test_lasx_vext2xv_w_h() { -34359738358622, ); - assert_eq!(r, transmute(lasx_vext2xv_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9718,7 +11428,7 @@ unsafe fn test_lasx_vext2xv_d_w() { ); let r = i64x4::new(-585251458, -2113345963, -1846838006, -474453663); - assert_eq!(r, transmute(lasx_vext2xv_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9729,7 +11439,7 @@ unsafe fn test_lasx_vext2xv_w_b() { ); let r = i64x4::new(-240518168540, -528280977282, 30064770965, -489626271740); - assert_eq!(r, transmute(lasx_vext2xv_w_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_w_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9740,7 +11450,7 @@ unsafe fn test_lasx_vext2xv_d_h() { ); let r = i64x4::new(28568, -25911, 12053, -2728); - assert_eq!(r, transmute(lasx_vext2xv_d_h(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9751,7 +11461,7 @@ unsafe fn test_lasx_vext2xv_d_b() { ); let r = i64x4::new(18, 112, -36, -67); - assert_eq!(r, transmute(lasx_vext2xv_d_b(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_d_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9767,7 +11477,7 @@ unsafe fn test_lasx_vext2xv_hu_bu() { 16888898041348298, ); - assert_eq!(r, transmute(lasx_vext2xv_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9783,7 +11493,7 @@ unsafe fn test_lasx_vext2xv_wu_hu() { 225172250484459, ); - assert_eq!(r, transmute(lasx_vext2xv_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9800,7 +11510,7 @@ unsafe fn test_lasx_vext2xv_du_wu() { ); let r = i64x4::new(4027501046, 3358638690, 2495633600, 1035808674); - assert_eq!(r, transmute(lasx_vext2xv_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9811,7 +11521,7 @@ unsafe fn test_lasx_vext2xv_wu_bu() { ); let r = i64x4::new(987842478134, 481036337184, 266287972487, 979252543649); - assert_eq!(r, transmute(lasx_vext2xv_wu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_wu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9822,7 +11532,7 @@ unsafe fn test_lasx_vext2xv_du_hu() { ); let r = i64x4::new(61301, 41410, 35355, 19598); - assert_eq!(r, transmute(lasx_vext2xv_du_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9833,7 +11543,7 @@ unsafe fn test_lasx_vext2xv_du_bu() { ); let r = i64x4::new(69, 25, 36, 204); - assert_eq!(r, transmute(lasx_vext2xv_du_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_vext2xv_du_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9855,7 +11565,10 @@ unsafe fn test_lasx_xvpermi_q() { assert_eq!( r, - transmute(lasx_xvpermi_q::<49>(transmute(a), transmute(b))) + transmute(lasx_xvpermi_q::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -9874,7 +11587,7 @@ unsafe fn test_lasx_xvpermi_d() { 1609032298240495217, ); - assert_eq!(r, transmute(lasx_xvpermi_d::<137>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvpermi_d::<137>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -9900,7 +11613,13 @@ unsafe fn test_lasx_xvperm_w() { -3042141963630030871, ); - assert_eq!(r, transmute(lasx_xvperm_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvperm_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -9981,7 +11700,10 @@ unsafe fn test_lasx_xvpickve2gr_w() { ); let r: i32 = 1367768596; - assert_eq!(r, transmute(lasx_xvpickve2gr_w::<4>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_w::<4>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -9998,7 +11720,10 @@ unsafe fn test_lasx_xvpickve2gr_wu() { ); let r: u32 = 3194994707; - assert_eq!(r, transmute(lasx_xvpickve2gr_wu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_wu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10011,7 +11736,10 @@ unsafe fn test_lasx_xvpickve2gr_d() { ); let r: i64 = 6739870851682505277; - assert_eq!(r, transmute(lasx_xvpickve2gr_d::<2>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_d::<2>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10024,7 +11752,10 @@ unsafe fn test_lasx_xvpickve2gr_du() { ); let r: u64 = 9525833175373449635; - assert_eq!(r, transmute(lasx_xvpickve2gr_du::<3>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve2gr_du::<3>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -10043,7 +11774,13 @@ unsafe fn test_lasx_xvaddwev_q_d() { ); let r = i64x4::new(-7472750192138786681, -1, -7758725841623301722, -1); - assert_eq!(r, transmute(lasx_xvaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10070,7 +11807,13 @@ unsafe fn test_lasx_xvaddwev_d_w() { ); let r = i64x4::new(614980351, -1946929141, -3309402607, -619077207); - assert_eq!(r, transmute(lasx_xvaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10090,7 +11833,13 @@ unsafe fn test_lasx_xvaddwev_w_h() { -232787227420502, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10110,7 +11859,13 @@ unsafe fn test_lasx_xvaddwev_h_b() { -10414449598922739, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10129,7 +11884,13 @@ unsafe fn test_lasx_xvaddwev_q_du() { ); let r = i64x4::new(4866121314102936184, 1, 898239984703082844, 1); - assert_eq!(r, transmute(lasx_xvaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10144,7 +11905,13 @@ unsafe fn test_lasx_xvaddwev_d_wu() { ); let r = i64x4::new(4001409528, 3398767892, 6021892971, 4349349069); - assert_eq!(r, transmute(lasx_xvaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10164,7 +11931,13 @@ unsafe fn test_lasx_xvaddwev_w_hu() { 376479653317006, ); - assert_eq!(r, transmute(lasx_xvaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10184,7 +11957,13 @@ unsafe fn test_lasx_xvaddwev_h_bu() { 68962872563859917, ); - assert_eq!(r, transmute(lasx_xvaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10203,7 +11982,13 @@ unsafe fn test_lasx_xvsubwev_q_d() { ); let r = i64x4::new(8183582659207736591, -1, 5496584216395980167, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10230,7 +12015,13 @@ unsafe fn test_lasx_xvsubwev_d_w() { ); let r = i64x4::new(-1945765730, 1700549847, -1218066002, -827282692); - assert_eq!(r, transmute(lasx_xvsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10250,7 +12041,13 @@ unsafe fn test_lasx_xvsubwev_w_h() { 217514323726817, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10270,7 +12067,13 @@ unsafe fn test_lasx_xvsubwev_h_b() { -5910188531122352, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10289,7 +12092,13 @@ unsafe fn test_lasx_xvsubwev_q_du() { ); let r = i64x4::new(-7180841769120666233, -1, -3901807980557405007, -1); - assert_eq!(r, transmute(lasx_xvsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10304,7 +12113,13 @@ unsafe fn test_lasx_xvsubwev_d_wu() { ); let r = i64x4::new(-2531041484, -1085343469, -1900376905, 1600829569); - assert_eq!(r, transmute(lasx_xvsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10324,7 +12139,13 @@ unsafe fn test_lasx_xvsubwev_w_hu() { -117029268872947, ); - assert_eq!(r, transmute(lasx_xvsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10344,7 +12165,13 @@ unsafe fn test_lasx_xvsubwev_h_bu() { -7035942402260810, ); - assert_eq!(r, transmute(lasx_xvsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10368,7 +12195,13 @@ unsafe fn test_lasx_xvmulwev_q_d() { -2723954123981949807, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10400,7 +12233,13 @@ unsafe fn test_lasx_xvmulwev_d_w() { 904288373202150940, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10420,7 +12259,13 @@ unsafe fn test_lasx_xvmulwev_w_h() { -218736636965849761, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10440,7 +12285,13 @@ unsafe fn test_lasx_xvmulwev_h_b() { -532018857412992924, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10464,7 +12315,13 @@ unsafe fn test_lasx_xvmulwev_q_du() { 1973424773030267173, ); - assert_eq!(r, transmute(lasx_xvmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10484,7 +12341,13 @@ unsafe fn test_lasx_xvmulwev_d_wu() { 312983850752328844, ); - assert_eq!(r, transmute(lasx_xvmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10504,7 +12367,13 @@ unsafe fn test_lasx_xvmulwev_w_hu() { -4803214827614038190, ); - assert_eq!(r, transmute(lasx_xvmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10524,7 +12393,13 @@ unsafe fn test_lasx_xvmulwev_h_bu() { 4458585836433706972, ); - assert_eq!(r, transmute(lasx_xvmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10543,7 +12418,13 @@ unsafe fn test_lasx_xvaddwod_q_d() { ); let r = i64x4::new(-3813723879058076957, 0, 200103109406722390, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10570,7 +12451,13 @@ unsafe fn test_lasx_xvaddwod_d_w() { ); let r = i64x4::new(3142724184, -2585235328, -785720463, 926940003); - assert_eq!(r, transmute(lasx_xvaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10590,7 +12477,13 @@ unsafe fn test_lasx_xvaddwod_w_h() { -148498494282599, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10610,7 +12503,13 @@ unsafe fn test_lasx_xvaddwod_h_b() { -9570449863999416, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10629,7 +12528,13 @@ unsafe fn test_lasx_xvaddwod_q_du() { ); let r = i64x4::new(751645223963476143, 1, -1275901335613508018, 0); - assert_eq!(r, transmute(lasx_xvaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10644,7 +12549,13 @@ unsafe fn test_lasx_xvaddwod_d_wu() { ); let r = i64x4::new(4757884041, 1673456593, 2162927615, 5143136401); - assert_eq!(r, transmute(lasx_xvaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10664,7 +12575,13 @@ unsafe fn test_lasx_xvaddwod_w_hu() { 248416613500221, ); - assert_eq!(r, transmute(lasx_xvaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10684,7 +12601,13 @@ unsafe fn test_lasx_xvaddwod_h_bu() { 83880238860075230, ); - assert_eq!(r, transmute(lasx_xvaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10703,7 +12626,13 @@ unsafe fn test_lasx_xvsubwod_q_d() { ); let r = i64x4::new(1764856097736252489, 0, 7683656878360999333, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10730,7 +12659,13 @@ unsafe fn test_lasx_xvsubwod_d_w() { ); let r = i64x4::new(-959924898, 7572903, 2106559810, 3976421257); - assert_eq!(r, transmute(lasx_xvsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10750,7 +12685,13 @@ unsafe fn test_lasx_xvsubwod_w_h() { -17665200524651, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10770,7 +12711,13 @@ unsafe fn test_lasx_xvsubwod_h_b() { -3939721971105776, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10789,7 +12736,13 @@ unsafe fn test_lasx_xvsubwod_q_du() { ); let r = i64x4::new(-6069526046627127478, -1, -1804068722113556285, -1); - assert_eq!(r, transmute(lasx_xvsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10804,7 +12757,13 @@ unsafe fn test_lasx_xvsubwod_d_wu() { ); let r = i64x4::new(762157671, -772219478, -1655146846, -1402401592); - assert_eq!(r, transmute(lasx_xvsubwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10824,7 +12783,13 @@ unsafe fn test_lasx_xvsubwod_w_hu() { 164866614644743, ); - assert_eq!(r, transmute(lasx_xvsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10844,7 +12809,13 @@ unsafe fn test_lasx_xvsubwod_h_bu() { -280740536975491, ); - assert_eq!(r, transmute(lasx_xvsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10868,7 +12839,13 @@ unsafe fn test_lasx_xvmulwod_q_d() { -113061080830775254, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10900,7 +12877,13 @@ unsafe fn test_lasx_xvmulwod_d_w() { -1334126209007208500, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10920,7 +12903,13 @@ unsafe fn test_lasx_xvmulwod_w_h() { 337273560374881751, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10940,7 +12929,13 @@ unsafe fn test_lasx_xvmulwod_h_b() { -797714991416606612, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10964,7 +12959,13 @@ unsafe fn test_lasx_xvmulwod_q_du() { -6864651532066967840, ); - assert_eq!(r, transmute(lasx_xvmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -10984,7 +12985,13 @@ unsafe fn test_lasx_xvmulwod_d_wu() { 170736982952013264, ); - assert_eq!(r, transmute(lasx_xvmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11004,7 +13011,13 @@ unsafe fn test_lasx_xvmulwod_w_hu() { 648970298882764352, ); - assert_eq!(r, transmute(lasx_xvmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11024,7 +13037,13 @@ unsafe fn test_lasx_xvmulwod_h_bu() { 861263883582730760, ); - assert_eq!(r, transmute(lasx_xvmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11047,7 +13066,10 @@ unsafe fn test_lasx_xvaddwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11070,7 +13092,10 @@ unsafe fn test_lasx_xvaddwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11093,7 +13118,10 @@ unsafe fn test_lasx_xvaddwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11122,7 +13150,10 @@ unsafe fn test_lasx_xvmulwev_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwev_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11145,7 +13176,10 @@ unsafe fn test_lasx_xvmulwev_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwev_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11168,7 +13202,10 @@ unsafe fn test_lasx_xvmulwev_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwev_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11192,7 +13229,10 @@ unsafe fn test_lasx_xvaddwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvaddwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11215,7 +13255,10 @@ unsafe fn test_lasx_xvaddwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvaddwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11238,7 +13281,10 @@ unsafe fn test_lasx_xvaddwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvaddwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11267,7 +13313,10 @@ unsafe fn test_lasx_xvmulwod_d_wu_w() { assert_eq!( r, - transmute(lasx_xvmulwod_d_wu_w(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11290,7 +13339,10 @@ unsafe fn test_lasx_xvmulwod_w_hu_h() { assert_eq!( r, - transmute(lasx_xvmulwod_w_hu_h(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11313,7 +13365,10 @@ unsafe fn test_lasx_xvmulwod_h_bu_b() { assert_eq!( r, - transmute(lasx_xvmulwod_h_bu_b(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -11333,7 +13388,13 @@ unsafe fn test_lasx_xvhaddw_q_d() { ); let r = i64x4::new(7070440900316630840, -1, 4582440905924999074, 0); - assert_eq!(r, transmute(lasx_xvhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11352,7 +13413,13 @@ unsafe fn test_lasx_xvhaddw_qu_du() { ); let r = i64x4::new(-6342973196760799579, 0, -6232960347008472572, 1); - assert_eq!(r, transmute(lasx_xvhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11371,7 +13438,13 @@ unsafe fn test_lasx_xvhsubw_q_d() { ); let r = i64x4::new(5317548498597883842, 0, 6155348192460751216, -1); - assert_eq!(r, transmute(lasx_xvhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11390,7 +13463,13 @@ unsafe fn test_lasx_xvhsubw_qu_du() { ); let r = i64x4::new(11053881530518619, 0, -1215853579082277290, -1); - assert_eq!(r, transmute(lasx_xvhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -11422,7 +13501,11 @@ unsafe fn test_lasx_xvmaddwev_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11463,7 +13546,11 @@ unsafe fn test_lasx_xvmaddwev_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11496,7 +13583,11 @@ unsafe fn test_lasx_xvmaddwev_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11523,7 +13614,11 @@ unsafe fn test_lasx_xvmaddwev_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11557,9 +13652,9 @@ unsafe fn test_lasx_xvmaddwev_q_du() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11590,9 +13685,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11621,9 +13716,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11652,9 +13747,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11688,7 +13783,11 @@ unsafe fn test_lasx_xvmaddwod_q_d() { assert_eq!( r, - transmute(lasx_xvmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11729,7 +13828,11 @@ unsafe fn test_lasx_xvmaddwod_d_w() { assert_eq!( r, - transmute(lasx_xvmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11762,7 +13865,11 @@ unsafe fn test_lasx_xvmaddwod_w_h() { assert_eq!( r, - transmute(lasx_xvmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11789,7 +13896,11 @@ unsafe fn test_lasx_xvmaddwod_h_b() { assert_eq!( r, - transmute(lasx_xvmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lasx_xvmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -11823,9 +13934,9 @@ unsafe fn test_lasx_xvmaddwod_q_du() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11856,9 +13967,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11887,9 +13998,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11918,9 +14029,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11955,9 +14066,9 @@ unsafe fn test_lasx_xvmaddwev_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -11994,9 +14105,9 @@ unsafe fn test_lasx_xvmaddwev_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12031,9 +14142,9 @@ unsafe fn test_lasx_xvmaddwev_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12062,9 +14173,9 @@ unsafe fn test_lasx_xvmaddwev_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12099,9 +14210,9 @@ unsafe fn test_lasx_xvmaddwod_q_du_d() { assert_eq!( r, transmute(lasx_xvmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12138,9 +14249,9 @@ unsafe fn test_lasx_xvmaddwod_d_wu_w() { assert_eq!( r, transmute(lasx_xvmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12169,9 +14280,9 @@ unsafe fn test_lasx_xvmaddwod_w_hu_h() { assert_eq!( r, transmute(lasx_xvmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12200,9 +14311,9 @@ unsafe fn test_lasx_xvmaddwod_h_bu_b() { assert_eq!( r, transmute(lasx_xvmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -12224,7 +14335,13 @@ unsafe fn test_lasx_xvrotr_b() { 5842271601646106402, ); - assert_eq!(r, transmute(lasx_xvrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12244,7 +14361,13 @@ unsafe fn test_lasx_xvrotr_h() { 8109266518466894464, ); - assert_eq!(r, transmute(lasx_xvrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12264,7 +14387,13 @@ unsafe fn test_lasx_xvrotr_w() { 8567937817891640092, ); - assert_eq!(r, transmute(lasx_xvrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12288,7 +14417,13 @@ unsafe fn test_lasx_xvrotr_d() { 4254025119287920211, ); - assert_eq!(r, transmute(lasx_xvrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12312,7 +14447,13 @@ unsafe fn test_lasx_xvadd_q() { 1706530784161666452, ); - assert_eq!(r, transmute(lasx_xvadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvadd_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12336,7 +14477,13 @@ unsafe fn test_lasx_xvsub_q() { 1242748497994781383, ); - assert_eq!(r, transmute(lasx_xvsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvsub_q( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -12357,7 +14504,10 @@ unsafe fn test_lasx_xvaddwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12379,7 +14529,10 @@ unsafe fn test_lasx_xvaddwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvaddwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12406,7 +14559,10 @@ unsafe fn test_lasx_xvmulwev_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwev_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12433,7 +14589,10 @@ unsafe fn test_lasx_xvmulwod_q_du_d() { assert_eq!( r, - transmute(lasx_xvmulwod_q_du_d(transmute(a), transmute(b))) + transmute(lasx_xvmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12445,7 +14604,7 @@ unsafe fn test_lasx_xvmskgez_b() { ); let r = i64x4::new(13289, 0, 4927, 0); - assert_eq!(r, transmute(lasx_xvmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12456,7 +14615,7 @@ unsafe fn test_lasx_xvmsknz_b() { ); let r = i64x4::new(65535, 0, 65535, 0); - assert_eq!(r, transmute(lasx_xvmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12472,7 +14631,7 @@ unsafe fn test_lasx_xvexth_h_b() { -1689051729887256, ); - assert_eq!(r, transmute(lasx_xvexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12488,7 +14647,7 @@ unsafe fn test_lasx_xvexth_w_h() { -117171002791439, ); - assert_eq!(r, transmute(lasx_xvexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12505,7 +14664,7 @@ unsafe fn test_lasx_xvexth_d_w() { ); let r = i64x4::new(78514216, -1063299454, -1487536177, 1875317589); - assert_eq!(r, transmute(lasx_xvexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12518,7 +14677,7 @@ unsafe fn test_lasx_xvexth_q_d() { ); let r = i64x4::new(5196480214883180720, 0, 7776492634988202392, 0); - assert_eq!(r, transmute(lasx_xvexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12534,7 +14693,7 @@ unsafe fn test_lasx_xvexth_hu_bu() { 11259067788754993, ); - assert_eq!(r, transmute(lasx_xvexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12550,7 +14709,7 @@ unsafe fn test_lasx_xvexth_wu_hu() { 211376815493177, ); - assert_eq!(r, transmute(lasx_xvexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12561,7 +14720,7 @@ unsafe fn test_lasx_xvexth_du_wu() { ); let r = i64x4::new(3486710391, 717721410, 1954296323, 1406265475); - assert_eq!(r, transmute(lasx_xvexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12574,7 +14733,7 @@ unsafe fn test_lasx_xvexth_qu_du() { ); let r = i64x4::new(6305760528044738869, 0, 3857202168052068182, 0); - assert_eq!(r, transmute(lasx_xvexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lasx_xvexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12590,7 +14749,7 @@ unsafe fn test_lasx_xvrotri_b() { -3500418816657076903, ); - assert_eq!(r, transmute(lasx_xvrotri_b::<4>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_b::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12606,7 +14765,7 @@ unsafe fn test_lasx_xvrotri_h() { 4779464405959485451, ); - assert_eq!(r, transmute(lasx_xvrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12628,7 +14787,7 @@ unsafe fn test_lasx_xvrotri_w() { -1679179889808014898, ); - assert_eq!(r, transmute(lasx_xvrotri_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12646,7 +14805,7 @@ unsafe fn test_lasx_xvrotri_d() { -7958311692822812825, ); - assert_eq!(r, transmute(lasx_xvrotri_d::<16>(transmute(a)))); + assert_eq!(r, transmute(lasx_xvrotri_d::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12659,7 +14818,7 @@ unsafe fn test_lasx_xvextl_q_d() { ); let r = i64x4::new(-4167783494125842132, -1, 7476993593286219399, 0); - assert_eq!(r, transmute(lasx_xvextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xvextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -12681,7 +14840,10 @@ unsafe fn test_lasx_xvsrlni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12704,7 +14866,10 @@ unsafe fn test_lasx_xvsrlni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlni_h_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_h_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12739,7 +14904,10 @@ unsafe fn test_lasx_xvsrlni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlni_w_d::<26>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_w_d::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12761,7 +14929,10 @@ unsafe fn test_lasx_xvsrlni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrlni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12784,7 +14955,10 @@ unsafe fn test_lasx_xvsrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvsrlrni_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12807,7 +14981,10 @@ unsafe fn test_lasx_xvsrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvsrlrni_h_w::<5>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_h_w::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12842,7 +15019,10 @@ unsafe fn test_lasx_xvsrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvsrlrni_w_d::<43>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_w_d::<43>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12864,7 +15044,10 @@ unsafe fn test_lasx_xvsrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvsrlrni_d_q::<126>(transmute(a), transmute(b))) + transmute(lasx_xvsrlrni_d_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12887,7 +15070,10 @@ unsafe fn test_lasx_xvssrlni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12905,7 +15091,10 @@ unsafe fn test_lasx_xvssrlni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlni_h_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_h_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12940,7 +15129,10 @@ unsafe fn test_lasx_xvssrlni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlni_w_d::<14>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_w_d::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12967,7 +15159,10 @@ unsafe fn test_lasx_xvssrlni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlni_d_q::<35>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_d_q::<35>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -12990,7 +15185,10 @@ unsafe fn test_lasx_xvssrlni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlni_bu_h::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_bu_h::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13008,7 +15206,10 @@ unsafe fn test_lasx_xvssrlni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlni_hu_w::<31>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_hu_w::<31>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13032,7 +15233,10 @@ unsafe fn test_lasx_xvssrlni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlni_wu_d::<24>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_wu_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13054,7 +15258,10 @@ unsafe fn test_lasx_xvssrlni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlni_du_q::<109>(transmute(a), transmute(b))) + transmute(lasx_xvssrlni_du_q::<109>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13077,7 +15284,10 @@ unsafe fn test_lasx_xvssrlrni_b_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_b_h::<7>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_b_h::<7>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13100,7 +15310,10 @@ unsafe fn test_lasx_xvssrlrni_h_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_h_w::<11>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_h_w::<11>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13135,7 +15348,10 @@ unsafe fn test_lasx_xvssrlrni_w_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_w_d::<27>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_w_d::<27>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13157,7 +15373,10 @@ unsafe fn test_lasx_xvssrlrni_d_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_d_q::<94>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_d_q::<94>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13175,7 +15394,10 @@ unsafe fn test_lasx_xvssrlrni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrlrni_bu_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_bu_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13198,7 +15420,10 @@ unsafe fn test_lasx_xvssrlrni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrlrni_hu_w::<16>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_hu_w::<16>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13227,7 +15452,10 @@ unsafe fn test_lasx_xvssrlrni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrlrni_wu_d::<50>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_wu_d::<50>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13249,7 +15477,10 @@ unsafe fn test_lasx_xvssrlrni_du_q() { assert_eq!( r, - transmute(lasx_xvssrlrni_du_q::<53>(transmute(a), transmute(b))) + transmute(lasx_xvssrlrni_du_q::<53>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13272,7 +15503,10 @@ unsafe fn test_lasx_xvsrani_b_h() { assert_eq!( r, - transmute(lasx_xvsrani_b_h::<8>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_b_h::<8>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13295,7 +15529,10 @@ unsafe fn test_lasx_xvsrani_h_w() { assert_eq!( r, - transmute(lasx_xvsrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13330,7 +15567,10 @@ unsafe fn test_lasx_xvsrani_w_d() { assert_eq!( r, - transmute(lasx_xvsrani_w_d::<28>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_w_d::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13357,7 +15597,10 @@ unsafe fn test_lasx_xvsrani_d_q() { assert_eq!( r, - transmute(lasx_xvsrani_d_q::<66>(transmute(a), transmute(b))) + transmute(lasx_xvsrani_d_q::<66>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13380,7 +15623,10 @@ unsafe fn test_lasx_xvsrarni_b_h() { assert_eq!( r, - transmute(lasx_xvsrarni_b_h::<4>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_b_h::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13403,7 +15649,10 @@ unsafe fn test_lasx_xvsrarni_h_w() { assert_eq!( r, - transmute(lasx_xvsrarni_h_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_h_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13427,7 +15676,10 @@ unsafe fn test_lasx_xvsrarni_w_d() { assert_eq!( r, - transmute(lasx_xvsrarni_w_d::<63>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_w_d::<63>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13449,7 +15701,10 @@ unsafe fn test_lasx_xvsrarni_d_q() { assert_eq!( r, - transmute(lasx_xvsrarni_d_q::<102>(transmute(a), transmute(b))) + transmute(lasx_xvsrarni_d_q::<102>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13472,7 +15727,10 @@ unsafe fn test_lasx_xvssrani_b_h() { assert_eq!( r, - transmute(lasx_xvssrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13495,7 +15753,10 @@ unsafe fn test_lasx_xvssrani_h_w() { assert_eq!( r, - transmute(lasx_xvssrani_h_w::<0>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_h_w::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13530,7 +15791,10 @@ unsafe fn test_lasx_xvssrani_w_d() { assert_eq!( r, - transmute(lasx_xvssrani_w_d::<45>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_w_d::<45>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13557,7 +15821,10 @@ unsafe fn test_lasx_xvssrani_d_q() { assert_eq!( r, - transmute(lasx_xvssrani_d_q::<73>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_d_q::<73>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13575,7 +15842,10 @@ unsafe fn test_lasx_xvssrani_bu_h() { assert_eq!( r, - transmute(lasx_xvssrani_bu_h::<12>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_bu_h::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13593,7 +15863,10 @@ unsafe fn test_lasx_xvssrani_hu_w() { assert_eq!( r, - transmute(lasx_xvssrani_hu_w::<9>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13617,7 +15890,10 @@ unsafe fn test_lasx_xvssrani_wu_d() { assert_eq!( r, - transmute(lasx_xvssrani_wu_d::<42>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_wu_d::<42>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13639,7 +15915,10 @@ unsafe fn test_lasx_xvssrani_du_q() { assert_eq!( r, - transmute(lasx_xvssrani_du_q::<115>(transmute(a), transmute(b))) + transmute(lasx_xvssrani_du_q::<115>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13662,7 +15941,10 @@ unsafe fn test_lasx_xvssrarni_b_h() { assert_eq!( r, - transmute(lasx_xvssrarni_b_h::<6>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13685,7 +15967,10 @@ unsafe fn test_lasx_xvssrarni_h_w() { assert_eq!( r, - transmute(lasx_xvssrarni_h_w::<25>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_h_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13715,7 +16000,10 @@ unsafe fn test_lasx_xvssrarni_w_d() { assert_eq!( r, - transmute(lasx_xvssrarni_w_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_w_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13737,7 +16025,10 @@ unsafe fn test_lasx_xvssrarni_d_q() { assert_eq!( r, - transmute(lasx_xvssrarni_d_q::<123>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_d_q::<123>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13760,7 +16051,10 @@ unsafe fn test_lasx_xvssrarni_bu_h() { assert_eq!( r, - transmute(lasx_xvssrarni_bu_h::<10>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_bu_h::<10>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13778,7 +16072,10 @@ unsafe fn test_lasx_xvssrarni_hu_w() { assert_eq!( r, - transmute(lasx_xvssrarni_hu_w::<30>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_hu_w::<30>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13802,7 +16099,10 @@ unsafe fn test_lasx_xvssrarni_wu_d() { assert_eq!( r, - transmute(lasx_xvssrarni_wu_d::<61>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_wu_d::<61>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13824,7 +16124,10 @@ unsafe fn test_lasx_xvssrarni_du_q() { assert_eq!( r, - transmute(lasx_xvssrarni_du_q::<15>(transmute(a), transmute(b))) + transmute(lasx_xvssrarni_du_q::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -13836,7 +16139,7 @@ unsafe fn test_lasx_xbnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13849,7 +16152,7 @@ unsafe fn test_lasx_xbnz_d() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13860,7 +16163,7 @@ unsafe fn test_lasx_xbnz_h() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13871,7 +16174,7 @@ unsafe fn test_lasx_xbnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13882,7 +16185,7 @@ unsafe fn test_lasx_xbnz_w() { ); let r: i32 = 1; - assert_eq!(r, transmute(lasx_xbnz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13893,7 +16196,7 @@ unsafe fn test_lasx_xbz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_b(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_b(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13906,7 +16209,7 @@ unsafe fn test_lasx_xbz_d() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_d(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13917,7 +16220,7 @@ unsafe fn test_lasx_xbz_h() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_h(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_h(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13928,7 +16231,7 @@ unsafe fn test_lasx_xbz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_v(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_v(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13939,7 +16242,7 @@ unsafe fn test_lasx_xbz_w() { ); let r: i32 = 0; - assert_eq!(r, transmute(lasx_xbz_w(transmute(a)))); + assert_eq!(r, transmute(lasx_xbz_w(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -13958,7 +16261,13 @@ unsafe fn test_lasx_xvfcmp_caf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13973,7 +16282,13 @@ unsafe fn test_lasx_xvfcmp_caf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -13992,7 +16307,13 @@ unsafe fn test_lasx_xvfcmp_ceq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14007,7 +16328,13 @@ unsafe fn test_lasx_xvfcmp_ceq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14026,7 +16353,13 @@ unsafe fn test_lasx_xvfcmp_cle_d() { ); let r = i64x4::new(-1, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14041,7 +16374,13 @@ unsafe fn test_lasx_xvfcmp_cle_s() { ); let r = i64x4::new(0, -1, -1, -4294967296); - assert_eq!(r, transmute(lasx_xvfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14060,7 +16399,13 @@ unsafe fn test_lasx_xvfcmp_clt_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14075,7 +16420,13 @@ unsafe fn test_lasx_xvfcmp_clt_s() { ); let r = i64x4::new(-1, 4294967295, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14094,7 +16445,13 @@ unsafe fn test_lasx_xvfcmp_cne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14109,7 +16466,13 @@ unsafe fn test_lasx_xvfcmp_cne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14128,7 +16491,13 @@ unsafe fn test_lasx_xvfcmp_cor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14143,7 +16512,13 @@ unsafe fn test_lasx_xvfcmp_cor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14162,7 +16537,13 @@ unsafe fn test_lasx_xvfcmp_cueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14177,7 +16558,13 @@ unsafe fn test_lasx_xvfcmp_cueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14196,7 +16583,13 @@ unsafe fn test_lasx_xvfcmp_cule_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14211,7 +16604,13 @@ unsafe fn test_lasx_xvfcmp_cule_s() { ); let r = i64x4::new(-4294967296, 4294967295, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14230,7 +16629,13 @@ unsafe fn test_lasx_xvfcmp_cult_d() { ); let r = i64x4::new(0, -1, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14245,7 +16650,13 @@ unsafe fn test_lasx_xvfcmp_cult_s() { ); let r = i64x4::new(-1, 0, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14264,7 +16675,13 @@ unsafe fn test_lasx_xvfcmp_cun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14283,7 +16700,13 @@ unsafe fn test_lasx_xvfcmp_cune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14298,7 +16721,13 @@ unsafe fn test_lasx_xvfcmp_cune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14313,7 +16742,13 @@ unsafe fn test_lasx_xvfcmp_cun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14332,7 +16767,13 @@ unsafe fn test_lasx_xvfcmp_saf_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14347,7 +16788,13 @@ unsafe fn test_lasx_xvfcmp_saf_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14366,7 +16813,13 @@ unsafe fn test_lasx_xvfcmp_seq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14381,7 +16834,13 @@ unsafe fn test_lasx_xvfcmp_seq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14400,7 +16859,13 @@ unsafe fn test_lasx_xvfcmp_sle_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14415,7 +16880,13 @@ unsafe fn test_lasx_xvfcmp_sle_s() { ); let r = i64x4::new(0, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14434,7 +16905,13 @@ unsafe fn test_lasx_xvfcmp_slt_d() { ); let r = i64x4::new(0, -1, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14449,7 +16926,13 @@ unsafe fn test_lasx_xvfcmp_slt_s() { ); let r = i64x4::new(0, -4294967296, 4294967295, -1); - assert_eq!(r, transmute(lasx_xvfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14468,7 +16951,13 @@ unsafe fn test_lasx_xvfcmp_sne_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14483,7 +16972,13 @@ unsafe fn test_lasx_xvfcmp_sne_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14502,7 +16997,13 @@ unsafe fn test_lasx_xvfcmp_sor_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14517,7 +17018,13 @@ unsafe fn test_lasx_xvfcmp_sor_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14536,7 +17043,13 @@ unsafe fn test_lasx_xvfcmp_sueq_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14551,7 +17064,13 @@ unsafe fn test_lasx_xvfcmp_sueq_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14570,7 +17089,13 @@ unsafe fn test_lasx_xvfcmp_sule_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14585,7 +17110,13 @@ unsafe fn test_lasx_xvfcmp_sule_s() { ); let r = i64x4::new(0, 4294967295, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14604,7 +17135,13 @@ unsafe fn test_lasx_xvfcmp_sult_d() { ); let r = i64x4::new(0, -1, 0, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14619,7 +17156,13 @@ unsafe fn test_lasx_xvfcmp_sult_s() { ); let r = i64x4::new(-1, 4294967295, -1, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14638,7 +17181,13 @@ unsafe fn test_lasx_xvfcmp_sun_d() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14657,7 +17206,13 @@ unsafe fn test_lasx_xvfcmp_sune_d() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14672,7 +17227,13 @@ unsafe fn test_lasx_xvfcmp_sune_s() { ); let r = i64x4::new(-1, -1, -1, -1); - assert_eq!(r, transmute(lasx_xvfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14687,7 +17248,13 @@ unsafe fn test_lasx_xvfcmp_sun_s() { ); let r = i64x4::new(0, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_xvfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14700,7 +17267,10 @@ unsafe fn test_lasx_xvpickve_d_f() { ); let r = i64x4::new(4605596490350167974, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_d_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_d_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14711,7 +17281,10 @@ unsafe fn test_lasx_xvpickve_w_f() { ); let r = i64x4::new(1040565756, 0, 0, 0); - assert_eq!(r, transmute(lasx_xvpickve_w_f::<1>(transmute(a)))); + assert_eq!( + r, + transmute(lasx_xvpickve_w_f::<1>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lasx")] @@ -14764,7 +17337,7 @@ unsafe fn test_lasx_cast_128_s() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128_s(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14780,7 +17353,7 @@ unsafe fn test_lasx_cast_128_d() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128_d(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14796,7 +17369,7 @@ unsafe fn test_lasx_cast_128() { assert_eq!( r.as_array()[0..2], - transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2] + transmute::<_, i64x4>(lasx_cast_128(black_box(transmute(a)))).as_array()[0..2] ); } @@ -14811,7 +17384,13 @@ unsafe fn test_lasx_concat_128_s() { 4410275898954698048, ); - assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14825,7 +17404,13 @@ unsafe fn test_lasx_concat_128_d() { 4600308396523102002, ); - assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14839,7 +17424,13 @@ unsafe fn test_lasx_concat_128() { 7751541408133090748, ); - assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_concat_128( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -14850,7 +17441,7 @@ unsafe fn test_lasx_extract_128_lo_s() { ); let r = i64x2::new(4524431379435545192, 4532741359493293580); - assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14861,7 +17452,7 @@ unsafe fn test_lasx_extract_128_hi_s() { ); let r = i64x2::new(4572785117706267614, 4549394373627784333); - assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi_s(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14874,7 +17465,7 @@ unsafe fn test_lasx_extract_128_lo_d() { ); let r = i64x2::new(4606487981487128637, 4592443779247846248); - assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14887,7 +17478,7 @@ unsafe fn test_lasx_extract_128_hi_d() { ); let r = i64x2::new(4603881047625519227, 4604218419306666352); - assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi_d(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14900,7 +17491,7 @@ unsafe fn test_lasx_extract_128_lo() { ); let r = i64x2::new(1690990426210778543, -1056924033489771427); - assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_lo(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14913,7 +17504,7 @@ unsafe fn test_lasx_extract_128_hi() { ); let r = i64x2::new(-1903780563362068813, -7449796170151383489); - assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a)))); + assert_eq!(r, transmute(lasx_extract_128_hi(black_box(transmute(a))))); } #[simd_test(enable = "lasx")] @@ -14932,7 +17523,10 @@ unsafe fn test_lasx_insert_128_lo_s() { assert_eq!( r, - transmute(lasx_insert_128_lo_s(transmute(a), transmute(b))) + transmute(lasx_insert_128_lo_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14952,7 +17546,10 @@ unsafe fn test_lasx_insert_128_hi_s() { assert_eq!( r, - transmute(lasx_insert_128_hi_s(transmute(a), transmute(b))) + transmute(lasx_insert_128_hi_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14974,7 +17571,10 @@ unsafe fn test_lasx_insert_128_lo_d() { assert_eq!( r, - transmute(lasx_insert_128_lo_d(transmute(a), transmute(b))) + transmute(lasx_insert_128_lo_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -14996,7 +17596,10 @@ unsafe fn test_lasx_insert_128_hi_d() { assert_eq!( r, - transmute(lasx_insert_128_hi_d(transmute(a), transmute(b))) + transmute(lasx_insert_128_hi_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -15016,7 +17619,13 @@ unsafe fn test_lasx_insert_128_lo() { -4396186135186039276, ); - assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_insert_128_lo( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lasx")] @@ -15035,5 +17644,11 @@ unsafe fn test_lasx_insert_128_hi() { -7502655081590988207, ); - assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lasx_insert_128_hi( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs index 25efaadb4288..faa8859eba77 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs @@ -1453,35 +1453,35 @@ fn __lsx_vrepli_w(a: i32) -> __v4i32; } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsll_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsll_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsll_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsll_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsll_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsll_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsll_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsll_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1490,7 +1490,7 @@ pub fn lsx_vslli_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vslli_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1499,7 +1499,7 @@ pub fn lsx_vslli_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vslli_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1508,7 +1508,7 @@ pub fn lsx_vslli_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vslli_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1517,35 +1517,35 @@ pub fn lsx_vslli_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vslli_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsra_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsra_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsra_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsra_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsra_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsra_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsra_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsra_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1554,7 +1554,7 @@ pub fn lsx_vsrai_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrai_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1563,7 +1563,7 @@ pub fn lsx_vsrai_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrai_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1572,7 +1572,7 @@ pub fn lsx_vsrai_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrai_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1581,35 +1581,35 @@ pub fn lsx_vsrai_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrai_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrar_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrar_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrar_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrar_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrar_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrar_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrar_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrar_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1618,7 +1618,7 @@ pub fn lsx_vsrari_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrari_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1627,7 +1627,7 @@ pub fn lsx_vsrari_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrari_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1636,7 +1636,7 @@ pub fn lsx_vsrari_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrari_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1645,35 +1645,35 @@ pub fn lsx_vsrari_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrari_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrl_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrl_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrl_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrl_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrl_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrl_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrl_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrl_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1682,7 +1682,7 @@ pub fn lsx_vsrli_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrli_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1691,7 +1691,7 @@ pub fn lsx_vsrli_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrli_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1700,7 +1700,7 @@ pub fn lsx_vsrli_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrli_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1709,35 +1709,35 @@ pub fn lsx_vsrli_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrli_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlr_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlr_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlr_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlr_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1746,7 +1746,7 @@ pub fn lsx_vsrlri_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrlri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1755,7 +1755,7 @@ pub fn lsx_vsrlri_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrlri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1764,7 +1764,7 @@ pub fn lsx_vsrlri_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrlri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1773,35 +1773,35 @@ pub fn lsx_vsrlri_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vsrlri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitclr_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitclr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitclr_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitclr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitclr_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitclr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitclr_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitclr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1810,7 +1810,7 @@ pub fn lsx_vbitclri_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitclri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1819,7 +1819,7 @@ pub fn lsx_vbitclri_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitclri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1828,7 +1828,7 @@ pub fn lsx_vbitclri_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitclri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1837,35 +1837,35 @@ pub fn lsx_vbitclri_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitclri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitset_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitset_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitset_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitset_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitset_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitset_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitset_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitset_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1874,7 +1874,7 @@ pub fn lsx_vbitseti_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitseti_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1883,7 +1883,7 @@ pub fn lsx_vbitseti_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitseti_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1892,7 +1892,7 @@ pub fn lsx_vbitseti_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitseti_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1901,35 +1901,35 @@ pub fn lsx_vbitseti_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitseti_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitrev_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitrev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitrev_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitrev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitrev_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitrev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitrev_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitrev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1938,7 +1938,7 @@ pub fn lsx_vbitrevi_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitrevi_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1947,7 +1947,7 @@ pub fn lsx_vbitrevi_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitrevi_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1956,7 +1956,7 @@ pub fn lsx_vbitrevi_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitrevi_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -1965,35 +1965,35 @@ pub fn lsx_vbitrevi_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vbitrevi_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadd_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadd_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadd_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadd_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2002,7 +2002,7 @@ pub fn lsx_vaddi_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vaddi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2011,7 +2011,7 @@ pub fn lsx_vaddi_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vaddi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2020,7 +2020,7 @@ pub fn lsx_vaddi_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vaddi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2029,35 +2029,35 @@ pub fn lsx_vaddi_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vaddi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsub_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsub_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsub_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsub_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsub_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsub_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsub_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2066,7 +2066,7 @@ pub fn lsx_vsubi_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsubi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2075,7 +2075,7 @@ pub fn lsx_vsubi_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsubi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2084,7 +2084,7 @@ pub fn lsx_vsubi_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsubi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2093,35 +2093,35 @@ pub fn lsx_vsubi_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vsubi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2130,7 +2130,7 @@ pub fn lsx_vmaxi_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2139,7 +2139,7 @@ pub fn lsx_vmaxi_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2148,7 +2148,7 @@ pub fn lsx_vmaxi_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2157,35 +2157,35 @@ pub fn lsx_vmaxi_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmax_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmax_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2194,7 +2194,7 @@ pub fn lsx_vmaxi_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2203,7 +2203,7 @@ pub fn lsx_vmaxi_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2212,7 +2212,7 @@ pub fn lsx_vmaxi_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2221,35 +2221,35 @@ pub fn lsx_vmaxi_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vmaxi_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2258,7 +2258,7 @@ pub fn lsx_vmini_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2267,7 +2267,7 @@ pub fn lsx_vmini_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2276,7 +2276,7 @@ pub fn lsx_vmini_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2285,35 +2285,35 @@ pub fn lsx_vmini_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmin_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmin_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2322,7 +2322,7 @@ pub fn lsx_vmini_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2331,7 +2331,7 @@ pub fn lsx_vmini_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2340,7 +2340,7 @@ pub fn lsx_vmini_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2349,35 +2349,35 @@ pub fn lsx_vmini_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vmini_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vseq_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vseq_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vseq_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vseq_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vseq_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vseq_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vseq_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vseq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2386,7 +2386,7 @@ pub fn lsx_vseqi_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vseqi_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2395,7 +2395,7 @@ pub fn lsx_vseqi_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vseqi_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2404,7 +2404,7 @@ pub fn lsx_vseqi_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vseqi_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2413,7 +2413,7 @@ pub fn lsx_vseqi_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vseqi_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2422,35 +2422,35 @@ pub fn lsx_vslti_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2459,7 +2459,7 @@ pub fn lsx_vslti_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2468,7 +2468,7 @@ pub fn lsx_vslti_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2477,35 +2477,35 @@ pub fn lsx_vslti_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vslt_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vslt_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2514,7 +2514,7 @@ pub fn lsx_vslti_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2523,7 +2523,7 @@ pub fn lsx_vslti_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2532,7 +2532,7 @@ pub fn lsx_vslti_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2541,35 +2541,35 @@ pub fn lsx_vslti_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vslti_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2578,7 +2578,7 @@ pub fn lsx_vslei_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_b(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2587,7 +2587,7 @@ pub fn lsx_vslei_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_h(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2596,7 +2596,7 @@ pub fn lsx_vslei_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_w(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2605,35 +2605,35 @@ pub fn lsx_vslei_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_d(transmute(a), IMM_S5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsle_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsle_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2642,7 +2642,7 @@ pub fn lsx_vslei_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_bu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2651,7 +2651,7 @@ pub fn lsx_vslei_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_hu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2660,7 +2660,7 @@ pub fn lsx_vslei_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2669,7 +2669,7 @@ pub fn lsx_vslei_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vslei_du(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2678,7 +2678,7 @@ pub fn lsx_vsat_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2687,7 +2687,7 @@ pub fn lsx_vsat_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2696,7 +2696,7 @@ pub fn lsx_vsat_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2705,7 +2705,7 @@ pub fn lsx_vsat_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2714,7 +2714,7 @@ pub fn lsx_vsat_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_bu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2723,7 +2723,7 @@ pub fn lsx_vsat_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_hu(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2732,7 +2732,7 @@ pub fn lsx_vsat_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -2741,623 +2741,623 @@ pub fn lsx_vsat_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vsat_du(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadda_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadda_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadda_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadda_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadda_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadda_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadda_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadda_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsadd_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsadd_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavg_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavg_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vavgr_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vavgr_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssub_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssub_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vabsd_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vabsd_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmul_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmul_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmul_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmul_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmul_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmul_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmul_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmul_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmadd_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmadd_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmadd_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmadd_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmsub_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmsub_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmsub_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmsub_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vdiv_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vdiv_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_hu_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_hu_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_wu_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_wu_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_du_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_du_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_hu_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_hu_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_wu_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_wu_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_du_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_du_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmod_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmod_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplve_b(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vreplve_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplve_h(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vreplve_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplve_w(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vreplve_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplve_d(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vreplve_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3366,7 +3366,7 @@ pub fn lsx_vreplvei_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vreplvei_b(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3375,7 +3375,7 @@ pub fn lsx_vreplvei_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vreplvei_h(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3384,7 +3384,7 @@ pub fn lsx_vreplvei_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vreplvei_w(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3393,203 +3393,203 @@ pub fn lsx_vreplvei_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vreplvei_d(transmute(a), IMM1)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickev_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickev_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickev_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickev_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickod_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickod_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickod_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpickod_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpickod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvh_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvh_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvh_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvh_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvh_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvh_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvh_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvh_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvl_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvl_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvl_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvl_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvl_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvl_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vilvl_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vilvl_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackev_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackev_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackev_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackev_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackev_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackev_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackev_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackev_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackod_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackod_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackod_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackod_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackod_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackod_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpackod_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpackod_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vshuf_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vshuf_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vshuf_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vand_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vand_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3598,14 +3598,14 @@ pub fn lsx_vandi_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vandi_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vor_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3614,14 +3614,14 @@ pub fn lsx_vori_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vnor_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vnor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3630,14 +3630,14 @@ pub fn lsx_vnori_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vnori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vxor_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vxor_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3646,14 +3646,14 @@ pub fn lsx_vxori_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vxori_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vbitsel_v(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3662,7 +3662,7 @@ pub fn lsx_vbitseli_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vbitseli_b(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3671,7 +3671,7 @@ pub fn lsx_vshuf4i_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vshuf4i_b(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3680,7 +3680,7 @@ pub fn lsx_vshuf4i_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vshuf4i_h(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3689,119 +3689,119 @@ pub fn lsx_vshuf4i_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vshuf4i_w(transmute(a), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplgr2vr_b(a: i32) -> m128i { unsafe { transmute(__lsx_vreplgr2vr_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplgr2vr_h(a: i32) -> m128i { unsafe { transmute(__lsx_vreplgr2vr_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplgr2vr_w(a: i32) -> m128i { unsafe { transmute(__lsx_vreplgr2vr_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vreplgr2vr_d(a: i64) -> m128i { unsafe { transmute(__lsx_vreplgr2vr_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpcnt_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vpcnt_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpcnt_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vpcnt_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpcnt_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vpcnt_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vpcnt_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vpcnt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclo_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vclo_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclo_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vclo_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclo_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vclo_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclo_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vclo_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclz_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vclz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclz_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vclz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclz_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vclz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vclz_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vclz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3810,7 +3810,7 @@ pub fn lsx_vpickve2gr_b(a: m128i) -> i32 { unsafe { transmute(__lsx_vpickve2gr_b(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3819,7 +3819,7 @@ pub fn lsx_vpickve2gr_h(a: m128i) -> i32 { unsafe { transmute(__lsx_vpickve2gr_h(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3828,7 +3828,7 @@ pub fn lsx_vpickve2gr_w(a: m128i) -> i32 { unsafe { transmute(__lsx_vpickve2gr_w(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3837,7 +3837,7 @@ pub fn lsx_vpickve2gr_d(a: m128i) -> i64 { unsafe { transmute(__lsx_vpickve2gr_d(transmute(a), IMM1)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3846,7 +3846,7 @@ pub fn lsx_vpickve2gr_bu(a: m128i) -> u32 { unsafe { transmute(__lsx_vpickve2gr_bu(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3855,7 +3855,7 @@ pub fn lsx_vpickve2gr_hu(a: m128i) -> u32 { unsafe { transmute(__lsx_vpickve2gr_hu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3864,7 +3864,7 @@ pub fn lsx_vpickve2gr_wu(a: m128i) -> u32 { unsafe { transmute(__lsx_vpickve2gr_wu(transmute(a), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3873,7 +3873,7 @@ pub fn lsx_vpickve2gr_du(a: m128i) -> u64 { unsafe { transmute(__lsx_vpickve2gr_du(transmute(a), IMM1)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3882,7 +3882,7 @@ pub fn lsx_vinsgr2vr_b(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vinsgr2vr_b(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3891,7 +3891,7 @@ pub fn lsx_vinsgr2vr_h(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vinsgr2vr_h(transmute(a), transmute(b), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3900,7 +3900,7 @@ pub fn lsx_vinsgr2vr_w(a: m128i, b: i32) -> m128i { unsafe { transmute(__lsx_vinsgr2vr_w(transmute(a), transmute(b), IMM2)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -3909,448 +3909,448 @@ pub fn lsx_vinsgr2vr_d(a: m128i, b: i64) -> m128i { unsafe { transmute(__lsx_vinsgr2vr_d(transmute(a), transmute(b), IMM1)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfadd_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfadd_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfadd_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfadd_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfsub_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfsub_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfsub_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfsub_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmul_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfmul_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmul_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfmul_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfdiv_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfdiv_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfdiv_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfdiv_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvt_h_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcvt_h_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvt_s_d(a: m128d, b: m128d) -> m128 { unsafe { transmute(__lsx_vfcvt_s_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmin_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfmin_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmin_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfmin_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmina_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfmina_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmina_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfmina_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmax_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfmax_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmax_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfmax_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmaxa_s(a: m128, b: m128) -> m128 { unsafe { transmute(__lsx_vfmaxa_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmaxa_d(a: m128d, b: m128d) -> m128d { unsafe { transmute(__lsx_vfmaxa_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfclass_s(a: m128) -> m128i { unsafe { transmute(__lsx_vfclass_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfclass_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vfclass_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfsqrt_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfsqrt_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfsqrt_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfsqrt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrecip_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrecip_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrecip_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrecip_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrecipe_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrecipe_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrecipe_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrecipe_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrsqrte_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrsqrte_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx,frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrsqrte_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrsqrte_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrint_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrint_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrint_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrint_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrsqrt_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrsqrt_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrsqrt_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrsqrt_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vflogb_s(a: m128) -> m128 { unsafe { transmute(__lsx_vflogb_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vflogb_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vflogb_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvth_s_h(a: m128i) -> m128 { unsafe { transmute(__lsx_vfcvth_s_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvth_d_s(a: m128) -> m128d { unsafe { transmute(__lsx_vfcvth_d_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvtl_s_h(a: m128i) -> m128 { unsafe { transmute(__lsx_vfcvtl_s_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcvtl_d_s(a: m128) -> m128d { unsafe { transmute(__lsx_vfcvtl_d_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftint_w_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftint_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftint_l_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftint_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftint_wu_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftint_wu_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftint_lu_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftint_lu_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrz_w_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrz_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrz_l_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftintrz_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrz_wu_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrz_wu_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrz_lu_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftintrz_lu_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffint_s_w(a: m128i) -> m128 { unsafe { transmute(__lsx_vffint_s_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffint_d_l(a: m128i) -> m128d { unsafe { transmute(__lsx_vffint_d_l(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffint_s_wu(a: m128i) -> m128 { unsafe { transmute(__lsx_vffint_s_wu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffint_d_lu(a: m128i) -> m128d { unsafe { transmute(__lsx_vffint_d_lu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vandn_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vandn_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vneg_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vneg_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vneg_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vneg_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vneg_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vneg_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vneg_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vneg_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmuh_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmuh_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4359,7 +4359,7 @@ pub fn lsx_vsllwil_h_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_h_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4368,7 +4368,7 @@ pub fn lsx_vsllwil_w_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_w_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4377,7 +4377,7 @@ pub fn lsx_vsllwil_d_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_d_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4386,7 +4386,7 @@ pub fn lsx_vsllwil_hu_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_hu_bu(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4395,7 +4395,7 @@ pub fn lsx_vsllwil_wu_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_wu_hu(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4404,217 +4404,217 @@ pub fn lsx_vsllwil_du_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vsllwil_du_wu(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsran_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsran_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsran_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsran_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsran_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsran_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssran_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssran_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrarn_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrarn_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrarn_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrarn_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarn_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrln_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrln_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrln_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrln_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrln_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrln_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlrn_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlrn_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsrlrn_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_bu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_hu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_wu_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4623,7 +4623,7 @@ pub fn lsx_vfrstpi_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vfrstpi_b(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4632,21 +4632,21 @@ pub fn lsx_vfrstpi_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vfrstpi_h(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrstp_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrstp_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4655,7 +4655,7 @@ pub fn lsx_vshuf4i_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vshuf4i_d(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4664,7 +4664,7 @@ pub fn lsx_vbsrl_v(a: m128i) -> m128i { unsafe { transmute(__lsx_vbsrl_v(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4673,7 +4673,7 @@ pub fn lsx_vbsll_v(a: m128i) -> m128i { unsafe { transmute(__lsx_vbsll_v(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4682,7 +4682,7 @@ pub fn lsx_vextrins_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vextrins_b(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4691,7 +4691,7 @@ pub fn lsx_vextrins_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vextrins_h(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4700,7 +4700,7 @@ pub fn lsx_vextrins_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vextrins_w(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -4709,1069 +4709,1069 @@ pub fn lsx_vextrins_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vextrins_d(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmskltz_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vmskltz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmskltz_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vmskltz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmskltz_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vmskltz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmskltz_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vmskltz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsigncov_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsigncov_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsigncov_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsigncov_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsigncov_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmadd_s(a: m128, b: m128, c: m128) -> m128 { unsafe { transmute(__lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { unsafe { transmute(__lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmsub_s(a: m128, b: m128, c: m128) -> m128 { unsafe { transmute(__lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { unsafe { transmute(__lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfnmadd_s(a: m128, b: m128, c: m128) -> m128 { unsafe { transmute(__lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfnmadd_d(a: m128d, b: m128d, c: m128d) -> m128d { unsafe { transmute(__lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfnmsub_s(a: m128, b: m128, c: m128) -> m128 { unsafe { transmute(__lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfnmsub_d(a: m128d, b: m128d, c: m128d) -> m128d { unsafe { transmute(__lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrne_w_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrne_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrne_l_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftintrne_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrp_w_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrp_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrp_l_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftintrp_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrm_w_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrm_w_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrm_l_d(a: m128d) -> m128i { unsafe { transmute(__lsx_vftintrm_l_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftint_w_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vftint_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffint_s_l(a: m128i, b: m128i) -> m128 { unsafe { transmute(__lsx_vffint_s_l(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrz_w_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vftintrz_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrp_w_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vftintrp_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrm_w_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vftintrm_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrne_w_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vftintrne_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintl_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftinth_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftinth_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffinth_d_w(a: m128i) -> m128d { unsafe { transmute(__lsx_vffinth_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vffintl_d_w(a: m128i) -> m128d { unsafe { transmute(__lsx_vffintl_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrzl_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrzl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrzh_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrzh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrpl_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrpl_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrph_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrph_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrml_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrml_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrmh_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrmh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrnel_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrnel_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vftintrneh_l_s(a: m128) -> m128i { unsafe { transmute(__lsx_vftintrneh_l_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrne_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrintrne_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrne_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrintrne_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrz_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrintrz_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrz_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrintrz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrp_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrintrp_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrp_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrintrp_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrm_s(a: m128) -> m128 { unsafe { transmute(__lsx_vfrintrm_s(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfrintrm_d(a: m128d) -> m128d { unsafe { transmute(__lsx_vfrintrm_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstelm_b(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM4, 4); - transmute(__lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4)) + __lsx_vstelm_b(transmute(a), mem_addr, IMM_S8, IMM4) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstelm_h(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM3, 3); - transmute(__lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3)) + __lsx_vstelm_h(transmute(a), mem_addr, IMM_S8, IMM3) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstelm_w(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM2, 2); - transmute(__lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2)) + __lsx_vstelm_w(transmute(a), mem_addr, IMM_S8, IMM2) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2, 3)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstelm_d(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S8, 8); static_assert_uimm_bits!(IMM1, 1); - transmute(__lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1)) + __lsx_vstelm_d(transmute(a), mem_addr, IMM_S8, IMM1) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_d_wu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_w_hu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_h_bu_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_d_wu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_w_hu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_h_bu_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwev_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsubwod_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsubwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwev_q_du_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwev_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vaddwod_q_du_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vaddwod_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_d_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_d_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_w_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_w_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_h_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_h_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_d_wu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_d_wu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_w_hu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_w_hu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_h_bu(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_h_bu(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_d_wu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_w_hu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_h_bu_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_d_wu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_d_wu_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_w_hu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_w_hu_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_h_bu_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_h_bu_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_q_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_q_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwev_q_du_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwev_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmulwod_q_du_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vmulwod_q_du_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhaddw_qu_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhaddw_qu_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_q_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_q_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vhsubw_qu_du(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vhsubw_qu_du(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_d_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_w_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_h_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_d_wu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_w_hu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_h_bu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_d_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_w_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_h_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_d_wu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_w_hu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_h_bu(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_d_wu_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_w_hu_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_h_bu_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_d_wu_w(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_d_wu_w(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_w_hu_h(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_w_hu_h(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_h_bu_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_h_bu_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_q_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_q_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_q_du(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_q_du(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwev_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwev_q_du_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmaddwod_q_du_d(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vmaddwod_q_du_d(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vrotr_b(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vrotr_b(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vrotr_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vrotr_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vrotr_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vrotr_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vrotr_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vrotr_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vadd_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vadd_q(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vsub_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsub_q(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5780,7 +5780,7 @@ pub unsafe fn lsx_vldrepl_b(mem_addr: *const i8) -> m128i { transmute(__lsx_vldrepl_b(mem_addr, IMM_S12)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5789,7 +5789,7 @@ pub unsafe fn lsx_vldrepl_h(mem_addr: *const i8) -> m128i { transmute(__lsx_vldrepl_h(mem_addr, IMM_S11)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5798,7 +5798,7 @@ pub unsafe fn lsx_vldrepl_w(mem_addr: *const i8) -> m128i { transmute(__lsx_vldrepl_w(mem_addr, IMM_S10)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5807,77 +5807,77 @@ pub unsafe fn lsx_vldrepl_d(mem_addr: *const i8) -> m128i { transmute(__lsx_vldrepl_d(mem_addr, IMM_S9)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmskgez_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vmskgez_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vmsknz_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vmsknz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_h_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_h_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_w_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_w_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_d_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_d_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_q_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_q_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_hu_bu(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_hu_bu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_wu_hu(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_wu_hu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_du_wu(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_du_wu(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vexth_qu_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vexth_qu_du(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5886,7 +5886,7 @@ pub fn lsx_vrotri_b(a: m128i) -> m128i { unsafe { transmute(__lsx_vrotri_b(transmute(a), IMM3)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5895,7 +5895,7 @@ pub fn lsx_vrotri_h(a: m128i) -> m128i { unsafe { transmute(__lsx_vrotri_h(transmute(a), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5904,7 +5904,7 @@ pub fn lsx_vrotri_w(a: m128i) -> m128i { unsafe { transmute(__lsx_vrotri_w(transmute(a), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5913,14 +5913,14 @@ pub fn lsx_vrotri_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vrotri_d(transmute(a), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vextl_q_d(a: m128i) -> m128i { unsafe { transmute(__lsx_vextl_q_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5929,7 +5929,7 @@ pub fn lsx_vsrlni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5938,7 +5938,7 @@ pub fn lsx_vsrlni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5947,7 +5947,7 @@ pub fn lsx_vsrlni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5956,7 +5956,7 @@ pub fn lsx_vsrlni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5965,7 +5965,7 @@ pub fn lsx_vsrlrni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5974,7 +5974,7 @@ pub fn lsx_vsrlrni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5983,7 +5983,7 @@ pub fn lsx_vsrlrni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -5992,7 +5992,7 @@ pub fn lsx_vsrlrni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrlrni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6001,7 +6001,7 @@ pub fn lsx_vssrlni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6010,7 +6010,7 @@ pub fn lsx_vssrlni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6019,7 +6019,7 @@ pub fn lsx_vssrlni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6028,7 +6028,7 @@ pub fn lsx_vssrlni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6037,7 +6037,7 @@ pub fn lsx_vssrlni_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6046,7 +6046,7 @@ pub fn lsx_vssrlni_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6055,7 +6055,7 @@ pub fn lsx_vssrlni_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6064,7 +6064,7 @@ pub fn lsx_vssrlni_du_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6073,7 +6073,7 @@ pub fn lsx_vssrlrni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6082,7 +6082,7 @@ pub fn lsx_vssrlrni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6091,7 +6091,7 @@ pub fn lsx_vssrlrni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6100,7 +6100,7 @@ pub fn lsx_vssrlrni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6109,7 +6109,7 @@ pub fn lsx_vssrlrni_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6118,7 +6118,7 @@ pub fn lsx_vssrlrni_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6127,7 +6127,7 @@ pub fn lsx_vssrlrni_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6136,7 +6136,7 @@ pub fn lsx_vssrlrni_du_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6145,7 +6145,7 @@ pub fn lsx_vsrani_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrani_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6154,7 +6154,7 @@ pub fn lsx_vsrani_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrani_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6163,7 +6163,7 @@ pub fn lsx_vsrani_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrani_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6172,7 +6172,7 @@ pub fn lsx_vsrani_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrani_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6181,7 +6181,7 @@ pub fn lsx_vsrarni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6190,7 +6190,7 @@ pub fn lsx_vsrarni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6199,7 +6199,7 @@ pub fn lsx_vsrarni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6208,7 +6208,7 @@ pub fn lsx_vsrarni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vsrarni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6217,7 +6217,7 @@ pub fn lsx_vssrani_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6226,7 +6226,7 @@ pub fn lsx_vssrani_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6235,7 +6235,7 @@ pub fn lsx_vssrani_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6244,7 +6244,7 @@ pub fn lsx_vssrani_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6253,7 +6253,7 @@ pub fn lsx_vssrani_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6262,7 +6262,7 @@ pub fn lsx_vssrani_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6271,7 +6271,7 @@ pub fn lsx_vssrani_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6280,7 +6280,7 @@ pub fn lsx_vssrani_du_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrani_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6289,7 +6289,7 @@ pub fn lsx_vssrarni_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_b_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6298,7 +6298,7 @@ pub fn lsx_vssrarni_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_h_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6307,7 +6307,7 @@ pub fn lsx_vssrarni_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_w_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6316,7 +6316,7 @@ pub fn lsx_vssrarni_d_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_d_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6325,7 +6325,7 @@ pub fn lsx_vssrarni_bu_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_bu_h(transmute(a), transmute(b), IMM4)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6334,7 +6334,7 @@ pub fn lsx_vssrarni_hu_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_hu_w(transmute(a), transmute(b), IMM5)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6343,7 +6343,7 @@ pub fn lsx_vssrarni_wu_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_wu_d(transmute(a), transmute(b), IMM6)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6352,7 +6352,7 @@ pub fn lsx_vssrarni_du_q(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrarni_du_q(transmute(a), transmute(b), IMM7)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6361,7 +6361,7 @@ pub fn lsx_vpermi_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vpermi_w(transmute(a), transmute(b), IMM8)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6370,65 +6370,65 @@ pub unsafe fn lsx_vld(mem_addr: *const i8) -> m128i { transmute(__lsx_vld(mem_addr, IMM_S12)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vst(a: m128i, mem_addr: *mut i8) { static_assert_simm_bits!(IMM_S12, 12); - transmute(__lsx_vst(transmute(a), mem_addr, IMM_S12)) + __lsx_vst(transmute(a), mem_addr, IMM_S12) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrlrn_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrlrn_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_b_h(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_b_h(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_h_w(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_h_w(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vssrln_w_d(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vssrln_w_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vorn_v(a: m128i, b: m128i) -> m128i { unsafe { transmute(__lsx_vorn_v(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6437,413 +6437,413 @@ pub fn lsx_vldi() -> m128i { unsafe { transmute(__lsx_vldi(IMM_S13)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vshuf_b(a: m128i, b: m128i, c: m128i) -> m128i { unsafe { transmute(__lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vldx(mem_addr: *const i8, b: i64) -> m128i { transmute(__lsx_vldx(mem_addr, transmute(b))) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lsx_vstx(a: m128i, mem_addr: *mut i8, b: i64) { - transmute(__lsx_vstx(transmute(a), mem_addr, transmute(b))) + __lsx_vstx(transmute(a), mem_addr, transmute(b)) } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vextl_qu_du(a: m128i) -> m128i { unsafe { transmute(__lsx_vextl_qu_du(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bnz_b(a: m128i) -> i32 { unsafe { transmute(__lsx_bnz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bnz_d(a: m128i) -> i32 { unsafe { transmute(__lsx_bnz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bnz_h(a: m128i) -> i32 { unsafe { transmute(__lsx_bnz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bnz_v(a: m128i) -> i32 { unsafe { transmute(__lsx_bnz_v(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bnz_w(a: m128i) -> i32 { unsafe { transmute(__lsx_bnz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bz_b(a: m128i) -> i32 { unsafe { transmute(__lsx_bz_b(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bz_d(a: m128i) -> i32 { unsafe { transmute(__lsx_bz_d(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bz_h(a: m128i) -> i32 { unsafe { transmute(__lsx_bz_h(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bz_v(a: m128i) -> i32 { unsafe { transmute(__lsx_bz_v(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_bz_w(a: m128i) -> i32 { unsafe { transmute(__lsx_bz_w(transmute(a))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_caf_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_caf_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_caf_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_caf_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_ceq_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_ceq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_ceq_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_ceq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cle_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cle_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cle_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_clt_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_clt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_clt_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_clt_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cne_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cne_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cne_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cne_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cor_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cor_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cor_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cor_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cueq_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cueq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cueq_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cueq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cule_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cule_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cule_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cule_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cult_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cult_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cult_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cult_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cun_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cun_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cune_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_cune_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cune_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cune_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_cun_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_cun_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_saf_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_saf_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_saf_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_saf_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_seq_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_seq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_seq_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_seq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sle_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sle_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sle_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sle_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_slt_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_slt_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_slt_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_slt_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sne_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sne_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sne_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sne_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sor_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sor_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sor_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sor_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sueq_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sueq_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sueq_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sueq_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sule_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sule_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sule_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sule_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sult_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sult_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sult_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sult_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sun_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sun_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sune_d(a: m128d, b: m128d) -> m128i { unsafe { transmute(__lsx_vfcmp_sune_d(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sune_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sune_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn lsx_vfcmp_sun_s(a: m128, b: m128) -> m128i { unsafe { transmute(__lsx_vfcmp_sun_s(transmute(a), transmute(b))) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6852,7 +6852,7 @@ pub fn lsx_vrepli_b() -> m128i { unsafe { transmute(__lsx_vrepli_b(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6861,7 +6861,7 @@ pub fn lsx_vrepli_d() -> m128i { unsafe { transmute(__lsx_vrepli_d(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -6870,7 +6870,7 @@ pub fn lsx_vrepli_h() -> m128i { unsafe { transmute(__lsx_vrepli_h(IMM_S10)) } } -#[inline] +#[inline(always)] #[target_feature(enable = "lsx")] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] diff --git a/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs b/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs index 5670bd4378a8..748e2b597ada 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/lsx/tests.rs @@ -5,6 +5,7 @@ core_arch::{loongarch64::*, simd::*}, mem::transmute, }; +use std::hint::black_box; use stdarch_test::simd_test; #[simd_test(enable = "lsx")] @@ -17,7 +18,10 @@ unsafe fn test_lsx_vsll_b() { ); let r = i64x2::new(70990221811840, -3257029622096690968); - assert_eq!(r, transmute(lsx_vsll_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -26,7 +30,10 @@ unsafe fn test_lsx_vsll_h() { let b = i16x8::new(-10317, -20778, -9962, -8975, 25298, 12929, -13803, -18669); let r = i64x2::new(-5063658964307128392, -3539825456407336052); - assert_eq!(r, transmute(lsx_vsll_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -35,7 +42,10 @@ unsafe fn test_lsx_vsll_w() { let b = i32x4::new(82237029, -819106294, -96895338, -456101700); let r = i64x2::new(-7163824029380778240, 2305843009528266752); - assert_eq!(r, transmute(lsx_vsll_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -44,7 +54,10 @@ unsafe fn test_lsx_vsll_d() { let b = i64x2::new(8592669249977019309, -1379694176202045825); let r = i64x2::new(1790743801833193472, 0); - assert_eq!(r, transmute(lsx_vsll_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsll_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -54,7 +67,7 @@ unsafe fn test_lsx_vslli_b() { ); let r = i64x2::new(-2780807324588213414, -3708578564830607166); - assert_eq!(r, transmute(lsx_vslli_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -62,7 +75,7 @@ unsafe fn test_lsx_vslli_h() { let a = i16x8::new(18469, -14840, 23655, -3474, 7467, 2798, -15418, 26847); let r = i64x2::new(-7241759886206301888, 4017476402818337472); - assert_eq!(r, transmute(lsx_vslli_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -70,7 +83,7 @@ unsafe fn test_lsx_vslli_w() { let a = i32x4::new(20701902, -1777432355, 6349179, 1747667894); let r = i64x2::new(4189319625752393728, -5967594959501136896); - assert_eq!(r, transmute(lsx_vslli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -78,7 +91,7 @@ unsafe fn test_lsx_vslli_d() { let a = i64x2::new(-5896889635782282086, -8807609320972692839); let r = i64x2::new(-4233027607937510592, -5142337165482896608); - assert_eq!(r, transmute(lsx_vslli_d::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslli_d::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -91,7 +104,10 @@ unsafe fn test_lsx_vsra_b() { ); let r = i64x2::new(-1080315035391229440, 720022881735668484); - assert_eq!(r, transmute(lsx_vsra_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -100,7 +116,10 @@ unsafe fn test_lsx_vsra_h() { let b = i16x8::new(14017, 3796, 23987, -27244, -13363, 21333, -10262, 23633); let r = i64x2::new(164116464290576704, -1935703552267190275); - assert_eq!(r, transmute(lsx_vsra_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -109,7 +128,10 @@ unsafe fn test_lsx_vsra_w() { let b = i32x4::new(-670772992, 2044335288, -1224858031, 520588790); let r = i64x2::new(-210763200496, 1619202657181); - assert_eq!(r, transmute(lsx_vsra_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -118,7 +140,10 @@ unsafe fn test_lsx_vsra_d() { let b = i64x2::new(4251079558060308329, 4657697142994416829); let r = i64x2::new(-623956, 3); - assert_eq!(r, transmute(lsx_vsra_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsra_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -128,7 +153,7 @@ unsafe fn test_lsx_vsrai_b() { ); let r = i64x2::new(-2018743940785760257, -2093355901512246518); - assert_eq!(r, transmute(lsx_vsrai_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -136,7 +161,7 @@ unsafe fn test_lsx_vsrai_h() { let a = i16x8::new(-22502, -7299, 19084, -21578, -28082, 20851, 23456, 15524); let r = i64x2::new(-1688828385492998, 844446405361657); - assert_eq!(r, transmute(lsx_vsrai_h::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_h::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -144,7 +169,7 @@ unsafe fn test_lsx_vsrai_w() { let a = i32x4::new(743537539, 1831641900, -1639033567, -984629971); let r = i64x2::new(30008936499988, -16131897170029); - assert_eq!(r, transmute(lsx_vsrai_w::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_w::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -152,7 +177,7 @@ unsafe fn test_lsx_vsrai_d() { let a = i64x2::new(-8375997486414293750, 1714581574012370587); let r = i64x2::new(-476121, 97462); - assert_eq!(r, transmute(lsx_vsrai_d::<44>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrai_d::<44>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -165,7 +190,13 @@ unsafe fn test_lsx_vsrar_b() { ); let r = i64x2::new(139917463134404866, 143840305941130491); - assert_eq!(r, transmute(lsx_vsrar_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -174,7 +205,13 @@ unsafe fn test_lsx_vsrar_h() { let b = i16x8::new(-26450, 2176, 31587, 2222, 13726, 30172, 1067, -14273); let r = i64x2::new(-287115463426050, 42950131714); - assert_eq!(r, transmute(lsx_vsrar_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -183,7 +220,13 @@ unsafe fn test_lsx_vsrar_w() { let b = i32x4::new(-1532076758, 940127488, 1781366421, 1497262222); let r = i64x2::new(7179867468326627830, 560544771735247); - assert_eq!(r, transmute(lsx_vsrar_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -192,7 +235,13 @@ unsafe fn test_lsx_vsrar_d() { let b = i64x2::new(3571440266112779495, -725943254065719378); let r = i64x2::new(-890187, -17811); - assert_eq!(r, transmute(lsx_vsrar_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrar_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -202,7 +251,7 @@ unsafe fn test_lsx_vsrari_b() { ); let r = i64x2::new(867219992078845182, -503291487652282122); - assert_eq!(r, transmute(lsx_vsrari_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -210,7 +259,7 @@ unsafe fn test_lsx_vsrari_h() { let a = i16x8::new(29939, -1699, 12357, 30805, -30883, 31936, 15701, -11818); let r = i64x2::new(4222154715365391, -1688815499411471); - assert_eq!(r, transmute(lsx_vsrari_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -218,7 +267,7 @@ unsafe fn test_lsx_vsrari_w() { let a = i32x4::new(588196178, -1058764534, 1325397591, 1169671026); let r = i64x2::new(-4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vsrari_w::<30>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_w::<30>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -226,7 +275,7 @@ unsafe fn test_lsx_vsrari_d() { let a = i64x2::new(-2795326946470057100, 6746045132217841338); let r = i64x2::new(-174707934154378569, 421627820763615084); - assert_eq!(r, transmute(lsx_vsrari_d::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrari_d::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -239,7 +288,10 @@ unsafe fn test_lsx_vsrl_b() { ); let r = i64x2::new(1300161376517358116, 72917012339034650); - assert_eq!(r, transmute(lsx_vsrl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -248,7 +300,10 @@ unsafe fn test_lsx_vsrl_h() { let b = i16x8::new(16605, -13577, -26644, -17739, 11000, -29283, -15971, 20169); let r = i64x2::new(468374382728249347, 20829178341621860); - assert_eq!(r, transmute(lsx_vsrl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -257,7 +312,10 @@ unsafe fn test_lsx_vsrl_w() { let b = i32x4::new(1777885221, -1725401090, 1849724045, -1051851102); let r = i64x2::new(12953227061, 1599606693325790121); - assert_eq!(r, transmute(lsx_vsrl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -266,7 +324,10 @@ unsafe fn test_lsx_vsrl_d() { let b = i64x2::new(-7903128394835365398, 7601347629202818185); let r = i64x2::new(649044, 1572171616025062); - assert_eq!(r, transmute(lsx_vsrl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrl_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -276,7 +337,7 @@ unsafe fn test_lsx_vsrli_b() { ); let r = i64x2::new(1952909805632365845, 3971107439766933248); - assert_eq!(r, transmute(lsx_vsrli_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -284,7 +345,7 @@ unsafe fn test_lsx_vsrli_h() { let a = i16x8::new(29545, 354, 27695, 20915, -32766, -24491, 10641, 20310); let r = i64x2::new(11259230996660281, 10977609996304448); - assert_eq!(r, transmute(lsx_vsrli_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -292,7 +353,7 @@ unsafe fn test_lsx_vsrli_w() { let a = i32x4::new(627703601, 922874410, -234412645, -1216101872); let r = i64x2::new(3870813506329215, 12913695352717769); - assert_eq!(r, transmute(lsx_vsrli_w::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_w::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -300,7 +361,7 @@ unsafe fn test_lsx_vsrli_d() { let a = i64x2::new(1407685950714554203, -6076144426076800688); let r = i64x2::new(9, 85); - assert_eq!(r, transmute(lsx_vsrli_d::<57>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrli_d::<57>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -313,7 +374,13 @@ unsafe fn test_lsx_vsrlr_b() { ); let r = i64x2::new(3317746744565237249, 144420860932066826); - assert_eq!(r, transmute(lsx_vsrlr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -322,7 +389,13 @@ unsafe fn test_lsx_vsrlr_h() { let b = i16x8::new(19500, -26403, -1282, 12290, -18989, 25105, -24347, 6707); let r = i64x2::new(1991716935204929539, 311033695131730530); - assert_eq!(r, transmute(lsx_vsrlr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -331,7 +404,13 @@ unsafe fn test_lsx_vsrlr_w() { let b = i32x4::new(1830015593, -1452673200, 962662328, -252736055); let r = i64x2::new(7864089021084, 20473000998469780); - assert_eq!(r, transmute(lsx_vsrlr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -340,7 +419,13 @@ unsafe fn test_lsx_vsrlr_d() { let b = i64x2::new(-1543621369665313706, 8544381131364512650); let r = i64x2::new(1428972826343, 4256393046182047); - assert_eq!(r, transmute(lsx_vsrlr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -350,7 +435,7 @@ unsafe fn test_lsx_vsrlri_b() { ); let r = i64x2::new(93866580842851436, 1896906350202744602); - assert_eq!(r, transmute(lsx_vsrlri_b::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_b::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -358,7 +443,7 @@ unsafe fn test_lsx_vsrlri_h() { let a = i16x8::new(-18045, 1968, 22966, 3692, 2010, -17108, 3373, -30706); let r = i64x2::new(1039304252363684227, -8642956144778934310); - assert_eq!(r, transmute(lsx_vsrlri_h::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_h::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -366,7 +451,7 @@ unsafe fn test_lsx_vsrlri_w() { let a = i32x4::new(1306456564, -1401620667, -839707416, -1634862919); let r = i64x2::new(1553353645217275455, 1428132662790218397); - assert_eq!(r, transmute(lsx_vsrlri_w::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_w::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -374,7 +459,7 @@ unsafe fn test_lsx_vsrlri_d() { let a = i64x2::new(-3683179565838693027, 6160461828074490983); let r = i64x2::new(205, 85); - assert_eq!(r, transmute(lsx_vsrlri_d::<56>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsrlri_d::<56>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -387,7 +472,13 @@ unsafe fn test_lsx_vbitclr_b() { ); let r = i64x2::new(-7325372782311046420, -5316383129963115396); - assert_eq!(r, transmute(lsx_vbitclr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -396,7 +487,13 @@ unsafe fn test_lsx_vbitclr_h() { let b = u16x8::new(26587, 57597, 34751, 38678, 23919, 45729, 62569, 5978); let r = i64x2::new(-5495443997997256700, -3317648531059028099); - assert_eq!(r, transmute(lsx_vbitclr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -405,7 +502,13 @@ unsafe fn test_lsx_vbitclr_w() { let b = u32x4::new(1968231094, 2827365864, 4097273355, 4016923215); let r = i64x2::new(-7626667807832507452, 546969093373761021); - assert_eq!(r, transmute(lsx_vbitclr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -414,7 +517,13 @@ unsafe fn test_lsx_vbitclr_d() { let b = u64x2::new(5723204188033770667, 2981956604140378920); let r = i64x2::new(-1242851545812588193, -5509634528458855560); - assert_eq!(r, transmute(lsx_vbitclr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitclr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -424,7 +533,7 @@ unsafe fn test_lsx_vbitclri_b() { ); let r = i64x2::new(7503621968728299154, -6865556469255070542); - assert_eq!(r, transmute(lsx_vbitclri_b::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_b::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -432,7 +541,7 @@ unsafe fn test_lsx_vbitclri_h() { let a = u16x8::new(17366, 58985, 22108, 45942, 27326, 19605, 9632, 32322); let r = i64x2::new(-5515130134779575338, 8809640793386347198); - assert_eq!(r, transmute(lsx_vbitclri_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -440,7 +549,7 @@ unsafe fn test_lsx_vbitclri_w() { let a = u32x4::new(718858183, 3771164920, 1842485081, 896350597); let r = i64x2::new(-2249714073768237625, 3849796501707560281); - assert_eq!(r, transmute(lsx_vbitclri_w::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_w::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -448,7 +557,7 @@ unsafe fn test_lsx_vbitclri_d() { let a = u64x2::new(10838658690401820648, 3833745076866321369); let r = i64x2::new(-7608085933063544856, 3833744527110507481); - assert_eq!(r, transmute(lsx_vbitclri_d::<39>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitclri_d::<39>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -461,7 +570,13 @@ unsafe fn test_lsx_vbitset_b() { ); let r = i64x2::new(-7941579666116909337, -8620998056061183460); - assert_eq!(r, transmute(lsx_vbitset_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -470,7 +585,13 @@ unsafe fn test_lsx_vbitset_h() { let b = u16x8::new(64512, 23847, 57770, 47705, 8024, 31966, 14493, 50266); let r = i64x2::new(8218739538452480967, 9190693790629616954); - assert_eq!(r, transmute(lsx_vbitset_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -479,7 +600,13 @@ unsafe fn test_lsx_vbitset_w() { let b = u32x4::new(3259082048, 1303228302, 1429001720, 209615081); let r = i64x2::new(5472281065241838073, -4235320193476931022); - assert_eq!(r, transmute(lsx_vbitset_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -488,7 +615,13 @@ unsafe fn test_lsx_vbitset_d() { let b = u64x2::new(12687331714071910183, 1753585392879336372); let r = i64x2::new(8117422612773760492, 5031452210401715131); - assert_eq!(r, transmute(lsx_vbitset_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitset_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -498,7 +631,7 @@ unsafe fn test_lsx_vbitseti_b() { ); let r = i64x2::new(6185254145054243811, 5860546440891134157); - assert_eq!(r, transmute(lsx_vbitseti_b::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_b::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -506,7 +639,7 @@ unsafe fn test_lsx_vbitseti_h() { let a = u16x8::new(15222, 59961, 52253, 2908, 61562, 41309, 63627, 4191); let r = i64x2::new(819316619673811830, 1179934905985921146); - assert_eq!(r, transmute(lsx_vbitseti_h::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_h::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -514,7 +647,7 @@ unsafe fn test_lsx_vbitseti_w() { let a = u32x4::new(3788412756, 1863556832, 1913138259, 1199998627); let r = i64x2::new(8012922850722617172, 5162962059379878995); - assert_eq!(r, transmute(lsx_vbitseti_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -522,7 +655,7 @@ unsafe fn test_lsx_vbitseti_d() { let a = u64x2::new(10744510173660993785, 16946223211744108759); let r = i64x2::new(-7702233900048557831, -1500520861831225129); - assert_eq!(r, transmute(lsx_vbitseti_d::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitseti_d::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -535,7 +668,13 @@ unsafe fn test_lsx_vbitrev_b() { ); let r = i64x2::new(7553563628828981794, -3550669970358088907); - assert_eq!(r, transmute(lsx_vbitrev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -544,7 +683,13 @@ unsafe fn test_lsx_vbitrev_h() { let b = u16x8::new(21347, 23131, 57157, 13786, 34463, 33445, 23964, 48087); let r = i64x2::new(-2253077037977362312, -1686202867067838120); - assert_eq!(r, transmute(lsx_vbitrev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -553,7 +698,13 @@ unsafe fn test_lsx_vbitrev_w() { let b = u32x4::new(3330530584, 4153020036, 822570638, 2652744506); let r = i64x2::new(4583672484591007782, 3195058299616182309); - assert_eq!(r, transmute(lsx_vbitrev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -562,7 +713,13 @@ unsafe fn test_lsx_vbitrev_d() { let b = u64x2::new(10942298949673565895, 12884740754463765660); let r = i64x2::new(-2430080033105247697, -384636561250515393); - assert_eq!(r, transmute(lsx_vbitrev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vbitrev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -572,7 +729,7 @@ unsafe fn test_lsx_vbitrevi_b() { ); let r = i64x2::new(8727320563398842300, 7658903196653594166); - assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -580,7 +737,7 @@ unsafe fn test_lsx_vbitrevi_h() { let a = u16x8::new(15083, 24599, 61212, 12408, 48399, 59833, 45416, 58826); let r = i64x2::new(8104420064785562347, -6500117680329458417); - assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -588,7 +745,7 @@ unsafe fn test_lsx_vbitrevi_w() { let a = u32x4::new(1200613355, 1418062686, 3847355950, 3312937419); let r = i64x2::new(6099540060505368555, -4226793400815190482); - assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_w::<21>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -596,7 +753,7 @@ unsafe fn test_lsx_vbitrevi_d() { let a = u64x2::new(295858379748270823, 1326723086853575042); let r = i64x2::new(295858379748254439, 1326723086853591426); - assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbitrevi_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -609,7 +766,10 @@ unsafe fn test_lsx_vadd_b() { ); let r = i64x2::new(5228548393274527852, 1107461330348121713); - assert_eq!(r, transmute(lsx_vadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -618,7 +778,10 @@ unsafe fn test_lsx_vadd_h() { let b = i16x8::new(-25040, 15453, -28080, -31322, -24429, -12453, -18073, 27019); let r = i64x2::new(1938006946753467667, 3264410328302682781); - assert_eq!(r, transmute(lsx_vadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -627,7 +790,10 @@ unsafe fn test_lsx_vadd_w() { let b = i32x4::new(-1169804484, 389773725, -731843701, -1825112934); let r = i64x2::new(-2841313158179161935, -1386205072290870384); - assert_eq!(r, transmute(lsx_vadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -636,7 +802,10 @@ unsafe fn test_lsx_vadd_d() { let b = i64x2::new(7093939531558864473, 4047047970310912233); let r = i64x2::new(-204689461315224217, -5456447511965942904); - assert_eq!(r, transmute(lsx_vadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -646,7 +815,7 @@ unsafe fn test_lsx_vaddi_bu() { ); let r = i64x2::new(-7790681010872578420, 298548864442153210); - assert_eq!(r, transmute(lsx_vaddi_bu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_bu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -654,7 +823,7 @@ unsafe fn test_lsx_vaddi_hu() { let a = i16x8::new(-16986, -28417, 11657, 16608, -30167, 18602, 8897, -854); let r = i64x2::new(4681541984598867390, -233585914045887935); - assert_eq!(r, transmute(lsx_vaddi_hu::<24>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_hu::<24>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -662,7 +831,7 @@ unsafe fn test_lsx_vaddi_wu() { let a = i32x4::new(1142343549, 56714754, -180143297, 408668191); let r = i64x2::new(243588023362963327, 1755216527965240129); - assert_eq!(r, transmute(lsx_vaddi_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -670,7 +839,7 @@ unsafe fn test_lsx_vaddi_du() { let a = i64x2::new(4516502893749962130, 9158051921593642947); let r = i64x2::new(4516502893749962139, 9158051921593642956); - assert_eq!(r, transmute(lsx_vaddi_du::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vaddi_du::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -683,7 +852,10 @@ unsafe fn test_lsx_vsub_b() { ); let r = i64x2::new(-4051929421319416371, 8737463450488952169); - assert_eq!(r, transmute(lsx_vsub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -692,7 +864,10 @@ unsafe fn test_lsx_vsub_h() { let b = i16x8::new(15368, 16207, 9677, 21447, -29583, -22036, 1845, 15671); let r = i64x2::new(-913983189443969573, 2742472381424198215); - assert_eq!(r, transmute(lsx_vsub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -701,7 +876,10 @@ unsafe fn test_lsx_vsub_w() { let b = i32x4::new(617176389, -1376778690, 1463940361, 620446698); let r = i64x2::new(-7247543435452521192, -8067077040042720878); - assert_eq!(r, transmute(lsx_vsub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -710,7 +888,10 @@ unsafe fn test_lsx_vsub_d() { let b = i64x2::new(1314101702815749241, 7673634401554993450); let r = i64x2::new(5925090640479842026, 5645651807574135757); - assert_eq!(r, transmute(lsx_vsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -720,7 +901,7 @@ unsafe fn test_lsx_vsubi_bu() { ); let r = i64x2::new(-8192169673836457574, 4758493248402185941); - assert_eq!(r, transmute(lsx_vsubi_bu::<19>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_bu::<19>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -728,7 +909,7 @@ unsafe fn test_lsx_vsubi_hu() { let a = i16x8::new(13272, -26858, -235, 16054, 29698, 1377, 4604, -3878); let r = i64x2::new(4514576075959186376, -1096043853912116238); - assert_eq!(r, transmute(lsx_vsubi_hu::<16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_hu::<16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -736,7 +917,7 @@ unsafe fn test_lsx_vsubi_wu() { let a = i32x4::new(1277091145, -2076591216, -1523555105, -945754023); let r = i64x2::new(-8918891362898748088, -4061982600368986914); - assert_eq!(r, transmute(lsx_vsubi_wu::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_wu::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -744,7 +925,7 @@ unsafe fn test_lsx_vsubi_du() { let a = i64x2::new(-8248876128472283209, -2119651236628000925); let r = i64x2::new(-8248876128472283234, -2119651236628000950); - assert_eq!(r, transmute(lsx_vsubi_du::<25>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsubi_du::<25>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -757,7 +938,10 @@ unsafe fn test_lsx_vmax_b() { ); let r = i64x2::new(1260734548147228113, 7591133008682590587); - assert_eq!(r, transmute(lsx_vmax_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -766,7 +950,10 @@ unsafe fn test_lsx_vmax_h() { let b = i16x8::new(25637, -11569, -23103, 6983, -17125, 5183, -709, 5986); let r = i64x2::new(1965654441534120997, 1684966995419662474); - assert_eq!(r, transmute(lsx_vmax_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -775,7 +962,10 @@ unsafe fn test_lsx_vmax_w() { let b = i32x4::new(643859790, -389733899, -1309288060, 1934346522); let r = i64x2::new(-1673894349703707314, 8307955054730158361); - assert_eq!(r, transmute(lsx_vmax_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -784,7 +974,10 @@ unsafe fn test_lsx_vmax_d() { let b = i64x2::new(-6137495199657896371, 2160025776787809810); let r = i64x2::new(-990960773872867733, 6406870358170165030); - assert_eq!(r, transmute(lsx_vmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -794,7 +987,7 @@ unsafe fn test_lsx_vmaxi_b() { ); let r = i64x2::new(5908253215318699518, 1728939149412407162); - assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_b::<-2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -802,7 +995,7 @@ unsafe fn test_lsx_vmaxi_h() { let a = i16x8::new(-14059, 19536, 15816, 28251, 23079, -10486, -11781, 25565); let r = i64x2::new(7952017497535807498, 7195907822558272039); - assert_eq!(r, transmute(lsx_vmaxi_h::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_h::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -810,7 +1003,7 @@ unsafe fn test_lsx_vmaxi_w() { let a = i32x4::new(-1136628686, -168033999, -2082324641, -1789957469); let r = i64x2::new(55834574861, 55834574861); - assert_eq!(r, transmute(lsx_vmaxi_w::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_w::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -818,7 +1011,7 @@ unsafe fn test_lsx_vmaxi_d() { let a = i64x2::new(-490958606840895025, -602287987736508723); let r = i64x2::new(-5, -5); - assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_d::<-5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -831,7 +1024,13 @@ unsafe fn test_lsx_vmax_bu() { ); let r = i64x2::new(-5712542810735052010, 4588590651995571688); - assert_eq!(r, transmute(lsx_vmax_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -840,7 +1039,13 @@ unsafe fn test_lsx_vmax_hu() { let b = u16x8::new(61508, 27224, 11696, 15294, 30725, 4809, 55995, 24012); let r = i64x2::new(6366821095949791300, 6759017637785204741); - assert_eq!(r, transmute(lsx_vmax_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -849,7 +1054,13 @@ unsafe fn test_lsx_vmax_wu() { let b = u32x4::new(2856502284, 546582019, 3814541188, 2370198139); let r = i64x2::new(2347551899043152908, -8266820577849948284); - assert_eq!(r, transmute(lsx_vmax_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -858,7 +1069,13 @@ unsafe fn test_lsx_vmax_du() { let b = u64x2::new(15559502733477870114, 3537017767853389449); let r = i64x2::new(-1341110034690820781, -6520089917898609068); - assert_eq!(r, transmute(lsx_vmax_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmax_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -868,7 +1085,7 @@ unsafe fn test_lsx_vmaxi_bu() { ); let r = i64x2::new(-1045930669804428840, -8076220938123067729); - assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_bu::<27>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -876,7 +1093,7 @@ unsafe fn test_lsx_vmaxi_hu() { let a = u16x8::new(56394, 18974, 59, 64239, 15178, 38205, 20044, 21066); let r = i64x2::new(-365072790147113910, 5929637950214978378); - assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_hu::<23>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -884,7 +1101,7 @@ unsafe fn test_lsx_vmaxi_wu() { let a = u32x4::new(2234002286, 3837532269, 3218694441, 2956128392); let r = i64x2::new(-1964668478775874706, -5750269304073789143); - assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_wu::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -892,7 +1109,7 @@ unsafe fn test_lsx_vmaxi_du() { let a = u64x2::new(3145066433415682744, 697260191203805367); let r = i64x2::new(3145066433415682744, 697260191203805367); - assert_eq!(r, transmute(lsx_vmaxi_du::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmaxi_du::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -905,7 +1122,10 @@ unsafe fn test_lsx_vmin_b() { ); let r = i64x2::new(1870285769536668398, -8941449826914199819); - assert_eq!(r, transmute(lsx_vmin_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -914,7 +1134,10 @@ unsafe fn test_lsx_vmin_h() { let b = i16x8::new(-5519, 15267, -28304, -5842, 32145, 6582, -9646, -24918); let r = i64x2::new(-1644216902720689551, -7013553423522578637); - assert_eq!(r, transmute(lsx_vmin_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -923,7 +1146,10 @@ unsafe fn test_lsx_vmin_w() { let b = i32x4::new(-425011290, -2104111279, 175390640, 571448257); let r = i64x2::new(-9037089126579775578, 2454351575346593712); - assert_eq!(r, transmute(lsx_vmin_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -932,7 +1158,10 @@ unsafe fn test_lsx_vmin_d() { let b = i64x2::new(7269804448576860985, -2384075780126369706); let r = i64x2::new(5262417572890363865, -2384075780126369706); - assert_eq!(r, transmute(lsx_vmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -942,7 +1171,7 @@ unsafe fn test_lsx_vmini_b() { ); let r = i64x2::new(-1187557278141451540, -940475489144045070); - assert_eq!(r, transmute(lsx_vmini_b::<-14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_b::<-14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -950,7 +1179,7 @@ unsafe fn test_lsx_vmini_h() { let a = i16x8::new(26119, -26421, -26720, 11534, 11181, -13024, -9525, -1565); let r = i64x2::new(-677708916064259, -440267769697468419); - assert_eq!(r, transmute(lsx_vmini_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -958,7 +1187,7 @@ unsafe fn test_lsx_vmini_w() { let a = i32x4::new(1937226480, -56354461, -210581139, 118641668); let r = i64x2::new(-242040566978707451, 25559222637); - assert_eq!(r, transmute(lsx_vmini_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -966,7 +1195,7 @@ unsafe fn test_lsx_vmini_d() { let a = i64x2::new(-6839357499730806877, 2982085289136510651); let r = i64x2::new(-6839357499730806877, 11); - assert_eq!(r, transmute(lsx_vmini_d::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_d::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -979,7 +1208,13 @@ unsafe fn test_lsx_vmin_bu() { ); let r = i64x2::new(3617816997909406996, 4784078933357220137); - assert_eq!(r, transmute(lsx_vmin_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -988,7 +1223,13 @@ unsafe fn test_lsx_vmin_hu() { let b = u16x8::new(30424, 14541, 7654, 46014, 42452, 14971, 14903, 13871); let r = i64x2::new(-5494921620712753448, 3904403410832303572); - assert_eq!(r, transmute(lsx_vmin_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -997,7 +1238,13 @@ unsafe fn test_lsx_vmin_wu() { let b = u32x4::new(1456829356, 2264966310, 1587887390, 645429404); let r = i64x2::new(-8718787844260924500, 2772098183187911585); - assert_eq!(r, transmute(lsx_vmin_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1006,7 +1253,13 @@ unsafe fn test_lsx_vmin_du() { let b = u64x2::new(15079551366517035256, 13891052596545854864); let r = i64x2::new(6641707046382446478, 5750385968612732680); - assert_eq!(r, transmute(lsx_vmin_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmin_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1016,7 +1269,7 @@ unsafe fn test_lsx_vmini_bu() { ); let r = i64x2::new(361700864190383365, 361700864190317829); - assert_eq!(r, transmute(lsx_vmini_bu::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_bu::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1024,7 +1277,7 @@ unsafe fn test_lsx_vmini_hu() { let a = u16x8::new(51791, 41830, 16737, 31634, 36341, 58491, 48701, 8690); let r = i64x2::new(5066626891382802, 5066626891382802); - assert_eq!(r, transmute(lsx_vmini_hu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_hu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1032,7 +1285,7 @@ unsafe fn test_lsx_vmini_wu() { let a = u32x4::new(1158888991, 2639721369, 556001789, 2902942998); let r = i64x2::new(77309411346, 77309411346); - assert_eq!(r, transmute(lsx_vmini_wu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_wu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1040,7 +1293,7 @@ unsafe fn test_lsx_vmini_du() { let a = u64x2::new(17903595768445663391, 13119300660970895532); let r = i64x2::new(13, 13); - assert_eq!(r, transmute(lsx_vmini_du::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vmini_du::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1053,7 +1306,10 @@ unsafe fn test_lsx_vseq_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1062,7 +1318,10 @@ unsafe fn test_lsx_vseq_h() { let b = i16x8::new(-7387, -24074, 15709, -4629, 30465, -9504, -21403, -30287); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1071,7 +1330,10 @@ unsafe fn test_lsx_vseq_w() { let b = i32x4::new(-493722413, -522973881, -1254416384, -884207273); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1080,7 +1342,10 @@ unsafe fn test_lsx_vseq_d() { let b = i64x2::new(3023654898382436999, 1783520577741396523); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vseq_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1090,7 +1355,7 @@ unsafe fn test_lsx_vseqi_b() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_b::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_b::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1098,7 +1363,7 @@ unsafe fn test_lsx_vseqi_h() { let a = i16x8::new(-3205, 25452, 20774, 22065, -8424, 16590, -15971, -14154); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_h::<-1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_h::<-1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1106,7 +1371,7 @@ unsafe fn test_lsx_vseqi_w() { let a = i32x4::new(199798215, -798304779, -1812193878, -1830438161); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_w::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_w::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1114,7 +1379,7 @@ unsafe fn test_lsx_vseqi_d() { let a = i64x2::new(-7376858177879278972, 1947027764115386661); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vseqi_d::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vseqi_d::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1124,7 +1389,7 @@ unsafe fn test_lsx_vslti_b() { ); let r = i64x2::new(-1099511627776, 1095216660480); - assert_eq!(r, transmute(lsx_vslti_b::<-4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_b::<-4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1137,7 +1402,10 @@ unsafe fn test_lsx_vslt_b() { ); let r = i64x2::new(-72056494526365441, -280375465148416); - assert_eq!(r, transmute(lsx_vslt_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1146,7 +1414,10 @@ unsafe fn test_lsx_vslt_h() { let b = i16x8::new(-10624, 12762, 31216, 13253, 2299, -12591, -8652, -22348); let r = i64x2::new(-4294967296, 65535); - assert_eq!(r, transmute(lsx_vslt_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1155,7 +1426,10 @@ unsafe fn test_lsx_vslt_w() { let b = i32x4::new(-1849021639, -756143028, 54274044, 646446450); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vslt_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1164,7 +1438,10 @@ unsafe fn test_lsx_vslt_d() { let b = i64x2::new(1481173131774551907, 270656941607020532); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1172,7 +1449,7 @@ unsafe fn test_lsx_vslti_h() { let a = i16x8::new(-8902, 5527, 17224, -27356, 4424, 28839, 29975, 18805); let r = i64x2::new(-281474976645121, 0); - assert_eq!(r, transmute(lsx_vslti_h::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_h::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1180,7 +1457,7 @@ unsafe fn test_lsx_vslti_w() { let a = i32x4::new(995282502, -1964668207, -996118772, 1812234755); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vslti_w::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_w::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1188,7 +1465,7 @@ unsafe fn test_lsx_vslti_d() { let a = i64x2::new(1441753618400573134, 3878439049744730841); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_d::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_d::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1201,7 +1478,13 @@ unsafe fn test_lsx_vslt_bu() { ); let r = i64x2::new(-281474959998721, -72057589742960896); - assert_eq!(r, transmute(lsx_vslt_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1210,7 +1493,13 @@ unsafe fn test_lsx_vslt_hu() { let b = u16x8::new(513, 13075, 20319, 44422, 12609, 18638, 20227, 21354); let r = i64x2::new(281474976645120, -281474976645121); - assert_eq!(r, transmute(lsx_vslt_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1219,7 +1508,13 @@ unsafe fn test_lsx_vslt_wu() { let b = u32x4::new(1402243125, 1129899238, 2591537060, 4152171743); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vslt_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1228,7 +1523,13 @@ unsafe fn test_lsx_vslt_du() { let b = u64x2::new(835355141719377733, 10472626544222695938); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslt_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vslt_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1238,7 +1539,7 @@ unsafe fn test_lsx_vslti_bu() { ); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_bu::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_bu::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1246,7 +1547,7 @@ unsafe fn test_lsx_vslti_hu() { let a = u16x8::new(60550, 12178, 30950, 44771, 25514, 35987, 55940, 21614); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_hu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_hu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1254,7 +1555,7 @@ unsafe fn test_lsx_vslti_wu() { let a = u32x4::new(912580668, 18660032, 3405726641, 4033549497); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_wu::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_wu::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1262,7 +1563,7 @@ unsafe fn test_lsx_vslti_du() { let a = u64x2::new(17196150830761730262, 5893061291971214149); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslti_du::<14>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslti_du::<14>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1275,7 +1576,10 @@ unsafe fn test_lsx_vsle_b() { ); let r = i64x2::new(281470681808895, 280375465148415); - assert_eq!(r, transmute(lsx_vsle_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1284,7 +1588,10 @@ unsafe fn test_lsx_vsle_h() { let b = i16x8::new(-30602, -9535, 10944, 3343, -1093, 6600, -19453, -4561); let r = i64x2::new(281470681743360, -281470681808896); - assert_eq!(r, transmute(lsx_vsle_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1293,7 +1600,10 @@ unsafe fn test_lsx_vsle_w() { let b = i32x4::new(-1810853975, 2021418524, 215198844, 1124361386); let r = i64x2::new(-4294967296, -4294967296); - assert_eq!(r, transmute(lsx_vsle_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1302,7 +1612,10 @@ unsafe fn test_lsx_vsle_d() { let b = i64x2::new(71694374951002423, -4307912969104303925); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vsle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1312,7 +1625,7 @@ unsafe fn test_lsx_vslei_b() { ); let r = i64x2::new(72056494526365440, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_b::<3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_b::<3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1320,7 +1633,7 @@ unsafe fn test_lsx_vslei_h() { let a = i16x8::new(31276, -16628, -30006, -20587, 2104, -30062, 18261, -6449); let r = i64x2::new(-65536, -281470681808896); - assert_eq!(r, transmute(lsx_vslei_h::<-3>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_h::<-3>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1328,7 +1641,7 @@ unsafe fn test_lsx_vslei_w() { let a = i32x4::new(-1890390435, 1289536678, 1490122113, 2120063492); let r = i64x2::new(4294967295, 0); - assert_eq!(r, transmute(lsx_vslei_w::<-16>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_w::<-16>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1336,7 +1649,7 @@ unsafe fn test_lsx_vslei_d() { let a = i64x2::new(-123539898448811963, 8007480165241051883); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vslei_d::<8>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_d::<8>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1349,7 +1662,13 @@ unsafe fn test_lsx_vsle_bu() { ); let r = i64x2::new(1095216660480, 72057594021150720); - assert_eq!(r, transmute(lsx_vsle_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1358,7 +1677,13 @@ unsafe fn test_lsx_vsle_hu() { let b = u16x8::new(50529, 35111, 24746, 62465, 21587, 30574, 11054, 11653); let r = i64x2::new(-4294967296, 281474976710655); - assert_eq!(r, transmute(lsx_vsle_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1367,7 +1692,13 @@ unsafe fn test_lsx_vsle_wu() { let b = u32x4::new(1321018603, 1091195011, 3525236625, 4061062671); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vsle_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1376,7 +1707,13 @@ unsafe fn test_lsx_vsle_du() { let b = u64x2::new(16044633718831874991, 3531311371811276914); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vsle_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsle_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1386,7 +1723,7 @@ unsafe fn test_lsx_vslei_bu() { ); let r = i64x2::new(71776119061217280, 280375465082880); - assert_eq!(r, transmute(lsx_vslei_bu::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_bu::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1394,7 +1731,7 @@ unsafe fn test_lsx_vslei_hu() { let a = u16x8::new(1430, 10053, 35528, 28458, 2394, 22098, 40236, 20853); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_hu::<10>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_hu::<10>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1402,7 +1739,7 @@ unsafe fn test_lsx_vslei_wu() { let a = u32x4::new(3289026584, 3653636092, 2919866047, 2895662832); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_wu::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_wu::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1410,7 +1747,7 @@ unsafe fn test_lsx_vslei_du() { let a = u64x2::new(17462377852989253439, 17741928456729041079); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vslei_du::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vslei_du::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1420,7 +1757,7 @@ unsafe fn test_lsx_vsat_b() { ); let r = i64x2::new(-2964542792447819074, 3186937137643144200); - assert_eq!(r, transmute(lsx_vsat_b::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_b::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1428,7 +1765,7 @@ unsafe fn test_lsx_vsat_h() { let a = i16x8::new(-22234, -8008, -23350, 13768, 26313, -27447, -3569, 6025); let r = i64x2::new(576451960371214336, 576451960371152895); - assert_eq!(r, transmute(lsx_vsat_h::<11>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_h::<11>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1436,7 +1773,7 @@ unsafe fn test_lsx_vsat_w() { let a = i32x4::new(-84179653, 874415975, 1823119516, 1667850968); let r = i64x2::new(137438953440, 133143986207); - assert_eq!(r, transmute(lsx_vsat_w::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_w::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1444,7 +1781,7 @@ unsafe fn test_lsx_vsat_d() { let a = i64x2::new(6859869867233872152, 2514172105675226457); let r = i64x2::new(262143, 262143); - assert_eq!(r, transmute(lsx_vsat_d::<18>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_d::<18>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1454,7 +1791,7 @@ unsafe fn test_lsx_vsat_bu() { ); let r = i64x2::new(2125538672170008439, 6577605268441825038); - assert_eq!(r, transmute(lsx_vsat_bu::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_bu::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1462,7 +1799,7 @@ unsafe fn test_lsx_vsat_hu() { let a = u16x8::new(36681, 34219, 6160, 8687, 4544, 20195, 35034, 916); let r = i64x2::new(287953294993589247, 257835472485549055); - assert_eq!(r, transmute(lsx_vsat_hu::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_hu::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1470,7 +1807,7 @@ unsafe fn test_lsx_vsat_wu() { let a = u32x4::new(1758000759, 4138051566, 2705324001, 3927640324); let r = i64x2::new(70364449226751, 70364449226751); - assert_eq!(r, transmute(lsx_vsat_wu::<13>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_wu::<13>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1478,7 +1815,7 @@ unsafe fn test_lsx_vsat_du() { let a = u64x2::new(1953136817312581670, 2606878300382729363); let r = i64x2::new(9007199254740991, 9007199254740991); - assert_eq!(r, transmute(lsx_vsat_du::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsat_du::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -1491,7 +1828,13 @@ unsafe fn test_lsx_vadda_b() { ); let r = i64x2::new(8248499858970022011, 8535863472581999270); - assert_eq!(r, transmute(lsx_vadda_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1500,7 +1843,13 @@ unsafe fn test_lsx_vadda_h() { let b = i16x8::new(-21543, 21720, 14529, -19143, -28953, 13450, 8037, 29413); let r = i64x2::new(-8646732423142600033, 8924050915627474398); - assert_eq!(r, transmute(lsx_vadda_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1509,7 +1858,13 @@ unsafe fn test_lsx_vadda_w() { let b = i32x4::new(287041349, 249467792, 312776520, 1314435078); let r = i64x2::new(8345875378983299469, 6092442344252138029); - assert_eq!(r, transmute(lsx_vadda_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1518,7 +1873,13 @@ unsafe fn test_lsx_vadda_d() { let b = i64x2::new(-4324432602362661920, 6402427893748093984); let r = i64x2::new(6071741662385212188, -5328622052402301597); - assert_eq!(r, transmute(lsx_vadda_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadda_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1531,7 +1892,13 @@ unsafe fn test_lsx_vsadd_b() { ); let r = i64x2::new(-3422653801050278697, 1909270979770548186); - assert_eq!(r, transmute(lsx_vsadd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1540,7 +1907,13 @@ unsafe fn test_lsx_vsadd_h() { let b = i16x8::new(26970, 17131, 15547, -7614, -8479, 22338, 3567, -22299); let r = i64x2::new(6720170624686097630, -304244782337649222); - assert_eq!(r, transmute(lsx_vsadd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1549,7 +1922,13 @@ unsafe fn test_lsx_vsadd_w() { let b = i32x4::new(-1026388582, 222487110, 501504960, -1863994162); let r = i64x2::new(-6565289918505943040, -6915373914453178024); - assert_eq!(r, transmute(lsx_vsadd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1558,7 +1937,13 @@ unsafe fn test_lsx_vsadd_d() { let b = i64x2::new(-6599608819082608284, -5088169537193133686); let r = i64x2::new(-8567396806692999839, -9223372036854775808); - assert_eq!(r, transmute(lsx_vsadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1571,7 +1956,13 @@ unsafe fn test_lsx_vsadd_bu() { ); let r = i64x2::new(-5404438145481572386, -7318352348905473); - assert_eq!(r, transmute(lsx_vsadd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1580,7 +1971,13 @@ unsafe fn test_lsx_vsadd_hu() { let b = u16x8::new(31219, 59227, 25607, 62798, 18845, 3238, 19902, 24978); let r = i64x2::new(-8740258447361, -136834913009665); - assert_eq!(r, transmute(lsx_vsadd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1589,7 +1986,13 @@ unsafe fn test_lsx_vsadd_wu() { let b = u32x4::new(3676524021, 3894343575, 904432536, 1616820031); let r = i64x2::new(-1, -7583652642497232897); - assert_eq!(r, transmute(lsx_vsadd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1598,7 +2001,13 @@ unsafe fn test_lsx_vsadd_du() { let b = u64x2::new(11054638512585704882, 3549000132135395099); let r = i64x2::new(-3651327027786652925, -623479558932885349); - assert_eq!(r, transmute(lsx_vsadd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsadd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1611,7 +2020,10 @@ unsafe fn test_lsx_vavg_b() { ); let r = i64x2::new(-152206416164856247, 4369276355735447089); - assert_eq!(r, transmute(lsx_vavg_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1620,7 +2032,10 @@ unsafe fn test_lsx_vavg_h() { let b = i16x8::new(-3088, -25854, -32552, -8417, 7808, -12495, 22032, -5168); let r = i64x2::new(696836182083297626, -4337760619710117321); - assert_eq!(r, transmute(lsx_vavg_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1629,7 +2044,10 @@ unsafe fn test_lsx_vavg_w() { let b = i32x4::new(-324844828, -1580060766, -1909832882, 328273785); let r = i64x2::new(475428188150908257, 4521676108535152711); - assert_eq!(r, transmute(lsx_vavg_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1638,7 +2056,10 @@ unsafe fn test_lsx_vavg_d() { let b = i64x2::new(3169904420607189220, 5159962511251707672); let r = i64x2::new(2328313764472338215, 5669256157716045974); - assert_eq!(r, transmute(lsx_vavg_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1651,7 +2072,13 @@ unsafe fn test_lsx_vavg_bu() { ); let r = i64x2::new(-5663745084945885565, 2801126043194071837); - assert_eq!(r, transmute(lsx_vavg_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1660,7 +2087,13 @@ unsafe fn test_lsx_vavg_hu() { let b = u16x8::new(44835, 36733, 12115, 42874, 4819, 12201, 27397, 25394); let r = i64x2::new(-4196978047981735086, -6439149718662907396); - assert_eq!(r, transmute(lsx_vavg_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1669,7 +2102,13 @@ unsafe fn test_lsx_vavg_wu() { let b = u32x4::new(160886383, 26081142, 459122380, 2523086630); let r = i64x2::new(123816739188229069, -5586965600173345916); - assert_eq!(r, transmute(lsx_vavg_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1678,7 +2117,13 @@ unsafe fn test_lsx_vavg_du() { let b = u64x2::new(9749063966076740681, 5963120178993456389); let r = i64x2::new(-7770235857859936532, 7939635441364553211); - assert_eq!(r, transmute(lsx_vavg_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavg_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1691,7 +2136,13 @@ unsafe fn test_lsx_vavgr_b() { ); let r = i64x2::new(1883712581662731545, -1226681417271426582); - assert_eq!(r, transmute(lsx_vavgr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1700,7 +2151,13 @@ unsafe fn test_lsx_vavgr_h() { let b = i16x8::new(-9758, -8332, 20577, 31066, 31120, 14788, -22323, 16722); let r = i64x2::new(3801916629507170613, 3994084079587580569); - assert_eq!(r, transmute(lsx_vavgr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1709,7 +2166,13 @@ unsafe fn test_lsx_vavgr_w() { let b = i32x4::new(1278058715, -155858446, -195547847, -750518746); let r = i64x2::new(4040594005688324125, -5795079921582298726); - assert_eq!(r, transmute(lsx_vavgr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1718,7 +2181,13 @@ unsafe fn test_lsx_vavgr_d() { let b = i64x2::new(8758126674980055299, -7441643514470614533); let r = i64x2::new(3399991646978312393, -1904131665097658207); - assert_eq!(r, transmute(lsx_vavgr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1731,7 +2200,13 @@ unsafe fn test_lsx_vavgr_bu() { ); let r = i64x2::new(9122444831751176042, 6010164553039771699); - assert_eq!(r, transmute(lsx_vavgr_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1740,7 +2215,13 @@ unsafe fn test_lsx_vavgr_hu() { let b = u16x8::new(26111, 34713, 61420, 23702, 29204, 9543, 62786, 7043); let r = i64x2::new(7022187818705851223, 4754859411904311722); - assert_eq!(r, transmute(lsx_vavgr_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1749,7 +2230,13 @@ unsafe fn test_lsx_vavgr_wu() { let b = u32x4::new(1930150361, 3668628165, 2983921396, 2410913126); let r = i64x2::new(-5401180487351753235, 8140240017388800980); - assert_eq!(r, transmute(lsx_vavgr_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1758,7 +2245,13 @@ unsafe fn test_lsx_vavgr_du() { let b = u64x2::new(8650759135311802962, 11380630663742852932); let r = i64x2::new(6046550632940509412, 8095423581736830430); - assert_eq!(r, transmute(lsx_vavgr_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vavgr_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1771,7 +2264,13 @@ unsafe fn test_lsx_vssub_b() { ); let r = i64x2::new(628822736562549631, -9187601072510296593); - assert_eq!(r, transmute(lsx_vssub_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1780,7 +2279,13 @@ unsafe fn test_lsx_vssub_h() { let b = i16x8::new(-26027, 6118, -13204, 25080, 12458, 8441, 24701, 11617); let r = i64x2::new(-9223231300041015297, 1942699741282756937); - assert_eq!(r, transmute(lsx_vssub_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1789,7 +2294,13 @@ unsafe fn test_lsx_vssub_w() { let b = i32x4::new(-1808829767, 2144666490, 146236682, 1180114488); let r = i64x2::new(-9223372035405031217, -177933965588659662); - assert_eq!(r, transmute(lsx_vssub_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1798,7 +2309,13 @@ unsafe fn test_lsx_vssub_d() { let b = i64x2::new(-2293337525465880409, 5736255249834646932); let r = i64x2::new(2921430482628531027, -4208815595153969049); - assert_eq!(r, transmute(lsx_vssub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1811,7 +2328,13 @@ unsafe fn test_lsx_vssub_bu() { ); let r = i64x2::new(1441151919413273782, 87960930222283); - assert_eq!(r, transmute(lsx_vssub_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1820,7 +2343,13 @@ unsafe fn test_lsx_vssub_hu() { let b = u16x8::new(50468, 33060, 15257, 59071, 59343, 21993, 42978, 20097); let r = i64x2::new(902801202201243247, -7922957643493867520); - assert_eq!(r, transmute(lsx_vssub_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1829,7 +2358,13 @@ unsafe fn test_lsx_vssub_wu() { let b = u32x4::new(31483972, 3489479082, 152079374, 1875131600); let r = i64x2::new(66202020638834260, 1378022115978010238); - assert_eq!(r, transmute(lsx_vssub_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1838,7 +2373,13 @@ unsafe fn test_lsx_vssub_du() { let b = u64x2::new(6460869225596371206, 16765308520486969885); let r = i64x2::new(8426906920692365065, 0); - assert_eq!(r, transmute(lsx_vssub_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssub_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1851,7 +2392,13 @@ unsafe fn test_lsx_vabsd_b() { ); let r = i64x2::new(4230359294854509733, 2116586434120326452); - assert_eq!(r, transmute(lsx_vabsd_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1860,7 +2407,13 @@ unsafe fn test_lsx_vabsd_h() { let b = i16x8::new(9346, 27961, 21592, 10762, -6831, 17219, 14968, -1750); let r = i64x2::new(4018377481144584593, 2994052849949411737); - assert_eq!(r, transmute(lsx_vabsd_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1869,7 +2422,13 @@ unsafe fn test_lsx_vabsd_w() { let b = i32x4::new(-638463360, -1154268425, 818053243, -1766966029); let r = i64x2::new(4346218292750542585, 1613133471209364690); - assert_eq!(r, transmute(lsx_vabsd_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1878,7 +2437,13 @@ unsafe fn test_lsx_vabsd_d() { let b = i64x2::new(-8533946706796471089, 1165272962517390961); let r = i64x2::new(7188249046367538699, 8146605509049538382); - assert_eq!(r, transmute(lsx_vabsd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1891,7 +2456,13 @@ unsafe fn test_lsx_vabsd_bu() { ); let r = i64x2::new(2316568964225934796, 5350198762417854927); - assert_eq!(r, transmute(lsx_vabsd_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1900,7 +2471,13 @@ unsafe fn test_lsx_vabsd_hu() { let b = u16x8::new(42102, 40052, 6807, 16289, 29686, 38061, 42843, 26642); let r = i64x2::new(-6889746235852116468, 1175584127230950722); - assert_eq!(r, transmute(lsx_vabsd_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1909,7 +2486,13 @@ unsafe fn test_lsx_vabsd_wu() { let b = u32x4::new(3008439409, 976530727, 1726048801, 4235308512); let r = i64x2::new(-5056055741505581388, 103751774096297765); - assert_eq!(r, transmute(lsx_vabsd_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1918,7 +2501,13 @@ unsafe fn test_lsx_vabsd_du() { let b = u64x2::new(305704565845198935, 18327726360649467511); let r = i64x2::new(-4540227154002526968, -1590034053554043722); - assert_eq!(r, transmute(lsx_vabsd_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vabsd_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -1931,7 +2520,10 @@ unsafe fn test_lsx_vmul_b() { ); let r = i64x2::new(-836412611799730432, -7959044669412588992); - assert_eq!(r, transmute(lsx_vmul_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1940,7 +2532,10 @@ unsafe fn test_lsx_vmul_h() { let b = i16x8::new(-18582, -25667, 17674, 8424, -17121, -21798, 28934, -353); let r = i64x2::new(-7419436171490628650, 3947512047518358605); - assert_eq!(r, transmute(lsx_vmul_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1949,7 +2544,10 @@ unsafe fn test_lsx_vmul_w() { let b = i32x4::new(1754730718, 782084571, 894216679, -1895747372); let r = i64x2::new(6602438528086061106, 4680306660704041039); - assert_eq!(r, transmute(lsx_vmul_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1958,7 +2556,10 @@ unsafe fn test_lsx_vmul_d() { let b = i64x2::new(8096709215426138432, -5454415917204378153); let r = i64x2::new(-1062747544199352000, -649255846668983579); - assert_eq!(r, transmute(lsx_vmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmul_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -1976,7 +2577,11 @@ unsafe fn test_lsx_vmadd_b() { assert_eq!( r, - transmute(lsx_vmadd_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -1989,7 +2594,11 @@ unsafe fn test_lsx_vmadd_h() { assert_eq!( r, - transmute(lsx_vmadd_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2002,7 +2611,11 @@ unsafe fn test_lsx_vmadd_w() { assert_eq!( r, - transmute(lsx_vmadd_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2015,7 +2628,11 @@ unsafe fn test_lsx_vmadd_d() { assert_eq!( r, - transmute(lsx_vmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2034,7 +2651,11 @@ unsafe fn test_lsx_vmsub_b() { assert_eq!( r, - transmute(lsx_vmsub_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2047,7 +2668,11 @@ unsafe fn test_lsx_vmsub_h() { assert_eq!( r, - transmute(lsx_vmsub_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2060,7 +2685,11 @@ unsafe fn test_lsx_vmsub_w() { assert_eq!( r, - transmute(lsx_vmsub_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2073,7 +2702,11 @@ unsafe fn test_lsx_vmsub_d() { assert_eq!( r, - transmute(lsx_vmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2087,7 +2720,10 @@ unsafe fn test_lsx_vdiv_b() { ); let r = i64x2::new(720575944674246657, 281475060530176); - assert_eq!(r, transmute(lsx_vdiv_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2096,7 +2732,10 @@ unsafe fn test_lsx_vdiv_h() { let b = i16x8::new(-11221, 24673, 19931, 3799, -3251, -21373, -13758, -31286); let r = i64x2::new(-1125904201744385, 281470681743353); - assert_eq!(r, transmute(lsx_vdiv_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2105,7 +2744,10 @@ unsafe fn test_lsx_vdiv_w() { let b = i32x4::new(-775731190, 1887886939, 1001718213, 1135075421); let r = i64x2::new(4294967295, 4294967297); - assert_eq!(r, transmute(lsx_vdiv_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2114,7 +2756,10 @@ unsafe fn test_lsx_vdiv_d() { let b = i64x2::new(-9175012156877545557, -6390704898809702209); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2127,7 +2772,13 @@ unsafe fn test_lsx_vdiv_bu() { ); let r = i64x2::new(261, 72058702139687425); - assert_eq!(r, transmute(lsx_vdiv_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2136,7 +2787,13 @@ unsafe fn test_lsx_vdiv_hu() { let b = u16x8::new(25282, 44917, 13706, 63351, 58837, 46710, 29092, 57823); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vdiv_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2145,7 +2802,13 @@ unsafe fn test_lsx_vdiv_wu() { let b = u32x4::new(1130189258, 1211056894, 2357258312, 3855913706); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vdiv_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2154,7 +2817,13 @@ unsafe fn test_lsx_vdiv_du() { let b = u64x2::new(14945948123666054968, 10864054932328247404); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vdiv_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vdiv_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2167,7 +2836,13 @@ unsafe fn test_lsx_vhaddw_h_b() { ); let r = i64x2::new(13791943145684950, -562821104926904); - assert_eq!(r, transmute(lsx_vhaddw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2178,7 +2853,13 @@ unsafe fn test_lsx_vhaddw_w_h() { ); let r = i64x2::new(56307021213062, 183021441324639); - assert_eq!(r, transmute(lsx_vhaddw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2187,7 +2868,13 @@ unsafe fn test_lsx_vhaddw_d_w() { let b = i32x4::new(-1119468785, -1334232049, -1752131604, -2016112631); let r = i64x2::new(-2502031305, -1217615295); - assert_eq!(r, transmute(lsx_vhaddw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2200,7 +2887,13 @@ unsafe fn test_lsx_vhaddw_hu_bu() { ); let r = i64x2::new(45601115212087520, 21110838012870921); - assert_eq!(r, transmute(lsx_vhaddw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2209,7 +2902,13 @@ unsafe fn test_lsx_vhaddw_wu_hu() { let b = u16x8::new(40369, 53005, 64424, 35720, 9231, 19965, 20662, 8208); let r = i64x2::new(411432097222434, 312888367535410); - assert_eq!(r, transmute(lsx_vhaddw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2218,7 +2917,13 @@ unsafe fn test_lsx_vhaddw_du_wu() { let b = u32x4::new(728838120, 1267673009, 2659634151, 2264611356); let r = i64x2::new(4172122985, 4839922613); - assert_eq!(r, transmute(lsx_vhaddw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2231,7 +2936,13 @@ unsafe fn test_lsx_vhsubw_h_b() { ); let r = i64x2::new(-4503363402989617, -31243430355664844); - assert_eq!(r, transmute(lsx_vhsubw_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2240,7 +2951,13 @@ unsafe fn test_lsx_vhsubw_w_h() { let b = i16x8::new(-14204, -13312, 8240, -4455, -6362, -4711, -30790, -15773); let r = i64x2::new(70059506530916, 60275571046613); - assert_eq!(r, transmute(lsx_vhsubw_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2249,7 +2966,13 @@ unsafe fn test_lsx_vhsubw_d_w() { let b = i32x4::new(-1671723008, 870456702, 264823818, 13322401); let r = i64x2::new(-201438605, 449141316); - assert_eq!(r, transmute(lsx_vhsubw_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2262,7 +2985,13 @@ unsafe fn test_lsx_vhsubw_hu_bu() { ); let r = i64x2::new(-62206416523952172, 42783380429340790); - assert_eq!(r, transmute(lsx_vhsubw_hu_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_hu_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2271,7 +3000,13 @@ unsafe fn test_lsx_vhsubw_wu_hu() { let b = u16x8::new(5212, 32159, 36502, 59290, 7604, 229, 35511, 47443); let r = i64x2::new(24696062008394, -147484881944276); - assert_eq!(r, transmute(lsx_vhsubw_wu_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_wu_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2280,7 +3015,13 @@ unsafe fn test_lsx_vhsubw_du_wu() { let b = u32x4::new(1383087137, 2403951939, 360532131, 3513614550); let r = i64x2::new(-601935499, 31776736); - assert_eq!(r, transmute(lsx_vhsubw_du_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_du_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2293,7 +3034,10 @@ unsafe fn test_lsx_vmod_b() { ); let r = i64x2::new(2804691417388804007, -2461515231199824166); - assert_eq!(r, transmute(lsx_vmod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2302,7 +3046,10 @@ unsafe fn test_lsx_vmod_h() { let b = i16x8::new(1550, 9221, -12080, 14553, -24847, 28286, 1074, 192); let r = i64x2::new(3930282117007147005, -10982007906888970); - assert_eq!(r, transmute(lsx_vmod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2311,7 +3058,10 @@ unsafe fn test_lsx_vmod_w() { let b = i32x4::new(344507881, 1692387020, -1397506903, -1257953510); let r = i64x2::new(-5027973877095011085, 2553570821342119010); - assert_eq!(r, transmute(lsx_vmod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2320,7 +3070,10 @@ unsafe fn test_lsx_vmod_d() { let b = i64x2::new(4636642606889723746, -259899475747531088); let r = i64x2::new(-1381676014874400835, -257849503742906530); - assert_eq!(r, transmute(lsx_vmod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2333,7 +3086,13 @@ unsafe fn test_lsx_vmod_bu() { ); let r = i64x2::new(7287961163701724026, 4745974892933063220); - assert_eq!(r, transmute(lsx_vmod_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2342,7 +3101,13 @@ unsafe fn test_lsx_vmod_hu() { let b = u16x8::new(15317, 24954, 61354, 3720, 21471, 6193, 8193, 35745); let r = i64x2::new(315403234587388856, 7101062794264266609); - assert_eq!(r, transmute(lsx_vmod_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2351,7 +3116,13 @@ unsafe fn test_lsx_vmod_wu() { let b = u32x4::new(49228057, 2249712923, 358897384, 1782599598); let r = i64x2::new(1070413902953059662, 3340025749258890964); - assert_eq!(r, transmute(lsx_vmod_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2360,7 +3131,13 @@ unsafe fn test_lsx_vmod_du() { let b = u64x2::new(16850073055169051895, 16069565262862467484); let r = i64x2::new(7747010922784437137, 20234676239478699); - assert_eq!(r, transmute(lsx_vmod_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmod_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2370,7 +3147,7 @@ unsafe fn test_lsx_vreplve_b() { ); let r = i64x2::new(-2893606913523066921, -2893606913523066921); - assert_eq!(r, transmute(lsx_vreplve_b(transmute(a), -8))); + assert_eq!(r, transmute(lsx_vreplve_b(black_box(transmute(a)), -8))); } #[simd_test(enable = "lsx")] @@ -2378,7 +3155,7 @@ unsafe fn test_lsx_vreplve_h() { let a = i16x8::new(-29429, -23495, 8705, -7614, -25353, 11887, -25989, -12818); let r = i64x2::new(-3607719825936298514, -3607719825936298514); - assert_eq!(r, transmute(lsx_vreplve_h(transmute(a), 7))); + assert_eq!(r, transmute(lsx_vreplve_h(black_box(transmute(a)), 7))); } #[simd_test(enable = "lsx")] @@ -2386,7 +3163,7 @@ unsafe fn test_lsx_vreplve_w() { let a = i32x4::new(1584940676, 95787593, -1655264847, 682404402); let r = i64x2::new(411404579393346121, 411404579393346121); - assert_eq!(r, transmute(lsx_vreplve_w(transmute(a), -3))); + assert_eq!(r, transmute(lsx_vreplve_w(black_box(transmute(a)), -3))); } #[simd_test(enable = "lsx")] @@ -2394,7 +3171,7 @@ unsafe fn test_lsx_vreplve_d() { let a = i64x2::new(7614424214598615675, -7096892795239148002); let r = i64x2::new(7614424214598615675, 7614424214598615675); - assert_eq!(r, transmute(lsx_vreplve_d(transmute(a), 0))); + assert_eq!(r, transmute(lsx_vreplve_d(black_box(transmute(a)), 0))); } #[simd_test(enable = "lsx")] @@ -2404,7 +3181,7 @@ unsafe fn test_lsx_vreplvei_b() { ); let r = i64x2::new(-2097865012304223518, -2097865012304223518); - assert_eq!(r, transmute(lsx_vreplvei_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2412,7 +3189,7 @@ unsafe fn test_lsx_vreplvei_h() { let a = i16x8::new(-15455, -4410, 5029, 25863, -23170, 26570, 27423, -834); let r = i64x2::new(7719006069021698847, 7719006069021698847); - assert_eq!(r, transmute(lsx_vreplvei_h::<6>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_h::<6>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2420,7 +3197,7 @@ unsafe fn test_lsx_vreplvei_w() { let a = i32x4::new(1843143434, 491125746, -328585251, -1996512058); let r = i64x2::new(7916240772710277898, 7916240772710277898); - assert_eq!(r, transmute(lsx_vreplvei_w::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_w::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2428,7 +3205,7 @@ unsafe fn test_lsx_vreplvei_d() { let a = i64x2::new(4333963848299154309, -8310246545782080694); let r = i64x2::new(-8310246545782080694, -8310246545782080694); - assert_eq!(r, transmute(lsx_vreplvei_d::<1>(transmute(a)))); + assert_eq!(r, transmute(lsx_vreplvei_d::<1>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2441,7 +3218,13 @@ unsafe fn test_lsx_vpickev_b() { ); let r = i64x2::new(3921750152141124833, -933322373843017127); - assert_eq!(r, transmute(lsx_vpickev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2450,7 +3233,13 @@ unsafe fn test_lsx_vpickev_h() { let b = i16x8::new(-5248, -1786, -21768, 23214, -4223, 23538, -24936, -32316); let r = i64x2::new(-7018596679058658432, 139073165196191894); - assert_eq!(r, transmute(lsx_vpickev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2459,7 +3248,13 @@ unsafe fn test_lsx_vpickev_w() { let b = i32x4::new(-1187277846, -787064901, -980229113, 1746235326); let r = i64x2::new(-4210051979814398998, -769258006856513132); - assert_eq!(r, transmute(lsx_vpickev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2468,7 +3263,13 @@ unsafe fn test_lsx_vpickev_d() { let b = i64x2::new(6574352346370076190, -3979792156310826694); let r = i64x2::new(6574352346370076190, 1789073368466131160); - assert_eq!(r, transmute(lsx_vpickev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2481,7 +3282,13 @@ unsafe fn test_lsx_vpickod_b() { ); let r = i64x2::new(8220640377280882872, -6083110277645985532); - assert_eq!(r, transmute(lsx_vpickod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2490,7 +3297,13 @@ unsafe fn test_lsx_vpickod_h() { let b = i16x8::new(12047, 25024, -10709, -28077, 24357, 19934, 10289, 28546); let r = i64x2::new(8035070303515402688, 6167254016163165900); - assert_eq!(r, transmute(lsx_vpickod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2499,7 +3312,13 @@ unsafe fn test_lsx_vpickod_w() { let b = i32x4::new(-99240403, 314407358, 543396756, 1976776696); let r = i64x2::new(8490191261129341374, -7045044594236590438); - assert_eq!(r, transmute(lsx_vpickod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2508,7 +3327,13 @@ unsafe fn test_lsx_vpickod_d() { let b = i64x2::new(-4197243771252175958, -543692393753629390); let r = i64x2::new(-543692393753629390, -7578696032343374601); - assert_eq!(r, transmute(lsx_vpickod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpickod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2521,7 +3346,13 @@ unsafe fn test_lsx_vilvh_b() { ); let r = i64x2::new(1211180715666052671, -2634368371891034045); - assert_eq!(r, transmute(lsx_vilvh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2530,7 +3361,13 @@ unsafe fn test_lsx_vilvh_h() { let b = i16x8::new(23768, -31845, 28689, 14757, 9499, 7795, -13573, -10011); let r = i64x2::new(-4714953853167983333, 4564918175499275003); - assert_eq!(r, transmute(lsx_vilvh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2539,7 +3376,13 @@ unsafe fn test_lsx_vilvh_w() { let b = i32x4::new(-737076987, 38515006, 602108871, -63099569); let r = i64x2::new(-5365723764939852857, -1200522227779556017); - assert_eq!(r, transmute(lsx_vilvh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2548,7 +3391,13 @@ unsafe fn test_lsx_vilvh_d() { let b = i64x2::new(-2160658667838026389, 1449429407527660400); let r = i64x2::new(1449429407527660400, 5375050218784453679); - assert_eq!(r, transmute(lsx_vilvh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvh_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2561,7 +3410,13 @@ unsafe fn test_lsx_vilvl_b() { ); let r = i64x2::new(6945744258789947856, 8515979671552484861); - assert_eq!(r, transmute(lsx_vilvl_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2570,7 +3425,13 @@ unsafe fn test_lsx_vilvl_h() { let b = i16x8::new(11601, 6788, 3174, -4208, -25999, -25660, -4591, 7133); let r = i64x2::new(-6560589601043632815, -2260825085889541018); - assert_eq!(r, transmute(lsx_vilvl_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2579,7 +3440,13 @@ unsafe fn test_lsx_vilvl_w() { let b = i32x4::new(486029703, 1245981961, 112180197, 1939621508); let r = i64x2::new(-4282490222245561977, 7435326725564935433); - assert_eq!(r, transmute(lsx_vilvl_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2588,7 +3455,13 @@ unsafe fn test_lsx_vilvl_d() { let b = i64x2::new(3142531875873363679, 736682102982019415); let r = i64x2::new(3142531875873363679, 7063413230460842607); - assert_eq!(r, transmute(lsx_vilvl_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vilvl_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2601,7 +3474,13 @@ unsafe fn test_lsx_vpackev_b() { ); let r = i64x2::new(-1928363389519380677, -1882898104368665381); - assert_eq!(r, transmute(lsx_vpackev_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2610,7 +3489,13 @@ unsafe fn test_lsx_vpackev_h() { let b = i16x8::new(-9444, 5210, -14402, 17972, 16606, 2450, 5123, 14727); let r = i64x2::new(7533052947329899292, 1461440082551914718); - assert_eq!(r, transmute(lsx_vpackev_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2619,7 +3504,13 @@ unsafe fn test_lsx_vpackev_w() { let b = i32x4::new(-872903277, 1255047449, -2110158279, 682925573); let r = i64x2::new(5636997704425442707, -8345976908349339079); - assert_eq!(r, transmute(lsx_vpackev_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2628,7 +3519,13 @@ unsafe fn test_lsx_vpackev_d() { let b = i64x2::new(-9119315954224042738, -4563700463464702181); let r = i64x2::new(-9119315954224042738, 7118943335298607169); - assert_eq!(r, transmute(lsx_vpackev_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackev_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2641,7 +3538,13 @@ unsafe fn test_lsx_vpackod_b() { ); let r = i64x2::new(4389351353151377653, -4315624792288929032); - assert_eq!(r, transmute(lsx_vpackod_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2650,7 +3553,13 @@ unsafe fn test_lsx_vpackod_h() { let b = i16x8::new(-23247, 17928, -13353, -20146, 5696, 22071, -10728, -30262); let r = i64x2::new(-4433598883325590008, -9178747487946648009); - assert_eq!(r, transmute(lsx_vpackod_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2659,7 +3568,13 @@ unsafe fn test_lsx_vpackod_w() { let b = i32x4::new(445270781, 793617340, -1461557030, -22199234); let r = i64x2::new(51238874735551420, 6731566319615689790); - assert_eq!(r, transmute(lsx_vpackod_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2668,7 +3583,13 @@ unsafe fn test_lsx_vpackod_d() { let b = i64x2::new(9039771682296134623, -6404442538060227683); let r = i64x2::new(-6404442538060227683, -4670773907187480618); - assert_eq!(r, transmute(lsx_vpackod_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vpackod_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -2680,7 +3601,11 @@ unsafe fn test_lsx_vshuf_h() { assert_eq!( r, - transmute(lsx_vshuf_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2693,7 +3618,11 @@ unsafe fn test_lsx_vshuf_w() { assert_eq!( r, - transmute(lsx_vshuf_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2706,7 +3635,11 @@ unsafe fn test_lsx_vshuf_d() { assert_eq!( r, - transmute(lsx_vshuf_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2720,7 +3653,10 @@ unsafe fn test_lsx_vand_v() { ); let r = i64x2::new(244105884219744360, -9223116804091473582); - assert_eq!(r, transmute(lsx_vand_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vand_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2730,7 +3666,7 @@ unsafe fn test_lsx_vandi_b() { ); let r = i64x2::new(-8135737750142058361, -7666517314596397435); - assert_eq!(r, transmute(lsx_vandi_b::<159>(transmute(a)))); + assert_eq!(r, transmute(lsx_vandi_b::<159>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2743,7 +3679,10 @@ unsafe fn test_lsx_vor_v() { ); let r = i64x2::new(-2351582766212852737, -4924766118269159990); - assert_eq!(r, transmute(lsx_vor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2753,7 +3692,7 @@ unsafe fn test_lsx_vori_b() { ); let r = i64x2::new(-589140355308650538, -3179554720060804109); - assert_eq!(r, transmute(lsx_vori_b::<210>(transmute(a)))); + assert_eq!(r, transmute(lsx_vori_b::<210>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2766,7 +3705,10 @@ unsafe fn test_lsx_vnor_v() { ); let r = i64x2::new(3036560889408918025, 7823034030269427744); - assert_eq!(r, transmute(lsx_vnor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vnor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2776,7 +3718,7 @@ unsafe fn test_lsx_vnori_b() { ); let r = i64x2::new(5227628601268782144, 596802560304890884); - assert_eq!(r, transmute(lsx_vnori_b::<51>(transmute(a)))); + assert_eq!(r, transmute(lsx_vnori_b::<51>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2789,7 +3731,10 @@ unsafe fn test_lsx_vxor_v() { ); let r = i64x2::new(8732028225622312747, 6858262329367852470); - assert_eq!(r, transmute(lsx_vxor_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vxor_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -2799,7 +3744,7 @@ unsafe fn test_lsx_vxori_b() { ); let r = i64x2::new(3478586993001400570, 4687744515358339026); - assert_eq!(r, transmute(lsx_vxori_b::<225>(transmute(a)))); + assert_eq!(r, transmute(lsx_vxori_b::<225>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2817,7 +3762,11 @@ unsafe fn test_lsx_vbitsel_v() { assert_eq!( r, - transmute(lsx_vbitsel_v(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vbitsel_v( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -2833,7 +3782,10 @@ unsafe fn test_lsx_vbitseli_b() { assert_eq!( r, - transmute(lsx_vbitseli_b::<65>(transmute(a), transmute(b))) + transmute(lsx_vbitseli_b::<65>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -2844,7 +3796,7 @@ unsafe fn test_lsx_vshuf4i_b() { ); let r = i64x2::new(3937170420478429898, -3347145886530736916); - assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_b::<234>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2852,7 +3804,7 @@ unsafe fn test_lsx_vshuf4i_h() { let a = i16x8::new(27707, -1094, -15784, -28387, 31634, -12323, -30387, -11480); let r = i64x2::new(-7989953385787032646, -3231104182470389795); - assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_h::<209>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2860,35 +3812,38 @@ unsafe fn test_lsx_vshuf4i_w() { let a = i32x4::new(768986805, -1036149600, -1196682940, -214444511); let r = i64x2::new(3302773179299516085, -5139714087882845884); - assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(transmute(a)))); + assert_eq!(r, transmute(lsx_vshuf4i_w::<160>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_b() { let r = i64x2::new(795741901218843403, 795741901218843403); - assert_eq!(r, transmute(lsx_vreplgr2vr_b(970839819))); + assert_eq!(r, transmute(lsx_vreplgr2vr_b(black_box(970839819)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_h() { let r = i64x2::new(-6504141532176800324, -6504141532176800324); - assert_eq!(r, transmute(lsx_vreplgr2vr_h(93693372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_h(black_box(93693372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_w() { let r = i64x2::new(-6737078705572473188, -6737078705572473188); - assert_eq!(r, transmute(lsx_vreplgr2vr_w(-1568598372))); + assert_eq!(r, transmute(lsx_vreplgr2vr_w(black_box(-1568598372)))); } #[simd_test(enable = "lsx")] unsafe fn test_lsx_vreplgr2vr_d() { let r = i64x2::new(5000134708087557572, 5000134708087557572); - assert_eq!(r, transmute(lsx_vreplgr2vr_d(5000134708087557572))); + assert_eq!( + r, + transmute(lsx_vreplgr2vr_d(black_box(5000134708087557572))) + ); } #[simd_test(enable = "lsx")] @@ -2898,7 +3853,7 @@ unsafe fn test_lsx_vpcnt_b() { ); let r = i64x2::new(217867142450840068, 145528077781566722); - assert_eq!(r, transmute(lsx_vpcnt_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2906,7 +3861,7 @@ unsafe fn test_lsx_vpcnt_h() { let a = i16x8::new(-512, 10388, -21267, -27094, 1085, -26444, -29360, -11576); let r = i64x2::new(1970367786975239, 1970350607237126); - assert_eq!(r, transmute(lsx_vpcnt_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2914,7 +3869,7 @@ unsafe fn test_lsx_vpcnt_w() { let a = i32x4::new(1399276601, -2094725994, -100739325, -1239551533); let r = i64x2::new(47244640271, 81604378645); - assert_eq!(r, transmute(lsx_vpcnt_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2922,7 +3877,7 @@ unsafe fn test_lsx_vpcnt_d() { let a = i64x2::new(-4470823169399930539, 3184270543884128372); let r = i64x2::new(29, 25); - assert_eq!(r, transmute(lsx_vpcnt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vpcnt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2932,7 +3887,7 @@ unsafe fn test_lsx_vclo_b() { ); let r = i64x2::new(72057594071547904, 3311470116864); - assert_eq!(r, transmute(lsx_vclo_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2940,7 +3895,7 @@ unsafe fn test_lsx_vclo_h() { let a = i16x8::new(-5432, 27872, -9150, 27393, 25236, 1028, -21312, -25189); let r = i64x2::new(8589934595, 281479271677952); - assert_eq!(r, transmute(lsx_vclo_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2948,7 +3903,7 @@ unsafe fn test_lsx_vclo_w() { let a = i32x4::new(1214322611, -1755838761, -1222326743, -1511364419); let r = i64x2::new(4294967296, 4294967297); - assert_eq!(r, transmute(lsx_vclo_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2956,7 +3911,7 @@ unsafe fn test_lsx_vclo_d() { let a = i64x2::new(-249299854527467825, -459308653408461862); let r = i64x2::new(6, 5); - assert_eq!(r, transmute(lsx_vclo_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclo_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2966,7 +3921,7 @@ unsafe fn test_lsx_vclz_b() { ); let r = i64x2::new(144116287587483648, 72903118479688195); - assert_eq!(r, transmute(lsx_vclz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2974,7 +3929,7 @@ unsafe fn test_lsx_vclz_h() { let a = i16x8::new(1222, 32426, 3164, -10763, 10189, -4197, -21841, -28676); let r = i64x2::new(17179934725, 2); - assert_eq!(r, transmute(lsx_vclz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2982,7 +3937,7 @@ unsafe fn test_lsx_vclz_w() { let a = i32x4::new(-490443689, -1039971379, -217310592, -1921086575); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vclz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -2990,7 +3945,7 @@ unsafe fn test_lsx_vclz_d() { let a = i64x2::new(4630351532137644314, -6587611980764816064); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vclz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vclz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3000,7 +3955,10 @@ unsafe fn test_lsx_vpickve2gr_b() { ); let r: i32 = 51; - assert_eq!(r, transmute(lsx_vpickve2gr_b::<15>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_b::<15>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3008,7 +3966,7 @@ unsafe fn test_lsx_vpickve2gr_h() { let a = i16x8::new(-12924, 31013, 18171, 20404, 21226, 14128, -6255, 26521); let r: i32 = 21226; - assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_h::<4>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3016,7 +3974,7 @@ unsafe fn test_lsx_vpickve2gr_w() { let a = i32x4::new(-1559379275, 2065542381, -1882161334, 1502157419); let r: i32 = -1882161334; - assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3024,7 +3982,7 @@ unsafe fn test_lsx_vpickve2gr_d() { let a = i64x2::new(-6941380853339482104, 8405634758774935528); let r: i64 = -6941380853339482104; - assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(transmute(a)))); + assert_eq!(r, transmute(lsx_vpickve2gr_d::<0>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3034,7 +3992,10 @@ unsafe fn test_lsx_vpickve2gr_bu() { ); let r: u32 = 199; - assert_eq!(r, transmute(lsx_vpickve2gr_bu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_bu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3042,7 +4003,10 @@ unsafe fn test_lsx_vpickve2gr_hu() { let a = i16x8::new(25003, 5139, -12977, 7550, -12177, 19294, -2216, 12693); let r: u32 = 25003; - assert_eq!(r, transmute(lsx_vpickve2gr_hu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_hu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3050,7 +4014,10 @@ unsafe fn test_lsx_vpickve2gr_wu() { let a = i32x4::new(-295894883, 551663550, -710853968, 82692774); let r: u32 = 3999072413; - assert_eq!(r, transmute(lsx_vpickve2gr_wu::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_wu::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3058,7 +4025,10 @@ unsafe fn test_lsx_vpickve2gr_du() { let a = i64x2::new(748282319555413922, -1352335765832355666); let r: u64 = 748282319555413922; - assert_eq!(r, transmute(lsx_vpickve2gr_du::<0>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vpickve2gr_du::<0>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3070,7 +4040,7 @@ unsafe fn test_lsx_vinsgr2vr_b() { assert_eq!( r, - transmute(lsx_vinsgr2vr_b::<14>(transmute(a), 1333652061)) + transmute(lsx_vinsgr2vr_b::<14>(black_box(transmute(a)), 1333652061)) ); } @@ -3079,7 +4049,10 @@ unsafe fn test_lsx_vinsgr2vr_h() { let a = i16x8::new(-20591, 7819, 25287, -11296, 4604, 28833, -1306, 6418); let r = i64x2::new(-3179432729573085295, 1806782266980897276); - assert_eq!(r, transmute(lsx_vinsgr2vr_h::<5>(transmute(a), -987420193))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_h::<5>(black_box(transmute(a)), -987420193)) + ); } #[simd_test(enable = "lsx")] @@ -3087,7 +4060,10 @@ unsafe fn test_lsx_vinsgr2vr_w() { let a = i32x4::new(1608179655, 886830932, -621638499, 2021214690); let r = i64x2::new(3808909851629379527, 8681050995079237782); - assert_eq!(r, transmute(lsx_vinsgr2vr_w::<2>(transmute(a), -960507754))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_w::<2>(black_box(transmute(a)), -960507754)) + ); } #[simd_test(enable = "lsx")] @@ -3095,7 +4071,10 @@ unsafe fn test_lsx_vinsgr2vr_d() { let a = i64x2::new(-6562091001143116290, -2425423285843953307); let r = i64x2::new(-6562091001143116290, -233659266); - assert_eq!(r, transmute(lsx_vinsgr2vr_d::<1>(transmute(a), -233659266))); + assert_eq!( + r, + transmute(lsx_vinsgr2vr_d::<1>(black_box(transmute(a)), -233659266)) + ); } #[simd_test(enable = "lsx")] @@ -3104,7 +4083,13 @@ unsafe fn test_lsx_vfadd_s() { let b = u32x4::new(1050272808, 1054022924, 1064036136, 1063113730); let r = i64x2::new(4588396142719948771, 4567018621615066847); - assert_eq!(r, transmute(lsx_vfadd_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3113,7 +4098,13 @@ unsafe fn test_lsx_vfadd_d() { let b = u64x2::new(4605819027271079334, 4601207158507578498); let r = i64x2::new(4608685566198055604, 4608371493448991663); - assert_eq!(r, transmute(lsx_vfadd_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfadd_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3122,7 +4113,13 @@ unsafe fn test_lsx_vfsub_s() { let b = u32x4::new(1063475462, 1045836432, 1065150677, 1042376676); let r = i64x2::new(4532926601401089072, 4475386505810184670); - assert_eq!(r, transmute(lsx_vfsub_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3131,7 +4128,13 @@ unsafe fn test_lsx_vfsub_d() { let b = u64x2::new(4605973926398825814, 4600156145303017004); let r = i64x2::new(-4622342180736116526, 4603750919602422881); - assert_eq!(r, transmute(lsx_vfsub_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfsub_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3140,7 +4143,13 @@ unsafe fn test_lsx_vfmul_s() { let b = u32x4::new(1065241951, 1044285812, 1050678216, 1009264512); let r = i64x2::new(4471727895898079441, 4289440988347233543); - assert_eq!(r, transmute(lsx_vfmul_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3149,7 +4158,13 @@ unsafe fn test_lsx_vfmul_d() { let b = u64x2::new(4605208047666947899, 4599634375243914522); let r = i64x2::new(4591550625791030606, 4595475933048682142); - assert_eq!(r, transmute(lsx_vfmul_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmul_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3158,7 +4173,13 @@ unsafe fn test_lsx_vfdiv_s() { let b = u32x4::new(1055538538, 1042248668, 1061233585, 1063649172); let r = i64x2::new(4613180427594946541, 4523223175100126088); - assert_eq!(r, transmute(lsx_vfdiv_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3167,7 +4188,13 @@ unsafe fn test_lsx_vfdiv_d() { let b = u64x2::new(4606326032528596062, 4601783079746725386); let r = i64x2::new(4592460108638699314, 4612120084672695832); - assert_eq!(r, transmute(lsx_vfdiv_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfdiv_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3176,7 +4203,13 @@ unsafe fn test_lsx_vfcvt_h_s() { let b = u32x4::new(1049501482, 1043939972, 1042291392, 1041250232); let r = i64x2::new(3495410141992989809, 3873441386606634666); - assert_eq!(r, transmute(lsx_vfcvt_h_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_h_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3185,7 +4218,13 @@ unsafe fn test_lsx_vfcvt_s_d() { let b = u64x2::new(4600251021237488420, 4593890179408150924); let r = i64x2::new(4469319308295208818, 4496796258465732597); - assert_eq!(r, transmute(lsx_vfcvt_s_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcvt_s_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3194,7 +4233,13 @@ unsafe fn test_lsx_vfmin_s() { let b = u32x4::new(1060093085, 1026130528, 1057322097, 1057646773); let r = i64x2::new(4407197060203522560, 4542558301798153756); - assert_eq!(r, transmute(lsx_vfmin_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3203,7 +4248,13 @@ unsafe fn test_lsx_vfmin_d() { let b = u64x2::new(4584808359801648672, 4602712060570539582); let r = i64x2::new(4584808359801648672, 4602712060570539582); - assert_eq!(r, transmute(lsx_vfmin_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmin_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3212,7 +4263,13 @@ unsafe fn test_lsx_vfmina_s() { let b = u32x4::new(1049119234, 1058336224, 1057046116, 1029386720); let r = i64x2::new(4519411155382848002, 4421182298393539560); - assert_eq!(r, transmute(lsx_vfmina_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3221,7 +4278,13 @@ unsafe fn test_lsx_vfmina_d() { let b = u64x2::new(4599088744110071826, 4598732503789588496); let r = i64x2::new(4599088744110071826, 4598732503789588496); - assert_eq!(r, transmute(lsx_vfmina_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmina_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3230,7 +4293,13 @@ unsafe fn test_lsx_vfmax_s() { let b = u32x4::new(1042175760, 1040826492, 1059132266, 1050815434); let r = i64x2::new(4557520760982391874, 4573984521684325226); - assert_eq!(r, transmute(lsx_vfmax_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3239,7 +4308,13 @@ unsafe fn test_lsx_vfmax_d() { let b = u64x2::new(4593616624275112016, 4605244843740986156); let r = i64x2::new(4606275407710467505, 4605244843740986156); - assert_eq!(r, transmute(lsx_vfmax_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmax_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3248,7 +4323,13 @@ unsafe fn test_lsx_vfmaxa_s() { let b = u32x4::new(1064739422, 1055122552, 1049654310, 1057411362); let r = i64x2::new(4531716855176798814, 4541547219258471462); - assert_eq!(r, transmute(lsx_vfmaxa_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3257,7 +4338,13 @@ unsafe fn test_lsx_vfmaxa_d() { let b = u64x2::new(4603647289310579471, 4603999027307573908); let r = i64x2::new(4603647289310579471, 4606304546706191737); - assert_eq!(r, transmute(lsx_vfmaxa_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfmaxa_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3265,7 +4352,7 @@ unsafe fn test_lsx_vfclass_s() { let a = u32x4::new(1059786314, 1058231666, 1061513647, 1038650488); let r = i64x2::new(549755814016, 549755814016); - assert_eq!(r, transmute(lsx_vfclass_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3273,7 +4360,7 @@ unsafe fn test_lsx_vfclass_d() { let a = u64x2::new(4601724705608768104, 4601126152607382566); let r = i64x2::new(128, 128); - assert_eq!(r, transmute(lsx_vfclass_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfclass_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3281,7 +4368,7 @@ unsafe fn test_lsx_vfsqrt_s() { let a = u32x4::new(1055398716, 1050305974, 995168768, 1064901995); let r = i64x2::new(4543169501430832482, 4574681629207255333); - assert_eq!(r, transmute(lsx_vfsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3289,7 +4376,7 @@ unsafe fn test_lsx_vfsqrt_d() { let a = u64x2::new(4605784293613801157, 4602267946351406890); let r = i64x2::new(4606453893731357485, 4604397310232711799); - assert_eq!(r, transmute(lsx_vfsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3297,7 +4384,7 @@ unsafe fn test_lsx_vfrecip_s() { let a = u32x4::new(1003452672, 1050811504, 1044295808, 1064402913); let r = i64x2::new(4632552602764963931, 4577820515916044016); - assert_eq!(r, transmute(lsx_vfrecip_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3305,7 +4392,7 @@ unsafe fn test_lsx_vfrecip_d() { let a = u64x2::new(4598634931235673106, 4598630619264835010); let r = i64x2::new(4615355353482170689, 4615362460048142095); - assert_eq!(r, transmute(lsx_vfrecip_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecip_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3313,7 +4400,7 @@ unsafe fn test_lsx_vfrecipe_s() { let a = u32x4::new(1057583779, 1062308847, 1060089100, 1048454688); let r = i64x2::new(4583644530211711115, 4647978179615164140); - assert_eq!(r, transmute(lsx_vfrecipe_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3321,7 +4408,7 @@ unsafe fn test_lsx_vfrecipe_d() { let a = u64x2::new(4605515926442181274, 4605369703273365674); let r = i64x2::new(4608204937770303488, 4608317161507651584); - assert_eq!(r, transmute(lsx_vfrecipe_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrecipe_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3329,7 +4416,7 @@ unsafe fn test_lsx_vfrsqrte_s() { let a = u32x4::new(1064377488, 1055815904, 1056897740, 1064016656); let r = i64x2::new(4592421282989204764, 4577184195020153336); - assert_eq!(r, transmute(lsx_vfrsqrte_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx,frecipe")] @@ -3337,7 +4424,7 @@ unsafe fn test_lsx_vfrsqrte_d() { let a = u64x2::new(4602766865443628663, 4605323203937791867); let r = i64x2::new(4608986772678901760, 4607734355383549952); - assert_eq!(r, transmute(lsx_vfrsqrte_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrte_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3345,7 +4432,7 @@ unsafe fn test_lsx_vfrint_s() { let a = u32x4::new(1062138521, 1056849108, 1034089720, 1038314384); let r = i64x2::new(1065353216, 0); - assert_eq!(r, transmute(lsx_vfrint_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3353,7 +4440,7 @@ unsafe fn test_lsx_vfrint_d() { let a = u64x2::new(4598620052333442366, 4603262362368837514); let r = i64x2::new(0, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrint_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrint_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3361,7 +4448,7 @@ unsafe fn test_lsx_vfrsqrt_s() { let a = u32x4::new(1058614029, 1050504950, 1013814976, 1062355001); let r = i64x2::new(4604601921912011494, 4579384257679777264); - assert_eq!(r, transmute(lsx_vfrsqrt_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3369,7 +4456,7 @@ unsafe fn test_lsx_vfrsqrt_d() { let a = u64x2::new(4602924191185043139, 4606088351077917251); let r = i64x2::new(4608881149202581394, 4607483676176768181); - assert_eq!(r, transmute(lsx_vfrsqrt_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrsqrt_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3377,7 +4464,7 @@ unsafe fn test_lsx_vflogb_s() { let a = u32x4::new(1053488512, 1061429282, 1064965594, 1061326585); let r = i64x2::new(-4647714812225126400, -4647714812233515008); - assert_eq!(r, transmute(lsx_vflogb_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3385,7 +4472,7 @@ unsafe fn test_lsx_vflogb_d() { let a = u64x2::new(4589481276789128632, 4599408395082246526); let r = i64x2::new(-4607182418800017408, -4611686018427387904); - assert_eq!(r, transmute(lsx_vflogb_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vflogb_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3393,7 +4480,7 @@ unsafe fn test_lsx_vfcvth_s_h() { let a = i16x8::new(29550, -13884, 689, -1546, 24006, -19112, -12769, 1779); let r = i64x2::new(-4707668984349540352, 4097818267320836096); - assert_eq!(r, transmute(lsx_vfcvth_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3401,7 +4488,7 @@ unsafe fn test_lsx_vfcvth_d_s() { let a = u32x4::new(1051543000, 1042275304, 1038283216, 1063876621); let r = i64x2::new(4592649323212177408, 4606389677895712768); - assert_eq!(r, transmute(lsx_vfcvth_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvth_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3409,7 +4496,7 @@ unsafe fn test_lsx_vfcvtl_s_h() { let a = i16x8::new(-21951, -13772, -17190, 9566, -19227, 9682, 13427, -30861); let r = i64x2::new(-4519784435355738112, 4371798972740354048); - assert_eq!(r, transmute(lsx_vfcvtl_s_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_s_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3417,7 +4504,7 @@ unsafe fn test_lsx_vfcvtl_d_s() { let a = u32x4::new(1059809930, 1051084496, 1062618346, 1058273673); let r = i64x2::new(4604206389789720576, 4599521958080544768); - assert_eq!(r, transmute(lsx_vfcvtl_d_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfcvtl_d_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3425,7 +4512,7 @@ unsafe fn test_lsx_vftint_w_s() { let a = u32x4::new(1064738153, 1040181800, 1064331056, 1050732566); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftint_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3433,7 +4520,7 @@ unsafe fn test_lsx_vftint_l_d() { let a = u64x2::new(4602244632405616462, 4606437548563176328); let r = i64x2::new(0, 1); - assert_eq!(r, transmute(lsx_vftint_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3441,7 +4528,7 @@ unsafe fn test_lsx_vftint_wu_s() { let a = u32x4::new(1051598962, 1051261298, 1059326008, 1057784192); let r = i64x2::new(0, 4294967297); - assert_eq!(r, transmute(lsx_vftint_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3449,7 +4536,7 @@ unsafe fn test_lsx_vftint_lu_d() { let a = u64x2::new(4605561240422589260, 4595241299507769712); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftint_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftint_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3457,7 +4544,7 @@ unsafe fn test_lsx_vftintrz_w_s() { let a = u32x4::new(1027659872, 1064207676, 1058472873, 1055740014); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3465,7 +4552,7 @@ unsafe fn test_lsx_vftintrz_l_d() { let a = u64x2::new(4605051539601556532, 4605129242354661923); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3473,7 +4560,7 @@ unsafe fn test_lsx_vftintrz_wu_s() { let a = u32x4::new(1060876751, 1053710034, 1057340881, 1055555596); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_wu_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_wu_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3481,7 +4568,7 @@ unsafe fn test_lsx_vftintrz_lu_d() { let a = u64x2::new(4598711097624940956, 4598268778109474002); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_lu_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrz_lu_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3489,7 +4576,7 @@ unsafe fn test_lsx_vffint_s_w() { let a = i32x4::new(81337967, 1396520141, 2124859806, 1655115736); let r = i64x2::new(5667351778062705614, 5676028806041521555); - assert_eq!(r, transmute(lsx_vffint_s_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3497,7 +4584,7 @@ unsafe fn test_lsx_vffint_d_l() { let a = i64x2::new(-1543454772280682525, -7672333112582708041); let r = i64x2::new(-4344448119835677720, -4333977527979901593); - assert_eq!(r, transmute(lsx_vffint_d_l(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_l(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3505,7 +4592,7 @@ unsafe fn test_lsx_vffint_s_wu() { let a = u32x4::new(2224947834, 194720725, 2248289069, 1131100007); let r = i64x2::new(5564675890493038082, 5658445755393114667); - assert_eq!(r, transmute(lsx_vffint_s_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_s_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3513,7 +4600,7 @@ unsafe fn test_lsx_vffint_d_lu() { let a = u64x2::new(11793247389644223387, 1356636411353166515); let r = i64x2::new(4892164017273962878, 4878194157796724979); - assert_eq!(r, transmute(lsx_vffint_d_lu(transmute(a)))); + assert_eq!(r, transmute(lsx_vffint_d_lu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3526,7 +4613,13 @@ unsafe fn test_lsx_vandn_v() { ); let r = i64x2::new(184648152262214664, 2315143230533931624); - assert_eq!(r, transmute(lsx_vandn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vandn_v( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3536,7 +4629,7 @@ unsafe fn test_lsx_vneg_b() { ); let r = i64x2::new(-6195839201974406282, 3566844512212398771); - assert_eq!(r, transmute(lsx_vneg_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3544,7 +4637,7 @@ unsafe fn test_lsx_vneg_h() { let a = i16x8::new(-6540, 25893, -2534, 29805, -28719, -16331, -20168, 14650); let r = i64x2::new(-8389350794815923828, -4123521786840387537); - assert_eq!(r, transmute(lsx_vneg_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3552,7 +4645,7 @@ unsafe fn test_lsx_vneg_w() { let a = i32x4::new(-927815384, -898911982, 716171852, -2025175544); let r = i64x2::new(3860797565600356056, 8698062733717804468); - assert_eq!(r, transmute(lsx_vneg_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3560,7 +4653,7 @@ unsafe fn test_lsx_vneg_d() { let a = i64x2::new(4241851098775470984, 2487122929432859927); let r = i64x2::new(-4241851098775470984, -2487122929432859927); - assert_eq!(r, transmute(lsx_vneg_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vneg_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3573,7 +4666,10 @@ unsafe fn test_lsx_vmuh_b() { ); let r = i64x2::new(931993372669836524, 2017024359980467698); - assert_eq!(r, transmute(lsx_vmuh_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_b(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3582,7 +4678,10 @@ unsafe fn test_lsx_vmuh_h() { let b = i16x8::new(-446, -16863, 19467, -13578, -9673, -26572, -7864, 9855); let r = i64x2::new(-1422322400225984462, -842721997477184351); - assert_eq!(r, transmute(lsx_vmuh_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_h(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3591,7 +4690,10 @@ unsafe fn test_lsx_vmuh_w() { let b = i32x4::new(-1684820454, 449222301, 1106076122, 431017950); let r = i64x2::new(-950505610786872114, 420439596918869732); - assert_eq!(r, transmute(lsx_vmuh_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_w(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3600,7 +4702,10 @@ unsafe fn test_lsx_vmuh_d() { let b = i64x2::new(-1208434038665242614, -6078343251861677818); let r = i64x2::new(-121343209662433286, 284995587689374477); - assert_eq!(r, transmute(lsx_vmuh_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_d(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -3613,7 +4718,13 @@ unsafe fn test_lsx_vmuh_bu() { ); let r = i64x2::new(8725461799780227590, -3369022092985820632); - assert_eq!(r, transmute(lsx_vmuh_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3622,7 +4733,13 @@ unsafe fn test_lsx_vmuh_hu() { let b = u16x8::new(14769, 6489, 58866, 5997, 46648, 26325, 42186, 26942); let r = i64x2::new(1572068217944938757, 4366267597274655896); - assert_eq!(r, transmute(lsx_vmuh_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3631,7 +4748,13 @@ unsafe fn test_lsx_vmuh_wu() { let b = u32x4::new(1981234883, 1290836259, 1284878577, 702668871); let r = i64x2::new(4011887256539048298, 960560772888018584); - assert_eq!(r, transmute(lsx_vmuh_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3640,7 +4763,13 @@ unsafe fn test_lsx_vmuh_du() { let b = u64x2::new(14805542397189366587, 10025341254588295994); let r = i64x2::new(-9132083796568587258, 2493261783600858707); - assert_eq!(r, transmute(lsx_vmuh_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmuh_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3650,7 +4779,7 @@ unsafe fn test_lsx_vsllwil_h_b() { ); let r = i64x2::new(-990777899147527584, 126109727303143360); - assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_h_b::<5>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3658,7 +4787,7 @@ unsafe fn test_lsx_vsllwil_w_h() { let a = i16x8::new(25135, -4241, 25399, -32451, 5597, -16847, 3192, -14694); let r = i64x2::new(-9326057613926912, -71360503652913664); - assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_w_h::<9>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3666,7 +4795,7 @@ unsafe fn test_lsx_vsllwil_d_w() { let a = i32x4::new(1472328927, -2106442262, 379100488, -607174188); let r = i64x2::new(6030659284992, -8627987505152); - assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(transmute(a)))); + assert_eq!(r, transmute(lsx_vsllwil_d_w::<12>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -3676,7 +4805,10 @@ unsafe fn test_lsx_vsllwil_hu_bu() { ); let r = i64x2::new(6953679870551405312, 6809531147446388736); - assert_eq!(r, transmute(lsx_vsllwil_hu_bu::<7>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_hu_bu::<7>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3684,7 +4816,10 @@ unsafe fn test_lsx_vsllwil_wu_hu() { let a = u16x8::new(370, 47410, 29611, 6206, 10390, 34658, 65264, 5264); let r = i64x2::new(52127846272954880, 6823569169558272); - assert_eq!(r, transmute(lsx_vsllwil_wu_hu::<8>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_wu_hu::<8>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3692,7 +4827,10 @@ unsafe fn test_lsx_vsllwil_du_wu() { let a = u32x4::new(3249798491, 4098547305, 1101510259, 3478509641); let r = i64x2::new(13630642809995264, 17190553355550720); - assert_eq!(r, transmute(lsx_vsllwil_du_wu::<22>(transmute(a)))); + assert_eq!( + r, + transmute(lsx_vsllwil_du_wu::<22>(black_box(transmute(a)))) + ); } #[simd_test(enable = "lsx")] @@ -3701,7 +4839,13 @@ unsafe fn test_lsx_vsran_b_h() { let b = i16x8::new(-12507, -16997, -17826, 5682, -298, -28572, -8117, -13478); let r = i64x2::new(-864943573596831881, 0); - assert_eq!(r, transmute(lsx_vsran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3710,7 +4854,13 @@ unsafe fn test_lsx_vsran_h_w() { let b = i32x4::new(-52337348, -677553123, -58200260, -1473338606); let r = i64x2::new(1267763303694925820, 0); - assert_eq!(r, transmute(lsx_vsran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3719,7 +4869,13 @@ unsafe fn test_lsx_vsran_w_d() { let b = i64x2::new(-8585295495893484131, -2657141976436452013); let r = i64x2::new(-5882350952887806270, 0); - assert_eq!(r, transmute(lsx_vsran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3728,7 +4884,13 @@ unsafe fn test_lsx_vssran_b_h() { let b = i16x8::new(9459, 15241, 22170, 28027, 5348, 14784, 22613, -9469); let r = i64x2::new(9187483431610086528, 0); - assert_eq!(r, transmute(lsx_vssran_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3737,7 +4899,13 @@ unsafe fn test_lsx_vssran_h_w() { let b = i32x4::new(2070726003, -944816867, -160621862, -1222036466); let r = i64x2::new(-5219109151313101350, 0); - assert_eq!(r, transmute(lsx_vssran_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3746,7 +4914,13 @@ unsafe fn test_lsx_vssran_w_d() { let b = i64x2::new(-7078666005882550400, -2564990402652718339); let r = i64x2::new(-15032385536, 0); - assert_eq!(r, transmute(lsx_vssran_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3755,7 +4929,13 @@ unsafe fn test_lsx_vssran_bu_h() { let b = u16x8::new(2372, 26267, 4722, 47876, 44857, 55242, 45998, 51450); let r = i64x2::new(47227865344, 0); - assert_eq!(r, transmute(lsx_vssran_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3764,7 +4944,13 @@ unsafe fn test_lsx_vssran_hu_w() { let b = u32x4::new(2085279153, 2679576985, 2935643238, 3797496208); let r = i64x2::new(281470684234479, 0); - assert_eq!(r, transmute(lsx_vssran_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3773,7 +4959,13 @@ unsafe fn test_lsx_vssran_wu_d() { let b = u64x2::new(3904652404244024971, 4230656884168675704); let r = i64x2::new(536870912000, 0); - assert_eq!(r, transmute(lsx_vssran_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssran_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3782,7 +4974,13 @@ unsafe fn test_lsx_vsrarn_b_h() { let b = i16x8::new(-19071, -903, 11542, -25909, 24111, 14882, -27192, -8283); let r = i64x2::new(7076043428318610384, 0); - assert_eq!(r, transmute(lsx_vsrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3791,7 +4989,13 @@ unsafe fn test_lsx_vsrarn_h_w() { let b = i32x4::new(-1571698573, 1467958613, -1857488008, 424713310); let r = i64x2::new(498163119212, 0); - assert_eq!(r, transmute(lsx_vsrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3800,7 +5004,13 @@ unsafe fn test_lsx_vsrarn_w_d() { let b = i64x2::new(-8645668865455529235, -3129277582817496880); let r = i64x2::new(-8628090759335017621, 0); - assert_eq!(r, transmute(lsx_vsrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3809,7 +5019,13 @@ unsafe fn test_lsx_vssrarn_b_h() { let b = i16x8::new(24298, 2343, 24641, 20910, 3142, -1171, 25850, 15932); let r = i64x2::new(-148338468081139694, 0); - assert_eq!(r, transmute(lsx_vssrarn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3818,7 +5034,13 @@ unsafe fn test_lsx_vssrarn_h_w() { let b = i32x4::new(1911424854, -931292983, -1710824608, -1179580317); let r = i64x2::new(-9223231301513904204, 0); - assert_eq!(r, transmute(lsx_vssrarn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3827,7 +5049,13 @@ unsafe fn test_lsx_vssrarn_w_d() { let b = i64x2::new(2843689038926761304, -6830262024912907383); let r = i64x2::new(-9223372034707292161, 0); - assert_eq!(r, transmute(lsx_vssrarn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3836,7 +5064,13 @@ unsafe fn test_lsx_vssrarn_bu_h() { let b = u16x8::new(60210, 40155, 14296, 25577, 1550, 1674, 5330, 10645); let r = i64x2::new(10999415373897, 0); - assert_eq!(r, transmute(lsx_vssrarn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3845,7 +5079,13 @@ unsafe fn test_lsx_vssrarn_hu_w() { let b = u32x4::new(3570029841, 3229468238, 1070101998, 3159433736); let r = i64x2::new(281474976645120, 0); - assert_eq!(r, transmute(lsx_vssrarn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3854,7 +5094,13 @@ unsafe fn test_lsx_vssrarn_wu_d() { let b = u64x2::new(1112771813772164907, 646071836375127186); let r = i64x2::new(963446, 0); - assert_eq!(r, transmute(lsx_vssrarn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrarn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3863,7 +5109,13 @@ unsafe fn test_lsx_vsrln_b_h() { let b = i16x8::new(-11667, 13077, -23656, 5150, -23771, -31329, 20729, 15169); let r = i64x2::new(23363148983015937, 0); - assert_eq!(r, transmute(lsx_vsrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3872,7 +5124,13 @@ unsafe fn test_lsx_vsrln_h_w() { let b = i32x4::new(1775989751, -1602688801, -801213995, -1801759515); let r = i64x2::new(-7033214568759295968, 0); - assert_eq!(r, transmute(lsx_vsrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3881,7 +5139,13 @@ unsafe fn test_lsx_vsrln_w_d() { let b = i64x2::new(-1428152872702150626, 3907864416256094744); let r = i64x2::new(-8718771486483115547, 0); - assert_eq!(r, transmute(lsx_vsrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3890,7 +5154,13 @@ unsafe fn test_lsx_vssrln_bu_h() { let b = u16x8::new(41072, 41125, 44619, 49581, 20733, 905, 47558, 7801); let r = i64x2::new(8862857593125412863, 0); - assert_eq!(r, transmute(lsx_vssrln_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3899,7 +5169,13 @@ unsafe fn test_lsx_vssrln_hu_w() { let b = u32x4::new(1325069171, 1380839173, 3495604120, 2839043866); let r = i64x2::new(16889194387279379, 0); - assert_eq!(r, transmute(lsx_vssrln_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3908,7 +5184,13 @@ unsafe fn test_lsx_vssrln_wu_d() { let b = u64x2::new(3908262745817581251, 17131627096934512209); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrln_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3917,7 +5199,13 @@ unsafe fn test_lsx_vsrlrn_b_h() { let b = i16x8::new(22830, -27866, -24616, -9547, 11336, 320, 19908, 7056); let r = i64x2::new(-4888418841542521598, 0); - assert_eq!(r, transmute(lsx_vsrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3926,7 +5214,13 @@ unsafe fn test_lsx_vsrlrn_h_w() { let b = i32x4::new(1387862348, 119424523, 185407104, 1890720739); let r = i64x2::new(2222313691660711041, 0); - assert_eq!(r, transmute(lsx_vsrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3935,7 +5229,13 @@ unsafe fn test_lsx_vsrlrn_w_d() { let b = i64x2::new(-8550351213501194562, 7071641301481388656); let r = i64x2::new(182866822561795, 0); - assert_eq!(r, transmute(lsx_vsrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3944,7 +5244,13 @@ unsafe fn test_lsx_vssrlrn_bu_h() { let b = u16x8::new(51122, 39148, 45511, 57479, 62603, 43668, 5537, 61004); let r = i64x2::new(432344477600776959, 0); - assert_eq!(r, transmute(lsx_vssrlrn_bu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_bu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3953,7 +5259,13 @@ unsafe fn test_lsx_vssrlrn_hu_w() { let b = u32x4::new(1618795892, 3678356443, 862445734, 2115250342); let r = i64x2::new(-4293983341, 0); - assert_eq!(r, transmute(lsx_vssrlrn_hu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_hu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3962,7 +5274,13 @@ unsafe fn test_lsx_vssrlrn_wu_d() { let b = u64x2::new(13406765083608623828, 7214649593148131096); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vssrlrn_wu_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_wu_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -3977,7 +5295,10 @@ unsafe fn test_lsx_vfrstpi_b() { assert_eq!( r, - transmute(lsx_vfrstpi_b::<28>(transmute(a), transmute(b))) + transmute(lsx_vfrstpi_b::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -3987,7 +5308,13 @@ unsafe fn test_lsx_vfrstpi_h() { let b = i16x8::new(9590, -8044, 15088, 4172, 1721, 27581, -19895, -25679); let r = i64x2::new(-4160352588467724069, 5959935604366651239); - assert_eq!(r, transmute(lsx_vfrstpi_h::<1>(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfrstpi_h::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4005,7 +5332,11 @@ unsafe fn test_lsx_vfrstp_b() { assert_eq!( r, - transmute(lsx_vfrstp_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4018,7 +5349,11 @@ unsafe fn test_lsx_vfrstp_h() { assert_eq!( r, - transmute(lsx_vfrstp_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfrstp_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4030,7 +5365,10 @@ unsafe fn test_lsx_vshuf4i_d() { assert_eq!( r, - transmute(lsx_vshuf4i_d::<153>(transmute(a), transmute(b))) + transmute(lsx_vshuf4i_d::<153>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4041,7 +5379,7 @@ unsafe fn test_lsx_vbsrl_v() { ); let r = i64x2::new(4570595419764160432, 56); - assert_eq!(r, transmute(lsx_vbsrl_v::<7>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsrl_v::<7>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4051,7 +5389,7 @@ unsafe fn test_lsx_vbsll_v() { ); let r = i64x2::new(0, -1801439850948198400); - assert_eq!(r, transmute(lsx_vbsll_v::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vbsll_v::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4066,7 +5404,10 @@ unsafe fn test_lsx_vextrins_b() { assert_eq!( r, - transmute(lsx_vextrins_b::<21>(transmute(a), transmute(b))) + transmute(lsx_vextrins_b::<21>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4078,7 +5419,10 @@ unsafe fn test_lsx_vextrins_h() { assert_eq!( r, - transmute(lsx_vextrins_h::<33>(transmute(a), transmute(b))) + transmute(lsx_vextrins_h::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4090,7 +5434,10 @@ unsafe fn test_lsx_vextrins_w() { assert_eq!( r, - transmute(lsx_vextrins_w::<57>(transmute(a), transmute(b))) + transmute(lsx_vextrins_w::<57>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4102,7 +5449,10 @@ unsafe fn test_lsx_vextrins_d() { assert_eq!( r, - transmute(lsx_vextrins_d::<62>(transmute(a), transmute(b))) + transmute(lsx_vextrins_d::<62>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -4113,7 +5463,7 @@ unsafe fn test_lsx_vmskltz_b() { ); let r = i64x2::new(40038, 0); - assert_eq!(r, transmute(lsx_vmskltz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4121,7 +5471,7 @@ unsafe fn test_lsx_vmskltz_h() { let a = i16x8::new(16730, 29121, -23447, -8647, -22303, 21817, 30964, -27069); let r = i64x2::new(156, 0); - assert_eq!(r, transmute(lsx_vmskltz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4129,7 +5479,7 @@ unsafe fn test_lsx_vmskltz_w() { let a = i32x4::new(-657282776, -1247210048, 162595942, 949871015); let r = i64x2::new(3, 0); - assert_eq!(r, transmute(lsx_vmskltz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4137,7 +5487,7 @@ unsafe fn test_lsx_vmskltz_d() { let a = i64x2::new(7728638770319849738, 4250984610820351699); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vmskltz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskltz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4150,7 +5500,13 @@ unsafe fn test_lsx_vsigncov_b() { ); let r = i64x2::new(-9074694153930972472, 1986788453588057010); - assert_eq!(r, transmute(lsx_vsigncov_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4159,7 +5515,13 @@ unsafe fn test_lsx_vsigncov_h() { let b = i16x8::new(27367, 4727, -2962, 14937, 26207, -19075, -26630, 10708); let r = i64x2::new(-4204122973533661927, -3013866947575178847); - assert_eq!(r, transmute(lsx_vsigncov_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4168,7 +5530,13 @@ unsafe fn test_lsx_vsigncov_w() { let b = i32x4::new(-1719915889, 290419288, 202835952, -1715336967); let r = i64x2::new(-1247341342367689359, -7367316170792699888); - assert_eq!(r, transmute(lsx_vsigncov_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4177,7 +5545,13 @@ unsafe fn test_lsx_vsigncov_d() { let b = i64x2::new(-7146260093067324952, -4263419240070336957); let r = i64x2::new(-7146260093067324952, 4263419240070336957); - assert_eq!(r, transmute(lsx_vsigncov_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsigncov_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4189,7 +5563,11 @@ unsafe fn test_lsx_vfmadd_s() { assert_eq!( r, - transmute(lsx_vfmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4202,7 +5580,11 @@ unsafe fn test_lsx_vfmadd_d() { assert_eq!( r, - transmute(lsx_vfmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4215,7 +5597,11 @@ unsafe fn test_lsx_vfmsub_s() { assert_eq!( r, - transmute(lsx_vfmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4228,7 +5614,11 @@ unsafe fn test_lsx_vfmsub_d() { assert_eq!( r, - transmute(lsx_vfmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4241,7 +5631,11 @@ unsafe fn test_lsx_vfnmadd_s() { assert_eq!( r, - transmute(lsx_vfnmadd_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4254,7 +5648,11 @@ unsafe fn test_lsx_vfnmadd_d() { assert_eq!( r, - transmute(lsx_vfnmadd_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmadd_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4267,7 +5665,11 @@ unsafe fn test_lsx_vfnmsub_s() { assert_eq!( r, - transmute(lsx_vfnmsub_s(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_s( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4280,7 +5682,11 @@ unsafe fn test_lsx_vfnmsub_d() { assert_eq!( r, - transmute(lsx_vfnmsub_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vfnmsub_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -4289,7 +5695,7 @@ unsafe fn test_lsx_vftintrne_w_s() { let a = u32x4::new(1031214064, 1059673230, 1042813024, 1053602874); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4297,7 +5703,7 @@ unsafe fn test_lsx_vftintrne_l_d() { let a = u64x2::new(4606989588359571497, 4604713245380178790); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrne_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrne_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4305,7 +5711,7 @@ unsafe fn test_lsx_vftintrp_w_s() { let a = u32x4::new(1061716225, 1050491008, 1064711040, 1065018777); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4313,7 +5719,7 @@ unsafe fn test_lsx_vftintrp_l_d() { let a = u64x2::new(4587516915944025472, 4601504548481216392); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrp_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrp_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4321,7 +5727,7 @@ unsafe fn test_lsx_vftintrm_w_s() { let a = u32x4::new(1045772456, 1065200707, 1061587478, 1035467272); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_w_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4329,7 +5735,7 @@ unsafe fn test_lsx_vftintrm_l_d() { let a = u64x2::new(4597123259408216804, 4594399417822716772); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_l_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrm_l_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4338,7 +5744,13 @@ unsafe fn test_lsx_vftint_w_d() { let b = u64x2::new(4606905060326467647, 4606985586417166381); let r = i64x2::new(4294967297, 0); - assert_eq!(r, transmute(lsx_vftint_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftint_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4347,7 +5759,13 @@ unsafe fn test_lsx_vffint_s_l() { let b = i64x2::new(5814449889729512723, -111756032377486319); let r = i64x2::new(-2610252963668467161, 6669016150524087533); - assert_eq!(r, transmute(lsx_vffint_s_l(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vffint_s_l( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4356,7 +5774,13 @@ unsafe fn test_lsx_vftintrz_w_d() { let b = u64x2::new(4599106720144900270, 4600531579473237336); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrz_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrz_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4365,7 +5789,13 @@ unsafe fn test_lsx_vftintrp_w_d() { let b = u64x2::new(4606104970322966899, 4595679410565085836); let r = i64x2::new(4294967297, 4294967297); - assert_eq!(r, transmute(lsx_vftintrp_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrp_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4374,7 +5804,13 @@ unsafe fn test_lsx_vftintrm_w_d() { let b = u64x2::new(4606733822200032543, 4589510164179968984); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrm_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrm_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4383,7 +5819,13 @@ unsafe fn test_lsx_vftintrne_w_d() { let b = u64x2::new(4599197176714081204, 4605745859931721980); let r = i64x2::new(4294967296, 0); - assert_eq!(r, transmute(lsx_vftintrne_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vftintrne_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4391,7 +5833,7 @@ unsafe fn test_lsx_vftintl_l_s() { let a = u32x4::new(1058856635, 1060563398, 1061422616, 1056124918); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4399,7 +5841,7 @@ unsafe fn test_lsx_vftinth_l_s() { let a = u32x4::new(1045383680, 1040752748, 1061879518, 1054801708); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftinth_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftinth_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4407,7 +5849,7 @@ unsafe fn test_lsx_vffinth_d_w() { let a = i32x4::new(517100418, -188510766, 949226647, -87467194); let r = i64x2::new(4741245898611228672, -4497729803343888384); - assert_eq!(r, transmute(lsx_vffinth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffinth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4415,7 +5857,7 @@ unsafe fn test_lsx_vffintl_d_w() { let a = i32x4::new(1273684401, -2137528906, -2109294912, -1646387998); let r = i64x2::new(4743129027571613696, -4476619782820462592); - assert_eq!(r, transmute(lsx_vffintl_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vffintl_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4423,7 +5865,7 @@ unsafe fn test_lsx_vftintrzl_l_s() { let a = u32x4::new(1031186688, 987838976, 1034565688, 1061017371); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4431,7 +5873,7 @@ unsafe fn test_lsx_vftintrzh_l_s() { let a = u32x4::new(1049433828, 1048953580, 1060964637, 1059899586); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrzh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrzh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4439,7 +5881,7 @@ unsafe fn test_lsx_vftintrpl_l_s() { let a = u32x4::new(1061834803, 1064858941, 1060475110, 1063896216); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrpl_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrpl_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4447,7 +5889,7 @@ unsafe fn test_lsx_vftintrph_l_s() { let a = u32x4::new(1059691939, 1065187151, 1059017027, 1061117394); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrph_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrph_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4455,7 +5897,7 @@ unsafe fn test_lsx_vftintrml_l_s() { let a = u32x4::new(1062985651, 1065211455, 1056421466, 1057373572); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrml_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrml_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4463,7 +5905,7 @@ unsafe fn test_lsx_vftintrmh_l_s() { let a = u32x4::new(1050224290, 1063763666, 1057677270, 1063622234); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vftintrmh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrmh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4471,7 +5913,7 @@ unsafe fn test_lsx_vftintrnel_l_s() { let a = u32x4::new(1060174609, 1050974638, 1047193308, 1062040876); let r = i64x2::new(1, 0); - assert_eq!(r, transmute(lsx_vftintrnel_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrnel_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4479,7 +5921,7 @@ unsafe fn test_lsx_vftintrneh_l_s() { let a = u32x4::new(1055675382, 1036879184, 1064176794, 1063791852); let r = i64x2::new(1, 1); - assert_eq!(r, transmute(lsx_vftintrneh_l_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vftintrneh_l_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4487,7 +5929,7 @@ unsafe fn test_lsx_vfrintrne_s() { let a = u32x4::new(1054667842, 1061395025, 1062986478, 1062529334); let r = i64x2::new(4575657221408423936, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrne_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4495,7 +5937,7 @@ unsafe fn test_lsx_vfrintrne_d() { let a = u64x2::new(4603260356641870565, 4601614335120512898); let r = i64x2::new(4607182418800017408, 0); - assert_eq!(r, transmute(lsx_vfrintrne_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrne_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4503,7 +5945,7 @@ unsafe fn test_lsx_vfrintrz_s() { let a = u32x4::new(1063039577, 1033416832, 1052369306, 1057885024); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4511,7 +5953,7 @@ unsafe fn test_lsx_vfrintrz_d() { let a = u64x2::new(4601515428088814484, 4604735152905786794); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4519,7 +5961,7 @@ unsafe fn test_lsx_vfrintrp_s() { let a = u32x4::new(1061968959, 1056597596, 1064869916, 1058742360); let r = i64x2::new(4575657222473777152, 4575657222473777152); - assert_eq!(r, transmute(lsx_vfrintrp_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4527,7 +5969,7 @@ unsafe fn test_lsx_vfrintrp_d() { let a = u64x2::new(4603531792479663401, 4587997630530425392); let r = i64x2::new(4607182418800017408, 4607182418800017408); - assert_eq!(r, transmute(lsx_vfrintrp_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrp_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4535,7 +5977,7 @@ unsafe fn test_lsx_vfrintrm_s() { let a = u32x4::new(1058024441, 1044087184, 1059777964, 1050835426); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_s(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_s(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4543,7 +5985,7 @@ unsafe fn test_lsx_vfrintrm_d() { let a = u64x2::new(4589388034824743512, 4606800774570289382); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfrintrm_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vfrintrm_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -4556,7 +5998,7 @@ unsafe fn test_lsx_vstelm_b() { ]; let r = i64x2::new(2624488095427530938, -2742340989646681128); - lsx_vstelm_b::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_b::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4568,7 +6010,7 @@ unsafe fn test_lsx_vstelm_h() { ]; let r = i64x2::new(-5777879910580360821, -8010388107109560809); - lsx_vstelm_h::<0, 1>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_h::<0, 1>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4580,7 +6022,7 @@ unsafe fn test_lsx_vstelm_w() { ]; let r = i64x2::new(-7107014201697162202, -4954294907532227136); - lsx_vstelm_w::<0, 3>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_w::<0, 3>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4592,7 +6034,7 @@ unsafe fn test_lsx_vstelm_d() { ]; let r = i64x2::new(2628828971609511929, -1577551211298588582); - lsx_vstelm_d::<0, 0>(transmute(a), o.as_mut_ptr()); + lsx_vstelm_d::<0, 0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -4602,7 +6044,13 @@ unsafe fn test_lsx_vaddwev_d_w() { let b = i32x4::new(-2105551735, -1478351177, 1027048582, -607110700); let r = i64x2::new(-3995454036, 2115628395); - assert_eq!(r, transmute(lsx_vaddwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4611,7 +6059,13 @@ unsafe fn test_lsx_vaddwev_w_h() { let b = i16x8::new(-17479, -32614, 24343, 25426, -14077, -12419, 10115, 23013); let r = i64x2::new(57531086920254, -11304353922851); - assert_eq!(r, transmute(lsx_vaddwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4624,7 +6078,13 @@ unsafe fn test_lsx_vaddwev_h_b() { ); let r = i64x2::new(-6191796646052051, 32369798417022969); - assert_eq!(r, transmute(lsx_vaddwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4633,7 +6093,13 @@ unsafe fn test_lsx_vaddwod_d_w() { let b = i32x4::new(420515981, 473447119, 1471756335, 1044924117); let r = i64x2::new(126219465, 3020814787); - assert_eq!(r, transmute(lsx_vaddwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4642,7 +6108,13 @@ unsafe fn test_lsx_vaddwod_w_h() { let b = i16x8::new(-26581, -22301, 18214, -3616, -24489, 12150, -10765, -24232); let r = i64x2::new(-151719719748481, -112154480997307); - assert_eq!(r, transmute(lsx_vaddwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4655,7 +6127,13 @@ unsafe fn test_lsx_vaddwod_h_b() { ); let r = i64x2::new(-18014780768845678, 14636475441676413); - assert_eq!(r, transmute(lsx_vaddwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4664,7 +6142,13 @@ unsafe fn test_lsx_vaddwev_d_wu() { let b = u32x4::new(1482213353, 1001198416, 3345983326, 2244256337); let r = i64x2::new(4022160583, 4539965521); - assert_eq!(r, transmute(lsx_vaddwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4673,7 +6157,13 @@ unsafe fn test_lsx_vaddwev_w_hu() { let b = u16x8::new(28483, 24704, 9817, 62062, 47674, 8032, 29897, 62737); let r = i64x2::new(176725019407839, 226649719257774); - assert_eq!(r, transmute(lsx_vaddwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4686,7 +6176,13 @@ unsafe fn test_lsx_vaddwev_h_bu() { ); let r = i64x2::new(85006057160704351, 47850943627526421); - assert_eq!(r, transmute(lsx_vaddwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4695,7 +6191,13 @@ unsafe fn test_lsx_vaddwod_d_wu() { let b = u32x4::new(2782520439, 2496077290, 2678772394, 196273109); let r = i64x2::new(4147231270, 2289089430); - assert_eq!(r, transmute(lsx_vaddwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4704,7 +6206,13 @@ unsafe fn test_lsx_vaddwod_w_hu() { let b = u16x8::new(20353, 34039, 21222, 4948, 58293, 4766, 51360, 37497); let r = i64x2::new(82519206727777, 206875689791292); - assert_eq!(r, transmute(lsx_vaddwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4717,7 +6225,13 @@ unsafe fn test_lsx_vaddwod_h_bu() { ); let r = i64x2::new(73466429242409013, 32932877227196635); - assert_eq!(r, transmute(lsx_vaddwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4726,7 +6240,13 @@ unsafe fn test_lsx_vaddwev_d_wu_w() { let b = i32x4::new(-1308530150, 1427930358, 1723198474, 1987356336); let r = i64x2::new(2478528121, 3014708115); - assert_eq!(r, transmute(lsx_vaddwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4735,7 +6255,13 @@ unsafe fn test_lsx_vaddwev_w_hu_h() { let b = i16x8::new(-11621, -6593, 7431, -1189, -12361, -15174, 16182, -32434); let r = i64x2::new(64158221463769, 194716637325930); - assert_eq!(r, transmute(lsx_vaddwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4748,7 +6274,13 @@ unsafe fn test_lsx_vaddwev_h_bu_b() { ); let r = i64x2::new(71776235037065355, -7880749580746636); - assert_eq!(r, transmute(lsx_vaddwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4757,7 +6289,13 @@ unsafe fn test_lsx_vaddwod_d_wu_w() { let b = i32x4::new(-1646368557, 586112311, 376247963, 1048800083); let r = i64x2::new(3497092601, 3306080422); - assert_eq!(r, transmute(lsx_vaddwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4766,7 +6304,13 @@ unsafe fn test_lsx_vaddwod_w_hu_h() { let b = i16x8::new(31700, 22725, 14068, -14860, -28839, -14513, -1195, 27082); let r = i64x2::new(-10273561712908, 369560461022726); - assert_eq!(r, transmute(lsx_vaddwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4779,7 +6323,13 @@ unsafe fn test_lsx_vaddwod_h_bu_b() { ); let r = i64x2::new(49259327819481212, 19140654913421439); - assert_eq!(r, transmute(lsx_vaddwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4788,7 +6338,13 @@ unsafe fn test_lsx_vsubwev_d_w() { let b = i32x4::new(-2090701374, 629564229, -1170676885, 1069800209); let r = i64x2::new(4070621277, 63900397); - assert_eq!(r, transmute(lsx_vsubwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4797,7 +6353,13 @@ unsafe fn test_lsx_vsubwev_w_h() { let b = i16x8::new(-23957, 9416, -29569, -13210, 5333, 8420, 18648, -24201); let r = i64x2::new(228187317494294, -105188044063209); - assert_eq!(r, transmute(lsx_vsubwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4810,7 +6372,13 @@ unsafe fn test_lsx_vsubwev_h_b() { ); let r = i64x2::new(-41939247539617653, -14355228098887689); - assert_eq!(r, transmute(lsx_vsubwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4819,7 +6387,13 @@ unsafe fn test_lsx_vsubwod_d_w() { let b = i32x4::new(1436617964, -45524609, 502994793, -2039550077); let r = i64x2::new(-1037882987, 3497647797); - assert_eq!(r, transmute(lsx_vsubwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4828,7 +6402,13 @@ unsafe fn test_lsx_vsubwod_w_h() { let b = i16x8::new(-1276, 12669, 24115, 19617, -26739, 1910, -757, 23994); let r = i64x2::new(-158286724709540, -182411556002309); - assert_eq!(r, transmute(lsx_vsubwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4841,7 +6421,13 @@ unsafe fn test_lsx_vsubwod_h_b() { ); let r = i64x2::new(23925540523802608, 562958549909362); - assert_eq!(r, transmute(lsx_vsubwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4850,7 +6436,13 @@ unsafe fn test_lsx_vsubwev_d_wu() { let b = u32x4::new(1691253880, 1939268473, 1629937431, 2921768539); let r = i64x2::new(974418830, 1402878171); - assert_eq!(r, transmute(lsx_vsubwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4859,7 +6451,13 @@ unsafe fn test_lsx_vsubwev_w_hu() { let b = u16x8::new(15957, 42770, 43138, 30319, 50823, 18089, 64120, 18054); let r = i64x2::new(-41807211666923, -194858371266981); - assert_eq!(r, transmute(lsx_vsubwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4872,7 +6470,13 @@ unsafe fn test_lsx_vsubwev_h_bu() { ); let r = i64x2::new(-1407181617889293, 47851128289689387); - assert_eq!(r, transmute(lsx_vsubwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4881,7 +6485,13 @@ unsafe fn test_lsx_vsubwod_d_wu() { let b = u32x4::new(103354715, 19070238, 1662532733, 3761231766); let r = i64x2::new(3487028338, -1512426824); - assert_eq!(r, transmute(lsx_vsubwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4890,7 +6500,13 @@ unsafe fn test_lsx_vsubwod_w_hu() { let b = u16x8::new(21739, 45406, 21733, 63910, 6659, 16020, 1211, 637); let r = i64x2::new(-93999654264447, 232211701825972); - assert_eq!(r, transmute(lsx_vsubwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4903,7 +6519,13 @@ unsafe fn test_lsx_vsubwod_h_bu() { ); let r = i64x2::new(-14355150803107815, 14636020195655765); - assert_eq!(r, transmute(lsx_vsubwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4912,7 +6534,13 @@ unsafe fn test_lsx_vaddwev_q_d() { let b = i64x2::new(6738886902337351868, -5985538541381931477); let r = i64x2::new(5606769623790009521, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4921,7 +6549,13 @@ unsafe fn test_lsx_vaddwod_q_d() { let b = i64x2::new(-1244049724346527963, -3275029038845457041); let r = i64x2::new(-4417812606654001824, -1); - assert_eq!(r, transmute(lsx_vaddwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4930,7 +6564,13 @@ unsafe fn test_lsx_vaddwev_q_du() { let b = u64x2::new(6745766838534849346, 15041258018068294402); let r = i64x2::new(5074243625310689089, 1); - assert_eq!(r, transmute(lsx_vaddwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4939,7 +6579,13 @@ unsafe fn test_lsx_vaddwod_q_du() { let b = u64x2::new(13496765248439164553, 4640846570780442359); let r = i64x2::new(-2107214925415534967, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4948,7 +6594,13 @@ unsafe fn test_lsx_vsubwev_q_d() { let b = i64x2::new(8029026411722387723, -2105201823388787841); let r = i64x2::new(480269655671735476, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4957,7 +6609,13 @@ unsafe fn test_lsx_vsubwod_q_d() { let b = i64x2::new(5758437127240728961, 2933507971643343184); let r = i64x2::new(-8752278892998837291, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4966,7 +6624,13 @@ unsafe fn test_lsx_vsubwev_q_du() { let b = u64x2::new(1574118313456291324, 7787456577305510529); let r = i64x2::new(-4672772323591679948, 0); - assert_eq!(r, transmute(lsx_vsubwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4975,7 +6639,13 @@ unsafe fn test_lsx_vsubwod_q_du() { let b = u64x2::new(5627376085113520030, 12775637764770549815); let r = i64x2::new(6257163948134922640, -1); - assert_eq!(r, transmute(lsx_vsubwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsubwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4984,7 +6654,13 @@ unsafe fn test_lsx_vaddwev_q_du_d() { let b = i64x2::new(-1159499132550683978, -4257322329662100669); let r = i64x2::new(-8502520416635627524, 0); - assert_eq!(r, transmute(lsx_vaddwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -4993,7 +6669,13 @@ unsafe fn test_lsx_vaddwod_q_du_d() { let b = i64x2::new(-3902573037873546881, 160140233311333524); let r = i64x2::new(286209858134078253, 0); - assert_eq!(r, transmute(lsx_vaddwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vaddwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5002,7 +6684,13 @@ unsafe fn test_lsx_vmulwev_d_w() { let b = i32x4::new(8741677, -276509855, -1214560052, -1338519080); let r = i64x2::new(11251431313755612, -2205748716678689436); - assert_eq!(r, transmute(lsx_vmulwev_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5011,7 +6699,13 @@ unsafe fn test_lsx_vmulwev_w_h() { let b = i16x8::new(30661, -20472, 1422, -16868, 4256, 9713, -27765, -7287); let r = i64x2::new(-178740441125036345, 469367082934888736); - assert_eq!(r, transmute(lsx_vmulwev_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5024,7 +6718,13 @@ unsafe fn test_lsx_vmulwev_h_b() { ); let r = i64x2::new(38855607073696482, 823864071118590255); - assert_eq!(r, transmute(lsx_vmulwev_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5033,7 +6733,13 @@ unsafe fn test_lsx_vmulwod_d_w() { let b = i32x4::new(63312847, -1377579771, -2054819244, -1416520586); let r = i64x2::new(1549708311038418702, 2478205834807109862); - assert_eq!(r, transmute(lsx_vmulwod_d_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5042,7 +6748,13 @@ unsafe fn test_lsx_vmulwod_w_h() { let b = i16x8::new(23748, 11912, 4946, -23048, 22372, 24702, -24875, -27771); let r = i64x2::new(3222038736804363232, 360450672278114574); - assert_eq!(r, transmute(lsx_vmulwod_w_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5055,7 +6767,13 @@ unsafe fn test_lsx_vmulwod_h_b() { ); let r = i64x2::new(-351280556043402912, 951366355207905332); - assert_eq!(r, transmute(lsx_vmulwod_h_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5064,7 +6782,13 @@ unsafe fn test_lsx_vmulwev_d_wu() { let b = u32x4::new(1769900227, 2256955703, 2342391995, 2407560006); let r = i64x2::new(3651844205567962921, 7772247680216328210); - assert_eq!(r, transmute(lsx_vmulwev_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5073,7 +6797,13 @@ unsafe fn test_lsx_vmulwev_w_hu() { let b = u16x8::new(20499, 45056, 20580, 12771, 53914, 60742, 45402, 40547); let r = i64x2::new(4070644332601545987, 8033224333626513014); - assert_eq!(r, transmute(lsx_vmulwev_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5086,7 +6816,13 @@ unsafe fn test_lsx_vmulwev_h_bu() { ); let r = i64x2::new(271910110892810861, 1947809607093856504); - assert_eq!(r, transmute(lsx_vmulwev_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5095,7 +6831,13 @@ unsafe fn test_lsx_vmulwod_d_wu() { let b = u32x4::new(3750239707, 1422851626, 1277923597, 1377279439); let r = i64x2::new(2821622727533716246, 3005960862740149995); - assert_eq!(r, transmute(lsx_vmulwod_d_wu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5104,7 +6846,13 @@ unsafe fn test_lsx_vmulwod_w_hu() { let b = u16x8::new(38950, 5357, 36233, 17707, 61077, 61518, 5789, 13317); let r = i64x2::new(2460325445475503463, 3109522059894091248); - assert_eq!(r, transmute(lsx_vmulwod_w_hu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5117,7 +6865,13 @@ unsafe fn test_lsx_vmulwod_h_bu() { ); let r = i64x2::new(7364114643151226902, 6612146073643521312); - assert_eq!(r, transmute(lsx_vmulwod_h_bu(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5126,7 +6880,13 @@ unsafe fn test_lsx_vmulwev_d_wu_w() { let b = i32x4::new(1254729285, 1938836163, -1902169358, -257980375); let r = i64x2::new(2295762833698990875, -6669027432954818262); - assert_eq!(r, transmute(lsx_vmulwev_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5135,7 +6895,13 @@ unsafe fn test_lsx_vmulwev_w_hu_h() { let b = i16x8::new(-30477, -10049, 16428, -30668, 21000, 24834, -3219, -9555); let r = i64x2::new(3369342936690107644, -701630285043265176); - assert_eq!(r, transmute(lsx_vmulwev_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5148,7 +6914,13 @@ unsafe fn test_lsx_vmulwev_h_bu_b() { ); let r = i64x2::new(-1134643098233554544, -1885853116779133038); - assert_eq!(r, transmute(lsx_vmulwev_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5157,7 +6929,13 @@ unsafe fn test_lsx_vmulwod_d_wu_w() { let b = i32x4::new(1204047391, -1970001586, 608763444, -2082771896); let r = i64x2::new(-5967343163181744876, -3673352984882804288); - assert_eq!(r, transmute(lsx_vmulwod_d_wu_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_d_wu_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5166,7 +6944,13 @@ unsafe fn test_lsx_vmulwod_w_hu_h() { let b = i16x8::new(-3735, -12972, -4920, 7170, 11577, 9785, 4896, -537); let r = i64x2::new(1024392868267999948, -48053790042385565); - assert_eq!(r, transmute(lsx_vmulwod_w_hu_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_w_hu_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5179,7 +6963,13 @@ unsafe fn test_lsx_vmulwod_h_bu_b() { ); let r = i64x2::new(1905300476090387090, -3940634277386171400); - assert_eq!(r, transmute(lsx_vmulwod_h_bu_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_h_bu_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5188,7 +6978,13 @@ unsafe fn test_lsx_vmulwev_q_d() { let b = i64x2::new(7023560313675997328, 4368639658790376608); let r = i64x2::new(-1409563343912029488, -2779799970834089134); - assert_eq!(r, transmute(lsx_vmulwev_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5197,7 +6993,13 @@ unsafe fn test_lsx_vmulwod_q_d() { let b = i64x2::new(1734538850547798281, 6505001633960390309); let r = i64x2::new(655114704133495137, -1013080750363369114); - assert_eq!(r, transmute(lsx_vmulwod_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5206,7 +7008,13 @@ unsafe fn test_lsx_vmulwev_q_du() { let b = u64x2::new(15048173707940873365, 13594773395779002998); let r = i64x2::new(-4049323972691826149, 6179334620527225413); - assert_eq!(r, transmute(lsx_vmulwev_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5215,7 +7023,13 @@ unsafe fn test_lsx_vmulwod_q_du() { let b = u64x2::new(16172423495582959833, 11676106279348566952); let r = i64x2::new(-66293137947075128, 3694303051148166412); - assert_eq!(r, transmute(lsx_vmulwod_q_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5224,7 +7038,13 @@ unsafe fn test_lsx_vmulwev_q_du_d() { let b = i64x2::new(-7071166739782294817, 8496829998090419991); let r = i64x2::new(5234431817964974175, -5931105679667820544); - assert_eq!(r, transmute(lsx_vmulwev_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwev_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5233,7 +7053,13 @@ unsafe fn test_lsx_vmulwod_q_du_d() { let b = i64x2::new(-9085162554263782091, -3351642387065053502); let r = i64x2::new(-3119502026085414102, -1153233394465180223); - assert_eq!(r, transmute(lsx_vmulwod_q_du_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vmulwod_q_du_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5242,7 +7068,13 @@ unsafe fn test_lsx_vhaddw_q_d() { let b = i64x2::new(9222966760421493517, -8347454331188625422); let r = i64x2::new(6438946365641244151, 0); - assert_eq!(r, transmute(lsx_vhaddw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5251,7 +7083,13 @@ unsafe fn test_lsx_vhaddw_qu_du() { let b = u64x2::new(2141387370256045519, 12417156199252644485); let r = i64x2::new(5083013417816990364, 0); - assert_eq!(r, transmute(lsx_vhaddw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhaddw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5260,7 +7098,13 @@ unsafe fn test_lsx_vhsubw_q_d() { let b = i64x2::new(-3245503809142406078, 8660213762027125085); let r = i64x2::new(817818278178354941, 0); - assert_eq!(r, transmute(lsx_vhsubw_q_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_q_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5269,7 +7113,13 @@ unsafe fn test_lsx_vhsubw_qu_du() { let b = u64x2::new(3098179646743711521, 11374525358855478565); let r = i64x2::new(-8990580109137044958, 0); - assert_eq!(r, transmute(lsx_vhsubw_qu_du(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vhsubw_qu_du( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5281,7 +7131,11 @@ unsafe fn test_lsx_vmaddwev_d_w() { assert_eq!( r, - transmute(lsx_vmaddwev_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5294,7 +7148,11 @@ unsafe fn test_lsx_vmaddwev_w_h() { assert_eq!( r, - transmute(lsx_vmaddwev_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5311,7 +7169,11 @@ unsafe fn test_lsx_vmaddwev_h_b() { assert_eq!( r, - transmute(lsx_vmaddwev_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5324,7 +7186,11 @@ unsafe fn test_lsx_vmaddwev_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwev_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5337,7 +7203,11 @@ unsafe fn test_lsx_vmaddwev_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwev_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5354,7 +7224,11 @@ unsafe fn test_lsx_vmaddwev_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwev_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5367,7 +7241,11 @@ unsafe fn test_lsx_vmaddwod_d_w() { assert_eq!( r, - transmute(lsx_vmaddwod_d_w(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_w( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5380,7 +7258,11 @@ unsafe fn test_lsx_vmaddwod_w_h() { assert_eq!( r, - transmute(lsx_vmaddwod_w_h(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_h( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5397,7 +7279,11 @@ unsafe fn test_lsx_vmaddwod_h_b() { assert_eq!( r, - transmute(lsx_vmaddwod_h_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5410,7 +7296,11 @@ unsafe fn test_lsx_vmaddwod_d_wu() { assert_eq!( r, - transmute(lsx_vmaddwod_d_wu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_d_wu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5423,7 +7313,11 @@ unsafe fn test_lsx_vmaddwod_w_hu() { assert_eq!( r, - transmute(lsx_vmaddwod_w_hu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_w_hu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5440,7 +7334,11 @@ unsafe fn test_lsx_vmaddwod_h_bu() { assert_eq!( r, - transmute(lsx_vmaddwod_h_bu(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_h_bu( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5454,9 +7352,9 @@ unsafe fn test_lsx_vmaddwev_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwev_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5471,9 +7369,9 @@ unsafe fn test_lsx_vmaddwev_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwev_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5492,9 +7390,9 @@ unsafe fn test_lsx_vmaddwev_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwev_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5509,9 +7407,9 @@ unsafe fn test_lsx_vmaddwod_d_wu_w() { assert_eq!( r, transmute(lsx_vmaddwod_d_wu_w( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5526,9 +7424,9 @@ unsafe fn test_lsx_vmaddwod_w_hu_h() { assert_eq!( r, transmute(lsx_vmaddwod_w_hu_h( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5547,9 +7445,9 @@ unsafe fn test_lsx_vmaddwod_h_bu_b() { assert_eq!( r, transmute(lsx_vmaddwod_h_bu_b( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5563,7 +7461,11 @@ unsafe fn test_lsx_vmaddwev_q_d() { assert_eq!( r, - transmute(lsx_vmaddwev_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5576,7 +7478,11 @@ unsafe fn test_lsx_vmaddwod_q_d() { assert_eq!( r, - transmute(lsx_vmaddwod_q_d(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_d( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5589,7 +7495,11 @@ unsafe fn test_lsx_vmaddwev_q_du() { assert_eq!( r, - transmute(lsx_vmaddwev_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwev_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5602,7 +7512,11 @@ unsafe fn test_lsx_vmaddwod_q_du() { assert_eq!( r, - transmute(lsx_vmaddwod_q_du(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vmaddwod_q_du( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -5616,9 +7530,9 @@ unsafe fn test_lsx_vmaddwev_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwev_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5633,9 +7547,9 @@ unsafe fn test_lsx_vmaddwod_q_du_d() { assert_eq!( r, transmute(lsx_vmaddwod_q_du_d( - transmute(a), - transmute(b), - transmute(c) + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) )) ); } @@ -5650,7 +7564,13 @@ unsafe fn test_lsx_vrotr_b() { ); let r = i64x2::new(2841128540244802403, -8694309599374351908); - assert_eq!(r, transmute(lsx_vrotr_b(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_b( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5659,7 +7579,13 @@ unsafe fn test_lsx_vrotr_h() { let b = i16x8::new(-6485, 1418, 8263, -29872, -6491, 3930, -20621, 32531); let r = i64x2::new(2742461657407651598, 3308267577913279393); - assert_eq!(r, transmute(lsx_vrotr_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5668,7 +7594,13 @@ unsafe fn test_lsx_vrotr_w() { let b = i32x4::new(1956224189, -1858012941, -1889446514, -2130978943); let r = i64x2::new(6458469860191573231, -8548346292466177157); - assert_eq!(r, transmute(lsx_vrotr_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5677,7 +7609,13 @@ unsafe fn test_lsx_vrotr_d() { let b = i64x2::new(4553458262651691654, -5062393334123159235); let r = i64x2::new(-3594618648537251961, 7897385285240526033); - assert_eq!(r, transmute(lsx_vrotr_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vrotr_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -5686,7 +7624,10 @@ unsafe fn test_lsx_vadd_q() { let b = i64x2::new(114135477458514099, 3481307531297359399); let r = i64x2::new(2537705118259771652, 4159381110985057604); - assert_eq!(r, transmute(lsx_vadd_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vadd_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5695,7 +7636,10 @@ unsafe fn test_lsx_vsub_q() { let b = i64x2::new(-8526086848853095438, -1323481969747305966); let r = i64x2::new(-2027679534337857341, -1789445478164204527); - assert_eq!(r, transmute(lsx_vsub_q(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vsub_q(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -5745,7 +7689,7 @@ unsafe fn test_lsx_vmskgez_b() { ); let r = i64x2::new(24930, 0); - assert_eq!(r, transmute(lsx_vmskgez_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmskgez_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5755,7 +7699,7 @@ unsafe fn test_lsx_vmsknz_b() { ); let r = i64x2::new(65535, 0); - assert_eq!(r, transmute(lsx_vmsknz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vmsknz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5765,7 +7709,7 @@ unsafe fn test_lsx_vexth_h_b() { ); let r = i64x2::new(-3377613816397739, 32088276197572514); - assert_eq!(r, transmute(lsx_vexth_h_b(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_h_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5773,7 +7717,7 @@ unsafe fn test_lsx_vexth_w_h() { let a = i16x8::new(14576, -26514, 14165, -15781, 10106, 1864, 23348, 30478); let r = i64x2::new(8005819049850, 130902013270836); - assert_eq!(r, transmute(lsx_vexth_w_h(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_w_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5781,7 +7725,7 @@ unsafe fn test_lsx_vexth_d_w() { let a = i32x4::new(863783254, 799653326, -1122161877, -652869192); let r = i64x2::new(-1122161877, -652869192); - assert_eq!(r, transmute(lsx_vexth_d_w(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_d_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5789,7 +7733,7 @@ unsafe fn test_lsx_vexth_q_d() { let a = i64x2::new(2924262436748867523, 1959694872821330818); let r = i64x2::new(1959694872821330818, 0); - assert_eq!(r, transmute(lsx_vexth_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5799,7 +7743,7 @@ unsafe fn test_lsx_vexth_hu_bu() { ); let r = i64x2::new(61080980486815914, 60235902725652628); - assert_eq!(r, transmute(lsx_vexth_hu_bu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_hu_bu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5807,7 +7751,7 @@ unsafe fn test_lsx_vexth_wu_hu() { let a = u16x8::new(58875, 18924, 17611, 30197, 33869, 53931, 4693, 53025); let r = i64x2::new(231631881274445, 227740640875093); - assert_eq!(r, transmute(lsx_vexth_wu_hu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_wu_hu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5815,7 +7759,7 @@ unsafe fn test_lsx_vexth_du_wu() { let a = u32x4::new(3499742961, 2840979237, 2082263829, 1096292547); let r = i64x2::new(2082263829, 1096292547); - assert_eq!(r, transmute(lsx_vexth_du_wu(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_du_wu(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5823,7 +7767,7 @@ unsafe fn test_lsx_vexth_qu_du() { let a = u64x2::new(14170556367894986991, 14238702840099699193); let r = i64x2::new(-4208041233609852423, 0); - assert_eq!(r, transmute(lsx_vexth_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vexth_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5833,7 +7777,7 @@ unsafe fn test_lsx_vrotri_b() { ); let r = i64x2::new(-2919654548887155519, -96080239582005205); - assert_eq!(r, transmute(lsx_vrotri_b::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_b::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5841,7 +7785,7 @@ unsafe fn test_lsx_vrotri_h() { let a = i16x8::new(-14120, -16812, -19570, -990, 24476, -7640, 20329, 8879); let r = i64x2::new(-556925602567188047, 4998607264501841720); - assert_eq!(r, transmute(lsx_vrotri_h::<15>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_h::<15>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5849,7 +7793,7 @@ unsafe fn test_lsx_vrotri_w() { let a = i32x4::new(-1760224525, -1644621284, 1835781046, -1487934110); let r = i64x2::new(2845787365010917052, -6209343103231659283); - assert_eq!(r, transmute(lsx_vrotri_w::<2>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_w::<2>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5857,7 +7801,7 @@ unsafe fn test_lsx_vrotri_d() { let a = i64x2::new(8884634342417174882, 244175985366916345); let r = i64x2::new(-3963790888197019724, 4020656082573561910); - assert_eq!(r, transmute(lsx_vrotri_d::<52>(transmute(a)))); + assert_eq!(r, transmute(lsx_vrotri_d::<52>(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5865,7 +7809,7 @@ unsafe fn test_lsx_vextl_q_d() { let a = i64x2::new(-5110246490938885255, 377414780188285171); let r = i64x2::new(-5110246490938885255, -1); - assert_eq!(r, transmute(lsx_vextl_q_d(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_q_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -5880,7 +7824,10 @@ unsafe fn test_lsx_vsrlni_b_h() { assert_eq!( r, - transmute(lsx_vsrlni_b_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_b_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5892,7 +7839,10 @@ unsafe fn test_lsx_vsrlni_h_w() { assert_eq!( r, - transmute(lsx_vsrlni_h_w::<26>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_h_w::<26>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5904,7 +7854,10 @@ unsafe fn test_lsx_vsrlni_w_d() { assert_eq!( r, - transmute(lsx_vsrlni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5916,7 +7869,10 @@ unsafe fn test_lsx_vsrlni_d_q() { assert_eq!( r, - transmute(lsx_vsrlni_d_q::<74>(transmute(a), transmute(b))) + transmute(lsx_vsrlni_d_q::<74>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5932,7 +7888,10 @@ unsafe fn test_lsx_vsrlrni_b_h() { assert_eq!( r, - transmute(lsx_vsrlrni_b_h::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_b_h::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5944,7 +7903,10 @@ unsafe fn test_lsx_vsrlrni_h_w() { assert_eq!( r, - transmute(lsx_vsrlrni_h_w::<6>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_h_w::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5956,7 +7918,10 @@ unsafe fn test_lsx_vsrlrni_w_d() { assert_eq!( r, - transmute(lsx_vsrlrni_w_d::<52>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_w_d::<52>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5968,7 +7933,10 @@ unsafe fn test_lsx_vsrlrni_d_q() { assert_eq!( r, - transmute(lsx_vsrlrni_d_q::<101>(transmute(a), transmute(b))) + transmute(lsx_vsrlrni_d_q::<101>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5984,7 +7952,10 @@ unsafe fn test_lsx_vssrlni_b_h() { assert_eq!( r, - transmute(lsx_vssrlni_b_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_b_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -5996,7 +7967,10 @@ unsafe fn test_lsx_vssrlni_h_w() { assert_eq!( r, - transmute(lsx_vssrlni_h_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_h_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6008,7 +7982,10 @@ unsafe fn test_lsx_vssrlni_w_d() { assert_eq!( r, - transmute(lsx_vssrlni_w_d::<12>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_w_d::<12>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6020,7 +7997,10 @@ unsafe fn test_lsx_vssrlni_d_q() { assert_eq!( r, - transmute(lsx_vssrlni_d_q::<88>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_d_q::<88>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6036,7 +8016,10 @@ unsafe fn test_lsx_vssrlni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6048,7 +8031,10 @@ unsafe fn test_lsx_vssrlni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlni_hu_w::<9>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_hu_w::<9>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6060,7 +8046,10 @@ unsafe fn test_lsx_vssrlni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlni_wu_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_wu_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6072,7 +8061,10 @@ unsafe fn test_lsx_vssrlni_du_q() { assert_eq!( r, - transmute(lsx_vssrlni_du_q::<6>(transmute(a), transmute(b))) + transmute(lsx_vssrlni_du_q::<6>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6088,7 +8080,10 @@ unsafe fn test_lsx_vssrlrni_b_h() { assert_eq!( r, - transmute(lsx_vssrlrni_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6100,7 +8095,10 @@ unsafe fn test_lsx_vssrlrni_h_w() { assert_eq!( r, - transmute(lsx_vssrlrni_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6112,7 +8110,10 @@ unsafe fn test_lsx_vssrlrni_w_d() { assert_eq!( r, - transmute(lsx_vssrlrni_w_d::<1>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_w_d::<1>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6124,7 +8125,10 @@ unsafe fn test_lsx_vssrlrni_d_q() { assert_eq!( r, - transmute(lsx_vssrlrni_d_q::<60>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_d_q::<60>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6140,7 +8144,10 @@ unsafe fn test_lsx_vssrlrni_bu_h() { assert_eq!( r, - transmute(lsx_vssrlrni_bu_h::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_bu_h::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6152,7 +8159,10 @@ unsafe fn test_lsx_vssrlrni_hu_w() { assert_eq!( r, - transmute(lsx_vssrlrni_hu_w::<25>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_hu_w::<25>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6164,7 +8174,10 @@ unsafe fn test_lsx_vssrlrni_wu_d() { assert_eq!( r, - transmute(lsx_vssrlrni_wu_d::<36>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_wu_d::<36>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6176,7 +8189,10 @@ unsafe fn test_lsx_vssrlrni_du_q() { assert_eq!( r, - transmute(lsx_vssrlrni_du_q::<38>(transmute(a), transmute(b))) + transmute(lsx_vssrlrni_du_q::<38>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6192,7 +8208,10 @@ unsafe fn test_lsx_vsrani_b_h() { assert_eq!( r, - transmute(lsx_vsrani_b_h::<5>(transmute(a), transmute(b))) + transmute(lsx_vsrani_b_h::<5>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6204,7 +8223,10 @@ unsafe fn test_lsx_vsrani_h_w() { assert_eq!( r, - transmute(lsx_vsrani_h_w::<4>(transmute(a), transmute(b))) + transmute(lsx_vsrani_h_w::<4>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6216,7 +8238,10 @@ unsafe fn test_lsx_vsrani_w_d() { assert_eq!( r, - transmute(lsx_vsrani_w_d::<24>(transmute(a), transmute(b))) + transmute(lsx_vsrani_w_d::<24>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6228,7 +8253,10 @@ unsafe fn test_lsx_vsrani_d_q() { assert_eq!( r, - transmute(lsx_vsrani_d_q::<81>(transmute(a), transmute(b))) + transmute(lsx_vsrani_d_q::<81>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6244,7 +8272,10 @@ unsafe fn test_lsx_vsrarni_b_h() { assert_eq!( r, - transmute(lsx_vsrarni_b_h::<3>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_b_h::<3>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6256,7 +8287,10 @@ unsafe fn test_lsx_vsrarni_h_w() { assert_eq!( r, - transmute(lsx_vsrarni_h_w::<15>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_h_w::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6268,7 +8302,10 @@ unsafe fn test_lsx_vsrarni_w_d() { assert_eq!( r, - transmute(lsx_vsrarni_w_d::<59>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_w_d::<59>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6280,7 +8317,10 @@ unsafe fn test_lsx_vsrarni_d_q() { assert_eq!( r, - transmute(lsx_vsrarni_d_q::<0>(transmute(a), transmute(b))) + transmute(lsx_vsrarni_d_q::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6296,7 +8336,10 @@ unsafe fn test_lsx_vssrani_b_h() { assert_eq!( r, - transmute(lsx_vssrani_b_h::<0>(transmute(a), transmute(b))) + transmute(lsx_vssrani_b_h::<0>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6308,7 +8351,10 @@ unsafe fn test_lsx_vssrani_h_w() { assert_eq!( r, - transmute(lsx_vssrani_h_w::<28>(transmute(a), transmute(b))) + transmute(lsx_vssrani_h_w::<28>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6320,7 +8366,10 @@ unsafe fn test_lsx_vssrani_w_d() { assert_eq!( r, - transmute(lsx_vssrani_w_d::<49>(transmute(a), transmute(b))) + transmute(lsx_vssrani_w_d::<49>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6332,7 +8381,10 @@ unsafe fn test_lsx_vssrani_d_q() { assert_eq!( r, - transmute(lsx_vssrani_d_q::<80>(transmute(a), transmute(b))) + transmute(lsx_vssrani_d_q::<80>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6348,7 +8400,10 @@ unsafe fn test_lsx_vssrani_bu_h() { assert_eq!( r, - transmute(lsx_vssrani_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrani_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6360,7 +8415,10 @@ unsafe fn test_lsx_vssrani_hu_w() { assert_eq!( r, - transmute(lsx_vssrani_hu_w::<23>(transmute(a), transmute(b))) + transmute(lsx_vssrani_hu_w::<23>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6372,7 +8430,10 @@ unsafe fn test_lsx_vssrani_wu_d() { assert_eq!( r, - transmute(lsx_vssrani_wu_d::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrani_wu_d::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6384,7 +8445,10 @@ unsafe fn test_lsx_vssrani_du_q() { assert_eq!( r, - transmute(lsx_vssrani_du_q::<33>(transmute(a), transmute(b))) + transmute(lsx_vssrani_du_q::<33>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6400,7 +8464,10 @@ unsafe fn test_lsx_vssrarni_b_h() { assert_eq!( r, - transmute(lsx_vssrarni_b_h::<2>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_b_h::<2>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6412,7 +8479,10 @@ unsafe fn test_lsx_vssrarni_h_w() { assert_eq!( r, - transmute(lsx_vssrarni_h_w::<29>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_h_w::<29>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6424,7 +8494,10 @@ unsafe fn test_lsx_vssrarni_w_d() { assert_eq!( r, - transmute(lsx_vssrarni_w_d::<18>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_w_d::<18>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6436,7 +8509,10 @@ unsafe fn test_lsx_vssrarni_d_q() { assert_eq!( r, - transmute(lsx_vssrarni_d_q::<70>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_d_q::<70>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6452,7 +8528,10 @@ unsafe fn test_lsx_vssrarni_bu_h() { assert_eq!( r, - transmute(lsx_vssrarni_bu_h::<14>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_bu_h::<14>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6464,7 +8543,10 @@ unsafe fn test_lsx_vssrarni_hu_w() { assert_eq!( r, - transmute(lsx_vssrarni_hu_w::<13>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_hu_w::<13>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6476,7 +8558,10 @@ unsafe fn test_lsx_vssrarni_wu_d() { assert_eq!( r, - transmute(lsx_vssrarni_wu_d::<15>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_wu_d::<15>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6488,7 +8573,10 @@ unsafe fn test_lsx_vssrarni_du_q() { assert_eq!( r, - transmute(lsx_vssrarni_du_q::<126>(transmute(a), transmute(b))) + transmute(lsx_vssrarni_du_q::<126>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6500,7 +8588,10 @@ unsafe fn test_lsx_vpermi_w() { assert_eq!( r, - transmute(lsx_vpermi_w::<158>(transmute(a), transmute(b))) + transmute(lsx_vpermi_w::<158>( + black_box(transmute(a)), + black_box(transmute(b)) + )) ); } @@ -6524,7 +8615,7 @@ unsafe fn test_lsx_vst() { ]; let r = i64x2::new(4153633675232462821, -2083384694265299697); - lsx_vst::<0>(transmute(a), o.as_mut_ptr()); + lsx_vst::<0>(black_box(transmute(a)), o.as_mut_ptr()); assert_eq!(r, transmute(o)); } @@ -6534,7 +8625,13 @@ unsafe fn test_lsx_vssrlrn_b_h() { let b = i16x8::new(17437, 9775, -20467, -31838, 5913, 4238, -7458, 2822); let r = i64x2::new(5981906731171643399, 0); - assert_eq!(r, transmute(lsx_vssrlrn_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6543,7 +8640,13 @@ unsafe fn test_lsx_vssrlrn_h_w() { let b = i32x4::new(-2116426818, 1641049288, 712377342, -1572394121); let r = i64x2::new(31243728857268226, 0); - assert_eq!(r, transmute(lsx_vssrlrn_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6552,7 +8655,13 @@ unsafe fn test_lsx_vssrlrn_w_d() { let b = i64x2::new(-3890929847852895653, -7819301294522132056); let r = i64x2::new(66519777023098879, 0); - assert_eq!(r, transmute(lsx_vssrlrn_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrlrn_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6561,7 +8670,13 @@ unsafe fn test_lsx_vssrln_b_h() { let b = i16x8::new(-14062, -29610, -24609, -8884, -1818, 32133, 29934, -6498); let r = i64x2::new(140183437672319, 0); - assert_eq!(r, transmute(lsx_vssrln_b_h(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_b_h( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6570,7 +8685,13 @@ unsafe fn test_lsx_vssrln_h_w() { let b = i32x4::new(-1437891045, 1546371535, -1800954476, -1892390372); let r = i64x2::new(2820489990832156, 0); - assert_eq!(r, transmute(lsx_vssrln_h_w(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_h_w( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6579,7 +8700,13 @@ unsafe fn test_lsx_vssrln_w_d() { let b = i64x2::new(2034490755997557661, -3470252066162700534); let r = i64x2::new(9223372034707292159, 0); - assert_eq!(r, transmute(lsx_vssrln_w_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vssrln_w_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6592,7 +8719,10 @@ unsafe fn test_lsx_vorn_v() { ); let r = i64x2::new(-883973744907789059, -2901520201165080862); - assert_eq!(r, transmute(lsx_vorn_v(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vorn_v(black_box(transmute(a)), black_box(transmute(b)))) + ); } #[simd_test(enable = "lsx")] @@ -6615,7 +8745,11 @@ unsafe fn test_lsx_vshuf_b() { assert_eq!( r, - transmute(lsx_vshuf_b(transmute(a), transmute(b), transmute(c))) + transmute(lsx_vshuf_b( + black_box(transmute(a)), + black_box(transmute(b)), + black_box(transmute(c)) + )) ); } @@ -6639,7 +8773,7 @@ unsafe fn test_lsx_vstx() { ]; let r = i64x2::new(-1493444417618012559, 7191635320606490850); - lsx_vstx(transmute(a), o.as_mut_ptr(), 0); + lsx_vstx(black_box(transmute(a)), o.as_mut_ptr(), 0); assert_eq!(r, transmute(o)); } @@ -6648,7 +8782,7 @@ unsafe fn test_lsx_vextl_qu_du() { let a = u64x2::new(14708598110732796778, 2132245682694336458); let r = i64x2::new(-3738145962976754838, 0); - assert_eq!(r, transmute(lsx_vextl_qu_du(transmute(a)))); + assert_eq!(r, transmute(lsx_vextl_qu_du(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6658,7 +8792,7 @@ unsafe fn test_lsx_bnz_b() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6666,7 +8800,7 @@ unsafe fn test_lsx_bnz_d() { let a = u64x2::new(2935166648440262530, 9853932033129373129); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6674,7 +8808,7 @@ unsafe fn test_lsx_bnz_h() { let a = u16x8::new(55695, 60003, 59560, 35123, 25693, 41352, 61626, 42007); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6684,7 +8818,7 @@ unsafe fn test_lsx_bnz_v() { ); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6692,7 +8826,7 @@ unsafe fn test_lsx_bnz_w() { let a = u32x4::new(1172712391, 4211490091, 1954893853, 1606462106); let r: i32 = 1; - assert_eq!(r, transmute(lsx_bnz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bnz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6702,7 +8836,7 @@ unsafe fn test_lsx_bz_b() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_b(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_b(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6710,7 +8844,7 @@ unsafe fn test_lsx_bz_d() { let a = u64x2::new(6051854163594201075, 9957257179760945130); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_d(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_d(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6718,7 +8852,7 @@ unsafe fn test_lsx_bz_h() { let a = u16x8::new(19470, 29377, 53886, 60432, 20799, 41755, 54479, 52192); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_h(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_h(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6728,7 +8862,7 @@ unsafe fn test_lsx_bz_v() { ); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_v(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_v(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6736,7 +8870,7 @@ unsafe fn test_lsx_bz_w() { let a = u32x4::new(840335855, 1404686204, 628335401, 1171808080); let r: i32 = 0; - assert_eq!(r, transmute(lsx_bz_w(transmute(a)))); + assert_eq!(r, transmute(lsx_bz_w(black_box(transmute(a))))); } #[simd_test(enable = "lsx")] @@ -6745,7 +8879,13 @@ unsafe fn test_lsx_vfcmp_caf_d() { let b = u64x2::new(4594845432849836188, 4605165420863530034); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6754,7 +8894,13 @@ unsafe fn test_lsx_vfcmp_caf_s() { let b = u32x4::new(1058412800, 1058762495, 1028487696, 1027290752); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_caf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_caf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6763,7 +8909,13 @@ unsafe fn test_lsx_vfcmp_ceq_d() { let b = u64x2::new(4605937250150464526, 4596769502461699132); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6772,7 +8924,13 @@ unsafe fn test_lsx_vfcmp_ceq_s() { let b = u32x4::new(1057471620, 1064008655, 1062698831, 1064822930); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_ceq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_ceq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6781,7 +8939,13 @@ unsafe fn test_lsx_vfcmp_cle_d() { let b = u64x2::new(4596931282408842596, 4592481315209481584); let r = i64x2::new(-1, 0); - assert_eq!(r, transmute(lsx_vfcmp_cle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6790,7 +8954,13 @@ unsafe fn test_lsx_vfcmp_cle_s() { let b = u32x4::new(1021993344, 1043028808, 1064182329, 1054794412); let r = i64x2::new(-4294967296, -1); - assert_eq!(r, transmute(lsx_vfcmp_cle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6799,7 +8969,13 @@ unsafe fn test_lsx_vfcmp_clt_d() { let b = u64x2::new(4603056125735978454, 4595932368389116476); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6808,7 +8984,13 @@ unsafe fn test_lsx_vfcmp_clt_s() { let b = u32x4::new(1040327468, 1040072248, 1063314103, 1061361061); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_clt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_clt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6817,7 +8999,13 @@ unsafe fn test_lsx_vfcmp_cne_d() { let b = u64x2::new(4602354759349431170, 4598595124838935466); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6826,7 +9014,13 @@ unsafe fn test_lsx_vfcmp_cne_s() { let b = u32x4::new(1063262940, 1058010357, 1052721962, 1061295988); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6835,7 +9029,13 @@ unsafe fn test_lsx_vfcmp_cor_d() { let b = u64x2::new(4606863361114437050, 4600753700959452152); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6844,7 +9044,13 @@ unsafe fn test_lsx_vfcmp_cor_s() { let b = u32x4::new(1053615382, 1065255138, 1051565294, 1041776832); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6853,7 +9059,13 @@ unsafe fn test_lsx_vfcmp_cueq_d() { let b = u64x2::new(4603317345052528721, 4586734343919602352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6862,7 +9074,13 @@ unsafe fn test_lsx_vfcmp_cueq_s() { let b = u32x4::new(1057082822, 1059761998, 1052599998, 1054369118); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6871,7 +9089,13 @@ unsafe fn test_lsx_vfcmp_cule_d() { let b = u64x2::new(4604253448175093958, 4599648167588382448); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6880,7 +9104,13 @@ unsafe fn test_lsx_vfcmp_cule_s() { let b = u32x4::new(1051100696, 1062219104, 1064568294, 1032521352); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_cule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6889,7 +9119,13 @@ unsafe fn test_lsx_vfcmp_cult_d() { let b = u64x2::new(4602944708025910986, 4606429728449082215); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_cult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6898,7 +9134,13 @@ unsafe fn test_lsx_vfcmp_cult_s() { let b = u32x4::new(1030808384, 1044268840, 1050761328, 1037308928); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6907,7 +9149,13 @@ unsafe fn test_lsx_vfcmp_cun_d() { let b = u64x2::new(4599145506416791474, 4602762942707610466); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6916,7 +9164,13 @@ unsafe fn test_lsx_vfcmp_cune_d() { let b = u64x2::new(4602895209237804084, 4598685577984089858); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6925,7 +9179,13 @@ unsafe fn test_lsx_vfcmp_cune_s() { let b = u32x4::new(1049955876, 1032474200, 1023410112, 1050347912); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_cune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6934,7 +9194,13 @@ unsafe fn test_lsx_vfcmp_cun_s() { let b = u32x4::new(1053288920, 1059911123, 1058695573, 1062913175); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_cun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_cun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6943,7 +9209,13 @@ unsafe fn test_lsx_vfcmp_saf_d() { let b = u64x2::new(4589118818065931376, 4603302333347826011); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6952,7 +9224,13 @@ unsafe fn test_lsx_vfcmp_saf_s() { let b = u32x4::new(1044756936, 1054667546, 1059141760, 1062203553); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_saf_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_saf_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6961,7 +9239,13 @@ unsafe fn test_lsx_vfcmp_seq_d() { let b = u64x2::new(4594167956310606988, 4596272126122589228); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6970,7 +9254,13 @@ unsafe fn test_lsx_vfcmp_seq_s() { let b = u32x4::new(1057231588, 1051495460, 1057998997, 1049117328); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_seq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_seq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6979,7 +9269,13 @@ unsafe fn test_lsx_vfcmp_sle_d() { let b = u64x2::new(4603919005855163252, 4594682846653946884); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6988,7 +9284,13 @@ unsafe fn test_lsx_vfcmp_sle_s() { let b = u32x4::new(1045989468, 1052518900, 1046184640, 1032417352); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sle_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sle_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -6997,7 +9299,13 @@ unsafe fn test_lsx_vfcmp_slt_d() { let b = u64x2::new(4600564867142526828, 4585131890265864544); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_slt_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7006,7 +9314,13 @@ unsafe fn test_lsx_vfcmp_slt_s() { let b = u32x4::new(1063435026, 1062439603, 1060665555, 1059252630); let r = i64x2::new(-1, -4294967296); - assert_eq!(r, transmute(lsx_vfcmp_slt_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_slt_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7015,7 +9329,13 @@ unsafe fn test_lsx_vfcmp_sne_d() { let b = u64x2::new(4606789952952688555, 4605380358192261377); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7024,7 +9344,13 @@ unsafe fn test_lsx_vfcmp_sne_s() { let b = u32x4::new(1055803760, 1063372602, 1062608900, 1054634370); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sne_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sne_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7033,7 +9359,13 @@ unsafe fn test_lsx_vfcmp_sor_d() { let b = u64x2::new(4606380175568635560, 4602092067387067462); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7042,7 +9374,13 @@ unsafe fn test_lsx_vfcmp_sor_s() { let b = u32x4::new(1064534350, 1035771168, 1059142426, 1034677600); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sor_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sor_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7051,7 +9389,13 @@ unsafe fn test_lsx_vfcmp_sueq_d() { let b = u64x2::new(4602917609947054533, 4605983209212177197); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7060,7 +9404,13 @@ unsafe fn test_lsx_vfcmp_sueq_s() { let b = u32x4::new(1064871165, 1059796257, 1055456352, 1058662692); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sueq_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sueq_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7069,7 +9419,13 @@ unsafe fn test_lsx_vfcmp_sule_d() { let b = u64x2::new(4594044173266256632, 4601549551994738386); let r = i64x2::new(0, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7078,7 +9434,13 @@ unsafe fn test_lsx_vfcmp_sule_s() { let b = u32x4::new(1061061244, 1051874412, 1041025316, 1056018690); let r = i64x2::new(4294967295, -1); - assert_eq!(r, transmute(lsx_vfcmp_sule_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sule_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7087,7 +9449,13 @@ unsafe fn test_lsx_vfcmp_sult_d() { let b = u64x2::new(4603848042095479627, 4605032971316970060); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sult_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7096,7 +9464,13 @@ unsafe fn test_lsx_vfcmp_sult_s() { let b = u32x4::new(1053631630, 1064026599, 1058029398, 1041182304); let r = i64x2::new(-4294967296, 4294967295); - assert_eq!(r, transmute(lsx_vfcmp_sult_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sult_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7105,7 +9479,13 @@ unsafe fn test_lsx_vfcmp_sun_d() { let b = u64x2::new(4560681020073292800, 4604624347352815433); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7114,7 +9494,13 @@ unsafe fn test_lsx_vfcmp_sune_d() { let b = u64x2::new(4593947987798339484, 4603656097008761637); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_d(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_d( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7123,7 +9509,13 @@ unsafe fn test_lsx_vfcmp_sune_s() { let b = u32x4::new(1049327168, 1034635272, 1042258196, 1062844003); let r = i64x2::new(-1, -1); - assert_eq!(r, transmute(lsx_vfcmp_sune_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sune_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] @@ -7132,7 +9524,13 @@ unsafe fn test_lsx_vfcmp_sun_s() { let b = u32x4::new(1057442863, 1064573466, 1058086753, 1015993248); let r = i64x2::new(0, 0); - assert_eq!(r, transmute(lsx_vfcmp_sun_s(transmute(a), transmute(b)))); + assert_eq!( + r, + transmute(lsx_vfcmp_sun_s( + black_box(transmute(a)), + black_box(transmute(b)) + )) + ); } #[simd_test(enable = "lsx")] diff --git a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs index ab968aff20bb..41c21aac2a57 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs @@ -11,7 +11,7 @@ use crate::arch::asm; /// Reads the 64-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtime_d() -> (i64, isize) { let (val, tid): (i64, isize); @@ -48,21 +48,21 @@ pub fn rdtime_d() -> (i64, isize) { } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crc_w_d_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crcc_w_d_w(a: i64, b: i32) -> i32 { unsafe { __crcc_w_d_w(a, b) } } /// Generates the cache operation instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn cacop(b: i64) { static_assert_uimm_bits!(IMM5, 5); @@ -71,7 +71,7 @@ pub unsafe fn cacop(b: i64) { } /// Reads the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrrd() -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -79,7 +79,7 @@ pub unsafe fn csrrd() -> i64 { } /// Writes the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrwr(a: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -87,7 +87,7 @@ pub unsafe fn csrwr(a: i64) -> i64 { } /// Exchanges the CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { static_assert_uimm_bits!(IMM14, 14); @@ -95,35 +95,35 @@ pub unsafe fn csrxchg(a: i64, b: i64) -> i64 { } /// Reads the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_d(a: i32) -> i64 { __iocsrrd_d(a) } /// Writes the 64-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_d(a: i64, b: i32) { __iocsrwr_d(a, b) } /// Generates the less-than-or-equal asseration instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtle(a: i64, b: i64) { __asrtle(a, b); } /// Generates the greater-than asseration instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn asrtgt(a: i64, b: i64) { __asrtgt(a, b); } /// Loads the page table directory entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn lddir(a: i64) -> i64 { @@ -132,7 +132,7 @@ pub unsafe fn lddir(a: i64) -> i64 { } /// Loads the page table entry -#[inline] +#[inline(always)] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn ldpte(a: i64) { diff --git a/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs index 8991fe857682..b2a67fb60997 100644 --- a/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs @@ -3,7 +3,7 @@ use crate::arch::asm; /// Reads the lower 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimel_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -12,7 +12,7 @@ pub fn rdtimel_w() -> (i32, isize) { } /// Reads the upper 32-bit stable counter value and the counter ID -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn rdtimeh_w() -> (i32, isize) { let (val, tid): (i32, isize); @@ -71,49 +71,49 @@ pub fn rdtimeh_w() -> (i32, isize) { } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crc_w_b_w(a: i32, b: i32) -> i32 { unsafe { __crc_w_b_w(a, b) } } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crc_w_h_w(a: i32, b: i32) -> i32 { unsafe { __crc_w_h_w(a, b) } } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crc_w_w_w(a: i32, b: i32) -> i32 { unsafe { __crc_w_w_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crcc_w_b_w(a: i32, b: i32) -> i32 { unsafe { __crcc_w_b_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crcc_w_h_w(a: i32, b: i32) -> i32 { unsafe { __crcc_w_h_w(a, b) } } /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn crcc_w_w_w(a: i32, b: i32) -> i32 { unsafe { __crcc_w_w_w(a, b) } } /// Generates the memory barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn dbar() { static_assert_uimm_bits!(IMM15, 15); @@ -121,7 +121,7 @@ pub fn dbar() { } /// Generates the instruction-fetch barrier instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn ibar() { static_assert_uimm_bits!(IMM15, 15); @@ -129,7 +129,7 @@ pub fn ibar() { } /// Moves data from a GPR to the FCSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn movgr2fcsr(a: i32) { static_assert_uimm_bits!(IMM2, 2); @@ -137,7 +137,7 @@ pub unsafe fn movgr2fcsr(a: i32) { } /// Moves data from a FCSR to the GPR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn movfcsr2gr() -> i32 { static_assert_uimm_bits!(IMM2, 2); @@ -145,49 +145,49 @@ pub fn movfcsr2gr() -> i32 { } /// Reads the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_b(a: i32) -> i32 { __iocsrrd_b(a) } /// Reads the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_h(a: i32) -> i32 { __iocsrrd_h(a) } /// Reads the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrrd_w(a: i32) -> i32 { __iocsrrd_w(a) } /// Writes the 8-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_b(a: i32, b: i32) { __iocsrwr_b(a, b) } /// Writes the 16-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_h(a: i32, b: i32) { __iocsrwr_h(a, b) } /// Writes the 32-bit IO-CSR -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn iocsrwr_w(a: i32, b: i32) { __iocsrwr_w(a, b) } /// Generates the breakpoint instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn brk() { static_assert_uimm_bits!(IMM15, 15); @@ -195,14 +195,14 @@ pub unsafe fn brk() { } /// Reads the CPU configuration register -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn cpucfg(a: i32) -> i32 { unsafe { __cpucfg(a) } } /// Generates the syscall instruction -#[inline] +#[inline(always)] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn syscall() { static_assert_uimm_bits!(IMM15, 15); @@ -210,7 +210,7 @@ pub unsafe fn syscall() { } /// Calculate the approximate single-precision result of 1.0 divided -#[inline] +#[inline(always)] #[target_feature(enable = "frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn frecipe_s(a: f32) -> f32 { @@ -218,7 +218,7 @@ pub fn frecipe_s(a: f32) -> f32 { } /// Calculate the approximate double-precision result of 1.0 divided -#[inline] +#[inline(always)] #[target_feature(enable = "frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn frecipe_d(a: f64) -> f64 { @@ -226,7 +226,7 @@ pub fn frecipe_d(a: f64) -> f64 { } /// Calculate the approximate single-precision result of dividing 1.0 by the square root -#[inline] +#[inline(always)] #[target_feature(enable = "frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn frsqrte_s(a: f32) -> f32 { @@ -234,7 +234,7 @@ pub fn frsqrte_s(a: f32) -> f32 { } /// Calculate the approximate double-precision result of dividing 1.0 by the square root -#[inline] +#[inline(always)] #[target_feature(enable = "frecipe")] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub fn frsqrte_d(a: f64) -> f64 { diff --git a/library/stdarch/crates/core_arch/src/macros.rs b/library/stdarch/crates/core_arch/src/macros.rs index 00e92428b3e7..83039bc65acc 100644 --- a/library/stdarch/crates/core_arch/src/macros.rs +++ b/library/stdarch/crates/core_arch/src/macros.rs @@ -14,6 +14,22 @@ macro_rules! static_assert { }; } +#[allow(unused_macros)] +macro_rules! static_assert_range { + ($imm:ident, $min:literal..=$max:literal) => { + static_assert!( + $min <= $imm && $imm <= $max, + concat!( + stringify!($imm), + " is not in range ", + stringify!($min), + "-", + stringify!($max), + ) + ) + }; +} + #[allow(unused_macros)] macro_rules! static_assert_uimm_bits { ($imm:ident, $bits:expr) => { diff --git a/library/stdarch/crates/core_arch/src/mips/msa.rs b/library/stdarch/crates/core_arch/src/mips/msa.rs index 6246433da558..bc601baef9e2 100644 --- a/library/stdarch/crates/core_arch/src/mips/msa.rs +++ b/library/stdarch/crates/core_arch/src/mips/msa.rs @@ -1407,7 +1407,7 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { @@ -1423,7 +1423,7 @@ pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { @@ -1439,7 +1439,7 @@ pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { @@ -1455,7 +1455,7 @@ pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(addvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_d(a: v2i64) -> v2i64 { @@ -1486,7 +1486,7 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))] +#[cfg_attr(test, assert_instr(andi.b, IMM8 = 0b10010111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_andi_b(a: v16u8) -> v16u8 { @@ -1938,7 +1938,7 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bclri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { @@ -1954,7 +1954,7 @@ pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bclri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { @@ -1970,7 +1970,7 @@ pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bclri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { @@ -1986,7 +1986,7 @@ pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bclri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_d(a: v2u64) -> v2u64 { @@ -2062,7 +2062,7 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsli.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2078,7 +2078,7 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsli.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2094,7 +2094,7 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsli.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2110,7 +2110,7 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsli.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2186,7 +2186,7 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(binsri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2202,7 +2202,7 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(binsri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { @@ -2218,7 +2218,7 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(binsri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { @@ -2234,7 +2234,7 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(binsri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64) -> v2u64 { @@ -2265,7 +2265,7 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmnzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2296,7 +2296,7 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bmzi.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2372,7 +2372,7 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bnegi.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { @@ -2388,7 +2388,7 @@ pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bnegi.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { @@ -2404,7 +2404,7 @@ pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bnegi.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { @@ -2420,7 +2420,7 @@ pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bnegi.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_d(a: v2u64) -> v2u64 { @@ -2512,7 +2512,7 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(bseli.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8) -> v16u8 { @@ -2588,7 +2588,7 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(bseti.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { @@ -2604,7 +2604,7 @@ pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(bseti.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { @@ -2620,7 +2620,7 @@ pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(bseti.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { @@ -2636,7 +2636,7 @@ pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(bseti.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_d(a: v2u64) -> v2u64 { @@ -2769,7 +2769,7 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { @@ -2785,7 +2785,7 @@ pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { @@ -2801,7 +2801,7 @@ pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { @@ -2817,7 +2817,7 @@ pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(ceqi.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { @@ -2832,7 +2832,7 @@ pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { /// Can not be tested in user mode #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(cfcmsa, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(cfcmsa, IMM5 = 0b11111))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_cfcmsa() -> i32 { @@ -2969,7 +2969,7 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { @@ -2986,7 +2986,7 @@ pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { @@ -3003,7 +3003,7 @@ pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { @@ -3020,7 +3020,7 @@ pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { @@ -3037,7 +3037,7 @@ pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clei_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { @@ -3054,7 +3054,7 @@ pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { @@ -3071,7 +3071,7 @@ pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { @@ -3088,7 +3088,7 @@ pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clei_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_d(a: v2u64) -> v2i64 { @@ -3225,7 +3225,7 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_s.b, IMM_S5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { @@ -3242,7 +3242,7 @@ pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { @@ -3259,7 +3259,7 @@ pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { @@ -3276,7 +3276,7 @@ pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { @@ -3293,7 +3293,7 @@ pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))] +#[cfg_attr(test, assert_instr(clti_u.b, IMM5 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { @@ -3310,7 +3310,7 @@ pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { @@ -3327,7 +3327,7 @@ pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { @@ -3344,7 +3344,7 @@ pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(clti_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { @@ -3359,7 +3359,7 @@ pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_s.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { @@ -3374,7 +3374,7 @@ pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_s.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { @@ -3389,7 +3389,7 @@ pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_s.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { @@ -3404,7 +3404,7 @@ pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_s.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { @@ -3419,7 +3419,7 @@ pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(copy_u.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { @@ -3434,7 +3434,7 @@ pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(copy_u.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { @@ -3449,7 +3449,7 @@ pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(copy_u.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { @@ -3464,7 +3464,7 @@ pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(copy_u.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { @@ -3481,7 +3481,7 @@ pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ctcmsa, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(ctcmsa, IMM5 = 0b1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ctcmsa(a: i32) -> () { @@ -5855,7 +5855,7 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insert.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { @@ -5871,7 +5871,7 @@ pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insert.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { @@ -5887,7 +5887,7 @@ pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insert.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { @@ -5903,7 +5903,7 @@ pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insert.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { @@ -5919,7 +5919,7 @@ pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(insve.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { @@ -5935,7 +5935,7 @@ pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(insve.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { @@ -5951,7 +5951,7 @@ pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(insve.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { @@ -5967,7 +5967,7 @@ pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(insve.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { @@ -5983,7 +5983,7 @@ pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ld.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { @@ -5999,7 +5999,7 @@ pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(ld.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { @@ -6016,7 +6016,7 @@ pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(ld.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { @@ -6033,7 +6033,7 @@ pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(ld.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { @@ -6050,7 +6050,7 @@ pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_b() -> v16i8 { @@ -6066,7 +6066,7 @@ pub unsafe fn __msa_ldi_b() -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.h, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.h, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_h() -> v8i16 { @@ -6082,7 +6082,7 @@ pub unsafe fn __msa_ldi_h() -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.w, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.w, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_w() -> v4i32 { @@ -6098,7 +6098,7 @@ pub unsafe fn __msa_ldi_w() -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ldi.d, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(ldi.d, IMM_S10 = -1))] #[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_d() -> v2i64 { @@ -6410,7 +6410,7 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { @@ -6426,7 +6426,7 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { @@ -6442,7 +6442,7 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { @@ -6458,7 +6458,7 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { @@ -6474,7 +6474,7 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { @@ -6490,7 +6490,7 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { @@ -6506,7 +6506,7 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { @@ -6522,7 +6522,7 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(maxi_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_d(a: v2u64) -> v2u64 { @@ -6654,7 +6654,7 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.b, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { @@ -6670,7 +6670,7 @@ pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.h, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { @@ -6686,7 +6686,7 @@ pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.w, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { @@ -6702,7 +6702,7 @@ pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_s.d, IMM_S5 = -1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_d(a: v2i64) -> v2i64 { @@ -6774,7 +6774,7 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.b, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { @@ -6790,7 +6790,7 @@ pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.h, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { @@ -6806,7 +6806,7 @@ pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { @@ -6822,7 +6822,7 @@ pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(mini_u.d, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_d(a: v2u64) -> v2u64 { @@ -7343,7 +7343,7 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(nori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_nori_b(a: v16u8) -> v16u8 { @@ -7375,7 +7375,7 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(ori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ori_b(a: v16u8) -> v16u8 { @@ -7555,7 +7555,7 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_s.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { @@ -7571,7 +7571,7 @@ pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_s.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { @@ -7587,7 +7587,7 @@ pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_s.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { @@ -7603,7 +7603,7 @@ pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_s.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { @@ -7619,7 +7619,7 @@ pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))] +#[cfg_attr(test, assert_instr(sat_u.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { @@ -7635,7 +7635,7 @@ pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))] +#[cfg_attr(test, assert_instr(sat_u.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { @@ -7651,7 +7651,7 @@ pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))] +#[cfg_attr(test, assert_instr(sat_u.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { @@ -7667,7 +7667,7 @@ pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))] +#[cfg_attr(test, assert_instr(sat_u.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { @@ -7684,7 +7684,7 @@ pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { @@ -7701,7 +7701,7 @@ pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.h, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { @@ -7718,7 +7718,7 @@ pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(shf.w, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_w(a: v4i32) -> v4i32 { @@ -7823,7 +7823,7 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(sldi.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { @@ -7844,7 +7844,7 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(sldi.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { @@ -7865,7 +7865,7 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(sldi.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { @@ -7886,7 +7886,7 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(sldi.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64) -> v2i64 { @@ -7962,7 +7962,7 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(slli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { @@ -7978,7 +7978,7 @@ pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(slli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { @@ -7994,7 +7994,7 @@ pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(slli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { @@ -8010,7 +8010,7 @@ pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(slli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_d(a: v2i64) -> v2i64 { @@ -8085,7 +8085,7 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(splati.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { @@ -8100,7 +8100,7 @@ pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(splati.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { @@ -8115,7 +8115,7 @@ pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(splati.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { @@ -8130,7 +8130,7 @@ pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(splati.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_d(a: v2i64) -> v2i64 { @@ -8206,7 +8206,7 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srai.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { @@ -8222,7 +8222,7 @@ pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srai.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { @@ -8238,7 +8238,7 @@ pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srai.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { @@ -8254,7 +8254,7 @@ pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srai.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_d(a: v2i64) -> v2i64 { @@ -8335,7 +8335,7 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srari.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { @@ -8352,7 +8352,7 @@ pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srari.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { @@ -8369,7 +8369,7 @@ pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srari.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { @@ -8386,7 +8386,7 @@ pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srari.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_d(a: v2i64) -> v2i64 { @@ -8462,7 +8462,7 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srli.b, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { @@ -8478,7 +8478,7 @@ pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srli.h, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { @@ -8494,7 +8494,7 @@ pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))] +#[cfg_attr(test, assert_instr(srli.w, IMM2 = 0b11))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { @@ -8510,7 +8510,7 @@ pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))] +#[cfg_attr(test, assert_instr(srli.d, IMM1 = 0b1))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_d(a: v2i64) -> v2i64 { @@ -8591,7 +8591,7 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))] +#[cfg_attr(test, assert_instr(srlri.b, IMM3 = 0b111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { @@ -8608,7 +8608,7 @@ pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))] +#[cfg_attr(test, assert_instr(srlri.h, IMM4 = 0b1111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { @@ -8625,7 +8625,7 @@ pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))] +#[cfg_attr(test, assert_instr(srlri.w, IMM5 = 0b11111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { @@ -8642,7 +8642,7 @@ pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))] +#[cfg_attr(test, assert_instr(srlri.d, IMM6 = 0b111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { @@ -8658,7 +8658,7 @@ pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))] +#[cfg_attr(test, assert_instr(st.b, IMM_S10 = -1))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () { @@ -8674,7 +8674,7 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))] +#[cfg_attr(test, assert_instr(st.h, IMM_S11 = -2))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () { @@ -8691,7 +8691,7 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))] +#[cfg_attr(test, assert_instr(st.w, IMM_S12 = -4))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () { @@ -8708,7 +8708,7 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))] +#[cfg_attr(test, assert_instr(st.d, IMM_S13 = -8))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8) -> () { @@ -9021,7 +9021,7 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.b, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { @@ -9037,7 +9037,7 @@ pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.h, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { @@ -9053,7 +9053,7 @@ pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.w, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { @@ -9069,7 +9069,7 @@ pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))] +#[cfg_attr(test, assert_instr(subvi.d, IMM5 = 0b10111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_d(a: v2i64) -> v2i64 { @@ -9173,7 +9173,7 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 { /// #[inline] #[target_feature(enable = "msa")] -#[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))] +#[cfg_attr(test, assert_instr(xori.b, IMM8 = 0b11111111))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_xori_b(a: v16u8) -> v16u8 { @@ -9602,7 +9602,7 @@ unsafe fn test_msa_addvi_b() { 103, -126, 103, -126 ); - assert_eq!(r, mem::transmute(__msa_addvi_b(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9618,7 +9618,7 @@ unsafe fn test_msa_addvi_h() { -32766, 3279, -97, -124 ); - assert_eq!(r, mem::transmute(__msa_addvi_h(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_h::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9628,7 +9628,7 @@ unsafe fn test_msa_addvi_w() { #[rustfmt::skip] let r = i32x4::new(103, -2147483646, 103, -2147483645); - assert_eq!(r, mem::transmute(__msa_addvi_w(mem::transmute(a), 67))); + assert_eq!(r, mem::transmute(__msa_addvi_w::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9638,7 +9638,7 @@ unsafe fn test_msa_addvi_d() { #[rustfmt::skip] let r = i64x2::new(117, -9223372036854775791); - assert_eq!(r, mem::transmute(__msa_addvi_d(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_addvi_d::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -9688,7 +9688,7 @@ unsafe fn test_msa_andi_b() { 4, 5, 4, 5 ); - assert_eq!(r, mem::transmute(__msa_andi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_andi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10233,7 +10233,7 @@ unsafe fn test_msa_bclri_b() { 247, 147, 55, 1 ); - assert_eq!(r, mem::transmute(__msa_bclri_b(mem::transmute(a), 3))); + assert_eq!(r, mem::transmute(__msa_bclri_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10243,7 +10243,7 @@ unsafe fn test_msa_bclri_h() { #[rustfmt::skip] let r = u16x8::new(107, 1155, 155, 1, 107, 1155, 155, 1); - assert_eq!(r, mem::transmute(__msa_bclri_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bclri_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10253,7 +10253,7 @@ unsafe fn test_msa_bclri_w() { #[rustfmt::skip] let r = u32x4::new(202722547, 102722547, 2722547, 1); - assert_eq!(r, mem::transmute(__msa_bclri_w(mem::transmute(a), 23))); + assert_eq!(r, mem::transmute(__msa_bclri_w::<23>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10263,7 +10263,7 @@ unsafe fn test_msa_bclri_d() { #[rustfmt::skip] let r = u64x2::new(73672157683, 11110973672157683); - assert_eq!(r, mem::transmute(__msa_bclri_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_bclri_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10408,7 +10408,7 @@ unsafe fn test_msa_binsli_b() { assert_eq!( r, - mem::transmute(__msa_binsli_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsli_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10432,7 +10432,7 @@ unsafe fn test_msa_binsli_h() { assert_eq!( r, - mem::transmute(__msa_binsli_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsli_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10447,7 +10447,7 @@ unsafe fn test_msa_binsli_w() { assert_eq!( r, - mem::transmute(__msa_binsli_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsli_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10462,7 +10462,7 @@ unsafe fn test_msa_binsli_d() { assert_eq!( r, - mem::transmute(__msa_binsli_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsli_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10608,7 +10608,7 @@ unsafe fn test_msa_binsri_b() { assert_eq!( r, - mem::transmute(__msa_binsri_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_binsri_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -10632,7 +10632,7 @@ unsafe fn test_msa_binsri_h() { assert_eq!( r, - mem::transmute(__msa_binsri_h(mem::transmute(a), mem::transmute(b), 13)) + mem::transmute(__msa_binsri_h::<13>(mem::transmute(a), mem::transmute(b))) ); } @@ -10647,7 +10647,7 @@ unsafe fn test_msa_binsri_w() { assert_eq!( r, - mem::transmute(__msa_binsri_w(mem::transmute(a), mem::transmute(b), 17)) + mem::transmute(__msa_binsri_w::<17>(mem::transmute(a), mem::transmute(b))) ); } @@ -10662,7 +10662,7 @@ unsafe fn test_msa_binsri_d() { assert_eq!( r, - mem::transmute(__msa_binsri_d(mem::transmute(a), mem::transmute(b), 48)) + mem::transmute(__msa_binsri_d::<48>(mem::transmute(a), mem::transmute(b))) ); } @@ -10733,7 +10733,7 @@ unsafe fn test_msa_bmnzi_b() { assert_eq!( r, - mem::transmute(__msa_bmnzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmnzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10804,7 +10804,7 @@ unsafe fn test_msa_bmzi_b() { assert_eq!( r, - mem::transmute(__msa_bmzi_b(mem::transmute(a), mem::transmute(b), 7)) + mem::transmute(__msa_bmzi_b::<7>(mem::transmute(a), mem::transmute(b))) ); } @@ -10900,7 +10900,7 @@ unsafe fn test_msa_bnegi_b() { 34, 116, 111, 239 ); - assert_eq!(r, mem::transmute(__msa_bnegi_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_bnegi_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10916,7 +10916,7 @@ unsafe fn test_msa_bnegi_h() { 30719, 1228, 2148, 2175 ); - assert_eq!(r, mem::transmute(__msa_bnegi_h(mem::transmute(a), 11))); + assert_eq!(r, mem::transmute(__msa_bnegi_h::<11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10926,7 +10926,7 @@ unsafe fn test_msa_bnegi_w() { #[rustfmt::skip] let r = u32x4::new(16777316, 2130706431, 16777316, 2164260864); - assert_eq!(r, mem::transmute(__msa_bnegi_w(mem::transmute(a), 24))); + assert_eq!(r, mem::transmute(__msa_bnegi_w::<24>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -10936,7 +10936,7 @@ unsafe fn test_msa_bnegi_d() { #[rustfmt::skip] let r = u64x2::new(4398046511204, 9223376434901286912); - assert_eq!(r, mem::transmute(__msa_bnegi_d(mem::transmute(a), 42))); + assert_eq!(r, mem::transmute(__msa_bnegi_d::<42>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11065,7 +11065,7 @@ unsafe fn test_msa_bseli_b() { assert_eq!( r, - mem::transmute(__msa_bseli_b(mem::transmute(a), mem::transmute(b), 121)) + mem::transmute(__msa_bseli_b::<121>(mem::transmute(a), mem::transmute(b))) ); } @@ -11161,7 +11161,7 @@ unsafe fn test_msa_bseti_b() { 255, 159, 55, 5 ); - assert_eq!(r, mem::transmute(__msa_bseti_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11171,7 +11171,7 @@ unsafe fn test_msa_bseti_h() { #[rustfmt::skip] let r = u16x8::new(255, 159, 55, 5, 255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11181,7 +11181,7 @@ unsafe fn test_msa_bseti_w() { #[rustfmt::skip] let r = u32x4::new(255, 159, 55, 5); - assert_eq!(r, mem::transmute(__msa_bseti_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11191,7 +11191,7 @@ unsafe fn test_msa_bseti_d() { #[rustfmt::skip] let r = u64x2::new(255, 159); - assert_eq!(r, mem::transmute(__msa_bseti_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_bseti_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11341,7 +11341,7 @@ unsafe fn test_msa_ceqi_b() { 0, 0, -1, 0 ); - assert_eq!(r, mem::transmute(__msa_ceqi_b(mem::transmute(a), -4))); + assert_eq!(r, mem::transmute(__msa_ceqi_b::<-4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11354,7 +11354,7 @@ unsafe fn test_msa_ceqi_h() { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_ceqi_h(mem::transmute(a), -11))); + assert_eq!(r, mem::transmute(__msa_ceqi_h::<-11>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11364,7 +11364,7 @@ unsafe fn test_msa_ceqi_w() { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_ceqi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_ceqi_w::<5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11551,7 +11551,7 @@ unsafe fn test_msa_clei_s_b() { #[rustfmt::skip] let r = i8x16::new(-1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1, -1, -1, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_b(mem::transmute(a), -2))); + assert_eq!(r, mem::transmute(__msa_clei_s_b::<-2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11564,7 +11564,7 @@ unsafe fn test_msa_clei_s_h() { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, -1, 0, 0, 0, -1); - assert_eq!(r, mem::transmute(__msa_clei_s_h(mem::transmute(a), -1))); + assert_eq!(r, mem::transmute(__msa_clei_s_h::<-1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11574,7 +11574,7 @@ unsafe fn test_msa_clei_s_w() { #[rustfmt::skip] let r = i32x4::new(0, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_s_w(mem::transmute(a), 6))); + assert_eq!(r, mem::transmute(__msa_clei_s_w::<6>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11607,7 +11607,7 @@ unsafe fn test_msa_clei_u_b() { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clei_u_b(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_b::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11620,7 +11620,7 @@ unsafe fn test_msa_clei_u_h() { #[rustfmt::skip] let r = i16x8::new(-1, 0, -1, 0, -1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_h(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_h::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11630,7 +11630,7 @@ unsafe fn test_msa_clei_u_w() { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_w(mem::transmute(a), 31))); + assert_eq!(r, mem::transmute(__msa_clei_u_w::<31>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11640,7 +11640,7 @@ unsafe fn test_msa_clei_u_d() { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clei_u_d(mem::transmute(a), 25))); + assert_eq!(r, mem::transmute(__msa_clei_u_d::<25>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11810,7 +11810,7 @@ unsafe fn test_msa_clti_s_b() { 0, -1, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_s_b(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_clti_s_b::<-5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11823,7 +11823,7 @@ unsafe fn test_msa_clti_s_h() { #[rustfmt::skip] let r = i16x8::new(-1, 0, 0, 0, -1, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_clti_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11833,7 +11833,7 @@ unsafe fn test_msa_clti_s_w() { #[rustfmt::skip] let r = i32x4::new(-1, 0, -1, 0); - assert_eq!(r, mem::transmute(__msa_clti_s_w(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_clti_s_w::<-10>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -11866,7 +11866,7 @@ unsafe fn test_msa_clti_u_b() { -1, 0, 0, 0 ); - assert_eq!(r, mem::transmute(__msa_clti_u_b(mem::transmute(a), 50))); + assert_eq!(r, mem::transmute(__msa_clti_u_b::<3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11879,7 +11879,7 @@ unsafe fn test_msa_clti_u_h() { #[rustfmt::skip] let r = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_h(mem::transmute(a), 30))); + assert_eq!(r, mem::transmute(__msa_clti_u_h::<30>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11889,7 +11889,7 @@ unsafe fn test_msa_clti_u_w() { #[rustfmt::skip] let r = i32x4::new(0, 0, 0, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_w(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_w::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11899,7 +11899,7 @@ unsafe fn test_msa_clti_u_d() { #[rustfmt::skip] let r = i64x2::new(-1, 0); - assert_eq!(r, mem::transmute(__msa_clti_u_d(mem::transmute(a), 10))); + assert_eq!(r, mem::transmute(__msa_clti_u_d::<10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11914,7 +11914,7 @@ unsafe fn test_msa_copy_s_b() { #[rustfmt::skip] let r = -100 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_s_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11927,7 +11927,7 @@ unsafe fn test_msa_copy_s_h() { #[rustfmt::skip] let r = 32767 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_s_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11936,7 +11936,7 @@ unsafe fn test_msa_copy_s_w() { let a = i32x4::new(100, 2147483647, 5, -2147483647); let r = 2147483647 as i32; - assert_eq!(r, mem::transmute(__msa_copy_s_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11946,7 +11946,7 @@ unsafe fn test_msa_copy_s_d() { #[rustfmt::skip] let r = 9223372036854775807 as i64; - assert_eq!(r, mem::transmute(__msa_copy_s_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_s_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11961,7 +11961,7 @@ unsafe fn test_msa_copy_u_b() { #[rustfmt::skip] let r = 100 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_b(mem::transmute(a), 12))); + assert_eq!(r, mem::transmute(__msa_copy_u_b::<12>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11974,7 +11974,7 @@ unsafe fn test_msa_copy_u_h() { #[rustfmt::skip] let r = 32767 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_h(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_copy_u_h::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11984,7 +11984,7 @@ unsafe fn test_msa_copy_u_w() { #[rustfmt::skip] let r = 2147483647 as u32; - assert_eq!(r, mem::transmute(__msa_copy_u_w(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_w::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -11994,7 +11994,7 @@ unsafe fn test_msa_copy_u_d() { #[rustfmt::skip] let r = 9223372036854775807 as u64; - assert_eq!(r, mem::transmute(__msa_copy_u_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_copy_u_d::<1>(mem::transmute(a)))); } // Can not be tested in user mode @@ -14618,7 +14618,10 @@ unsafe fn test_msa_insert_b() { 5, 127, 4, 127 ); - assert_eq!(r, mem::transmute(__msa_insert_b(mem::transmute(a), 12, 5))); + assert_eq!( + r, + mem::transmute(__msa_insert_b::<12>(mem::transmute(a), 5)) + ); } #[simd_test(enable = "msa")] @@ -14634,7 +14637,7 @@ unsafe fn test_msa_insert_h() { 5, 3276, 100, 11 ); - assert_eq!(r, mem::transmute(__msa_insert_h(mem::transmute(a), 4, 5))); + assert_eq!(r, mem::transmute(__msa_insert_h::<4>(mem::transmute(a), 5))); } #[simd_test(enable = "msa")] @@ -14644,7 +14647,7 @@ unsafe fn test_msa_insert_w() { #[rustfmt::skip] let r = i32x4::new(100, 7, 5, -2147483647); - assert_eq!(r, mem::transmute(__msa_insert_w(mem::transmute(a), 1, 7))); + assert_eq!(r, mem::transmute(__msa_insert_w::<1>(mem::transmute(a), 7))); } #[simd_test(enable = "msa")] @@ -14654,7 +14657,10 @@ unsafe fn test_msa_insert_d() { #[rustfmt::skip] let r = i64x2::new(3, 100); - assert_eq!(r, mem::transmute(__msa_insert_d(mem::transmute(a), 1, 100))); + assert_eq!( + r, + mem::transmute(__msa_insert_d::<1>(mem::transmute(a), 100)) + ); } #[simd_test(enable = "msa")] @@ -14683,7 +14689,7 @@ unsafe fn test_msa_insve_b() { assert_eq!( r, - mem::transmute(__msa_insve_b(mem::transmute(a), 12, mem::transmute(b))) + mem::transmute(__msa_insve_b::<12>(mem::transmute(a), mem::transmute(b))) ); } @@ -14707,7 +14713,7 @@ unsafe fn test_msa_insve_h() { assert_eq!( r, - mem::transmute(__msa_insve_h(mem::transmute(a), 4, mem::transmute(b))) + mem::transmute(__msa_insve_h::<4>(mem::transmute(a), mem::transmute(b))) ); } @@ -14722,7 +14728,7 @@ unsafe fn test_msa_insve_w() { assert_eq!( r, - mem::transmute(__msa_insve_w(mem::transmute(a), 3, mem::transmute(b))) + mem::transmute(__msa_insve_w::<3>(mem::transmute(a), mem::transmute(b))) ); } @@ -14737,7 +14743,7 @@ unsafe fn test_msa_insve_d() { assert_eq!( r, - mem::transmute(__msa_insve_d(mem::transmute(a), 1, mem::transmute(b))) + mem::transmute(__msa_insve_d::<1>(mem::transmute(a), mem::transmute(b))) ); } @@ -14759,7 +14765,7 @@ unsafe fn test_msa_ld_b() { 25, 26, 27, 28 ); - assert_eq!(r, mem::transmute(__msa_ld_b(p, 9))); + assert_eq!(r, mem::transmute(__msa_ld_b::<9>(p))); } #[simd_test(enable = "msa")] @@ -14773,7 +14779,7 @@ unsafe fn test_msa_ld_h() { #[rustfmt::skip] let r = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10); - assert_eq!(r, mem::transmute(__msa_ld_h(p, -2))); + assert_eq!(r, mem::transmute(__msa_ld_h::<-2>(p))); } #[simd_test(enable = "msa")] @@ -14784,7 +14790,7 @@ unsafe fn test_msa_ld_w() { #[rustfmt::skip] let r = i32x4::new(2, 3, 4, 5); - assert_eq!(r, mem::transmute(__msa_ld_w(p, -4))); + assert_eq!(r, mem::transmute(__msa_ld_w::<-4>(p))); } #[simd_test(enable = "msa")] @@ -14795,7 +14801,7 @@ unsafe fn test_msa_ld_d() { #[rustfmt::skip] let r = i64x2::new(0, 1); - assert_eq!(r, mem::transmute(__msa_ld_d(p, -32))); + assert_eq!(r, mem::transmute(__msa_ld_d::<-32>(p))); } #[simd_test(enable = "msa")] @@ -14808,7 +14814,7 @@ unsafe fn test_msa_ldi_b() { -20, -20, -20, -20 ); - assert_eq!(r, mem::transmute(__msa_ldi_b(-20))); + assert_eq!(r, mem::transmute(__msa_ldi_b::<-20>())); } #[simd_test(enable = "msa")] @@ -14819,7 +14825,7 @@ unsafe fn test_msa_ldi_h() { 255, 255, 255, 255 ); - assert_eq!(r, mem::transmute(__msa_ldi_h(255))); + assert_eq!(r, mem::transmute(__msa_ldi_h::<255>())); } #[simd_test(enable = "msa")] @@ -14827,7 +14833,7 @@ unsafe fn test_msa_ldi_w() { #[rustfmt::skip] let r = i32x4::new(-509, -509, -509, -509); - assert_eq!(r, mem::transmute(__msa_ldi_w(-509))); + assert_eq!(r, mem::transmute(__msa_ldi_w::<-509>())); } // FIXME: https://reviews.llvm.org/D59884 @@ -15288,7 +15294,7 @@ unsafe fn test_msa_maxi_s_b() { 1, -16, -6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_s_b(mem::transmute(a), -16))); + assert_eq!(r, mem::transmute(__msa_maxi_s_b::<-16>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15298,7 +15304,7 @@ unsafe fn test_msa_maxi_s_h() { #[rustfmt::skip] let r = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15); - assert_eq!(r, mem::transmute(__msa_maxi_s_h(mem::transmute(a), 15))); + assert_eq!(r, mem::transmute(__msa_maxi_s_h::<15>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15308,7 +15314,7 @@ unsafe fn test_msa_maxi_s_w() { #[rustfmt::skip] let r = i32x4::new(1, 3, -5, -5); - assert_eq!(r, mem::transmute(__msa_maxi_s_w(mem::transmute(a), -5))); + assert_eq!(r, mem::transmute(__msa_maxi_s_w::<-5>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15341,7 +15347,7 @@ unsafe fn test_msa_maxi_u_b() { 5, 5, 6, 8 ); - assert_eq!(r, mem::transmute(__msa_maxi_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15351,7 +15357,7 @@ unsafe fn test_msa_maxi_u_h() { #[rustfmt::skip] let r = u16x8::new(5, 5, 6, 8, 5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15361,7 +15367,7 @@ unsafe fn test_msa_maxi_u_w() { #[rustfmt::skip] let r = u32x4::new(5, 5, 6, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15371,7 +15377,7 @@ unsafe fn test_msa_maxi_u_d() { #[rustfmt::skip] let r = u64x2::new(5, 8); - assert_eq!(r, mem::transmute(__msa_maxi_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_maxi_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15541,7 +15547,7 @@ unsafe fn test_msa_mini_s_b() { -10, -10, -10, -10 ); - assert_eq!(r, mem::transmute(__msa_mini_s_b(mem::transmute(a), -10))); + assert_eq!(r, mem::transmute(__msa_mini_s_b::<-10>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15551,7 +15557,7 @@ unsafe fn test_msa_mini_s_h() { #[rustfmt::skip] let r = i16x8::new(-3, -3, -3, -4, -3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_h(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_h::<-3>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15561,7 +15567,7 @@ unsafe fn test_msa_mini_s_w() { #[rustfmt::skip] let r = i32x4::new(-3, -3, -3, -4); - assert_eq!(r, mem::transmute(__msa_mini_s_w(mem::transmute(a), -3))); + assert_eq!(r, mem::transmute(__msa_mini_s_w::<-3>(mem::transmute(a)))); } // FIXME: https://reviews.llvm.org/D59884 @@ -15669,7 +15675,7 @@ unsafe fn test_msa_mini_u_b() { 1, 3, 5, 5 ); - assert_eq!(r, mem::transmute(__msa_mini_u_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15679,7 +15685,7 @@ unsafe fn test_msa_mini_u_h() { #[rustfmt::skip] let r = u16x8::new(1, 3, 5, 5, 1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15689,7 +15695,7 @@ unsafe fn test_msa_mini_u_w() { #[rustfmt::skip] let r = u32x4::new(1, 3, 5, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -15699,7 +15705,7 @@ unsafe fn test_msa_mini_u_d() { #[rustfmt::skip] let r = u64x2::new(1, 5); - assert_eq!(r, mem::transmute(__msa_mini_u_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_mini_u_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16393,7 +16399,7 @@ unsafe fn test_msa_nori_b() { 242, 241, 240, 235 ); - assert_eq!(r, mem::transmute(__msa_nori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_nori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16443,7 +16449,7 @@ unsafe fn test_msa_ori_b() { 13, 14, 15, 20 ); - assert_eq!(r, mem::transmute(__msa_ori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_ori_b::<4>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16669,7 +16675,7 @@ unsafe fn test_msa_sat_s_b() { 3, 3, 3, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_s_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_s_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16682,7 +16688,7 @@ unsafe fn test_msa_sat_s_h() { #[rustfmt::skip] let r = i16x8::new(127, 127, 127, 1, 127, 127, 127, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_s_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16692,7 +16698,7 @@ unsafe fn test_msa_sat_s_w() { #[rustfmt::skip] let r = i32x4::new(131071, 131071, 131071, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_s_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16702,7 +16708,7 @@ unsafe fn test_msa_sat_s_d() { #[rustfmt::skip] let r = i64x2::new(137438953471, 1); - assert_eq!(r, mem::transmute(__msa_sat_s_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_s_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16722,7 +16728,7 @@ unsafe fn test_msa_sat_u_b() { 7, 7, 7, 1 ); - assert_eq!(r, mem::transmute(__msa_sat_u_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_sat_u_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16735,7 +16741,7 @@ unsafe fn test_msa_sat_u_h() { #[rustfmt::skip] let r = u16x8::new(255, 255, 155, 1, 255, 255, 155, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_h(mem::transmute(a), 7))); + assert_eq!(r, mem::transmute(__msa_sat_u_h::<7>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16745,7 +16751,7 @@ unsafe fn test_msa_sat_u_w() { #[rustfmt::skip] let r = u32x4::new(262143, 262143, 262143, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_w(mem::transmute(a), 17))); + assert_eq!(r, mem::transmute(__msa_sat_u_w::<17>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16755,7 +16761,7 @@ unsafe fn test_msa_sat_u_d() { #[rustfmt::skip] let r = u64x2::new(274877906943, 1); - assert_eq!(r, mem::transmute(__msa_sat_u_d(mem::transmute(a), 37))); + assert_eq!(r, mem::transmute(__msa_sat_u_d::<37>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16775,7 +16781,7 @@ unsafe fn test_msa_shf_b() { 11, 3, 4, 12 ); - assert_eq!(r, mem::transmute(__msa_shf_b(mem::transmute(a), 120))); + assert_eq!(r, mem::transmute(__msa_shf_b::<120>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16788,7 +16794,7 @@ unsafe fn test_msa_shf_h() { #[rustfmt::skip] let r = i16x8::new(11, 14, 12, 13, 11, 14, 12, 13); - assert_eq!(r, mem::transmute(__msa_shf_h(mem::transmute(a), 156))); + assert_eq!(r, mem::transmute(__msa_shf_h::<156>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16798,7 +16804,7 @@ unsafe fn test_msa_shf_w() { #[rustfmt::skip] let r = i32x4::new(1, 3, 2, 4); - assert_eq!(r, mem::transmute(__msa_shf_w(mem::transmute(a), 216))); + assert_eq!(r, mem::transmute(__msa_shf_w::<216>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -16902,7 +16908,7 @@ unsafe fn test_msa_sldi_b() { assert_eq!( r, - mem::transmute(__msa_sldi_b(mem::transmute(a), mem::transmute(b), 5)) + mem::transmute(__msa_sldi_b::<5>(mem::transmute(a), mem::transmute(b))) ); } @@ -16917,7 +16923,7 @@ unsafe fn test_msa_sldi_h() { assert_eq!( r, - mem::transmute(__msa_sldi_h(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_h::<2>(mem::transmute(a), mem::transmute(b))) ); } @@ -16932,7 +16938,7 @@ unsafe fn test_msa_sldi_w() { assert_eq!( r, - mem::transmute(__msa_sldi_w(mem::transmute(a), mem::transmute(b), 4)) + mem::transmute(__msa_sldi_w::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -16947,7 +16953,7 @@ unsafe fn test_msa_sldi_d() { assert_eq!( r, - mem::transmute(__msa_sldi_d(mem::transmute(a), mem::transmute(b), 2)) + mem::transmute(__msa_sldi_d::<0>(mem::transmute(a), mem::transmute(b))) ); } @@ -17043,7 +17049,7 @@ unsafe fn test_msa_slli_b() { 4, 8, 12, 16 ); - assert_eq!(r, mem::transmute(__msa_slli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17056,7 +17062,7 @@ unsafe fn test_msa_slli_h() { #[rustfmt::skip] let r = i16x8::new(4, 8, 12, 16, 4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17066,7 +17072,7 @@ unsafe fn test_msa_slli_w() { #[rustfmt::skip] let r = i32x4::new(4, 8, 12, 16); - assert_eq!(r, mem::transmute(__msa_slli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_slli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17076,7 +17082,7 @@ unsafe fn test_msa_slli_d() { #[rustfmt::skip] let r = i64x2::new(2, 4); - assert_eq!(r, mem::transmute(__msa_slli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_slli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17149,7 +17155,7 @@ unsafe fn test_msa_splati_b() { 3, 3, 3, 3 ); - assert_eq!(r, mem::transmute(__msa_splati_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17162,7 +17168,7 @@ unsafe fn test_msa_splati_h() { #[rustfmt::skip] let r = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17172,7 +17178,7 @@ unsafe fn test_msa_splati_w() { #[rustfmt::skip] let r = i32x4::new(3, 3, 3, 3); - assert_eq!(r, mem::transmute(__msa_splati_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_splati_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17182,7 +17188,7 @@ unsafe fn test_msa_splati_d() { #[rustfmt::skip] let r = i64x2::new(2, 2); - assert_eq!(r, mem::transmute(__msa_splati_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_splati_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17286,7 +17292,7 @@ unsafe fn test_msa_srai_b() { 31, 31, 13, 0 ); - assert_eq!(r, mem::transmute(__msa_srai_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17299,7 +17305,7 @@ unsafe fn test_msa_srai_h() { #[rustfmt::skip] let r = i16x8::new(8191, 31, 13, 0, 8191, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17308,7 +17314,7 @@ unsafe fn test_msa_srai_w() { let a = i32x4::new(i32::MAX, 125, 55, 1); let r = i32x4::new(536870911, 31, 13, 0); - assert_eq!(r, mem::transmute(__msa_srai_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17318,7 +17324,7 @@ unsafe fn test_msa_srai_d() { #[rustfmt::skip] let r = i64x2::new(2305843009213693951, 13); - assert_eq!(r, mem::transmute(__msa_srai_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srai_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17422,7 +17428,7 @@ unsafe fn test_msa_srari_b() { 31, 32, 14, 0 ); - assert_eq!(r, mem::transmute(__msa_srari_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17432,7 +17438,7 @@ unsafe fn test_msa_srari_h() { #[rustfmt::skip] let r = i16x8::new(539, 289, 39, 0, 539, 289, 39, 0); - assert_eq!(r, mem::transmute(__msa_srari_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17442,7 +17448,7 @@ unsafe fn test_msa_srari_w() { #[rustfmt::skip] let r = i32x4::new(52777789, 27777789, 2777789, 0); - assert_eq!(r, mem::transmute(__msa_srari_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17452,7 +17458,7 @@ unsafe fn test_msa_srari_d() { #[rustfmt::skip] let r = i64x2::new(52777777789, 27777777789); - assert_eq!(r, mem::transmute(__msa_srari_d(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srari_d::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17553,7 +17559,7 @@ unsafe fn test_msa_srli_b() { 6, 12, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17569,7 +17575,7 @@ unsafe fn test_msa_srli_h() { 8191, 819, 25, 31 ); - assert_eq!(r, mem::transmute(__msa_srli_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17579,7 +17585,7 @@ unsafe fn test_msa_srli_w() { #[rustfmt::skip] let r = i32x4::new(25, 536870911, 25, 536870911); - assert_eq!(r, mem::transmute(__msa_srli_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srli_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17589,7 +17595,7 @@ unsafe fn test_msa_srli_d() { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387903); - assert_eq!(r, mem::transmute(__msa_srli_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srli_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17689,7 +17695,7 @@ unsafe fn test_msa_srlri_b() { 6, 13, 25, 32 ); - assert_eq!(r, mem::transmute(__msa_srlri_b(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_b::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17701,7 +17707,7 @@ unsafe fn test_msa_srlri_h() { ); let r = i16x8::new(8192, 819, 25, 32, 8192, 819, 25, 32); - assert_eq!(r, mem::transmute(__msa_srlri_h(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_h::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17711,7 +17717,7 @@ unsafe fn test_msa_srlri_w() { #[rustfmt::skip] let r = i32x4::new(25, 38, 50, 536870912); - assert_eq!(r, mem::transmute(__msa_srlri_w(mem::transmute(a), 2))); + assert_eq!(r, mem::transmute(__msa_srlri_w::<2>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17721,7 +17727,7 @@ unsafe fn test_msa_srlri_d() { #[rustfmt::skip] let r = i64x2::new(50, 4611686018427387904); - assert_eq!(r, mem::transmute(__msa_srlri_d(mem::transmute(a), 1))); + assert_eq!(r, mem::transmute(__msa_srlri_d::<1>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -17747,7 +17753,7 @@ unsafe fn test_msa_st_b() { 21, 22, 23, 24, 25, 26, 27, 28 ]; - __msa_st_b(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_b::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17758,7 +17764,7 @@ unsafe fn test_msa_st_h() { let mut arr: [i16; 8] = [0, 0, 0, 0, 0, 0, 0, 0]; #[rustfmt::skip] let r : [i16; 8] = [13, 14, 15, 16, 17, 18, 19, 20]; - __msa_st_h(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_h::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17769,7 +17775,7 @@ unsafe fn test_msa_st_w() { let mut arr: [i32; 4] = [0, 0, 0, 0]; #[rustfmt::skip] let r : [i32; 4] = [13, 14, 15, 16]; - __msa_st_w(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_w::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -17780,7 +17786,7 @@ unsafe fn test_msa_st_d() { let mut arr: [i64; 2] = [0, 0]; #[rustfmt::skip] let r : [i64; 2] = [13, 14]; - __msa_st_d(mem::transmute(a), arr.as_mut_ptr() as *mut u8, 0); + __msa_st_d::<0>(mem::transmute(a), arr.as_mut_ptr() as *mut u8); assert_eq!(arr, r); } @@ -18194,7 +18200,7 @@ unsafe fn test_msa_subvi_b() { 95, 122, 45, 123 ); - assert_eq!(r, mem::transmute(__msa_subvi_b(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_b::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18210,7 +18216,7 @@ unsafe fn test_msa_subvi_h() { 32762, 3271, -105, 32763 ); - assert_eq!(r, mem::transmute(__msa_subvi_h(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_h::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18220,7 +18226,7 @@ unsafe fn test_msa_subvi_w() { #[rustfmt::skip] let r = i32x4::new(95, 145, 195, 2147483642); - assert_eq!(r, mem::transmute(__msa_subvi_w(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_w::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18230,7 +18236,7 @@ unsafe fn test_msa_subvi_d() { #[rustfmt::skip] let r = i64x2::new(95, 9223372036854775802); - assert_eq!(r, mem::transmute(__msa_subvi_d(mem::transmute(a), 5))); + assert_eq!(r, mem::transmute(__msa_subvi_d::<5>(mem::transmute(a)))); } #[simd_test(enable = "msa")] @@ -18392,6 +18398,6 @@ unsafe fn test_msa_xori_b() { 9, 10, 11, 20 ); - assert_eq!(r, mem::transmute(__msa_xori_b(mem::transmute(a), 4))); + assert_eq!(r, mem::transmute(__msa_xori_b::<4>(mem::transmute(a)))); } } diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs index f68121ad3171..78ec39f91ff3 100644 --- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs +++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs @@ -4700,10 +4700,10 @@ macro_rules! test_vec_2 { { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] fn $name() { - let a: s_t_l!($ty) = $ty::new($($a),+).into(); - let b: s_t_l!($ty) = $ty::new($($b),+).into(); + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); - let d = $ty_out::new($($d),+); + let d = $ty_out::from_array([$($d),+]); let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } @@ -4711,8 +4711,8 @@ fn $name() { { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { #[simd_test(enable = "altivec")] fn $name() { - let a: s_t_l!($ty) = $ty::new($($a),+).into(); - let b: s_t_l!($ty) = $ty::new($($b),+).into(); + let a: s_t_l!($ty) = $ty::from_array([$($a),+]).into(); + let b: s_t_l!($ty) = $ty::from_array([$($b),+]).into(); let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!($d, r); @@ -4728,7 +4728,7 @@ fn $name() { let d = vector_float::from(f32x4::new($($d),+)); let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) }); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); } }; @@ -6212,10 +6212,10 @@ macro_rules! test_vec_perm { [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+)); - let b = $longtype::from($shorttype::new($($b),+)); - let c = vector_unsigned_char::from(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); @@ -6664,7 +6664,7 @@ fn vec_ctf_u32() { let check = |a, b| { let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); }; @@ -6720,7 +6720,7 @@ fn vec_ctf_i32() { let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); println!("{:?} {:?}", a, b); - let e = m32x4::new(true, true, true, true); + let e = m32x4::splat(true); assert_eq!(e, r); }; diff --git a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs index 0aac23617340..4a7b561a20c5 100644 --- a/library/stdarch/crates/core_arch/src/powerpc/vsx.rs +++ b/library/stdarch/crates/core_arch/src/powerpc/vsx.rs @@ -238,14 +238,14 @@ macro_rules! test_vec_xxpermdi { {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vsx")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+, $($b),+)); - let b = $longtype::from($shorttype::new($($c),+, $($d),+)); + let a = $longtype::from($shorttype::from_array([$($a),+, $($b),+])); + let b = $longtype::from($shorttype::from_array([$($c),+, $($d),+])); unsafe { - assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); - assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); - assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); - assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); + assert_eq!($shorttype::from_array([$($a),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($c),+]), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); + assert_eq!($shorttype::from_array([$($a),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); + assert_eq!($shorttype::from_array([$($b),+, $($d),+]), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); } } } diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs index 376c912c0409..fc5af1b14d0c 100644 --- a/library/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs @@ -6463,10 +6463,10 @@ macro_rules! test_vec_perm { [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vector")] fn $name() { - let a = $longtype::from($shorttype::new($($a),+)); - let b = $longtype::from($shorttype::new($($b),+)); - let c = vector_unsigned_char::from(u8x16::new($($c),+)); - let d = $shorttype::new($($d),+); + let a = $longtype::from($shorttype::from_array([$($a),+])); + let b = $longtype::from($shorttype::from_array([$($b),+])); + let c = vector_unsigned_char::from(u8x16::from_array([$($c),+])); + let d = $shorttype::from_array([$($d),+]); let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); diff --git a/library/stdarch/crates/core_arch/src/simd.rs b/library/stdarch/crates/core_arch/src/simd.rs index 313c47479203..2c6829b465c4 100644 --- a/library/stdarch/crates/core_arch/src/simd.rs +++ b/library/stdarch/crates/core_arch/src/simd.rs @@ -20,6 +20,8 @@ pub(crate) unsafe trait SimdElement: Copy + const PartialEq + crate::fmt::Debug { + // SAFETY: all bits patterns of types implementing this trait must be valid + const ZERO: Self = unsafe { crate::mem::zeroed() }; } unsafe impl SimdElement for u8 {} @@ -42,8 +44,7 @@ unsafe impl SimdElement for f64 {} impl Simd { /// A value of this type where all elements are zeroed out. - // SAFETY: `T` implements `SimdElement`, so it is zeroable. - pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() }; + pub(crate) const ZERO: Self = Self::splat(T::ZERO); #[inline(always)] pub(crate) const fn from_array(elements: [T; N]) -> Self { @@ -100,6 +101,103 @@ fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { } } +impl Simd { + #[inline] + pub(crate) const fn new(x0: T) -> Self { + Self([x0]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T) -> Self { + Self([x0, x1]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T) -> Self { + Self([x0, x1, x2, x3]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new(x0: T, x1: T, x2: T, x3: T, x4: T, x5: T, x6: T, x7: T) -> Self { + Self([x0, x1, x2, x3, x4, x5, x6, x7]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, + ]) + } +} + +impl Simd { + #[inline] + pub(crate) const fn new( + x0: T, + x1: T, + x2: T, + x3: T, + x4: T, + x5: T, + x6: T, + x7: T, + x8: T, + x9: T, + x10: T, + x11: T, + x12: T, + x13: T, + x14: T, + x15: T, + x16: T, + x17: T, + x18: T, + x19: T, + x20: T, + x21: T, + x22: T, + x23: T, + x24: T, + x25: T, + x26: T, + x27: T, + x28: T, + x29: T, + x30: T, + x31: T, + ) -> Self { + Self([ + x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, + x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, + ]) + } +} + impl Simd { #[inline] pub(crate) const fn to_bits(self) -> Simd { @@ -142,19 +240,6 @@ pub(crate) const fn from_bits(bits: Simd) -> Self { } } -macro_rules! simd_ty { - ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = Simd<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: $elem_type),*) -> Self { - Self([$($param_name),*]) - } - } - } -} - #[repr(simd)] #[derive(Copy)] pub(crate) struct SimdM([T; N]); @@ -163,7 +248,6 @@ impl SimdM { #[inline(always)] const fn bool_to_internal(x: bool) -> T { // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid. - let zeros = const { unsafe { crate::mem::zeroed::() } }; let ones = const { // Ideally, this would be `transmute([0xFFu8; size_of::()])`, but // `size_of::()` is not allowed to use a generic parameter there. @@ -175,13 +259,24 @@ const fn bool_to_internal(x: bool) -> T { } unsafe { r.assume_init() } }; - [zeros, ones][x as usize] + [T::ZERO, ones][x as usize] + } + + #[inline] + pub(crate) const fn from_array(elements: [bool; N]) -> Self { + let mut internal = [T::ZERO; N]; + let mut i = 0; + while i < N { + internal[i] = Self::bool_to_internal(elements[i]); + i += 1; + } + Self(internal) } #[inline] #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] pub(crate) const fn splat(value: bool) -> Self { - unsafe { crate::intrinsics::simd::simd_splat(value) } + unsafe { crate::intrinsics::simd::simd_splat(Self::bool_to_internal(value)) } } #[inline] @@ -218,897 +313,98 @@ fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { } } -macro_rules! simd_m_ty { - ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => { - pub(crate) type $id = SimdM<$elem_type, $len>; - - impl $id { - #[inline(always)] - pub(crate) const fn new($($param_name: bool),*) -> Self { - Self([$(Self::bool_to_internal($param_name)),*]) - } - } - } -} - // 16-bit wide types: -simd_ty!(u8x2[u8;2]: x0, x1); -simd_ty!(i8x2[i8;2]: x0, x1); +pub(crate) type u8x2 = Simd; +pub(crate) type i8x2 = Simd; // 32-bit wide types: -simd_ty!(u8x4[u8;4]: x0, x1, x2, x3); -simd_ty!(u16x2[u16;2]: x0, x1); +pub(crate) type u8x4 = Simd; +pub(crate) type u16x2 = Simd; -simd_ty!(i8x4[i8;4]: x0, x1, x2, x3); -simd_ty!(i16x2[i16;2]: x0, x1); +pub(crate) type i8x4 = Simd; +pub(crate) type i16x2 = Simd; // 64-bit wide types: -simd_ty!( - u8x8[u8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u16x4[u16;4]: x0, x1, x2, x3); -simd_ty!(u32x2[u32;2]: x0, x1); -simd_ty!(u64x1[u64;1]: x1); +pub(crate) type u8x8 = Simd; +pub(crate) type u16x4 = Simd; +pub(crate) type u32x2 = Simd; +pub(crate) type u64x1 = Simd; -simd_ty!( - i8x8[i8;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i16x4[i16;4]: x0, x1, x2, x3); -simd_ty!(i32x2[i32;2]: x0, x1); -simd_ty!(i64x1[i64;1]: x1); +pub(crate) type i8x8 = Simd; +pub(crate) type i16x4 = Simd; +pub(crate) type i32x2 = Simd; +pub(crate) type i64x1 = Simd; -simd_ty!(f32x2[f32;2]: x0, x1); -simd_ty!(f64x1[f64;1]: x1); +pub(crate) type f16x4 = Simd; +pub(crate) type f32x2 = Simd; +pub(crate) type f64x1 = Simd; // 128-bit wide types: -simd_ty!( - u8x16[u8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u16x8[u16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u32x4[u32;4]: x0, x1, x2, x3); -simd_ty!(u64x2[u64;2]: x0, x1); +pub(crate) type u8x16 = Simd; +pub(crate) type u16x8 = Simd; +pub(crate) type u32x4 = Simd; +pub(crate) type u64x2 = Simd; -simd_ty!( - i8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i32x4[i32;4]: x0, x1, x2, x3); -simd_ty!(i64x2[i64;2]: x0, x1); +pub(crate) type i8x16 = Simd; +pub(crate) type i16x8 = Simd; +pub(crate) type i32x4 = Simd; +pub(crate) type i64x2 = Simd; -simd_ty!(f16x4[f16;4]: x0, x1, x2, x3); +pub(crate) type f16x8 = Simd; +pub(crate) type f32x4 = Simd; +pub(crate) type f64x2 = Simd; -simd_ty!( - f16x8[f16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f32x4[f32;4]: x0, x1, x2, x3); -simd_ty!(f64x2[f64;2]: x0, x1); - -simd_m_ty!( - m8x16[i8;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m16x8[i16;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_m_ty!(m32x4[i32;4]: x0, x1, x2, x3); -simd_m_ty!(m64x2[i64;2]: x0, x1); +pub(crate) type m8x16 = SimdM; +pub(crate) type m16x8 = SimdM; +pub(crate) type m32x4 = SimdM; +pub(crate) type m64x2 = SimdM; // 256-bit wide types: -simd_ty!( - u8x32[u8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u16x16[u16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - u32x8[u32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(u64x4[u64;4]: x0, x1, x2, x3); +pub(crate) type u8x32 = Simd; +pub(crate) type u16x16 = Simd; +pub(crate) type u32x8 = Simd; +pub(crate) type u64x4 = Simd; -simd_ty!( - i8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - i16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - i32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(i64x4[i64;4]: x0, x1, x2, x3); +pub(crate) type i8x32 = Simd; +pub(crate) type i16x16 = Simd; +pub(crate) type i32x8 = Simd; +pub(crate) type i64x4 = Simd; -simd_ty!( - f16x16[f16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_ty!( - f32x8[f32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); -simd_ty!(f64x4[f64;4]: x0, x1, x2, x3); +pub(crate) type f16x16 = Simd; +pub(crate) type f32x8 = Simd; +pub(crate) type f64x4 = Simd; -simd_m_ty!( - m8x32[i8;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_m_ty!( - m16x16[i16;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); -simd_m_ty!( - m32x8[i32;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type m8x32 = SimdM; +pub(crate) type m16x16 = SimdM; +pub(crate) type m32x8 = SimdM; // 512-bit wide types: -simd_ty!( - i8x64[i8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); +pub(crate) type u8x64 = Simd; +pub(crate) type u16x32 = Simd; +pub(crate) type u32x16 = Simd; +pub(crate) type u64x8 = Simd; -simd_ty!( - u8x64[u8;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); +pub(crate) type i8x64 = Simd; +pub(crate) type i16x32 = Simd; +pub(crate) type i32x16 = Simd; +pub(crate) type i64x8 = Simd; -simd_ty!( - i16x32[i16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); - -simd_ty!( - u16x32[u16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); - -simd_ty!( - i32x16[i32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - u32x16[u32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - f16x32[f16;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - f32x16[f32;16]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15 -); - -simd_ty!( - i64x8[i64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); - -simd_ty!( - u64x8[u64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); - -simd_ty!( - f64x8[f64;8]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7 -); +pub(crate) type f16x32 = Simd; +pub(crate) type f32x16 = Simd; +pub(crate) type f64x8 = Simd; // 1024-bit wide types: -simd_ty!( - u16x64[u16;64]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31, - x32, - x33, - x34, - x35, - x36, - x37, - x38, - x39, - x40, - x41, - x42, - x43, - x44, - x45, - x46, - x47, - x48, - x49, - x50, - x51, - x52, - x53, - x54, - x55, - x56, - x57, - x58, - x59, - x60, - x61, - x62, - x63 -); -simd_ty!( - i32x32[i32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); -simd_ty!( - u32x32[u32;32]: - x0, - x1, - x2, - x3, - x4, - x5, - x6, - x7, - x8, - x9, - x10, - x11, - x12, - x13, - x14, - x15, - x16, - x17, - x18, - x19, - x20, - x21, - x22, - x23, - x24, - x25, - x26, - x27, - x28, - x29, - x30, - x31 -); + +pub(crate) type u16x64 = Simd; +pub(crate) type u32x32 = Simd; + +pub(crate) type i32x32 = Simd; /// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they /// were before moving to array-based simd. diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs index 3730496e1ec3..0c725402a917 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -16807,12 +16807,12 @@ pub const fn _mm512_set_epi8( e0: i8, ) -> __m512i { unsafe { - let r = i8x64::new( + let r = i8x64::from_array([ e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19, e20, e21, e22, e23, e24, e25, e26, e27, e28, e29, e30, e31, e32, e33, e34, e35, e36, e37, e38, e39, e40, e41, e42, e43, e44, e45, e46, e47, e48, e49, e50, e51, e52, e53, e54, e55, e56, e57, e58, e59, e60, e61, e62, e63, - ); + ]); transmute(r) } } diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs index 9183eabd530c..867387290119 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse.rs @@ -2997,66 +2997,87 @@ fn test_mm_ucomineq_ss() { } } + macro_rules! test_mm_cvtss_si32_impl { + ($alias:ident) => { + let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; + let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; + for i in 0..inputs.len() { + let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); + let e = result[i]; + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; + } + #[simd_test(enable = "sse")] fn test_mm_cvtss_si32() { - let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; - let result = &[42i32, -3, i32::MIN, 0, i32::MIN, 2147483520]; - for i in 0..inputs.len() { - let x = _mm_setr_ps(inputs[i], 1.0, 3.0, 4.0); - let e = result[i]; - let r = _mm_cvtss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvtss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_mm_cvtss_si32_impl!(_mm_cvtss_si32); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvt_ss2si() { + test_mm_cvtss_si32_impl!(_mm_cvt_ss2si); + } + + macro_rules! test_cvttss_si32_impl { + ($alias:ident) => { + let inputs = &[ + (42.0f32, 42i32), + (-31.4, -31), + (-33.5, -33), + (-34.5, -34), + (10.999, 10), + (-5.99, -5), + (4.0e10, i32::MIN), + (4.0e-10, 0), + (NAN, i32::MIN), + (2147483500.1, 2147483520), + ]; + for (i, &(xi, e)) in inputs.iter().enumerate() { + let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); + let r = $alias(x); + assert_eq!(e, r, "TestCase #{} f({:?}) = {}, expected: {}", i, x, r, e); + } + }; } #[simd_test(enable = "sse")] fn test_mm_cvttss_si32() { - let inputs = &[ - (42.0f32, 42i32), - (-31.4, -31), - (-33.5, -33), - (-34.5, -34), - (10.999, 10), - (-5.99, -5), - (4.0e10, i32::MIN), - (4.0e-10, 0), - (NAN, i32::MIN), - (2147483500.1, 2147483520), - ]; - for (i, &(xi, e)) in inputs.iter().enumerate() { - let x = _mm_setr_ps(xi, 1.0, 3.0, 4.0); - let r = _mm_cvttss_si32(x); - assert_eq!( - e, r, - "TestCase #{} _mm_cvttss_si32({:?}) = {}, expected: {}", - i, x, r, e - ); - } + test_cvttss_si32_impl!(_mm_cvttss_si32); + } + + #[simd_test(enable = "sse")] + fn test_mm_cvtt_ss2si() { + test_cvttss_si32_impl!(_mm_cvtt_ss2si); + } + + macro_rules! test_mm_cvtsi32_ss_impl { + ($alias:ident) => { + let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); + + let r = $alias(a, 4555); + assert_eq_m128(_mm_setr_ps(4555.0, 6.0, 7.0, 8.0), r); + + let r = $alias(a, 322223333); + assert_eq_m128(_mm_setr_ps(322223333.0, 6.0, 7.0, 8.0), r); + + let r = $alias(a, -432); + assert_eq_m128(_mm_setr_ps(-432.0, 6.0, 7.0, 8.0), r); + + let r = $alias(a, -322223333); + assert_eq_m128(_mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0), r); + }; } #[simd_test(enable = "sse")] const fn test_mm_cvtsi32_ss() { - let a = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); + test_mm_cvtsi32_ss_impl!(_mm_cvtsi32_ss); + } - let r = _mm_cvtsi32_ss(a, 4555); - let e = _mm_setr_ps(4555.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); - - let r = _mm_cvtsi32_ss(a, 322223333); - let e = _mm_setr_ps(322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); - - let r = _mm_cvtsi32_ss(a, -432); - let e = _mm_setr_ps(-432.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); - - let r = _mm_cvtsi32_ss(a, -322223333); - let e = _mm_setr_ps(-322223333.0, 6.0, 7.0, 8.0); - assert_eq_m128(e, r); + #[simd_test(enable = "sse")] + fn test_mm_cvt_si2ss() { + test_mm_cvtsi32_ss_impl!(_mm_cvt_si2ss); } #[simd_test(enable = "sse")] @@ -3071,18 +3092,24 @@ const fn test_mm_set_ss() { assert_eq_m128(r, _mm_setr_ps(4.25, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_set1_ps_impl { + ($alias:ident) => { + let r = $alias(black_box(4.25)); + assert_eq!(get_m128(r, 0), 4.25); + assert_eq!(get_m128(r, 1), 4.25); + assert_eq!(get_m128(r, 2), 4.25); + assert_eq!(get_m128(r, 3), 4.25); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_set1_ps() { - let r1 = _mm_set1_ps(black_box(4.25)); - let r2 = _mm_set_ps1(black_box(4.25)); - assert_eq!(get_m128(r1, 0), 4.25); - assert_eq!(get_m128(r1, 1), 4.25); - assert_eq!(get_m128(r1, 2), 4.25); - assert_eq!(get_m128(r1, 3), 4.25); - assert_eq!(get_m128(r2, 0), 4.25); - assert_eq!(get_m128(r2, 1), 4.25); - assert_eq!(get_m128(r2, 2), 4.25); - assert_eq!(get_m128(r2, 3), 4.25); + test_mm_set1_ps_impl!(_mm_set1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_set_ps1() { + test_mm_set1_ps_impl!(_mm_set_ps1); } #[simd_test(enable = "sse")] @@ -3171,11 +3198,22 @@ const fn test_mm_load_ss() { assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0)); } + macro_rules! test_mm_load1_ps_impl { + ($alias:ident) => { + let a = 42.0f32; + let r = unsafe { $alias(ptr::addr_of!(a)) }; + assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_load1_ps() { - let a = 42.0f32; - let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) }; - assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); + test_mm_load1_ps_impl!(_mm_load1_ps); + } + + #[simd_test(enable = "sse")] + const fn test_mm_load_ps1() { + test_mm_load1_ps_impl!(_mm_load_ps1); } #[simd_test(enable = "sse")] @@ -3227,19 +3265,24 @@ const fn test_mm_store_ss() { assert_eq!(vals[2], 0.0); } + macro_rules! test_mm_store1_ps_impl { + ($alias:ident) => { + let mut vals = Memory { data: [0.0f32; 4] }; + let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); + let p = vals.data.as_mut_ptr(); + unsafe { $alias(p, *black_box(&a)) }; + assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + }; + } + #[simd_test(enable = "sse")] const fn test_mm_store1_ps() { - let mut vals = Memory { data: [0.0f32; 4] }; - let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); + test_mm_store1_ps_impl!(_mm_store1_ps); + } - // guaranteed to be aligned to 16 bytes - let p = vals.data.as_mut_ptr(); - - unsafe { - _mm_store1_ps(p, *black_box(&a)); - } - - assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); + #[simd_test(enable = "sse")] + const fn test_mm_store_ps1() { + test_mm_store1_ps_impl!(_mm_store_ps1); } #[simd_test(enable = "sse")] diff --git a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs index 65c179ef0d08..c1563a7364ce 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs @@ -12,6 +12,8 @@ #[serde(deny_unknown_fields)] struct ReturnType { value: String, + #[serde(rename = "element_bit_size")] + _element_bit_size: Option, } #[derive(Deserialize, Debug)] @@ -50,6 +52,8 @@ struct JsonIntrinsic { args_prep: Option>, #[serde(rename = "Architectures")] architectures: Vec, + #[serde(rename = "instructions")] + _instructions: Option>>, } pub fn get_neon_intrinsics( diff --git a/library/stdarch/crates/simd-test-macro/src/lib.rs b/library/stdarch/crates/simd-test-macro/src/lib.rs index 92bb40946e1f..9219540a1065 100644 --- a/library/stdarch/crates/simd-test-macro/src/lib.rs +++ b/library/stdarch/crates/simd-test-macro/src/lib.rs @@ -71,6 +71,7 @@ pub fn simd_test( "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected", "loongarch32" | "loongarch64" => "is_loongarch_feature_detected", "s390x" => "is_s390x_feature_detected", + "mips64" | "mips64el" => "is_mips64_feature_detected", t => panic!("unknown target: {t}"), }; let macro_test = Ident::new(macro_test, Span::call_site()); diff --git a/library/stdarch/crates/stdarch-gen-arm/README.md b/library/stdarch/crates/stdarch-gen-arm/README.md index 4da14bcbb6c9..970721681c04 100644 --- a/library/stdarch/crates/stdarch-gen-arm/README.md +++ b/library/stdarch/crates/stdarch-gen-arm/README.md @@ -1,11 +1,11 @@ # stdarch-gen-arm generator guide ## Running the generator -- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec` -``` -$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec - Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s - Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec` -``` + +Run: `cargo +nightly run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec crates/core_arch/src` + +NOTE: If you are running this from rust-lang/rust, you must be in the `library/stdarch` +working directory. + ## Input/Output ### Input files (intrinsic YAML definitions) - `crates/stdarch-gen-arm/spec//*.spec.yml` @@ -205,9 +205,6 @@ MatchKind: - `Array` - An array of expressions - Usage: `Array: [, ...]` -- `SvUndef` - - Returns the LLVM `undef` symbol - - Usage: `SvUndef` - `Multiply` - Simply `*` - Usage: `Multiply: [, ]` diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index e88860717b6d..a769d352649c 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -4031,17 +4031,10 @@ intrinsics: unsafe: [neon] assert_instr: [ld3] types: - - ['*const i64', int64x2x3_t, '*const int64x2_t', i64] - - ['*const f64', float64x2x3_t, '*const float64x2_t', f64] + - ['*const i64', int64x2x3_t, i64, "2"] + - ['*const f64', float64x2x3_t, f64, "2"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4174,17 +4167,11 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const f64', float64x2x4_t, f64, '*const float64x2_t'] - - ['*const i64', int64x2x4_t, i64, '*const int64x2_t'] + - ['*const f64', float64x2x4_t, f64, "2"] + - ['*const i64', int64x2x4_t, i64, "2"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] + - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 56b2252c9ef0..f6ef7f17d73b 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -5642,27 +5642,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x3_t, int8x8_t] - - [i16, int16x4x3_t, int16x4_t] - - [i32, int32x2x3_t, int32x2_t] - - [i8, int8x16x3_t, int8x16_t] - - [i16, int16x8x3_t, int16x8_t] - - [i32, int32x4x3_t, int32x4_t] - - [f32, float32x2x3_t, float32x2_t] - - [f32, float32x4x3_t, float32x4_t] + - [i8, int8x8x3_t, "8"] + - [i16, int16x4x3_t, "4"] + - [i32, int32x2x3_t, "2"] + - [i8, int8x16x3_t, "16"] + - [i16, int16x8x3_t, "8"] + - [i32, int32x4x3_t, "4"] + - [f32, float32x2x3_t, "2"] + - [f32, float32x4x3_t, "4"] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] - + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml new file mode 100644 index 000000000000..383e50b7cc70 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/spec/sve/aarch64.spec.yml @@ -0,0 +1,5201 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve] + llvm_prefix: llvm.aarch64.sve + +uses_neon_types: true +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +intrinsics: + - name: svacge[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facge.{sve_type}" } + + - name: svacgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "facgt.{sve_type}" } + + - name: svacle[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facge] + n_variant_op: op2 + compose: + - FnCall: ["svacge_{type}", [$pg, $op2, $op1]] + + - name: svaclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute compare less than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [facgt] + n_variant_op: op2 + compose: + - FnCall: ["svacgt_{type}", [$pg, $op2, $op1]] + + - name: svcadd[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[fcadd, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcadd.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $IMM_ROTATION]] + + - name: svcmla[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[fcmla, "IMM_ROTATION = 90"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: fcmla.{sve_type} + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$pg, $op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[fcmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: fcmla.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.f}add"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}add.{sve_type}" } + + - name: svqsub[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.x.{sve_type}" } + + - name: svcnt[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count nonzero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [cnt] + compose: + - LLVMLink: { name: "cnt.{sve_type[0]}" } + + - name: svcls[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading sign bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [i16, u16], [i32, u32], [i64, u64]] + zeroing_method: { drop: inactive } + assert_instr: [cls] + compose: + - LLVMLink: { name: "cls.{sve_type[0]}" } + + - name: svclz[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Count leading zero bits + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + zeroing_method: { drop: inactive } + assert_instr: [clz] + compose: + - LLVMLink: { name: "clz.{sve_type[0]}" } + + - name: svext{size_literal[1]}[_{type[0]}]{_mxz} + attr: [*sve-unstable] + substitutions: + sign_or_zero: + match_kind: "{type[0]}" + default: Sign + unsigned: Zero + kind_literal: { match_kind: "{type[0]}", default: s, unsigned: u } + doc: "{sign_or_zero}-extend the low {size[1]} bits" + arguments: + ["inactive: {sve_type[0]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + zeroing_method: { drop: inactive } + assert_instr: ["{type_kind[0].su}xt{size_literal[1]}"] + compose: + - LLVMLink: + name: "{type_kind[0].su}xt{size_literal[1]}.{sve_type[0]}" + + - name: svsqrt[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Square root + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { drop: inactive } + assert_instr: [fsqrt] + compose: + - LLVMLink: { name: "fsqrt.{sve_type}" } + + - name: svcmpeq[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmeq, default: cmpeq }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpeq.{sve_type}" } + + - name: svcmpeq_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + assert_instr: [cmpeq] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpeq.wide.{sve_type[0]}" } + + - name: svcmpge[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpge.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphs.{sve_type}" } + + - name: svcmpge_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + n_variant_op: op2 + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpge, unsigned: cmphs }] + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpge.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphs.wide.{sve_type[0]}" } + + - name: svcmpgt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type}" + - default: + LLVMLink: { name: "{type_kind.f}cmpgt.{sve_type}" } + unsigned: + LLVMLink: { name: "cmphi.{sve_type}" } + + - name: svcmpgt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare greater than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmpgt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmphi.wide.{sve_type[0]}" } + + - name: svcmple[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmge, default: cmpge, unsigned: cmphs }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpge_{type}", [$pg, $op2, $op1]] + + - name: svcmple_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than or equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmple, unsigned: cmpls }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmple.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmpls.wide.{sve_type[0]}" } + + - name: svcmplt[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare less than + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmgt, default: cmpgt, unsigned: cmphi }] + n_variant_op: op2 + compose: + - FnCall: ["svcmpgt_{type}", [$pg, $op2, $op1]] + + - name: svcmplt_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare less than + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: [{ default: cmplt, unsigned: cmplo }] + n_variant_op: op2 + compose: + - MatchKind: + - "{type[0]}" + - default: + LLVMLink: { name: "cmplt.wide.{sve_type[0]}" } + unsigned: + LLVMLink: { name: "cmplo.wide.{sve_type[0]}" } + + - name: svcmpne[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [{ float: fcmne, default: cmpne }] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}cmpne.{sve_type}" } + + - name: svcmpne_wide[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Compare not equal to + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{predicate[0]}" + types: [[[i8, i16, i32], i64]] + assert_instr: [cmpne] + n_variant_op: op2 + compose: + - LLVMLink: { name: "cmpne.wide.{sve_type[0]}" } + + - name: svcmpuo[{_n}_{type}] + attr: [*sve-unstable] + doc: Compare unordered with + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [f32, f64] + assert_instr: [fcmuo] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fcmpuo.{sve_type}" } + + - name: svcnt{size_literal} + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + return_type: u64 + types: [i8, i16, i32, i64] + assert_instr: + - default: { byte: rdvl, halfword: cnth, default: cntw, doubleword: cntd } + compose: + - FnCall: ["svcnt{size_literal}_pat", [], ["{{ svpattern::SV_ALL }}"]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: + - [rdvl, "PATTERN = {{ svpattern::SV_ALL }}"] + - ["cnt{size_literal}", "PATTERN = {{ svpattern::SV_MUL4 }}"] + types: [i8] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svcnt{size_literal}_pat + attr: [*sve-unstable] + doc: Count the number of {size}-bit elements in a vector + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: u64 + assert_instr: [["cnt{size_literal}", "PATTERN = {{ svpattern::SV_ALL }}"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: cnt{size_literal} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svlen[_{type}] + attr: [*sve-unstable] + doc: Count the number of elements in a full vector + arguments: ["_op: {sve_type}"] + return_type: "u64" + types: [i8, u8, i16, u16, i32, u32, f32, i64, u64, f64] + assert_instr: [{ default: { default: "cnt{size_literal}", byte: rdvl } }] + compose: + - FnCall: ["svcnt{size_literal}", []] + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup[_n]_{type}{_mxz} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + assert_instr: [mov] + compose: + - LLVMLink: { name: "dup.{sve_type}" } + + - name: svdup[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["op: bool"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [sbfx, whilelo] + compose: + - LLVMLink: { name: "dup.x.{sve_type}" } + + - name: svdup_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Broadcast a scalar value + arguments: ["data: {sve_type[0]}", "index: {type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - FnCall: + - svtbl_{type[0]} + - - $data + - FnCall: ["svdup_n_{type[1]}", [$index]] + + - name: svdupq_lane[_{type}] + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["data: {sve_type}", "index: u64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [tbl] + compose: + - LLVMLink: { name: "dupq.lane.{sve_type}" } + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + - "x8: {type}" + - "x9: {type}" + - "x10: {type}" + - "x11: {type}" + - "x12: {type}" + - "x13: {type}" + - "x14: {type}" + - "x15: {type}" + return_type: "{sve_type}" + types: [i8, u8] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.experimental.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - - $x0 + - $x1 + - $x2 + - $x3 + - $x4 + - $x5 + - $x6 + - $x7 + - $x8 + - $x9 + - $x10 + - $x11 + - $x12 + - $x13 + - $x14 + - $x15 + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b8] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + - "x8: bool" + - "x9: bool" + - "x10: bool" + - "x11: bool" + - "x12: bool" + - "x13: bool" + - "x14: bool" + - "x15: bool" + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s8 + - - CastAs: [$x0, i8] + - CastAs: [$x1, i8] + - CastAs: [$x2, i8] + - CastAs: [$x3, i8] + - CastAs: [$x4, i8] + - CastAs: [$x5, i8] + - CastAs: [$x6, i8] + - CastAs: [$x7, i8] + - CastAs: [$x8, i8] + - CastAs: [$x9, i8] + - CastAs: [$x10, i8] + - CastAs: [$x11, i8] + - CastAs: [$x12, i8] + - CastAs: [$x13, i8] + - CastAs: [$x14, i8] + - CastAs: [$x15, i8] + - FnCall: + - svcmpne_wide_s8 + - - FnCall: [svptrue_b8, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: + - "x0: {type}" + - "x1: {type}" + - "x2: {type}" + - "x3: {type}" + - "x4: {type}" + - "x5: {type}" + - "x6: {type}" + - "x7: {type}" + return_type: "{sve_type}" + types: [i16, u16] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.experimental.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: + - "crate::mem::transmute" + - - [$x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b16] + arguments: + - "x0: bool" + - "x1: bool" + - "x2: bool" + - "x3: bool" + - "x4: bool" + - "x5: bool" + - "x6: bool" + - "x7: bool" + return_type: svbool_t + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s16 + - - CastAs: [$x0, i16] + - CastAs: [$x1, i16] + - CastAs: [$x2, i16] + - CastAs: [$x3, i16] + - CastAs: [$x4, i16] + - CastAs: [$x5, i16] + - CastAs: [$x6, i16] + - CastAs: [$x7, i16] + - FnCall: + - svcmpne_wide_s16 + - - FnCall: [svptrue_b16, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}", "x2: {type}", "x3: {type}"] + return_type: "{sve_type}" + types: [f32, i32, u32] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.experimental.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1, $x2, $x3]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b32] + arguments: ["x0: bool", "x1: bool", "x2: bool", "x3: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: + - svdupq_n_s32 + - - CastAs: [$x0, i32] + - CastAs: [$x1, i32] + - CastAs: [$x2, i32] + - CastAs: [$x3, i32] + - FnCall: + - svcmpne_wide_s32 + - - FnCall: [svptrue_b32, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + arguments: ["x0: {type}", "x1: {type}"] + return_type: "{sve_type}" + types: [f64, i64, u64] + assert_instr: [] + compose: + - LLVMLink: + name: llvm.experimental.vector.insert.{sve_type}.{neon_type} + arguments: ["op0: {sve_type}", "op1: {neon_type}", "idx: i64"] + - Let: + - op + - FnCall: + - "{llvm_link}" + - - FnCall: ["svundef_{type}", [], [], true] + - FnCall: ["crate::mem::transmute", [[$x0, $x1]]] + - 0 + - FnCall: ["svdupq_lane_{type}", [$op, 0]] + + - name: svdupq[_n]_{type} + attr: [*sve-unstable] + doc: Broadcast a quadword of scalars + types: [b64] + arguments: ["x0: bool", "x1: bool"] + return_type: "svbool_t" + assert_instr: [] + compose: + - Let: + - op1 + - FnCall: [svdupq_n_s64, [CastAs: [$x0, i64], CastAs: [$x1, i64]]] + - FnCall: + - svcmpne_s64 + - - FnCall: [svptrue_b64, []] + - $op1 + - FnCall: [svdup_n_s64, [0]] + + - name: svcreate2[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of two vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create2", [$x0, $x1], [], true] + + - name: svcreate3[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of three vectors + arguments: ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create3", [$x0, $x1, $x2], [], true] + + - name: svcreate4[_{type}] + attr: [*sve-unstable] + doc: Create a tuple of four vectors + arguments: + ["x0: {sve_type}", "x1: {sve_type}", "x2: {sve_type}", "x3: {sve_type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_create4", [$x0, $x1, $x2, $x3], [], true] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized vector + arguments: [] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef2_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of two vectors + arguments: [] + return_type: "{sve_type_x2}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate2_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef3_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of three vectors + arguments: [] + return_type: "{sve_type_x3}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate3_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + - FnCall: ["svdup_n_{type}", ["0"]] + + - name: svundef4_{type} + attr: [*sve-unstable] + safety: + unsafe: [uninitialized] + doc: Create an uninitialized tuple of four vectors + arguments: [] + return_type: "{sve_type_x4}" + types: [f32, f64] + assert_instr: [] + compose: + - FnCall: + - "svcreate4_{type}" + - - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + - FnCall: ["svdup_n_{type}", ["0{type}"]] + + - name: svindex_{type} + attr: [*sve-unstable] + doc: Create linear series + arguments: ["base: {type}", "step: {type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [index] + compose: + - LLVMLink: { name: "index.{sve_type}" } + + - name: svget2[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of two vectors + arguments: ["tuple: {sve_type_x2}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget3[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of three vectors + arguments: ["tuple: {sve_type_x3}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svget4[_{type}] + attr: [*sve-unstable] + doc: Extract one vector from a tuple of four vectors + arguments: ["tuple: {sve_type_x4}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_get", [$tuple], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset2[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of two vectors + arguments: ["tuple: {sve_type_x2}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 1] }] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset3[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of three vectors + arguments: ["tuple: {sve_type_x3}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 2] }] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svset4[_{type}] + attr: [*sve-unstable] + doc: Change one vector in a tuple of four vectors + arguments: ["tuple: {sve_type_x4}", "x: {sve_type}"] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, range: [0, 3] }] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [] + compose: + - FnCall: ["crate::intrinsics::simd::scalable::sve_tuple_set", [$tuple, $x], ["_", "_", "{{IMM_INDEX}}"], true] + + - name: svzip1[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1.{sve_type}" } + + - name: svzip1_{type} + attr: [*sve-unstable] + doc: Interleave elements from low halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1.{sve_type}" } + + - name: svzip1q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from low halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip1] + compose: + - LLVMLink: { name: "zip1q.{sve_type}" } + + - name: svzip2[_{type}] + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2.{sve_type}" } + + - name: svzip2_{type} + attr: [*sve-unstable] + doc: Interleave elements from high halves of two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2.{sve_type}" } + + - name: svzip2q[_{type}] + attr: [*sve-unstable] + doc: Interleave quadwords from high halves of two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [zip2] + compose: + - LLVMLink: { name: "zip2q.{sve_type}" } + + - name: svuzp1[_{type}] + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1.{sve_type}" } + + - name: svuzp1_{type} + attr: [*sve-unstable] + doc: Concatenate even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1.{sve_type}" } + + - name: svuzp1q[_{type}] + attr: [*sve-unstable] + doc: Concatenate even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp1] + compose: + - LLVMLink: { name: "uzp1q.{sve_type}" } + + - name: svuzp2[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2.{sve_type}" } + + - name: svuzp2_{type} + attr: [*sve-unstable] + doc: Concatenate odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2.{sve_type}" } + + - name: svuzp2q[_{type}] + attr: [*sve-unstable] + doc: Concatenate odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [uzp2] + compose: + - LLVMLink: { name: "uzp2q.{sve_type}" } + + - name: svtrn1[_{type}] + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1.{sve_type}" } + + - name: svtrn1_{type} + attr: [*sve-unstable] + doc: Interleave even elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1.{sve_type}" } + + - name: svtrn1q[_{type}] + attr: [*sve-unstable] + doc: Interleave even quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn1] + compose: + - LLVMLink: { name: "trn1q.{sve_type}" } + + - name: svtrn2[_{type}] + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2.{sve_type}" } + + - name: svtrn2_{type} + attr: [*sve-unstable] + doc: Interleave odd elements from two inputs + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2.{sve_type}" } + + - name: svtrn2q[_{type}] + attr: [*sve-unstable] + doc: Interleave odd quadwords from two inputs + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [trn2] + compose: + - LLVMLink: { name: "trn2q.{sve_type}" } + + - name: svrev[_{type}] + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [rev] + compose: + - LLVMLink: { name: "rev.{sve_type}" } + + - name: svrev_{type} + attr: [*sve-unstable] + doc: Reverse all elements + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [b8, b16, b32, b64] + assert_instr: [rev] + compose: + - LLVMLink: { name: "rev.{sve_type}" } + + - name: svrevb[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bytes within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revb] + compose: + - LLVMLink: { name: "revb.{sve_type}" } + + - name: svrevh[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse halfwords within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i32, i64, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revh] + compose: + - LLVMLink: { name: "revh.{sve_type}" } + + - name: svrevw[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse words within elements + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i64, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [revw] + compose: + - LLVMLink: { name: "revw.{sve_type}" } + + - name: svrbit[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reverse bits + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: "inactive" } + assert_instr: [rbit] + compose: + - LLVMLink: { name: "rbit.{sve_type}" } + + - name: svext[_{type}] + attr: [*sve-unstable] + doc: Extract vector from pair of vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, sve_max_elems_type: "{type}" }] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[ext, "IMM3 = 1"]] + compose: + - LLVMLink: + name: ext.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsplice[_{type}] + attr: [*sve-unstable] + doc: Splice two vectors under predicate control + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [splice] + compose: + - LLVMLink: { name: "splice.{sve_type}" } + + - name: svinsr[_n_{type}] + attr: [*sve-unstable] + doc: Insert scalar in shifted vector + arguments: ["op1: {sve_type}", "op2: {type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [insr] + compose: + - LLVMLink: { name: "insr.{sve_type}" } + + - name: svld1[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1.{sve_type}" } + + - name: svld1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1]}" + + - name: svld1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1]}" + + - name: svld1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svld1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ld1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svld1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ld1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ld1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ld1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svld1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ld1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svld1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ld1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svld1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnt1.{sve_type}" } + + - name: svldnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnt1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svld1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ld1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svld1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ld1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ld1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svld1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld2[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld2.sret.{sve_type}" } + + - name: svld2_vnum[_{type}] + attr: [*sve-unstable] + doc: Load two-element tuples into two vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld2{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld3[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld3.sret.{sve_type}" } + + - name: svld3_vnum[_{type}] + attr: [*sve-unstable] + doc: Load three-element tuples into three vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld3{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld4[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld4.sret.{sve_type}" } + + - name: svld4_vnum[_{type}] + attr: [*sve-unstable] + doc: Load four-element tuples into four vectors + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld4{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svld4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svld1rq[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 128 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1rq{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1rq.{sve_type}" } + + - name: svld1ro[_{type}] + attr: [*sve-unstable] + doc: Load and replicate 256 bits of data + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + target_features: [f64mm] + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ld1ro{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ld1ro.{sve_type}" } + + - name: svldnf1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldnf1.{sve_type}" } + + - name: svldnf1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldnf1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldnf1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldnf1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnf1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldnf1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldnf1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldnf1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, non-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_non_faulting + - dereference: predicated_non_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldnf1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnf1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - LLVMLink: { name: "ldff1.{sve_type}" } + + - name: svldff1_vnum[_{type}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate}", "base: *{type}", "vnum: i64"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["ldff1{size_literal}"] + test: { load: 0 } + compose: + - FnCall: + - "svldff1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1s{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + + - name: svldff1u{size_literal[1]}_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.{sve_type[0] as {type[1]}}" + arguments: ["pg: {predicate[0]}", "base: *{type[1]}"] + return_type: "{sve_type[0] as {type[1]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base]] + - [Type: "{sve_type[0] as {type[1]}}", _] + + - name: svldff1s{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], i8] + - [[i32, i64, u32, u64], i16] + - [[i64, u64], i32] + assert_instr: ["ldff1s{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1s{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1u{size_literal[1]}_vnum_{type[0]} + attr: [*sve-unstable] + doc: Load {size[1]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset_vnum: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: ["pg: {predicate[0]}", "base: *{type[1]}", "vnum: i64"] + return_type: "{sve_type[0]}" + types: + - [[i16, i32, i64, u16, u32, u64], u8] + - [[i32, i64, u32, u64], u16] + - [[i64, u64], u32] + assert_instr: ["ldff1{size_literal[1]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1u{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + + - name: svldff1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1]}" + + - name: svldff1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1]}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1]}" + + - name: svldff1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldff1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldff1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldff1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], i16] + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], u16] + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldff1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i32, u32], [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldff1.gather.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldff1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldff1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - crate::intrinsics::simd::simd_cast + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + doc: Load {size[2]}-bit data and sign-extend, first-faulting + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldff1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["ldff1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldff1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, first-faulting + safety: + unsafe: + - pointer_offset: predicated_first_faulting + - dereference: predicated_first_faulting + - unpredictable_on_fault + - no_provenance: bases + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldff1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldff1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svrdffr_z + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: ["pg: svbool_t"] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - LLVMLink: { name: "rdffr.z" } + + - name: svrdffr + attr: [*sve-unstable] + doc: Read FFR, returning predicate of succesfully loaded elements + arguments: [] + return_type: svbool_t + assert_instr: [rdffr] + compose: + - FnCall: [svrdffr_z, [FnCall: [svptrue_b8, []]]] + + - name: svsetffr + attr: [*sve-unstable] + doc: Initialize the first-fault register to all-true + arguments: [] + assert_instr: [setffr] + compose: + - LLVMLink: { name: "setffr" } + + - name: svwrffr + attr: [*sve-unstable] + doc: Write to the first-fault register + arguments: ["op: svbool_t"] + assert_instr: [wrffr] + compose: + - LLVMLink: { name: "wrffr" } + + - name: svqinc{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qinc{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqinc{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qinc{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qinc{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqinc{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qinc{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqinc{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqinc{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating increment by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qinc{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qinc{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal[1]}[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - ["{type_kind[0].su}qdec{size_literal[1]}", "IMM_FACTOR = 1"] + compose: + - FnCall: + - "svqdec{size_literal[1]}_pat_n_{type[0]}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal[1]}_pat[_n_{type[0]}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type[1]}" + default: word + byte: byte + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {type[0]}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{type[0]}" + types: + - [[i32, i64, u32, u64], [i8, i16, i32, i64]] + assert_instr: + - - "{type_kind[0].su}qdec{size_literal[1]}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind[0].su}qdec{size_literal[1]}.n{size[0]}" + arguments: ["op: {type[0]}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{type[0]}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svqdec{size_literal}[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const IMM_FACTOR: i32"] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: [["{type_kind.su}qdec{size_literal}", "IMM_FACTOR = 1"]] + compose: + - FnCall: + - "svqdec{size_literal}_pat_{type}" + - [$op] + - ["{{svpattern::SV_ALL}}", $IMM_FACTOR] + + - name: svqdec{size_literal}_pat[_{type}] + attr: [*sve-unstable] + substitutions: + textual_size: + match_size: "{type}" + default: word + halfword: halfword + doubleword: doubleword + doc: Saturating decrement by number of {textual_size} elements + arguments: ["op: {sve_type}"] + static_defs: ["const PATTERN: svpattern", "const IMM_FACTOR: i32"] + constraints: [{ variable: IMM_FACTOR, range: [1, 16] }] + return_type: "{sve_type}" + types: [i16, u16, i32, u32, i64, u64] + assert_instr: + - - "{type_kind.su}qdec{size_literal}" + - "PATTERN = {{svpattern::SV_ALL}}, IMM_FACTOR = 1" + compose: + - LLVMLink: + name: "{type_kind.su}qdec{size_literal}.{sve_type}" + arguments: ["op: {sve_type}", "pattern: svpattern", "imm_factor: i32"] + return_type: "{sve_type}" + - FnCall: ["{llvm_link}", [$op, $PATTERN, $IMM_FACTOR]] + + - name: svst1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svst1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svst1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svst1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "st1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svst1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["st1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, i16] + - [[i32, u32], u32, u16] + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svst1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i32, u32], i32, [i8, i16]] + - [[i32, u32], u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "st1.scatter.{type_kind[0].su}xtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "st1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "st1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svst1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["st1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svst1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svstnt1[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "stnt1.{sve_type}" + arguments: + - "data: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: ["{llvm_link}", [$data, $pg, $base]] + + - name: svstnt1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["stnt1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svstnt1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1{size_literal[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate[0]}", "base: *mut {type[1]}", "data: {sve_type[0]}"] + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "st1.{sve_type[0] as {type[1]}}" + arguments: + - "data: {sve_type[0] as {type[1]}}" + - "pg: {predicate[0]}" + - "ptr: *mut {type[1]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base] + + - name: svst1{size_literal[1]}_vnum[_{type[0]}] + attr: [*sve-unstable] + doc: Truncate to {size[1]} bits and store + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "vnum: i64" + - "data: {sve_type[0]}" + types: + - [[i16, i32, i64], i8] + - [[u16, u32, u64], u8] + - [[i32, i64], i16] + - [[u32, u64], u16] + - [i64, i32] + - [u64, u32] + assert_instr: ["st1{size_literal[1]}"] + test: { store: 1 } + compose: + - FnCall: + - "svst1{size_literal[1]}_{type[0]}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: + [{ FnCall: ["svcnt{size_literal[0]}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst1_vnum[_{type}] + attr: [*sve-unstable] + doc: Non-truncating store + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + ["pg: {predicate}", "base: *mut {type}", "vnum: i64", "data: {sve_type}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st1{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst1_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst2[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x2}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st2.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type}", ["$data"], [0]] + - FnCall: ["svget2_{type}", ["$data"], [1]] + - "$pg" + - "$base" + + - name: svst2_vnum[_{type}] + attr: [*sve-unstable] + doc: Store two vectors into two-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x2}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st2{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst2_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst3[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x3}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st3.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget3_{type}", ["$data"], [0]] + - FnCall: ["svget3_{type}", ["$data"], [1]] + - FnCall: ["svget3_{type}", ["$data"], [2]] + - "$pg" + - "$base" + + - name: svst3_vnum[_{type}] + attr: [*sve-unstable] + doc: Store three vectors into three-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x3}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st3{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst3_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svst4[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + arguments: ["pg: {predicate}", "base: *mut {type}", "data: {sve_type_x4}"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - LLVMLink: + name: "st4.{sve_type}" + arguments: + - "data0: {sve_type}" + - "data1: {sve_type}" + - "data2: {sve_type}" + - "data3: {sve_type}" + - "pg: {predicate}" + - "ptr: *mut {type}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget4_{type}", ["$data"], [0]] + - FnCall: ["svget4_{type}", ["$data"], [1]] + - FnCall: ["svget4_{type}", ["$data"], [2]] + - FnCall: ["svget4_{type}", ["$data"], [3]] + - "$pg" + - "$base" + + - name: svst4_vnum[_{type}] + attr: [*sve-unstable] + doc: Store four vectors into four-element tuples + safety: + unsafe: + - pointer_offset_vnum: predicated + - dereference: predicated + arguments: + - "pg: {predicate}" + - "base: *mut {type}" + - "vnum: i64" + - "data: {sve_type_x4}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["st4{size_literal}"] + test: { store: 0 } + compose: + - FnCall: + - "svst4_{type}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - $data + + - name: svtbl[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table + arguments: ["data: {sve_type[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [tbl] + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + compose: + - LLVMLink: { name: "tbl.{sve_type[0]}" } + + - name: svwhilele_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilele, unsigned: whilels }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilele.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilels.{sve_type[1]}.{type[0]}" } } + + - name: svwhilelt_{type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While incrementing scalar is less than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilelt, unsigned: whilelo }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilelt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilelo.{sve_type[1]}.{type[0]}" } } + + - name: svmax[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind}max"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}max.{sve_type}" } + + - name: svmaxnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Maximum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fmaxnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}maxnm.{sve_type}" } + + - name: svpfalse[_b] + attr: [*sve-unstable] + doc: Set all predicate elements to false + arguments: [] + return_type: "svbool_t" + # TODO: With current implementation, `pfalse` isn't generated, will need to add intrinsic to + # generate `zeroinitializer` + # assert_instr: [pfalse] + compose: + - FnCall: + - "svdupq_n_b8" + - - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + - false + + - name: svptrue_pat_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + static_defs: ["const PATTERN: svpattern"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [[ptrue, "PATTERN = {{svpattern::SV_ALL}}"]] + compose: + - LLVMLink: + name: ptrue.{sve_type} + arguments: ["pattern: svpattern"] + - FnCall: ["{llvm_link}", [$PATTERN]] + + - name: svptrue_{type} + attr: [*sve-unstable] + doc: Set predicate elements to true + arguments: [] + return_type: "svbool_t" + types: [b8, b16, b32, b64] + assert_instr: [ptrue] + compose: + - FnCall: ["svptrue_pat_{type}", [], ["{{svpattern::SV_ALL}}"]] + + - name: svptest_any + attr: [*sve-unstable] + doc: Test whether any active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.any.nxv16i1" } + + - name: svptest_first + attr: [*sve-unstable] + doc: Test whether first active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.first.nxv16i1" } + + - name: svptest_last + attr: [*sve-unstable] + doc: Test whether last active element is true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "bool" + assert_instr: [ptest] + compose: + - LLVMLink: { name: "ptest.last.nxv16i1" } + + - name: svpfirst[_b] + attr: [*sve-unstable] + doc: Set the first active predicate element to true + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [pfirst] + compose: + - LLVMLink: { name: "pfirst.nxv16i1" } + + - name: svpnext_{type} + attr: [*sve-unstable] + doc: Find next active predicate + arguments: ["pg: {predicate}", "op: {predicate}"] + return_type: "{predicate}" + types: [b8, b16, b32, b64] + assert_instr: [pnext] + compose: + - LLVMLink: { name: "pnext.{sve_type}" } + + - name: svbrkn[_b]_z + attr: [*sve-unstable] + doc: Propagate break to next partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkn] + compose: + - LLVMLink: { name: "brkn.z.nxv16i1" } + + - name: svbrkb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.z.nxv16i1" } + + - name: svbrkb[_b]_m + attr: [*sve-unstable] + doc: Break before first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkb] + compose: + - LLVMLink: { name: "brkb.nxv16i1" } + + - name: svbrkpb[_b]_z + attr: [*sve-unstable] + doc: Break before first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpb] + compose: + - LLVMLink: { name: "brkpb.z.nxv16i1" } + + - name: svbrka[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.z.nxv16i1" } + + - name: svbrka[_b]_m + attr: [*sve-unstable] + doc: Break after first true condition + arguments: ["inactive: svbool_t", "pg: svbool_t", "op: svbool_t"] + return_type: "svbool_t" + assert_instr: [brka] + compose: + - LLVMLink: { name: "brka.nxv16i1" } + + - name: svbrkpa[_b]_z + attr: [*sve-unstable] + doc: Break after first true condition, propagating from previous partition + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [brkpa] + compose: + - LLVMLink: { name: "brkpa.z.nxv16i1" } + + - name: svsel[_b] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: "svbool_t" + assert_instr: [sel] + compose: + - FnCall: ["simd_select", [$pg, $op1, $op2]] + + - name: svsel[_{type}] + attr: [*sve-unstable] + doc: Conditionally select elements + arguments: ["pg: svbool_t", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [sel] + compose: + - FnCall: + - "simd_select" + - - MatchSize: + - "{type}" + - { default: { MethodCall: [$pg, sve_into, []] }, byte: $pg } + - $op1 + - $op2 + - - MatchSize: + - "{type}" + - byte: svbool_t + halfword: svbool8_t + default: svbool4_t + doubleword: svbool2_t + - _ + + - name: svsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}sub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}sub.{sve_type}" } + + - name: svsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64, f32, f64] + assert_instr: ["{type_kind.f}subr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}subr.{sve_type}" } + + - name: svcntp_{predicate} + attr: [*sve-unstable] + doc: Count set predicate bits + arguments: ["pg: {predicate}", "op: {predicate}"] + types: [b8, b16, b32, b64] + return_type: u64 + assert_instr: [cntp] + compose: + - LLVMLink: { name: "cntp.{predicate}" } + + - name: svcompact[_{type}] + attr: [*sve-unstable] + doc: Shuffle active elements of vector to the right and fill with zero + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: [compact] + compose: + - LLVMLink: { name: "compact.{sve_type}" } + + - name: svlasta[_{type}] + attr: [*sve-unstable] + doc: Extract element after last + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lasta] + compose: + - LLVMLink: { name: "lasta.{sve_type}" } + + - name: svclasta[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.{sve_type}" } + + - name: svclasta[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract element after last + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clasta] + compose: + - LLVMLink: { name: "clasta.n.{sve_type}" } + + - name: svlastb[_{type}] + attr: [*sve-unstable] + doc: Extract last element + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [lastb] + compose: + - LLVMLink: { name: "lastb.{sve_type}" } + + - name: svclastb[_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {sve_type}", "data: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.{sve_type}" } + + - name: svclastb[_n_{type}] + attr: [*sve-unstable] + doc: Conditionally extract last element + arguments: ["pg: {predicate}", "fallback: {type}", "data: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [clastb] + compose: + - LLVMLink: { name: "clastb.n.{sve_type}" } + + - name: svqdecp[_{type}] + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind.su}qdecp.{sve_type}" } + + - name: svqdecp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating decrement by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qdecp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qdecp.n{size[0]}.{sve_type[1]}" } + + - name: svqincp[_{type}] + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {sve_type}", "pg: {predicate}"] + return_type: "{sve_type}" + types: [i16, i32, i64, u16, u32, u64] + assert_instr: ["{type_kind.su}qincp"] + compose: + - LLVMLink: { name: "{type_kind.su}qincp.{sve_type}" } + + - name: svqincp[_n_{type[0]}]_{type[1]} + attr: [*sve-unstable] + doc: Saturating increment by active element count + arguments: ["op: {type[0]}", "pg: {sve_type[1]}"] + return_type: "{type[0]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: ["{type_kind[0].su}qincp"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qincp.n{size[0]}.{sve_type[1]}" } + + - name: svtmad[_{type}] + attr: [*sve-unstable] + doc: Trigonometric multiply-add coefficient + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: [0, 7] }] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [[ftmad, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "ftmad.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: + - "{llvm_link}" + - [op1, op2, IMM3] + + - name: svtsmul[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric starting value + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftsmul] + compose: + - LLVMLink: + name: "ftsmul.x.{sve_type[0]}" + + - name: svtssel[_{type[0]}] + attr: [*sve-unstable] + doc: Trigonometric select coefficient + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + assert_instr: [ftssel] + compose: + - LLVMLink: + name: "ftssel.x.{sve_type[0]}" + + - name: svprf{size_literal} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf.{sve_type}" + arguments: + ["pg: {predicate}", "base: *crate::ffi::c_void", "op: svprfop"] + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - $OP + + - name: svprf{size_literal}_vnum + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset_vnum: predicated + substitutions: + textual_size: + match_size: "{type}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + arguments: ["pg: {predicate}", "base: *T", "vnum: i64"] + static_defs: ["const OP: svprfop", T] + types: [b8, b16, b32, b64] + assert_instr: + - ["prf{size_literal}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"] + test: { load: 0 } + compose: + - FnCall: + - "svprf{size_literal}" + - - $pg + - MethodCall: + - $base + - offset + - - Multiply: + - CastAs: [{ FnCall: ["svcnt{size_literal}", []] }, isize] + - CastAs: [$vnum, isize] + - - $OP + - _ + + - name: svprf{size_literal[1]}_gather_[{type[0]}]{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + indices_or_offsets: + { match_size: "{type[1]}", default: "indices", byte: "offsets" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[i32, u32, i64, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "base: *T", "{indices_or_offsets}: {sve_type[0]}"] + static_defs: ["const OP: svprfop", T] + assert_instr: + [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}, T = i64"]] + test: { load: 0 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "prf{size_literal[1]}.gather.{type_kind[0].su}xtw.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + doubleword: + LLVMLink: + name: "prf{size_literal[1]}.gather.index.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "base: *crate::ffi::c_void" + - "{indices_or_offsets}: {sve_type[0]}" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - CastAs: [$base, "*const crate::ffi::c_void"] + - "${indices_or_offsets}" + - $OP + + - name: svprf{size_literal[1]}_gather[_{type[0]}base] + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prf{size_literal[1]}", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "op: svprfop" + - FnCall: ["{llvm_link}", [$pg, $bases, 0, $OP]] + + - name: svprf{size_literal[1]}_gather[_{type[0]}base]_{index_or_offset} + attr: [*sve-unstable] + safety: + unsafe: + - pointer_offset: predicated + - no_provenance: bases + substitutions: + index_or_offset: + { match_size: "{type[1]}", default: "index", byte: "offset" } + textual_size: + match_size: "{type[1]}" + default: words + byte: bytes + halfword: halfwords + doubleword: doublewords + doc: Prefetch {textual_size} + types: + - [[u32, u64], [i8, i16, i32, i64]] + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "{index_or_offset}: i64"] + static_defs: ["const OP: svprfop"] + assert_instr: [["prfb", "OP = {{svprfop::SV_PLDL1KEEP}}"]] + test: { load: 0 } + compose: + - LLVMLink: + name: "prf{size_literal[1]}.gather.scalar.offset.{sve_type[0]}" + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "{index_or_offset}: i64" + - "op: svprfop" + - FnCall: + - "{llvm_link}" + - - $pg + - $bases + - MatchSize: + - "{type[1]}" + - byte: $offset + halfword: { MethodCall: [$index, unchecked_shl, [1]] } + default: { MethodCall: [$index, unchecked_shl, [2]] } + doubleword: { MethodCall: [$index, unchecked_shl, [3]] } + - $OP + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[f32, f64], [i32, u32, i64, u64]] + zeroing_method: { drop: inactive } + substitutions: + convert_from: { match_kind: "{type[1]}", default: s, unsigned: u } + assert_instr: ["{convert_from}cvtf"] + compose: + - LLVMLink: + name: "{convert_from}cvtf.{type[0]}{type[1]}" + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i32, u32, i64, u64], [f32, f64]] + zeroing_method: { drop: inactive } + substitutions: + convert_to: { match_kind: "{type[0]}", default: s, unsigned: u } + assert_instr: ["fcvtz{convert_to}"] + compose: + - LLVMLink: { name: "fcvtz{convert_to}.{type[0]}{type[1]}" } + + - name: svcvt_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Floating-point convert + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64], [f64, f32]] + zeroing_method: { drop: inactive } + assert_instr: [fcvt] + compose: + - LLVMLink: { name: "fcvt.{type[0]}{type[1]}" } + + - name: svreinterpret_{type[0]}[_{type[1]}] + attr: [*sve-unstable] + doc: Reinterpret vector contents + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + assert_instr: [] + types: + - - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + - [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + + - name: svrinta[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties away from zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinta] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinta.{sve_type}" } + + - name: svrinti[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (inexact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frinti] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frinti.{sve_type}" } + + - name: svrintm[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards -∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintm] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintm.{sve_type}" } + + - name: svrintn[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round to nearest, ties to even + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintn] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintn.{sve_type}" } + + - name: svrintp[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards +∞ + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintp] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintp.{sve_type}" } + + - name: svrintx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round using current rounding mode (exact) + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintx.{sve_type}" } + + - name: svrintz[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Round towards zero + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frintz] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frintz.{sve_type}" } + + - name: svabd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute difference + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f64, f32, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}abd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind}abd.{sve_type}" } + + - name: svabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}abs"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}abs.{sve_type}" } + + - name: svand[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [and] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "and.{sve_type}" } + + - name: svandv[_{type}] + attr: [*sve-unstable] + doc: Bitwise AND reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [andv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "andv.{sve_type}" } + + - name: svand[_b]_z + attr: [*sve-unstable] + doc: Bitwise AND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [and] + compose: + - LLVMLink: { name: "and.z.nvx16i1" } + + - name: svmov[_b]_z + attr: [*sve-unstable] + doc: Move + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [mov] + compose: + - FnCall: ["svand_b_z", [$pg, $op, $op]] + + - name: svbic[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bic] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "bic.{sve_type}" } + + - name: svbic[_b]_z + attr: [*sve-unstable] + doc: Bitwise clear + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [bic] + compose: + - LLVMLink: { name: "bic.z.nvx16i1" } + + - name: sveor[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "eor.{sve_type}" } + + - name: sveorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [eorv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "eorv.{sve_type}" } + + - name: sveor[_b]_z + attr: [*sve-unstable] + doc: Bitwise exclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [eor] + compose: + - LLVMLink: { name: "eor.z.nvx16i1" } + + - name: svnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [not] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "not.{sve_type}" } + + - name: svnot[_b]_z + attr: [*sve-unstable] + doc: Bitwise invert + arguments: ["pg: svbool_t", "op: svbool_t"] + return_type: svbool_t + assert_instr: [not] + compose: + - FnCall: ["sveor_b_z", [$pg, $op, $pg]] + + - name: svcnot[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logically invert boolean condition + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [cnot] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "cnot.{sve_type}" } + + - name: svnand[_b]_z + attr: [*sve-unstable] + doc: Bitwise NAND + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nand] + compose: + - LLVMLink: { name: "nand.z.nxv16i1" } + + - name: svnor[_b]_z + attr: [*sve-unstable] + doc: Bitwise NOR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [nor] + compose: + - LLVMLink: { name: "nor.z.nxv16i1" } + + - name: svorr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [orr] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "orr.{sve_type}" } + + - name: svorv[_{type}] + attr: [*sve-unstable] + doc: Bitwise inclusive OR reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [orv] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: { name: "orv.{sve_type}" } + + - name: svorr[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orr] + compose: + - LLVMLink: { name: "orr.z.nvx16i1" } + + - name: svorn[_b]_z + attr: [*sve-unstable] + doc: Bitwise inclusive OR, inverting second argument + arguments: ["pg: svbool_t", "op1: svbool_t", "op2: svbool_t"] + return_type: svbool_t + assert_instr: [orn] + compose: + - LLVMLink: { name: "orn.z.nvx16i1" } + + - name: svlsl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], u8] + - [[i16, u16], u16] + - [[i32, u32], u32] + - [[i64, u64], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.{sve_type[0]}" } + + - name: svlsl_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32, u8, u16, u32], u64] + assert_instr: [lsl] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsl.wide.{sve_type[0]}" } + + - name: svasr[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.{sve_type[0]}" } + + - name: svasr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, i16, i32], u64] + assert_instr: [asr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "asr.wide.{sve_type[0]}" } + + - name: svasrd[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Arithmetic shift right for divide by immediate + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64] + assert_instr: [[asrd, "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "asrd.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svlsr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.{sve_type}" } + + - name: svlsr_wide[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Logical shift right + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[u8, u16, u32], u64] + assert_instr: [lsr] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "lsr.wide.{sve_type[0]}" } + + - name: svadda[_{type}] + attr: [*sve-unstable] + doc: Add reduction (strictly-ordered) + arguments: ["pg: {predicate}", "initial: {type}", "op: {sve_type}"] + return_type: "{type}" + assert_instr: [fadda] + types: [f32, f64] + compose: + - LLVMLink: { name: "fadda.{sve_type}" } + + - name: svaddv[_{type}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i64, u64] + assert_instr: [{ float: faddv, default: uaddv }] + compose: + - LLVMLink: { name: "{type_kind.fsu}addv.{sve_type}" } + + - name: svaddv[_{type[0]}] + attr: [*sve-unstable] + doc: Add reduction + arguments: ["pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{type[1]}" + types: + - [[i8, i16, i32], i64] + - [[u8, u16, u32], u64] + assert_instr: ["{type_kind[0].su}addv"] + compose: + - LLVMLink: { name: "{type_kind[0].su}addv.{sve_type[0]}" } + + - name: svmaxv[_{type}] + attr: [*sve-unstable] + doc: Maximum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxv.{sve_type}" } + + - name: svmaxnmv[_{type}] + attr: [*sve-unstable] + doc: Maximum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fmaxnmv] + compose: + - LLVMLink: { name: "fmaxnmv.{sve_type}" } + + - name: svminv[_{type}] + attr: [*sve-unstable] + doc: Minimum reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minv"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minv.{sve_type}" } + + - name: svminnmv[_{type}] + attr: [*sve-unstable] + doc: Minimum number reduction to scalar + arguments: ["pg: {predicate}", "op: {sve_type}"] + return_type: "{type}" + types: [f32, f64] + assert_instr: [fminnmv] + compose: + - LLVMLink: { name: "fminnmv.{sve_type}" } + + - name: svmul[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.f}mul"] + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.f}mul.{sve_type}" } + + - name: svmulh[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply, returning high-half + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["{type_kind.su}mulh"] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}mulh.{sve_type}" } + + - name: svmulx[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply extended (∞×0=2) + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: ["fmulx"] + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fmulx.{sve_type}" } + + - name: svrecpe[_{type}] + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpe] + compose: + - LLVMLink: { name: "frecpe.x.{sve_type}" } + + - name: svrecps[_{type}] + attr: [*sve-unstable] + doc: Reciprocal step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecps] + compose: + - LLVMLink: { name: "frecps.x.{sve_type}" } + + - name: svrecpx[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal exponent + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frecpx] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "frecpx.x.{sve_type}" } + + - name: svrsqrte[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrte] + compose: + - LLVMLink: { name: "frsqrte.x.{sve_type}" } + + - name: svrsqrts[_{type}] + attr: [*sve-unstable] + doc: Reciprocal square root step + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: [frsqrts] + compose: + - LLVMLink: { name: "frsqrts.x.{sve_type}" } + + - name: svmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mad"] + compose: + - LLVMLink: { name: "{type_kind.f}mad.{sve_type}" } + + - name: svmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mla"] + compose: + - LLVMLink: { name: "{type_kind.f}mla.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}mls"] + compose: + - LLVMLink: { name: "{type_kind.f}mls.{sve_type}" } + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [f32, f64] + assert_instr: [[fmls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "fmls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: ["{type_kind.f}msb"] + compose: + - LLVMLink: { name: "{type_kind.f}msb.{sve_type}" } + + - name: svnmad[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmad] + compose: + - LLVMLink: { name: "fnmad.{sve_type}" } + + - name: svnmla[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-add, addend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmla] + compose: + - LLVMLink: { name: "fnmla.{sve_type}" } + + - name: svnmls[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, minuend first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmls] + compose: + - LLVMLink: { name: "fnmls.{sve_type}" } + + - name: svnmsb[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negated multiply-subtract, multiplicand first + arguments: + - "pg: {predicate}" + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + n_variant_op: op3 + assert_instr: [fnmsb] + compose: + - LLVMLink: { name: "fnmsb.{sve_type}" } + + - name: svneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64] + assert_instr: ["{type_kind.f}neg"] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "{type_kind.f}neg.{sve_type}" } + + - name: svqadd[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating add + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.x.{sve_type}" } + + - name: svadr{size_literal[2]}[_{type[0]}base]_[{type[1]}]{index_or_offset} + attr: [*sve-unstable] + substitutions: + index_or_offset: { match_size: "{type[2]}", default: index, byte: offset } + indices_or_offsets: + { match_size: "{type[2]}", default: indices, byte: offsets } + doc: Compute vector addresses for {size[2]}-bit data + arguments: ["bases: {sve_type[0]}", "{indices_or_offsets}: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u32, [i32, u32], [i8, i16, i32, i64]] + - [u64, [i64, u64], [i8, i16, i32, i64]] + assert_instr: [adr] + compose: + - LLVMLink: { name: "adr{size_literal[2]}.{sve_type[0]}" } + + - name: svdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: ["{type_kind[0].su}dot"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}dot.{sve_type[0]}" } + + - name: svdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: + - [i32, i8] + - [i64, i16] + - [u32, u8] + - [u64, u16] + assert_instr: [["{type_kind[0].su}dot", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}dot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svusdot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - LLVMLink: { name: "usdot.{sve_type[0]}" } + + - name: svusdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, u8, i8]] + assert_instr: [[usdot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "usdot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svsudot[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8, u8]] + assert_instr: [usdot] + n_variant_op: op3 + compose: + - FnCall: ["svusdot_{type[0]}", [$op1, $op3, $op2]] + + - name: svsudot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Dot product (signed × unsigned) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" }] + types: [[i32, i8, u8]] + assert_instr: [[sudot, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sudot.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[2]}" + - "imm_index: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svdiv[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}div"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}div.{sve_type}" } + + - name: svdivr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Divide reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i32, i64, u32, u64] + assert_instr: ["{type_kind.fsu}divr"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}divr.{sve_type}" } + + - name: svexpa[_{type[0]}] + attr: [*sve-unstable] + doc: Floating-point exponential accelerator + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, u32], [f64, u64]] + assert_instr: [fexpa] + compose: + - LLVMLink: { name: "fexpa.x.{sve_type[0]} " } + + - name: svscale[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Adjust exponent + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [fscale] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "fscale.{sve_type[0]}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f32mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f32] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}" } + + - name: svmmla[_{type}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [f64mm] + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [f64] + assert_instr: [fmmla] + compose: + - LLVMLink: { name: "fmmla.{sve_type}" } + + - name: svmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [u32, u8]] + assert_instr: ["{type_kind[0].su}mmla"] + compose: + - LLVMLink: { name: "{type_kind[0].su}mmla.{sve_type[0]}" } + + - name: svusmmla[_{type[0]}] + attr: [*sve-unstable] + doc: Matrix multiply-accumulate (unsigned × signed) + target_features: [i8mm] + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[2]}"] + return_type: "{sve_type[0]}" + types: [[i32, u8, i8]] + assert_instr: [usmmla] + compose: + - LLVMLink: { name: "usmmla.{sve_type[0]}" } + + - name: svmin[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.fsu}min"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.fsu}min.{sve_type}" } + + - name: svminnm[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Minimum number + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + zeroing_method: { select: op1 } + assert_instr: [fminnm] + n_variant_op: op2 + compose: + - LLVMLink: { name: "fminnm.{sve_type}" } diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml new file mode 100644 index 000000000000..269d7ff0eacb --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/spec/sve2/aarch64.spec.yml @@ -0,0 +1,3206 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [sve, sve2] + llvm_prefix: llvm.aarch64.sve + +auto_llvm_sign_conversion: true +generate_load_store_tests: true + +# `#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]` +sve-unstable: &sve-unstable + FnCall: [unstable, ['feature = "stdarch_aarch64_sve"', 'issue= "145052"']] + +# `#[cfg_attr(all(test, not(target_env = "msvc"))]` +msvc-disabled: &msvc-disabled + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]] + +intrinsics: + - name: svbext[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Gather lower bits from positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bext] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bext.x.{sve_type}" } + + - name: svbgrp[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Group bits to right or left as selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bgrp] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bgrp.x.{sve_type}" } + + - name: svbdep[{_n}_{type}] + attr: [*sve-unstable] + target_features: [sve2-bitperm] + doc: Scatter lower bits into positions selected by bitmask + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u16, u32, u64] + assert_instr: [bdep] + n_variant_op: op2 + compose: + - LLVMLink: { name: "bdep.x.{sve_type}" } + + - name: svhistcnt[_{type[0]}]_z + attr: [*sve-unstable] + doc: Count matching elements + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i32, u32], [i64, u64], [u32, u32], [u64, u64]] + assert_instr: [histcnt] + compose: + - LLVMLink: { name: "histcnt.{sve_type[0]}" } + + - name: svhistseg[_{type[0]}] + attr: [*sve-unstable] + doc: Count matching elements in 128-bit segments + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[i8, u8], [u8, u8]] + assert_instr: [histseg] + compose: + - LLVMLink: { name: "histseg.{sve_type[0]}" } + + - name: svmatch[_{type}] + attr: [*sve-unstable] + doc: Detect any matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [match] + compose: + - LLVMLink: { name: "match.{sve_type}" } + + - name: svnmatch[_{type}] + attr: [*sve-unstable] + doc: Detect no matching elements + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{predicate}" + types: [i8, i16, u8, u16] + assert_instr: [nmatch] + compose: + - LLVMLink: { name: "nmatch.{sve_type}" } + + - name: svhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}hadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hadd.{sve_type}" } + + - name: svrhadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding halving add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}rhadd"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}rhadd.{sve_type}" } + + - name: svaddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnb.{sve_type[0]}" } + + - name: svaddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [addhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "addhnt.{sve_type[0]}" } + + - name: svraddhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (bottom) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnb.{sve_type[0]}" } + + - name: svraddhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding add narrow high part (top) + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + return_type: "{sve_type[1]}" + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + assert_instr: [raddhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "raddhnt.{sve_type[0]}" } + + - name: svcadd[_{type}] + attr: [*sve-unstable] + doc: Complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [90, 270] }] + assert_instr: [[cadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cadd.x.{sve_type} + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_ROTATION]] + + - name: svcdot[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cdot, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcdot_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Complex dot product + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i32, i8], [i64, i16]] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - { variable: IMM_INDEX, vec_max_elems_type: "{type[0]}" } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cdot, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cdot.lane.{sve_type[0]} + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svcmla[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[cmla, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svcmla_lane[_{type}] + attr: [*sve-unstable] + doc: Complex multiply-add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32, u16, u32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[cmla, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: cmla.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqrdcmlah[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: IMM_ROTATION, any_values: [0, 90, 180, 270] }] + assert_instr: [[sqrdcmlah, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_ROTATION]] + + - name: svqrdcmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling complex multiply-add high with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i16, i32] + static_defs: ["const IMM_INDEX: i32", "const IMM_ROTATION: i32"] + constraints: + - variable: IMM_INDEX + range: { match_size: "{type}", default: [0, 1], halfword: [0, 3] } + - { variable: IMM_ROTATION, any_values: [0, 90, 180, 270] } + assert_instr: [[sqrdcmlah, "IMM_INDEX = 0, IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: sqrdcmlah.lane.x.{sve_type} + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "imm_index: i32" + - "imm_rotation: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX, $IMM_ROTATION]] + + - name: svqcadd[_{type}] + attr: [*sve-unstable] + doc: Saturating complex add with rotate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + static_defs: ["const IMM_ROTATION: i32"] + constraints: [{ variable: "IMM_ROTATION", any_values: [90, 270] }] + assert_instr: [[sqcadd, "IMM_ROTATION = 90"]] + compose: + - LLVMLink: + name: "sqcadd.x.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_rotation: i32"] + - FnCall: ["{llvm_link}", ["$op1", "$op2", "$IMM_ROTATION"]] + + - name: svsublb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublb"] + n_variant_op: op2 + compose: + - LLVMLink: + name: "{type_kind[0].su}sublb.{sve_type[0]}" + + - name: svsublbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (bottom - top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssublbt] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssublbt.{sve_type[0]}" + + - name: svsublt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}sublt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}sublt.{sve_type[0]}" } + + - name: svsubltb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract long (top - bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: [ssubltb] + n_variant_op: op2 + compose: + - LLVMLink: + name: "ssubltb.{sve_type[0]}" + + - name: svsubwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwb.{sve_type[0]}" } + + - name: svsubwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}subwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}subwt.{sve_type[0]}" } + + - name: svrsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnb.{sve_type[0]}" } + + - name: svrsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Rounding subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [rsubhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "rsubhnt.{sve_type[0]}" } + + - name: svsubhnb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnb.{sve_type[0]}" } + + - name: svsubhnt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Subtract narrow high part (top) + arguments: + ["even: {sve_type[1]}", "op1: {sve_type[0]}", "op2: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [subhnt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "subhnt.{sve_type[0]}" } + + - name: svsbclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclb.{sve_type}" } + + - name: svsbclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Subtract with borrow long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [sbclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sbclt.{sve_type}" } + + - name: svqsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsub"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsub.{sve_type}" } + + - name: svqsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + zeroing_method: { select: op1 } + assert_instr: ["{type_kind.su}qsubr"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qsubr.{sve_type}" } + + - name: svhsub[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsub.{sve_type}" } + + - name: svhsubr[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Halving subtract reversed + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}hsub"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}hsubr.{sve_type}" } + + - name: svwhilege_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than or equal to + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilege, unsigned: whilehs }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilege.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehs.{sve_type[1]}.{type[0]}" } } + + - name: svwhilegt_{sve_type[1]}[_{type[0]}] + attr: [*sve-unstable] + doc: While decrementing scalar is greater than + arguments: ["op1: {type[0]}", "op2: {type[0]}"] + return_type: "{sve_type[1]}" + types: [[[i32, i64, u32, u64], [b8, b16, b32, b64]]] + assert_instr: [{ default: whilegt, unsigned: whilehi }] + compose: + - MatchKind: + - "{type[0]}" + - default: { LLVMLink: { name: "whilegt.{sve_type[1]}.{type[0]}" } } + unsigned: { LLVMLink: { name: "whilehi.{sve_type[1]}.{type[0]}" } } + + - name: svwhilerw_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilerw.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilerw[_{type}] + attr: [*sve-unstable] + doc: While free of read-after-write conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilerw] + compose: + - FnCall: + - "svwhilerw_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svwhilewr_{size}ptr + attr: [*sve-unstable] + safety: + unsafe: [] + visibility: private + static_defs: [T] + substitutions: + size_alt: + match_size: "{type}" + byte: b + halfword: h + default: s + doubleword: d + arguments: ["op1: *T", "op2: *T"] + return_type: "{predicate}" + types: [i8, i16, i32, i64] + assert_instr: [] + compose: + - Let: [op1, CastAs: [$op1, "*const crate::ffi::c_void"]] + - Let: [op2, CastAs: [$op2, "*const crate::ffi::c_void"]] + - LLVMLink: + name: "whilewr.{size_alt}.{predicate}.p0" + arguments: ["op1: *crate::ffi::c_void", "op2: *crate::ffi::c_void"] + + - name: svwhilewr[_{type}] + attr: [*sve-unstable] + doc: While free of write-after-read conflicts + # TODO: This might be safe even with unrelated pointers, but the LLVM builtin's guarantees don't + # seem to be documented, so we conservatively keep this unsafe for now. + safety: + unsafe: + - custom: "[`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints + must be met for at least the base pointers, `op1` and `op2`." + arguments: ["op1: *{type}", "op2: *{type}"] + return_type: "svbool_t" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [whilewr] + compose: + - FnCall: + - "svwhilewr_{size}ptr" + - - $op1 + - $op2 + - - Type: "{type}" + + - name: svtbl2[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in two-vector table + arguments: ["data: {sve_type_x2[0]}", "indices: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbl] + compose: + - LLVMLink: + name: "tbl2.{sve_type[0]}" + arguments: + - "data0: {sve_type[0]}" + - "data1: {sve_type[0]}" + - "indices: {sve_type[1]}" + - FnCall: + - "{llvm_link}" + - - FnCall: ["svget2_{type[0]}", ["$data"], [0]] + - FnCall: ["svget2_{type[0]}", ["$data"], [1]] + - $indices + + - name: svtbx[_{type[0]}] + attr: [*sve-unstable] + doc: Table lookup in single-vector table (merging) + arguments: + - "fallback: {sve_type[0]}" + - "data: {sve_type[0]}" + - "indices: {sve_type[1]}" + return_type: "{sve_type[0]}" + types: + - [f32, u32] + - [f64, u64] + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + - [u8, u8] + - [u16, u16] + - [u32, u32] + - [u64, u64] + assert_instr: [tbx] + compose: + - LLVMLink: { name: "tbx.{sve_type[0]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_m + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - LLVMLink: { name: "fcvtlt.{type[0]}{type[1]}" } + + - name: svcvtlt_{type[0]}[_{type[1]}]_x + attr: [*sve-unstable] + doc: Up convert long (top) + arguments: ["pg: svbool_t", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f64, f32]] + assert_instr: [fcvtlt] + compose: + - FnCall: + - "svcvtlt_{type[0]}_{type[1]}_m" + - - FnCall: ["crate::intrinsics::transmute_unchecked", [$op], [], true] + - $pg + - $op + + - name: svcvtnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert and narrow (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtnt] + compose: + - LLVMLink: { name: "fcvtnt.{type[0]}{type[1]}" } + + - name: svcvtx_{type[0]}[_{type[1]}]{_mxz} + attr: [*sve-unstable] + doc: Down convert, rounding to odd + arguments: + ["inactive: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + zeroing_method: { drop: inactive } + assert_instr: [fcvtx] + compose: + - LLVMLink: { name: "fcvtx.{type[0]}{type[1]}" } + + - name: svcvtxnt_{type[0]}[_{type[1]}]{_mx} + attr: [*sve-unstable] + doc: Down convert, rounding to odd (top) + arguments: + ["even: {sve_type[0]}", "pg: {max_predicate}", "op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[f32, f64]] + assert_instr: [fcvtxnt] + compose: + - LLVMLink: { name: "fcvtxnt.{type[0]}{type[1]}" } + + - name: svldnt1_gather_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: { name: "ldnt1.gather.index.{sve_type[1]}" } + + - name: svldnt1_gather_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[1]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: { name: "ldnt1.gather.uxtw.{sve_type[1]}" } + doubleword: + LLVMLink: { name: "ldnt1.gather.{sve_type[1]}" } + + - name: svldnt1_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1]}.{sve_type[0]}" + + - name: svldnt1_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Unextended load, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["ldnt1{size_literal[0]}"] + test: { load: 1 } + compose: + - FnCall: + - "svldnt1_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [i64, u64], [i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "indices: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [[i64, u64], [u64, i64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.index.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $indices]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [[i64, u64], [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + + - name: svldnt1u{size_literal[2]}_gather_[{type[0]}]offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + ["pg: {predicate[0]}", "base: *{type[2]}", "offsets: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [[i64, u64], [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "ldnt1.gather.uxtw.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + doubleword: + LLVMLink: + name: "ldnt1.gather.{sve_type[1] as {type[2]}}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $base, $offsets]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_offset_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "offset: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [u32, i32], [u8, u16]] + - [u64, [u64, i64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - LLVMLink: + name: "ldnt1.gather.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + return_type: "{sve_type[1] as {type[2]}}" + - FnCall: + - "crate::intrinsics::simd::simd_cast" + - - FnCall: ["{llvm_link}", [$pg, $bases, $offset]] + - - Type: "{sve_type[1] as {type[2]}}" + - _ + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], [u8, u16]] + - [u64, [i64, u64], [u8, u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + + - name: svldnt1s{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and sign-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1s{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1s{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svldnt1u{size_literal[2]}_gather[_{type[0]}base]_index_{type[1]} + attr: [*sve-unstable] + doc: Load {size[2]}-bit data and zero-extend, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: ["pg: {predicate[0]}", "bases: {sve_type[0]}", "index: i64"] + return_type: "{sve_type[1]}" + types: + - [u32, [i32, u32], u16] + - [u64, [i64, u64], [u16, u32]] + assert_instr: ["ldnt1{size_literal[2]}"] + test: { load: 2 } + compose: + - FnCall: + - "svldnt1u{size_literal[2]}_gather_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + + - name: svstnt1_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "indices: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $indices]] + + - name: svstnt1_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [[i64, u64], [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1]}" + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "base: *mut {type[1]}" + - "offsets: {sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $base, $offsets]] + + - name: svstnt1_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - LLVMLink: + arguments: + - "data: {sve_type[1]}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + name: "stnt1.scatter.scalar.offset.{sve_type[1]}.{sve_type[0]}" + - FnCall: ["{llvm_link}", [$data, $pg, $bases, $offset]] + + - name: svstnt1_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Non-truncating store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [f32, i32, u32]] + - [u64, [f64, i64, u64]] + assert_instr: ["stnt1{size_literal[0]}"] + test: { store: 1 } + compose: + - FnCall: + - "svstnt1_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[0]}"]] + - $data + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [[i64, u64], i64, [i16, i32]] + - [[i64, u64], u64, [u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.index.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "indices: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $indices] + + - name: svstnt1{size_literal[2]}_scatter_[{type[0]}]offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - "data: {sve_type[1]}" + types: + - [u32, i32, [i8, i16]] + - [u32, u32, [u8, u16]] + - [[i64, u64], i64, [i8, i16, i32]] + - [[i64, u64], u64, [u8, u16, u32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - MatchSize: + - "{type[0]}" + - default: + LLVMLink: + name: "stnt1.scatter.uxtw.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + doubleword: + LLVMLink: + name: "stnt1.scatter.{sve_type[1] as {type[2]}}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "base: *mut {type[2]}" + - "offsets: {sve_type[0]}" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $base, $offsets] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_offset[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - LLVMLink: + name: "stnt1.scatter.scalar.offset.{sve_type[1] as {type[2]}}.{sve_type[0]}" + arguments: + - "data: {sve_type[1] as {type[2]}}" + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "offset: i64" + - FnCall: + - "{llvm_link}" + - [FnCall: ["crate::intrinsics::simd::simd_cast", [$data]], $pg, $bases, $offset] + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + ["pg: {predicate[0]}", "bases: {sve_type[0]}", "data: {sve_type[1]}"] + types: + - [u32, [i32, u32], [i8, i16]] + - [u64, [i64, u64], [i8, i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - 0 + - $data + + - name: svstnt1{size_literal[2]}_scatter[_{type[0]}base]_index[_{type[1]}] + attr: [*sve-unstable] + doc: Truncate to {size[2]} bits and store, non-temporal + safety: + unsafe: + - pointer_offset: predicated + - dereference: predicated + - no_provenance: bases + - non_temporal + arguments: + - "pg: {predicate[0]}" + - "bases: {sve_type[0]}" + - "index: i64" + - "data: {sve_type[1]}" + types: + - [u32, [i32, u32], i16] + - [u64, [i64, u64], [i16, i32]] + assert_instr: ["stnt1{size_literal[2]}"] + test: { store: 2 } + compose: + - FnCall: + - "svstnt1{size_literal[2]}_scatter_{type[0]}base_offset_{type[1]}" + - - $pg + - $bases + - MethodCall: [$index, unchecked_shl, ["{size_in_bytes_log2[2]}"]] + - $data + + - name: svaba[{_n}_{type}] + attr: [*sve-unstable] + doc: Absolute difference and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind}aba"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind}aba.{sve_type}" } + + - name: svqabs[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating absolute value + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqabs] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqabs.{sve_type}" } + + - name: svabdlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlb.{sve_type[0]}" } + + - name: svabdlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abdlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}abdlt.{sve_type[0]}" } + + - name: svabalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalb.{sve_type[0]}" } + + - name: svabalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Absolute difference long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}abalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}abalt.{sve_type[0]}" } + + - name: svbcax[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise clear and exclusive OR + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bcax] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bcax.{sve_type}" } + + - name: sveorbt[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (bottom, top) + arguments: ["odd: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eorbt] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eorbt.{sve_type}" } + + - name: sveortb[{_n}_{type}] + attr: [*sve-unstable] + doc: Interleaving exclusive OR (top, bottom) + arguments: ["even: {sve_type}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eortb] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op2 + compose: + - LLVMLink: { name: "eortb.{sve_type}" } + + - name: sveor3[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR of three vectors + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [eor3] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "eor3.{sve_type}" } + + - name: svbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl.{sve_type}" } + + - name: svbsl1n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with first input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl1n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl1n.{sve_type}" } + + - name: svbsl2n[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select with second input inverted + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [bsl2n] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "bsl2n.{sve_type}" } + + - name: svnbsl[{_n}_{type}] + attr: [*sve-unstable] + doc: Bitwise select + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [nbsl] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + n_variant_op: op3 + compose: + - LLVMLink: { name: "nbsl.{sve_type}" } + + - name: svxar[_n_{type}] + attr: [*sve-unstable] + doc: Bitwise exclusive OR and rotate right + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + assert_instr: [[xar, "IMM3 = 1"]] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + compose: + - LLVMLink: + name: "xar.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrax1[_{type}] + attr: [*sve-unstable] + doc: Bitwise rotate left by 1 and exclusive OR + target_features: [sve2-sha3] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + assert_instr: [rax1] + types: [i64, u64] + compose: + - LLVMLink: { name: "rax1" } + + - name: svshllb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (bottom) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllb", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllb.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshllt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift left long (top) + arguments: ["op1: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}shllt", "IMM2 = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}shllt.{sve_type[0]}" + arguments: ["op1: {sve_type[1]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}rshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}rshl.{sve_type[0]}" } + + - name: svqrshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating rounding shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qrshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qrshl.{sve_type[0]}" } + + - name: svqshl[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [[i8, u8], i8] + - [[i16, u16], i16] + - [[i32, u32], i32] + - [[i64, u64], i64] + assert_instr: ["{type_kind[0].su}qshl"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}qshl.{sve_type[0]}" } + + - name: svqshlu[_n_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating shift left unsigned + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["0", "{size_minus_one[1]}"] }] + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [[sqshlu, "IMM2 = 0"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "sqshlu.{sve_type[0]}" + arguments: ["pg: {predicate[0]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svsli[_n_{type}] + attr: [*sve-unstable] + doc: Shift left and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["0", "{size_minus_one}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sli, "IMM3 = 0"]] + compose: + - LLVMLink: + name: "sli.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshr[_n_{type}]{_mxz} + attr: [*sve-unstable] + doc: Rounding shift right + arguments: ["pg: {predicate}", "op1: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rshr", "IMM2 = 1"]] + zeroing_method: { select: op1 } + compose: + - LLVMLink: + name: "{type_kind.su}rshr.{sve_type}" + arguments: ["pg: {predicate}", "op1: {sve_type}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$pg, $op1, $IMM2]] + + - name: svrsra[_n_{type}] + attr: [*sve-unstable] + doc: Rounding shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}rsra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}rsra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[rshrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "rshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qrshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qrshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqrshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqrshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating rounding shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqrshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqrshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnb", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [["{type_kind[0].su}qshrnt", "IMM2 = 1"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}qshrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqshrunb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svqshrunt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Saturating shift right unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [[sqshrunt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "sqshrunt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svsra[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and accumulate + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [["{type_kind.su}sra", "IMM3 = 1"]] + compose: + - LLVMLink: + name: "{type_kind.su}sra.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svsri[_n_{type}] + attr: [*sve-unstable] + doc: Shift right and insert + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM3: i32"] + constraints: [{ variable: IMM3, range: ["1", "{size}"] }] + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: [[sri, "IMM3 = 1"]] + compose: + - LLVMLink: + name: "sri.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm3: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM3]] + + - name: svshrnb[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (bottom) + arguments: ["op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnb, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnb.{sve_type[0]}" + arguments: ["op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$op1, $IMM2]] + + - name: svshrnt[_n_{type[0]}] + attr: [*sve-unstable] + doc: Shift right narrow (top) + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}"] + return_type: "{sve_type[1]}" + static_defs: ["const IMM2: i32"] + constraints: [{ variable: IMM2, range: ["1", "{size[1]}"] }] + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: [[shrnt, "IMM2 = 1"]] + compose: + - LLVMLink: + name: "shrnt.{sve_type[0]}" + arguments: ["even: {sve_type[1]}", "op1: {sve_type[0]}", "imm2: i32"] + - FnCall: ["{llvm_link}", [$even, $op1, $IMM2]] + + - name: svqxtnb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnb"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnb.{sve_type[0]}" } + + - name: svqxtnt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}qxtnt"] + compose: + - LLVMLink: { name: "{type_kind[0].su}qxtnt.{sve_type[0]}" } + + - name: svqxtunb[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (bottom) + arguments: ["op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunb] + compose: + - LLVMLink: { name: "sqxtunb.{sve_type[0]}" } + + - name: svqxtunt[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating extract unsigned narrow (top) + arguments: ["even: {sve_type[1]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: + - [i16, u8] + - [i32, u16] + - [i64, u32] + assert_instr: [sqxtunt] + compose: + - LLVMLink: { name: "sqxtunt.{sve_type[0]}" } + + - name: svmovlb[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (bottom) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllb"] + compose: + - FnCall: ["svshllb_n_{type[0]}", [$op], [0]] + + - name: svmovlt[_{type[0]}] + attr: [*sve-unstable] + doc: Move long (top) + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}shllt"] + compose: + - FnCall: ["svshllt_n_{type[0]}", [$op], [0]] + + - name: svunpkhi[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpkhi"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpkhi.{sve_type[0]}" } + + - name: svunpkhi[_b] + attr: [*sve-unstable] + doc: Unpack and extend high half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpkhi] + compose: + - LLVMLink: { name: "punpkhi.nxv16i1" } + + - name: svunpklo[_{type[0]}] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}unpklo"] + compose: + - LLVMLink: { name: "{type_kind[0].su}unpklo.{sve_type[0]}" } + + - name: svunpklo[_b] + attr: [*sve-unstable] + doc: Unpack and extend low half + arguments: ["op: svbool_t"] + return_type: "svbool8_t" + assert_instr: [punpklo] + compose: + - LLVMLink: { name: "punpklo.nxv16i1" } + + - name: svaddp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Add pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.f}addp"] + compose: + - LLVMLink: { name: "{type_kind.f}addp.{sve_type}" } + + - name: svadalp[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Add and accumulate long pairwise + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}adalp"] + zeroing_method: { select: op1 } + compose: + - LLVMLink: { name: "{type_kind[0].su}adalp.{sve_type[0]}" } + + - name: svmaxp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}maxp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}maxp.{sve_type}" } + + - name: svmaxnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Maximum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fmaxnmp"] + compose: + - LLVMLink: { name: "fmaxnmp.{sve_type}" } + + - name: svminp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64, i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.fsu}minp"] + compose: + - LLVMLink: { name: "{type_kind.fsu}minp.{sve_type}" } + + - name: svminnmp[_{type}]{_mx} + attr: [*sve-unstable] + doc: Minimum number pairwise + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [f32, f64] + assert_instr: ["fminnmp"] + compose: + - LLVMLink: { name: "fminnmp.{sve_type}" } + + - name: svmul_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["{type_kind.f}mul", "IMM_INDEX = 0"]] + types: [f32, f64, i16, i32, i64, u16, u32, u64] + compose: + - LLVMLink: + name: "{type_kind.f}mul.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmulh.{sve_type}" } + + - name: svqdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqrdmulh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmulh] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqrdmulh.{sve_type}" } + + - name: svqrdmulh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply high + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + assert_instr: [["sqrdmulh", "IMM_INDEX = 0"]] + types: [i16, i32, i64] + compose: + - LLVMLink: + name: "sqrdmulh.lane.{sve_type}" + arguments: ["op1: {sve_type}", "op2: {sve_type}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullb.{sve_type[0]}" } + + - name: svqdmullb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullb", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svqdmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: [sqdmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "sqdmullt.{sve_type[0]}" } + + - name: svqdmullt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + assert_instr: [["sqdmullt", "IMM_INDEX = 0"]] + types: [[i32, i16], [i64, i32]] + compose: + - LLVMLink: + name: "sqdmullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, IMM_INDEX]] + + - name: svmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}mullb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullb.{sve_type[0]}" } + + - name: svmullb_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullb` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullb", "IMM_INDEX = 0"]]}]] + doc: Multiply long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullb.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svmullt[{_n}_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}mullt.{sve_type[0]}" } + + - name: svmullt_lane[_{type[0]}] + attr: + - *sve-unstable + # FIXME(arm-maintainers): MSVC disassembly of `[su]mullt` fails + - FnCall: [cfg_attr, [*msvc-disabled, {FnCall: [assert_instr, ["{type_kind[0].su}mullt", "IMM_INDEX = 0"]]}]] + doc: Multiply long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i32, i16] + - [i64, i32] + - [u32, u16] + - [u64, u32] + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + compose: + - LLVMLink: + name: "{type_kind[0].su}mullt.lane.{sve_type[0]}" + arguments: + ["op1: {sve_type[1]}", "op2: {sve_type[1]}", "imm_index: i32"] + - FnCall: ["{llvm_link}", [$op1, $op2, $IMM_INDEX]] + + - name: svrecpe[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [urecpe] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "urecpe.{sve_type}" } + + - name: svrsqrte[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Reciprocal square root estimate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [ursqrte] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "ursqrte.{sve_type}" } + + - name: svmla_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-add, addend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mla, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mla.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmls_lane[_{type}] + attr: [*sve-unstable] + doc: Multiply-subtract, minuend first + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64, u16, u32, u64] + assert_instr: [[mls, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "mls.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalb.{sve_type[0]}" } + + - name: svmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlalt.{sve_type[0]}" } + + - name: svmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslb.{sve_type[0]}" } + + - name: svmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + [[i16, i8], [i32, i16], [i64, i32], [u16, u8], [u32, u16], [u64, u32]] + assert_instr: ["{type_kind[0].su}mlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "{type_kind[0].su}mlslt.{sve_type[0]}" } + + - name: svmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32], [u32, u16], [u64, u32]] + assert_instr: [["{type_kind[0].su}mlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "{type_kind[0].su}mlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlah[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlah] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlah.{sve_type}" } + + - name: svqrdmlah_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-add high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlah, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlah.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqrdmlsh[{_n}_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqrdmlsh] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqrdmlsh.{sve_type}" } + + - name: svqrdmlsh_lane[_{type}] + attr: [*sve-unstable] + doc: Saturating rounding doubling multiply-subtract high + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type}" }] + types: [i16, i32, i64] + assert_instr: [[sqrdmlsh, "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqrdmlsh.lane.{sve_type}" + arguments: + - "op1: {sve_type}" + - "op2: {sve_type}" + - "op3: {sve_type}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalb.{sve_type[0]}" } + + - name: svqdmlalb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlalbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalbt.{sve_type[0]}" } + + - name: svqdmlalt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlalt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlalt.{sve_type[0]}" } + + - name: svqdmlalt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-add long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlalt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlalt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslb"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslb.{sve_type[0]}" } + + - name: svqdmlslb_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslb", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslb.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqdmlslbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (bottom × top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslbt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslbt.{sve_type[0]}" } + + - name: svqdmlslt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[i16, i8], [i32, i16], [i64, i32]] + assert_instr: ["sqdmlslt"] + n_variant_op: op3 + compose: + - LLVMLink: { name: "sqdmlslt.{sve_type[0]}" } + + - name: svqdmlslt_lane[_{type[0]}] + attr: [*sve-unstable] + doc: Saturating doubling multiply-subtract long (top) + arguments: + ["op1: {sve_type[0]}", "op2: {sve_type[1]}", "op3: {sve_type[1]}"] + return_type: "{sve_type[0]}" + static_defs: ["const IMM_INDEX: i32"] + constraints: [{ variable: IMM_INDEX, vec_max_elems_type: "{type[1]}" }] + types: [[i32, i16], [i64, i32]] + assert_instr: [["sqdmlslt", "IMM_INDEX = 0"]] + compose: + - LLVMLink: + name: "sqdmlslt.lane.{sve_type[0]}" + arguments: + - "op1: {sve_type[0]}" + - "op2: {sve_type[1]}" + - "op3: {sve_type[1]}" + - "IMM_INDEX: i32" + - FnCall: ["{llvm_link}", [$op1, $op2, $op3, $IMM_INDEX]] + + - name: svqneg[_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating negate + arguments: ["inactive: {sve_type}", "pg: {predicate}", "op: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64] + assert_instr: [sqneg] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "sqneg.{sve_type}" } + + - name: svadclb[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (bottom) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclb] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclb.{sve_type}" } + + - name: svadclt[{_n}_{type}] + attr: [*sve-unstable] + doc: Add with carry long (top) + arguments: ["op1: {sve_type}", "op2: {sve_type}", "op3: {sve_type}"] + return_type: "{sve_type}" + types: [u32, u64] + assert_instr: [adclt] + n_variant_op: op3 + compose: + - LLVMLink: { name: "adclt.{sve_type}" } + + - name: svqadd[{_n}_{type}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add + arguments: ["pg: {predicate}", "op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [i8, i16, i32, i64, u8, u16, u32, u64] + assert_instr: ["{type_kind.su}qadd"] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind.su}qadd.{sve_type}" } + + - name: svsqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with signed addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [u8, i8] + - [u16, i16] + - [u32, i32] + - [u64, i64] + assert_instr: [usqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "usqadd.{sve_type[0]}" } + + - name: svuqadd[{_n}_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Saturating add with unsigned addend + arguments: + ["pg: {predicate[0]}", "op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i8, u8] + - [i16, u16] + - [i32, u32] + - [i64, u64] + assert_instr: [suqadd] + zeroing_method: { select: op1 } + n_variant_op: op2 + compose: + - LLVMLink: { name: "suqadd.{sve_type[0]}" } + + - name: svaddlb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlb.{sve_type[0]}" } + + - name: svaddlbt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (bottom + top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + assert_instr: ["{type_kind[0].su}addlbt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlbt.{sve_type[0]}" } + + - name: svaddlt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add long (top) + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addlt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addlt.{sve_type[0]}" } + + - name: svaddwb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (bottom) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwb"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwb.{sve_type[0]}" } + + - name: svaddwt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Add wide (top) + arguments: ["op1: {sve_type[0]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: + - [i16, i8] + - [i32, i16] + - [i64, i32] + - [u16, u8] + - [u32, u16] + - [u64, u32] + assert_instr: ["{type_kind[0].su}addwt"] + n_variant_op: op2 + compose: + - LLVMLink: { name: "{type_kind[0].su}addwt.{sve_type[0]}" } + + - name: svlogb[_{type[0]}]{_mxz} + attr: [*sve-unstable] + doc: Base 2 logarithm as integer + arguments: + ["inactive: {sve_type[1]}", "pg: {predicate[0]}", "op: {sve_type[0]}"] + return_type: "{sve_type[1]}" + types: [[f32, i32], [f64, i64]] + assert_instr: [flogb] + zeroing_method: { drop: inactive } + compose: + - LLVMLink: { name: "flogb.{sve_type[0]}" } + + - name: svpmul[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [pmul] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmul.{sve_type}" } + + - name: svpmullb_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullb.pair.{sve_type}" } + + - name: svpmullb[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (bottom) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullb] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullb_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svpmullt_pair[{_n}_{type}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8, u32, u64] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - LLVMLink: { name: "pmullt.pair.{sve_type}" } + + - name: svpmullt[{_n}_{type[0]}] + attr: [*sve-unstable] + doc: Polynomial multiply long (top) + target_features: [sve2-aes] + arguments: ["op1: {sve_type[1]}", "op2: {sve_type[1]}"] + return_type: "{sve_type[0]}" + types: [[u16, u8], [u64, u32]] + assert_instr: [pmullt] + n_variant_op: op2 + compose: + - FnCall: + - "crate::intrinsics::transmute_unchecked" + - [FnCall: ["svpmullt_pair_{type[1]}", [$op1, $op2]]] + - [] + - true + + - name: svaesd[_{type}] + attr: [*sve-unstable] + doc: AES single round decryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesd] + compose: + - LLVMLink: { name: "aesd" } + + - name: svaese[_{type}] + attr: [*sve-unstable] + doc: AES single round encryption + target_features: [sve2-aes] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aese] + compose: + - LLVMLink: { name: "aese" } + + - name: svaesmc[_{type}] + attr: [*sve-unstable] + doc: AES mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesmc] + compose: + - LLVMLink: { name: "aesmc" } + + - name: svaesimc[_{type}] + attr: [*sve-unstable] + doc: AES inverse mix columns + target_features: [sve2-aes] + arguments: ["op: {sve_type}"] + return_type: "{sve_type}" + types: [u8] + assert_instr: [aesimc] + compose: + - LLVMLink: { name: "aesimc" } + + - name: svsm4e[_{type}] + attr: [*sve-unstable] + doc: SM4 encryption and decryption + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4e] + compose: + - LLVMLink: { name: "sm4e" } + + - name: svsm4ekey[_{type}] + attr: [*sve-unstable] + doc: SM4 key updates + target_features: [sve2-sm4] + arguments: ["op1: {sve_type}", "op2: {sve_type}"] + return_type: "{sve_type}" + types: [u32] + assert_instr: [sm4ekey] + compose: + - LLVMLink: { name: "sm4ekey" } diff --git a/library/stdarch/crates/stdarch-gen-arm/src/context.rs b/library/stdarch/crates/stdarch-gen-arm/src/context.rs index 9b8eb8e8b9bf..85342a180485 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/context.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/context.rs @@ -43,6 +43,10 @@ pub struct GlobalContext { /// Should all LLVM wrappers convert their arguments to a signed type #[serde(default)] pub auto_llvm_sign_conversion: bool, + + /// Should SVE load/store tests be generated? + #[serde(default)] + pub generate_load_store_tests: bool, } /// Context of an intrinsic group @@ -218,7 +222,7 @@ pub fn make_assertion_from_constraint(&self, constraint: &Constraint) -> Result< } => Ok(Expression::MacroCall( "static_assert_range".to_string(), format!( - "{variable}, {min}, {max}", + "{variable}, {min}..={max}", min = range.start(), max = range.end() ), @@ -246,7 +250,7 @@ pub fn make_assertion_from_constraint(&self, constraint: &Constraint) -> Result< |bitsize| Ok(higher_limit / bitsize - 1))?; Ok(Expression::MacroCall( "static_assert_range".to_string(), - format!("{variable}, 0, {max}"), + format!("{variable}, 0..={max}"), )) } else { Err(format!( diff --git a/library/stdarch/crates/stdarch-gen-arm/src/expression.rs b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs index bf48f0dab749..0b6ffef9d8d3 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/expression.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs @@ -143,8 +143,6 @@ pub enum Expression { LLVMLink(LLVMLink), /// Casts the given expression to the specified (unchecked) type CastAs(Box, String), - /// Returns the LLVM `undef` symbol - SvUndef, /// Multiplication Multiply(Box, Box), /// Xor @@ -295,7 +293,7 @@ pub fn build(&mut self, intrinsic: &Intrinsic, ctx: &mut Context) -> context::Re /// - An unnecessary `unsafe` is a warning, made into an error by the CI's `-D warnings`. /// /// This **panics** if it encounters an expression that shouldn't appear in a safe function at - /// all (such as `SvUndef`). + /// all. pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool { match self { // The call will need to be unsafe, but the declaration does not. @@ -347,9 +345,6 @@ pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool { }, // We only use macros to check const generics (using static assertions). Self::MacroCall(_name, _args) => false, - // Materialising uninitialised values is always unsafe, and we avoid it in safe - // functions. - Self::SvUndef => panic!("Refusing to wrap unsafe SvUndef in safe function '{ctx_fn}'."), // Variants that aren't tokenised. We shouldn't encounter these here. Self::MatchKind(..) => { unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.") @@ -390,9 +385,7 @@ fn from_str(s: &str) -> Result { static MACRO_RE: LazyLock = LazyLock::new(|| Regex::new(r"^(?P[\w\d_]+)!\((?P.*?)\);?$").unwrap()); - if s == "SvUndef" { - Ok(Expression::SvUndef) - } else if MACRO_RE.is_match(s) { + if MACRO_RE.is_match(s) { let c = MACRO_RE.captures(s).unwrap(); let ex = c["ex"].to_string(); let _: TokenStream = ex @@ -533,7 +526,6 @@ fn to_tokens(&self, tokens: &mut TokenStream) { let ty: TokenStream = ty.parse().expect("invalid syntax"); tokens.append_all(quote! { #ex as #ty }) } - Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }), Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }), Self::Xor(lhs, rhs) => tokens.append_all(quote! { #lhs ^ #rhs }), Self::Type(ty) => ty.to_tokens(tokens), diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs index ce427d54b355..8d7b075ca6b8 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs @@ -550,7 +550,7 @@ pub fn build(&mut self, ctx: &mut Context) -> context::Result { /// Alters all the unsigned types from the signature. This is required where /// a signed and unsigned variant require the same binding to an exposed - /// LLVM instrinsic. + /// LLVM intrinsic. pub fn sanitise_uints(&mut self) { let transform = |tk: &mut TypeKind| { if let Some(BaseType::Sized(BaseTypeKind::UInt, size)) = tk.base_type() { @@ -630,7 +630,7 @@ pub fn apply_conversions_to_call( match (scope, kind.base_type()) { (Argument, Some(Sized(Bool, bitsize))) if *bitsize != 8 => { - Ok(convert("into", arg)) + Ok(convert("sve_into", arg)) } (Argument, Some(Sized(UInt, _) | Unsized(UInt))) => { if ctx.global.auto_llvm_sign_conversion { @@ -647,27 +647,26 @@ pub fn apply_conversions_to_call( }) .try_collect()?; - let return_type_conversion = if !ctx.global.auto_llvm_sign_conversion { - None - } else { - self.signature - .as_ref() - .and_then(|sig| sig.return_type.as_ref()) - .and_then(|ty| { - if let Some(Sized(Bool, bitsize)) = ty.base_type() { - (*bitsize != 8).then_some(Bool) - } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { - Some(UInt) - } else { - None - } - }) - }; + let return_type_conversion = self + .signature + .as_ref() + .and_then(|sig| sig.return_type.as_ref()) + .and_then(|ty| { + if let Some(Sized(Bool, bitsize)) = ty.base_type() { + (*bitsize != 8).then_some(Bool) + } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { + Some(UInt) + } else { + None + } + }); let fn_call = Expression::FnCall(fn_call); match return_type_conversion { - Some(Bool) => Ok(convert("into", fn_call)), - Some(UInt) => Ok(convert("as_unsigned", fn_call)), + Some(Bool) => Ok(convert("sve_into", fn_call)), + Some(UInt) if ctx.global.auto_llvm_sign_conversion => { + Ok(convert("as_unsigned", fn_call)) + } _ => Ok(fn_call), } } @@ -872,8 +871,8 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { Self::NoProvenance(arg) => write!( f, "Addresses passed in `{arg}` lack provenance, so this is similar to using a \ - `usize as ptr` cast (or [`core::ptr::from_exposed_addr`]) on each lane before \ - using it." + `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane \ + before using it." ), Self::UnpredictableOnFault => write!( f, @@ -1139,7 +1138,7 @@ fn generate_big_endian(&self, variant: &mut Intrinsic) { } else { /* If we do not need to reorder anything then immediately add * the expressions from the big_endian_expressions and - * concatinate the compose vector */ + * concatenate the compose vector */ variant.big_endian_compose.extend(big_endian_expressions); variant .big_endian_compose @@ -1157,11 +1156,11 @@ fn generate_big_endian(&self, variant: &mut Intrinsic) { /* If we do not create a shuffle call we do not need modify the * return value and append to the big endian ast array. A bit confusing - * as in code we are making the final call before caputuring the return + * as in code we are making the final call before capturing the return * value of the intrinsic that has been called.*/ let ret_val_name = "ret_val".to_string(); if let Some(simd_shuffle_call) = create_shuffle_call(&ret_val_name, return_type) { - /* There is a possibility that the funcion arguments did not + /* There is a possibility that the function arguments did not * require big endian treatment, thus we need to now add the * original function body before appending the return value.*/ if variant.big_endian_compose.is_empty() { @@ -1695,8 +1694,8 @@ enum Endianness { NA, } -/// Based on the endianess will create the appropriate intrinsic, or simply -/// create the desired intrinsic without any endianess +/// Based on the endianness will create the appropriate intrinsic, or simply +/// create the desired intrinsic without any endianness fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut TokenStream) { let signature = &intrinsic.signature; let fn_name = signature.fn_name().to_string(); diff --git a/library/stdarch/crates/stdarch-gen-arm/src/main.rs b/library/stdarch/crates/stdarch-gen-arm/src/main.rs index e14e2782485b..b7e2aa416fb5 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/main.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/main.rs @@ -54,7 +54,7 @@ fn main() -> Result<(), String> { vv.into_iter().flatten().collect_vec() })?; - if filepath.ends_with("sve.spec.yml") || filepath.ends_with("sve2.spec.yml") { + if input.ctx.generate_load_store_tests { let loads = intrinsics.iter() .filter_map(|i| { if matches!(i.test, Test::Load(..)) { diff --git a/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs index bd47ff2bd155..c3aa22294d9f 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs @@ -289,9 +289,9 @@ pub fn express_reinterpretation_from( ( BaseType::Sized(Float | Int | UInt, _), BaseType::Sized(Float | Int | UInt, _), - ) => Some(FnCall::new_expression( + ) => Some(FnCall::new_unsafe_expression( // Conversions between float and (u)int, or where the lane size changes. - "simd_reinterpret".parse().unwrap(), + "transmute_unchecked".parse().unwrap(), vec![expr.into()], )), _ => None, diff --git a/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs index 3cfbabfe0ab2..79837e2224ee 100644 --- a/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs +++ b/library/stdarch/crates/stdarch-gen-hexagon/src/main.rs @@ -515,12 +515,6 @@ fn parse_header(content: &str) -> Vec { intrinsics } -/// Convert Q6 name to Rust function name (lowercase with underscores) -fn q6_to_rust_name(q6_name: &str) -> String { - // Q6_V_hi_W -> q6_v_hi_w - q6_name.to_lowercase() -} - /// Generate the module documentation fn generate_module_doc(mode: VectorMode) -> String { format!( @@ -541,6 +535,18 @@ fn generate_module_doc(mode: VectorMode) -> String { //! //! To use this module, compile with `-C target-feature=+{target_feature}`. //! +//! ## Naming Convention +//! +//! Function names preserve the original Q6 naming case because the convention +//! uses case to distinguish register types: +//! - `W` (uppercase) = vector pair (`HvxVectorPair`) +//! - `V` (uppercase) = vector (`HvxVector`) +//! - `Q` (uppercase) = predicate (`HvxVectorPred`) +//! - `R` = scalar register (`i32`) +//! +//! For example, `Q6_W_vcombine_VV` operates on a vector pair while +//! `Q6_V_hi_W` extracts a vector from a pair. +//! //! ## Architecture Versions //! //! Different intrinsics require different HVX architecture versions. Use the @@ -577,6 +583,7 @@ fn generate_types(mode: VectorMode) -> String { format!( r#" #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #[cfg(test)] use stdarch_test::assert_instr; @@ -1433,7 +1440,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { // Generate simple intrinsics for info in intrinsics.iter().filter(|i| !i.is_compound) { - let rust_name = q6_to_rust_name(&info.q6_name); + let rust_name = &info.q6_name; // Generate doc comment output.push_str(&format!("/// `{}`\n", info.asm_syntax)); @@ -1505,7 +1512,7 @@ fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { let overrides = get_compound_overrides(); for info in intrinsics.iter().filter(|i| i.is_compound) { if let Some(ref compound_expr) = info.compound_expr { - let rust_name = q6_to_rust_name(&info.q6_name); + let rust_name = &info.q6_name; // Get the primary instruction for assert_instr let _primary_instr = get_compound_primary_instr(compound_expr) diff --git a/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs b/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs index 10b87c70e9ed..3a946a12d661 100644 --- a/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs +++ b/library/stdarch/crates/stdarch-gen-loongarch/src/main.rs @@ -571,21 +571,21 @@ enum TypeKind { } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "SI" { call_params = match asm_fmts[2].as_str() { "si12" => format!( - "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S12)){unsafe_end}" + "static_assert_simm_bits!(IMM_S12, 12);\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S12){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "DI" { call_params = match asm_fmts[2].as_str() { "rk" => format!( - "{unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, transmute(b))){unsafe_end}" + "{unsafe_start}__{current_name}(transmute(a), mem_addr, transmute(b)){unsafe_end}" ), _ => panic!("unsupported assembly format: {}", asm_fmts[2]), }; } else if para_num == 4 { call_params = match (asm_fmts[2].as_str(), current_name.chars().last().unwrap()) { ("si8", t) => format!( - "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}transmute(__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0})){unsafe_end}", + "static_assert_simm_bits!(IMM_S8, 8);\n static_assert_uimm_bits!(IMM{0}, {0});\n {unsafe_start}__{current_name}(transmute(a), mem_addr, IMM_S8, IMM{0}){unsafe_end}", type_to_imm(t) ), (_, _) => panic!( @@ -597,7 +597,7 @@ enum TypeKind { let function = if !rustc_legacy_const_generics.is_empty() { format!( r#" -#[inline]{target_feature} +#[inline(always)]{target_feature} #[{rustc_legacy_const_generics}] #[unstable(feature = "stdarch_loongarch", issue = "117427")] {fn_decl}{{ @@ -609,7 +609,7 @@ enum TypeKind { } else { format!( r#" -#[inline]{target_feature} +#[inline(always)]{target_feature} #[unstable(feature = "stdarch_loongarch", issue = "117427")] {fn_decl}{{ {call_params} @@ -847,6 +847,7 @@ union v4df out.push_str(" printf(\" core_arch::{loongarch64::*, simd::*},\\n\");\n"); out.push_str(" printf(\" mem::transmute,\\n\");\n"); out.push_str(" printf(\"};\\n\");\n"); + out.push_str(" printf(\"use std::hint::black_box;\\n\");\n"); out.push_str(" printf(\"use stdarch_test::simd_test;\\n\");\n"); out.push_str(&call_function_str); out.push_str(" return 0;\n"); @@ -1323,10 +1324,10 @@ fn gen_test_body( _ => "unsupported parameter number".to_string(), }; let mut as_params = match para_num { - 1 => "(transmute(a))".to_string(), - 2 => "(transmute(a), transmute(b))".to_string(), - 3 => "(transmute(a), transmute(b), transmute(c))".to_string(), - 4 => "(transmute(a), transmute(b), transmute(c), transmute(d))".to_string(), + 1 => "(black_box(transmute(a)))".to_string(), + 2 => "(black_box(transmute(a)), black_box(transmute(b)))".to_string(), + 3 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)))".to_string(), + 4 => "(black_box(transmute(a)), black_box(transmute(b)), black_box(transmute(c)), black_box(transmute(d)))".to_string(), _ => panic!("unsupported parameter number"), }; let mut as_args = String::new(); @@ -1356,9 +1357,9 @@ fn gen_test_body( { fn_params = "(a)".to_string(); if in_t[0] == "SI" { - as_params = "(%d)".to_string(); + as_params = "(black_box(%d))".to_string(); } else { - as_params = "(%ld)".to_string(); + as_params = "(black_box(%ld))".to_string(); } as_args = ", a".to_string(); } else if para_num == 2 && (in_t[1] == "UQI" || in_t[1] == "USI") { @@ -1370,7 +1371,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1383,13 +1384,13 @@ fn gen_test_body( ); let val = rand_i32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {val})"); - as_params = format!("::<{val}>(transmute(a))"); + as_params = format!("::<{val}>(black_box(transmute(a)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } } else if para_num == 2 && in_t[1] == "SI" && asm_fmts[2].starts_with("rk") { fn_params = "(a.v, b)".to_string(); - as_params = "(transmute(a), %d)".to_string(); + as_params = "(black_box(transmute(a)), %d)".to_string(); as_args = ", b".to_string(); } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "SI" { if asm_fmts[2].starts_with("si") { @@ -1441,7 +1442,7 @@ fn gen_test_body( let ival = rand_i32(32); let uval = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, {ival}, {uval})"); - as_params = format!("::<{uval}>(transmute(a), {ival})"); + as_params = format!("::<{uval}>(black_box(transmute(a)), {ival})"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1456,7 +1457,7 @@ fn gen_test_body( ); let val = rand_u32(asm_fmts[2].get(2..).unwrap().parse::().unwrap()); fn_params = format!("(a.v, b.v, {val})"); - as_params = format!("::<{val}>(transmute(a), transmute(b))"); + as_params = format!("::<{val}>(black_box(transmute(a)), black_box(transmute(b)))"); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1478,7 +1479,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "::<0>(transmute(a), o.as_mut_ptr())".to_string(); + as_params = "::<0>(black_box(transmute(a)), o.as_mut_ptr())".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1500,7 +1501,7 @@ fn gen_test_body( type_to_ct(in_t[1]) ); fn_params = "(a.v, b, 0)".to_string(); - as_params = "(transmute(a), o.as_mut_ptr(), 0)".to_string(); + as_params = "(black_box(transmute(a)), o.as_mut_ptr(), 0)".to_string(); } else { panic!("unsupported assembly format: {}", asm_fmts[2]); } @@ -1524,7 +1525,7 @@ fn gen_test_body( ); let val = rand_u32(type_to_imm(t).try_into().unwrap()); fn_params = format!("(a.v, b, 0, {val})"); - as_params = format!("::<0, {val}>(transmute(a), o.as_mut_ptr())"); + as_params = format!("::<0, {val}>(black_box(transmute(a)), o.as_mut_ptr())"); } (_, _) => panic!( "unsupported assembly format: {} for {}", diff --git a/library/stdarch/crates/stdarch-test/src/disassembly.rs b/library/stdarch/crates/stdarch-test/src/disassembly.rs index 237e8d2dc28a..7cf657baa0d7 100644 --- a/library/stdarch/crates/stdarch-test/src/disassembly.rs +++ b/library/stdarch/crates/stdarch-test/src/disassembly.rs @@ -158,16 +158,26 @@ fn parse(output: &str) -> HashSet { }; if cfg!(any(target_arch = "aarch64", target_arch = "arm64ec")) { - // Normalize [us]shll.* ..., #0 instructions to the preferred form: [us]xtl.* ... - // as neither LLVM objdump nor dumpbin does that. - // See https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-Long--an-alias-of-USHLL--USHLL2- - // and https://developer.arm.com/documentation/ddi0602/latest/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-Long--an-alias-of-SSHLL--SSHLL2- - // for details. + // Normalize `[us]shll{2}.* ..., #0` instructions to the preferred + // form: `[us]xtl{2}.* ...` as neither LLVM objdump nor dumpbin does that. + // + // SVE has `[us]shll[tb]` instructions that don't have an equivalent alias. + // + // See Arm documentation for details: + // + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/UXTL--UXTL2--Unsigned-extend-long--an-alias-of-USHLL--USHLL2-?lang=en + // - https://developer.arm.com/documentation/ddi0602/2026-03/SIMD-FP-Instructions/SXTL--SXTL2--Signed-extend-long--an-alias-of-SSHLL--SSHLL2-?lang=en fn is_shll(instr: &str) -> bool { if cfg!(target_env = "msvc") { - instr.starts_with("ushll") || instr.starts_with("sshll") + instr == "ushll" + || instr == "ushll2" + || instr == "sshll" + || instr == "sshll2" } else { - instr.starts_with("ushll.") || instr.starts_with("sshll.") + instr == "ushll." + || instr == "ushll2." + || instr == "sshll." + || instr == "sshll2." } } match (parts.first(), parts.last()) { diff --git a/library/stdarch/crates/stdarch-verify/src/lib.rs b/library/stdarch/crates/stdarch-verify/src/lib.rs index c81f5f45bcce..f7304ab32685 100644 --- a/library/stdarch/crates/stdarch-verify/src/lib.rs +++ b/library/stdarch/crates/stdarch-verify/src/lib.rs @@ -120,6 +120,13 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { ); } + // Newer intrinsics don't have `rustc_legacy_const_generics` - assume they belong at + // the end of the argument list + if required_const.is_empty() && legacy_const_generics.is_empty() { + legacy_const_generics = + (arguments.len()..(arguments.len() + const_arguments.len())).collect(); + } + // The list of required consts, used to verify the arguments, comes from either the // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. let required_const = if required_const.is_empty() { @@ -136,14 +143,14 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { arguments.insert(idx, ty); } - // strip leading underscore from fn name when building a test - // _mm_foo -> mm_foo such that the test name is test_mm_foo. - let test_name_string = format!("{name}"); - let mut test_name_id = test_name_string.as_str(); - while test_name_id.starts_with('_') { - test_name_id = &test_name_id[1..]; - } - let has_test = tests.contains(&format!("test_{test_name_id}")); + // Strip leading underscore from fn name when building a test + // `_mm_foo` -> `mm_foo` such that the test name is `test_mm_foo`. + let test_name = name.to_string(); + let test_name = test_name.trim_start_matches('_'); + let has_test = tests.contains(&format!("test_{test_name}")) + // SVE load/store tests start with `test` or `_with_` + || tests.iter().any(|t| t.starts_with(&format!("test_{test_name}")) + || t.ends_with(&format!("_with_{test_name}"))); let doc = find_doc(&f.attrs); @@ -347,6 +354,50 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "v4f32" => quote! { &v4f32 }, "v2f64" => quote! { &v2f64 }, + "svbool_t" => quote! { &SVBOOL }, + "svint8_t" => quote! { &SVI8 }, + "svint8x2_t" => quote! { &SVI8X2 }, + "svint8x3_t" => quote! { &SVI8X3 }, + "svint8x4_t" => quote! { &SVI8X4 }, + "svint16_t" => quote! { &SVI16 }, + "svint16x2_t" => quote! { &SVI16X2 }, + "svint16x3_t" => quote! { &SVI16X3 }, + "svint16x4_t" => quote! { &SVI16X4 }, + "svint32_t" => quote! { &SVI32 }, + "svint32x2_t" => quote! { &SVI32X2 }, + "svint32x3_t" => quote! { &SVI32X3 }, + "svint32x4_t" => quote! { &SVI32X4 }, + "svint64_t" => quote! { &SVI64 }, + "svint64x2_t" => quote! { &SVI64X2 }, + "svint64x3_t" => quote! { &SVI64X3 }, + "svint64x4_t" => quote! { &SVI64X4 }, + "svuint8_t" => quote! { &SVU8 }, + "svuint8x2_t" => quote! { &SVU8X2 }, + "svuint8x3_t" => quote! { &SVU8X3 }, + "svuint8x4_t" => quote! { &SVU8X4 }, + "svuint16_t" => quote! { &SVU16 }, + "svuint16x2_t" => quote! { &SVU16X2 }, + "svuint16x3_t" => quote! { &SVU16X3 }, + "svuint16x4_t" => quote! { &SVU16X4 }, + "svuint32_t" => quote! { &SVU32 }, + "svuint32x2_t" => quote! { &SVU32X2 }, + "svuint32x3_t" => quote! { &SVU32X3 }, + "svuint32x4_t" => quote! { &SVU32X4 }, + "svuint64_t" => quote! { &SVU64 }, + "svuint64x2_t" => quote! { &SVU64X2 }, + "svuint64x3_t" => quote! { &SVU64X3 }, + "svuint64x4_t" => quote! { &SVU64X4 }, + "svfloat32_t" => quote! { &SVF32 }, + "svfloat32x2_t" => quote! { &SVF32X2 }, + "svfloat32x3_t" => quote! { &SVF32X3 }, + "svfloat32x4_t" => quote! { &SVF32X4 }, + "svfloat64_t" => quote! { &SVF64 }, + "svfloat64x2_t" => quote! { &SVF64X2 }, + "svfloat64x3_t" => quote! { &SVF64X3 }, + "svfloat64x4_t" => quote! { &SVF64X4 }, + "svprfop" => quote! { &SVPRFOP }, + "svpattern" => quote! { &SVPATTERN }, + // Generic types "T" => quote! { &GENERICT }, "U" => quote! { &GENERICU }, diff --git a/library/stdarch/crates/stdarch-verify/tests/arm.rs b/library/stdarch/crates/stdarch-verify/tests/arm.rs index 3ef9ce2a38b6..2242bf4264e5 100644 --- a/library/stdarch/crates/stdarch-verify/tests/arm.rs +++ b/library/stdarch/crates/stdarch-verify/tests/arm.rs @@ -16,6 +16,7 @@ struct Function { doc: &'static str, } +static BOOL: Type = Type::PrimBool; static F16: Type = Type::PrimFloat(16); static F32: Type = Type::PrimFloat(32); static F64: Type = Type::PrimFloat(64); @@ -28,6 +29,7 @@ struct Function { static U64: Type = Type::PrimUnsigned(64); static U8: Type = Type::PrimUnsigned(8); static NEVER: Type = Type::Never; +static VOID: Type = Type::Void; static GENERICT: Type = Type::GenericParam("T"); static GENERICU: Type = Type::GenericParam("U"); @@ -151,19 +153,78 @@ struct Function { static U8X8X3: Type = Type::U(8, 8, 3); static U8X8X4: Type = Type::U(8, 8, 4); +static SVBOOL: Type = Type::Pred(1); +static SVBOOLX2: Type = Type::Pred(2); +static SVBOOLX3: Type = Type::Pred(3); +static SVBOOLX4: Type = Type::Pred(4); +static SVCOUNT: Type = Type::Pred(1); +static SVF16: Type = Type::SVF(16, 1); +static SVF16X2: Type = Type::SVF(16, 2); +static SVF16X3: Type = Type::SVF(16, 3); +static SVF16X4: Type = Type::SVF(16, 4); +static SVF32: Type = Type::SVF(32, 1); +static SVF32X2: Type = Type::SVF(32, 2); +static SVF32X3: Type = Type::SVF(32, 3); +static SVF32X4: Type = Type::SVF(32, 4); +static SVF64: Type = Type::SVF(64, 1); +static SVF64X2: Type = Type::SVF(64, 2); +static SVF64X3: Type = Type::SVF(64, 3); +static SVF64X4: Type = Type::SVF(64, 4); +static SVI8: Type = Type::SVI(8, 1); +static SVI8X2: Type = Type::SVI(8, 2); +static SVI8X3: Type = Type::SVI(8, 3); +static SVI8X4: Type = Type::SVI(8, 4); +static SVI16: Type = Type::SVI(16, 1); +static SVI16X2: Type = Type::SVI(16, 2); +static SVI16X3: Type = Type::SVI(16, 3); +static SVI16X4: Type = Type::SVI(16, 4); +static SVI32: Type = Type::SVI(32, 1); +static SVI32X2: Type = Type::SVI(32, 2); +static SVI32X3: Type = Type::SVI(32, 3); +static SVI32X4: Type = Type::SVI(32, 4); +static SVI64: Type = Type::SVI(64, 1); +static SVI64X2: Type = Type::SVI(64, 2); +static SVI64X3: Type = Type::SVI(64, 3); +static SVI64X4: Type = Type::SVI(64, 4); +static SVU8: Type = Type::SVU(8, 1); +static SVU8X2: Type = Type::SVU(8, 2); +static SVU8X3: Type = Type::SVU(8, 3); +static SVU8X4: Type = Type::SVU(8, 4); +static SVU16: Type = Type::SVU(16, 1); +static SVU16X2: Type = Type::SVU(16, 2); +static SVU16X3: Type = Type::SVU(16, 3); +static SVU16X4: Type = Type::SVU(16, 4); +static SVU32: Type = Type::SVU(32, 1); +static SVU32X2: Type = Type::SVU(32, 2); +static SVU32X3: Type = Type::SVU(32, 3); +static SVU32X4: Type = Type::SVU(32, 4); +static SVU64: Type = Type::SVU(64, 1); +static SVU64X2: Type = Type::SVU(64, 2); +static SVU64X3: Type = Type::SVU(64, 3); +static SVU64X4: Type = Type::SVU(64, 4); +static SVPRFOP: Type = Type::Enum("svprfop"); +static SVPATTERN: Type = Type::Enum("svpattern"); + #[derive(Debug, Copy, Clone, PartialEq)] enum Type { + Void, + PrimBool, PrimFloat(u8), PrimSigned(u8), PrimUnsigned(u8), PrimPoly(u8), MutPtr(&'static Type), ConstPtr(&'static Type), + Enum(&'static str), GenericParam(&'static str), I(u8, u8, u8), U(u8, u8, u8), P(u8, u8, u8), F(u8, u8, u8), + Pred(u8), + SVI(u8, u8), + SVU(u8, u8), + SVF(u8, u8), Never, } @@ -182,231 +243,20 @@ fn verify_all_signatures() { let mut all_valid = true; for rust in FUNCTIONS { + // Most SVE intrinsics just rely on the intrinsics test tool for validation if !rust.has_test { - let skip = [ - "vaddq_s64", - "vaddq_u64", - "vrsqrte_f32", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "udf", - "_clz_u8", - "_clz_u16", - "_clz_u32", - "_rbit_u32", - "_rev_u16", - "_rev_u32", - "__breakpoint", - "vpminq_f32", - "vpminq_f64", - "vpmaxq_f32", - "vpmaxq_f64", - "vcombine_s8", - "vcombine_s16", - "vcombine_s32", - "vcombine_s64", - "vcombine_u8", - "vcombine_u16", - "vcombine_u32", - "vcombine_u64", - "vcombine_p64", - "vcombine_f32", - "vcombine_p8", - "vcombine_p16", - "vcombine_f64", - "vtbl1_s8", - "vtbl1_u8", - "vtbl1_p8", - "vtbl2_s8", - "vtbl2_u8", - "vtbl2_p8", - "vtbl3_s8", - "vtbl3_u8", - "vtbl3_p8", - "vtbl4_s8", - "vtbl4_u8", - "vtbl4_p8", - "vtbx1_s8", - "vtbx1_u8", - "vtbx1_p8", - "vtbx2_s8", - "vtbx2_u8", - "vtbx2_p8", - "vtbx3_s8", - "vtbx3_u8", - "vtbx3_p8", - "vtbx4_s8", - "vtbx4_u8", - "vtbx4_p8", - "vqtbl1_s8", - "vqtbl1q_s8", - "vqtbl1_u8", - "vqtbl1q_u8", - "vqtbl1_p8", - "vqtbl1q_p8", - "vqtbx1_s8", - "vqtbx1q_s8", - "vqtbx1_u8", - "vqtbx1q_u8", - "vqtbx1_p8", - "vqtbx1q_p8", - "vqtbl2_s8", - "vqtbl2q_s8", - "vqtbl2_u8", - "vqtbl2q_u8", - "vqtbl2_p8", - "vqtbl2q_p8", - "vqtbx2_s8", - "vqtbx2q_s8", - "vqtbx2_u8", - "vqtbx2q_u8", - "vqtbx2_p8", - "vqtbx2q_p8", - "vqtbl3_s8", - "vqtbl3q_s8", - "vqtbl3_u8", - "vqtbl3q_u8", - "vqtbl3_p8", - "vqtbl3q_p8", - "vqtbx3_s8", - "vqtbx3q_s8", - "vqtbx3_u8", - "vqtbx3q_u8", - "vqtbx3_p8", - "vqtbx3q_p8", - "vqtbl4_s8", - "vqtbl4q_s8", - "vqtbl4_u8", - "vqtbl4q_u8", - "vqtbl4_p8", - "vqtbl4q_p8", - "vqtbx4_s8", - "vqtbx4q_s8", - "vqtbx4_u8", - "vqtbx4q_u8", - "vqtbx4_p8", - "vqtbx4q_p8", - "brk", - "_rev_u64", - "_clz_u64", - "_rbit_u64", - "_cls_u32", - "_cls_u64", - "_prefetch", - "vsli_n_s8", - "vsliq_n_s8", - "vsli_n_s16", - "vsliq_n_s16", - "vsli_n_s32", - "vsliq_n_s32", - "vsli_n_s64", - "vsliq_n_s64", - "vsli_n_u8", - "vsliq_n_u8", - "vsli_n_u16", - "vsliq_n_u16", - "vsli_n_u32", - "vsliq_n_u32", - "vsli_n_u64", - "vsliq_n_u64", - "vsli_n_p8", - "vsliq_n_p8", - "vsli_n_p16", - "vsliq_n_p16", - "vsli_n_p64", - "vsliq_n_p64", - "vsri_n_s8", - "vsriq_n_s8", - "vsri_n_s16", - "vsriq_n_s16", - "vsri_n_s32", - "vsriq_n_s32", - "vsri_n_s64", - "vsriq_n_s64", - "vsri_n_u8", - "vsriq_n_u8", - "vsri_n_u16", - "vsriq_n_u16", - "vsri_n_u32", - "vsriq_n_u32", - "vsri_n_u64", - "vsriq_n_u64", - "vsri_n_p8", - "vsriq_n_p8", - "vsri_n_p16", - "vsriq_n_p16", - "vsri_n_p64", - "vsriq_n_p64", - "__smulbb", - "__smultb", - "__smulbt", - "__smultt", - "__smulwb", - "__smulwt", - "__qadd", - "__qsub", - "__qdbl", - "__smlabb", - "__smlabt", - "__smlatb", - "__smlatt", - "__smlawb", - "__smlawt", - "__qadd8", - "__qsub8", - "__qsub16", - "__qadd16", - "__qasx", - "__qsax", - "__sadd16", - "__sadd8", - "__smlad", - "__smlsd", - "__sasx", - "__sel", - "__shadd8", - "__shadd16", - "__shsub8", - "__usub8", - "__ssub8", - "__shsub16", - "__smuad", - "__smuadx", - "__smusd", - "__smusdx", - "__usad8", - "__usada8", - "__ldrex", - "__strex", - "__ldrexb", - "__strexb", - "__ldrexh", - "__strexh", - "__clrex", - "__dbg", - ]; + if !SKIP_RUNTIME_TESTS.contains(&rust.name) + // Most run-time tests are handled by the intrinsic-test tool, except for + // load/stores (which have generated tests) + && (!rust.name.starts_with("sv") || rust.name.starts_with("svld") + || rust.name.starts_with("svst")) + // The load/store test generator can't handle these cases yet + && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset")) + && !(rust.name.starts_with("svldff1") && rust.name.contains("gather")) + { + println!("missing run-time test for `{}`", rust.name); + all_valid = false; + } } // Skip some intrinsics that aren't NEON and are located in different @@ -479,12 +329,21 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { let mut nconst = 0; let iter = rust.arguments.iter().zip(&arm.arguments).enumerate(); for (i, (rust_ty, (arm, arm_const))) in iter { - if *rust_ty != arm { - bail!("mismatched arguments: {rust_ty:?} != {arm:?}") + match (*rust_ty, arm) { + // SVE uses generic type parameters to handle void pointers + (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), + // SVE const generics use i32 over u64 for usability reasons + (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { + () + } + // svset doesn't have its const argument last as we assumed when building the Function + _ if rust.name.starts_with("svset") => (), + (x, y) if x == y => (), + _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"), } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) { + if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { bail!("argument const mismatch"); } } @@ -493,7 +352,10 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { bail!("wrong number of const arguments"); } - if rust.instrs.is_empty() { + if rust.instrs.is_empty() + && arm.instruction != "" + && !SKIP_ASSERT_INSTR_TESTS.contains(&rust.name) + { bail!( "instruction not listed for `{}`, but arm lists {:?}", rust.name, @@ -532,7 +394,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { Ok(()) } -#[derive(PartialEq)] +#[derive(Debug, PartialEq)] struct Intrinsic { name: String, ret: Option, @@ -547,7 +409,7 @@ struct JsonIntrinsic { arguments: Vec, return_type: ReturnType, #[serde(default)] - instructions: Vec>, + instructions: Option>>, } #[derive(Deserialize, Debug)] @@ -566,6 +428,8 @@ fn parse_intrinsics(intrinsics: Vec) -> HashMap Intrinsic { let name = intr.name; + // Remove '[' and ']' so that intrinsics of the form `svwhilerw[_s16]` becomes `svwhilerw_s16`. + let name = name.replace('[', "").replace(']', ""); let ret = if intr.return_type.value == "void" { None } else { @@ -574,18 +438,24 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { // This ignores multiple instructions and different optional sequences for now to mimic // the old HTML scraping behaviour - let instruction = intr.instructions.swap_remove(0).swap_remove(0); + let instruction = intr + .instructions + .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0)); let arguments = intr .arguments .iter() .map(|s| { - let (ty, konst) = match s.strip_prefix("const") { - Some(stripped) => (stripped.trim_start(), true), - None => (s.as_str(), false), + let ty = if let Some(i) = s.find('*') { + &s[..i + 1] + } else { + s.rsplit_once(' ').unwrap().0.trim_start_matches("const ") }; - let ty = ty.rsplit_once(' ').unwrap().0; - (parse_ty(ty), konst) + let ty = parse_ty(ty); + let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_)) + || s.starts_with("enum") + || s.rsplit_once(" ").unwrap().1.starts_with("imm"); + (ty, konst) }) .collect::>(); @@ -598,18 +468,27 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { } fn parse_ty(s: &str) -> Type { - let suffix = " const *"; - if let Some(base) = s.strip_suffix(suffix) { - Type::ConstPtr(parse_ty_base(base)) - } else if let Some(base) = s.strip_suffix(" *") { - Type::MutPtr(parse_ty_base(base)) + if let Some(ty) = s.strip_suffix("*") { + let ty = ty.trim(); + if let Some(ty) = ty.strip_prefix("const") { + // SVE intrinsics are west-const (`const int8_t *`) + Type::ConstPtr(parse_ty_base(ty)) + } else if let Some(ty) = ty.strip_suffix("const") { + // Neon intrinsics are east-const (`int8_t const *`) + Type::ConstPtr(parse_ty_base(ty)) + } else { + Type::MutPtr(parse_ty_base(ty)) + } } else { *parse_ty_base(s) } } fn parse_ty_base(s: &str) -> &'static Type { + let s = s.trim(); match s { + "bool" => &BOOL, + "void" => &VOID, "float16_t" => &F16, "float16x4_t" => &F16X4, "float16x4x2_t" => &F16X4X2, @@ -739,7 +618,4531 @@ fn parse_ty_base(s: &str) -> &'static Type { "uint8x8x2_t" => &U8X8X2, "uint8x8x3_t" => &U8X8X3, "uint8x8x4_t" => &U8X8X4, + "svbool_t" => &SVBOOL, + "svboolx2_t" => &SVBOOLX2, + "svboolx3_t" => &SVBOOLX3, + "svboolx4_t" => &SVBOOLX4, + "svcount_t" => &SVCOUNT, + "svfloat16_t" => &SVF16, + "svfloat16x2_t" => &SVF16X2, + "svfloat16x3_t" => &SVF16X3, + "svfloat16x4_t" => &SVF16X4, + "svfloat32_t" => &SVF32, + "svfloat32x2_t" => &SVF32X2, + "svfloat32x3_t" => &SVF32X3, + "svfloat32x4_t" => &SVF32X4, + "svfloat64_t" => &SVF64, + "svfloat64x2_t" => &SVF64X2, + "svfloat64x3_t" => &SVF64X3, + "svfloat64x4_t" => &SVF64X4, + "svint8_t" => &SVI8, + "svint8x2_t" => &SVI8X2, + "svint8x3_t" => &SVI8X3, + "svint8x4_t" => &SVI8X4, + "svint16_t" => &SVI16, + "svint16x2_t" => &SVI16X2, + "svint16x3_t" => &SVI16X3, + "svint16x4_t" => &SVI16X4, + "svint32_t" => &SVI32, + "svint32x2_t" => &SVI32X2, + "svint32x3_t" => &SVI32X3, + "svint32x4_t" => &SVI32X4, + "svint64_t" => &SVI64, + "svint64x2_t" => &SVI64X2, + "svint64x3_t" => &SVI64X3, + "svint64x4_t" => &SVI64X4, + "svuint8_t" => &SVU8, + "svuint8x2_t" => &SVU8X2, + "svuint8x3_t" => &SVU8X3, + "svuint8x4_t" => &SVU8X4, + "svuint16_t" => &SVU16, + "svuint16x2_t" => &SVU16X2, + "svuint16x3_t" => &SVU16X3, + "svuint16x4_t" => &SVU16X4, + "svuint32_t" => &SVU32, + "svuint32x2_t" => &SVU32X2, + "svuint32x3_t" => &SVU32X3, + "svuint32x4_t" => &SVU32X4, + "svuint64_t" => &SVU64, + "svuint64x2_t" => &SVU64X2, + "svuint64x3_t" => &SVU64X3, + "svuint64x4_t" => &SVU64X4, + "enum svprfop" => &SVPRFOP, + "enum svpattern" => &SVPATTERN, _ => panic!("failed to parse json type {s:?}"), } } + +// FIXME(arm-maintainers): Some tests require new rustc intrinsics in order to generate +// the appropriate instruction, though they do have the correct behaviour - these will be fixed +// but are disabled for now. +static SKIP_ASSERT_INSTR_TESTS: &'static [&'static str] = &["svpfalse_b"]; + +// FIXME(arm-maintainers): With the advent of the `intrinsic-test` tool, new tests of this kind +// are no longer being added and just adding to this list indefinitely isn't the best solution for +// dealing with that. +static SKIP_RUNTIME_TESTS: &'static [&'static str] = &[ + "vaddq_s64", + "vaddq_u64", + "vrsqrte_f32", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "udf", + "_clz_u8", + "_clz_u16", + "_clz_u32", + "_rbit_u32", + "_rev_u16", + "_rev_u32", + "__breakpoint", + "vpminq_f32", + "vpminq_f64", + "vpmaxq_f32", + "vpmaxq_f64", + "vcombine_s8", + "vcombine_s16", + "vcombine_s32", + "vcombine_s64", + "vcombine_u8", + "vcombine_u16", + "vcombine_u32", + "vcombine_u64", + "vcombine_p64", + "vcombine_f32", + "vcombine_p8", + "vcombine_p16", + "vcombine_f64", + "vtbl1_s8", + "vtbl1_u8", + "vtbl1_p8", + "vtbl2_s8", + "vtbl2_u8", + "vtbl2_p8", + "vtbl3_s8", + "vtbl3_u8", + "vtbl3_p8", + "vtbl4_s8", + "vtbl4_u8", + "vtbl4_p8", + "vtbx1_s8", + "vtbx1_u8", + "vtbx1_p8", + "vtbx2_s8", + "vtbx2_u8", + "vtbx2_p8", + "vtbx3_s8", + "vtbx3_u8", + "vtbx3_p8", + "vtbx4_s8", + "vtbx4_u8", + "vtbx4_p8", + "vqtbl1_s8", + "vqtbl1q_s8", + "vqtbl1_u8", + "vqtbl1q_u8", + "vqtbl1_p8", + "vqtbl1q_p8", + "vqtbx1_s8", + "vqtbx1q_s8", + "vqtbx1_u8", + "vqtbx1q_u8", + "vqtbx1_p8", + "vqtbx1q_p8", + "vqtbl2_s8", + "vqtbl2q_s8", + "vqtbl2_u8", + "vqtbl2q_u8", + "vqtbl2_p8", + "vqtbl2q_p8", + "vqtbx2_s8", + "vqtbx2q_s8", + "vqtbx2_u8", + "vqtbx2q_u8", + "vqtbx2_p8", + "vqtbx2q_p8", + "vqtbl3_s8", + "vqtbl3q_s8", + "vqtbl3_u8", + "vqtbl3q_u8", + "vqtbl3_p8", + "vqtbl3q_p8", + "vqtbx3_s8", + "vqtbx3q_s8", + "vqtbx3_u8", + "vqtbx3q_u8", + "vqtbx3_p8", + "vqtbx3q_p8", + "vqtbl4_s8", + "vqtbl4q_s8", + "vqtbl4_u8", + "vqtbl4q_u8", + "vqtbl4_p8", + "vqtbl4q_p8", + "vqtbx4_s8", + "vqtbx4q_s8", + "vqtbx4_u8", + "vqtbx4q_u8", + "vqtbx4_p8", + "vqtbx4q_p8", + "brk", + "_rev_u64", + "_clz_u64", + "_rbit_u64", + "_cls_u32", + "_cls_u64", + "_prefetch", + "vsli_n_s8", + "vsliq_n_s8", + "vsli_n_s16", + "vsliq_n_s16", + "vsli_n_s32", + "vsliq_n_s32", + "vsli_n_s64", + "vsliq_n_s64", + "vsli_n_u8", + "vsliq_n_u8", + "vsli_n_u16", + "vsliq_n_u16", + "vsli_n_u32", + "vsliq_n_u32", + "vsli_n_u64", + "vsliq_n_u64", + "vsli_n_p8", + "vsliq_n_p8", + "vsli_n_p16", + "vsliq_n_p16", + "vsli_n_p64", + "vsliq_n_p64", + "vsri_n_s8", + "vsriq_n_s8", + "vsri_n_s16", + "vsriq_n_s16", + "vsri_n_s32", + "vsriq_n_s32", + "vsri_n_s64", + "vsriq_n_s64", + "vsri_n_u8", + "vsriq_n_u8", + "vsri_n_u16", + "vsriq_n_u16", + "vsri_n_u32", + "vsriq_n_u32", + "vsri_n_u64", + "vsriq_n_u64", + "vsri_n_p8", + "vsriq_n_p8", + "vsri_n_p16", + "vsriq_n_p16", + "vsri_n_p64", + "vsriq_n_p64", + "__smulbb", + "__smultb", + "__smulbt", + "__smultt", + "__smulwb", + "__smulwt", + "__qadd", + "__qsub", + "__qdbl", + "__smlabb", + "__smlabt", + "__smlatb", + "__smlatt", + "__smlawb", + "__smlawt", + "__qadd8", + "__qsub8", + "__qsub16", + "__qadd16", + "__qasx", + "__qsax", + "__sadd16", + "__sadd8", + "__smlad", + "__smlsd", + "__sasx", + "__sel", + "__shadd8", + "__shadd16", + "__shsub8", + "__usub8", + "__ssub8", + "__shsub16", + "__smuad", + "__smuadx", + "__smusd", + "__smusdx", + "__usad8", + "__usada8", + "__ldrex", + "__strex", + "__ldrexb", + "__strexb", + "__ldrexh", + "__strexh", + "__clrex", + "__dbg", + "__crc32cd", + "__crc32d", + "__jcvt", + "vabal_high_s8", + "vabal_high_s16", + "vabal_high_s32", + "vabal_high_u8", + "vabal_high_u16", + "vabal_high_u32", + "vabd_f64", + "vabdq_f64", + "vabdd_f64", + "vabds_f32", + "vabdh_f16", + "vabdl_high_s16", + "vabdl_high_s32", + "vabdl_high_s8", + "vabdl_high_u8", + "vabdl_high_u16", + "vabdl_high_u32", + "vabs_f64", + "vabsq_f64", + "vabs_s64", + "vabsq_s64", + "vabsd_s64", + "vaddlv_s16", + "vaddlvq_s16", + "vaddlvq_s32", + "vaddlv_s32", + "vaddlv_s8", + "vaddlvq_s8", + "vaddlv_u16", + "vaddlvq_u16", + "vaddlvq_u32", + "vaddlv_u32", + "vaddlv_u8", + "vaddlvq_u8", + "vaddv_f32", + "vaddvq_f32", + "vaddvq_f64", + "vaddv_s32", + "vaddv_s8", + "vaddvq_s8", + "vaddv_s16", + "vaddvq_s16", + "vaddvq_s32", + "vaddv_u32", + "vaddv_u8", + "vaddvq_u8", + "vaddv_u16", + "vaddvq_u16", + "vaddvq_u32", + "vaddvq_s64", + "vaddvq_u64", + "vamax_f16", + "vamaxq_f16", + "vamax_f32", + "vamaxq_f32", + "vamaxq_f64", + "vamin_f16", + "vaminq_f16", + "vamin_f32", + "vaminq_f32", + "vaminq_f64", + "vbcaxq_s8", + "vbcaxq_s16", + "vbcaxq_s32", + "vbcaxq_s64", + "vbcaxq_u8", + "vbcaxq_u16", + "vbcaxq_u32", + "vbcaxq_u64", + "vcadd_rot270_f16", + "vcaddq_rot270_f16", + "vcadd_rot270_f32", + "vcaddq_rot270_f32", + "vcaddq_rot270_f64", + "vcadd_rot90_f16", + "vcaddq_rot90_f16", + "vcadd_rot90_f32", + "vcaddq_rot90_f32", + "vcaddq_rot90_f64", + "vcage_f64", + "vcageq_f64", + "vcaged_f64", + "vcages_f32", + "vcageh_f16", + "vcagt_f64", + "vcagtq_f64", + "vcagtd_f64", + "vcagts_f32", + "vcagth_f16", + "vcale_f64", + "vcaleq_f64", + "vcaled_f64", + "vcales_f32", + "vcaleh_f16", + "vcalt_f64", + "vcaltq_f64", + "vcaltd_f64", + "vcalts_f32", + "vcalth_f16", + "vceq_f64", + "vceqq_f64", + "vceq_s64", + "vceqq_s64", + "vceq_u64", + "vceqq_u64", + "vceq_p64", + "vceqq_p64", + "vceqd_f64", + "vceqs_f32", + "vceqd_s64", + "vceqd_u64", + "vceqh_f16", + "vceqz_f16", + "vceqzq_f16", + "vceqz_f32", + "vceqzq_f32", + "vceqz_f64", + "vceqzq_f64", + "vceqz_s8", + "vceqzq_s8", + "vceqz_s16", + "vceqzq_s16", + "vceqz_s32", + "vceqzq_s32", + "vceqz_s64", + "vceqzq_s64", + "vceqz_p8", + "vceqzq_p8", + "vceqz_p64", + "vceqzq_p64", + "vceqz_u8", + "vceqzq_u8", + "vceqz_u16", + "vceqzq_u16", + "vceqz_u32", + "vceqzq_u32", + "vceqz_u64", + "vceqzq_u64", + "vceqzd_s64", + "vceqzd_u64", + "vceqzh_f16", + "vceqzs_f32", + "vceqzd_f64", + "vcge_f64", + "vcgeq_f64", + "vcge_s64", + "vcgeq_s64", + "vcge_u64", + "vcgeq_u64", + "vcged_f64", + "vcges_f32", + "vcged_s64", + "vcged_u64", + "vcgeh_f16", + "vcgez_f32", + "vcgezq_f32", + "vcgez_f64", + "vcgezq_f64", + "vcgez_s8", + "vcgezq_s8", + "vcgez_s16", + "vcgezq_s16", + "vcgez_s32", + "vcgezq_s32", + "vcgez_s64", + "vcgezq_s64", + "vcgezd_f64", + "vcgezs_f32", + "vcgezd_s64", + "vcgezh_f16", + "vcgt_f64", + "vcgtq_f64", + "vcgt_s64", + "vcgtq_s64", + "vcgt_u64", + "vcgtq_u64", + "vcgtd_f64", + "vcgts_f32", + "vcgtd_s64", + "vcgtd_u64", + "vcgth_f16", + "vcgtz_f32", + "vcgtzq_f32", + "vcgtz_f64", + "vcgtzq_f64", + "vcgtz_s8", + "vcgtzq_s8", + "vcgtz_s16", + "vcgtzq_s16", + "vcgtz_s32", + "vcgtzq_s32", + "vcgtz_s64", + "vcgtzq_s64", + "vcgtzd_f64", + "vcgtzs_f32", + "vcgtzd_s64", + "vcgtzh_f16", + "vcle_f64", + "vcleq_f64", + "vcle_s64", + "vcleq_s64", + "vcle_u64", + "vcleq_u64", + "vcled_f64", + "vcles_f32", + "vcled_u64", + "vcled_s64", + "vcleh_f16", + "vclez_f32", + "vclezq_f32", + "vclez_f64", + "vclezq_f64", + "vclez_s8", + "vclezq_s8", + "vclez_s16", + "vclezq_s16", + "vclez_s32", + "vclezq_s32", + "vclez_s64", + "vclezq_s64", + "vclezd_f64", + "vclezs_f32", + "vclezd_s64", + "vclezh_f16", + "vclt_f64", + "vcltq_f64", + "vclt_s64", + "vcltq_s64", + "vclt_u64", + "vcltq_u64", + "vcltd_u64", + "vcltd_s64", + "vclth_f16", + "vclts_f32", + "vcltd_f64", + "vcltz_f32", + "vcltzq_f32", + "vcltz_f64", + "vcltzq_f64", + "vcltz_s8", + "vcltzq_s8", + "vcltz_s16", + "vcltzq_s16", + "vcltz_s32", + "vcltzq_s32", + "vcltz_s64", + "vcltzq_s64", + "vcltzd_f64", + "vcltzs_f32", + "vcltzd_s64", + "vcltzh_f16", + "vcmla_f16", + "vcmlaq_f16", + "vcmla_f32", + "vcmlaq_f32", + "vcmlaq_f64", + "vcmla_lane_f16", + "vcmlaq_lane_f16", + "vcmla_lane_f32", + "vcmlaq_lane_f32", + "vcmla_laneq_f16", + "vcmlaq_laneq_f16", + "vcmla_laneq_f32", + "vcmlaq_laneq_f32", + "vcmla_rot180_f16", + "vcmlaq_rot180_f16", + "vcmla_rot180_f32", + "vcmlaq_rot180_f32", + "vcmlaq_rot180_f64", + "vcmla_rot180_lane_f16", + "vcmlaq_rot180_lane_f16", + "vcmla_rot180_lane_f32", + "vcmlaq_rot180_lane_f32", + "vcmla_rot180_laneq_f16", + "vcmlaq_rot180_laneq_f16", + "vcmla_rot180_laneq_f32", + "vcmlaq_rot180_laneq_f32", + "vcmla_rot270_f16", + "vcmlaq_rot270_f16", + "vcmla_rot270_f32", + "vcmlaq_rot270_f32", + "vcmlaq_rot270_f64", + "vcmla_rot270_lane_f16", + "vcmlaq_rot270_lane_f16", + "vcmla_rot270_lane_f32", + "vcmlaq_rot270_lane_f32", + "vcmla_rot270_laneq_f16", + "vcmlaq_rot270_laneq_f16", + "vcmla_rot270_laneq_f32", + "vcmlaq_rot270_laneq_f32", + "vcmla_rot90_f16", + "vcmlaq_rot90_f16", + "vcmla_rot90_f32", + "vcmlaq_rot90_f32", + "vcmlaq_rot90_f64", + "vcmla_rot90_lane_f16", + "vcmlaq_rot90_lane_f16", + "vcmla_rot90_lane_f32", + "vcmlaq_rot90_lane_f32", + "vcmla_rot90_laneq_f16", + "vcmlaq_rot90_laneq_f16", + "vcmla_rot90_laneq_f32", + "vcmlaq_rot90_laneq_f32", + "vcopy_lane_f32", + "vcopy_lane_s8", + "vcopy_lane_s16", + "vcopy_lane_s32", + "vcopy_lane_u8", + "vcopy_lane_u16", + "vcopy_lane_u32", + "vcopy_lane_p8", + "vcopy_lane_p16", + "vcopy_laneq_f32", + "vcopy_laneq_s8", + "vcopy_laneq_s16", + "vcopy_laneq_s32", + "vcopy_laneq_u8", + "vcopy_laneq_u16", + "vcopy_laneq_u32", + "vcopy_laneq_p8", + "vcopy_laneq_p16", + "vcopyq_lane_f32", + "vcopyq_lane_f64", + "vcopyq_lane_s64", + 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"vld1_u8_x3", + "vld1_u8_x4", + "vld1q_u8_x2", + "vld1q_u8_x3", + "vld1q_u8_x4", + "vld1_u16_x2", + "vld1_u16_x3", + "vld1_u16_x4", + "vld1q_u16_x2", + "vld1q_u16_x3", + "vld1q_u16_x4", + "vld1_u32_x2", + "vld1_u32_x3", + "vld1_u32_x4", + "vld1q_u32_x2", + "vld1q_u32_x3", + "vld1q_u32_x4", + "vld1_u64_x2", + "vld1_u64_x3", + "vld1_u64_x4", + "vld1q_u64_x2", + "vld1q_u64_x3", + "vld1q_u64_x4", + "vld1_p8_x2", + "vld1_p8_x3", + "vld1_p8_x4", + "vld1q_p8_x2", + "vld1q_p8_x3", + "vld1q_p8_x4", + "vld1_p16_x2", + "vld1_p16_x3", + "vld1_p16_x4", + "vld1q_p16_x2", + "vld1q_p16_x3", + "vld1q_p16_x4", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f16", + "vld2q_dup_f16", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_f32", + "vld2q_dup_f32", + "vld2_dup_s8", + "vld2q_dup_s8", + "vld2_dup_s16", + "vld2q_dup_s16", + "vld2_dup_s32", + "vld2q_dup_s32", + "vld2_dup_p64", + "vld2_dup_s64", + "vld2_dup_s64", + "vld2_dup_u64", + "vld2_dup_u8", + "vld2_dup_u8", + "vld2q_dup_u8", + "vld2q_dup_u8", + "vld2_dup_u16", + "vld2_dup_u16", + "vld2q_dup_u16", + "vld2q_dup_u16", + "vld2_dup_u32", + "vld2_dup_u32", + "vld2q_dup_u32", + "vld2q_dup_u32", + "vld2_dup_p8", + "vld2_dup_p8", + "vld2q_dup_p8", + "vld2q_dup_p8", + "vld2_dup_p16", + "vld2_dup_p16", + "vld2q_dup_p16", + "vld2q_dup_p16", + "vld2_f16", + "vld2q_f16", + "vld2_f16", + "vld2q_f16", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_f32", + "vld2q_f32", + "vld2_s8", + "vld2q_s8", + "vld2_s16", + "vld2q_s16", + "vld2_s32", + "vld2q_s32", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f16", + "vld2q_lane_f16", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2q_lane_s16", + "vld2_lane_s32", + "vld2q_lane_s32", + "vld2_lane_f32", + "vld2q_lane_f32", + "vld2q_lane_s16", + "vld2q_lane_s32", + "vld2_lane_s8", + "vld2_lane_s16", + "vld2_lane_s32", + "vld2_lane_u8", + "vld2_lane_u16", + "vld2q_lane_u16", + "vld2_lane_u32", + "vld2q_lane_u32", + "vld2_lane_p8", + "vld2_lane_p16", + "vld2q_lane_p16", + "vld2_p64", + "vld2_s64", + "vld2_s64", + "vld2_u64", + "vld2_u8", + "vld2q_u8", + "vld2_u16", + "vld2q_u16", + "vld2_u32", + "vld2q_u32", + "vld2_p8", + "vld2q_p8", + "vld2_p16", + "vld2q_p16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f16", + "vld3q_dup_f16", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_s64", + "vld3_dup_f32", + "vld3q_dup_f32", + "vld3_dup_s8", + "vld3q_dup_s8", + "vld3_dup_s16", + "vld3q_dup_s16", + "vld3_dup_s32", + "vld3q_dup_s32", + "vld3_dup_p64", + "vld3_dup_s64", + "vld3_dup_u64", + "vld3_dup_u8", + "vld3_dup_u8", + "vld3q_dup_u8", + "vld3q_dup_u8", + "vld3_dup_u16", + "vld3_dup_u16", + "vld3q_dup_u16", + "vld3q_dup_u16", + "vld3_dup_u32", + "vld3_dup_u32", + "vld3q_dup_u32", + "vld3q_dup_u32", + "vld3_dup_p8", + "vld3_dup_p8", + "vld3q_dup_p8", + "vld3q_dup_p8", + "vld3_dup_p16", + "vld3_dup_p16", + "vld3q_dup_p16", + "vld3q_dup_p16", + "vld3_f16", + "vld3q_f16", + "vld3_f16", + "vld3q_f16", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_f32", + "vld3q_f32", + "vld3_s8", + "vld3q_s8", + "vld3_s16", + "vld3q_s16", + "vld3_s32", + "vld3q_s32", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f16", + "vld3q_lane_f16", + "vld3_lane_f32", + "vld3q_lane_f32", + "vld3_lane_f32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_s8", + "vld3_lane_s16", + "vld3q_lane_s16", + "vld3_lane_s32", + "vld3q_lane_s32", + "vld3_lane_u8", + "vld3_lane_u16", + "vld3q_lane_u16", + "vld3_lane_u32", + "vld3q_lane_u32", + "vld3_lane_p8", + "vld3_lane_p16", + "vld3q_lane_p16", + "vld3_p64", + "vld3_s64", + "vld3_s64", + "vld3_u64", + "vld3_u8", + "vld3q_u8", + "vld3_u16", + "vld3q_u16", + "vld3_u32", + "vld3q_u32", + "vld3_p8", + "vld3q_p8", + "vld3_p16", + "vld3q_p16", + "vld3q_lane_f32", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f16", + "vld4q_dup_f16", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_f32", + "vld4q_dup_f32", + "vld4_dup_s8", + "vld4q_dup_s8", + "vld4_dup_s16", + "vld4q_dup_s16", + "vld4_dup_s32", + "vld4q_dup_s32", + "vld4_dup_s64", + "vld4_dup_p64", + "vld4_dup_s64", + "vld4_dup_u64", + "vld4_dup_u8", + "vld4_dup_u8", + "vld4q_dup_u8", + "vld4q_dup_u8", + "vld4_dup_u16", + "vld4_dup_u16", + "vld4q_dup_u16", + "vld4q_dup_u16", + "vld4_dup_u32", + "vld4_dup_u32", + "vld4q_dup_u32", + "vld4q_dup_u32", + "vld4_dup_p8", + "vld4_dup_p8", + "vld4q_dup_p8", + "vld4q_dup_p8", + "vld4_dup_p16", + "vld4_dup_p16", + "vld4q_dup_p16", + "vld4q_dup_p16", + "vld4_f16", + "vld4q_f16", + "vld4_f16", + "vld4q_f16", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_f32", + "vld4q_f32", + "vld4_s8", + "vld4q_s8", + "vld4_s16", + "vld4q_s16", + "vld4_s32", + "vld4q_s32", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f16", + "vld4q_lane_f16", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_f32", + "vld4q_lane_f32", + "vld4_lane_s8", + "vld4_lane_s16", + "vld4q_lane_s16", + "vld4_lane_s32", + "vld4q_lane_s32", + "vld4_lane_u8", + "vld4_lane_u16", + "vld4q_lane_u16", + "vld4_lane_u32", + "vld4q_lane_u32", + "vld4_lane_p8", + "vld4_lane_p16", + "vld4q_lane_p16", + "vld4_p64", + "vld4_s64", + "vld4_s64", + "vld4_u64", + "vld4_u8", + "vld4q_u8", + "vld4_u16", + "vld4q_u16", + "vld4_u32", + "vld4q_u32", + "vld4_p8", + "vld4q_p8", + "vld4_p16", + "vld4q_p16", + "vmax_f16", + "vmaxq_f16", + "vmax_f32", + "vmaxq_f32", + "vmax_s8", + "vmaxq_s8", + "vmax_s16", + "vmaxq_s16", + "vmax_s32", + "vmaxq_s32", + "vmax_u8", + "vmaxq_u8", + "vmax_u16", + "vmaxq_u16", + "vmax_u32", + "vmaxq_u32", + "vmaxnm_f16", + "vmaxnmq_f16", + "vmaxnm_f32", + "vmaxnmq_f32", + "vmin_f16", + "vminq_f16", + "vmin_f32", + "vminq_f32", + "vmin_s8", + "vminq_s8", + "vmin_s16", + "vminq_s16", + "vmin_s32", + "vminq_s32", + "vmin_u8", + "vminq_u8", + "vmin_u16", + "vminq_u16", + "vmin_u32", + "vminq_u32", + "vminnm_f16", + "vminnmq_f16", + "vminnm_f32", + "vminnmq_f32", + "vmla_f32", + "vmlaq_f32", + "vmla_lane_f32", + "vmla_laneq_f32", + "vmlaq_lane_f32", + "vmlaq_laneq_f32", + "vmla_lane_s16", + "vmla_lane_u16", + "vmla_laneq_s16", + "vmla_laneq_u16", + "vmlaq_lane_s16", + "vmlaq_lane_u16", + "vmlaq_laneq_s16", + "vmlaq_laneq_u16", + "vmla_lane_s32", + "vmla_lane_u32", + "vmla_laneq_s32", + "vmla_laneq_u32", + "vmlaq_lane_s32", + "vmlaq_lane_u32", + "vmlaq_laneq_s32", + "vmlaq_laneq_u32", + "vmla_n_f32", + "vmlaq_n_f32", + "vmla_n_s16", + "vmlaq_n_s16", + "vmla_n_u16", + "vmlaq_n_u16", + "vmla_n_s32", + "vmlaq_n_s32", + "vmla_n_u32", + "vmlaq_n_u32", + "vmla_s8", + "vmlaq_s8", + "vmla_s16", + "vmlaq_s16", + "vmla_s32", + "vmlaq_s32", + "vmla_u8", + "vmlaq_u8", + "vmla_u16", + "vmlaq_u16", + "vmla_u32", + "vmlaq_u32", + "vmlal_lane_s16", + "vmlal_laneq_s16", + "vmlal_lane_s32", + "vmlal_laneq_s32", + "vmlal_lane_u16", + "vmlal_laneq_u16", + "vmlal_lane_u32", + "vmlal_laneq_u32", + "vmlal_n_s16", + "vmlal_n_s32", + "vmlal_n_u16", + "vmlal_n_u32", + "vmlal_s8", + "vmlal_s16", + "vmlal_s32", + "vmlal_u8", + "vmlal_u16", + "vmlal_u32", + "vmls_f32", + "vmlsq_f32", + "vmls_lane_f32", + "vmls_laneq_f32", + "vmlsq_lane_f32", + "vmlsq_laneq_f32", + "vmls_lane_s16", + "vmls_lane_u16", + "vmls_laneq_s16", + "vmls_laneq_u16", + "vmlsq_lane_s16", + "vmlsq_lane_u16", + "vmlsq_laneq_s16", + "vmlsq_laneq_u16", + "vmls_lane_s32", + "vmls_lane_u32", + "vmls_laneq_s32", + "vmls_laneq_u32", + "vmlsq_lane_s32", + "vmlsq_lane_u32", + "vmlsq_laneq_s32", + "vmlsq_laneq_u32", + "vmls_n_f32", + "vmlsq_n_f32", + "vmls_n_s16", + "vmlsq_n_s16", + "vmls_n_u16", + "vmlsq_n_u16", + "vmls_n_s32", + "vmlsq_n_s32", + "vmls_n_u32", + "vmlsq_n_u32", + "vmls_s8", + "vmlsq_s8", + "vmls_s16", + "vmlsq_s16", + "vmls_s32", + "vmlsq_s32", + "vmls_u8", + "vmlsq_u8", + "vmls_u16", + "vmlsq_u16", + "vmls_u32", + "vmlsq_u32", + "vmlsl_lane_s16", + "vmlsl_laneq_s16", + "vmlsl_lane_s32", + "vmlsl_laneq_s32", + "vmlsl_lane_u16", + "vmlsl_laneq_u16", + "vmlsl_lane_u32", + "vmlsl_laneq_u32", + "vmlsl_n_s16", + "vmlsl_n_s32", + "vmlsl_n_u16", + "vmlsl_n_u32", + "vmlsl_s8", + "vmlsl_s16", + "vmlsl_s32", + "vmlsl_u8", + "vmlsl_u16", + "vmlsl_u32", + "vmmlaq_s32", + "vmmlaq_u32", + "vmov_n_f16", + "vmovq_n_f16", + "vmul_f16", + "vmulq_f16", + "vmul_lane_f16", + "vmulq_lane_f16", + "vmul_lane_f32", + "vmul_laneq_f32", + "vmulq_lane_f32", + "vmulq_laneq_f32", + "vmul_lane_s16", + "vmulq_lane_s16", + "vmul_lane_s32", + "vmulq_lane_s32", + "vmul_lane_u16", + "vmulq_lane_u16", + "vmul_lane_u32", + "vmulq_lane_u32", + "vmul_laneq_s16", + "vmulq_laneq_s16", + "vmul_laneq_s32", + "vmulq_laneq_s32", + "vmul_laneq_u16", + "vmulq_laneq_u16", + "vmul_laneq_u32", + "vmulq_laneq_u32", + "vmul_n_f16", + "vmulq_n_f16", + "vmul_n_f32", + "vmulq_n_f32", + "vmul_n_s16", + "vmulq_n_s16", + "vmul_n_s32", + "vmulq_n_s32", + "vmul_n_u16", + "vmulq_n_u16", + "vmul_n_u32", + "vmulq_n_u32", + "vmul_p8", + "vmulq_p8", + "vmull_lane_s16", + "vmull_laneq_s16", + "vmull_lane_s32", + "vmull_laneq_s32", + "vmull_lane_u16", + "vmull_laneq_u16", + "vmull_lane_u32", + "vmull_laneq_u32", + "vmull_n_s16", + "vmull_n_s32", + "vmull_n_u16", + "vmull_n_u32", + "vmull_p8", + "vmull_s16", + "vmull_s32", + "vmull_s8", + "vmull_u8", + "vmull_u16", + "vmull_u32", + "vneg_f16", + "vnegq_f16", + "vneg_f32", + "vnegq_f32", + "vneg_s8", + "vnegq_s8", + "vneg_s16", + "vnegq_s16", + "vneg_s32", + "vnegq_s32", + "vpadal_s8", + "vpadalq_s8", + "vpadal_s16", + "vpadalq_s16", + "vpadal_s32", + "vpadalq_s32", + "vpadal_u8", + "vpadalq_u8", + "vpadal_u16", + "vpadalq_u16", + "vpadal_u32", + "vpadalq_u32", + "vpadd_f16", + "vpadd_f32", + "vpadd_s8", + "vpadd_s16", + "vpadd_s32", + "vpadd_u8", + "vpadd_u8", + "vpadd_u16", + "vpadd_u16", + "vpadd_u32", + "vpadd_u32", + "vpaddl_s8", + "vpaddlq_s8", + "vpaddl_s16", + "vpaddlq_s16", + "vpaddl_s32", + "vpaddlq_s32", + "vpaddl_u8", + "vpaddlq_u8", + "vpaddl_u16", + "vpaddlq_u16", + "vpaddl_u32", + "vpaddlq_u32", + "vpmax_f32", + "vpmax_s8", + "vpmax_s16", + "vpmax_s32", + "vpmax_u8", + "vpmax_u16", + "vpmax_u32", + "vpmin_f32", + "vpmin_s8", + "vpmin_s16", + "vpmin_s32", + "vpmin_u8", + "vpmin_u16", + "vpmin_u32", + "vqabs_s8", + "vqabsq_s8", + "vqabs_s16", + "vqabsq_s16", + "vqabs_s32", + "vqabsq_s32", + "vqadd_s64", + "vqaddq_s64", + "vqadd_u64", + "vqaddq_u64", + "vqdmlal_lane_s16", + "vqdmlal_lane_s32", + "vqdmlal_n_s16", + "vqdmlal_n_s32", + "vqdmlal_s16", + "vqdmlal_s32", + "vqdmlsl_lane_s16", + "vqdmlsl_lane_s32", + "vqdmlsl_n_s16", + "vqdmlsl_n_s32", + "vqdmlsl_s16", + "vqdmlsl_s32", + "vqdmulh_laneq_s16", + "vqdmulhq_laneq_s16", + "vqdmulh_laneq_s32", + "vqdmulhq_laneq_s32", + "vqdmulh_n_s16", + "vqdmulhq_n_s16", + "vqdmulh_n_s32", + "vqdmulhq_n_s32", + "vqdmulh_s16", + "vqdmulhq_s16", + "vqdmulh_s32", + "vqdmulhq_s32", + "vqdmull_lane_s16", + "vqdmull_lane_s32", + "vqdmull_n_s16", + "vqdmull_n_s32", + "vqdmull_s16", + "vqdmull_s32", + "vqmovn_s16", + "vqmovn_s32", + "vqmovn_s64", + "vqmovn_u16", + "vqmovn_u32", + "vqmovn_u64", + "vqmovun_s16", + "vqmovun_s32", + "vqmovun_s64", + "vqneg_s8", + "vqnegq_s8", + "vqneg_s16", + "vqnegq_s16", + "vqneg_s32", + "vqnegq_s32", + "vqrdmulh_lane_s16", + "vqrdmulh_lane_s32", + "vqrdmulh_laneq_s16", + "vqrdmulh_laneq_s32", + "vqrdmulhq_lane_s16", + "vqrdmulhq_lane_s32", + "vqrdmulhq_laneq_s16", + "vqrdmulhq_laneq_s32", + "vqrdmulh_n_s16", + "vqrdmulhq_n_s16", + "vqrdmulh_n_s32", + "vqrdmulhq_n_s32", + "vqrdmulh_s16", + "vqrdmulhq_s16", + "vqrdmulh_s32", + "vqrdmulhq_s32", + "vqrshl_s8", + "vqrshlq_s8", + "vqrshl_s16", + "vqrshlq_s16", + "vqrshl_s32", + "vqrshlq_s32", + "vqrshl_s64", + "vqrshlq_s64", + "vqrshl_u8", + "vqrshlq_u8", + "vqrshl_u16", + "vqrshlq_u16", + "vqrshl_u32", + "vqrshlq_u32", + "vqrshl_u64", + "vqrshlq_u64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_s16", + "vqrshrn_n_s32", + "vqrshrn_n_s64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrn_n_u16", + "vqrshrn_n_u32", + "vqrshrn_n_u64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqrshrun_n_s16", + "vqrshrun_n_s32", + "vqrshrun_n_s64", + "vqshl_n_s8", + "vqshlq_n_s8", + "vqshl_n_s16", + "vqshlq_n_s16", + "vqshl_n_s32", + "vqshlq_n_s32", + "vqshl_n_s64", + "vqshlq_n_s64", + "vqshl_n_u8", + "vqshlq_n_u8", + "vqshl_n_u16", + "vqshlq_n_u16", + "vqshl_n_u32", + "vqshlq_n_u32", + "vqshl_n_u64", + "vqshlq_n_u64", + "vqshl_s8", + "vqshlq_s8", + "vqshl_s16", + "vqshlq_s16", + "vqshl_s32", + "vqshlq_s32", + "vqshl_s64", + "vqshlq_s64", + "vqshl_u8", + "vqshlq_u8", + "vqshl_u16", + "vqshlq_u16", + "vqshl_u32", + "vqshlq_u32", + "vqshl_u64", + "vqshlq_u64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshlu_n_s8", + "vqshluq_n_s8", + "vqshlu_n_s16", + "vqshluq_n_s16", + "vqshlu_n_s32", + "vqshluq_n_s32", + "vqshlu_n_s64", + "vqshluq_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_s16", + "vqshrn_n_s32", + "vqshrn_n_s64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrn_n_u16", + "vqshrn_n_u32", + "vqshrn_n_u64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqshrun_n_s16", + "vqshrun_n_s32", + "vqshrun_n_s64", + "vqsub_s64", + "vqsubq_s64", + "vqsub_u64", + "vqsubq_u64", + "vraddhn_high_s16", + "vraddhn_high_s32", + "vraddhn_high_s64", + "vraddhn_high_u16", + "vraddhn_high_u32", + "vraddhn_high_u64", + "vraddhn_s16", + "vraddhn_s32", + "vraddhn_s64", + "vraddhn_u16", + "vraddhn_u16", + "vraddhn_u32", + "vraddhn_u32", + "vraddhn_u64", + "vraddhn_u64", + "vrecpe_f16", + "vrecpeq_f16", + "vrecpe_f32", + "vrecpeq_f32", + "vrecpe_u32", + "vrecpeq_u32", + "vrecps_f16", + "vrecpsq_f16", + "vrecps_f32", + "vrecpsq_f32", + "vreinterpret_f32_f16", + "vreinterpret_f32_f16", + "vreinterpret_s8_f16", + "vreinterpret_s8_f16", + "vreinterpret_s16_f16", + "vreinterpret_s16_f16", + "vreinterpret_s32_f16", + "vreinterpret_s32_f16", + "vreinterpret_s64_f16", + "vreinterpret_s64_f16", + "vreinterpret_u8_f16", + "vreinterpret_u8_f16", + "vreinterpret_u16_f16", + "vreinterpret_u16_f16", + "vreinterpret_u32_f16", + "vreinterpret_u32_f16", + "vreinterpret_u64_f16", + "vreinterpret_u64_f16", + "vreinterpret_p8_f16", + "vreinterpret_p8_f16", + "vreinterpret_p16_f16", + "vreinterpret_p16_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_f32_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s8_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s16_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s32_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_s64_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u8_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u16_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u32_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_u64_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p8_f16", + "vreinterpretq_p16_f16", + "vreinterpretq_p16_f16", + "vreinterpret_f16_f32", + "vreinterpret_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpretq_f16_f32", + "vreinterpret_f16_s8", + "vreinterpret_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpretq_f16_s8", + "vreinterpret_f16_s16", + "vreinterpret_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpretq_f16_s16", + "vreinterpret_f16_s32", + "vreinterpret_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpretq_f16_s32", + "vreinterpret_f16_s64", + "vreinterpret_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpretq_f16_s64", + "vreinterpret_f16_u8", + "vreinterpret_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpretq_f16_u8", + "vreinterpret_f16_u16", + "vreinterpret_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpretq_f16_u16", + "vreinterpret_f16_u32", + "vreinterpret_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpretq_f16_u32", + "vreinterpret_f16_u64", + "vreinterpret_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpretq_f16_u64", + "vreinterpret_f16_p8", + "vreinterpret_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpretq_f16_p8", + "vreinterpret_f16_p16", + "vreinterpret_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p16", + "vreinterpretq_f16_p128", + "vreinterpretq_f16_p128", + "vreinterpret_p64_f16", + "vreinterpret_p64_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p128_f16", + "vreinterpretq_p64_f16", + "vreinterpretq_p64_f16", + "vreinterpret_f16_p64", + "vreinterpret_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f16_p64", + "vreinterpretq_f32_p128", + "vreinterpretq_f32_p128", + "vreinterpret_s8_f32", + "vreinterpret_s8_f32", + "vreinterpret_s16_f32", + "vreinterpret_s16_f32", + "vreinterpret_s32_f32", + "vreinterpret_s32_f32", + "vreinterpret_s64_f32", + "vreinterpret_s64_f32", + "vreinterpret_u8_f32", + "vreinterpret_u8_f32", + "vreinterpret_u16_f32", + "vreinterpret_u16_f32", + "vreinterpret_u32_f32", + "vreinterpret_u32_f32", + "vreinterpret_u64_f32", + "vreinterpret_u64_f32", + "vreinterpret_p8_f32", + "vreinterpret_p8_f32", + "vreinterpret_p16_f32", + "vreinterpret_p16_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_p128_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s8_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s16_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s32_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_s64_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u8_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u16_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u32_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_u64_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p8_f32", + "vreinterpretq_p16_f32", + "vreinterpretq_p16_f32", + "vreinterpret_f32_s8", + "vreinterpret_f32_s8", + "vreinterpret_s16_s8", + "vreinterpret_s16_s8", + "vreinterpret_s32_s8", + "vreinterpret_s32_s8", + "vreinterpret_s64_s8", + "vreinterpret_s64_s8", + "vreinterpret_u8_s8", + "vreinterpret_u8_s8", + "vreinterpret_u16_s8", + "vreinterpret_u16_s8", + "vreinterpret_u32_s8", + "vreinterpret_u32_s8", + "vreinterpret_u64_s8", + "vreinterpret_u64_s8", + "vreinterpret_p8_s8", + "vreinterpret_p8_s8", + "vreinterpret_p16_s8", + "vreinterpret_p16_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_f32_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s16_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s32_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_s64_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u8_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u16_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u32_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_u64_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p8_s8", + "vreinterpretq_p16_s8", + "vreinterpretq_p16_s8", + "vreinterpret_f32_s16", + "vreinterpret_f32_s16", + "vreinterpret_s8_s16", + "vreinterpret_s8_s16", + "vreinterpret_s32_s16", + "vreinterpret_s32_s16", + "vreinterpret_s64_s16", + "vreinterpret_s64_s16", + "vreinterpret_u8_s16", + "vreinterpret_u8_s16", + "vreinterpret_u16_s16", + "vreinterpret_u16_s16", + "vreinterpret_u32_s16", + "vreinterpret_u32_s16", + "vreinterpret_u64_s16", + "vreinterpret_u64_s16", + "vreinterpret_p8_s16", + "vreinterpret_p8_s16", + "vreinterpret_p16_s16", + "vreinterpret_p16_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_f32_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s8_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s32_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_s64_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u8_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u16_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u32_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_u64_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p8_s16", + "vreinterpretq_p16_s16", + "vreinterpretq_p16_s16", + "vreinterpret_f32_s32", + "vreinterpret_f32_s32", + "vreinterpret_s8_s32", + "vreinterpret_s8_s32", + "vreinterpret_s16_s32", + "vreinterpret_s16_s32", + "vreinterpret_s64_s32", + "vreinterpret_s64_s32", + "vreinterpret_u8_s32", + "vreinterpret_u8_s32", + "vreinterpret_u16_s32", + "vreinterpret_u16_s32", + "vreinterpret_u32_s32", + "vreinterpret_u32_s32", + "vreinterpret_u64_s32", + "vreinterpret_u64_s32", + "vreinterpret_p8_s32", + "vreinterpret_p8_s32", + "vreinterpret_p16_s32", + "vreinterpret_p16_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_f32_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s8_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s16_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_s64_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u8_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u16_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u32_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_u64_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p8_s32", + "vreinterpretq_p16_s32", + "vreinterpretq_p16_s32", + "vreinterpret_f32_s64", + "vreinterpret_f32_s64", + "vreinterpret_s8_s64", + "vreinterpret_s8_s64", + "vreinterpret_s16_s64", + "vreinterpret_s16_s64", + "vreinterpret_s32_s64", + "vreinterpret_s32_s64", + "vreinterpret_u8_s64", + "vreinterpret_u8_s64", + "vreinterpret_u16_s64", + "vreinterpret_u16_s64", + "vreinterpret_u32_s64", + "vreinterpret_u32_s64", + "vreinterpret_u64_s64", + "vreinterpret_p8_s64", + "vreinterpret_p8_s64", + "vreinterpret_p16_s64", + "vreinterpret_p16_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_f32_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s8_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s16_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_s32_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u8_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u16_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u32_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_u64_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p8_s64", + "vreinterpretq_p16_s64", + "vreinterpretq_p16_s64", + "vreinterpret_f32_u8", + "vreinterpret_f32_u8", + "vreinterpret_s8_u8", + "vreinterpret_s8_u8", + "vreinterpret_s16_u8", + "vreinterpret_s16_u8", + "vreinterpret_s32_u8", + "vreinterpret_s32_u8", + "vreinterpret_s64_u8", + "vreinterpret_s64_u8", + "vreinterpret_u16_u8", + "vreinterpret_u16_u8", + "vreinterpret_u32_u8", + "vreinterpret_u32_u8", + "vreinterpret_u64_u8", + "vreinterpret_u64_u8", + "vreinterpret_p8_u8", + "vreinterpret_p8_u8", + "vreinterpret_p16_u8", + "vreinterpret_p16_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_f32_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s8_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s16_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s32_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_s64_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u16_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u32_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_u64_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p8_u8", + "vreinterpretq_p16_u8", + "vreinterpretq_p16_u8", + "vreinterpret_f32_u16", + "vreinterpret_f32_u16", + "vreinterpret_s8_u16", + "vreinterpret_s8_u16", + "vreinterpret_s16_u16", + "vreinterpret_s16_u16", + "vreinterpret_s32_u16", + "vreinterpret_s32_u16", + "vreinterpret_s64_u16", + "vreinterpret_s64_u16", + "vreinterpret_u8_u16", + "vreinterpret_u8_u16", + "vreinterpret_u32_u16", + "vreinterpret_u32_u16", + "vreinterpret_u64_u16", + "vreinterpret_u64_u16", + "vreinterpret_p8_u16", + "vreinterpret_p8_u16", + "vreinterpret_p16_u16", + "vreinterpret_p16_u16", + "vreinterpretq_f32_u16", + "vreinterpretq_f32_u16", + "vreinterpretq_s8_u16", + "vreinterpretq_s8_u16", + "vreinterpretq_s16_u16", + "vreinterpretq_s16_u16", + "vreinterpretq_s32_u16", + "vreinterpretq_s32_u16", + "vreinterpretq_s64_u16", + "vreinterpretq_s64_u16", + "vreinterpretq_u8_u16", + "vreinterpretq_u8_u16", + "vreinterpretq_u32_u16", + "vreinterpretq_u32_u16", + "vreinterpretq_u64_u16", + "vreinterpretq_u64_u16", + "vreinterpretq_p8_u16", + "vreinterpretq_p8_u16", + "vreinterpretq_p16_u16", + "vreinterpretq_p16_u16", + "vreinterpret_f32_u32", + "vreinterpret_f32_u32", + "vreinterpret_s8_u32", + "vreinterpret_s8_u32", + "vreinterpret_s16_u32", + "vreinterpret_s16_u32", + "vreinterpret_s32_u32", + "vreinterpret_s32_u32", + "vreinterpret_s64_u32", + "vreinterpret_s64_u32", + "vreinterpret_u8_u32", + "vreinterpret_u8_u32", + "vreinterpret_u16_u32", + "vreinterpret_u16_u32", + "vreinterpret_u64_u32", + "vreinterpret_u64_u32", + "vreinterpret_p8_u32", + "vreinterpret_p8_u32", + "vreinterpret_p16_u32", + "vreinterpret_p16_u32", + "vreinterpretq_f32_u32", + "vreinterpretq_f32_u32", + "vreinterpretq_s8_u32", + "vreinterpretq_s8_u32", + "vreinterpretq_s16_u32", + "vreinterpretq_s16_u32", + "vreinterpretq_s32_u32", + "vreinterpretq_s32_u32", + "vreinterpretq_s64_u32", + "vreinterpretq_s64_u32", + "vreinterpretq_u8_u32", + "vreinterpretq_u8_u32", + "vreinterpretq_u16_u32", + "vreinterpretq_u16_u32", + "vreinterpretq_u64_u32", + "vreinterpretq_u64_u32", + "vreinterpretq_p8_u32", + "vreinterpretq_p8_u32", + "vreinterpretq_p16_u32", + "vreinterpretq_p16_u32", + "vreinterpret_f32_u64", + "vreinterpret_f32_u64", + "vreinterpret_s8_u64", + "vreinterpret_s8_u64", + "vreinterpret_s16_u64", + "vreinterpret_s16_u64", + "vreinterpret_s32_u64", + "vreinterpret_s32_u64", + "vreinterpret_s64_u64", + "vreinterpret_u8_u64", + "vreinterpret_u8_u64", + "vreinterpret_u16_u64", + "vreinterpret_u16_u64", + "vreinterpret_u32_u64", + "vreinterpret_u32_u64", + "vreinterpret_p8_u64", + "vreinterpret_p8_u64", + "vreinterpret_p16_u64", + "vreinterpret_p16_u64", + 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"vst4q_lane_u32", + "vst4_lane_p8", + "vst4_lane_p16", + "vst4q_lane_p16", + "vst4_p64", + "vst4_s64", + "vst4_s64", + "vst4_u64", + "vst4_u8", + "vst4q_u8", + "vst4_u16", + "vst4q_u16", + "vst4_u32", + "vst4q_u32", + "vst4_p8", + "vst4q_p8", + "vst4_p16", + "vst4q_p16", + "vsub_f16", + "vsubq_f16", + "vsub_s64", + "vsubq_s64", + "vsub_u64", + "vsubq_u64", + "vsubhn_high_s16", + "vsubhn_high_s32", + "vsubhn_high_s64", + "vsubhn_high_u16", + "vsubhn_high_u32", + "vsubhn_high_u64", + "vsubhn_s16", + "vsubhn_s32", + "vsubhn_s64", + "vsubhn_u16", + "vsubhn_u32", + "vsubhn_u64", + "vsubl_s8", + "vsubl_s16", + "vsubl_s32", + "vsubl_u8", + "vsubl_u16", + "vsubl_u32", + "vsubw_s8", + "vsubw_s16", + "vsubw_s32", + "vsubw_u8", + "vsubw_u16", + "vsubw_u32", + "vsudot_lane_s32", + "vsudot_lane_s32", + "vsudotq_lane_s32", + "vsudotq_lane_s32", + "vsudot_laneq_s32", + "vsudotq_laneq_s32", + "vtrn_f16", + "vtrnq_f16", + "vtrn_f32", + "vtrn_s32", + "vtrn_u32", + "vtrnq_f32", + "vtrn_s8", + "vtrnq_s8", + "vtrn_s16", + "vtrnq_s16", + "vtrnq_s32", + "vtrn_u8", + "vtrnq_u8", + "vtrn_u16", + "vtrnq_u16", + "vtrnq_u32", + "vtrn_p8", + "vtrnq_p8", + "vtrn_p16", + "vtrnq_p16", + "vtst_s8", + "vtstq_s8", + "vtst_s16", + "vtstq_s16", + "vtst_s32", + "vtstq_s32", + "vtst_p8", + "vtstq_p8", + "vtst_p16", + "vtstq_p16", + "vtst_u8", + "vtstq_u8", + "vtst_u16", + "vtstq_u16", + "vtst_u32", + "vtstq_u32", + "vusdot_lane_s32", + "vusdot_lane_s32", + "vusdotq_lane_s32", + "vusdotq_lane_s32", + "vusdot_laneq_s32", + "vusdot_laneq_s32", + "vusdotq_laneq_s32", + "vusdotq_laneq_s32", + "vusdot_s32", + "vusdotq_s32", + "vusmmlaq_s32", + "vuzp_f16", + "vuzpq_f16", + "vuzp_f32", + "vuzp_s32", + "vuzp_u32", + "vuzpq_f32", + "vuzp_s8", + "vuzpq_s8", + "vuzp_s16", + "vuzpq_s16", + "vuzpq_s32", + "vuzp_u8", + "vuzpq_u8", + "vuzp_u16", + "vuzpq_u16", + "vuzpq_u32", + "vuzp_p8", + "vuzpq_p8", + "vuzp_p16", + "vuzpq_p16", + "vzip_f16", + "vzipq_f16", + "vzip_f32", + "vzip_s32", + "vzip_u32", + "vzip_s8", + "vzip_s16", + "vzip_u8", + "vzip_u16", + "vzip_p8", + "vzip_p16", + "vzipq_f32", + "vzipq_s8", + "vzipq_s16", + "vzipq_s32", + "vzipq_u8", + "vzipq_u16", + "vzipq_u32", + "vzipq_p8", + "vzipq_p16", + "__rndr", + "__rndrrs", +]; diff --git a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs index 7fc47be42e14..024a873de16e 100644 --- a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs +++ b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs @@ -214,7 +214,7 @@ fn verify_all_signatures() { "_m_prefetchrs", // CMPXCHG "cmpxchg16b", - // Undefined + // Undefined, "_mm_undefined_ps", "_mm_undefined_pd", "_mm_undefined_si128", @@ -250,9 +250,6 @@ fn verify_all_signatures() { "_mm_cvt_ss2si", "_mm_cvtt_ss2si", "_mm_cvt_si2ss", - "_mm_set_ps1", - "_mm_load_ps1", - "_mm_store_ps1", "_mm_bslli_si128", "_mm_bsrli_si128", "_bextr2_u32", diff --git a/library/stdarch/examples/gaussian.rs b/library/stdarch/examples/gaussian.rs index dea16f797aca..a310c24def9a 100644 --- a/library/stdarch/examples/gaussian.rs +++ b/library/stdarch/examples/gaussian.rs @@ -95,30 +95,30 @@ unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *m let below = *inp2.add(i); // Widen above + below to 16-bit using HvxVectorPair - // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair - let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below); + // Q6_Wh_vadd_VubVub: adds two u8 vectors, producing u16 results in a pair + let above_plus_below: HvxVectorPair = Q6_Wh_vadd_VubVub(above, below); // Widen center * 2 (add center to itself) - let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center); + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(center, center); // Add them: (above + below) + (center * 2) = above + 2*center + below - let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2); + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(above_plus_below, center_x2); // Extract high and low vectors from the pair (each contains u16 values) - let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16 - let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16 + let sum_lo = Q6_V_lo_W(sum); // Lower 64 elements as i16 + let sum_hi = Q6_V_hi_W(sum); // Upper 64 elements as i16 // Arithmetic right shift by 2 (divide by 4) with rounding // Add 2 for rounding before shift: (sum + 2) >> 2 - let two = q6_vh_vsplat_r(2); - let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); - let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); - let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); - let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); // Pack back to u8 with saturation: takes hi and lo halfword vectors, // saturates to u8, and interleaves them back to original order - let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); *outp.add(i) = result; } @@ -142,44 +142,44 @@ unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) { let outp = dst as *mut HvxVector; let n_chunks = width / VLEN; - let mut prev = q6_v_vzero(); + let mut prev = Q6_V_vzero(); for i in 0..n_chunks { let curr = *inp.add(i); let next = if i + 1 < n_chunks { *inp.add(i + 1) } else { - q6_v_vzero() + Q6_V_vzero() }; // Left neighbor (x-1): shift curr right by 1 byte, filling from prev - let left = q6_v_vlalign_vvr(curr, prev, 1); + let left = Q6_V_vlalign_VVR(curr, prev, 1); // Right neighbor (x+1): shift curr left by 1 byte, filling from next - let right = q6_v_valign_vvr(next, curr, 1); + let right = Q6_V_valign_VVR(next, curr, 1); // Widen left + right to 16-bit - let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right); + let left_plus_right: HvxVectorPair = Q6_Wh_vadd_VubVub(left, right); // Widen center * 2 - let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr); + let center_x2: HvxVectorPair = Q6_Wh_vadd_VubVub(curr, curr); // Add: left + 2*center + right - let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2); + let sum: HvxVectorPair = Q6_Wh_vadd_WhWh(left_plus_right, center_x2); // Extract high and low vectors - let sum_lo = q6_v_lo_w(sum); - let sum_hi = q6_v_hi_w(sum); + let sum_lo = Q6_V_lo_W(sum); + let sum_hi = Q6_V_hi_W(sum); // Arithmetic right shift by 2 with rounding - let two = q6_vh_vsplat_r(2); - let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); - let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); - let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); - let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + let two = Q6_Vh_vsplat_R(2); + let sum_lo_rounded = Q6_Vh_vadd_VhVh(sum_lo, two); + let sum_hi_rounded = Q6_Vh_vadd_VhVh(sum_hi, two); + let shifted_lo = Q6_Vh_vasr_VhVh(sum_lo_rounded, two); + let shifted_hi = Q6_Vh_vasr_VhVh(sum_hi_rounded, two); // Pack back to u8 with saturation - let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + let result = Q6_Vub_vsat_VhVh(shifted_hi, shifted_lo); *outp.add(i) = result; diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index bce85d19a10f..3a3b962a4873 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -224,21 +224,25 @@ ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s16]", "arguments": [ - "float16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -246,26 +250,165075 @@ ], "instructions": [ [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": 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+ "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f16", + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_x", "arguments": [ - "float16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -274,25 +165327,33 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f32", + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_z", "arguments": [ - "float32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -300,26 +165361,31 @@ ], "instructions": [ [ + "MOVPRFX", "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f32", + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_m", "arguments": [ - "float32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -328,25 +165394,33 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f64", + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_x", "arguments": [ - "float64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -355,6 +165429,37649 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" + ], + 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"arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" ] ] }, @@ -4404,7 +207121,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -4473,7 +207190,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -4519,7 +207236,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vm.4S" } }, "Architectures": [ @@ -5179,6 +207896,276 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f16", + "arguments": [ + "float16x4_t vn", + "float16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f32", + "arguments": [ + "float32x2_t vn", + "float32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f16", + "arguments": [ + "float16x8_t vn", + "float16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f32", + "arguments": [ + "float32x4_t vn", + "float32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f64", + "arguments": [ + "float64x2_t vn", + "float64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f16", + "arguments": [ + "float16x4_t vn", + "float16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f32", + "arguments": [ + "float32x2_t vn", + "float32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f16", + "arguments": [ + "float16x8_t vn", + "float16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f32", + "arguments": [ + "float32x4_t vn", + "float32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f64", + "arguments": [ + "float64x2_t vn", + "float64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vand_s16", @@ -5658,8 +208645,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5685,8 +208676,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5712,8 +208707,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5739,8 +208738,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5766,8 +208769,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5793,8 +208800,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5820,8 +208831,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5847,8 +208862,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -7253,7 +210272,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4H " + "register": "Vn.4H" }, "b": { "register": "Vm.4H" @@ -7281,7 +210300,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S " + "register": "Vn.2S" }, "b": { "register": "Vm.2S" @@ -7309,7 +210328,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4H " + "register": "Vn.4H" }, "b": { "register": "Vm.4H" @@ -7337,7 +210356,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S " + "register": "Vn.2S" }, "b": { "register": "Vm.2S" @@ -7365,7 +210384,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H " + "register": "Vn.8H" }, "b": { "register": "Vm.8H" @@ -7393,7 +210412,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S " + "register": "Vn.4S" }, "b": { "register": "Vm.4S" @@ -7421,7 +210440,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2D " + "register": "Vn.2D" }, "b": { "register": "Vm.2D" @@ -7448,7 +210467,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H " + "register": "Vn.8H" }, "b": { "register": "Vm.8H" @@ -7476,7 +210495,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S " + "register": "Vn.4S" }, "b": { "register": "Vm.4S" @@ -7504,7 +210523,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2D " + "register": "Vn.2D" }, "b": { "register": "Vm.2D" @@ -15417,8 +218436,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15445,8 +218468,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15474,8 +218501,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15507,8 +218538,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15540,8 +218575,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15573,8 +218612,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15590,7 +218633,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15606,8 +218649,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15634,8 +218681,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15663,8 +218714,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15696,8 +218751,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15729,8 +218788,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15762,8 +218825,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15779,7 +218846,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15795,8 +218862,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15823,8 +218894,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15852,8 +218927,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15885,8 +218964,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15918,8 +219001,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15951,8 +219038,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15968,7 +219059,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15984,8 +219075,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -16012,8 +219107,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -16041,8 +219140,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16074,8 +219177,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16107,8 +219214,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16140,8 +219251,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16157,7 +219272,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -16173,8 +219288,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16201,8 +219320,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16229,8 +219352,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16257,8 +219384,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16290,8 +219421,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16323,8 +219458,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16356,8 +219495,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16388,8 +219531,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16416,8 +219563,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16444,8 +219595,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16472,8 +219627,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16505,8 +219664,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16538,8 +219701,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16571,8 +219738,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16603,8 +219774,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16631,8 +219806,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16659,8 +219838,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16687,8 +219870,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16720,8 +219907,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16753,8 +219944,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16786,8 +219981,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16818,8 +220017,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16846,8 +220049,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16874,8 +220081,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16902,8 +220113,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16935,8 +220150,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16968,8 +220187,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -17001,8 +220224,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -20921,7 +224148,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -20991,7 +224217,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -21933,7 +225158,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22003,7 +225227,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22261,7 +225484,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22331,7 +225553,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22777,7 +225998,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22847,7 +226067,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -23293,7 +226512,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -23363,7 +226581,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -28161,8 +231378,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28188,8 +231409,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28215,8 +231440,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28242,8 +231471,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28269,8 +231502,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28296,8 +231533,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28323,8 +231564,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28350,8 +231595,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -30097,7 +233346,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -30680,7 +233929,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -30846,8 +234095,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -30875,8 +234128,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30908,8 +234165,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30941,8 +234202,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -30974,8 +234239,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31006,8 +234275,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31034,8 +234307,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31063,8 +234340,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31096,8 +234377,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31129,8 +234414,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31162,8 +234451,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31194,8 +234487,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31222,8 +234519,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31251,8 +234552,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31284,8 +234589,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31317,8 +234626,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31350,8 +234663,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31382,8 +234699,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31410,8 +234731,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31439,8 +234764,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31472,8 +234801,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31505,8 +234838,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31538,8 +234875,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31570,8 +234911,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31911,7 +235256,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -32492,7 +235837,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -34868,230 +238213,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x1_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x1_t src", - "const int lane" - ], - "return_type": { - "value": "int64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x2_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x2_t src", - "const int lane" - ], - "return_type": { - "value": "int64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x1_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x2_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_f64", - "arguments": [ - "float64_t const * ptr", - "float64x2_t src", - "const int lane" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f16", @@ -39947,7 +243068,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -39981,7 +243105,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40015,7 +243142,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40047,7 +243177,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40081,7 +243214,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40113,7 +243249,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40147,7 +243286,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40181,7 +243323,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40215,7 +243360,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40247,7 +243395,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40281,7 +243432,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40315,7 +243469,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40349,7 +243506,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40381,7 +243541,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -41104,7 +244267,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41138,7 +244304,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41172,7 +244341,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41204,7 +244376,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41238,7 +244413,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41270,7 +244448,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41302,7 +244483,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41336,7 +244520,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41370,7 +244557,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41402,7 +244592,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41434,7 +244627,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41468,7 +244664,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41502,7 +244701,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41534,7 +244736,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -42255,7 +245460,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42289,7 +245500,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42323,7 +245540,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42355,7 +245578,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42389,7 +245618,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42421,7 +245656,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42455,7 +245696,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42489,7 +245736,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42523,7 +245776,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42555,7 +245814,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42589,7 +245854,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42623,7 +245894,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42657,7 +245934,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42689,7 +245972,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -43412,7 +246701,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43446,7 +246741,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43480,7 +246781,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43512,7 +246819,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43546,7 +246859,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43578,7 +246897,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43610,7 +246935,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43644,7 +246975,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43678,7 +247015,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43710,7 +247053,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43742,7 +247091,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43776,7 +247131,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43810,7 +247171,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43842,7 +247209,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -44563,7 +247936,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44597,7 +247979,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44631,7 +248022,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44663,7 +248063,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44697,7 +248106,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44729,7 +248147,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44763,7 +248190,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44797,7 +248233,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44831,7 +248276,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44863,7 +248317,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44897,7 +248360,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44931,7 +248403,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44965,7 +248446,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44997,7 +248487,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -45720,7 +249219,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45754,7 +249262,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -45788,7 +249305,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -45820,7 +249346,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45854,7 +249389,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -45886,7 +249430,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -45918,7 +249471,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45952,7 +249514,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -45986,7 +249557,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -46018,7 +249598,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -46050,7 +249639,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -46084,7 +249682,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -46118,7 +249725,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -46150,7 +249766,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -46432,6 +250057,262 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x1_t src", + "const int lane" + ], + "return_type": { + "value": "float64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x1_t src", + "const int lane" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x2_t src", + "const int lane" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x2_t src", + "const int lane" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vldrq_p128", @@ -46456,6 +250337,1374 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_f16", + "arguments": [ + "float16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p16", + "arguments": [ + "poly16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p8", + "arguments": [ + "poly8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s16", + "arguments": [ + "int16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s8", + "arguments": [ + "int8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u16", + "arguments": [ + "uint16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u8", + "arguments": [ + "uint8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_f16", + "arguments": [ + "float16x4_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": 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+ "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_u8", + "arguments": [ + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmax_f16", @@ -47388,7 +252637,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -47457,7 +252706,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48631,7 +253880,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48700,7 +253949,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48971,7 +254220,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49002,7 +254251,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49019,13 +254268,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -49034,7 +254280,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49203,20 +254449,17 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49393,7 +254636,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -50980,7 +256223,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51011,7 +256254,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51028,13 +256271,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51043,7 +256283,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51212,20 +256452,17 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51402,7 +256639,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51765,7 +257002,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51796,7 +257033,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51813,13 +257050,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51828,7 +257062,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51997,20 +257231,17 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -52187,7 +257418,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53774,7 +259005,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53805,7 +259036,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53822,13 +259053,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -53837,7 +259065,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -54006,20 +259234,17 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -54196,7 +259421,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -75953,8 +281178,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -75980,8 +281208,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76007,8 +281238,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76034,8 +281268,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76061,8 +281298,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76088,8 +281328,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76115,8 +281358,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76142,8 +281391,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76169,8 +281424,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76196,8 +281457,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76223,8 +281490,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76250,8 +281523,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76277,8 +281556,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76304,8 +281592,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76331,8 +281628,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76358,8 +281664,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76385,8 +281700,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76412,8 +281736,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76629,8 +281962,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76660,8 +281996,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76691,8 +282030,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76722,8 +282064,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76753,8 +282098,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76784,8 +282132,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76815,8 +282166,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76846,8 +282203,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76877,8 +282240,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76908,8 +282277,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76939,8 +282314,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76970,8 +282351,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -77001,8 +282388,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77032,8 +282428,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77063,8 +282468,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77094,8 +282508,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77125,8 +282548,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77156,8 +282588,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77543,7 +282984,9 @@ "a": { "register": "Vn.2D" }, - "b": {} + "b": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -93507,6 +298950,141 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f16", + "arguments": [ + "float16x4_t vn", + "int16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f32", + "arguments": [ + "float32x2_t vn", + "int32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f16", + "arguments": [ + "float16x8_t vn", + "int16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f32", + "arguments": [ + "float32x4_t vn", + "int32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f64", + "arguments": [ + "float64x2_t vn", + "int64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vset_lane_f16", @@ -94769,7 +300347,9 @@ "value": "uint64x2_t" }, "Arguments_Preparation": { - "hash_ab": {}, + "hash_ab": { + "register": "Vm.2D" + }, "hash_c_": { "register": "Qn" }, @@ -94804,7 +300384,9 @@ "hash_gf": { "register": "Qn" }, - "kwh_kwh2": {} + "kwh_kwh2": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -94860,7 +300442,9 @@ "w14_15": { "register": "Vn.2D" }, - "w9_10": {} + "w9_10": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -98006,8 +303590,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98033,8 +303621,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98060,8 +303652,12 @@ "a": { "register": "Vn.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.4S" + }, + "c": { + "register": "Va.4S" + } }, "Architectures": [ "A64" @@ -98088,8 +303684,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98120,8 +303720,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98152,8 +303756,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98184,8 +303792,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98214,7 +303826,9 @@ "a": { "register": "Vn.4S" }, - "b": {} + "b": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98239,7 +303853,9 @@ "a": { "register": "Vd.4S" }, - "b": {} + "b": { + "register": "Vn.4S" + } }, "Architectures": [ "A64" @@ -100197,7 +305813,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -100226,7 +305845,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -100255,7 +305880,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -100313,7 +305947,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -100342,7 +305979,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -100371,7 +306014,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -100427,7 +306079,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -100454,7 +306109,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -100481,7 +306142,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -100967,6 +306637,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1_mf8_x4", + "arguments": [ + "int8_t * ptr", + "int8x8x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1_p16", @@ -101010,7 +306716,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101039,7 +306748,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101068,7 +306783,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101125,7 +306849,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -101153,7 +306880,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -101181,7 +306914,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -101238,7 +306980,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -101267,7 +307012,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -101296,7 +307047,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -101354,7 +307114,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101383,7 +307146,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101412,7 +307181,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101470,7 +307248,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -101499,7 +307280,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -101528,7 +307315,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -101586,7 +307382,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -101615,7 +307414,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -101644,7 +307449,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -101702,7 +307516,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -101731,7 +307548,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -101760,7 +307583,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -101818,7 +307650,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101847,7 +307682,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101876,7 +307717,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101934,7 +307784,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -101963,7 +307816,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -101992,7 +307851,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -102050,7 +307918,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -102079,7 +307950,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -102108,7 +307985,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -102166,7 +308052,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -102195,7 +308084,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -102224,7 +308119,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -102282,7 +308186,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -102311,7 +308218,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -102340,7 +308253,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -102398,7 +308320,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -102427,7 +308352,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -102456,7 +308387,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -102512,7 +308452,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -102539,7 +308482,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -102566,7 +308515,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103052,6 +309010,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_mf8_x4", + "arguments": [ + "int8_t * ptr", + "int8x16x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1q_p16", @@ -103095,7 +309089,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103124,7 +309121,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103153,7 +309156,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -103210,7 +309222,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -103238,7 +309253,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -103267,7 +309288,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103324,7 +309354,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -103353,7 +309386,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -103382,7 +309421,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -103440,7 +309488,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103469,7 +309520,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103498,7 +309555,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -103556,7 +309622,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -103585,7 +309654,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -103614,7 +309689,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -103672,7 +309756,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -103701,7 +309788,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -103730,7 +309823,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103788,7 +309890,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -103817,7 +309922,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -103846,7 +309957,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -103904,7 +310024,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103933,7 +310056,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103962,7 +310091,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -104020,7 +310158,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -104049,7 +310190,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -104078,7 +310225,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -104136,7 +310292,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -104165,7 +310324,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -104194,7 +310359,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -104252,7 +310426,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -104281,7 +310458,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -104310,7 +310493,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -104339,7 +310531,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104368,7 +310563,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104397,7 +310595,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104429,7 +310630,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104463,7 +310667,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104497,7 +310704,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104529,7 +310739,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104563,7 +310776,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104595,7 +310811,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104629,7 +310848,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104663,7 +310885,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104697,7 +310922,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104729,7 +310957,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104763,7 +310994,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104797,7 +311031,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104831,7 +311068,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104863,7 +311103,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104892,7 +311135,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104921,7 +311167,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104949,7 +311198,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104978,7 +311230,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -105007,7 +311262,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -105036,7 +311294,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -105065,7 +311326,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -105094,7 +311358,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -105123,7 +311390,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -105152,7 +311422,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -105181,7 +311454,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -105210,7 +311486,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105239,7 +311518,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105268,7 +311550,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105300,7 +311585,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105334,7 +311622,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105363,12 +311654,15 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 2 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105400,7 +311694,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105434,7 +311731,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105466,7 +311766,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105498,7 +311801,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105532,7 +311838,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105566,7 +311875,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105598,7 +311910,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105630,7 +311945,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105664,7 +311982,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105698,7 +312019,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105730,7 +312054,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105757,7 +312084,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105786,7 +312116,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105813,7 +312146,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105842,7 +312178,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105871,7 +312210,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105900,7 +312242,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105927,7 +312272,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105956,7 +312304,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105985,7 +312336,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -106014,7 +312368,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -106041,7 +312398,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -106070,7 +312430,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106099,7 +312465,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106128,7 +312500,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106160,7 +312538,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106194,7 +312578,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106228,7 +312618,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106260,7 +312656,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106294,7 +312696,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106326,7 +312734,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106360,7 +312774,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106394,7 +312814,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106428,7 +312854,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106460,7 +312892,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106494,7 +312932,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106528,7 +312972,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106562,7 +313012,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106594,7 +313050,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106623,7 +313085,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106652,7 +313120,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106680,7 +313154,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106709,7 +313189,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106738,7 +313224,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106767,7 +313259,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106796,7 +313294,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106825,7 +313329,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106854,7 +313364,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106883,7 +313399,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106912,7 +313434,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106941,7 +313469,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -106970,7 +313504,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -106999,7 +313539,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107031,7 +313577,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107065,7 +313617,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107099,7 +313657,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107131,7 +313695,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107165,7 +313735,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107197,7 +313773,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107231,7 +313813,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107265,7 +313853,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107299,7 +313893,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107331,7 +313931,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107365,7 +313971,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107399,7 +314011,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107433,7 +314051,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107465,7 +314089,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107494,7 +314124,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107523,7 +314159,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107550,7 +314192,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107579,7 +314227,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107608,7 +314262,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107637,7 +314297,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107664,7 +314330,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107693,7 +314365,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107722,7 +314400,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107751,7 +314435,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107778,7 +314468,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107807,7 +314503,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -107836,7 +314541,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -107865,7 +314579,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -107897,7 +314620,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -107931,7 +314663,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -107965,7 +314706,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -107997,7 +314747,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108031,7 +314790,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108063,7 +314831,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108097,7 +314874,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108131,7 +314917,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108165,7 +314960,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108197,7 +315001,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108231,7 +315044,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108265,7 +315087,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108299,7 +315130,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108331,7 +315171,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108360,7 +315209,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108389,7 +315247,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108417,7 +315284,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108446,7 +315322,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108475,7 +315360,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108504,7 +315398,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108533,7 +315436,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108562,7 +315474,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108591,7 +315512,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108620,7 +315550,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108649,7 +315588,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108678,7 +315626,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108707,7 +315664,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -108736,7 +315702,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108768,7 +315743,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108802,7 +315786,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -108836,7 +315829,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108868,7 +315870,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108902,7 +315913,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108934,7 +315954,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -108966,7 +315995,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109000,7 +316038,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109034,7 +316081,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109066,7 +316122,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109098,7 +316163,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109132,7 +316206,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109166,7 +316249,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109198,7 +316290,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109225,7 +316326,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109254,7 +316364,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109281,7 +316400,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109310,7 +316438,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109339,7 +316476,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109368,7 +316514,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109395,7 +316550,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109424,7 +316588,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109453,7 +316626,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109482,7 +316664,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109509,7 +316700,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109526,38 +316726,106 @@ }, { "SIMD_ISA": "Neon", - "name": "vstrq_p128", + "name": "vstl1_lane_f64", "arguments": [ - "poly128_t * ptr", - "poly128_t val" + "float64_t * ptr", + "float64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Qt" + "register": "Vt.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "STR" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_f64", + "name": "vstl1_lane_p64", "arguments": [ - "float64_t * ptr", - "float64x1_t val", + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x1_t val", "const int lane" ], "return_type": { @@ -109616,38 +316884,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vstl1_lane_p64", - "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vstl1q_lane_p64", @@ -109682,10 +316918,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_u64", + "name": "vstl1q_lane_s64", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", + "int64_t * ptr", + "int64x2_t val", "const int lane" ], "return_type": { @@ -109694,13 +316930,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.1D" + "register": "Vt.2D" } }, "Architectures": [ @@ -109746,65 +316982,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_s64", + "name": "vstrq_p128", "arguments": [ - "int64_t * ptr", - "int64x1_t val", - "const int lane" + "poly128_t * ptr", + "poly128_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.1D" + "register": "Qt" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "STL1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vstl1q_lane_s64", - "arguments": [ - "int64_t * ptr", - "int64x2_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" + "STR" ] ] }, @@ -111655,7 +318855,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -111711,10 +318910,12 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111738,10 +318939,12 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111765,10 +318968,12 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111792,10 +318997,12 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111819,10 +319026,12 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111846,10 +319055,12 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111873,10 +319084,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111900,10 +319116,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111927,10 +319148,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111954,10 +319180,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111981,10 +319212,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112008,10 +319244,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112036,11 +319277,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112068,11 +319313,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112100,11 +319349,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112132,11 +319385,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112161,11 +319418,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112190,11 +319451,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112219,11 +319484,18 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112251,11 +319523,18 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112283,11 +319562,18 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112315,11 +319601,18 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112344,11 +319637,18 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112373,11 +319673,18 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -115435,6 +322742,7 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -117386,7 +324694,9 @@ "a": { "register": "Vn.2D" }, - "b": {}, + "b": { + "register": "Vm.2D" + }, "imm6": { "minimum": 0, "maximum": 63 @@ -119297,1746 +326607,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vamin_f16", - "arguments": [ - "float16x4_t a", - "float16x4_t b" - ], - "return_type": { - "value": "float16x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - 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"Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "__jcvt", diff --git a/library/stdarch/rust-version b/library/stdarch/rust-version index db9492636f6a..a8efb5c477c1 100644 --- a/library/stdarch/rust-version +++ b/library/stdarch/rust-version @@ -1 +1 @@ -eda4fc7733ee89e484d7120cafbd80dcb2fce66e +e4fdb554ad2c0270473181438e338c42b5b30b0c diff --git a/src/bootstrap/bootstrap.py b/src/bootstrap/bootstrap.py index b893bb3f5821..ad256c2e97be 100644 --- a/src/bootstrap/bootstrap.py +++ b/src/bootstrap/bootstrap.py @@ -49,7 +49,7 @@ def eprint(*args, **kwargs): print(*args, **kwargs) -def get(base, url, path, checksums, verbose=False): +def get(base, url, path, checksums, verbose=0): with tempfile.NamedTemporaryFile(delete=False) as temp_file: temp_path = temp_file.name @@ -66,11 +66,11 @@ def get(base, url, path, checksums, verbose=False): sha256 = checksums[url] if os.path.exists(path): if verify(path, sha256, False): - if verbose: + if verbose > 0: eprint("using already-download file", path) return else: - if verbose: + if verbose > 0: eprint( "ignoring already-download file", path, @@ -80,12 +80,12 @@ def get(base, url, path, checksums, verbose=False): download(temp_path, "{}/{}".format(base, url), True, verbose) if not verify(temp_path, sha256, verbose): raise RuntimeError("failed verification") - if verbose: + if verbose > 0: eprint("moving {} to {}".format(temp_path, path)) shutil.move(temp_path, path) finally: if os.path.isfile(temp_path): - if verbose: + if verbose > 0: eprint("removing", temp_path) os.unlink(temp_path) @@ -113,11 +113,11 @@ def _download(path, url, probably_big, verbose, exception): # If an error occurs: # - If we are on win32 fallback to powershell # - Otherwise raise the error if appropriate - if probably_big or verbose: + if probably_big or verbose > 0: eprint("downloading {}".format(url)) try: - if (probably_big or verbose) and "GITHUB_ACTIONS" not in os.environ: + if (probably_big or verbose > 0) and "GITHUB_ACTIONS" not in os.environ: option = "--progress-bar" else: option = "--silent" @@ -180,7 +180,7 @@ def _download(path, url, probably_big, verbose, exception): def verify(path, expected, verbose): """Check if the sha256 sum of the given path is valid""" - if verbose: + if verbose > 0: eprint("verifying", path) with open(path, "rb") as source: found = hashlib.sha256(source.read()).hexdigest() @@ -194,7 +194,7 @@ def verify(path, expected, verbose): return verified -def unpack(tarball, tarball_suffix, dst, verbose=False, match=None): +def unpack(tarball, tarball_suffix, dst, verbose=0, match=None): """Unpack the given tarball file""" eprint("extracting", tarball) fname = os.path.basename(tarball).replace(tarball_suffix, "") @@ -208,7 +208,7 @@ def unpack(tarball, tarball_suffix, dst, verbose=False, match=None): name = name[len(match) + 1 :] dst_path = os.path.join(dst, name) - if verbose: + if verbose > 0: eprint(" extracting", member) tar.extract(member, dst) src_path = os.path.join(dst, member) @@ -218,9 +218,9 @@ def unpack(tarball, tarball_suffix, dst, verbose=False, match=None): shutil.rmtree(os.path.join(dst, fname)) -def run(args, verbose=False, exception=False, is_bootstrap=False, **kwargs): +def run(args, verbose=0, exception=False, is_bootstrap=False, **kwargs): """Run a child program in a new process""" - if verbose: + if verbose > 0: eprint("running: " + " ".join(args)) sys.stdout.flush() # Ensure that the .exe is used on Windows just in case a Linux ELF has been @@ -233,7 +233,7 @@ def run(args, verbose=False, exception=False, is_bootstrap=False, **kwargs): code = ret.wait() if code != 0: err = "failed to run: " + " ".join(args) - if verbose or exception: + if verbose > 0 or exception: raise RuntimeError(err) # For most failures, we definitely do want to print this error, or the user will have no # idea what went wrong. But when we've successfully built bootstrap and it failed, it will @@ -293,13 +293,13 @@ def default_build_triple(verbose): version = version.decode(default_encoding) host = next(x for x in version.split("\n") if x.startswith("host: ")) triple = host.split("host: ")[1] - if verbose: + if verbose > 0: eprint( "detected default triple {} from pre-installed rustc".format(triple) ) return triple except Exception as e: - if verbose: + if verbose > 0: eprint("pre-installed rustc not detected: {}".format(e)) eprint("falling back to auto-detect") @@ -699,7 +699,7 @@ class RustBuild(object): # Unpack the tarballs in parallel. # In Python 2.7, Pool cannot be used as a context manager. pool_size = min(len(tarballs_download_info), get_cpus()) - if self.verbose: + if self.verbose > 0: print( "Choosing a pool size of", pool_size, @@ -1126,6 +1126,8 @@ class RustBuild(object): ] # verbose cargo output is very noisy, so only enable it with -vv args.extend("--verbose" for _ in range(self.verbose - 1)) + if self.verbose < 0: + args.append("--quiet") target_features = [] if self.get_toml("crt-static", build_section) == "true": @@ -1262,7 +1264,7 @@ def parse_args(args): # Pass allow_abbrev=False to remove support for inexact matches (e.g., # `--json` turning on `--json-output`). The argument list here is partial, - # most flags are matched in the Rust bootstrap code. This prevents the the + # most flags are matched in the Rust bootstrap code. This prevents the # default ambiguity checks in argparse from functioning correctly. parser = argparse.ArgumentParser(add_help=False, allow_abbrev=False) parser.add_argument("-h", "--help", action="store_true") @@ -1275,7 +1277,12 @@ def parse_args(args): parser.add_argument( "--warnings", choices=["deny", "warn", "default"], default="default" ) - parser.add_argument("-v", "--verbose", action="count", default=0) + group = parser.add_mutually_exclusive_group() + group.add_argument("-v", "--verbose", action="count", default=0) + # Note that we're storing the `--quiet` value in `verbose`. That way we don't need to thread + # `self.quiet` throughout the code. That could be error prone, which could let some output + # through that should have been suppressed. + group.add_argument("-q", "--quiet", action="store_const", const=-1, dest="verbose") return parser.parse_known_args(args)[0] diff --git a/src/bootstrap/src/core/build_steps/dist.rs b/src/bootstrap/src/core/build_steps/dist.rs index 28a7afd6c61a..222b98207328 100644 --- a/src/bootstrap/src/core/build_steps/dist.rs +++ b/src/bootstrap/src/core/build_steps/dist.rs @@ -636,9 +636,9 @@ fn prepare_image(builder: &Builder<'_>, target_compiler: Compiler, image: &Path) let page_src = file_entry.path(); let page_dst = man_dst.join(file_entry.file_name()); let src_text = t!(std::fs::read_to_string(&page_src)); - let new_text = src_text.replace("", &builder.version); + let version = builder.rust_info().version(builder.build, &builder.version); + let new_text = src_text.replace("", &version); t!(std::fs::write(&page_dst, &new_text)); - t!(fs::copy(&page_src, &page_dst)); } // Debugger scripts diff --git a/src/bootstrap/src/core/build_steps/doc.rs b/src/bootstrap/src/core/build_steps/doc.rs index a918ae929d2e..c67981deda33 100644 --- a/src/bootstrap/src/core/build_steps/doc.rs +++ b/src/bootstrap/src/core/build_steps/doc.rs @@ -932,13 +932,7 @@ fn run(self, builder: &Builder<'_>) { // see https://github.com/rust-lang/rust/pull/122066#issuecomment-1983049222 // If there is any bug, please comment out the next line. cargo.rustdocflag("--generate-link-to-definition"); - // FIXME: Currently, `--generate-macro-expansion` option is buggy in `beta` rustdoc. To - // allow CI to pass, we only enable the option in stage 2 and higher. - // cfg(bootstrap) - // ^ Adding this so it's not forgotten when the new release is done. - if builder.top_stage > 1 { - cargo.rustdocflag("--generate-macro-expansion"); - } + cargo.rustdocflag("--generate-macro-expansion"); compile::rustc_cargo(builder, &mut cargo, target, &build_compiler, &self.crates); cargo.arg("-Zskip-rustdoc-fingerprint"); diff --git a/src/bootstrap/src/core/build_steps/llvm.rs b/src/bootstrap/src/core/build_steps/llvm.rs index a2cf801afa11..087a395a067f 100644 --- a/src/bootstrap/src/core/build_steps/llvm.rs +++ b/src/bootstrap/src/core/build_steps/llvm.rs @@ -651,6 +651,18 @@ fn configure_cmake( // LLVM and LLD builds can produce a lot of those and hit CI limits on log size. cfg.define("CMAKE_INSTALL_MESSAGE", "LAZY"); + if builder.config.quiet { + // Only log errors and warnings from `cmake`. + cfg.define("CMAKE_MESSAGE_LOG_LEVEL", "WARNING"); + + // If we're configuring llvm to build with `ninja`, we can suppress output from it with + // `--quiet`. Otherwise don't add anything since we don't know which build system is going + // to use. + if builder.ninja() { + cfg.build_arg("--quiet"); + } + } + // Do not allow the user's value of DESTDIR to influence where // LLVM will install itself. LLVM must always be installed in our // own build directories. diff --git a/src/bootstrap/src/core/build_steps/test.rs b/src/bootstrap/src/core/build_steps/test.rs index c222aa230564..991592ec522d 100644 --- a/src/bootstrap/src/core/build_steps/test.rs +++ b/src/bootstrap/src/core/build_steps/test.rs @@ -2334,6 +2334,10 @@ fn run(self, builder: &Builder<'_>) { cmd.arg("--verbose"); } + if builder.config.cmd.verbose_run_make_subprocess_output() { + cmd.arg("--verbose-run-make-subprocess-output"); + } + if builder.config.rustc_debug_assertions { cmd.arg("--with-rustc-debug-assertions"); } diff --git a/src/bootstrap/src/core/builder/cargo.rs b/src/bootstrap/src/core/builder/cargo.rs index f785254d90da..e9659f0176fc 100644 --- a/src/bootstrap/src/core/builder/cargo.rs +++ b/src/bootstrap/src/core/builder/cargo.rs @@ -509,6 +509,11 @@ pub fn bare_cargo( } }; + // Optionally suppress cargo output. + if self.config.quiet { + cargo.arg("--quiet"); + } + // Run cargo from the source root so it can find .cargo/config. // This matters when using vendoring and the working directory is outside the repository. cargo.current_dir(&self.src); diff --git a/src/bootstrap/src/core/config/config.rs b/src/bootstrap/src/core/config/config.rs index 36e6432ee82a..04f020e44dd1 100644 --- a/src/bootstrap/src/core/config/config.rs +++ b/src/bootstrap/src/core/config/config.rs @@ -140,6 +140,7 @@ pub struct Config { pub config: Option, pub jobs: Option, pub cmd: Subcommand, + pub quiet: bool, pub incremental: bool, pub dump_bootstrap_shims: bool, /// Arguments appearing after `--` to be forwarded to tools, @@ -369,6 +370,7 @@ pub(crate) fn parse_inner( let Flags { cmd: flags_cmd, verbose: flags_verbose, + quiet: flags_quiet, incremental: flags_incremental, config: flags_config, build_dir: flags_build_dir, @@ -1433,6 +1435,7 @@ pub(crate) fn parse_inner( print_step_timings: build_print_step_timings.unwrap_or(false), profiler: build_profiler.unwrap_or(false), python: build_python.map(PathBuf::from), + quiet: flags_quiet, reproducible_artifacts: flags_reproducible_artifact, reuse: build_reuse.map(PathBuf::from), rust_analyzer_info, diff --git a/src/bootstrap/src/core/config/flags.rs b/src/bootstrap/src/core/config/flags.rs index 2f1e234d6ebc..dce8a4c09a7e 100644 --- a/src/bootstrap/src/core/config/flags.rs +++ b/src/bootstrap/src/core/config/flags.rs @@ -46,9 +46,12 @@ pub struct Flags { #[command(subcommand)] pub cmd: Subcommand, - #[arg(global = true, short, long, action = clap::ArgAction::Count)] + #[arg(global = true, short, long, action = clap::ArgAction::Count, conflicts_with = "quiet")] /// use verbose output (-vv for very verbose) pub verbose: u8, // each extra -v after the first is passed to Cargo + #[arg(global = true, short, long, conflicts_with = "verbose")] + /// use quiet output + pub quiet: bool, #[arg(global = true, short, long)] /// use incremental compilation pub incremental: bool, @@ -422,6 +425,10 @@ pub enum Subcommand { #[arg(long)] /// don't capture stdout/stderr of tests no_capture: bool, + #[arg(long, default_value_t = true, action = clap::ArgAction::Set, default_missing_value = "true", num_args = 0..=1, require_equals = true)] + /// whether to show verbose subprocess output for run-make tests; + /// set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture) + verbose_run_make_subprocess_output: bool, #[arg(long)] /// Use a different codegen backend when running tests. test_codegen_backend: Option, @@ -631,6 +638,15 @@ pub fn no_capture(&self) -> bool { } } + pub fn verbose_run_make_subprocess_output(&self) -> bool { + match *self { + Subcommand::Test { verbose_run_make_subprocess_output, .. } => { + verbose_run_make_subprocess_output + } + _ => true, + } + } + pub fn rustfix_coverage(&self) -> bool { match *self { Subcommand::Test { rustfix_coverage, .. } => rustfix_coverage, diff --git a/src/bootstrap/src/core/debuggers/lldb.rs b/src/bootstrap/src/core/debuggers/lldb.rs index 55c9818eb315..230239512da8 100644 --- a/src/bootstrap/src/core/debuggers/lldb.rs +++ b/src/bootstrap/src/core/debuggers/lldb.rs @@ -19,7 +19,7 @@ pub(crate) fn discover_lldb(builder: &Builder<'_>) -> Option { .arg("--version") .run_capture(builder) .stdout_if_ok() - .and_then(|v| if v.trim().is_empty() { None } else { Some(v) })?; + .filter(|v| !v.trim().is_empty())?; Some(Lldb { lldb_exe, lldb_version }) } diff --git a/src/bootstrap/src/core/download.rs b/src/bootstrap/src/core/download.rs index b8e00c596f28..3b3044484f39 100644 --- a/src/bootstrap/src/core/download.rs +++ b/src/bootstrap/src/core/download.rs @@ -398,6 +398,16 @@ pub fn download_ci_gcc(&self, gcc_sha: &str, root_dir: &Path) { self.download_file(&format!("{base}/{gcc_sha}/{filename}"), &tarball, help_on_error); } self.unpack(&tarball, root_dir, "gcc-dev"); + + if self.should_fix_bins_and_dylibs() { + let lib_dir = root_dir.join("lib"); + for entry in t!(fs::read_dir(lib_dir)) { + let lib = t!(entry).path(); + if path_is_dylib(&lib) { + self.fix_bin_or_dylib(&lib); + } + } + } } } @@ -677,6 +687,8 @@ fn fix_bin_or_dylib(out: &Path, fname: &Path, exec_ctx: &ExecutionContext) { // bintools: Needed for the path of `ld-linux.so` (via `nix-support/dynamic-linker`). // cc.lib: Needed similarly for `libstdc++.so.6`. // zlib: Needed as a system dependency of `libLLVM-*.so`. + // zstd.out: Needed as a system dependency of `libgccjit.so`. `.out` is necessary as the + // default output of `zstd` derivation is `.bin`. // patchelf: Needed for patching ELF binaries (see doc comment above). let nix_deps_dir = out.join(".nix-deps"); const NIX_EXPR: &str = " @@ -685,6 +697,7 @@ fn fix_bin_or_dylib(out: &Path, fname: &Path, exec_ctx: &ExecutionContext) { name = \"rust-stage0-dependencies\"; paths = [ zlib + zstd.out patchelf stdenv.cc.bintools stdenv.cc.cc.lib diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs index c4a6b68aedee..ca8af279b92b 100644 --- a/src/bootstrap/src/core/sanity.rs +++ b/src/bootstrap/src/core/sanity.rs @@ -37,8 +37,6 @@ pub struct Finder { /// when the newly-bumped stage 0 compiler now knows about the formerly-missing targets. const STAGE0_MISSING_TARGETS: &[&str] = &[ // just a dummy comment so the list doesn't get onelined - "x86_64-unknown-linux-gnumsan", - "x86_64-unknown-linux-gnutsan", ]; /// Minimum version threshold for libstdc++ required when using prebuilt LLVM diff --git a/src/bootstrap/src/utils/change_tracker.rs b/src/bootstrap/src/utils/change_tracker.rs index 3ae2373e1da2..331403f959b4 100644 --- a/src/bootstrap/src/utils/change_tracker.rs +++ b/src/bootstrap/src/utils/change_tracker.rs @@ -621,4 +621,9 @@ pub fn human_readable_changes(changes: &[ChangeInfo]) -> String { severity: ChangeSeverity::Info, summary: "`x.py` stopped accepting partial argument names. Use full names to avoid errors.", }, + ChangeInfo { + change_id: 154587, + severity: ChangeSeverity::Info, + summary: "New `--verbose-run-make-subprocess-output` flag for `x.py test` (defaults to true). Set `--verbose-run-make-subprocess-output=false` to suppress verbose subprocess output for passing run-make tests when using `--no-capture`.", + }, ]; diff --git a/src/ci/docker/host-x86_64/dist-arm-linux-musl/Dockerfile b/src/ci/docker/host-x86_64/dist-arm-linux-musl/Dockerfile index 99667d68ab7a..a34b97d9b3b7 100644 --- a/src/ci/docker/host-x86_64/dist-arm-linux-musl/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-arm-linux-musl/Dockerfile @@ -6,6 +6,8 @@ RUN sh /scripts/cross-apt-packages.sh WORKDIR /build COPY scripts/musl-toolchain.sh /build/ +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ # We need to mitigate rust-lang/rust#34978 when compiling musl itself as well RUN CFLAGS="-Wa,--compress-debug-sections=none -Wl,--compress-debug-sections=none" \ CXXFLAGS="-Wa,--compress-debug-sections=none -Wl,--compress-debug-sections=none" \ diff --git a/src/ci/docker/host-x86_64/dist-i586-gnu-i586-i686-musl/Dockerfile b/src/ci/docker/host-x86_64/dist-i586-gnu-i586-i686-musl/Dockerfile index 31d009b6969a..cf8ff07a5b07 100644 --- a/src/ci/docker/host-x86_64/dist-i586-gnu-i586-i686-musl/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-i586-gnu-i586-i686-musl/Dockerfile @@ -39,6 +39,8 @@ ENV \ WORKDIR /build/ COPY scripts/musl.sh /build/ +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ RUN CC=gcc CFLAGS="-m32 -Wa,-mrelax-relocations=no" \ CXX=g++ CXXFLAGS="-m32 -Wa,-mrelax-relocations=no" \ bash musl.sh i686 --target=i686 && \ diff --git a/src/ci/docker/host-x86_64/dist-various-1/Dockerfile b/src/ci/docker/host-x86_64/dist-various-1/Dockerfile index ff80d0e3c296..33b48de87271 100644 --- a/src/ci/docker/host-x86_64/dist-various-1/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-various-1/Dockerfile @@ -65,6 +65,8 @@ ENV PATH="/build/emsdk:/build/emsdk/upstream/emscripten:/build/emsdk/node/curren ENV STAGING_DIR=/tmp COPY scripts/musl.sh /build +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ RUN env \ CC=arm-linux-gnueabi-gcc CFLAGS="-march=armv5te -marm -mfloat-abi=soft" \ CXX=arm-linux-gnueabi-g++ CXXFLAGS="-march=armv5te -marm -mfloat-abi=soft" \ diff --git a/src/ci/docker/host-x86_64/dist-various-2/Dockerfile b/src/ci/docker/host-x86_64/dist-various-2/Dockerfile index e248e1e44ca3..13d76c001a2f 100644 --- a/src/ci/docker/host-x86_64/dist-various-2/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-various-2/Dockerfile @@ -68,6 +68,8 @@ ENV \ WORKDIR /build COPY scripts/musl.sh /build +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ RUN env \ CC=arm-linux-gnueabi-gcc-9 CFLAGS="-march=armv7-a" \ CXX=arm-linux-gnueabi-g++-9 CXXFLAGS="-march=armv7-a" \ diff --git a/src/ci/docker/host-x86_64/dist-x86_64-musl/Dockerfile b/src/ci/docker/host-x86_64/dist-x86_64-musl/Dockerfile index 68f914a81552..aaca6b2bb9af 100644 --- a/src/ci/docker/host-x86_64/dist-x86_64-musl/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-x86_64-musl/Dockerfile @@ -25,6 +25,8 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ WORKDIR /build/ COPY scripts/musl-toolchain.sh /build/ +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ # We need to mitigate rust-lang/rust#34978 when compiling musl itself as well RUN CFLAGS="-Wa,-mrelax-relocations=no -Wa,--compress-debug-sections=none -Wl,--compress-debug-sections=none" \ CXXFLAGS="-Wa,-mrelax-relocations=no -Wa,--compress-debug-sections=none -Wl,--compress-debug-sections=none" \ diff --git a/src/ci/docker/host-x86_64/test-various/Dockerfile b/src/ci/docker/host-x86_64/test-various/Dockerfile index 10ea2646bf3b..626929d6c19b 100644 --- a/src/ci/docker/host-x86_64/test-various/Dockerfile +++ b/src/ci/docker/host-x86_64/test-various/Dockerfile @@ -35,6 +35,8 @@ ENV PATH="/node/bin:${PATH}" WORKDIR /build/ COPY scripts/musl-toolchain.sh /build/ +COPY scripts/musl-cve-2026-6042.diff /build/ +COPY scripts/musl-cve-2026-40200.diff /build/ RUN bash musl-toolchain.sh x86_64 && rm -rf build WORKDIR / diff --git a/src/ci/docker/scripts/musl-cve-2026-40200.diff b/src/ci/docker/scripts/musl-cve-2026-40200.diff new file mode 100644 index 000000000000..88298ca471d3 --- /dev/null +++ b/src/ci/docker/scripts/musl-cve-2026-40200.diff @@ -0,0 +1,179 @@ +>From 228da39e38c1cae13cbe637e771412c1984dba5d Mon Sep 17 00:00:00 2001 +From: Rich Felker +Date: Thu, 9 Apr 2026 22:51:30 -0400 +Subject: [PATCH 1/3] qsort: fix leonardo heap corruption from bug in + doubleword ctz primitive + +the pntz function, implementing a "count trailing zeros" variant for a +bit vector consisting of two size_t words, erroneously returned zero +rather than the number of bits in the low word when the first bit set +was the low bit of the high word. + +as a result, a loop in the trinkle function which should have a +guaranteed small bound on the number of iterations, could run +unboundedly, thereby overflowing a stack-based working-space array +which was sized for the bound. + +CVE-2026-40200 has been assigned for this issue. +--- + src/stdlib/qsort.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/stdlib/qsort.c b/src/stdlib/qsort.c +index ab79dc6f..13219ab3 100644 +--- a/src/stdlib/qsort.c ++++ b/src/stdlib/qsort.c +@@ -34,11 +34,11 @@ + + typedef int (*cmpfun)(const void *, const void *, void *); + ++/* returns index of first bit set, excluding the low bit assumed to always ++ * be set, starting from low bit of p[0] up through high bit of p[1] */ + static inline int pntz(size_t p[2]) { +- int r = ntz(p[0] - 1); +- if(r != 0 || (r = 8*sizeof(size_t) + ntz(p[1])) != 8*sizeof(size_t)) { +- return r; +- } ++ if (p[0] != 1) return ntz(p[0] - 1); ++ if (p[1]) return 8*sizeof(size_t) + ntz(p[1]); + return 0; + } + +-- +2.21.0 + + +>From b3291b9a9f77f1f993d2b4f8c68a26cf09221ae7 Mon Sep 17 00:00:00 2001 +From: Rich Felker +Date: Thu, 9 Apr 2026 23:40:53 -0400 +Subject: [PATCH 2/3] qsort: hard-preclude oob array writes independent of any + invariants + +while the root cause of CVE-2026-40200 was a faulty ctz primitive, the +fallout of the bug would have been limited to erroneous sorting or +infinite loop if not for the stores to a stack-based array that +depended on trusting invariants in order not to go out of bounds. + +increase the size of the array to a power of two so that we can mask +indices into it to force them into range. in the absence of any +further bug, the masking is a no-op, but it does not have any +measurable performance cost, and it makes spatial memory safety +trivial to prove (and for readers not familiar with the algorithms to +trust). +--- + src/stdlib/qsort.c | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +diff --git a/src/stdlib/qsort.c b/src/stdlib/qsort.c +index 13219ab3..e4bce9f7 100644 +--- a/src/stdlib/qsort.c ++++ b/src/stdlib/qsort.c +@@ -89,10 +89,16 @@ static inline void shr(size_t p[2], int n) + p[1] >>= n; + } + ++/* power-of-two length for working array so that we can mask indices and ++ * not depend on any invariant of the algorithm for spatial memory safety. ++ * the original size was just 14*sizeof(size_t)+1 */ ++#define AR_LEN (16 * sizeof(size_t)) ++#define AR_MASK (AR_LEN - 1) ++ + static void sift(unsigned char *head, size_t width, cmpfun cmp, void *arg, int pshift, size_t lp[]) + { + unsigned char *rt, *lf; +- unsigned char *ar[14 * sizeof(size_t) + 1]; ++ unsigned char *ar[AR_LEN]; + int i = 1; + + ar[0] = head; +@@ -104,16 +110,16 @@ static void sift(unsigned char *head, size_t width, cmpfun cmp, void *arg, int p + break; + } + if(cmp(lf, rt, arg) >= 0) { +- ar[i++] = lf; ++ ar[i++ & AR_MASK] = lf; + head = lf; + pshift -= 1; + } else { +- ar[i++] = rt; ++ ar[i++ & AR_MASK] = rt; + head = rt; + pshift -= 2; + } + } +- cycle(width, ar, i); ++ cycle(width, ar, i & AR_MASK); + } + + static void trinkle(unsigned char *head, size_t width, cmpfun cmp, void *arg, size_t pp[2], int pshift, int trusty, size_t lp[]) +@@ -121,7 +127,7 @@ static void trinkle(unsigned char *head, size_t width, cmpfun cmp, void *arg, si + unsigned char *stepson, + *rt, *lf; + size_t p[2]; +- unsigned char *ar[14 * sizeof(size_t) + 1]; ++ unsigned char *ar[AR_LEN]; + int i = 1; + int trail; + +@@ -142,7 +148,7 @@ static void trinkle(unsigned char *head, size_t width, cmpfun cmp, void *arg, si + } + } + +- ar[i++] = stepson; ++ ar[i++ & AR_MASK] = stepson; + head = stepson; + trail = pntz(p); + shr(p, trail); +@@ -150,7 +156,7 @@ static void trinkle(unsigned char *head, size_t width, cmpfun cmp, void *arg, si + trusty = 0; + } + if(!trusty) { +- cycle(width, ar, i); ++ cycle(width, ar, i & AR_MASK); + sift(head, width, cmp, arg, pshift, lp); + } + } +-- +2.21.0 + + +>From 5122f9f3c99fee366167c5de98b31546312921ab Mon Sep 17 00:00:00 2001 +From: Luca Kellermann +Date: Fri, 10 Apr 2026 03:03:22 +0200 +Subject: [PATCH 3/3] qsort: fix shift UB in shl and shr + +if shl() or shr() are called with n==8*sizeof(size_t), n is adjusted +to 0. the shift by (sizeof(size_t) * 8 - n) that then follows will +consequently shift by the width of size_t, which is UB and in practice +produces an incorrect result. + +return early in this case. the bitvector p was already shifted by the +required amount. +--- + src/stdlib/qsort.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/stdlib/qsort.c b/src/stdlib/qsort.c +index e4bce9f7..28607450 100644 +--- a/src/stdlib/qsort.c ++++ b/src/stdlib/qsort.c +@@ -71,6 +71,7 @@ static inline void shl(size_t p[2], int n) + n -= 8 * sizeof(size_t); + p[1] = p[0]; + p[0] = 0; ++ if (!n) return; + } + p[1] <<= n; + p[1] |= p[0] >> (sizeof(size_t) * 8 - n); +@@ -83,6 +84,7 @@ static inline void shr(size_t p[2], int n) + n -= 8 * sizeof(size_t); + p[0] = p[1]; + p[1] = 0; ++ if (!n) return; + } + p[0] >>= n; + p[0] |= p[1] << (sizeof(size_t) * 8 - n); +-- +2.21.0 + + diff --git a/src/ci/docker/scripts/musl-cve-2026-6042.diff b/src/ci/docker/scripts/musl-cve-2026-6042.diff new file mode 100644 index 000000000000..9b39420ea3c5 --- /dev/null +++ b/src/ci/docker/scripts/musl-cve-2026-6042.diff @@ -0,0 +1,321 @@ +>From 67219f0130ec7c876ac0b299046460fad31caabf Mon Sep 17 00:00:00 2001 +From: Rich Felker +Date: Mon, 30 Mar 2026 16:00:50 -0400 +Subject: [PATCH] fix pathological slowness & incorrect mappings in iconv + gb18030 decoder + +in order to implement the "UTF" aspect of gb18030 (ability to +represent arbitrary unicode characters not present in the 2-byte +mapping), we have to apply the index obtained from the encoded 4-byte +sequence into the set of unmapped characters. this was done by +scanning repeatedly over the table of mapped characters and counting +off mapped characters below a running index by which to adjust the +running index by on each iteration. this iterative process eventually +leaves us with the value of the Nth unmapped character replacing the +index, but depending on which particular character that is, the number +of iterations needed to find it can be in the tens of thousands, and +each iteration traverses the whole 126x190 table in the inner loop. +this can lead to run times exceeding an entire second per character on +moderate-speed machines. + +on top of that, the transformation logic produced wrong results for +BMP characters above the the surrogate range, as a result of not +correctly accounting for it being excluded, and for characters outside +the BMP, as a result of a misunderstanding of how gb18030 encodes +them. + +this patch replaces the unmapped character lookup with a single linear +search of a list of unmapped ranges. there are only 206 such ranges, +and these are permanently assigned and unchangeable as a consequence +of the character encoding having to be stable, so a simple array of +16-bit start/length values for each range consumes only 824 bytes, a +very reasonable size cost here. + +this new table accounts for the previously-incorrect surrogate +handling, and non-BMP characters are handled correctly by a single +offset, without the need for any unmapped-range search. + +there are still a small number of mappings that are incorrect due to +late changes made in the definition of gb18030, swapping PUA +codepoints with proper Unicode characters. correcting these requires a +postprocessing step that will be added later. +--- + src/locale/gb18030utf.h | 206 ++++++++++++++++++++++++++++++++++++++++ + src/locale/iconv.c | 33 +++++-- + 2 files changed, 230 insertions(+), 9 deletions(-) + create mode 100644 src/locale/gb18030utf.h + +diff --git a/src/locale/gb18030utf.h b/src/locale/gb18030utf.h +new file mode 100644 +index 00000000..322a2440 +--- /dev/null ++++ b/src/locale/gb18030utf.h +@@ -0,0 +1,206 @@ ++{ 0x80, 36 }, ++{ 0xa5, 2 }, ++{ 0xa9, 7 }, ++{ 0xb2, 5 }, ++{ 0xb8, 31 }, ++{ 0xd8, 8 }, ++{ 0xe2, 6 }, ++{ 0xeb, 1 }, ++{ 0xee, 4 }, ++{ 0xf4, 3 }, ++{ 0xf8, 1 }, ++{ 0xfb, 1 }, ++{ 0xfd, 4 }, ++{ 0x102, 17 }, ++{ 0x114, 7 }, ++{ 0x11c, 15 }, ++{ 0x12c, 24 }, ++{ 0x145, 3 }, ++{ 0x149, 4 }, ++{ 0x14e, 29 }, ++{ 0x16c, 98 }, ++{ 0x1cf, 1 }, ++{ 0x1d1, 1 }, ++{ 0x1d3, 1 }, ++{ 0x1d5, 1 }, ++{ 0x1d7, 1 }, ++{ 0x1d9, 1 }, ++{ 0x1db, 1 }, ++{ 0x1dd, 28 }, ++{ 0x1fa, 87 }, ++{ 0x252, 15 }, ++{ 0x262, 101 }, ++{ 0x2c8, 1 }, ++{ 0x2cc, 13 }, ++{ 0x2da, 183 }, ++{ 0x3a2, 1 }, ++{ 0x3aa, 7 }, ++{ 0x3c2, 1 }, ++{ 0x3ca, 55 }, ++{ 0x402, 14 }, ++{ 0x450, 1 }, ++{ 0x452, 7102 }, ++{ 0x2011, 2 }, ++{ 0x2017, 1 }, ++{ 0x201a, 2 }, ++{ 0x201e, 7 }, ++{ 0x2027, 9 }, ++{ 0x2031, 1 }, ++{ 0x2034, 1 }, ++{ 0x2036, 5 }, ++{ 0x203c, 112 }, ++{ 0x20ad, 86 }, ++{ 0x2104, 1 }, ++{ 0x2106, 3 }, ++{ 0x210a, 12 }, ++{ 0x2117, 10 }, ++{ 0x2122, 62 }, ++{ 0x216c, 4 }, ++{ 0x217a, 22 }, ++{ 0x2194, 2 }, ++{ 0x219a, 110 }, ++{ 0x2209, 6 }, ++{ 0x2210, 1 }, ++{ 0x2212, 3 }, ++{ 0x2216, 4 }, ++{ 0x221b, 2 }, ++{ 0x2221, 2 }, ++{ 0x2224, 1 }, ++{ 0x2226, 1 }, ++{ 0x222c, 2 }, ++{ 0x222f, 5 }, ++{ 0x2238, 5 }, ++{ 0x223e, 10 }, ++{ 0x2249, 3 }, ++{ 0x224d, 5 }, ++{ 0x2253, 13 }, ++{ 0x2262, 2 }, ++{ 0x2268, 6 }, ++{ 0x2270, 37 }, ++{ 0x2296, 3 }, ++{ 0x229a, 11 }, ++{ 0x22a6, 25 }, ++{ 0x22c0, 82 }, ++{ 0x2313, 333 }, ++{ 0x246a, 10 }, ++{ 0x249c, 100 }, ++{ 0x254c, 4 }, ++{ 0x2574, 13 }, ++{ 0x2590, 3 }, ++{ 0x2596, 10 }, ++{ 0x25a2, 16 }, ++{ 0x25b4, 8 }, ++{ 0x25be, 8 }, ++{ 0x25c8, 3 }, ++{ 0x25cc, 2 }, ++{ 0x25d0, 18 }, ++{ 0x25e6, 31 }, ++{ 0x2607, 2 }, ++{ 0x260a, 54 }, ++{ 0x2641, 1 }, ++{ 0x2643, 2110 }, ++{ 0x2e82, 2 }, ++{ 0x2e85, 3 }, ++{ 0x2e89, 2 }, ++{ 0x2e8d, 10 }, ++{ 0x2e98, 15 }, ++{ 0x2ea8, 2 }, ++{ 0x2eab, 3 }, ++{ 0x2eaf, 4 }, ++{ 0x2eb4, 2 }, ++{ 0x2eb8, 3 }, ++{ 0x2ebc, 14 }, ++{ 0x2ecb, 293 }, ++{ 0x2ffc, 4 }, ++{ 0x3004, 1 }, ++{ 0x3018, 5 }, ++{ 0x301f, 2 }, ++{ 0x302a, 20 }, ++{ 0x303f, 2 }, ++{ 0x3094, 7 }, ++{ 0x309f, 2 }, ++{ 0x30f7, 5 }, ++{ 0x30ff, 6 }, ++{ 0x312a, 246 }, ++{ 0x322a, 7 }, ++{ 0x3232, 113 }, ++{ 0x32a4, 234 }, ++{ 0x3390, 12 }, ++{ 0x339f, 2 }, ++{ 0x33a2, 34 }, ++{ 0x33c5, 9 }, ++{ 0x33cf, 2 }, ++{ 0x33d3, 2 }, ++{ 0x33d6, 113 }, ++{ 0x3448, 43 }, ++{ 0x3474, 298 }, ++{ 0x359f, 111 }, ++{ 0x360f, 11 }, ++{ 0x361b, 765 }, ++{ 0x3919, 85 }, ++{ 0x396f, 96 }, ++{ 0x39d1, 14 }, ++{ 0x39e0, 147 }, ++{ 0x3a74, 218 }, ++{ 0x3b4f, 287 }, ++{ 0x3c6f, 113 }, ++{ 0x3ce1, 885 }, ++{ 0x4057, 264 }, ++{ 0x4160, 471 }, ++{ 0x4338, 116 }, ++{ 0x43ad, 4 }, ++{ 0x43b2, 43 }, ++{ 0x43de, 248 }, ++{ 0x44d7, 373 }, ++{ 0x464d, 20 }, ++{ 0x4662, 193 }, ++{ 0x4724, 5 }, ++{ 0x472a, 82 }, ++{ 0x477d, 16 }, ++{ 0x478e, 441 }, ++{ 0x4948, 50 }, ++{ 0x497b, 2 }, ++{ 0x497e, 4 }, ++{ 0x4984, 1 }, ++{ 0x4987, 20 }, ++{ 0x499c, 3 }, ++{ 0x49a0, 22 }, ++{ 0x49b8, 703 }, ++{ 0x4c78, 39 }, ++{ 0x4ca4, 111 }, ++{ 0x4d1a, 148 }, ++{ 0x4daf, 81 }, ++{ 0x9fa6, 14426 }, ++{ 0xe76c, 1 }, ++{ 0xe7c8, 1 }, ++{ 0xe7e7, 13 }, ++{ 0xe815, 1 }, ++{ 0xe819, 5 }, ++{ 0xe81f, 7 }, ++{ 0xe827, 4 }, ++{ 0xe82d, 4 }, ++{ 0xe833, 8 }, ++{ 0xe83c, 7 }, ++{ 0xe844, 16 }, ++{ 0xe856, 14 }, ++{ 0xe865, 4295 }, ++{ 0xf92d, 76 }, ++{ 0xf97a, 27 }, ++{ 0xf996, 81 }, ++{ 0xf9e8, 9 }, ++{ 0xf9f2, 26 }, ++{ 0xfa10, 1 }, ++{ 0xfa12, 1 }, ++{ 0xfa15, 3 }, ++{ 0xfa19, 6 }, ++{ 0xfa22, 1 }, ++{ 0xfa25, 2 }, ++{ 0xfa2a, 1030 }, ++{ 0xfe32, 1 }, ++{ 0xfe45, 4 }, ++{ 0xfe53, 1 }, ++{ 0xfe58, 1 }, ++{ 0xfe67, 1 }, ++{ 0xfe6c, 149 }, ++{ 0xff5f, 129 }, ++{ 0xffe6, 26 }, +diff --git a/src/locale/iconv.c b/src/locale/iconv.c +index 52178950..4151411d 100644 +--- a/src/locale/iconv.c ++++ b/src/locale/iconv.c +@@ -74,6 +74,10 @@ static const unsigned short gb18030[126][190] = { + #include "gb18030.h" + }; + ++static const unsigned short gb18030utf[][2] = { ++#include "gb18030utf.h" ++}; ++ + static const unsigned short big5[89][157] = { + #include "big5.h" + }; +@@ -224,6 +228,8 @@ static unsigned uni_to_jis(unsigned c) + } + } + ++#define countof(a) (sizeof (a) / sizeof *(a)) ++ + size_t iconv(iconv_t cd, char **restrict in, size_t *restrict inb, char **restrict out, size_t *restrict outb) + { + size_t x=0; +@@ -430,15 +436,24 @@ size_t iconv(iconv_t cd, char **restrict in, size_t *restrict inb, char **restri + d = *((unsigned char *)*in + 3); + if (d-'0'>9) goto ilseq; + c += d-'0'; +- c += 128; +- for (d=0; d<=c; ) { +- k = 0; +- for (int i=0; i<126; i++) +- for (int j=0; j<190; j++) +- if (gb18030[i][j]-d <= c-d) +- k++; +- d = c+1; +- c += k; ++ /* Starting at 90 30 81 30 (189000), mapping is ++ * linear without gaps, to U+10000 and up. */ ++ if (c >= 189000) { ++ c -= 189000; ++ c += 0x10000; ++ if (c >= 0x110000) goto ilseq; ++ break; ++ } ++ /* Otherwise we must process an index into set ++ * of characters unmapped by 2-byte table. */ ++ for (int i=0; ; i++) { ++ if (i==countof(gb18030utf)) ++ goto ilseq; ++ if (c= 1.2.7. +cp /build/musl-cve-2026-6042.diff ./patches/musl-1.2.5/0003-cve-2026-6042.diff +cp /build/musl-cve-2026-40200.diff ./patches/musl-1.2.5/0004-cve-2026-40200.diff + hide_output make -j$(nproc) TARGET=$TARGET MUSL_VER=1.2.5 LINUX_HEADERS_SITE=$LINUX_HEADERS_SITE LINUX_VER=$LINUX_VER hide_output make install TARGET=$TARGET MUSL_VER=1.2.5 LINUX_HEADERS_SITE=$LINUX_HEADERS_SITE LINUX_VER=$LINUX_VER OUTPUT=$OUTPUT diff --git a/src/ci/docker/scripts/musl.sh b/src/ci/docker/scripts/musl.sh index 7e293d748ce1..7258d3935e0f 100644 --- a/src/ci/docker/scripts/musl.sh +++ b/src/ci/docker/scripts/musl.sh @@ -71,6 +71,19 @@ EOF *outb -= k; break; EOF + + # Apply patches for CVE-2026-6042 and CVE-2026-40200. + # + # At the time of adding these patches no release containing them has been published by the musl + # project, so we just apply them directly on top of the version we were distributing already. The + # patches should be removed once we upgrade to musl >= 1.2.7. + # + # Advisory: https://www.openwall.com/lists/oss-security/2026/04/09/19 + # Patches: https://www.openwall.com/lists/musl/2026/04/03/2/1 + patch -p1 -d $MUSL = &'a u32; ``` Will emit the following: ```text -error: layout_of(&'a u32) = Layout { - fields: Primitive, - variants: Single { - index: 0, - }, - abi: Scalar( - Scalar { - value: Pointer, - valid_range: 1..=18446744073709551615, - }, - ), - largest_niche: Some( - Niche { - offset: Size { - raw: 0, - }, - scalar: Scalar { - value: Pointer, - valid_range: 1..=18446744073709551615, - }, - }, - ), - align: AbiAndPrefAlign { - abi: Align { - pow2: 3, - }, - pref: Align { - pow2: 3, - }, - }, - size: Size { - raw: 8, - }, -} +error: layout_of(&u32) = Layout { + size: Size(8 bytes), + align: AbiAlign { + abi: Align(8 bytes), + }, + backend_repr: Scalar( + Initialized { + value: Pointer( + AddressSpace( + 0, + ), + ), + valid_range: 1..=18446744073709551615, + }, + ), + fields: Primitive, + largest_niche: Some( + Niche { + offset: Size(0 bytes), + value: Pointer( + AddressSpace( + 0, + ), + ), + valid_range: 1..=18446744073709551615, + }, + ), + uninhabited: false, + variants: Single { + index: 0, + }, + max_repr_align: None, + unadjusted_abi_align: Align(8 bytes), + randomization_seed: 281492156579847, + } --> src/lib.rs:4:1 | 4 | type T<'a> = &'a u32; diff --git a/src/doc/rustc-dev-guide/src/stability.md b/src/doc/rustc-dev-guide/src/stability.md index f2f2dd909fae..93c59675d893 100644 --- a/src/doc/rustc-dev-guide/src/stability.md +++ b/src/doc/rustc-dev-guide/src/stability.md @@ -23,6 +23,9 @@ The `unstable` attribute infects all sub-items, where the attribute doesn't have to be reapplied. So if you apply this to a module, all items in the module will be unstable. +If you rename a feature, you can add `old_name = "old_name"` to produce a +useful error message. + You can make specific sub-items stable by using the `#[stable]` attribute on them. The stability scheme works similarly to how `pub` works. You can have public functions of nonpublic modules and you can have stable functions in @@ -189,4 +192,11 @@ Currently, the items that can be annotated with `#[unstable_feature_bound]` are: - free function - trait +## renamed and removed features +Unstable features can get renamed and removed. If you rename a feature, you can add `old_name = "old_name"` to the `#[unstable]` attribute. +If you remove a feature, the `#!unstable_removed(feature = "foo", reason = "brief description", link = "link", since = "1.90.0")` +attribute should be used to produce a good error message for users of the removed feature. + +The `link` field can be used to link to the most relevant information on the removal of the feature such as a GitHub issue, comment or PR. + [blog]: https://www.ralfj.de/blog/2018/07/19/const.html diff --git a/src/doc/rustc-dev-guide/src/tests/compiletest.md b/src/doc/rustc-dev-guide/src/tests/compiletest.md index 83fcfecc1de7..068e876d0fd8 100644 --- a/src/doc/rustc-dev-guide/src/tests/compiletest.md +++ b/src/doc/rustc-dev-guide/src/tests/compiletest.md @@ -190,11 +190,6 @@ substring must not appear anywhere in the compiler output. This can be useful to ensure certain errors do not appear, but this can be fragile as error messages change over time, and a test may no longer be checking the right thing but will still pass. -`cfail` tests support the `should-ice` directive to specify that a test should -cause an Internal Compiler Error (ICE). -This is a highly specialized directive -to check that the incremental cache continues to work after an ICE. - Incremental tests may use the attribute `#[rustc_clean(...)]` attribute. This attribute compares the fingerprint from the current compilation session with the previous one. The first revision should never have an active `rustc_clean` attribute, since it will always be dirty. @@ -460,6 +455,15 @@ However, revisions or building auxiliary via directives are not currently suppor `rmake.rs` and `run-make-support` may *not* use any nightly/unstable features, as they must be compilable by a stage 0 rustc that may be a beta or even stable rustc. +By default, run-make tests print each subprocess command and its stdout/stderr. +When running with `--no-capture` on `panic=abort` test suites (such as `cg_clif`), +this can flood the terminal. Omit `--verbose-run-make-subprocess-output` to +suppress this output for passing tests — failing tests always print regardless: + +```bash +./x test tests/run-make --no-capture --verbose-run-make-subprocess-output=false +``` + #### Quickly check if `rmake.rs` tests can be compiled You can quickly check if `rmake.rs` tests can be compiled without having to diff --git a/src/doc/rustc-dev-guide/src/tests/directives.md b/src/doc/rustc-dev-guide/src/tests/directives.md index f160f3fffc10..a9fe59e85d09 100644 --- a/src/doc/rustc-dev-guide/src/tests/directives.md +++ b/src/doc/rustc-dev-guide/src/tests/directives.md @@ -80,8 +80,7 @@ See [Controlling pass/fail expectations](ui.md#controlling-passfail-expectations | `run-fail-or-crash` | Program must `run-fail` or `run-crash` | `ui` | N/A | | `ignore-pass` | Ignore `--pass` flag | `ui`, `crashes`, `codegen`, `incremental` | N/A | | `dont-check-failure-status` | Don't check exact failure status (i.e. `1`) | `ui`, `incremental` | N/A | -| `failure-status` | Check | `ui`, `crashes` | Any `u16` | -| `should-ice` | Check failure status is `101` | `coverage`, `incremental` | N/A | +| `failure-status` | On failure, the compiler must exit with this status code. To expect an ICE, use `//@ failure-status: 101`. | `ui`, `crashes`, `incremental` | Any `u16` | | `should-fail` | Compiletest self-test | All | N/A | ### Controlling output snapshots and normalizations @@ -318,7 +317,6 @@ See [Pretty-printer](compiletest.md#pretty-printer-tests). - [`revisions`](compiletest.md#revisions) — compile multiple times -[`forbid-output`](compiletest.md#incremental-tests) — incremental cfail rejects output pattern -- [`should-ice`](compiletest.md#incremental-tests) — incremental cfail should ICE - [`reference`] — an annotation linking to a rule in the reference - `disable-gdb-pretty-printers` — disable gdb pretty printers for debuginfo tests diff --git a/src/doc/rustc/src/platform-support/hexagon-unknown-linux-musl.md b/src/doc/rustc/src/platform-support/hexagon-unknown-linux-musl.md index eefe82133906..9f4e8239cc7d 100644 --- a/src/doc/rustc/src/platform-support/hexagon-unknown-linux-musl.md +++ b/src/doc/rustc/src/platform-support/hexagon-unknown-linux-musl.md @@ -12,6 +12,7 @@ DSP architecture. ## Target maintainers [@androm3da](https://github.com/androm3da) +[@quic-mliebel](https://github.com/quic-mliebel) ## Requirements The target is cross-compiled. This target supports `std`. By default, code diff --git a/src/doc/rustdoc/src/unstable-features.md b/src/doc/rustdoc/src/unstable-features.md index ae007c4c13bb..1c91ad343b8c 100644 --- a/src/doc/rustdoc/src/unstable-features.md +++ b/src/doc/rustdoc/src/unstable-features.md @@ -759,6 +759,12 @@ it permits remapping source path prefixes in all output, including compiler diag debug information, macro expansions, etc. It takes a value of the form `FROM=TO` where a path prefix equal to `FROM` is rewritten to the value `TO`. +## `--remap-path-scope`: Scopes to which the source remapping should be done + +This flag is the equivalent flag from `rustc` `--remap-path-scope`. + +Defines which scopes of paths should be remapped by --remap-path-prefix. + ### `documentation` scope `rustdoc` (and by extension `rustc`) have a special `documentation` remapping scope, it diff --git a/src/doc/unstable-book/src/compiler-flags/llvm-writable.md b/src/doc/unstable-book/src/compiler-flags/llvm-writable.md new file mode 100644 index 000000000000..22fd01bbe076 --- /dev/null +++ b/src/doc/unstable-book/src/compiler-flags/llvm-writable.md @@ -0,0 +1,11 @@ +# `llvm-writable` + +--- + +Setting this flag will allow the compiler to insert the [writable](https://llvm.org/docs/LangRef.html#writable) LLVM flag. +This allows for more optimizations but also introduces more Undefined Behaviour. +To be more precise, mutable reference function arguments are now considered to be always writable, which means the compiler may insert writes to those references even if the original code contained no such writes. +The attribute `#[rustc_no_writable]` can be used to disable the optimization on a per-function basis. + +The [Miri](https://github.com/rust-lang/miri) tool can be used to detect some problematic cases. +However, note that when using Tree Borrows, you must set `-Zmiri-tree-borrows-implicit-writes` to ensure that the UB arising from these implicit writes is detected. diff --git a/src/doc/unstable-book/src/compiler-flags/sanitizer.md b/src/doc/unstable-book/src/compiler-flags/sanitizer.md index eb070c22dc28..b0f6c97ff5a7 100644 --- a/src/doc/unstable-book/src/compiler-flags/sanitizer.md +++ b/src/doc/unstable-book/src/compiler-flags/sanitizer.md @@ -552,10 +552,6 @@ HWAddressSanitizer is supported on the following targets: * `aarch64-linux-android` * `aarch64-unknown-linux-gnu` -HWAddressSanitizer requires `tagged-globals` target feature to instrument -globals. To enable this target feature compile with `-C -target-feature=+tagged-globals` - See the [Clang HWAddressSanitizer documentation][clang-hwasan] for more details. ## Example @@ -570,9 +566,8 @@ fn main() { ``` ```shell -$ rustc main.rs -Zsanitizer=hwaddress -C target-feature=+tagged-globals -C -linker=aarch64-linux-gnu-gcc -C link-arg=-fuse-ld=lld --target -aarch64-unknown-linux-gnu +$ rustc main.rs -Zsanitizer=hwaddress -Clinker=aarch64-linux-gnu-gcc +-Clink-arg=-fuse-ld=lld --target aarch64-unknown-linux-gnu ``` ```shell diff --git a/src/doc/unstable-book/src/language-features/cfg-target-object-format.md b/src/doc/unstable-book/src/language-features/cfg-target-object-format.md new file mode 100644 index 000000000000..34d6e2faca0f --- /dev/null +++ b/src/doc/unstable-book/src/language-features/cfg-target-object-format.md @@ -0,0 +1,34 @@ +# `cfg_target_object_format` + +The tracking issue for this feature is: [#152586] + +[#152586]: https://github.com/rust-lang/rust/issues/152586 + +------------------------ + +The `cfg_target_object_format` feature makes it possible to execute different code +depending on the current target's object file format. + +## Examples + +```rust +#![feature(cfg_target_object_format)] + +#[cfg(target_object_format = "elf")] +fn a() { + // ... +} + +#[cfg(target_object_format = "mach-o")] +fn a() { + // ... +} + +fn b() { + if cfg!(target_object_format = "wasm") { + // ... + } else { + // ... + } +} +``` diff --git a/src/doc/unstable-book/src/language-features/rustc-attrs.md b/src/doc/unstable-book/src/language-features/rustc-attrs.md index c67b806f06af..924f639a312c 100644 --- a/src/doc/unstable-book/src/language-features/rustc-attrs.md +++ b/src/doc/unstable-book/src/language-features/rustc-attrs.md @@ -9,19 +9,20 @@ only discuss a few of them. ------------------------ The `rustc_attrs` feature allows debugging rustc type layouts by using -`#[rustc_layout(...)]` to debug layout at compile time (it even works +`#[rustc_dump_layout(...)]` to debug layout at compile time (it even works with `cargo check`) as an alternative to `rustc -Z print-type-sizes` that is way more verbose. -Options provided by `#[rustc_layout(...)]` are `debug`, `size`, `align`, -`abi`. Note that it only works on sized types without generics. +Options provided by `#[rustc_dump_layout(...)]` are `backend_repr`, `align`, +`debug`, `homogeneous_aggregate` and `size`. +Note that it only works on sized types without generics. ## Examples ```rust,compile_fail #![feature(rustc_attrs)] -#[rustc_layout(abi, size)] +#[rustc_dump_layout(backend_repr, size)] pub enum X { Y(u8, u8, u8), Z(isize), @@ -31,7 +32,7 @@ pub enum X { When that is compiled, the compiler will error with something like ```text -error: abi: Aggregate { sized: true } +error: backend_repr: Aggregate { sized: true } --> src/lib.rs:4:1 | 4 | / pub enum T { diff --git a/src/etc/completions/x.fish b/src/etc/completions/x.fish index 92af4f04dcba..0b50ee19f8a5 100644 --- a/src/etc/completions/x.fish +++ b/src/etc/completions/x.fish @@ -1,6 +1,6 @@ # Print an optspec for argparse to handle cmd's options that are independent of any subcommand. function __fish_x_global_optspecs - string join \n v/verbose i/incremental config= build-dir= build= host= target= exclude= skip= include-default-paths rustc-error-format= on-fail= dry-run dump-bootstrap-shims stage= keep-stage= keep-stage-std= src= j/jobs= warnings= json-output compile-time-deps color= bypass-bootstrap-lock rust-profile-generate= rust-profile-use= llvm-profile-use= llvm-profile-generate enable-bolt-settings skip-stage0-validation reproducible-artifact= set= ci= skip-std-check-if-no-download-rustc h/help + string join \n v/verbose q/quiet i/incremental config= build-dir= build= host= target= exclude= skip= include-default-paths rustc-error-format= on-fail= dry-run dump-bootstrap-shims stage= keep-stage= keep-stage-std= src= j/jobs= warnings= json-output compile-time-deps color= bypass-bootstrap-lock rust-profile-generate= rust-profile-use= llvm-profile-use= llvm-profile-generate enable-bolt-settings skip-stage0-validation reproducible-artifact= set= ci= skip-std-check-if-no-download-rustc h/help end function __fish_x_needs_command @@ -47,6 +47,7 @@ complete -c x -n "__fish_x_needs_command" -l reproducible-artifact -d 'Additiona complete -c x -n "__fish_x_needs_command" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_needs_command" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_needs_command" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_needs_command" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_needs_command" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_needs_command" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_needs_command" -l dry-run -d 'dry run; don\'t build anything' @@ -104,6 +105,7 @@ complete -c x -n "__fish_x_using_subcommand build" -l set -d 'override options i complete -c x -n "__fish_x_using_subcommand build" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand build" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x -n "__fish_x_using_subcommand build" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand build" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand build" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand build" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand build" -l dry-run -d 'dry run; don\'t build anything' @@ -140,6 +142,7 @@ complete -c x -n "__fish_x_using_subcommand b" -l set -d 'override options in bo complete -c x -n "__fish_x_using_subcommand b" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand b" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x -n "__fish_x_using_subcommand b" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand b" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand b" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand b" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand b" -l dry-run -d 'dry run; don\'t build anything' @@ -177,6 +180,7 @@ complete -c x -n "__fish_x_using_subcommand check" -l ci -d 'Make bootstrap to b complete -c x -n "__fish_x_using_subcommand check" -l all-targets -d 'Check all targets' complete -c x -n "__fish_x_using_subcommand check" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x -n "__fish_x_using_subcommand check" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand check" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand check" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand check" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand check" -l dry-run -d 'dry run; don\'t build anything' @@ -214,6 +218,7 @@ complete -c x -n "__fish_x_using_subcommand c" -l ci -d 'Make bootstrap to behav complete -c x -n "__fish_x_using_subcommand c" -l all-targets -d 'Check all targets' complete -c x -n "__fish_x_using_subcommand c" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x -n "__fish_x_using_subcommand c" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand c" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand c" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand c" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand c" -l dry-run -d 'dry run; don\'t build anything' @@ -256,6 +261,7 @@ complete -c x -n "__fish_x_using_subcommand clippy" -l fix complete -c x -n "__fish_x_using_subcommand clippy" -l allow-dirty complete -c x -n "__fish_x_using_subcommand clippy" -l allow-staged complete -c x -n "__fish_x_using_subcommand clippy" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand clippy" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand clippy" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand clippy" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand clippy" -l dry-run -d 'dry run; don\'t build anything' @@ -291,6 +297,7 @@ complete -c x -n "__fish_x_using_subcommand fix" -l reproducible-artifact -d 'Ad complete -c x -n "__fish_x_using_subcommand fix" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand fix" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand fix" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand fix" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand fix" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand fix" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand fix" -l dry-run -d 'dry run; don\'t build anything' @@ -328,6 +335,7 @@ complete -c x -n "__fish_x_using_subcommand fmt" -l ci -d 'Make bootstrap to beh complete -c x -n "__fish_x_using_subcommand fmt" -l check -d 'check formatting instead of applying' complete -c x -n "__fish_x_using_subcommand fmt" -l all -d 'apply to all appropriate files, not just those that have been modified' complete -c x -n "__fish_x_using_subcommand fmt" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand fmt" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand fmt" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand fmt" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand fmt" -l dry-run -d 'dry run; don\'t build anything' @@ -365,6 +373,7 @@ complete -c x -n "__fish_x_using_subcommand doc" -l ci -d 'Make bootstrap to beh complete -c x -n "__fish_x_using_subcommand doc" -l open -d 'open the docs in a browser' complete -c x -n "__fish_x_using_subcommand doc" -l json -d 'render the documentation in JSON format in addition to the usual HTML format' complete -c x -n "__fish_x_using_subcommand doc" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand doc" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand doc" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand doc" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand doc" -l dry-run -d 'dry run; don\'t build anything' @@ -402,6 +411,7 @@ complete -c x -n "__fish_x_using_subcommand d" -l ci -d 'Make bootstrap to behav complete -c x -n "__fish_x_using_subcommand d" -l open -d 'open the docs in a browser' complete -c x -n "__fish_x_using_subcommand d" -l json -d 'render the documentation in JSON format in addition to the usual HTML format' complete -c x -n "__fish_x_using_subcommand d" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand d" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand d" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand d" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand d" -l dry-run -d 'dry run; don\'t build anything' @@ -420,6 +430,7 @@ complete -c x -n "__fish_x_using_subcommand test" -l extra-checks -d 'comma-sepa complete -c x -n "__fish_x_using_subcommand test" -l compare-mode -d 'mode describing what file the actual ui output will be compared to' -r complete -c x -n "__fish_x_using_subcommand test" -l pass -d 'force {check,build,run}-pass tests to this mode' -r complete -c x -n "__fish_x_using_subcommand test" -l run -d 'whether to execute run-* tests' -r +complete -c x -n "__fish_x_using_subcommand test" -l verbose-run-make-subprocess-output -d 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand test" -l test-codegen-backend -d 'Use a different codegen backend when running tests' -r complete -c x -n "__fish_x_using_subcommand test" -l config -d 'TOML configuration file for build' -r -F complete -c x -n "__fish_x_using_subcommand test" -l build-dir -d 'Build directory, overrides `build.build-dir` in `bootstrap.toml`' -r -f -a "(__fish_complete_directories)" @@ -455,6 +466,7 @@ complete -c x -n "__fish_x_using_subcommand test" -l no-capture -d 'don\'t captu complete -c x -n "__fish_x_using_subcommand test" -l bypass-ignore-backends -d 'Ignore `//@ ignore-backends` directives' complete -c x -n "__fish_x_using_subcommand test" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x -n "__fish_x_using_subcommand test" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand test" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand test" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand test" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand test" -l dry-run -d 'dry run; don\'t build anything' @@ -473,6 +485,7 @@ complete -c x -n "__fish_x_using_subcommand t" -l extra-checks -d 'comma-separat complete -c x -n "__fish_x_using_subcommand t" -l compare-mode -d 'mode describing what file the actual ui output will be compared to' -r complete -c x -n "__fish_x_using_subcommand t" -l pass -d 'force {check,build,run}-pass tests to this mode' -r complete -c x -n "__fish_x_using_subcommand t" -l run -d 'whether to execute run-* tests' -r +complete -c x -n "__fish_x_using_subcommand t" -l verbose-run-make-subprocess-output -d 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand t" -l test-codegen-backend -d 'Use a different codegen backend when running tests' -r complete -c x -n "__fish_x_using_subcommand t" -l config -d 'TOML configuration file for build' -r -F complete -c x -n "__fish_x_using_subcommand t" -l build-dir -d 'Build directory, overrides `build.build-dir` in `bootstrap.toml`' -r -f -a "(__fish_complete_directories)" @@ -508,6 +521,7 @@ complete -c x -n "__fish_x_using_subcommand t" -l no-capture -d 'don\'t capture complete -c x -n "__fish_x_using_subcommand t" -l bypass-ignore-backends -d 'Ignore `//@ ignore-backends` directives' complete -c x -n "__fish_x_using_subcommand t" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x -n "__fish_x_using_subcommand t" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand t" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand t" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand t" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand t" -l dry-run -d 'dry run; don\'t build anything' @@ -549,6 +563,7 @@ complete -c x -n "__fish_x_using_subcommand miri" -l doc -d 'Only run doc tests' complete -c x -n "__fish_x_using_subcommand miri" -l tests -d 'Only run unit and integration tests' complete -c x -n "__fish_x_using_subcommand miri" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x -n "__fish_x_using_subcommand miri" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand miri" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand miri" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand miri" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand miri" -l dry-run -d 'dry run; don\'t build anything' @@ -585,6 +600,7 @@ complete -c x -n "__fish_x_using_subcommand bench" -l reproducible-artifact -d ' complete -c x -n "__fish_x_using_subcommand bench" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand bench" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand bench" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand bench" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand bench" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand bench" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand bench" -l dry-run -d 'dry run; don\'t build anything' @@ -621,6 +637,7 @@ complete -c x -n "__fish_x_using_subcommand clean" -l set -d 'override options i complete -c x -n "__fish_x_using_subcommand clean" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand clean" -l all -d 'Clean the entire build directory (not used by default)' complete -c x -n "__fish_x_using_subcommand clean" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand clean" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand clean" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand clean" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand clean" -l dry-run -d 'dry run; don\'t build anything' @@ -656,6 +673,7 @@ complete -c x -n "__fish_x_using_subcommand dist" -l reproducible-artifact -d 'A complete -c x -n "__fish_x_using_subcommand dist" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand dist" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand dist" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand dist" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand dist" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand dist" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand dist" -l dry-run -d 'dry run; don\'t build anything' @@ -691,6 +709,7 @@ complete -c x -n "__fish_x_using_subcommand install" -l reproducible-artifact -d complete -c x -n "__fish_x_using_subcommand install" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand install" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand install" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand install" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand install" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand install" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand install" -l dry-run -d 'dry run; don\'t build anything' @@ -727,6 +746,7 @@ complete -c x -n "__fish_x_using_subcommand run" -l reproducible-artifact -d 'Ad complete -c x -n "__fish_x_using_subcommand run" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand run" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand run" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand run" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand run" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand run" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand run" -l dry-run -d 'dry run; don\'t build anything' @@ -763,6 +783,7 @@ complete -c x -n "__fish_x_using_subcommand r" -l reproducible-artifact -d 'Addi complete -c x -n "__fish_x_using_subcommand r" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand r" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand r" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand r" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand r" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand r" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand r" -l dry-run -d 'dry run; don\'t build anything' @@ -798,6 +819,7 @@ complete -c x -n "__fish_x_using_subcommand setup" -l reproducible-artifact -d ' complete -c x -n "__fish_x_using_subcommand setup" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand setup" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand setup" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand setup" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand setup" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand setup" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand setup" -l dry-run -d 'dry run; don\'t build anything' @@ -835,6 +857,7 @@ complete -c x -n "__fish_x_using_subcommand vendor" -l set -d 'override options complete -c x -n "__fish_x_using_subcommand vendor" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand vendor" -l versioned-dirs -d 'Always include version in subdir name' complete -c x -n "__fish_x_using_subcommand vendor" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand vendor" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand vendor" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand vendor" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand vendor" -l dry-run -d 'dry run; don\'t build anything' @@ -870,6 +893,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l dry-run -d 'dry run; don\'t build anything' @@ -913,6 +937,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_fro complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l dry-run -d 'dry run; don\'t build anything' @@ -951,6 +976,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_fro complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from samply" -l dry-run -d 'dry run; don\'t build anything' @@ -989,6 +1015,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_fro complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l dry-run -d 'dry run; don\'t build anything' @@ -1027,6 +1054,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_fro complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l dry-run -d 'dry run; don\'t build anything' @@ -1062,6 +1090,7 @@ complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_fro complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -l set -d 'override options in bootstrap.toml' -r -f complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -s q -l quiet -d 'use quiet output' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -s i -l incremental -d 'use incremental compilation' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x -n "__fish_x_using_subcommand perf; and __fish_seen_subcommand_from compare" -l dry-run -d 'dry run; don\'t build anything' diff --git a/src/etc/completions/x.ps1 b/src/etc/completions/x.ps1 index d4bf45f73836..e03994f4acaf 100644 --- a/src/etc/completions/x.ps1 +++ b/src/etc/completions/x.ps1 @@ -46,6 +46,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -110,6 +112,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -153,6 +157,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -197,6 +203,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -241,6 +249,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -290,6 +300,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--allow-staged', '--allow-staged', [CompletionResultType]::ParameterName, 'allow-staged') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -332,6 +344,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -376,6 +390,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--all', '--all', [CompletionResultType]::ParameterName, 'apply to all appropriate files, not just those that have been modified') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -420,6 +436,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--json', '--json', [CompletionResultType]::ParameterName, 'render the documentation in JSON format in addition to the usual HTML format') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -464,6 +482,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--json', '--json', [CompletionResultType]::ParameterName, 'render the documentation in JSON format in addition to the usual HTML format') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -487,6 +507,7 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--compare-mode', '--compare-mode', [CompletionResultType]::ParameterName, 'mode describing what file the actual ui output will be compared to') [CompletionResult]::new('--pass', '--pass', [CompletionResultType]::ParameterName, 'force {check,build,run}-pass tests to this mode') [CompletionResult]::new('--run', '--run', [CompletionResultType]::ParameterName, 'whether to execute run-* tests') + [CompletionResult]::new('--verbose-run-make-subprocess-output', '--verbose-run-make-subprocess-output', [CompletionResultType]::ParameterName, 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)') [CompletionResult]::new('--test-codegen-backend', '--test-codegen-backend', [CompletionResultType]::ParameterName, 'Use a different codegen backend when running tests') [CompletionResult]::new('--config', '--config', [CompletionResultType]::ParameterName, 'TOML configuration file for build') [CompletionResult]::new('--build-dir', '--build-dir', [CompletionResultType]::ParameterName, 'Build directory, overrides `build.build-dir` in `bootstrap.toml`') @@ -524,6 +545,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -547,6 +570,7 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--compare-mode', '--compare-mode', [CompletionResultType]::ParameterName, 'mode describing what file the actual ui output will be compared to') [CompletionResult]::new('--pass', '--pass', [CompletionResultType]::ParameterName, 'force {check,build,run}-pass tests to this mode') [CompletionResult]::new('--run', '--run', [CompletionResultType]::ParameterName, 'whether to execute run-* tests') + [CompletionResult]::new('--verbose-run-make-subprocess-output', '--verbose-run-make-subprocess-output', [CompletionResultType]::ParameterName, 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)') [CompletionResult]::new('--test-codegen-backend', '--test-codegen-backend', [CompletionResultType]::ParameterName, 'Use a different codegen backend when running tests') [CompletionResult]::new('--config', '--config', [CompletionResultType]::ParameterName, 'TOML configuration file for build') [CompletionResult]::new('--build-dir', '--build-dir', [CompletionResultType]::ParameterName, 'Build directory, overrides `build.build-dir` in `bootstrap.toml`') @@ -584,6 +608,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -632,6 +658,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -675,6 +703,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -718,6 +748,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--all', '--all', [CompletionResultType]::ParameterName, 'Clean the entire build directory (not used by default)') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -760,6 +792,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -802,6 +836,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -845,6 +881,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -888,6 +926,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -930,6 +970,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -974,6 +1016,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--versioned-dirs', '--versioned-dirs', [CompletionResultType]::ParameterName, 'Always include version in subdir name') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1016,6 +1060,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1066,6 +1112,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1111,6 +1159,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1156,6 +1206,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1201,6 +1253,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1243,6 +1297,8 @@ Register-ArgumentCompleter -Native -CommandName 'x' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') diff --git a/src/etc/completions/x.py.fish b/src/etc/completions/x.py.fish index 0dbbe1ea43ef..8e3bec4fdd92 100644 --- a/src/etc/completions/x.py.fish +++ b/src/etc/completions/x.py.fish @@ -1,6 +1,6 @@ # Print an optspec for argparse to handle cmd's options that are independent of any subcommand. function __fish_x.py_global_optspecs - string join \n v/verbose i/incremental config= build-dir= build= host= target= exclude= skip= include-default-paths rustc-error-format= on-fail= dry-run dump-bootstrap-shims stage= keep-stage= keep-stage-std= src= j/jobs= warnings= json-output compile-time-deps color= bypass-bootstrap-lock rust-profile-generate= rust-profile-use= llvm-profile-use= llvm-profile-generate enable-bolt-settings skip-stage0-validation reproducible-artifact= set= ci= skip-std-check-if-no-download-rustc h/help + string join \n v/verbose q/quiet i/incremental config= build-dir= build= host= target= exclude= skip= include-default-paths rustc-error-format= on-fail= dry-run dump-bootstrap-shims stage= keep-stage= keep-stage-std= src= j/jobs= warnings= json-output compile-time-deps color= bypass-bootstrap-lock rust-profile-generate= rust-profile-use= llvm-profile-use= llvm-profile-generate enable-bolt-settings skip-stage0-validation reproducible-artifact= set= ci= skip-std-check-if-no-download-rustc h/help end function __fish_x.py_needs_command @@ -47,6 +47,7 @@ complete -c x.py -n "__fish_x.py_needs_command" -l reproducible-artifact -d 'Add complete -c x.py -n "__fish_x.py_needs_command" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_needs_command" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_needs_command" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_needs_command" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_needs_command" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_needs_command" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_needs_command" -l dry-run -d 'dry run; don\'t build anything' @@ -104,6 +105,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand build" -l set -d 'override opt complete -c x.py -n "__fish_x.py_using_subcommand build" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand build" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x.py -n "__fish_x.py_using_subcommand build" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand build" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand build" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand build" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand build" -l dry-run -d 'dry run; don\'t build anything' @@ -140,6 +142,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand b" -l set -d 'override options complete -c x.py -n "__fish_x.py_using_subcommand b" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand b" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x.py -n "__fish_x.py_using_subcommand b" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand b" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand b" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand b" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand b" -l dry-run -d 'dry run; don\'t build anything' @@ -177,6 +180,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand check" -l ci -d 'Make bootstra complete -c x.py -n "__fish_x.py_using_subcommand check" -l all-targets -d 'Check all targets' complete -c x.py -n "__fish_x.py_using_subcommand check" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x.py -n "__fish_x.py_using_subcommand check" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand check" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand check" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand check" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand check" -l dry-run -d 'dry run; don\'t build anything' @@ -214,6 +218,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand c" -l ci -d 'Make bootstrap to complete -c x.py -n "__fish_x.py_using_subcommand c" -l all-targets -d 'Check all targets' complete -c x.py -n "__fish_x.py_using_subcommand c" -l timings -d 'Pass `--timings` to Cargo to get crate build timings' complete -c x.py -n "__fish_x.py_using_subcommand c" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand c" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand c" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand c" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand c" -l dry-run -d 'dry run; don\'t build anything' @@ -256,6 +261,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand clippy" -l fix complete -c x.py -n "__fish_x.py_using_subcommand clippy" -l allow-dirty complete -c x.py -n "__fish_x.py_using_subcommand clippy" -l allow-staged complete -c x.py -n "__fish_x.py_using_subcommand clippy" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand clippy" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand clippy" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand clippy" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand clippy" -l dry-run -d 'dry run; don\'t build anything' @@ -291,6 +297,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand fix" -l reproducible-artifact complete -c x.py -n "__fish_x.py_using_subcommand fix" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand fix" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand fix" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand fix" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand fix" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand fix" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand fix" -l dry-run -d 'dry run; don\'t build anything' @@ -328,6 +335,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand fmt" -l ci -d 'Make bootstrap complete -c x.py -n "__fish_x.py_using_subcommand fmt" -l check -d 'check formatting instead of applying' complete -c x.py -n "__fish_x.py_using_subcommand fmt" -l all -d 'apply to all appropriate files, not just those that have been modified' complete -c x.py -n "__fish_x.py_using_subcommand fmt" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand fmt" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand fmt" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand fmt" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand fmt" -l dry-run -d 'dry run; don\'t build anything' @@ -365,6 +373,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand doc" -l ci -d 'Make bootstrap complete -c x.py -n "__fish_x.py_using_subcommand doc" -l open -d 'open the docs in a browser' complete -c x.py -n "__fish_x.py_using_subcommand doc" -l json -d 'render the documentation in JSON format in addition to the usual HTML format' complete -c x.py -n "__fish_x.py_using_subcommand doc" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand doc" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand doc" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand doc" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand doc" -l dry-run -d 'dry run; don\'t build anything' @@ -402,6 +411,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand d" -l ci -d 'Make bootstrap to complete -c x.py -n "__fish_x.py_using_subcommand d" -l open -d 'open the docs in a browser' complete -c x.py -n "__fish_x.py_using_subcommand d" -l json -d 'render the documentation in JSON format in addition to the usual HTML format' complete -c x.py -n "__fish_x.py_using_subcommand d" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand d" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand d" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand d" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand d" -l dry-run -d 'dry run; don\'t build anything' @@ -420,6 +430,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand test" -l extra-checks -d 'comm complete -c x.py -n "__fish_x.py_using_subcommand test" -l compare-mode -d 'mode describing what file the actual ui output will be compared to' -r complete -c x.py -n "__fish_x.py_using_subcommand test" -l pass -d 'force {check,build,run}-pass tests to this mode' -r complete -c x.py -n "__fish_x.py_using_subcommand test" -l run -d 'whether to execute run-* tests' -r +complete -c x.py -n "__fish_x.py_using_subcommand test" -l verbose-run-make-subprocess-output -d 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand test" -l test-codegen-backend -d 'Use a different codegen backend when running tests' -r complete -c x.py -n "__fish_x.py_using_subcommand test" -l config -d 'TOML configuration file for build' -r -F complete -c x.py -n "__fish_x.py_using_subcommand test" -l build-dir -d 'Build directory, overrides `build.build-dir` in `bootstrap.toml`' -r -f -a "(__fish_complete_directories)" @@ -455,6 +466,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand test" -l no-capture -d 'don\'t complete -c x.py -n "__fish_x.py_using_subcommand test" -l bypass-ignore-backends -d 'Ignore `//@ ignore-backends` directives' complete -c x.py -n "__fish_x.py_using_subcommand test" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x.py -n "__fish_x.py_using_subcommand test" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand test" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand test" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand test" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand test" -l dry-run -d 'dry run; don\'t build anything' @@ -473,6 +485,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand t" -l extra-checks -d 'comma-s complete -c x.py -n "__fish_x.py_using_subcommand t" -l compare-mode -d 'mode describing what file the actual ui output will be compared to' -r complete -c x.py -n "__fish_x.py_using_subcommand t" -l pass -d 'force {check,build,run}-pass tests to this mode' -r complete -c x.py -n "__fish_x.py_using_subcommand t" -l run -d 'whether to execute run-* tests' -r +complete -c x.py -n "__fish_x.py_using_subcommand t" -l verbose-run-make-subprocess-output -d 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand t" -l test-codegen-backend -d 'Use a different codegen backend when running tests' -r complete -c x.py -n "__fish_x.py_using_subcommand t" -l config -d 'TOML configuration file for build' -r -F complete -c x.py -n "__fish_x.py_using_subcommand t" -l build-dir -d 'Build directory, overrides `build.build-dir` in `bootstrap.toml`' -r -f -a "(__fish_complete_directories)" @@ -508,6 +521,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand t" -l no-capture -d 'don\'t ca complete -c x.py -n "__fish_x.py_using_subcommand t" -l bypass-ignore-backends -d 'Ignore `//@ ignore-backends` directives' complete -c x.py -n "__fish_x.py_using_subcommand t" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x.py -n "__fish_x.py_using_subcommand t" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand t" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand t" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand t" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand t" -l dry-run -d 'dry run; don\'t build anything' @@ -549,6 +563,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand miri" -l doc -d 'Only run doc complete -c x.py -n "__fish_x.py_using_subcommand miri" -l tests -d 'Only run unit and integration tests' complete -c x.py -n "__fish_x.py_using_subcommand miri" -l no-doc -d 'Deprecated. Use `--all-targets` or `--tests` instead' complete -c x.py -n "__fish_x.py_using_subcommand miri" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand miri" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand miri" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand miri" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand miri" -l dry-run -d 'dry run; don\'t build anything' @@ -585,6 +600,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand bench" -l reproducible-artifac complete -c x.py -n "__fish_x.py_using_subcommand bench" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand bench" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand bench" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand bench" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand bench" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand bench" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand bench" -l dry-run -d 'dry run; don\'t build anything' @@ -621,6 +637,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand clean" -l set -d 'override opt complete -c x.py -n "__fish_x.py_using_subcommand clean" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand clean" -l all -d 'Clean the entire build directory (not used by default)' complete -c x.py -n "__fish_x.py_using_subcommand clean" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand clean" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand clean" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand clean" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand clean" -l dry-run -d 'dry run; don\'t build anything' @@ -656,6 +673,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand dist" -l reproducible-artifact complete -c x.py -n "__fish_x.py_using_subcommand dist" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand dist" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand dist" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand dist" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand dist" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand dist" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand dist" -l dry-run -d 'dry run; don\'t build anything' @@ -691,6 +709,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand install" -l reproducible-artif complete -c x.py -n "__fish_x.py_using_subcommand install" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand install" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand install" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand install" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand install" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand install" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand install" -l dry-run -d 'dry run; don\'t build anything' @@ -727,6 +746,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand run" -l reproducible-artifact complete -c x.py -n "__fish_x.py_using_subcommand run" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand run" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand run" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand run" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand run" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand run" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand run" -l dry-run -d 'dry run; don\'t build anything' @@ -763,6 +783,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand r" -l reproducible-artifact -d complete -c x.py -n "__fish_x.py_using_subcommand r" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand r" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand r" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand r" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand r" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand r" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand r" -l dry-run -d 'dry run; don\'t build anything' @@ -798,6 +819,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand setup" -l reproducible-artifac complete -c x.py -n "__fish_x.py_using_subcommand setup" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand setup" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand setup" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand setup" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand setup" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand setup" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand setup" -l dry-run -d 'dry run; don\'t build anything' @@ -835,6 +857,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand vendor" -l set -d 'override op complete -c x.py -n "__fish_x.py_using_subcommand vendor" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand vendor" -l versioned-dirs -d 'Always include version in subdir name' complete -c x.py -n "__fish_x.py_using_subcommand vendor" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand vendor" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand vendor" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand vendor" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand vendor" -l dry-run -d 'dry run; don\'t build anything' @@ -870,6 +893,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subc complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and not __fish_seen_subcommand_from eprintln samply cachegrind benchmark compare" -l dry-run -d 'dry run; don\'t build anything' @@ -913,6 +937,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcomma complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from eprintln" -l dry-run -d 'dry run; don\'t build anything' @@ -951,6 +976,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcomma complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from samply" -l dry-run -d 'dry run; don\'t build anything' @@ -989,6 +1015,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcomma complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from cachegrind" -l dry-run -d 'dry run; don\'t build anything' @@ -1027,6 +1054,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcomma complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from benchmark" -l dry-run -d 'dry run; don\'t build anything' @@ -1062,6 +1090,7 @@ complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcomma complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -l set -d 'override options in bootstrap.toml' -r -f complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -l ci -d 'Make bootstrap to behave as it\'s running on the CI environment or not' -r -f -a "{true\t'',false\t''}" complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -s v -l verbose -d 'use verbose output (-vv for very verbose)' +complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -s q -l quiet -d 'use quiet output' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -s i -l incremental -d 'use incremental compilation' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -l include-default-paths -d 'include default paths in addition to the provided ones' complete -c x.py -n "__fish_x.py_using_subcommand perf; and __fish_seen_subcommand_from compare" -l dry-run -d 'dry run; don\'t build anything' diff --git a/src/etc/completions/x.py.ps1 b/src/etc/completions/x.py.ps1 index b4e3b8c580a4..edcc5d0bb5ef 100644 --- a/src/etc/completions/x.py.ps1 +++ b/src/etc/completions/x.py.ps1 @@ -46,6 +46,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -110,6 +112,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -153,6 +157,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -197,6 +203,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -241,6 +249,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--timings', '--timings', [CompletionResultType]::ParameterName, 'Pass `--timings` to Cargo to get crate build timings') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -290,6 +300,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--allow-staged', '--allow-staged', [CompletionResultType]::ParameterName, 'allow-staged') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -332,6 +344,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -376,6 +390,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--all', '--all', [CompletionResultType]::ParameterName, 'apply to all appropriate files, not just those that have been modified') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -420,6 +436,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--json', '--json', [CompletionResultType]::ParameterName, 'render the documentation in JSON format in addition to the usual HTML format') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -464,6 +482,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--json', '--json', [CompletionResultType]::ParameterName, 'render the documentation in JSON format in addition to the usual HTML format') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -487,6 +507,7 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--compare-mode', '--compare-mode', [CompletionResultType]::ParameterName, 'mode describing what file the actual ui output will be compared to') [CompletionResult]::new('--pass', '--pass', [CompletionResultType]::ParameterName, 'force {check,build,run}-pass tests to this mode') [CompletionResult]::new('--run', '--run', [CompletionResultType]::ParameterName, 'whether to execute run-* tests') + [CompletionResult]::new('--verbose-run-make-subprocess-output', '--verbose-run-make-subprocess-output', [CompletionResultType]::ParameterName, 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)') [CompletionResult]::new('--test-codegen-backend', '--test-codegen-backend', [CompletionResultType]::ParameterName, 'Use a different codegen backend when running tests') [CompletionResult]::new('--config', '--config', [CompletionResultType]::ParameterName, 'TOML configuration file for build') [CompletionResult]::new('--build-dir', '--build-dir', [CompletionResultType]::ParameterName, 'Build directory, overrides `build.build-dir` in `bootstrap.toml`') @@ -524,6 +545,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -547,6 +570,7 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--compare-mode', '--compare-mode', [CompletionResultType]::ParameterName, 'mode describing what file the actual ui output will be compared to') [CompletionResult]::new('--pass', '--pass', [CompletionResultType]::ParameterName, 'force {check,build,run}-pass tests to this mode') [CompletionResult]::new('--run', '--run', [CompletionResultType]::ParameterName, 'whether to execute run-* tests') + [CompletionResult]::new('--verbose-run-make-subprocess-output', '--verbose-run-make-subprocess-output', [CompletionResultType]::ParameterName, 'whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)') [CompletionResult]::new('--test-codegen-backend', '--test-codegen-backend', [CompletionResultType]::ParameterName, 'Use a different codegen backend when running tests') [CompletionResult]::new('--config', '--config', [CompletionResultType]::ParameterName, 'TOML configuration file for build') [CompletionResult]::new('--build-dir', '--build-dir', [CompletionResultType]::ParameterName, 'Build directory, overrides `build.build-dir` in `bootstrap.toml`') @@ -584,6 +608,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -632,6 +658,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--no-doc', '--no-doc', [CompletionResultType]::ParameterName, 'Deprecated. Use `--all-targets` or `--tests` instead') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -675,6 +703,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -718,6 +748,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--all', '--all', [CompletionResultType]::ParameterName, 'Clean the entire build directory (not used by default)') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -760,6 +792,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -802,6 +836,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -845,6 +881,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -888,6 +926,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -930,6 +970,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -974,6 +1016,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--versioned-dirs', '--versioned-dirs', [CompletionResultType]::ParameterName, 'Always include version in subdir name') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1016,6 +1060,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1066,6 +1112,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1111,6 +1159,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1156,6 +1206,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1201,6 +1253,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') @@ -1243,6 +1297,8 @@ Register-ArgumentCompleter -Native -CommandName 'x.py' -ScriptBlock { [CompletionResult]::new('--ci', '--ci', [CompletionResultType]::ParameterName, 'Make bootstrap to behave as it''s running on the CI environment or not') [CompletionResult]::new('-v', '-v', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') [CompletionResult]::new('--verbose', '--verbose', [CompletionResultType]::ParameterName, 'use verbose output (-vv for very verbose)') + [CompletionResult]::new('-q', '-q', [CompletionResultType]::ParameterName, 'use quiet output') + [CompletionResult]::new('--quiet', '--quiet', [CompletionResultType]::ParameterName, 'use quiet output') [CompletionResult]::new('-i', '-i', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--incremental', '--incremental', [CompletionResultType]::ParameterName, 'use incremental compilation') [CompletionResult]::new('--include-default-paths', '--include-default-paths', [CompletionResultType]::ParameterName, 'include default paths in addition to the provided ones') diff --git a/src/etc/completions/x.py.sh b/src/etc/completions/x.py.sh index 8a7aee2a091c..f32a078b2094 100644 --- a/src/etc/completions/x.py.sh +++ b/src/etc/completions/x.py.sh @@ -97,7 +97,7 @@ _x.py() { case "${cmd}" in x.py) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... build b check c clippy fix fmt doc d test t miri bench clean dist install run r setup vendor perf" + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... build b check c clippy fix fmt doc d test t miri bench clean dist install run r setup vendor perf" if [[ ${cur} == -* || ${COMP_CWORD} -eq 1 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -283,7 +283,7 @@ _x.py() { return 0 ;; x.py__bench) - opts="-v -i -j -h --test-args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --test-args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -473,7 +473,7 @@ _x.py() { return 0 ;; x.py__build) - opts="-v -i -j -h --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -659,7 +659,7 @@ _x.py() { return 0 ;; x.py__build) - opts="-v -i -j -h --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -845,7 +845,7 @@ _x.py() { return 0 ;; x.py__check) - opts="-v -i -j -h --all-targets --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all-targets --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1031,7 +1031,7 @@ _x.py() { return 0 ;; x.py__check) - opts="-v -i -j -h --all-targets --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all-targets --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1217,7 +1217,7 @@ _x.py() { return 0 ;; x.py__clean) - opts="-v -i -j -h --all --stage --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all --stage --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1400,7 +1400,7 @@ _x.py() { return 0 ;; x.py__clippy) - opts="-A -D -W -F -v -i -j -h --fix --allow-dirty --allow-staged --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-A -D -W -F -v -q -i -j -h --fix --allow-dirty --allow-staged --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1602,7 +1602,7 @@ _x.py() { return 0 ;; x.py__dist) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1788,7 +1788,7 @@ _x.py() { return 0 ;; x.py__doc) - opts="-v -i -j -h --open --json --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --open --json --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1974,7 +1974,7 @@ _x.py() { return 0 ;; x.py__doc) - opts="-v -i -j -h --open --json --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --open --json --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2160,7 +2160,7 @@ _x.py() { return 0 ;; x.py__fix) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2346,7 +2346,7 @@ _x.py() { return 0 ;; x.py__fmt) - opts="-v -i -j -h --check --all --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --check --all --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2532,7 +2532,7 @@ _x.py() { return 0 ;; x.py__install) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2718,7 +2718,7 @@ _x.py() { return 0 ;; x.py__miri) - opts="-v -i -j -h --no-fail-fast --test-args --all-targets --doc --tests --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --all-targets --doc --tests --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2908,7 +2908,7 @@ _x.py() { return 0 ;; x.py__perf) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... eprintln samply cachegrind benchmark compare" + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... eprintln samply cachegrind benchmark compare" if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3094,7 +3094,7 @@ _x.py() { return 0 ;; x.py__perf__benchmark) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3292,7 +3292,7 @@ _x.py() { return 0 ;; x.py__perf__cachegrind) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3490,7 +3490,7 @@ _x.py() { return 0 ;; x.py__perf__compare) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3676,7 +3676,7 @@ _x.py() { return 0 ;; x.py__perf__eprintln) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3874,7 +3874,7 @@ _x.py() { return 0 ;; x.py__perf__samply) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4072,7 +4072,7 @@ _x.py() { return 0 ;; x.py__run) - opts="-v -i -j -h --args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4262,7 +4262,7 @@ _x.py() { return 0 ;; x.py__run) - opts="-v -i -j -h --args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4452,7 +4452,7 @@ _x.py() { return 0 ;; x.py__setup) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [|hook|editor|link] [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [|hook|editor|link] [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4638,7 +4638,7 @@ _x.py() { return 0 ;; x.py__test) - opts="-v -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --verbose-run-make-subprocess-output --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4668,6 +4668,10 @@ _x.py() { COMPREPLY=($(compgen -f "${cur}")) return 0 ;; + --verbose-run-make-subprocess-output) + COMPREPLY=($(compgen -W "true false" -- "${cur}")) + return 0 + ;; --test-codegen-backend) COMPREPLY=($(compgen -f "${cur}")) return 0 @@ -4852,7 +4856,7 @@ _x.py() { return 0 ;; x.py__test) - opts="-v -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --verbose-run-make-subprocess-output --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4882,6 +4886,10 @@ _x.py() { COMPREPLY=($(compgen -f "${cur}")) return 0 ;; + --verbose-run-make-subprocess-output) + COMPREPLY=($(compgen -W "true false" -- "${cur}")) + return 0 + ;; --test-codegen-backend) COMPREPLY=($(compgen -f "${cur}")) return 0 @@ -5066,7 +5074,7 @@ _x.py() { return 0 ;; x.py__vendor) - opts="-v -i -j -h --sync --versioned-dirs --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --sync --versioned-dirs --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 diff --git a/src/etc/completions/x.py.zsh b/src/etc/completions/x.py.zsh index e24da218a05d..16fca305719c 100644 --- a/src/etc/completions/x.py.zsh +++ b/src/etc/completions/x.py.zsh @@ -38,8 +38,10 @@ _x.py() { '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -91,8 +93,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -136,8 +140,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -182,8 +188,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all-targets[Check all targets]' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -228,8 +236,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all-targets[Check all targets]' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -279,8 +289,10 @@ _arguments "${_arguments_options[@]}" : \ '--fix[]' \ '--allow-dirty[]' \ '--allow-staged[]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -323,8 +335,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -369,8 +383,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--check[check formatting instead of applying]' \ '--all[apply to all appropriate files, not just those that have been modified]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -415,8 +431,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--open[open the docs in a browser]' \ '--json[render the documentation in JSON format in addition to the usual HTML format]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -461,8 +479,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--open[open the docs in a browser]' \ '--json[render the documentation in JSON format in addition to the usual HTML format]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -488,6 +508,7 @@ _arguments "${_arguments_options[@]}" : \ '--compare-mode=[mode describing what file the actual ui output will be compared to]:COMPARE MODE:_default' \ '--pass=[force {check,build,run}-pass tests to this mode]:check | build | run:_default' \ '--run=[whether to execute run-* tests]:auto | always | never:_default' \ +'--verbose-run-make-subprocess-output=[whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)]' \ '--test-codegen-backend=[Use a different codegen backend when running tests]:TEST_CODEGEN_BACKEND:_default' \ '--config=[TOML configuration file for build]:FILE:_files' \ '--build-dir=[Build directory, overrides \`build.build-dir\` in \`bootstrap.toml\`]:DIR:_files -/' \ @@ -523,8 +544,10 @@ _arguments "${_arguments_options[@]}" : \ '--no-capture[don'\''t capture stdout/stderr of tests]' \ '--bypass-ignore-backends[Ignore \`//@ ignore-backends\` directives]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -550,6 +573,7 @@ _arguments "${_arguments_options[@]}" : \ '--compare-mode=[mode describing what file the actual ui output will be compared to]:COMPARE MODE:_default' \ '--pass=[force {check,build,run}-pass tests to this mode]:check | build | run:_default' \ '--run=[whether to execute run-* tests]:auto | always | never:_default' \ +'--verbose-run-make-subprocess-output=[whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)]' \ '--test-codegen-backend=[Use a different codegen backend when running tests]:TEST_CODEGEN_BACKEND:_default' \ '--config=[TOML configuration file for build]:FILE:_files' \ '--build-dir=[Build directory, overrides \`build.build-dir\` in \`bootstrap.toml\`]:DIR:_files -/' \ @@ -585,8 +609,10 @@ _arguments "${_arguments_options[@]}" : \ '--no-capture[don'\''t capture stdout/stderr of tests]' \ '--bypass-ignore-backends[Ignore \`//@ ignore-backends\` directives]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -635,8 +661,10 @@ _arguments "${_arguments_options[@]}" : \ '--doc[Only run doc tests]' \ '--tests[Only run unit and integration tests]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -680,8 +708,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -725,8 +755,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all[Clean the entire build directory (not used by default)]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -769,8 +801,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -813,8 +847,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -858,8 +894,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -903,8 +941,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -947,8 +987,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -994,8 +1036,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--versioned-dirs[Always include version in subdir name]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1038,8 +1082,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1094,8 +1140,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1141,8 +1189,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1188,8 +1238,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1235,8 +1287,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1280,8 +1334,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ diff --git a/src/etc/completions/x.sh b/src/etc/completions/x.sh index a4b44b73f47a..27b2a45efd53 100644 --- a/src/etc/completions/x.sh +++ b/src/etc/completions/x.sh @@ -97,7 +97,7 @@ _x() { case "${cmd}" in x) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... build b check c clippy fix fmt doc d test t miri bench clean dist install run r setup vendor perf" + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... build b check c clippy fix fmt doc d test t miri bench clean dist install run r setup vendor perf" if [[ ${cur} == -* || ${COMP_CWORD} -eq 1 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -283,7 +283,7 @@ _x() { return 0 ;; x__bench) - opts="-v -i -j -h --test-args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --test-args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -473,7 +473,7 @@ _x() { return 0 ;; x__build) - opts="-v -i -j -h --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -659,7 +659,7 @@ _x() { return 0 ;; x__build) - opts="-v -i -j -h --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -845,7 +845,7 @@ _x() { return 0 ;; x__check) - opts="-v -i -j -h --all-targets --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all-targets --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1031,7 +1031,7 @@ _x() { return 0 ;; x__check) - opts="-v -i -j -h --all-targets --timings --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all-targets --timings --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1217,7 +1217,7 @@ _x() { return 0 ;; x__clean) - opts="-v -i -j -h --all --stage --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --all --stage --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1400,7 +1400,7 @@ _x() { return 0 ;; x__clippy) - opts="-A -D -W -F -v -i -j -h --fix --allow-dirty --allow-staged --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-A -D -W -F -v -q -i -j -h --fix --allow-dirty --allow-staged --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1602,7 +1602,7 @@ _x() { return 0 ;; x__dist) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1788,7 +1788,7 @@ _x() { return 0 ;; x__doc) - opts="-v -i -j -h --open --json --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --open --json --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -1974,7 +1974,7 @@ _x() { return 0 ;; x__doc) - opts="-v -i -j -h --open --json --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --open --json --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2160,7 +2160,7 @@ _x() { return 0 ;; x__fix) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2346,7 +2346,7 @@ _x() { return 0 ;; x__fmt) - opts="-v -i -j -h --check --all --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --check --all --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2532,7 +2532,7 @@ _x() { return 0 ;; x__install) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2718,7 +2718,7 @@ _x() { return 0 ;; x__miri) - opts="-v -i -j -h --no-fail-fast --test-args --all-targets --doc --tests --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --all-targets --doc --tests --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -2908,7 +2908,7 @@ _x() { return 0 ;; x__perf) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... eprintln samply cachegrind benchmark compare" + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]... eprintln samply cachegrind benchmark compare" if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3094,7 +3094,7 @@ _x() { return 0 ;; x__perf__benchmark) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3292,7 +3292,7 @@ _x() { return 0 ;; x__perf__cachegrind) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3490,7 +3490,7 @@ _x() { return 0 ;; x__perf__compare) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3676,7 +3676,7 @@ _x() { return 0 ;; x__perf__eprintln) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -3874,7 +3874,7 @@ _x() { return 0 ;; x__perf__samply) - opts="-v -i -j -h --include --exclude --scenarios --profiles --verbose --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --include --exclude --scenarios --profiles --verbose --quiet --incremental --config --build-dir --build --host --target --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 3 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4072,7 +4072,7 @@ _x() { return 0 ;; x__run) - opts="-v -i -j -h --args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4262,7 +4262,7 @@ _x() { return 0 ;; x__run) - opts="-v -i -j -h --args --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --args --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4452,7 +4452,7 @@ _x() { return 0 ;; x__setup) - opts="-v -i -j -h --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [|hook|editor|link] [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [|hook|editor|link] [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4638,7 +4638,7 @@ _x() { return 0 ;; x__test) - opts="-v -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --verbose-run-make-subprocess-output --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4668,6 +4668,10 @@ _x() { COMPREPLY=($(compgen -f "${cur}")) return 0 ;; + --verbose-run-make-subprocess-output) + COMPREPLY=($(compgen -W "true false" -- "${cur}")) + return 0 + ;; --test-codegen-backend) COMPREPLY=($(compgen -f "${cur}")) return 0 @@ -4852,7 +4856,7 @@ _x() { return 0 ;; x__test) - opts="-v -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --no-fail-fast --test-args --compiletest-rustc-args --all-targets --doc --tests --bless --extra-checks --force-rerun --only-modified --compare-mode --pass --run --rustfix-coverage --no-capture --verbose-run-make-subprocess-output --test-codegen-backend --bypass-ignore-backends --no-doc --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 @@ -4882,6 +4886,10 @@ _x() { COMPREPLY=($(compgen -f "${cur}")) return 0 ;; + --verbose-run-make-subprocess-output) + COMPREPLY=($(compgen -W "true false" -- "${cur}")) + return 0 + ;; --test-codegen-backend) COMPREPLY=($(compgen -f "${cur}")) return 0 @@ -5066,7 +5074,7 @@ _x() { return 0 ;; x__vendor) - opts="-v -i -j -h --sync --versioned-dirs --verbose --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." + opts="-v -q -i -j -h --sync --versioned-dirs --verbose --quiet --incremental --config --build-dir --build --host --target --exclude --skip --include-default-paths --rustc-error-format --on-fail --dry-run --dump-bootstrap-shims --stage --keep-stage --keep-stage-std --src --jobs --warnings --json-output --compile-time-deps --color --bypass-bootstrap-lock --rust-profile-generate --rust-profile-use --llvm-profile-use --llvm-profile-generate --enable-bolt-settings --skip-stage0-validation --reproducible-artifact --set --ci --skip-std-check-if-no-download-rustc --help [PATHS]... [ARGS]..." if [[ ${cur} == -* || ${COMP_CWORD} -eq 2 ]] ; then COMPREPLY=( $(compgen -W "${opts}" -- "${cur}") ) return 0 diff --git a/src/etc/completions/x.zsh b/src/etc/completions/x.zsh index 7f43781684b4..8382f900d021 100644 --- a/src/etc/completions/x.zsh +++ b/src/etc/completions/x.zsh @@ -38,8 +38,10 @@ _x() { '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -91,8 +93,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -136,8 +140,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -182,8 +188,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all-targets[Check all targets]' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -228,8 +236,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all-targets[Check all targets]' \ '--timings[Pass \`--timings\` to Cargo to get crate build timings]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -279,8 +289,10 @@ _arguments "${_arguments_options[@]}" : \ '--fix[]' \ '--allow-dirty[]' \ '--allow-staged[]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -323,8 +335,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -369,8 +383,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--check[check formatting instead of applying]' \ '--all[apply to all appropriate files, not just those that have been modified]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -415,8 +431,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--open[open the docs in a browser]' \ '--json[render the documentation in JSON format in addition to the usual HTML format]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -461,8 +479,10 @@ _arguments "${_arguments_options[@]}" : \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--open[open the docs in a browser]' \ '--json[render the documentation in JSON format in addition to the usual HTML format]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -488,6 +508,7 @@ _arguments "${_arguments_options[@]}" : \ '--compare-mode=[mode describing what file the actual ui output will be compared to]:COMPARE MODE:_default' \ '--pass=[force {check,build,run}-pass tests to this mode]:check | build | run:_default' \ '--run=[whether to execute run-* tests]:auto | always | never:_default' \ +'--verbose-run-make-subprocess-output=[whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)]' \ '--test-codegen-backend=[Use a different codegen backend when running tests]:TEST_CODEGEN_BACKEND:_default' \ '--config=[TOML configuration file for build]:FILE:_files' \ '--build-dir=[Build directory, overrides \`build.build-dir\` in \`bootstrap.toml\`]:DIR:_files -/' \ @@ -523,8 +544,10 @@ _arguments "${_arguments_options[@]}" : \ '--no-capture[don'\''t capture stdout/stderr of tests]' \ '--bypass-ignore-backends[Ignore \`//@ ignore-backends\` directives]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -550,6 +573,7 @@ _arguments "${_arguments_options[@]}" : \ '--compare-mode=[mode describing what file the actual ui output will be compared to]:COMPARE MODE:_default' \ '--pass=[force {check,build,run}-pass tests to this mode]:check | build | run:_default' \ '--run=[whether to execute run-* tests]:auto | always | never:_default' \ +'--verbose-run-make-subprocess-output=[whether to show verbose subprocess output for run-make tests; set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture)]' \ '--test-codegen-backend=[Use a different codegen backend when running tests]:TEST_CODEGEN_BACKEND:_default' \ '--config=[TOML configuration file for build]:FILE:_files' \ '--build-dir=[Build directory, overrides \`build.build-dir\` in \`bootstrap.toml\`]:DIR:_files -/' \ @@ -585,8 +609,10 @@ _arguments "${_arguments_options[@]}" : \ '--no-capture[don'\''t capture stdout/stderr of tests]' \ '--bypass-ignore-backends[Ignore \`//@ ignore-backends\` directives]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -635,8 +661,10 @@ _arguments "${_arguments_options[@]}" : \ '--doc[Only run doc tests]' \ '--tests[Only run unit and integration tests]' \ '--no-doc[Deprecated. Use \`--all-targets\` or \`--tests\` instead]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -680,8 +708,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -725,8 +755,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--all[Clean the entire build directory (not used by default)]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -769,8 +801,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -813,8 +847,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -858,8 +894,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -903,8 +941,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -947,8 +987,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -994,8 +1036,10 @@ _arguments "${_arguments_options[@]}" : \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ '--versioned-dirs[Always include version in subdir name]' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1038,8 +1082,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1094,8 +1140,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1141,8 +1189,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1188,8 +1238,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1235,8 +1287,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ @@ -1280,8 +1334,10 @@ _arguments "${_arguments_options[@]}" : \ '*--reproducible-artifact=[Additional reproducible artifacts that should be added to the reproducible artifacts archive]:REPRODUCIBLE_ARTIFACT:_default' \ '*--set=[override options in bootstrap.toml]:section.option=value:' \ '--ci=[Make bootstrap to behave as it'\''s running on the CI environment or not]:bool:(true false)' \ -'*-v[use verbose output (-vv for very verbose)]' \ -'*--verbose[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*-v[use verbose output (-vv for very verbose)]' \ +'(-q --quiet)*--verbose[use verbose output (-vv for very verbose)]' \ +'(-v --verbose)-q[use quiet output]' \ +'(-v --verbose)--quiet[use quiet output]' \ '-i[use incremental compilation]' \ '--incremental[use incremental compilation]' \ '--include-default-paths[include default paths in addition to the provided ones]' \ diff --git a/src/etc/xhelp b/src/etc/xhelp index 3061110efb23..4bd6575fc697 100644 --- a/src/etc/xhelp +++ b/src/etc/xhelp @@ -26,6 +26,8 @@ Arguments: Options: -v, --verbose... use verbose output (-vv for very verbose) + -q, --quiet + use quiet output -i, --incremental use incremental compilation --config diff --git a/src/librustdoc/clean/auto_trait.rs b/src/librustdoc/clean/auto_trait.rs index fc61103d939f..8379cb8c6eaa 100644 --- a/src/librustdoc/clean/auto_trait.rs +++ b/src/librustdoc/clean/auto_trait.rs @@ -234,7 +234,7 @@ fn clean_region_outlives_constraints<'tcx>( // Each `RegionTarget` (a `RegionVid` or a `Region`) maps to its smaller and larger regions. // Note that "larger" regions correspond to sub regions in the surface language. // E.g., in `'a: 'b`, `'a` is the larger region. - for (c, _) in ®ions.constraints { + for c in regions.constraints.iter().flat_map(|(c, _)| c.iter_outlives()) { match c.kind { ConstraintKind::VarSubVar => { let sub_vid = c.sub.as_var(); @@ -265,6 +265,9 @@ fn clean_region_outlives_constraints<'tcx>( .push(c.sub); } } + ConstraintKind::VarEqVar | ConstraintKind::VarEqReg | ConstraintKind::RegEqReg => { + unreachable!() + } } } diff --git a/src/librustdoc/clean/cfg.rs b/src/librustdoc/clean/cfg.rs index 086ee7def98b..631a3b47b557 100644 --- a/src/librustdoc/clean/cfg.rs +++ b/src/librustdoc/clean/cfg.rs @@ -423,6 +423,13 @@ fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { (sym::unix, None) => "Unix", (sym::windows, None) => "Windows", (sym::debug_assertions, None) => "debug-assertions enabled", + (sym::target_object_format, Some(format)) => match self.1 { + Format::LongHtml => { + return write!(fmt, "object format {format}"); + } + Format::LongPlain => return write!(fmt, "object format `{format}`"), + Format::ShortHtml => return write!(fmt, "{format}"), + }, (sym::target_os, Some(os)) => human_readable_target_os(*os).unwrap_or_default(), (sym::target_arch, Some(arch)) => { human_readable_target_arch(*arch).unwrap_or_default() @@ -545,15 +552,15 @@ fn human_readable_target_arch(os: Symbol) -> Option<&'static str> { Some(match arch { // tidy-alphabetical-start AArch64 => "AArch64", - AmdGpu => "AMG GPU", + AmdGpu => "AMD GPU", Arm => "ARM", Arm64EC => "ARM64EC", Avr => "AVR", Bpf => "BPF", CSky => "C-SKY", Hexagon => "Hexagon", - LoongArch32 => "LoongArch64", - LoongArch64 => "LoongArch32", + LoongArch32 => "LoongArch32", + LoongArch64 => "LoongArch64", M68k => "Motorola 680x0", Mips => "MIPS", Mips32r6 => "MIPS release 6", diff --git a/src/librustdoc/clean/mod.rs b/src/librustdoc/clean/mod.rs index 9e8fc2e99fa8..4eecf9e2f00c 100644 --- a/src/librustdoc/clean/mod.rs +++ b/src/librustdoc/clean/mod.rs @@ -235,7 +235,8 @@ fn generate_item_with_correct_attrs( attrs.extend(get_all_import_attributes(cx, import_id, def_id, is_inline)); is_inline = is_inline || import_is_inline; } - add_without_unwanted_attributes(&mut attrs, target_attrs, is_inline, None); + let keep_target_cfg = is_inline || matches!(kind, ItemKind::TypeAliasItem(..)); + add_without_unwanted_attributes(&mut attrs, target_attrs, keep_target_cfg, None); attrs } else { // We only keep the item's attributes. @@ -1172,7 +1173,7 @@ fn clean_fn_decl_with_params<'tcx>( { output = output.sugared_async_return_type(); } - FnDecl { inputs: params, output, c_variadic: decl.c_variadic } + FnDecl { inputs: params, output, c_variadic: decl.c_variadic() } } fn clean_poly_fn_sig<'tcx>( @@ -1210,7 +1211,7 @@ fn clean_poly_fn_sig<'tcx>( }) .collect(); - FnDecl { inputs: params, output, c_variadic: sig.skip_binder().c_variadic } + FnDecl { inputs: params, output, c_variadic: sig.skip_binder().c_variadic() } } fn clean_trait_ref<'tcx>(trait_ref: &hir::TraitRef<'tcx>, cx: &mut DocContext<'tcx>) -> Path { @@ -2914,7 +2915,8 @@ fn get_name(tcx: TyCtxt<'_>, item: &hir::Item<'_>, renamed: Option) -> O ItemKind::Fn { ref sig, generics, body: body_id, .. } => { clean_fn_or_proc_macro(item, sig, generics, body_id, &mut name, cx) } - ItemKind::Trait(_, _, _, _, generics, bounds, item_ids) => { + // FIXME: rustdoc will need to handle `impl` restrictions at some point + ItemKind::Trait(_, _, _, _impl_restriction, _, generics, bounds, item_ids) => { let items = item_ids .iter() .map(|&ti| clean_trait_item(cx.tcx.hir_trait_item(ti), cx)) diff --git a/src/librustdoc/config.rs b/src/librustdoc/config.rs index 3caff6edd504..d726c612acf6 100644 --- a/src/librustdoc/config.rs +++ b/src/librustdoc/config.rs @@ -15,8 +15,8 @@ use rustc_session::lint::Level; use rustc_session::search_paths::SearchPath; use rustc_session::{EarlyDiagCtxt, getopts}; -use rustc_span::FileName; use rustc_span::edition::Edition; +use rustc_span::{FileName, RemapPathScopeComponents}; use rustc_target::spec::TargetTuple; use crate::core::new_dcx; @@ -140,6 +140,8 @@ pub(crate) struct Options { pub(crate) no_run: bool, /// What sources are being mapped. pub(crate) remap_path_prefix: Vec<(PathBuf, PathBuf)>, + /// Which scope(s) to use with `--remap-path-prefix` + pub(crate) remap_path_scope: RemapPathScopeComponents, /// The path to a rustc-like binary to build tests with. If not set, we /// default to loading from `$sysroot/bin/rustc`. @@ -222,6 +224,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { .field("no_run", &self.no_run) .field("test_builder_wrappers", &self.test_builder_wrappers) .field("remap-file-prefix", &self.remap_path_prefix) + .field("remap-file-scope", &self.remap_path_scope) .field("no_capture", &self.no_capture) .field("scrape_examples_options", &self.scrape_examples_options) .field("unstable_features", &self.unstable_features) @@ -413,9 +416,9 @@ pub(crate) fn from_matches( config::parse_error_format(early_dcx, matches, color, json_color, json_rendered); let diagnostic_width = matches.opt_get("diagnostic-width").unwrap_or_default(); - let mut target_modifiers = BTreeMap::::new(); - let codegen_options = CodegenOptions::build(early_dcx, matches, &mut target_modifiers); - let unstable_opts = UnstableOptions::build(early_dcx, matches, &mut target_modifiers); + let mut collected_options = Default::default(); + let codegen_options = CodegenOptions::build(early_dcx, matches, &mut collected_options); + let unstable_opts = UnstableOptions::build(early_dcx, matches, &mut collected_options); let remap_path_prefix = match parse_remap_path_prefix(matches) { Ok(prefix_mappings) => prefix_mappings, @@ -423,6 +426,8 @@ pub(crate) fn from_matches( early_dcx.early_fatal(err); } }; + let remap_path_scope = + rustc_session::config::parse_remap_path_scope(early_dcx, matches, &unstable_opts); let dcx = new_dcx(error_format, None, diagnostic_width, &unstable_opts); let dcx = dcx.handle(); @@ -756,10 +761,12 @@ fn println_condition(condition: Condition) { } let index_page = matches.opt_str("index-page").map(|s| PathBuf::from(&s)); - if let Some(ref index_page) = index_page - && !index_page.is_file() - { - dcx.fatal("option `--index-page` argument must be a file"); + if let Some(ref index_page) = index_page { + if index_page.is_file() { + loaded_paths.push(index_page.clone()); + } else { + dcx.fatal("option `--index-page` argument must be a file"); + } } let target = parse_target_triple(early_dcx, matches); @@ -887,6 +894,7 @@ fn println_condition(condition: Condition) { no_run, test_builder_wrappers, remap_path_prefix, + remap_path_scope, no_capture, crate_name, output_format, @@ -894,7 +902,7 @@ fn println_condition(condition: Condition) { scrape_examples_options, unstable_features, doctest_build_args, - target_modifiers, + target_modifiers: collected_options.target_modifiers, }; let render_options = RenderOptions { output, diff --git a/src/librustdoc/core.rs b/src/librustdoc/core.rs index 42d7237f68e5..21ce508d8560 100644 --- a/src/librustdoc/core.rs +++ b/src/librustdoc/core.rs @@ -87,10 +87,7 @@ pub(crate) fn with_param_env T>( } pub(crate) fn typing_env(&self) -> ty::TypingEnv<'tcx> { - ty::TypingEnv { - typing_mode: ty::TypingMode::non_body_analysis(), - param_env: self.param_env, - } + ty::TypingEnv::new(self.param_env, ty::TypingMode::non_body_analysis()) } /// Call the closure with the given parameters set as @@ -214,6 +211,7 @@ pub(crate) fn create_config( lint_cap, scrape_examples_options, remap_path_prefix, + remap_path_scope, target_modifiers, .. }: RustdocOptions, @@ -273,6 +271,7 @@ pub(crate) fn create_config( crate_name, test, remap_path_prefix, + remap_path_scope, output_types: if let Some(file) = render_options.dep_info() { OutputTypes::new(&[(OutputType::DepInfo, file.cloned())]) } else { diff --git a/src/librustdoc/doctest.rs b/src/librustdoc/doctest.rs index bfcdc3a50558..6ec4aaf28223 100644 --- a/src/librustdoc/doctest.rs +++ b/src/librustdoc/doctest.rs @@ -171,6 +171,7 @@ pub(crate) fn run(dcx: DiagCtxtHandle<'_>, input: Input, options: RustdocOptions target_triple: options.target.clone(), crate_name: options.crate_name.clone(), remap_path_prefix: options.remap_path_prefix.clone(), + remap_path_scope: options.remap_path_scope.clone(), unstable_opts: options.unstable_opts.clone(), error_format: options.error_format.clone(), target_modifiers: options.target_modifiers.clone(), diff --git a/src/librustdoc/html/markdown.rs b/src/librustdoc/html/markdown.rs index 858545bd0984..2034abdfd156 100644 --- a/src/librustdoc/html/markdown.rs +++ b/src/librustdoc/html/markdown.rs @@ -582,6 +582,7 @@ fn next(&mut self) -> Option { } } let id = self.id_map.derive(id); + let percent_encoded_id = small_url_encode(id.clone()); if let Some(ref mut builder) = self.toc { let mut text_header = String::new(); @@ -596,8 +597,9 @@ fn next(&mut self) -> Option { std::cmp::min(level as u32 + (self.heading_offset as u32), MAX_HEADER_LEVEL); self.buf.push_back((Event::Html(format!("").into()), 0..0)); - let start_tags = - format!("§"); + let start_tags = format!( + "§" + ); return Some((Event::Html(start_tags.into()), 0..0)); } event diff --git a/src/librustdoc/html/render/write_shared.rs b/src/librustdoc/html/render/write_shared.rs index b1c77063ca94..8cb43e002870 100644 --- a/src/librustdoc/html/render/write_shared.rs +++ b/src/librustdoc/html/render/write_shared.rs @@ -118,8 +118,9 @@ pub(crate) fn write_shared( let mut md_opts = opt.clone(); md_opts.output = cx.dst.clone(); md_opts.external_html = cx.shared.layout.external_html.clone(); + let file = try_err!(cx.sess().source_map().load_file(&index_page), &index_page); try_err!( - crate::markdown::render_and_write(index_page, md_opts, cx.shared.edition()), + crate::markdown::render_and_write(file, md_opts, cx.shared.edition()), &index_page ); } diff --git a/src/librustdoc/html/static/js/main.js b/src/librustdoc/html/static/js/main.js index 491be052bca2..8a72382cf90d 100644 --- a/src/librustdoc/html/static/js/main.js +++ b/src/librustdoc/html/static/js/main.js @@ -2123,20 +2123,27 @@ function preLoadCss(cssUrl) { return; } but.onclick = () => { - // Most page titles are ' in - Rust', except - // modules (which don't have the first part) and keywords/primitives - // (which don't have a module path) - const titleElement = document.querySelector("title"); - const title = titleElement && titleElement.textContent ? - titleElement.textContent.replace(" - Rust", "") : ""; - const [item, module] = title.split(" in "); - const path = [item]; - if (module !== undefined) { - path.unshift(module); - } + // We get the path from the "breadcrumbs" and the actual item name. + let path = ""; + // @ts-expect-error + const heading = document.getElementById(MAIN_ID).querySelector(".main-heading"); - copyContentToClipboard(path.join("::")); - copyButtonAnimation(but); + if (heading) { + const breadcrumbs = heading.querySelector(".rustdoc-breadcrumbs"); + if (breadcrumbs) { + // @ts-expect-error + path = breadcrumbs.innerText; + if (path.length > 0) { + path += "::"; + } + } + + // @ts-expect-error + path += heading.querySelector("h1 > span").innerText; + + copyContentToClipboard(path); + copyButtonAnimation(but); + } }; /** diff --git a/src/librustdoc/lib.rs b/src/librustdoc/lib.rs index 751db71ceff0..750ce27ea796 100644 --- a/src/librustdoc/lib.rs +++ b/src/librustdoc/lib.rs @@ -70,12 +70,14 @@ use std::path::Path; use std::process::ExitCode; +use rustc_ast::ast; use rustc_errors::DiagCtxtHandle; use rustc_hir::def_id::LOCAL_CRATE; use rustc_interface::interface; use rustc_middle::ty::TyCtxt; use rustc_session::config::{ErrorOutputType, RustcOptGroup, make_crate_type_option}; use rustc_session::{EarlyDiagCtxt, getopts}; +use rustc_span::{BytePos, Span, SyntaxContext}; use tracing::info; use crate::clean::utils::DOC_RUST_LANG_ORG_VERSION; @@ -554,6 +556,14 @@ fn opts() -> Vec { "Remap source names in compiler messages", "FROM=TO", ), + opt( + Unstable, + Opt, + "", + "remap-path-scope", + "Defines which scopes of paths should be remapped by `--remap-path-prefix`", + "[macro,diagnostics,debuginfo,coverage,object,all]", + ), opt( Unstable, FlagMulti, @@ -836,8 +846,39 @@ fn main_args(early_dcx: &mut EarlyDiagCtxt, at_args: &[String]) { // `run_compiler`. return wrap_return( dcx, - interface::run_compiler(config, |_compiler| { - markdown::render_and_write(&md_input, render_options, edition) + interface::run_compiler(config, |compiler| { + // construct a phony "crate" without actually running the parser + // allows us to use other compiler infrastructure like dep-info + let file = + compiler.sess.source_map().load_file(&md_input).map_err(|e| { + format!("{md_input}: {e}", md_input = md_input.display()) + })?; + let inner_span = Span::new( + file.start_pos, + BytePos(file.start_pos.0 + file.normalized_source_len.0), + SyntaxContext::root(), + None, + ); + let krate = ast::Crate { + attrs: Default::default(), + items: Default::default(), + spans: ast::ModSpans { inner_span, ..Default::default() }, + id: ast::DUMMY_NODE_ID, + is_placeholder: false, + }; + rustc_interface::create_and_enter_global_ctxt(compiler, krate, |tcx| { + let has_dep_info = render_options.dep_info().is_some(); + markdown::render_and_write(file, render_options, edition)?; + if has_dep_info { + // Register the loaded external files in the source map so they show up in depinfo. + // We can't load them via the source map because it gets created after we process the options. + for external_path in &loaded_paths { + let _ = compiler.sess.source_map().load_binary_file(external_path); + } + rustc_interface::passes::write_dep_info(tcx); + } + Ok(()) + }) }), ); } diff --git a/src/librustdoc/markdown.rs b/src/librustdoc/markdown.rs index 4ca2c104888b..594c9b1af339 100644 --- a/src/librustdoc/markdown.rs +++ b/src/librustdoc/markdown.rs @@ -9,10 +9,12 @@ //! [docs]: https://doc.rust-lang.org/stable/rustdoc/#using-standalone-markdown-files use std::fmt::{self, Write as _}; -use std::fs::{File, create_dir_all, read_to_string}; +use std::fs::{File, create_dir_all}; use std::io::prelude::*; -use std::path::Path; +use std::path::PathBuf; +use std::sync::Arc; +use rustc_span::SourceFile; use rustc_span::edition::Edition; use crate::config::RenderOptions; @@ -43,8 +45,8 @@ fn extract_leading_metadata(s: &str) -> (Vec<&str>, &str) { /// (e.g., output = "bar" => "bar/foo.html"). /// /// Requires session globals to be available, for symbol interning. -pub(crate) fn render_and_write>( - input: P, +pub(crate) fn render_and_write( + input: Arc, options: RenderOptions, edition: Edition, ) -> Result<(), String> { @@ -52,9 +54,9 @@ pub(crate) fn render_and_write>( return Err(format!("{output}: {e}", output = options.output.display())); } - let input = input.as_ref(); + let input_path = input.name.clone().into_local_path().unwrap_or(PathBuf::new()); let mut output = options.output; - output.push(input.file_name().unwrap()); + output.push(input_path.file_name().unwrap()); output.set_extension("html"); let mut css = String::new(); @@ -63,8 +65,7 @@ pub(crate) fn render_and_write>( .expect("Writing to a String can't fail"); } - let input_str = - read_to_string(input).map_err(|err| format!("{input}: {err}", input = input.display()))?; + let input_str = input.src.as_ref().map(|src| &src[..]).unwrap_or(""); let playground_url = options.markdown_playground_url.or(options.playground_url); let playground = playground_url.map(|url| markdown::Playground { crate_name: None, url }); diff --git a/src/librustdoc/passes/lint/redundant_explicit_links.rs b/src/librustdoc/passes/lint/redundant_explicit_links.rs index 13bc4c079aa7..8da21f100c6a 100644 --- a/src/librustdoc/passes/lint/redundant_explicit_links.rs +++ b/src/librustdoc/passes/lint/redundant_explicit_links.rs @@ -90,12 +90,23 @@ fn check_redundant_explicit_link<'md>( .into_offset_iter(); while let Some((event, link_range)) = offset_iter.next() { - if let Event::Start(Tag::Link { link_type, dest_url, .. }) = event { + if let Event::Start(Tag::Link { link_type, dest_url, title, .. }) = event { + if !title.is_empty() { + // Skips if the link specifies a title, e.g. `[Option](Option "title")`, + // in which case the explicit link cannot be removed without also + // removing the title. + continue; + } + let link_data = collect_link_data(&mut offset_iter); - if let Some(resolvable_link) = link_data.resolvable_link.as_ref() - && &link_data.display_link.replace('`', "") != resolvable_link - { + let Some(resolvable_link) = link_data.resolvable_link.as_ref() else { + // collect_link_data didn't return a resolvable_link + // most likely due to the displayed link containing inline markup + continue; + }; + + if &link_data.display_link.replace('`', "") != resolvable_link { // Skips if display link does not match to actual // resolvable link, usually happens if display link // has several segments, e.g. @@ -103,10 +114,7 @@ fn check_redundant_explicit_link<'md>( continue; } - let explicit_link = dest_url.to_string(); - let display_link = link_data.resolvable_link.clone()?; - - if explicit_link.ends_with(&display_link) || display_link.ends_with(&explicit_link) { + if dest_url.ends_with(resolvable_link) || resolvable_link.ends_with(&*dest_url) { match link_type { LinkType::Inline | LinkType::ReferenceUnknown => { check_inline_or_reference_unknown_redundancy( diff --git a/src/stage0 b/src/stage0 index 40be3f7a66a8..4261ef43e8e6 100644 --- a/src/stage0 +++ b/src/stage0 @@ -13,570 +13,574 @@ nightly_branch=main # All changes below this comment will be overridden the next time the # tool is executed. -compiler_channel_manifest_hash=18261f24c2dc26c5bfc6647e837c2e820a478f52d55aea7ff98eb24f43c750dd -compiler_git_commit_hash=ad726b5063362ec9897ef3d67452fc5606ee70fa -compiler_date=2026-03-05 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b/src/tools/clippy/CHANGELOG.md @@ -6,7 +6,124 @@ document. ## Unreleased / Beta / In Rust Nightly -[500e0ff...master](https://github.com/rust-lang/rust-clippy/compare/500e0ff...master) +[df995e...master](https://github.com/rust-lang/rust-clippy/compare/df995e...master) + +## Rust 1.95 + +Current stable, released 2026-04-16 + +[View all 107 merged pull requests](https://github.com/rust-lang/rust-clippy/pulls?q=merged%3A2026-01-09T11%3A07%3A27Z..2026-02-23T22%3A37%3A09Z+base%3Amaster) + +### New Lints + +* Added [`unnecessary_trailing_comma`] to `pedantic` + [#16530](https://github.com/rust-lang/rust-clippy/pull/16530) +* Added [`disallowed_fields`] to `style` + [#16218](https://github.com/rust-lang/rust-clippy/pull/16218) +* Added [`manual_checked_ops`] to `complexity` + [#16149](https://github.com/rust-lang/rust-clippy/pull/16149) +* Added [`duration_suboptimal_units`] to `pedantic` + [#16250](https://github.com/rust-lang/rust-clippy/pull/16250) +* Added [`manual_take`] to `complexity` + [#16368](https://github.com/rust-lang/rust-clippy/pull/16368) + +### Enhancements + +* [`explicit_counter_loop`] fix FN when loop counter starts at non-zero + [#16620](https://github.com/rust-lang/rust-clippy/pull/16620) +* [`manual_is_variant_and`] extend to cover `filter` chaining `is_some` + [#16521](https://github.com/rust-lang/rust-clippy/pull/16521) +* [`manual_is_variant_and`] enhance to cover manual `is_none_or` + [#16424](https://github.com/rust-lang/rust-clippy/pull/16424) +* [`collapsible_match`] extend to cover if-elses + [#16560](https://github.com/rust-lang/rust-clippy/pull/16560) +* [`useless_conversion`] also fire inside compiler desugarings + [#16594](https://github.com/rust-lang/rust-clippy/pull/16594) +* [`unwrap_used`] and [`expect_used`] add `allow-unwrap-types` configuration + [#16605](https://github.com/rust-lang/rust-clippy/pull/16605) +* [`unwrap_used`] and [`expect_used`] optimize `allow-unwrap-types` evaluation to eliminate performance regression + [#16652](https://github.com/rust-lang/rust-clippy/pull/16652) +* [`unchecked_time_subtraction`] extend to better handle `Duration` literals + [#16528](https://github.com/rust-lang/rust-clippy/pull/16528) +* [`unnecessary_fold`] match against an accumulator on both sides + [#16604](https://github.com/rust-lang/rust-clippy/pull/16604) +* [`iter_kv_map`] extend to cover `flat_map` and `filter_map` + [#16519](https://github.com/rust-lang/rust-clippy/pull/16519) +* [`question_mark`] enhance to cover `else if` + [#16455](https://github.com/rust-lang/rust-clippy/pull/16455) +* [`double_comparisons`] check for expressions such as `x != y && x >= y` + [#16033](https://github.com/rust-lang/rust-clippy/pull/16033) +* [`needless_collect`] enhance to cover vec `push`-alike cases + [#16305](https://github.com/rust-lang/rust-clippy/pull/16305) +* [`strlen_on_c_strings`] changes suggestion to use `CStr::count_bytes()` + [#16323](https://github.com/rust-lang/rust-clippy/pull/16323) +* [`transmuting_null`] now checks for `ptr::without_provenance` and `ptr::without_provenance_mut` + [#16336](https://github.com/rust-lang/rust-clippy/pull/16336) +* [`map_unwrap_or`] add cover for `Result::unwrap_or` + [#15718](https://github.com/rust-lang/rust-clippy/pull/15718) +* [`clone_on_ref_ptr`] don't add a `&` to the receiver if it's a reference + [#15742](https://github.com/rust-lang/rust-clippy/pull/15742) +* [`double_must_use`], [`drop_non_drop`], [`let_underscore_must_use`] consider `Result` and + `ControlFlow` as `T` wrt `#[must_use]` if `U` is uninhabited + [#16353](https://github.com/rust-lang/rust-clippy/pull/16353) +* [`str_to_string`] handle a case when `ToString::to_string` is passed as function parameter + [#16512](https://github.com/rust-lang/rust-clippy/pull/16512) +* [`must_use_candidate`] no longer lints `main` functions with return values + [#16552](https://github.com/rust-lang/rust-clippy/pull/16552) +* [`needless_continue`] `allow` and `expect` attributes can also be used on the statement + [#16265](https://github.com/rust-lang/rust-clippy/pull/16265) +* [`int_plus_one`] fix FN with negative literals, e.g. `-1 + x <= y` + [#16373](https://github.com/rust-lang/rust-clippy/pull/16373) + +### False Positive Fixes + +* [`assertions_on_result_states`] and [`missing_assert_message`] fix FP on edition 2015 and 2018 + [#16473](https://github.com/rust-lang/rust-clippy/pull/16473) +* [`redundant_iter_cloned`] fix FP with move closures and coroutines + [#16494](https://github.com/rust-lang/rust-clippy/pull/16494) +* [`str_to_string`] fix FP on non-str types + [#16571](https://github.com/rust-lang/rust-clippy/pull/16571) +* [`unnecessary_cast`] do not warn on casts of external function return type + [#16415](https://github.com/rust-lang/rust-clippy/pull/16415) +* [`cmp_owned`] fix FP when `to_string` comes from macro input + [#16468](https://github.com/rust-lang/rust-clippy/pull/16468) +* [`useless_attribute`] fix FP on `exported_private_dependencies` lint attributes + [#16470](https://github.com/rust-lang/rust-clippy/pull/16470) +* [`manual_dangling_ptr`] fix FP when pointee type is not `Sized` + [#16469](https://github.com/rust-lang/rust-clippy/pull/16469) +* [`test_attr_in_doctest`] fix FP on `test_harness` + [#16454](https://github.com/rust-lang/rust-clippy/pull/16454) +* [`doc_paragraphs_missing_punctuation`] allow unpunctuated paragraphs before lists and code blocks + [#16487](https://github.com/rust-lang/rust-clippy/pull/16487) +* [`elidable_lifetime_names`] skip linting proc-macro generated code + [#16402](https://github.com/rust-lang/rust-clippy/pull/16402) +* [`undocumented_unsafe_blocks`] recognize safety comments inside blocks and on same line in macros + [#16339](https://github.com/rust-lang/rust-clippy/pull/16339) + +### ICE Fixes + +* [`match_same_arms`] fix ICE in `match_same_arms` + [#16685](https://github.com/rust-lang/rust-clippy/pull/16685) +* [`nonminimal_bool`] fix ICE in `swap_binop()` by using the proper `TypeckResults` + [#16659](https://github.com/rust-lang/rust-clippy/pull/16659) +* [`redundant_closure_for_method_calls`] fix ICE when computing the path from a type to itself + [#16362](https://github.com/rust-lang/rust-clippy/pull/16362) + +### Documentation Improvements + +* [`cast_possible_wrap`] mention `cast_{un,}signed()` methods in the documentation + [#16407](https://github.com/rust-lang/rust-clippy/pull/16407) +* [`ignore_without_reason`] and [`redundant_test_prefix`] mention an extra `clippy` argument + needed to check tests + [#16205](https://github.com/rust-lang/rust-clippy/pull/16205) +* [`doc_paragraphs_missing_punctuation`] improve its documentation + [#16377](https://github.com/rust-lang/rust-clippy/pull/16377) +* [`missing_trait_methods`] better help message + [#16380](https://github.com/rust-lang/rust-clippy/pull/16380) +* [`strlen_on_c_strings`] mention the specific type (`CString` or `CStr`) + [#16391](https://github.com/rust-lang/rust-clippy/pull/16391) +* [`suspicious_to_owned`] improve lint messages + [#16376](https://github.com/rust-lang/rust-clippy/pull/16376) ## Rust 1.94 @@ -104,11 +221,6 @@ Current stable, released 2026-03-05 * [`needless_type_cast`] do not ICE on struct constructor [#16245](https://github.com/rust-lang/rust-clippy/pull/16245) -### New Lints - -* Added [`unnecessary_trailing_comma`] to `style` (single-line format-like macros only) - [#13965](https://github.com/rust-lang/rust-clippy/issues/13965) - ## Rust 1.93 Current stable, released 2026-01-22 diff --git a/src/tools/clippy/Cargo.toml b/src/tools/clippy/Cargo.toml index bcd800930c51..234478eadbf9 100644 --- a/src/tools/clippy/Cargo.toml +++ b/src/tools/clippy/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "clippy" -version = "0.1.96" +version = "0.1.97" description = "A bunch of helpful lints to avoid common pitfalls in Rust" repository = "https://github.com/rust-lang/rust-clippy" readme = "README.md" @@ -33,7 +33,7 @@ color-print = "0.3.4" anstream = "0.6.18" [dev-dependencies] -cargo_metadata = "0.18.1" +cargo_metadata = "0.23" ui_test = "0.30.2" regex = "1.5.5" serde = { version = "1.0.145", features = ["derive"] } diff --git a/src/tools/clippy/book/src/lint_configuration.md b/src/tools/clippy/book/src/lint_configuration.md index c87f8e9a68de..64d0bf9b62f6 100644 --- a/src/tools/clippy/book/src/lint_configuration.md +++ b/src/tools/clippy/book/src/lint_configuration.md @@ -928,6 +928,7 @@ The minimum rust version that the project supports. Defaults to the `rust-versio * [`manual_let_else`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_let_else) * [`manual_midpoint`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_midpoint) * [`manual_non_exhaustive`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_non_exhaustive) +* [`manual_noop_waker`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_noop_waker) * [`manual_option_as_slice`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_option_as_slice) * [`manual_pattern_char_comparison`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_pattern_char_comparison) * [`manual_range_contains`](https://rust-lang.github.io/rust-clippy/master/index.html#manual_range_contains) diff --git a/src/tools/clippy/clippy_config/Cargo.toml b/src/tools/clippy/clippy_config/Cargo.toml index 366c776b8f1a..3d5b425ac530 100644 --- a/src/tools/clippy/clippy_config/Cargo.toml +++ b/src/tools/clippy/clippy_config/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "clippy_config" -version = "0.1.96" +version = "0.1.97" edition = "2024" publish = false diff --git a/src/tools/clippy/clippy_config/src/conf.rs b/src/tools/clippy/clippy_config/src/conf.rs index 41099f94b044..465e88a783ed 100644 --- a/src/tools/clippy/clippy_config/src/conf.rs +++ b/src/tools/clippy/clippy_config/src/conf.rs @@ -789,6 +789,7 @@ fn span_from_toml_range(file: &SourceFile, span: Range) -> Span { manual_let_else, manual_midpoint, manual_non_exhaustive, + manual_noop_waker, manual_option_as_slice, manual_pattern_char_comparison, manual_range_contains, diff --git a/src/tools/clippy/clippy_lints/Cargo.toml b/src/tools/clippy/clippy_lints/Cargo.toml index 51e753efb52e..52b85103209b 100644 --- a/src/tools/clippy/clippy_lints/Cargo.toml +++ b/src/tools/clippy/clippy_lints/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "clippy_lints" -version = "0.1.96" +version = "0.1.97" description = "A bunch of helpful lints to avoid common pitfalls in Rust" repository = "https://github.com/rust-lang/rust-clippy" readme = "README.md" @@ -10,7 +10,7 @@ edition = "2024" [dependencies] arrayvec = { version = "0.7", default-features = false } -cargo_metadata = "0.18" +cargo_metadata = "0.23" clippy_config = { path = "../clippy_config" } clippy_utils = { path = "../clippy_utils" } declare_clippy_lint = { path = "../declare_clippy_lint" } diff --git a/src/tools/clippy/clippy_lints/src/arbitrary_source_item_ordering.rs b/src/tools/clippy/clippy_lints/src/arbitrary_source_item_ordering.rs index 454026e80ab3..dae0c8439ea8 100644 --- a/src/tools/clippy/clippy_lints/src/arbitrary_source_item_ordering.rs +++ b/src/tools/clippy/clippy_lints/src/arbitrary_source_item_ordering.rs @@ -306,9 +306,16 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'tcx>) { cur_f = Some(field); } }, - ItemKind::Trait(_constness, is_auto, _safety, _ident, _generics, _generic_bounds, item_ref) - if self.enable_ordering_for_trait && *is_auto == IsAuto::No => - { + ItemKind::Trait( + _constness, + is_auto, + _safety, + _impl_restriction, + _ident, + _generics, + _generic_bounds, + item_ref, + ) if self.enable_ordering_for_trait && *is_auto == IsAuto::No => { let mut cur_t: Option<(TraitItemId, Ident)> = None; for &item in *item_ref { diff --git a/src/tools/clippy/clippy_lints/src/attrs/mod.rs b/src/tools/clippy/clippy_lints/src/attrs/mod.rs index 372defbb4d7e..c15a378053e3 100644 --- a/src/tools/clippy/clippy_lints/src/attrs/mod.rs +++ b/src/tools/clippy/clippy_lints/src/attrs/mod.rs @@ -583,7 +583,7 @@ fn check_attribute(&mut self, cx: &EarlyContext<'_>, attr: &Attribute) { if matches!(name, sym::allow | sym::expect) && self.msrv.meets(msrvs::LINT_REASONS_STABILIZATION) { allow_attributes_without_reason::check(cx, name, items, attr); } - if is_lint_level(name) { + if is_lint_level(name, attr.id) { blanket_clippy_restriction_lints::check(cx, name, items); } if items.is_empty() || !attr.has_name(sym::deprecated) { diff --git a/src/tools/clippy/clippy_lints/src/attrs/unnecessary_clippy_cfg.rs b/src/tools/clippy/clippy_lints/src/attrs/unnecessary_clippy_cfg.rs index 5d095c9b27ad..6ee3290fa761 100644 --- a/src/tools/clippy/clippy_lints/src/attrs/unnecessary_clippy_cfg.rs +++ b/src/tools/clippy/clippy_lints/src/attrs/unnecessary_clippy_cfg.rs @@ -1,12 +1,10 @@ -use crate::attrs::is_lint_level; - use super::{Attribute, UNNECESSARY_CLIPPY_CFG}; use clippy_utils::diagnostics::{span_lint_and_note, span_lint_and_sugg}; use clippy_utils::source::SpanRangeExt; use itertools::Itertools; use rustc_ast::AttrStyle; use rustc_errors::Applicability; -use rustc_lint::{EarlyContext}; +use rustc_lint::{EarlyContext, Level}; use rustc_span::sym; pub(super) fn check( @@ -15,10 +13,9 @@ pub(super) fn check( behind_cfg_attr: &rustc_ast::MetaItem, attr: &Attribute, ) { - // FIXME use proper attr parsing here if cfg_attr.has_name(sym::clippy) && let Some(ident) = behind_cfg_attr.ident() - && is_lint_level(ident.name) + && Level::from_symbol(ident.name, || Some(attr.id)).is_some() && let Some(items) = behind_cfg_attr.meta_item_list() { let nb_items = items.len(); diff --git a/src/tools/clippy/clippy_lints/src/attrs/useless_attribute.rs b/src/tools/clippy/clippy_lints/src/attrs/useless_attribute.rs index 2d56086a9602..9a1e315ae530 100644 --- a/src/tools/clippy/clippy_lints/src/attrs/useless_attribute.rs +++ b/src/tools/clippy/clippy_lints/src/attrs/useless_attribute.rs @@ -15,7 +15,7 @@ pub(super) fn check(cx: &EarlyContext<'_>, item: &Item, attrs: &[Attribute]) { return; } if let Some(lint_list) = &attr.meta_item_list() - && attr.name().is_some_and(is_lint_level) + && attr.name().is_some_and(|name| is_lint_level(name, attr.id)) { for lint in lint_list { match item.kind { diff --git a/src/tools/clippy/clippy_lints/src/attrs/utils.rs b/src/tools/clippy/clippy_lints/src/attrs/utils.rs index 512f961228b1..7b66f91f6c07 100644 --- a/src/tools/clippy/clippy_lints/src/attrs/utils.rs +++ b/src/tools/clippy/clippy_lints/src/attrs/utils.rs @@ -1,5 +1,5 @@ use clippy_utils::macros::{is_panic, macro_backtrace}; -use rustc_ast::{MetaItemInner}; +use rustc_ast::{AttrId, MetaItemInner}; use rustc_hir::{ Block, Expr, ExprKind, ImplItem, ImplItemKind, Item, ItemKind, StmtKind, TraitFn, TraitItem, TraitItemKind, }; @@ -16,8 +16,8 @@ pub(super) fn is_word(nmi: &MetaItemInner, expected: Symbol) -> bool { } } -pub(super) fn is_lint_level(symbol: Symbol) -> bool { - Level::from_symbol(symbol).is_some() +pub(super) fn is_lint_level(symbol: Symbol, attr_id: AttrId) -> bool { + Level::from_symbol(symbol, || Some(attr_id)).is_some() } pub(super) fn is_relevant_item(cx: &LateContext<'_>, item: &Item<'_>) -> bool { diff --git a/src/tools/clippy/clippy_lints/src/booleans.rs b/src/tools/clippy/clippy_lints/src/booleans.rs index 8b7619d11a83..986e75577412 100644 --- a/src/tools/clippy/clippy_lints/src/booleans.rs +++ b/src/tools/clippy/clippy_lints/src/booleans.rs @@ -30,6 +30,8 @@ /// Ignores short circuiting behavior of `||` and /// `&&`. Ignores `|`, `&` and `^`. /// + /// Creates a big toll on performance, **only enable sporadically** + /// /// ### Example /// ```ignore /// if a && true {} @@ -43,7 +45,7 @@ /// ``` #[clippy::version = "pre 1.29.0"] pub NONMINIMAL_BOOL, - complexity, + pedantic, "boolean expressions that can be written more concisely" } @@ -57,6 +59,7 @@ /// /// ### Known problems /// Ignores short circuiting behavior. + /// Creates a big toll on performance, **only enable sporadically** /// /// ### Example /// ```rust,ignore @@ -70,7 +73,7 @@ /// ``` #[clippy::version = "pre 1.29.0"] pub OVERLY_COMPLEX_BOOL_EXPR, - correctness, + pedantic, "boolean expressions that contain terminals which can be eliminated" } diff --git a/src/tools/clippy/clippy_lints/src/byte_char_slices.rs b/src/tools/clippy/clippy_lints/src/byte_char_slices.rs index 6c023189f69e..5104594790fe 100644 --- a/src/tools/clippy/clippy_lints/src/byte_char_slices.rs +++ b/src/tools/clippy/clippy_lints/src/byte_char_slices.rs @@ -1,9 +1,15 @@ -use clippy_utils::diagnostics::span_lint_and_sugg; -use rustc_ast::ast::{BorrowKind, Expr, ExprKind, Mutability}; -use rustc_ast::token::{Lit, LitKind}; +use std::borrow::Cow; + +use clippy_utils::diagnostics::span_lint_and_then; +use clippy_utils::source::snippet_with_applicability; +use clippy_utils::sugg::Sugg; +use clippy_utils::{get_parent_expr, span_contains_cfg, span_contains_comment}; +use rustc_ast::LitKind; use rustc_errors::Applicability; -use rustc_lint::{EarlyContext, EarlyLintPass}; +use rustc_hir::{BorrowKind, Expr, ExprKind, Mutability}; +use rustc_lint::{LateContext, LateLintPass}; use rustc_session::declare_lint_pass; +use rustc_span::Span; declare_clippy_lint! { /// ### What it does @@ -30,47 +36,73 @@ declare_lint_pass!(ByteCharSlice => [BYTE_CHAR_SLICES]); -impl EarlyLintPass for ByteCharSlice { - fn check_expr(&mut self, cx: &EarlyContext<'_>, expr: &Expr) { +impl<'tcx> LateLintPass<'tcx> for ByteCharSlice { + fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'tcx>) { if !expr.span.from_expansion() - && let Some(slice) = is_byte_char_slices(expr) + && let Some((has_ref, slice)) = is_byte_char_slices(cx, expr) { - span_lint_and_sugg( + span_lint_and_then( cx, BYTE_CHAR_SLICES, expr.span, "can be more succinctly written as a byte str", - "try", - format!("b\"{slice}\""), - Applicability::MachineApplicable, + |diag| { + let mut app = Applicability::MachineApplicable; + let mut sugg = Sugg::hir_from_snippet(cx, expr, |_| { + let mut slice = slice.iter().fold("b\"".to_owned(), |mut acc, span| { + let snippet = snippet_with_applicability(cx, *span, "b'?'", &mut app); + acc.push_str(match &snippet[2..snippet.len() - 1] { + "\"" => "\\\"", + "\\'" => "'", + other => other, + }); + acc + }); + slice.push('"'); + Cow::Owned(slice) + }); + if !has_ref && !cx.typeck_results().expr_ty_adjusted(expr).is_array_slice() { + sugg = sugg.deref(); + } + + diag.span_suggestion(expr.span, "try", sugg, app); + }, ); } } } /// Checks whether the slice is that of byte chars, and if so, builds a byte-string out of it -fn is_byte_char_slices(expr: &Expr) -> Option { - if let ExprKind::AddrOf(BorrowKind::Ref, Mutability::Not, expr) = &expr.kind - && let ExprKind::Array(members) = &expr.kind - && !members.is_empty() +fn is_byte_char_slices<'tcx>(cx: &LateContext<'tcx>, expr: &'tcx Expr<'tcx>) -> Option<(bool, Vec)> { + let (has_ref, expr) = if let ExprKind::AddrOf(BorrowKind::Ref, Mutability::Not, inner) = expr.kind { + (true, inner) + } else if let Some(parent) = get_parent_expr(cx, expr) // Already checked by the parent expr. + && let ExprKind::AddrOf(BorrowKind::Ref, Mutability::Not, _) = parent.kind { - members - .iter() - .map(|member| match &member.kind { - ExprKind::Lit(Lit { - kind: LitKind::Byte, - symbol, - .. - }) => Some(symbol.as_str()), - _ => None, - }) - .map(|maybe_quote| match maybe_quote { - Some("\"") => Some("\\\""), - Some("\\'") => Some("'"), - other => other, - }) - .collect::>() + return None; } else { - None + (false, expr) + }; + + if let ExprKind::Array(members) = expr.kind + && !members.is_empty() + && !span_contains_comment(cx, expr.span) + && !span_contains_cfg(cx, expr.span) + { + return members + .iter() + .try_fold(Vec::new(), |mut acc, member| { + if let ExprKind::Lit(lit) = member.kind + && let LitKind::Byte(_) = lit.node + && expr.span.eq_ctxt(member.span) + { + acc.push(lit.span); + return Some(acc); + } + None + }) + .map(|s| (has_ref, s)); } + + None } diff --git a/src/tools/clippy/clippy_lints/src/cargo/multiple_crate_versions.rs b/src/tools/clippy/clippy_lints/src/cargo/multiple_crate_versions.rs index 44cd1f7192fb..21b5acf64073 100644 --- a/src/tools/clippy/clippy_lints/src/cargo/multiple_crate_versions.rs +++ b/src/tools/clippy/clippy_lints/src/cargo/multiple_crate_versions.rs @@ -32,7 +32,7 @@ pub(super) fn check(cx: &LateContext<'_>, metadata: &Metadata, allowed_duplicate { for (name, group) in &packages .iter() - .filter(|p| !allowed_duplicate_crates.contains(&p.name)) + .filter(|p| !allowed_duplicate_crates.contains(p.name.as_str())) .group_by(|p| &p.name) { let group: Vec<&Package> = group.collect(); diff --git a/src/tools/clippy/clippy_lints/src/cargo/wildcard_dependencies.rs b/src/tools/clippy/clippy_lints/src/cargo/wildcard_dependencies.rs index 0cf687d01928..c09b02ba449a 100644 --- a/src/tools/clippy/clippy_lints/src/cargo/wildcard_dependencies.rs +++ b/src/tools/clippy/clippy_lints/src/cargo/wildcard_dependencies.rs @@ -10,7 +10,7 @@ pub(super) fn check(cx: &LateContext<'_>, metadata: &Metadata) { // VersionReq::any() does not work if let Ok(wildcard_ver) = semver::VersionReq::parse("*") && let Some(ref source) = dep.source - && !source.starts_with("git") + && !source.repr.starts_with("git") && dep.req == wildcard_ver { span_lint( diff --git a/src/tools/clippy/clippy_lints/src/casts/fn_to_numeric_cast_any.rs b/src/tools/clippy/clippy_lints/src/casts/fn_to_numeric_cast_any.rs index 43ee91af6e5a..0ce2741ad059 100644 --- a/src/tools/clippy/clippy_lints/src/casts/fn_to_numeric_cast_any.rs +++ b/src/tools/clippy/clippy_lints/src/casts/fn_to_numeric_cast_any.rs @@ -8,11 +8,6 @@ use super::FN_TO_NUMERIC_CAST_ANY; pub(super) fn check(cx: &LateContext<'_>, expr: &Expr<'_>, cast_expr: &Expr<'_>, cast_from: Ty<'_>, cast_to: Ty<'_>) { - // We allow casts from any function type to any function type. - if cast_to.is_fn() { - return; - } - if cast_from.is_fn() { let mut applicability = Applicability::MaybeIncorrect; let from_snippet = snippet_with_applicability(cx, cast_expr.span, "..", &mut applicability); diff --git a/src/tools/clippy/clippy_lints/src/casts/mod.rs b/src/tools/clippy/clippy_lints/src/casts/mod.rs index 151f9c956c6d..de34b2691abc 100644 --- a/src/tools/clippy/clippy_lints/src/casts/mod.rs +++ b/src/tools/clippy/clippy_lints/src/casts/mod.rs @@ -911,10 +911,7 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { ptr_cast_constness::check(cx, expr, cast_from_expr, cast_from, cast_to, self.msrv); ptr_as_ptr::check(cx, expr, cast_from_expr, cast_from, cast_to_hir, cast_to, self.msrv); as_ptr_cast_mut::check(cx, expr, cast_from_expr, cast_to); - fn_to_numeric_cast_any::check(cx, expr, cast_from_expr, cast_from, cast_to); confusing_method_to_numeric_cast::check(cx, expr, cast_from_expr, cast_from, cast_to); - fn_to_numeric_cast::check(cx, expr, cast_from_expr, cast_from, cast_to); - fn_to_numeric_cast_with_truncation::check(cx, expr, cast_from_expr, cast_from, cast_to); zero_ptr::check(cx, expr, cast_from_expr, cast_to_hir, self.msrv); if self.msrv.meets(cx, msrvs::MANUAL_DANGLING_PTR) { @@ -932,6 +929,9 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { } cast_lossless::check(cx, expr, cast_from_expr, cast_from, cast_to, cast_to_hir, self.msrv); cast_enum_constructor::check(cx, expr, cast_from_expr, cast_from); + fn_to_numeric_cast_any::check(cx, expr, cast_from_expr, cast_from, cast_to); + fn_to_numeric_cast::check(cx, expr, cast_from_expr, cast_from, cast_to); + fn_to_numeric_cast_with_truncation::check(cx, expr, cast_from_expr, cast_from, cast_to); } as_underscore::check(cx, expr, cast_to_hir); diff --git a/src/tools/clippy/clippy_lints/src/casts/ref_as_ptr.rs b/src/tools/clippy/clippy_lints/src/casts/ref_as_ptr.rs index b3805c678174..aef04dc9f7f9 100644 --- a/src/tools/clippy/clippy_lints/src/casts/ref_as_ptr.rs +++ b/src/tools/clippy/clippy_lints/src/casts/ref_as_ptr.rs @@ -1,7 +1,7 @@ use clippy_utils::diagnostics::span_lint_and_sugg; use clippy_utils::source::snippet_with_applicability; use clippy_utils::sugg::Sugg; -use clippy_utils::{ExprUseNode, expr_use_ctxt, is_expr_temporary_value, std_or_core}; +use clippy_utils::{ExprUseNode, get_expr_use_site, is_expr_temporary_value, std_or_core}; use rustc_errors::Applicability; use rustc_hir::{Expr, ExprKind, Mutability, Ty, TyKind}; use rustc_lint::LateContext; @@ -22,13 +22,12 @@ pub(super) fn check<'tcx>( if matches!(cast_from.kind(), ty::Ref(..)) && let ty::RawPtr(_, to_mutbl) = cast_to.kind() - && let use_cx = expr_use_ctxt(cx, expr) && let Some(std_or_core) = std_or_core(cx) { if let ExprKind::AddrOf(_, _, addr_inner) = cast_expr.kind && is_expr_temporary_value(cx, addr_inner) && matches!( - use_cx.use_node(cx), + get_expr_use_site(cx.tcx, cx.typeck_results(), expr.span.ctxt(), expr).use_node(cx), ExprUseNode::LetStmt(_) | ExprUseNode::ConstStatic(_) ) { diff --git a/src/tools/clippy/clippy_lints/src/casts/unnecessary_cast.rs b/src/tools/clippy/clippy_lints/src/casts/unnecessary_cast.rs index f822590a721d..333f31ba00ea 100644 --- a/src/tools/clippy/clippy_lints/src/casts/unnecessary_cast.rs +++ b/src/tools/clippy/clippy_lints/src/casts/unnecessary_cast.rs @@ -8,10 +8,10 @@ use rustc_ast::{LitFloatType, LitIntType, LitKind}; use rustc_errors::Applicability; use rustc_hir::def::{DefKind, Res}; -use rustc_hir::{Expr, ExprKind, FnRetTy, Lit, Node, Path, QPath, TyKind, UnOp}; +use rustc_hir::{Expr, ExprKind, FnRetTy, HirId, Lit, Node, Path, QPath, TyKind, UnOp}; use rustc_lint::{LateContext, LintContext}; use rustc_middle::ty::adjustment::Adjust; -use rustc_middle::ty::{self, FloatTy, InferTy, Ty}; +use rustc_middle::ty::{self, FloatTy, GenericArg, InferTy, Ty}; use rustc_span::Symbol; use std::ops::ControlFlow; @@ -173,6 +173,16 @@ fn is_in_allowed_macro(cx: &LateContext<'_>, expr: &Expr<'_>) -> bool { cx.tcx.get_diagnostic_name(def_id).is_some_and(|sym| ALLOWED_MACROS.contains(&sym))) } + // Removing the cast here can change inference along the path to an outer + // method receiver, so avoid linting in that case. + if is_inference_sensitive_inner_expr(cx, cast_expr) + && contains_unsuffixed_numeric_literal(cast_expr) + && feeds_outer_method_receiver(cx, expr) + && has_lint_blocking_context_on_receiver_path(cx, expr) + { + return false; + } + if let Some(id) = cast_expr.res_local_id() && !cx.tcx.hir_span(id).eq_ctxt(cast_expr.span) { @@ -340,3 +350,338 @@ fn emit_lint( applicability, ); } + +fn contains_unsuffixed_numeric_literal<'e>(expr: &'e Expr<'e>) -> bool { + for_each_expr_without_closures(expr, |e| { + if let Some(lit) = get_numeric_literal(e) + && matches!( + lit.node, + LitKind::Int(_, LitIntType::Unsuffixed) | LitKind::Float(_, LitFloatType::Unsuffixed) + ) + { + return ControlFlow::Break(()); + } + + ControlFlow::Continue(()) + }) + .is_some() +} + +// Returns `true` for expressions whose resolved type or method depends on inference. +fn is_inference_sensitive_inner_expr(cx: &LateContext<'_>, expr: &Expr<'_>) -> bool { + match expr.kind { + ExprKind::MethodCall(..) | ExprKind::Binary(..) | ExprKind::Unary(..) | ExprKind::Index(..) => cx + .typeck_results() + .type_dependent_def_id(expr.hir_id) + .and_then(|def_id| cx.tcx.opt_associated_item(def_id)) + .is_some_and(|assoc| assoc.trait_container(cx.tcx).is_some()), + _ => false, + } +} + +// Returns `true` if the function's output type contains a type parameter +// originating from the selected input. +fn output_depends_on_input_param(cx: &LateContext<'_>, def_id: rustc_hir::def_id::DefId, input_index: usize) -> bool { + let sig = cx.tcx.fn_sig(def_id).instantiate_identity().skip_binder(); + + let Some(input_ty) = sig.inputs().get(input_index) else { + return false; + }; + + let output_ty = sig.output(); + + input_ty.walk().filter_map(GenericArg::as_type).any(|input_part| { + match input_part.kind() { + ty::Param(input_param) => output_ty + .walk() + .filter_map(GenericArg::as_type) + .any(|output_part| { + matches!(output_part.kind(), ty::Param(output_param) if output_param.index == input_param.index) + }), + _ => false, + } + }) +} + +// Returns `true` if the generic arguments include at least one explicit type or const +// argument and none of the provided generic arguments are placeholders like `::<_>`. +fn has_explicit_type_or_const_args(args: Option<&rustc_hir::GenericArgs<'_>>) -> bool { + let Some(args) = args else { + return false; + }; + + let mut has_explicit = false; + + for arg in args.args { + match arg { + rustc_hir::GenericArg::Type(_) | rustc_hir::GenericArg::Const(_) => { + has_explicit = true; + }, + rustc_hir::GenericArg::Infer(_) => return false, + rustc_hir::GenericArg::Lifetime(_) => {}, + } + } + + has_explicit +} + +// Controls whether the receiver path walk is looking for an outer method +// receiver or for a context where linting should stop. +#[derive(Copy, Clone)] +enum ReceiverPathMode { + FindReceiver, + FindLintBlockingContext, +} + +enum ReceiverPathResult { + Continue(HirId), + Stop(bool), +} + +fn stop_if_lint_blocking_else_continue(parent_hir_id: HirId, mode: ReceiverPathMode) -> ReceiverPathResult { + if matches!(mode, ReceiverPathMode::FindLintBlockingContext) { + ReceiverPathResult::Stop(true) + } else { + ReceiverPathResult::Continue(parent_hir_id) + } +} + +fn walk_receiver_path_method_call( + cx: &LateContext<'_>, + current_hir_id: HirId, + parent: &Expr<'_>, + segment: &rustc_hir::PathSegment<'_>, + receiver: &Expr<'_>, + args: &[Expr<'_>], + mode: ReceiverPathMode, +) -> ReceiverPathResult { + if receiver.hir_id == current_hir_id { + return if matches!(mode, ReceiverPathMode::FindLintBlockingContext) { + ReceiverPathResult::Continue(parent.hir_id) + } else { + ReceiverPathResult::Stop(true) + }; + } + + let Some(arg_index) = args.iter().position(|arg| arg.hir_id == current_hir_id) else { + return ReceiverPathResult::Stop(false); + }; + + let passthrough = !has_explicit_type_or_const_args(segment.args) + && cx + .typeck_results() + .type_dependent_def_id(parent.hir_id) + .is_some_and(|def_id| output_depends_on_input_param(cx, def_id, arg_index + 1)); + + if matches!(mode, ReceiverPathMode::FindLintBlockingContext) { + if passthrough + || args.iter().any(|arg| { + arg.hir_id != current_hir_id + && get_numeric_literal(arg).is_none() + && !cx.typeck_results().expr_ty(arg).is_primitive() + }) + { + ReceiverPathResult::Stop(true) + } else { + ReceiverPathResult::Continue(parent.hir_id) + } + } else if passthrough { + ReceiverPathResult::Continue(parent.hir_id) + } else { + ReceiverPathResult::Stop(false) + } +} + +fn walk_receiver_path_call( + cx: &LateContext<'_>, + current_hir_id: HirId, + parent: &Expr<'_>, + callee: &Expr<'_>, + args: &[Expr<'_>], + mode: ReceiverPathMode, +) -> ReceiverPathResult { + if callee.hir_id == current_hir_id { + return ReceiverPathResult::Continue(parent.hir_id); + } + + let Some(arg_index) = args.iter().position(|arg| arg.hir_id == current_hir_id) else { + return ReceiverPathResult::Stop(false); + }; + + let passthrough = if let ExprKind::Path(qpath) = callee.kind + && let Res::Def(DefKind::Fn, def_id) = cx.qpath_res(&qpath, callee.hir_id) + { + let has_explicit_args = match &qpath { + QPath::Resolved(_, path) => path + .segments + .last() + .is_some_and(|seg| has_explicit_type_or_const_args(seg.args)), + QPath::TypeRelative(_, segment) => has_explicit_type_or_const_args(segment.args), + }; + + !has_explicit_args && output_depends_on_input_param(cx, def_id, arg_index) + } else { + false + }; + + if matches!(mode, ReceiverPathMode::FindLintBlockingContext) { + ReceiverPathResult::Stop(passthrough) + } else if passthrough { + ReceiverPathResult::Continue(parent.hir_id) + } else { + ReceiverPathResult::Stop(false) + } +} + +// Walk one step up the receiver path for the current mode. +fn walk_receiver_path_step(cx: &LateContext<'_>, current_hir_id: HirId, mode: ReceiverPathMode) -> ReceiverPathResult { + match cx.tcx.parent_hir_node(current_hir_id) { + Node::Expr(parent) => match parent.kind { + // Main case. + // The current node may be the receiver. + // Or it may flow through a passthrough method. + ExprKind::MethodCall(segment, receiver, args, _) => { + walk_receiver_path_method_call(cx, current_hir_id, parent, segment, receiver, args, mode) + }, + // Regular calls only keep the path alive + // if the output still depends on this input. + ExprKind::Call(callee, args) => walk_receiver_path_call(cx, current_hir_id, parent, callee, args, mode), + // A sibling that is not primitive blocks the lint. + ExprKind::Binary(_, left, right) | ExprKind::Index(left, right, _) + if left.hir_id == current_hir_id || right.hir_id == current_hir_id => + { + if matches!(mode, ReceiverPathMode::FindLintBlockingContext) { + let sibling = if left.hir_id == current_hir_id { right } else { left }; + if get_numeric_literal(sibling).is_none() && !cx.typeck_results().expr_ty(sibling).is_primitive() { + ReceiverPathResult::Stop(true) + } else { + ReceiverPathResult::Continue(parent.hir_id) + } + } else { + ReceiverPathResult::Continue(parent.hir_id) + } + }, + // These expressions don't block the lint, so we continue walking up the path. + ExprKind::Unary(_, inner) + | ExprKind::Cast(inner, _) + | ExprKind::AddrOf(_, _, inner) + | ExprKind::Field(inner, _) + | ExprKind::DropTemps(inner) + if inner.hir_id == current_hir_id => + { + ReceiverPathResult::Continue(parent.hir_id) + }, + // A block can forward its tail expression, so we keep walking through it. + ExprKind::Block(block, _) + if block.hir_id == current_hir_id || block.expr.is_some_and(|tail| tail.hir_id == current_hir_id) => + { + ReceiverPathResult::Continue(parent.hir_id) + }, + // Depending on the mode, either keep walking or block the lint. + ExprKind::Loop(block, ..) if block.hir_id == current_hir_id => { + stop_if_lint_blocking_else_continue(parent.hir_id, mode) + }, + // Tuples and arrays wrap the current expression, so we continue walking up the path. + ExprKind::Tup(exprs) | ExprKind::Array(exprs) if exprs.iter().any(|e| e.hir_id == current_hir_id) => { + ReceiverPathResult::Continue(parent.hir_id) + }, + // The expression is stored in a field. We continue walking up the path to see how the struct is used. + ExprKind::Struct(_, fields, _) + if fields + .iter() + .any(|field| field.hir_id == current_hir_id || field.expr.hir_id == current_hir_id) => + { + ReceiverPathResult::Continue(parent.hir_id) + }, + // Depending on the mode, either keep walking or block the lint. + ExprKind::If(cond, then_expr, else_expr) + if cond.hir_id == current_hir_id + || then_expr.hir_id == current_hir_id + || else_expr.is_some_and(|else_expr| else_expr.hir_id == current_hir_id) => + { + stop_if_lint_blocking_else_continue(parent.hir_id, mode) + }, + // Depending on the mode, either keep walking or block the lint. + ExprKind::Match(scrutinee, arms, _) + if scrutinee.hir_id == current_hir_id + || arms + .iter() + .any(|arm| arm.hir_id == current_hir_id || arm.body.hir_id == current_hir_id) => + { + stop_if_lint_blocking_else_continue(parent.hir_id, mode) + }, + // Depending on the mode, either keep walking or block the lint. + ExprKind::Break(_, Some(inner)) if inner.hir_id == current_hir_id => { + stop_if_lint_blocking_else_continue(parent.hir_id, mode) + }, + _ => ReceiverPathResult::Stop(false), + }, + // These are structural HIR nodes. We just skip them and keep walking. + Node::ExprField(_) | Node::Block(_) | Node::Arm(_) | Node::Stmt(_) => { + ReceiverPathResult::Continue(cx.tcx.parent_hir_id(current_hir_id)) + }, + // Handle `let x = init; x` in the same block. + // Depending on the mode, either keep walking init or block the lint. + Node::LetStmt(local) => { + if let Some(block_hir_id) = let_init_to_block_hir_id(cx, local, current_hir_id) { + stop_if_lint_blocking_else_continue(block_hir_id, mode) + } else { + ReceiverPathResult::Stop(false) + } + }, + _ => ReceiverPathResult::Stop(false), + } +} + +// Returns `true` if `expr` eventually becomes the receiver of an outer method call. +fn feeds_outer_method_receiver(cx: &LateContext<'_>, expr: &Expr<'_>) -> bool { + let mut current_hir_id = expr.hir_id; + + loop { + match walk_receiver_path_step(cx, current_hir_id, ReceiverPathMode::FindReceiver) { + ReceiverPathResult::Continue(next) => current_hir_id = next, + ReceiverPathResult::Stop(result) => return result, + } + } +} + +// Returns `true` if the receiver path contains a context that should block the lint. +fn has_lint_blocking_context_on_receiver_path(cx: &LateContext<'_>, expr: &Expr<'_>) -> bool { + let mut current_hir_id = expr.hir_id; + + loop { + match walk_receiver_path_step(cx, current_hir_id, ReceiverPathMode::FindLintBlockingContext) { + ReceiverPathResult::Continue(next) => current_hir_id = next, + ReceiverPathResult::Stop(result) => return result, + } + } +} + +// If the initializer flows into the tail expression of the same block, returns that block HirId. +fn let_init_to_block_hir_id( + cx: &LateContext<'_>, + local: &rustc_hir::LetStmt<'_>, + current_hir_id: HirId, +) -> Option { + let init = local.init?; + if init.hir_id != current_hir_id { + return None; + } + + let stmt_hir_id = match cx.tcx.parent_hir_node(local.hir_id) { + Node::Stmt(stmt) => stmt.hir_id, + _ => return None, + }; + + let Node::Block(block) = cx.tcx.parent_hir_node(stmt_hir_id) else { + return None; + }; + + let tail = block.expr?; + let binding_hir_id = tail.res_local_id()?; + + match local.pat.kind { + rustc_hir::PatKind::Binding(_, local_hir_id, ..) if local_hir_id == binding_hir_id => Some(block.hir_id), + _ => None, + } +} diff --git a/src/tools/clippy/clippy_lints/src/cognitive_complexity.rs b/src/tools/clippy/clippy_lints/src/cognitive_complexity.rs index 911ca306aca4..95b99c1d2435 100644 --- a/src/tools/clippy/clippy_lints/src/cognitive_complexity.rs +++ b/src/tools/clippy/clippy_lints/src/cognitive_complexity.rs @@ -145,7 +145,7 @@ fn check_fn( def_id: LocalDefId, ) { #[allow(deprecated)] - if !cx.tcx.has_attr(def_id, sym::test) { + if cx.tcx.get_attrs(def_id, sym::test).next().is_none() { let expr = if kind.asyncness().is_async() { match get_async_fn_body(cx.tcx, body) { Some(b) => b, diff --git a/src/tools/clippy/clippy_lints/src/collapsible_if.rs b/src/tools/clippy/clippy_lints/src/collapsible_if.rs index ca04ce1764ff..52e602bbac57 100644 --- a/src/tools/clippy/clippy_lints/src/collapsible_if.rs +++ b/src/tools/clippy/clippy_lints/src/collapsible_if.rs @@ -3,12 +3,11 @@ use clippy_utils::msrvs::Msrv; use clippy_utils::source::{HasSession, IntoSpan as _, SpanRangeExt, snippet, snippet_block_with_applicability}; use clippy_utils::{can_use_if_let_chains, span_contains_cfg, span_contains_non_whitespace, sym, tokenize_with_text}; -use rustc_ast::BinOpKind; +use rustc_ast::{BinOpKind, MetaItemInner}; use rustc_errors::Applicability; -use rustc_hir::attrs::{AttributeKind, LintAttributeKind}; -use rustc_hir::{Attribute, Block, Expr, ExprKind, StmtKind}; +use rustc_hir::{Block, Expr, ExprKind, StmtKind}; use rustc_lexer::TokenKind; -use rustc_lint::{LateContext, LateLintPass}; +use rustc_lint::{LateContext, LateLintPass, Level}; use rustc_session::impl_lint_pass; use rustc_span::{BytePos, Span, Symbol}; @@ -238,24 +237,19 @@ fn check_significant_tokens_and_expect_attrs( !span_contains_non_whitespace(cx, span, self.lint_commented_code) }, - [Attribute::Parsed(AttributeKind::LintAttributes(sub_attrs))] => { - sub_attrs - .into_iter() - .filter(|attr| attr.kind == LintAttributeKind::Expect) - .flat_map(|attr| attr.lint_instances.iter().map(|group| (attr.attr_span, group))) - .filter(|(_, lint_id)| { - lint_id.tool_is_named(sym::clippy) - && (expected_lint_name == lint_id.lint_name() - || [expected_lint_name, sym::style, sym::all] - .contains(&lint_id.original_name_without_tool())) - }) - .any(|(attr_span, _)| { - // There is an `expect` attribute -- check that there is no _other_ significant text - let span_before_attr = inner_if.span.split_at(1).1.until(attr_span); - let span_after_attr = attr_span.between(inner_if_expr.span); - !span_contains_non_whitespace(cx, span_before_attr, self.lint_commented_code) - && !span_contains_non_whitespace(cx, span_after_attr, self.lint_commented_code) - }) + [attr] + if matches!(Level::from_attr(attr), Some((Level::Expect, _))) + && let Some(metas) = attr.meta_item_list() + && let Some(MetaItemInner::MetaItem(meta_item)) = metas.first() + && let [tool, lint_name] = meta_item.path.segments.as_slice() + && tool.ident.name == sym::clippy + && [expected_lint_name, sym::style, sym::all].contains(&lint_name.ident.name) => + { + // There is an `expect` attribute -- check that there is no _other_ significant text + let span_before_attr = inner_if.span.split_at(1).1.until(attr.span()); + let span_after_attr = attr.span().between(inner_if_expr.span); + !span_contains_non_whitespace(cx, span_before_attr, self.lint_commented_code) + && !span_contains_non_whitespace(cx, span_after_attr, self.lint_commented_code) }, // There are other attributes, which are significant tokens -- check failed diff --git a/src/tools/clippy/clippy_lints/src/dereference.rs b/src/tools/clippy/clippy_lints/src/dereference.rs index 89a6d445e818..ebaa7a39213d 100644 --- a/src/tools/clippy/clippy_lints/src/dereference.rs +++ b/src/tools/clippy/clippy_lints/src/dereference.rs @@ -4,7 +4,7 @@ use clippy_utils::sugg::has_enclosing_paren; use clippy_utils::ty::{adjust_derefs_manually_drop, implements_trait, is_manually_drop, peel_and_count_ty_refs}; use clippy_utils::{ - DefinedTy, ExprUseNode, expr_use_ctxt, get_parent_expr, is_block_like, is_from_proc_macro, is_lint_allowed, sym, + DefinedTy, ExprUseNode, get_expr_use_site, get_parent_expr, is_block_like, is_from_proc_macro, is_lint_allowed, sym, }; use rustc_ast::util::parser::ExprPrecedence; use rustc_data_structures::fx::FxIndexMap; @@ -19,7 +19,7 @@ use rustc_middle::ty::adjustment::{Adjust, Adjustment, AutoBorrow, AutoBorrowMutability}; use rustc_middle::ty::{self, Ty, TyCtxt, TypeVisitableExt, TypeckResults}; use rustc_session::impl_lint_pass; -use rustc_span::{Span, Symbol}; +use rustc_span::{Span, Symbol, SyntaxContext}; use std::borrow::Cow; declare_clippy_lint! { @@ -276,15 +276,15 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { match (self.state.take(), kind) { (None, kind) => { let expr_ty = typeck.expr_ty(expr); - let use_cx = expr_use_ctxt(cx, expr); - let adjusted_ty = use_cx.adjustments.last().map_or(expr_ty, |a| a.target); + let use_site = get_expr_use_site(cx.tcx, typeck, SyntaxContext::root(), expr); + let adjusted_ty = use_site.adjustments.last().map_or(expr_ty, |a| a.target); match kind { - RefOp::Deref if use_cx.same_ctxt => { - let use_node = use_cx.use_node(cx); + RefOp::Deref if use_site.same_ctxt => { + let use_node = use_site.use_node(cx); let sub_ty = typeck.expr_ty(sub_expr); if let ExprUseNode::FieldAccess(name) = use_node - && !use_cx.moved_before_use + && !use_site.moved_before_use && !ty_contains_field(sub_ty, name.name) { self.state = Some(( @@ -331,9 +331,9 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { }, )); }, - RefOp::AddrOf(mutability) if use_cx.same_ctxt => { + RefOp::AddrOf(mutability) if use_site.same_ctxt => { // Find the number of times the borrow is auto-derefed. - let mut iter = use_cx.adjustments.iter(); + let mut iter = use_site.adjustments.iter(); let mut deref_count = 0usize; let next_adjust = loop { match iter.next() { @@ -350,13 +350,13 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { } }; - let use_node = use_cx.use_node(cx); + let use_node = use_site.use_node(cx); let stability = use_node.defined_ty(cx).map_or(TyCoercionStability::None, |ty| { TyCoercionStability::for_defined_ty(cx, ty, use_node.is_return()) }); let can_auto_borrow = match use_node { ExprUseNode::FieldAccess(_) - if !use_cx.moved_before_use && matches!(sub_expr.kind, ExprKind::Field(..)) => + if !use_site.moved_before_use && matches!(sub_expr.kind, ExprKind::Field(..)) => { // `DerefMut` will not be automatically applied to `ManuallyDrop<_>` // field expressions when the base type is a union and the parent @@ -364,10 +364,10 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { // // e.g. `&mut x.y.z` where `x` is a union, and accessing `z` requires a // deref through `ManuallyDrop<_>` will not compile. - !adjust_derefs_manually_drop(use_cx.adjustments, expr_ty) + !adjust_derefs_manually_drop(use_site.adjustments, expr_ty) }, - ExprUseNode::Callee | ExprUseNode::FieldAccess(_) if !use_cx.moved_before_use => true, - ExprUseNode::MethodArg(hir_id, _, 0) if !use_cx.moved_before_use => { + ExprUseNode::Callee | ExprUseNode::FieldAccess(_) if !use_site.moved_before_use => true, + ExprUseNode::MethodArg(hir_id, _, 0) if !use_site.moved_before_use => { // Check for calls to trait methods where the trait is implemented // on a reference. // Two cases need to be handled: @@ -455,7 +455,7 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { msg, stability, for_field_access: if let ExprUseNode::FieldAccess(name) = use_node - && !use_cx.moved_before_use + && !use_site.moved_before_use { Some(name.name) } else { diff --git a/src/tools/clippy/clippy_lints/src/derive/derive_partial_eq_without_eq.rs b/src/tools/clippy/clippy_lints/src/derive/derive_partial_eq_without_eq.rs index fbace0bd73ac..3782c1dab355 100644 --- a/src/tools/clippy/clippy_lints/src/derive/derive_partial_eq_without_eq.rs +++ b/src/tools/clippy/clippy_lints/src/derive/derive_partial_eq_without_eq.rs @@ -85,8 +85,5 @@ fn typing_env_for_derived_eq(tcx: TyCtxt<'_>, did: DefId, eq_trait_id: DefId) -> .upcast(tcx) }), ))); - ty::TypingEnv { - typing_mode: ty::TypingMode::non_body_analysis(), - param_env, - } + ty::TypingEnv::new(param_env, ty::TypingMode::non_body_analysis()) } diff --git a/src/tools/clippy/clippy_lints/src/disallowed_fields.rs b/src/tools/clippy/clippy_lints/src/disallowed_fields.rs index 9873c32f427f..28fcb46c50b6 100644 --- a/src/tools/clippy/clippy_lints/src/disallowed_fields.rs +++ b/src/tools/clippy/clippy_lints/src/disallowed_fields.rs @@ -50,7 +50,7 @@ /// let range = Range { start: 0, end: 1 }; /// println!("{}", range.end); // `end` is _not_ disallowed in the config. /// ``` - #[clippy::version = "1.93.0"] + #[clippy::version = "1.95.0"] pub DISALLOWED_FIELDS, style, "declaration of a disallowed field use" diff --git a/src/tools/clippy/clippy_lints/src/eta_reduction.rs b/src/tools/clippy/clippy_lints/src/eta_reduction.rs index 3562200cbd92..229af104799d 100644 --- a/src/tools/clippy/clippy_lints/src/eta_reduction.rs +++ b/src/tools/clippy/clippy_lints/src/eta_reduction.rs @@ -4,7 +4,6 @@ use clippy_utils::source::{snippet_opt, snippet_with_applicability}; use clippy_utils::usage::{local_used_after_expr, local_used_in}; use clippy_utils::{get_path_from_caller_to_method_type, is_adjusted, is_no_std_crate}; -use rustc_abi::ExternAbi; use rustc_errors::Applicability; use rustc_hir::{BindingMode, Expr, ExprKind, FnRetTy, GenericArgs, Param, PatKind, QPath, Safety, TyKind, find_attr}; use rustc_infer::infer::TyCtxtInferExt; @@ -173,7 +172,7 @@ fn check_closure<'tcx>(cx: &LateContext<'tcx>, outer_receiver: Option<&Expr<'tcx && let output = typeck.expr_ty(body.value) && let ty::Tuple(tys) = *subs.type_at(1).kind() { - cx.tcx.mk_fn_sig(tys, output, false, Safety::Safe, ExternAbi::Rust) + cx.tcx.mk_fn_sig_safe_rust_abi(tys, output) } else { return; } @@ -318,7 +317,7 @@ fn check_inputs( } fn check_sig<'tcx>(closure_sig: FnSig<'tcx>, call_sig: FnSig<'tcx>) -> bool { - call_sig.safety.is_safe() && !has_late_bound_to_non_late_bound_regions(closure_sig, call_sig) + call_sig.safety().is_safe() && !has_late_bound_to_non_late_bound_regions(closure_sig, call_sig) } /// This walks through both signatures and checks for any time a late-bound region is expected by an diff --git a/src/tools/clippy/clippy_lints/src/float_literal.rs b/src/tools/clippy/clippy_lints/src/float_literal.rs index c6ae2cfc2545..ab1f5b88bace 100644 --- a/src/tools/clippy/clippy_lints/src/float_literal.rs +++ b/src/tools/clippy/clippy_lints/src/float_literal.rs @@ -1,6 +1,6 @@ use clippy_config::Conf; use clippy_utils::diagnostics::span_lint_and_then; -use clippy_utils::{ExprUseNode, expr_use_ctxt, numeric_literal}; +use clippy_utils::{ExprUseNode, get_expr_use_site, numeric_literal}; use rustc_ast::ast::{LitFloatType, LitKind}; use rustc_errors::Applicability; use rustc_hir as hir; @@ -143,7 +143,10 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx hir::Expr<'_>) { } } else if digits > max as usize && count_digits(&float_str) < digits { if digits >= self.const_literal_digits_threshold - && matches!(expr_use_ctxt(cx, expr).use_node(cx), ExprUseNode::ConstStatic(_)) + && matches!( + get_expr_use_site(cx.tcx, cx.typeck_results(), expr.span.ctxt(), expr).use_node(cx), + ExprUseNode::ConstStatic(_) + ) { // If a big enough number of digits is specified and it's a constant // we assume the user is definining a constant, and excessive precision is ok diff --git a/src/tools/clippy/clippy_lints/src/functions/misnamed_getters.rs b/src/tools/clippy/clippy_lints/src/functions/misnamed_getters.rs index fa63876410f0..215039952ca5 100644 --- a/src/tools/clippy/clippy_lints/src/functions/misnamed_getters.rs +++ b/src/tools/clippy/clippy_lints/src/functions/misnamed_getters.rs @@ -23,7 +23,7 @@ pub fn check_fn(cx: &LateContext<'_>, kind: FnKind<'_>, decl: &FnDecl<'_>, body: let name = ident.name.as_str(); - let name = match decl.implicit_self { + let name = match decl.implicit_self() { ImplicitSelfKind::RefMut => { let Some(name) = name.strip_suffix("_mut") else { return; diff --git a/src/tools/clippy/clippy_lints/src/functions/not_unsafe_ptr_arg_deref.rs b/src/tools/clippy/clippy_lints/src/functions/not_unsafe_ptr_arg_deref.rs index c6b0e7c54c06..e49dee4164b8 100644 --- a/src/tools/clippy/clippy_lints/src/functions/not_unsafe_ptr_arg_deref.rs +++ b/src/tools/clippy/clippy_lints/src/functions/not_unsafe_ptr_arg_deref.rs @@ -59,7 +59,7 @@ fn check_raw_ptr<'tcx>( }, hir::ExprKind::MethodCall(_, recv, args, _) => { let def_id = typeck.type_dependent_def_id(e.hir_id).unwrap(); - if cx.tcx.fn_sig(def_id).skip_binder().skip_binder().safety.is_unsafe() { + if cx.tcx.fn_sig(def_id).skip_binder().skip_binder().safety().is_unsafe() { check_arg(cx, &raw_ptrs, recv); for arg in args { check_arg(cx, &raw_ptrs, arg); diff --git a/src/tools/clippy/clippy_lints/src/implicit_saturating_sub.rs b/src/tools/clippy/clippy_lints/src/implicit_saturating_sub.rs index ee3619ea6746..666c4cb737f4 100644 --- a/src/tools/clippy/clippy_lints/src/implicit_saturating_sub.rs +++ b/src/tools/clippy/clippy_lints/src/implicit_saturating_sub.rs @@ -3,7 +3,7 @@ use clippy_config::Conf; use clippy_utils::diagnostics::{span_lint_and_sugg, span_lint_and_then}; use clippy_utils::msrvs::{self, Msrv}; -use clippy_utils::source::snippet_with_applicability; +use clippy_utils::source::snippet_with_context; use clippy_utils::sugg::{Sugg, make_binop}; use clippy_utils::{ SpanlessEq, eq_expr_value, higher, is_in_const_context, is_integer_literal, is_integer_literal_untyped, @@ -246,33 +246,35 @@ fn check_subtraction( // This part of the condition is voluntarily split from the one before to ensure that // if `snippet_opt` fails, it won't try the next conditions. if !is_in_const_context(cx) || msrv.meets(cx, msrvs::SATURATING_SUB_CONST) { - let mut applicability = Applicability::MachineApplicable; - let big_expr_sugg = (if is_integer_literal_untyped(big_expr) { - let get_snippet = |span: Span| { - let snippet = snippet_with_applicability(cx, span, "..", &mut applicability); - let big_expr_ty = cx.typeck_results().expr_ty(big_expr); - Cow::Owned(format!("{snippet}_{big_expr_ty}")) - }; - Sugg::hir_from_snippet(cx, big_expr, get_snippet) - } else { - Sugg::hir_with_applicability(cx, big_expr, "..", &mut applicability) - }) - .maybe_paren(); - let little_expr_sugg = Sugg::hir_with_applicability(cx, little_expr, "..", &mut applicability); - - let sugg = format!( - "{}{big_expr_sugg}.saturating_sub({little_expr_sugg}){}", - if is_composited { "{ " } else { "" }, - if is_composited { " }" } else { "" } - ); - span_lint_and_sugg( + span_lint_and_then( cx, IMPLICIT_SATURATING_SUB, expr_span, "manual arithmetic check found", - "replace it with", - sugg, - applicability, + |diag| { + let mut applicability = Applicability::MachineApplicable; + let expr_span_ctxt = expr_span.ctxt(); + let big_expr_sugg = (if is_integer_literal_untyped(big_expr) { + let get_snippet = |span: Span| { + let (snippet, _) = + snippet_with_context(cx, span, expr_span_ctxt, "..", &mut applicability); + let big_expr_ty = cx.typeck_results().expr_ty(big_expr); + Cow::Owned(format!("{snippet}_{big_expr_ty}")) + }; + Sugg::hir_from_snippet(cx, big_expr, get_snippet) + } else { + Sugg::hir_with_context(cx, big_expr, expr_span_ctxt, "..", &mut applicability) + }) + .maybe_paren(); + let little_expr_sugg = + Sugg::hir_with_context(cx, little_expr, expr_span_ctxt, "..", &mut applicability); + let sugg = format!( + "{}{big_expr_sugg}.saturating_sub({little_expr_sugg}){}", + if is_composited { "{ " } else { "" }, + if is_composited { " }" } else { "" } + ); + diag.span_suggestion(expr_span, "replace it with", sugg, applicability); + }, ); } } else if eq_expr_value(cx, left, little_expr) diff --git a/src/tools/clippy/clippy_lints/src/inherent_to_string.rs b/src/tools/clippy/clippy_lints/src/inherent_to_string.rs index 22082646eb31..afe2a1033cee 100644 --- a/src/tools/clippy/clippy_lints/src/inherent_to_string.rs +++ b/src/tools/clippy/clippy_lints/src/inherent_to_string.rs @@ -103,7 +103,7 @@ fn check_impl_item(&mut self, cx: &LateContext<'tcx>, impl_item: &'tcx ImplItem< && header.abi == ExternAbi::Rust && impl_item.ident.name == sym::to_string && let decl = signature.decl - && decl.implicit_self.has_implicit_self() + && decl.implicit_self().has_implicit_self() && decl.inputs.len() == 1 && impl_item.generics.params.iter().all(|p| matches!(p.kind, GenericParamKind::Lifetime { .. })) && !impl_item.span.from_expansion() diff --git a/src/tools/clippy/clippy_lints/src/int_plus_one.rs b/src/tools/clippy/clippy_lints/src/int_plus_one.rs index f8184b30f400..524cb6bf7536 100644 --- a/src/tools/clippy/clippy_lints/src/int_plus_one.rs +++ b/src/tools/clippy/clippy_lints/src/int_plus_one.rs @@ -1,6 +1,7 @@ use clippy_utils::diagnostics::span_lint_and_then; use clippy_utils::sugg; use rustc_ast::ast::{BinOpKind, Expr, ExprKind, LitKind, UnOp}; +use rustc_ast::util::parser::AssocOp; use rustc_data_structures::packed::Pu128; use rustc_errors::Applicability; use rustc_lint::{EarlyContext, EarlyLintPass}; @@ -134,12 +135,19 @@ fn emit_warning(cx: &EarlyContext<'_>, expr: &Expr, new_lhs: &Expr, le_or_ge: Le |diag| { let mut app = Applicability::MachineApplicable; let ctxt = expr.span.ctxt(); - let new_lhs = sugg::Sugg::ast(cx, new_lhs, "_", ctxt, &mut app); + let mut new_lhs = sugg::Sugg::ast(cx, new_lhs, "_", ctxt, &mut app); let new_rhs = sugg::Sugg::ast(cx, new_rhs, "_", ctxt, &mut app); let new_binop = match le_or_ge { LeOrGe::Ge => BinOpKind::Gt, LeOrGe::Le => BinOpKind::Lt, }; + // When the replacement operator is `<`, an `as` cast on the LHS + // must be parenthesized. Otherwise, the parser interprets the `<` + // as the start of generic arguments on the cast type + // (e.g., `x as usize < y` is parsed as `x as usize`). + if matches!(new_lhs, sugg::Sugg::BinOp(AssocOp::Cast, ..)) && new_binop == BinOpKind::Lt { + new_lhs = new_lhs.maybe_paren(); + } let rec = sugg::make_binop(new_binop, &new_lhs, &new_rhs); diag.span_suggestion(expr.span, "change it to", rec, app); }, diff --git a/src/tools/clippy/clippy_lints/src/item_name_repetitions.rs b/src/tools/clippy/clippy_lints/src/item_name_repetitions.rs index 70df856570b2..06bea4ba1ffd 100644 --- a/src/tools/clippy/clippy_lints/src/item_name_repetitions.rs +++ b/src/tools/clippy/clippy_lints/src/item_name_repetitions.rs @@ -528,7 +528,7 @@ fn check_item(&mut self, cx: &LateContext<'_>, item: &Item<'_>) { | ItemKind::Fn { ident, .. } | ItemKind::Macro(ident, ..) | ItemKind::Static(_, ident, ..) - | ItemKind::Trait(_, _, _, ident, ..) + | ItemKind::Trait(_, _, _, _, ident, ..) | ItemKind::TraitAlias(_, ident, ..) | ItemKind::TyAlias(ident, ..) | ItemKind::Union(ident, ..) diff --git a/src/tools/clippy/clippy_lints/src/iter_not_returning_iterator.rs b/src/tools/clippy/clippy_lints/src/iter_not_returning_iterator.rs index 753360906d66..73e4a856c046 100644 --- a/src/tools/clippy/clippy_lints/src/iter_not_returning_iterator.rs +++ b/src/tools/clippy/clippy_lints/src/iter_not_returning_iterator.rs @@ -64,7 +64,7 @@ fn check_impl_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx ImplItem<'tcx> } fn check_sig(cx: &LateContext<'_>, name: Symbol, sig: &FnSig<'_>, fn_id: LocalDefId) { - if sig.decl.implicit_self.has_implicit_self() { + if sig.decl.implicit_self().has_implicit_self() { let ret_ty = cx .tcx .instantiate_bound_regions_with_erased(cx.tcx.fn_sig(fn_id).instantiate_identity().output()); diff --git a/src/tools/clippy/clippy_lints/src/iter_without_into_iter.rs b/src/tools/clippy/clippy_lints/src/iter_without_into_iter.rs index 4e56f9c8472d..369037dad94f 100644 --- a/src/tools/clippy/clippy_lints/src/iter_without_into_iter.rs +++ b/src/tools/clippy/clippy_lints/src/iter_without_into_iter.rs @@ -205,7 +205,7 @@ fn check_impl_item(&mut self, cx: &LateContext<'_>, item: &rustc_hir::ImplItem<' && let FnRetTy::Return(ret) = sig.decl.output && is_nameable_in_impl_trait(ret) && cx.tcx.generics_of(item_did).is_own_empty() - && sig.decl.implicit_self == expected_implicit_self + && sig.decl.implicit_self() == expected_implicit_self && sig.decl.inputs.len() == 1 && let Some(imp) = get_parent_as_impl(cx.tcx, item.hir_id()) && imp.of_trait.is_none() diff --git a/src/tools/clippy/clippy_lints/src/len_without_is_empty.rs b/src/tools/clippy/clippy_lints/src/len_without_is_empty.rs index ae53bd608552..de6ccf56ab2a 100644 --- a/src/tools/clippy/clippy_lints/src/len_without_is_empty.rs +++ b/src/tools/clippy/clippy_lints/src/len_without_is_empty.rs @@ -44,7 +44,7 @@ impl<'tcx> LateLintPass<'tcx> for LenWithoutIsEmpty { fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'_>) { - if let ItemKind::Trait(_, _, _, ident, _, _, trait_items) = item.kind + if let ItemKind::Trait(_, _, _, _, ident, _, _, trait_items) = item.kind && !item.span.from_expansion() { check_trait_items(cx, item, ident, trait_items); @@ -54,7 +54,7 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'_>) { fn check_impl_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx ImplItem<'_>) { if item.ident.name == sym::len && let ImplItemKind::Fn(sig, _) = &item.kind - && sig.decl.implicit_self.has_implicit_self() + && sig.decl.implicit_self().has_implicit_self() && sig.decl.inputs.len() == 1 && cx.effective_visibilities.is_exported(item.owner_id.def_id) && matches!(sig.decl.output, FnRetTy::Return(_)) @@ -79,7 +79,7 @@ fn check_impl_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx ImplItem<'_>) check_for_is_empty( cx, sig.span, - sig.decl.implicit_self, + sig.decl.implicit_self(), output, ty_id, name, diff --git a/src/tools/clippy/clippy_lints/src/lib.rs b/src/tools/clippy/clippy_lints/src/lib.rs index 68a8f51e7f4d..72ee5cca0397 100644 --- a/src/tools/clippy/clippy_lints/src/lib.rs +++ b/src/tools/clippy/clippy_lints/src/lib.rs @@ -515,7 +515,6 @@ pub fn register_lint_passes(store: &mut rustc_lint::LintStore, conf: &'static Co Box::new(|| Box::new(visibility::Visibility)), Box::new(|| Box::new(multiple_bound_locations::MultipleBoundLocations)), Box::new(|| Box::new(field_scoped_visibility_modifiers::FieldScopedVisibilityModifiers)), - Box::new(|| Box::new(byte_char_slices::ByteCharSlice)), Box::new(|| Box::new(cfg_not_test::CfgNotTest)), Box::new(|| Box::new(empty_line_after::EmptyLineAfter::new())), // add early passes here, used by `cargo dev new_lint` @@ -866,7 +865,8 @@ pub fn register_lint_passes(store: &mut rustc_lint::LintStore, conf: &'static Co Box::new(move |_| Box::new(manual_take::ManualTake::new(conf))), Box::new(|_| Box::new(manual_checked_ops::ManualCheckedOps)), Box::new(move |tcx| Box::new(manual_pop_if::ManualPopIf::new(tcx, conf))), - Box::new(|_| Box::new(manual_noop_waker::ManualNoopWaker)), + Box::new(move |_| Box::new(manual_noop_waker::ManualNoopWaker::new(conf))), + Box::new(|_| Box::new(byte_char_slices::ByteCharSlice)), // add late passes here, used by `cargo dev new_lint` ]; store.late_passes.extend(late_lints); diff --git a/src/tools/clippy/clippy_lints/src/lifetimes.rs b/src/tools/clippy/clippy_lints/src/lifetimes.rs index 0bb4992cf6bb..ea99b523f09b 100644 --- a/src/tools/clippy/clippy_lints/src/lifetimes.rs +++ b/src/tools/clippy/clippy_lints/src/lifetimes.rs @@ -411,7 +411,7 @@ fn allowed_lts_from(named_generics: &[GenericParam<'_>]) -> FxIndexSet(cx: &LateContext<'tcx>, func: &FnDecl<'tcx>, ident: Option, msrv: Msrv) -> bool { if let Some(ident) = ident && ident.name == kw::SelfLower - && !func.implicit_self.has_implicit_self() + && !func.implicit_self().has_implicit_self() && let Some(self_ty) = func.inputs.first() && !msrv.meets(cx, msrvs::EXPLICIT_SELF_TYPE_ELISION) { @@ -697,7 +697,7 @@ fn visit_lifetime(&mut self, lifetime: &Lifetime) -> Self::Result { } } - if fd.lifetime_elision_allowed + if fd.lifetime_elision_allowed() && let Return(ret_ty) = fd.output && walk_unambig_ty(&mut V, ret_ty).is_break() { diff --git a/src/tools/clippy/clippy_lints/src/manual_is_power_of_two.rs b/src/tools/clippy/clippy_lints/src/manual_is_power_of_two.rs index 2ba79113e7bc..4501612540fb 100644 --- a/src/tools/clippy/clippy_lints/src/manual_is_power_of_two.rs +++ b/src/tools/clippy/clippy_lints/src/manual_is_power_of_two.rs @@ -51,7 +51,7 @@ fn build_sugg(&self, cx: &LateContext<'_>, expr: &Expr<'_>, receiver: &Expr<'_>) } let mut applicability = Applicability::MachineApplicable; - let snippet = Sugg::hir_with_applicability(cx, receiver, "_", &mut applicability); + let snippet = Sugg::hir_with_context(cx, receiver, expr.span.ctxt(), "_", &mut applicability); span_lint_and_sugg( cx, diff --git a/src/tools/clippy/clippy_lints/src/manual_noop_waker.rs b/src/tools/clippy/clippy_lints/src/manual_noop_waker.rs index c5de39dbf7f9..fb0e8a1d363f 100644 --- a/src/tools/clippy/clippy_lints/src/manual_noop_waker.rs +++ b/src/tools/clippy/clippy_lints/src/manual_noop_waker.rs @@ -1,8 +1,10 @@ +use clippy_config::Conf; use clippy_utils::diagnostics::span_lint_and_help; +use clippy_utils::msrvs::{self, Msrv}; use clippy_utils::{is_empty_block, sym}; use rustc_hir::{ImplItemKind, Item, ItemKind}; use rustc_lint::{LateContext, LateLintPass}; -use rustc_session::declare_lint_pass; +use rustc_session::impl_lint_pass; declare_clippy_lint! { /// ### What it does @@ -35,7 +37,17 @@ "manual implementations of noop wakers can be simplified using Waker::noop()" } -declare_lint_pass!(ManualNoopWaker => [MANUAL_NOOP_WAKER]); +impl_lint_pass!(ManualNoopWaker => [MANUAL_NOOP_WAKER]); + +pub struct ManualNoopWaker { + msrv: Msrv, +} + +impl ManualNoopWaker { + pub fn new(conf: &'static Conf) -> Self { + Self { msrv: conf.msrv } + } +} impl<'tcx> LateLintPass<'tcx> for ManualNoopWaker { fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'tcx>) { @@ -43,6 +55,7 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'tcx>) { && let Some(trait_ref) = imp.of_trait && let Some(trait_id) = trait_ref.trait_ref.trait_def_id() && cx.tcx.is_diagnostic_item(sym::Wake, trait_id) + && self.msrv.meets(cx, msrvs::WAKER_NOOP) { for impl_item_ref in imp.items { let impl_item = cx diff --git a/src/tools/clippy/clippy_lints/src/manual_rotate.rs b/src/tools/clippy/clippy_lints/src/manual_rotate.rs index e8db44698d9c..c371e5b47df8 100644 --- a/src/tools/clippy/clippy_lints/src/manual_rotate.rs +++ b/src/tools/clippy/clippy_lints/src/manual_rotate.rs @@ -1,7 +1,7 @@ use std::fmt::Display; use clippy_utils::consts::{ConstEvalCtxt, Constant}; -use clippy_utils::diagnostics::span_lint_and_sugg; +use clippy_utils::diagnostics::span_lint_and_then; use clippy_utils::sugg; use rustc_errors::Applicability; use rustc_hir::{BinOpKind, Expr, ExprKind}; @@ -116,17 +116,23 @@ fn check_expr<'tcx>(&mut self, cx: &LateContext<'tcx>, expr: &Expr<'tcx>) { } }; - let mut applicability = Applicability::MachineApplicable; - let expr_sugg = sugg::Sugg::hir_with_applicability(cx, l_expr, "_", &mut applicability).maybe_paren(); - let amount = sugg::Sugg::hir_with_applicability(cx, amount, "_", &mut applicability); - span_lint_and_sugg( + span_lint_and_then( cx, MANUAL_ROTATE, expr.span, "there is no need to manually implement bit rotation", - "this expression can be rewritten as", - format!("{expr_sugg}.{shift_function}({amount})"), - Applicability::MachineApplicable, + |diag| { + let mut applicability = Applicability::MachineApplicable; + let expr_sugg = sugg::Sugg::hir_with_context(cx, l_expr, expr.span.ctxt(), "_", &mut applicability) + .maybe_paren(); + let amount = sugg::Sugg::hir_with_context(cx, amount, expr.span.ctxt(), "_", &mut applicability); + diag.span_suggestion( + expr.span, + "this expression can be rewritten as", + format!("{expr_sugg}.{shift_function}({amount})"), + applicability, + ); + }, ); } } diff --git a/src/tools/clippy/clippy_lints/src/manual_take.rs b/src/tools/clippy/clippy_lints/src/manual_take.rs index a0c701b6c24a..dd8b0554a9ce 100644 --- a/src/tools/clippy/clippy_lints/src/manual_take.rs +++ b/src/tools/clippy/clippy_lints/src/manual_take.rs @@ -33,7 +33,7 @@ /// let mut x = true; /// let _ = std::mem::take(&mut x); /// ``` - #[clippy::version = "1.94.0"] + #[clippy::version = "1.95.0"] pub MANUAL_TAKE, complexity, "manual `mem::take` implementation" diff --git a/src/tools/clippy/clippy_lints/src/matches/manual_filter.rs b/src/tools/clippy/clippy_lints/src/matches/manual_filter.rs index da68f8421c16..9c2d60eb9c57 100644 --- a/src/tools/clippy/clippy_lints/src/matches/manual_filter.rs +++ b/src/tools/clippy/clippy_lints/src/matches/manual_filter.rs @@ -1,12 +1,15 @@ use clippy_utils::as_some_expr; -use clippy_utils::diagnostics::span_lint_and_sugg; +use clippy_utils::diagnostics::{span_lint_and_sugg, span_lint_and_then}; use clippy_utils::res::{MaybeDef, MaybeQPath, MaybeResPath}; +use clippy_utils::source::snippet_with_context; +use clippy_utils::sugg::Sugg; +use clippy_utils::ty::is_copy; use clippy_utils::visitors::contains_unsafe_block; - +use rustc_errors::Applicability; use rustc_hir::LangItem::OptionNone; use rustc_hir::{Arm, Expr, ExprKind, HirId, Pat, PatKind}; use rustc_lint::LateContext; -use rustc_span::{SyntaxContext, sym}; +use rustc_span::{Span, SyntaxContext, sym}; use super::MANUAL_FILTER; use super::manual_utils::{SomeExpr, check_with}; @@ -21,8 +24,8 @@ fn get_cond_expr<'tcx>( expr: &'tcx Expr<'_>, ctxt: SyntaxContext, ) -> Option> { - if let Some(block_expr) = peels_blocks_incl_unsafe_opt(expr) - && let ExprKind::If(cond, then_expr, Some(else_expr)) = block_expr.kind + let block_expr = peels_blocks_incl_unsafe(expr); + if let ExprKind::If(cond, then_expr, Some(else_expr)) = block_expr.kind && let PatKind::Binding(_, target, ..) = pat.kind && (is_some_expr(cx, target, ctxt, then_expr) && is_none_expr(cx, else_expr) || is_none_expr(cx, then_expr) && is_some_expr(cx, target, ctxt, else_expr)) @@ -89,6 +92,66 @@ fn add_ampersand_if_copy(body_str: String, has_copy_trait: bool) -> String { } } +/// Checks for the following pattern: +/// `opt.and_then(|x| if /* predicate on x */ { Some(x) } else { None })` +/// and suggests replacing with: +/// `opt.filter(|&x| /* predicate on x */ )` +pub(crate) fn check_and_then_method<'tcx>( + cx: &LateContext<'tcx>, + scrutinee: &'tcx Expr<'_>, + arg: &'tcx Expr<'_>, + call_span: Span, + expr: &'tcx Expr<'_>, +) { + let ty = cx.typeck_results().expr_ty(scrutinee); + if ty.is_diag_item(cx, sym::Option) + && let ExprKind::Closure(closure) = arg.kind + && let body = cx.tcx.hir_body(closure.body) + && let Some(fn_arg_span) = closure.fn_arg_span + && let [param] = body.params + && let expr_span_ctxt = expr.span.ctxt() + && let Some(some_expr) = get_cond_expr(cx, param.pat, body.value, expr_span_ctxt) + { + span_lint_and_then( + cx, + MANUAL_FILTER, + call_span, + "manual implementation of `Option::filter`", + |diag| { + let mut applicability = Applicability::MachineApplicable; + + let mut cond_snip = + Sugg::hir_with_context(cx, some_expr.expr, expr_span_ctxt, "..", &mut applicability); + if some_expr.needs_unsafe_block { + cond_snip = cond_snip.unsafeify(); + } + if some_expr.needs_negated { + cond_snip = !cond_snip; + } + + let (prefix_snip, _) = snippet_with_context( + cx, + closure.fn_decl_span.until(fn_arg_span), + expr_span_ctxt, + "..", + &mut applicability, + ); + let (param_snip, _) = + snippet_with_context(cx, param.pat.span, expr_span_ctxt, "..", &mut applicability); + diag.span_suggestion( + call_span, + "try", + format!( + "filter({prefix_snip}|{}{param_snip}| {cond_snip})", + if is_copy(cx, ty) { "&" } else { "" } + ), + applicability, + ); + }, + ); + } +} + pub(super) fn check_match<'tcx>( cx: &LateContext<'tcx>, scrutinee: &'tcx Expr<'_>, diff --git a/src/tools/clippy/clippy_lints/src/matches/manual_utils.rs b/src/tools/clippy/clippy_lints/src/matches/manual_utils.rs index 6a755fac45fe..26fd936767aa 100644 --- a/src/tools/clippy/clippy_lints/src/matches/manual_utils.rs +++ b/src/tools/clippy/clippy_lints/src/matches/manual_utils.rs @@ -87,28 +87,24 @@ pub(super) fn check_with<'tcx, F>( None => "", }; - match can_move_expr_to_closure(cx, some_expr.expr) { - Some(captures) => { - // Check if captures the closure will need conflict with borrows made in the scrutinee. - // TODO: check all the references made in the scrutinee expression. This will require interacting - // with the borrow checker. Currently only `[.]*` is checked for. - if let Some(binding_ref_mutability) = binding_ref { - let e = peel_hir_expr_while(scrutinee, |e| match e.kind { - ExprKind::Field(e, _) | ExprKind::AddrOf(_, _, e) => Some(e), - _ => None, - }); - if let ExprKind::Path(QPath::Resolved(None, Path { res: Res::Local(l), .. })) = e.kind { - match captures.get(l) { - Some(CaptureKind::Value | CaptureKind::Use | CaptureKind::Ref(Mutability::Mut)) => return None, - Some(CaptureKind::Ref(Mutability::Not)) if binding_ref_mutability == Mutability::Mut => { - return None; - }, - Some(CaptureKind::Ref(Mutability::Not)) | None => (), - } - } + let captures = can_move_expr_to_closure(cx, some_expr.expr)?; + // Check if captures the closure will need conflict with borrows made in the scrutinee. + // TODO: check all the references made in the scrutinee expression. This will require interacting + // with the borrow checker. Currently only `[.]*` is checked for. + if let Some(binding_ref_mutability) = binding_ref { + let e = peel_hir_expr_while(scrutinee, |e| match e.kind { + ExprKind::Field(e, _) | ExprKind::AddrOf(_, _, e) => Some(e), + _ => None, + }); + if let ExprKind::Path(QPath::Resolved(None, Path { res: Res::Local(l), .. })) = e.kind { + match captures.get(l) { + Some(CaptureKind::Value | CaptureKind::Use | CaptureKind::Ref(Mutability::Mut)) => return None, + Some(CaptureKind::Ref(Mutability::Not)) if binding_ref_mutability == Mutability::Mut => { + return None; + }, + Some(CaptureKind::Ref(Mutability::Not)) | None => (), } - }, - None => return None, + } } let mut app = Applicability::MachineApplicable; diff --git a/src/tools/clippy/clippy_lints/src/matches/mod.rs b/src/tools/clippy/clippy_lints/src/matches/mod.rs index 717c47b8aed3..0e43bba60682 100644 --- a/src/tools/clippy/clippy_lints/src/matches/mod.rs +++ b/src/tools/clippy/clippy_lints/src/matches/mod.rs @@ -1,6 +1,6 @@ mod collapsible_match; mod infallible_destructuring_match; -mod manual_filter; +pub(crate) mod manual_filter; mod manual_map; mod manual_ok_err; mod manual_unwrap_or; diff --git a/src/tools/clippy/clippy_lints/src/methods/expect_fun_call.rs b/src/tools/clippy/clippy_lints/src/methods/expect_fun_call.rs index 081f958bc8b7..89b37d507b70 100644 --- a/src/tools/clippy/clippy_lints/src/methods/expect_fun_call.rs +++ b/src/tools/clippy/clippy_lints/src/methods/expect_fun_call.rs @@ -75,7 +75,13 @@ fn get_arg_root<'a>(cx: &LateContext<'_>, arg: &'a hir::Expr<'a>) -> &'a hir::Ex let mut arg_root = peel_blocks(arg); loop { arg_root = match &arg_root.kind { - hir::ExprKind::AddrOf(hir::BorrowKind::Ref, _, expr) => expr, + hir::ExprKind::AddrOf(hir::BorrowKind::Ref, _, expr) => { + let expr_ty = cx.typeck_results().expr_ty(expr); + if expr_ty.is_str() { + break; + } + expr + }, hir::ExprKind::MethodCall(method_name, receiver, [], ..) => { if (method_name.ident.name == sym::as_str || method_name.ident.name == sym::as_ref) && { let arg_type = cx.typeck_results().expr_ty(receiver); diff --git a/src/tools/clippy/clippy_lints/src/methods/iter_out_of_bounds.rs b/src/tools/clippy/clippy_lints/src/methods/iter_out_of_bounds.rs index 6e998ccf896d..b0e805815bc9 100644 --- a/src/tools/clippy/clippy_lints/src/methods/iter_out_of_bounds.rs +++ b/src/tools/clippy/clippy_lints/src/methods/iter_out_of_bounds.rs @@ -35,13 +35,12 @@ fn get_iterator_length<'tcx>(cx: &LateContext<'tcx>, iter: &'tcx Expr<'tcx>) -> if let ty::Array(_, len) = cx.typeck_results().expr_ty(recv).peel_refs().kind() { // For slice::Iter<'_, T>, the receiver might be an array literal: [1,2,3].iter().skip(..) len.try_to_target_usize(cx.tcx).map(u128::from) - } else if let Some(args) = VecArgs::hir(cx, expr_or_init(cx, recv)) { + } else { + let args = VecArgs::hir(cx, expr_or_init(cx, recv))?; match args { VecArgs::Vec(vec) => vec.len().try_into().ok(), VecArgs::Repeat(_, len) => expr_as_u128(cx, len), } - } else { - None } }, Some(sym::IterEmpty) => Some(0), diff --git a/src/tools/clippy/clippy_lints/src/methods/manual_inspect.rs b/src/tools/clippy/clippy_lints/src/methods/manual_inspect.rs index 1a5b180b0c86..a89a656a6bc7 100644 --- a/src/tools/clippy/clippy_lints/src/methods/manual_inspect.rs +++ b/src/tools/clippy/clippy_lints/src/methods/manual_inspect.rs @@ -4,13 +4,13 @@ use clippy_utils::source::{IntoSpan, SpanRangeExt}; use clippy_utils::ty::get_field_by_name; use clippy_utils::visitors::{for_each_expr, for_each_expr_without_closures}; -use clippy_utils::{ExprUseNode, expr_use_ctxt, sym}; +use clippy_utils::{ExprUseNode, get_expr_use_site, sym}; use core::ops::ControlFlow; use rustc_errors::Applicability; use rustc_hir::{BindingMode, BorrowKind, ByRef, ClosureKind, Expr, ExprKind, Mutability, Node, PatKind}; use rustc_lint::LateContext; use rustc_middle::ty::adjustment::{Adjust, Adjustment, AutoBorrow, AutoBorrowMutability}; -use rustc_span::{DUMMY_SP, Span, Symbol}; +use rustc_span::{DUMMY_SP, Span, Symbol, SyntaxContext}; use super::MANUAL_INSPECT; @@ -49,7 +49,7 @@ pub(crate) fn check(cx: &LateContext<'_>, expr: &Expr<'_>, arg: &Expr<'_>, name: // Nested closures don't need to treat returns specially. let _: Option = for_each_expr(cx, cx.tcx.hir_body(c.body).value, |e| { if e.res_local_id() == Some(arg_id) { - let (kind, same_ctxt) = check_use(cx, e); + let (kind, same_ctxt) = check_use(cx, ctxt, e); match (kind, same_ctxt && e.span.ctxt() == ctxt) { (_, false) | (UseKind::Deref | UseKind::Return(..), true) => { requires_copy = true; @@ -67,7 +67,7 @@ pub(crate) fn check(cx: &LateContext<'_>, expr: &Expr<'_>, arg: &Expr<'_>, name: } else if matches!(e.kind, ExprKind::Ret(_)) { ret_count += 1; } else if e.res_local_id() == Some(arg_id) { - let (kind, same_ctxt) = check_use(cx, e); + let (kind, same_ctxt) = check_use(cx, ctxt, e); match (kind, same_ctxt && e.span.ctxt() == ctxt) { (UseKind::Return(..), false) => { return ControlFlow::Break(()); @@ -209,8 +209,8 @@ enum UseKind<'tcx> { } /// Checks how the value is used, and whether it was used in the same `SyntaxContext`. -fn check_use<'tcx>(cx: &LateContext<'tcx>, e: &'tcx Expr<'_>) -> (UseKind<'tcx>, bool) { - let use_cx = expr_use_ctxt(cx, e); +fn check_use<'tcx>(cx: &LateContext<'tcx>, ctxt: SyntaxContext, e: &'tcx Expr<'_>) -> (UseKind<'tcx>, bool) { + let use_cx = get_expr_use_site(cx.tcx, cx.typeck_results(), ctxt, e); if use_cx .adjustments .first() diff --git a/src/tools/clippy/clippy_lints/src/methods/manual_repeat_n.rs b/src/tools/clippy/clippy_lints/src/methods/manual_repeat_n.rs index 1bb112732fa5..6f65fc48b38a 100644 --- a/src/tools/clippy/clippy_lints/src/methods/manual_repeat_n.rs +++ b/src/tools/clippy/clippy_lints/src/methods/manual_repeat_n.rs @@ -2,7 +2,7 @@ use clippy_utils::msrvs::{self, Msrv}; use clippy_utils::res::{MaybeDef, MaybeTypeckRes}; use clippy_utils::source::{snippet, snippet_with_context}; -use clippy_utils::{expr_use_ctxt, fn_def_id, std_or_core, sym}; +use clippy_utils::{fn_def_id, get_expr_use_site, std_or_core, sym}; use rustc_errors::Applicability; use rustc_hir::{Expr, ExprKind}; use rustc_lint::LateContext; @@ -21,7 +21,7 @@ pub(super) fn check<'tcx>( && let ExprKind::Call(_, [repeat_arg]) = repeat_expr.kind && let Some(def_id) = fn_def_id(cx, repeat_expr) && cx.tcx.is_diagnostic_item(sym::iter_repeat, def_id) - && !expr_use_ctxt(cx, expr).is_ty_unified + && !get_expr_use_site(cx.tcx, cx.typeck_results(), expr.span.ctxt(), expr).is_ty_unified && let Some(std_or_core) = std_or_core(cx) && msrv.meets(cx, msrvs::REPEAT_N) { diff --git a/src/tools/clippy/clippy_lints/src/methods/map_with_unused_argument_over_ranges.rs b/src/tools/clippy/clippy_lints/src/methods/map_with_unused_argument_over_ranges.rs index f60387fe86f7..216ca7dbc27f 100644 --- a/src/tools/clippy/clippy_lints/src/methods/map_with_unused_argument_over_ranges.rs +++ b/src/tools/clippy/clippy_lints/src/methods/map_with_unused_argument_over_ranges.rs @@ -1,7 +1,7 @@ use crate::methods::MAP_WITH_UNUSED_ARGUMENT_OVER_RANGES; use clippy_utils::diagnostics::span_lint_and_then; use clippy_utils::msrvs::{self, Msrv}; -use clippy_utils::source::snippet_with_applicability; +use clippy_utils::source::snippet_with_context; use clippy_utils::sugg::Sugg; use clippy_utils::{eager_or_lazy, higher, std_or_core, usage}; use rustc_ast::LitKind; @@ -10,12 +10,13 @@ use rustc_errors::Applicability; use rustc_hir::{Body, Closure, Expr, ExprKind}; use rustc_lint::LateContext; -use rustc_span::Span; +use rustc_span::{Span, SyntaxContext}; fn extract_count_with_applicability( cx: &LateContext<'_>, range: higher::Range<'_>, applicability: &mut Applicability, + ctxt: SyntaxContext, ) -> Option { let start = range.start?; let end = range.end?; @@ -40,7 +41,7 @@ fn extract_count_with_applicability( }; return Some(format!("{count}")); } - let end_snippet = Sugg::hir_with_applicability(cx, end, "...", applicability) + let end_snippet = Sugg::hir_with_context(cx, end, ctxt, "...", applicability) .maybe_paren() .into_string(); if lower_bound == 0 { @@ -74,45 +75,23 @@ pub(super) fn check( value: body_expr, } = body_hir && !usage::BindingUsageFinder::are_params_used(cx, body_hir) - && let Some(count) = extract_count_with_applicability(cx, range, &mut applicability) + && let ctxt = ex.span.ctxt() + && let Some(count) = extract_count_with_applicability(cx, range, &mut applicability, ctxt) && let Some(exec_context) = std_or_core(cx) { - let method_to_use_name; - let new_span; - let use_take; - - if eager_or_lazy::switch_to_eager_eval(cx, body_expr) { + let (method_to_use_name, new_span, use_take) = if eager_or_lazy::switch_to_eager_eval(cx, body_expr) { if msrv.meets(cx, msrvs::REPEAT_N) { - method_to_use_name = "repeat_n"; - let body_snippet = snippet_with_applicability(cx, body_expr.span, "..", &mut applicability); - new_span = (arg.span, format!("{body_snippet}, {count}")); - use_take = false; + let (body_snippet, _) = snippet_with_context(cx, body_expr.span, ctxt, "..", &mut applicability); + ("repeat_n", (arg.span, format!("{body_snippet}, {count}")), false) } else { - method_to_use_name = "repeat"; - let body_snippet = snippet_with_applicability(cx, body_expr.span, "..", &mut applicability); - new_span = (arg.span, body_snippet.to_string()); - use_take = true; + let (body_snippet, _) = snippet_with_context(cx, body_expr.span, ctxt, "..", &mut applicability); + ("repeat", (arg.span, body_snippet.to_string()), true) } } else if msrv.meets(cx, msrvs::REPEAT_WITH) { - method_to_use_name = "repeat_with"; - new_span = (param.span, String::new()); - use_take = true; + ("repeat_with", (param.span, String::new()), true) } else { return; - } - - // We need to provide nonempty parts to diag.multipart_suggestion so we - // collate all our parts here and then remove those that are empty. - let mut parts = vec![ - ( - ex.span.with_hi(method_name_span.hi()), - format!("{exec_context}::iter::{method_to_use_name}"), - ), - new_span, - ]; - if use_take { - parts.push((ex.span.shrink_to_hi(), format!(".take({count})"))); - } + }; span_lint_and_then( cx, @@ -120,6 +99,19 @@ pub(super) fn check( ex.span, "map of a closure that does not depend on its parameter over a range", |diag| { + // We need to provide nonempty parts to diag.multipart_suggestion so we + // collate all our parts here and then remove those that are empty. + let mut parts = vec![ + ( + ex.span.with_hi(method_name_span.hi()), + format!("{exec_context}::iter::{method_to_use_name}"), + ), + new_span, + ]; + if use_take { + parts.push((ex.span.shrink_to_hi(), format!(".take({count})"))); + } + diag.multipart_suggestion( if use_take { format!("remove the explicit range and use `{method_to_use_name}` and `take`") diff --git a/src/tools/clippy/clippy_lints/src/methods/mod.rs b/src/tools/clippy/clippy_lints/src/methods/mod.rs index b39aec6e521c..7ca98686b8b1 100644 --- a/src/tools/clippy/clippy_lints/src/methods/mod.rs +++ b/src/tools/clippy/clippy_lints/src/methods/mod.rs @@ -163,6 +163,8 @@ use rustc_session::impl_lint_pass; use rustc_span::{Span, Symbol}; +use crate::matches::manual_filter; + declare_clippy_lint! { /// ### What it does /// Checks for usage of `_.and_then(|x| Some(y))`, `_.and_then(|x| Ok(y))` @@ -5062,7 +5064,7 @@ fn check_impl_item(&mut self, cx: &LateContext<'tcx>, impl_item: &'tcx hir::Impl let first_arg_ty_opt = method_sig.inputs().iter().next().copied(); should_implement_trait::check_impl_item(cx, impl_item, self_ty, implements_trait, first_arg_ty_opt, sig); - if sig.decl.implicit_self.has_implicit_self() + if sig.decl.implicit_self().has_implicit_self() && !(self.avoid_breaking_exported_api && cx.effective_visibilities.is_exported(impl_item.owner_id.def_id)) && let Some(first_arg) = iter_input_pats(sig.decl, cx.tcx.hir_body(id)).next() @@ -5089,7 +5091,7 @@ fn check_trait_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx TraitItem<'_> } if let TraitItemKind::Fn(ref sig, _) = item.kind { - if sig.decl.implicit_self.has_implicit_self() + if sig.decl.implicit_self().has_implicit_self() && let Some(first_arg_hir_ty) = sig.decl.inputs.first() && let Some(&first_arg_ty) = cx .tcx @@ -5154,6 +5156,8 @@ fn check_methods<'tcx>(&self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { return_and_then::check(cx, expr, recv, arg); } } + + manual_filter::check_and_then_method(cx, recv, arg, call_span, expr); }, (sym::any, [arg]) => { needless_character_iteration::check(cx, expr, recv, arg, false); diff --git a/src/tools/clippy/clippy_lints/src/methods/unnecessary_fold.rs b/src/tools/clippy/clippy_lints/src/methods/unnecessary_fold.rs index 0b38bdcdf544..15337082c03a 100644 --- a/src/tools/clippy/clippy_lints/src/methods/unnecessary_fold.rs +++ b/src/tools/clippy/clippy_lints/src/methods/unnecessary_fold.rs @@ -1,7 +1,7 @@ use clippy_utils::diagnostics::span_lint_and_then; use clippy_utils::res::{MaybeDef, MaybeQPath, MaybeResPath, MaybeTypeckRes}; use clippy_utils::source::snippet_with_context; -use clippy_utils::{DefinedTy, ExprUseNode, expr_use_ctxt, peel_blocks, strip_pat_refs}; +use clippy_utils::{DefinedTy, ExprUseNode, get_expr_use_site, peel_blocks, strip_pat_refs}; use rustc_ast::ast; use rustc_data_structures::packed::Pu128; use rustc_errors::{Applicability, Diag}; @@ -17,10 +17,10 @@ /// Do we need to suggest turbofish when suggesting a replacement method? /// Changing `fold` to `sum` needs it sometimes when the return type can't be /// inferred. This checks for some common cases where it can be safely omitted -fn needs_turbofish<'tcx>(cx: &LateContext<'tcx>, expr: &hir::Expr<'tcx>) -> bool { - let use_cx = expr_use_ctxt(cx, expr); - if use_cx.same_ctxt - && let use_node = use_cx.use_node(cx) +fn needs_turbofish<'tcx>(cx: &LateContext<'tcx>, expr: &'tcx hir::Expr<'tcx>) -> bool { + let use_site = get_expr_use_site(cx.tcx, cx.typeck_results(), expr.span.ctxt(), expr); + if use_site.same_ctxt + && let use_node = use_site.use_node(cx) && let Some(ty) = use_node.defined_ty(cx) { // some common cases where turbofish isn't needed: @@ -209,7 +209,7 @@ fn check_fold_with_method( pub(super) fn check<'tcx>( cx: &LateContext<'tcx>, - expr: &hir::Expr<'tcx>, + expr: &'tcx hir::Expr<'tcx>, init: &hir::Expr<'_>, acc: &hir::Expr<'_>, fold_span: Span, diff --git a/src/tools/clippy/clippy_lints/src/misc_early/mod.rs b/src/tools/clippy/clippy_lints/src/misc_early/mod.rs index 604b946d91a7..314004621ce0 100644 --- a/src/tools/clippy/clippy_lints/src/misc_early/mod.rs +++ b/src/tools/clippy/clippy_lints/src/misc_early/mod.rs @@ -197,7 +197,7 @@ declare_clippy_lint! { /// ### What it does - /// Checks for tuple patterns with a wildcard + /// Checks for tuple and struct patterns with a wildcard /// pattern (`_`) is next to a rest pattern (`..`). /// /// _NOTE_: While `_, ..` means there is at least one element left, `..` @@ -231,7 +231,7 @@ #[clippy::version = "1.40.0"] pub UNNEEDED_WILDCARD_PATTERN, complexity, - "tuple patterns with a wildcard pattern (`_`) is next to a rest pattern (`..`)" + "tuple and struct patterns with a wildcard pattern (`_`) is next to a rest pattern (`..`)" } declare_clippy_lint! { diff --git a/src/tools/clippy/clippy_lints/src/misc_early/unneeded_wildcard_pattern.rs b/src/tools/clippy/clippy_lints/src/misc_early/unneeded_wildcard_pattern.rs index 0eb5c36a28a2..897d720036ee 100644 --- a/src/tools/clippy/clippy_lints/src/misc_early/unneeded_wildcard_pattern.rs +++ b/src/tools/clippy/clippy_lints/src/misc_early/unneeded_wildcard_pattern.rs @@ -1,5 +1,5 @@ use clippy_utils::diagnostics::span_lint_and_sugg; -use rustc_ast::ast::{Pat, PatKind}; +use rustc_ast::ast::{Pat, PatFieldsRest, PatKind}; use rustc_errors::Applicability; use rustc_lint::EarlyContext; use rustc_span::Span; @@ -32,6 +32,19 @@ pub(super) fn check(cx: &EarlyContext<'_>, pat: &Pat) { right_index == 0, ); } + } else if let PatKind::Struct(_, _, patfields, rest) = &pat.kind + && let PatFieldsRest::Rest(rspan) = rest + && let Some((right_index, _right_pat)) = patfields + .iter() + .rev() + .take_while(|patfield| matches!(patfield.pat.kind, PatKind::Wild)) + .enumerate() + .last() + { + // Unlike the tuples above, structs have patfields rather than patterns, and separate out the + // `..` into a separate parameter. Also, the `..` can only be at the end of the pattern. + let singlewild = patfields.len() - right_index - 1; + span_lint(cx, patfields[singlewild].span.until(*rspan), right_index == 0); } } diff --git a/src/tools/clippy/clippy_lints/src/missing_doc.rs b/src/tools/clippy/clippy_lints/src/missing_doc.rs index 89a61298bf19..35e75d34a5d3 100644 --- a/src/tools/clippy/clippy_lints/src/missing_doc.rs +++ b/src/tools/clippy/clippy_lints/src/missing_doc.rs @@ -159,7 +159,7 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'_>) { | ItemKind::Macro(ident, ..) | ItemKind::Static(_, ident, ..) | ItemKind::Struct(ident, ..) - | ItemKind::Trait(_, _, _, ident, ..) + | ItemKind::Trait(_, _, _, _, ident, ..) | ItemKind::TraitAlias(_, ident, ..) | ItemKind::TyAlias(ident, ..) | ItemKind::Union(ident, ..) => ident.span, diff --git a/src/tools/clippy/clippy_lints/src/needless_bool.rs b/src/tools/clippy/clippy_lints/src/needless_bool.rs index a0ad1fe00c62..064c1b8909fb 100644 --- a/src/tools/clippy/clippy_lints/src/needless_bool.rs +++ b/src/tools/clippy/clippy_lints/src/needless_bool.rs @@ -112,7 +112,7 @@ fn check_expr(&mut self, cx: &LateContext<'tcx>, e: &'tcx Expr<'_>) { { let reduce = |ret, not| { let mut applicability = Applicability::MachineApplicable; - let snip = Sugg::hir_with_applicability(cx, cond, "", &mut applicability); + let snip = Sugg::hir_with_context(cx, cond, e.span.ctxt(), "", &mut applicability); let mut snip = if not { !snip } else { snip }; if ret { diff --git a/src/tools/clippy/clippy_lints/src/needless_borrows_for_generic_args.rs b/src/tools/clippy/clippy_lints/src/needless_borrows_for_generic_args.rs index 1374d8ed774b..3dbfd58cd04e 100644 --- a/src/tools/clippy/clippy_lints/src/needless_borrows_for_generic_args.rs +++ b/src/tools/clippy/clippy_lints/src/needless_borrows_for_generic_args.rs @@ -4,7 +4,7 @@ use clippy_utils::msrvs::{self, Msrv}; use clippy_utils::source::snippet_with_context; use clippy_utils::ty::{implements_trait, is_copy}; -use clippy_utils::{DefinedTy, ExprUseNode, expr_use_ctxt, peel_n_hir_expr_refs, sym}; +use clippy_utils::{DefinedTy, ExprUseNode, get_expr_use_site, peel_n_hir_expr_refs, sym}; use rustc_errors::Applicability; use rustc_hir::def::{DefKind, Res}; use rustc_hir::def_id::{DefId, LocalDefId}; @@ -17,6 +17,7 @@ self, ClauseKind, EarlyBinder, FnSig, GenericArg, GenericArgKind, ParamTy, ProjectionPredicate, Ty, }; use rustc_session::impl_lint_pass; +use rustc_span::SyntaxContext; use rustc_trait_selection::traits::query::evaluate_obligation::InferCtxtExt as _; use rustc_trait_selection::traits::{Obligation, ObligationCause}; use std::collections::VecDeque; @@ -82,10 +83,10 @@ impl<'tcx> LateLintPass<'tcx> for NeedlessBorrowsForGenericArgs<'tcx> { fn check_expr(&mut self, cx: &LateContext<'tcx>, expr: &'tcx Expr<'_>) { if matches!(expr.kind, ExprKind::AddrOf(..)) && !expr.span.from_expansion() - && let use_cx = expr_use_ctxt(cx, expr) - && use_cx.same_ctxt - && !use_cx.is_ty_unified - && let use_node = use_cx.use_node(cx) + && let use_site = get_expr_use_site(cx.tcx, cx.typeck_results(), SyntaxContext::root(), expr) + && use_site.same_ctxt + && !use_site.is_ty_unified + && let use_node = use_site.use_node(cx) && let Some(DefinedTy::Mir { def_site_def_id: _, ty }) = use_node.defined_ty(cx) && let ty::Param(param_ty) = *ty.skip_binder().kind() && let Some((hir_id, fn_id, i)) = match use_node { diff --git a/src/tools/clippy/clippy_lints/src/only_used_in_recursion.rs b/src/tools/clippy/clippy_lints/src/only_used_in_recursion.rs index 6c45964da0da..f1625b1a4c6e 100644 --- a/src/tools/clippy/clippy_lints/src/only_used_in_recursion.rs +++ b/src/tools/clippy/clippy_lints/src/only_used_in_recursion.rs @@ -321,7 +321,7 @@ fn check_body(&mut self, cx: &LateContext<'tcx>, body: &Body<'tcx>) { }) => ( owner_id.to_def_id(), FnKind::TraitFn, - usize::from(sig.decl.implicit_self.has_implicit_self()), + usize::from(sig.decl.implicit_self().has_implicit_self()), ), Node::ImplItem(&ImplItem { kind: ImplItemKind::Fn(ref sig, _), @@ -339,7 +339,7 @@ fn check_body(&mut self, cx: &LateContext<'tcx>, body: &Body<'tcx>) { FnKind::ImplTraitFn( std::ptr::from_ref(cx.tcx.erase_and_anonymize_regions(trait_ref.args)) as usize ), - usize::from(sig.decl.implicit_self.has_implicit_self()), + usize::from(sig.decl.implicit_self().has_implicit_self()), ) } else { (owner_id.to_def_id(), FnKind::Fn, 0) diff --git a/src/tools/clippy/clippy_lints/src/operators/bit_mask.rs b/src/tools/clippy/clippy_lints/src/operators/bit_mask.rs index 7f6dea573de8..104f786ead16 100644 --- a/src/tools/clippy/clippy_lints/src/operators/bit_mask.rs +++ b/src/tools/clippy/clippy_lints/src/operators/bit_mask.rs @@ -36,12 +36,19 @@ fn invert_cmp(cmp: BinOpKind) -> BinOpKind { } } -fn check_compare<'a>(cx: &LateContext<'a>, bit_op: &Expr<'a>, cmp_op: BinOpKind, cmp_value: u128, span: Span) { +fn check_compare<'a>(cx: &LateContext<'a>, bit_op: &Expr<'a>, cmp_op: BinOpKind, mut cmp_value: u128, span: Span) { if let ExprKind::Binary(op, left, right) = &bit_op.kind { if op.node != BinOpKind::BitAnd && op.node != BinOpKind::BitOr || is_from_proc_macro(cx, bit_op) { return; } if let Some(mask) = fetch_int_literal(cx, right).or_else(|| fetch_int_literal(cx, left)) { + let ty = cx.typeck_results().expr_ty(bit_op); + if !ty.is_ptr_sized_integral() + && let bits = ty.primitive_size(cx.tcx) + { + // Strip high bits that don't fit into the result type as they won't be used in the comparison + cmp_value &= bits.unsigned_int_max(); + } check_bit_mask(cx, op.node, cmp_op, mask, cmp_value, span); } } diff --git a/src/tools/clippy/clippy_lints/src/operators/identity_op.rs b/src/tools/clippy/clippy_lints/src/operators/identity_op.rs index ce50e6e35dcc..b18957aaff44 100644 --- a/src/tools/clippy/clippy_lints/src/operators/identity_op.rs +++ b/src/tools/clippy/clippy_lints/src/operators/identity_op.rs @@ -1,7 +1,7 @@ use clippy_utils::consts::{ConstEvalCtxt, Constant, FullInt, integer_const, is_zero_integer_const}; use clippy_utils::diagnostics::span_lint_and_sugg; use clippy_utils::source::snippet_with_applicability; -use clippy_utils::{ExprUseNode, clip, expr_use_ctxt, peel_hir_expr_refs, unsext}; +use clippy_utils::{ExprUseNode, clip, get_expr_use_site, peel_hir_expr_refs, unsext}; use rustc_errors::Applicability; use rustc_hir::def::{DefKind, Res}; use rustc_hir::{BinOpKind, Expr, ExprKind, Node, Path, QPath}; @@ -250,7 +250,7 @@ fn span_ineffective_operation( } fn is_expr_used_with_type_annotation<'tcx>(cx: &LateContext<'tcx>, expr: &'tcx Expr<'tcx>) -> bool { - match expr_use_ctxt(cx, expr).use_node(cx) { + match get_expr_use_site(cx.tcx, cx.typeck_results(), expr.span.ctxt(), expr).use_node(cx) { ExprUseNode::LetStmt(letstmt) => letstmt.ty.is_some(), ExprUseNode::Return(_) => true, _ => false, diff --git a/src/tools/clippy/clippy_lints/src/operators/manual_div_ceil.rs b/src/tools/clippy/clippy_lints/src/operators/manual_div_ceil.rs index a0f61f6d36c4..5a4823ddfcf6 100644 --- a/src/tools/clippy/clippy_lints/src/operators/manual_div_ceil.rs +++ b/src/tools/clippy/clippy_lints/src/operators/manual_div_ceil.rs @@ -148,7 +148,8 @@ fn build_suggestion( rhs: &Expr<'_>, applicability: &mut Applicability, ) { - let dividend_sugg = Sugg::hir_with_applicability(cx, lhs, "..", applicability).maybe_paren(); + let ctxt = expr.span.ctxt(); + let dividend_sugg = Sugg::hir_with_context(cx, lhs, ctxt, "..", applicability).maybe_paren(); let rhs_ty = cx.typeck_results().expr_ty(rhs); let type_suffix = if cx.typeck_results().expr_ty(lhs).is_numeric() && matches!( @@ -186,7 +187,7 @@ fn build_suggestion( }; // Dereference the RHS if it is a reference type - let divisor_snippet = match Sugg::hir_with_context(cx, rhs, expr.span.ctxt(), "_", applicability) { + let divisor_snippet = match Sugg::hir_with_context(cx, rhs, ctxt, "_", applicability) { sugg if rhs_ty.is_ref() => sugg.deref(), sugg => sugg, }; diff --git a/src/tools/clippy/clippy_lints/src/operators/needless_bitwise_bool.rs b/src/tools/clippy/clippy_lints/src/operators/needless_bitwise_bool.rs index 9d8e833ef6d7..cac3169bd289 100644 --- a/src/tools/clippy/clippy_lints/src/operators/needless_bitwise_bool.rs +++ b/src/tools/clippy/clippy_lints/src/operators/needless_bitwise_bool.rs @@ -1,5 +1,5 @@ use clippy_utils::diagnostics::span_lint_and_then; -use clippy_utils::source::SpanRangeExt; +use clippy_utils::source::snippet_with_context; use rustc_errors::Applicability; use rustc_hir::{BinOpKind, Expr, ExprKind}; use rustc_lint::LateContext; @@ -24,12 +24,12 @@ pub(super) fn check(cx: &LateContext<'_>, e: &Expr<'_>, op: BinOpKind, lhs: &Exp e.span, "use of bitwise operator instead of lazy operator between booleans", |diag| { - if let Some(lhs_snip) = lhs.span.get_source_text(cx) - && let Some(rhs_snip) = rhs.span.get_source_text(cx) - { - let sugg = format!("{lhs_snip} {op_str} {rhs_snip}"); - diag.span_suggestion(e.span, "try", sugg, Applicability::MachineApplicable); - } + let mut applicability = Applicability::MachineApplicable; + let expr_span_ctxt = e.span.ctxt(); + let (lhs_snip, _) = snippet_with_context(cx, lhs.span, expr_span_ctxt, "..", &mut applicability); + let (rhs_snip, _) = snippet_with_context(cx, rhs.span, expr_span_ctxt, "..", &mut applicability); + + diag.span_suggestion(e.span, "try", format!("{lhs_snip} {op_str} {rhs_snip}"), applicability); }, ); } diff --git a/src/tools/clippy/clippy_lints/src/question_mark.rs b/src/tools/clippy/clippy_lints/src/question_mark.rs index dfd7834a149b..4bd6b1696b35 100644 --- a/src/tools/clippy/clippy_lints/src/question_mark.rs +++ b/src/tools/clippy/clippy_lints/src/question_mark.rs @@ -2,10 +2,10 @@ use crate::question_mark_used::QUESTION_MARK_USED; use clippy_config::Conf; use clippy_config::types::MatchLintBehaviour; -use clippy_utils::diagnostics::span_lint_and_sugg; +use clippy_utils::diagnostics::{span_lint_and_sugg, span_lint_and_then}; use clippy_utils::msrvs::{self, Msrv}; use clippy_utils::res::{MaybeDef, MaybeQPath, MaybeResPath}; -use clippy_utils::source::{snippet_with_applicability, snippet_with_context}; +use clippy_utils::source::{indent_of, reindent_multiline, snippet_with_applicability, snippet_with_context}; use clippy_utils::sugg::Sugg; use clippy_utils::ty::{implements_trait, is_copy}; use clippy_utils::usage::local_used_after_expr; @@ -24,6 +24,7 @@ use rustc_lint::{LateContext, LateLintPass}; use rustc_middle::ty::{self, Ty}; use rustc_session::impl_lint_pass; +use rustc_span::Span; use rustc_span::symbol::Symbol; declare_clippy_lint! { @@ -222,13 +223,11 @@ fn is_early_return(smbl: Symbol, cx: &LateContext<'_>, if_block: &IfBlockType<'_ // We only need to check `if let Some(x) = option` not `if let None = option`, // because the later one will be suggested as `if option.is_none()` thus causing conflict. res.ctor_parent(cx).is_lang_item(cx, OptionSome) - && if_else.is_some() - && expr_return_none_or_err(smbl, cx, if_else.unwrap(), let_expr, None) + && matches!(if_else, Some(inner) if expr_return_none_or_err(smbl, cx, inner, let_expr, None)) }, sym::Result => { (res.ctor_parent(cx).is_lang_item(cx, ResultOk) - && if_else.is_some() - && expr_return_none_or_err(smbl, cx, if_else.unwrap(), let_expr, Some(let_pat_sym))) + && matches!(if_else, Some(inner) if expr_return_none_or_err(smbl, cx, inner, let_expr, Some(let_pat_sym)))) || res.ctor_parent(cx).is_lang_item(cx, ResultErr) && expr_return_none_or_err(smbl, cx, if_then, let_expr, Some(let_pat_sym)) && if_else.is_none() @@ -328,7 +327,7 @@ enum TryMode { } fn find_try_mode<'tcx>(cx: &LateContext<'tcx>, scrutinee: &Expr<'tcx>) -> Option { - let scrutinee_ty = cx.typeck_results().expr_ty_adjusted(scrutinee); + let scrutinee_ty = cx.typeck_results().expr_ty_adjusted(scrutinee).peel_refs(); let ty::Adt(scrutinee_adt_def, _) = scrutinee_ty.kind() else { return None; }; @@ -360,14 +359,18 @@ fn extract_ctor_call<'a, 'tcx>( // Extracts the local ID of a plain `val` pattern. fn extract_binding_pat(pat: &Pat<'_>) -> Option { - if let PatKind::Binding(BindingMode::NONE, binding, _, None) = pat.kind { + if let PatKind::Binding(_, binding, _, None) = pat.kind { Some(binding) } else { None } } -fn check_arm_is_some_or_ok<'tcx>(cx: &LateContext<'tcx>, mode: TryMode, arm: &Arm<'tcx>) -> bool { +fn check_arm_is_some_or_ok<'tcx>( + cx: &LateContext<'tcx>, + mode: TryMode, + arm: &Arm<'tcx>, +) -> Option> { let happy_ctor = match mode { TryMode::Result => ResultOk, TryMode::Option => OptionSome, @@ -378,13 +381,16 @@ fn check_arm_is_some_or_ok<'tcx>(cx: &LateContext<'tcx>, mode: TryMode, arm: &Ar && let Some(val_binding) = extract_ctor_call(cx, happy_ctor, arm.pat) // Extract out `val` && let Some(binding) = extract_binding_pat(val_binding) - // Check body is just `=> val` - && peel_blocks(arm.body).res_local_id() == Some(binding) { - true - } else { - false + // Check body is just `=> val` + return Some(if peel_blocks(arm.body).res_local_id() == Some(binding) { + IfLetOrMatchThen::DirectReturn + } else { + IfLetOrMatchThen::ManualUnwrap(val_binding.span, arm.body) + }); } + + None } fn check_arm_is_none_or_err<'tcx>(cx: &LateContext<'tcx>, mode: TryMode, arm: &Arm<'tcx>) -> bool { @@ -439,9 +445,23 @@ fn is_local_or_local_into(cx: &LateContext<'_>, expr: &Expr<'_>, val: HirId) -> } } -fn check_arms_are_try<'tcx>(cx: &LateContext<'tcx>, mode: TryMode, arm1: &Arm<'tcx>, arm2: &Arm<'tcx>) -> bool { - (check_arm_is_some_or_ok(cx, mode, arm1) && check_arm_is_none_or_err(cx, mode, arm2)) - || (check_arm_is_some_or_ok(cx, mode, arm2) && check_arm_is_none_or_err(cx, mode, arm1)) +fn check_arms_are_try<'tcx>( + cx: &LateContext<'tcx>, + mode: TryMode, + arm1: &Arm<'tcx>, + arm2: &Arm<'tcx>, +) -> Option> { + (check_arm_is_none_or_err(cx, mode, arm2).then(|| check_arm_is_some_or_ok(cx, mode, arm1))) + .or_else(|| check_arm_is_none_or_err(cx, mode, arm1).then(|| check_arm_is_some_or_ok(cx, mode, arm2))) + .flatten() +} + +#[derive(Debug)] +enum IfLetOrMatchThen<'tcx> { + /// Return the binding from an if let or match arm as is. + DirectReturn, + /// Working on the binding from an if let or match arm as if it comes from a `?`. + ManualUnwrap(Span, &'tcx Expr<'tcx>), } fn check_if_try_match<'tcx>(cx: &LateContext<'tcx>, expr: &Expr<'tcx>) { @@ -449,19 +469,47 @@ fn check_if_try_match<'tcx>(cx: &LateContext<'tcx>, expr: &Expr<'tcx>) { && !expr.span.from_expansion() && let Some(mode) = find_try_mode(cx, scrutinee) && !span_contains_cfg(cx, expr.span) - && check_arms_are_try(cx, mode, arm1, arm2) + && let Some(if_let_or_match_then) = check_arms_are_try(cx, mode, arm1, arm2) { - let mut applicability = Applicability::MachineApplicable; - let snippet = snippet_with_applicability(cx, scrutinee.span.source_callsite(), "..", &mut applicability); - - span_lint_and_sugg( + span_lint_and_then( cx, QUESTION_MARK, expr.span, "this `match` expression can be replaced with `?`", - "try instead", - snippet.into_owned() + "?", - applicability, + |diag| { + let mut applicability = Applicability::MachineApplicable; + let scrutinee_snippet = + snippet_with_applicability(cx, scrutinee.span.source_callsite(), "..", &mut applicability); + match if_let_or_match_then { + IfLetOrMatchThen::DirectReturn => { + diag.span_suggestion( + expr.span, + "try instead", + scrutinee_snippet.into_owned() + "?", + applicability, + ); + }, + IfLetOrMatchThen::ManualUnwrap(binding_span, arm_body) => { + let indent = indent_of(cx, expr.span).unwrap_or_default(); + let arm_body_snippet = snippet_with_applicability(cx, arm_body.span, "..", &mut applicability); + let mut sugg = reindent_multiline(&arm_body_snippet, true, Some(indent)); + let binding_snippet = snippet_with_applicability(cx, binding_span, "..", &mut applicability); + let inner_indent = " ".repeat(indent + 4); + if matches!(arm_body.kind, ExprKind::Block(..)) { + sugg.insert_str( + 1, + &format!("\n{inner_indent}let {binding_snippet} = {scrutinee_snippet}?;"), + ); + } else { + let outer_indent = " ".repeat(indent); + sugg = format!( + "{{\n{inner_indent}let {binding_snippet} = {scrutinee_snippet}?;\n{inner_indent}{sugg}\n{outer_indent}}}" + ); + } + diag.span_suggestion(expr.span, "try instead", sugg, applicability); + }, + } + }, ); } } @@ -486,8 +534,8 @@ fn check_if_let_some_or_err_and_early_return<'tcx>(cx: &LateContext<'tcx>, expr: if_then, if_else, ) - && ((is_early_return(sym::Option, cx, &if_block) && peel_blocks(if_then).res_local_id() == Some(bind_id)) - || is_early_return(sym::Result, cx, &if_block)) + && let is_option_early_return = is_early_return(sym::Option, cx, &if_block) + && (is_option_early_return || is_early_return(sym::Result, cx, &if_block)) && if_else .map(|e| eq_expr_value(cx, let_expr, peel_blocks(e))) .is_none_or(|e| !e) @@ -499,32 +547,53 @@ fn check_if_let_some_or_err_and_early_return<'tcx>(cx: &LateContext<'tcx>, expr: return; } - let mut applicability = Applicability::MachineApplicable; - let receiver_str = snippet_with_applicability(cx, let_expr.span, "..", &mut applicability); - let parent = cx.tcx.parent_hir_node(expr.hir_id); - let requires_semi = matches!(parent, Node::Stmt(_)) || cx.typeck_results().expr_ty(expr).is_unit(); - let method_call_str = match by_ref { - ByRef::Yes(_, Mutability::Mut) => ".as_mut()", - ByRef::Yes(_, Mutability::Not) => ".as_ref()", - ByRef::No => "", - }; - - let mut sugg = format!( - "{receiver_str}{method_call_str}?{}", - if requires_semi { ";" } else { "" } - ); - if is_else_clause(cx.tcx, expr) || (requires_semi && !matches!(parent, Node::Stmt(_) | Node::Block(_))) { - sugg = format!("{{ {sugg} }}"); + // Leave `if let Some(x) = opt { .. } else { None }` to `needless_match` or `manual_map_option`. + if is_option_early_return + && if_else.is_some_and(|else_| !matches!(peel_blocks_with_stmt(else_).kind, ExprKind::Ret(_))) + { + return; } - span_lint_and_sugg( + span_lint_and_then( cx, QUESTION_MARK, expr.span, "this block may be rewritten with the `?` operator", - "replace it with", - sugg, - applicability, + |diag| { + let mut applicability = Applicability::MachineApplicable; + let receiver_str = snippet_with_applicability(cx, let_expr.span, "..", &mut applicability); + if !is_option_early_return || peel_blocks(if_then).res_local_id() == Some(bind_id) { + let parent = cx.tcx.parent_hir_node(expr.hir_id); + let requires_semi = matches!(parent, Node::Stmt(_)) || cx.typeck_results().expr_ty(expr).is_unit(); + let method_call_str = match by_ref { + ByRef::Yes(_, Mutability::Mut) => ".as_mut()", + ByRef::Yes(_, Mutability::Not) => ".as_ref()", + ByRef::No => "", + }; + + let mut sugg = format!( + "{receiver_str}{method_call_str}?{}", + if requires_semi { ";" } else { "" } + ); + if is_else_clause(cx.tcx, expr) + || (requires_semi && !matches!(parent, Node::Stmt(_) | Node::Block(_))) + { + sugg = format!("{{ {sugg} }}"); + } + + diag.span_suggestion(expr.span, "replace it with", sugg, applicability); + return; + } + + let mut sugg = snippet_with_applicability(cx, if_then.span, "..", &mut applicability).into_owned(); + let binding_snippet = snippet_with_applicability(cx, field.span, "..", &mut applicability); + let indent = indent_of(cx, expr.span).unwrap_or_default(); + sugg.insert_str( + 1, + &format!("\n{}let {binding_snippet} = {receiver_str}?;", " ".repeat(indent + 4)), + ); + diag.span_suggestion(expr.span, "replace it with", sugg, applicability); + }, ); } } diff --git a/src/tools/clippy/clippy_lints/src/ranges.rs b/src/tools/clippy/clippy_lints/src/ranges.rs index 39019c646bd5..2f79ca18e813 100644 --- a/src/tools/clippy/clippy_lints/src/ranges.rs +++ b/src/tools/clippy/clippy_lints/src/ranges.rs @@ -6,7 +6,7 @@ use clippy_utils::source::{SpanRangeExt, snippet, snippet_with_applicability}; use clippy_utils::sugg::Sugg; use clippy_utils::ty::implements_trait; -use clippy_utils::{expr_use_ctxt, fn_def_id, get_parent_expr, higher, is_in_const_context, is_integer_const, sym}; +use clippy_utils::{fn_def_id, get_expr_use_site, get_parent_expr, higher, is_in_const_context, is_integer_const, sym}; use rustc_ast::Mutability; use rustc_ast::ast::RangeLimits; use rustc_errors::Applicability; @@ -14,7 +14,7 @@ use rustc_lint::{LateContext, LateLintPass, Lint}; use rustc_middle::ty::{self, ClauseKind, GenericArgKind, PredicatePolarity, Ty}; use rustc_session::impl_lint_pass; -use rustc_span::{DesugaringKind, Span, Spanned}; +use rustc_span::{DesugaringKind, Span, Spanned, SyntaxContext}; use std::cmp::Ordering; declare_clippy_lint! { @@ -355,18 +355,19 @@ fn check_range_bounds<'a>(cx: &'a LateContext<'_>, ex: &'a Expr<'_>) -> Option( cx: &LateContext<'tcx>, + ctxt: SyntaxContext, expr: &'tcx Expr<'_>, original: RangeLimits, inner_ty: Ty<'tcx>, ) -> bool { - let use_ctxt = expr_use_ctxt(cx, expr); - let (Node::Expr(parent_expr), false) = (use_ctxt.node, use_ctxt.is_ty_unified) else { + let use_site = get_expr_use_site(cx.tcx, cx.typeck_results(), ctxt, expr); + let (Node::Expr(parent_expr), false) = (use_site.node, use_site.is_ty_unified) else { return false; }; // Check if `expr` is the argument of a compiler-generated `IntoIter::into_iter(expr)` if let ExprKind::Call(func, [arg]) = parent_expr.kind - && arg.hir_id == use_ctxt.child_id + && arg.hir_id == use_site.child_id && let ExprKind::Path(qpath) = func.kind && cx.tcx.qpath_is_lang_item(qpath, LangItem::IntoIterIntoIter) && parent_expr.span.is_desugaring(DesugaringKind::ForLoop) @@ -377,7 +378,7 @@ fn can_switch_ranges<'tcx>( // Check if `expr` is used as the receiver of a method of the `Iterator`, `IntoIterator`, // or `RangeBounds` traits. if let ExprKind::MethodCall(_, receiver, _, _) = parent_expr.kind - && receiver.hir_id == use_ctxt.child_id + && receiver.hir_id == use_site.child_id && let Some(method_did) = cx.typeck_results().type_dependent_def_id(parent_expr.hir_id) && let Some(trait_did) = cx.tcx.trait_of_assoc(method_did) && matches!( @@ -392,7 +393,7 @@ fn can_switch_ranges<'tcx>( // or `RangeBounds` trait. if let ExprKind::Call(_, args) | ExprKind::MethodCall(_, _, args, _) = parent_expr.kind && let Some(id) = fn_def_id(cx, parent_expr) - && let Some(arg_idx) = args.iter().position(|e| e.hir_id == use_ctxt.child_id) + && let Some(arg_idx) = args.iter().position(|e| e.hir_id == use_site.child_id) { let input_idx = if matches!(parent_expr.kind, ExprKind::MethodCall(..)) { arg_idx + 1 @@ -512,16 +513,16 @@ fn check_range_switch<'tcx>( && span.can_be_used_for_suggestions() && limits == kind && let Some(y) = predicate(cx, end) - && can_switch_ranges(cx, expr, kind, cx.typeck_results().expr_ty(y)) + && can_switch_ranges(cx, span.ctxt(), expr, kind, cx.typeck_results().expr_ty(y)) { span_lint_and_then(cx, lint, span, msg, |diag| { let mut app = Applicability::MachineApplicable; let start = start.map_or(String::new(), |x| { - Sugg::hir_with_applicability(cx, x, "", &mut app) + Sugg::hir_with_context(cx, x, span.ctxt(), "", &mut app) .maybe_paren() .to_string() }); - let end = Sugg::hir_with_applicability(cx, y, "", &mut app).maybe_paren(); + let end = Sugg::hir_with_context(cx, y, span.ctxt(), "", &mut app).maybe_paren(); match span.with_source_text(cx, |src| src.starts_with('(') && src.ends_with(')')) { Some(true) => { diag.span_suggestion(span, "use", format!("({start}{operator}{end})"), app); diff --git a/src/tools/clippy/clippy_lints/src/return_self_not_must_use.rs b/src/tools/clippy/clippy_lints/src/return_self_not_must_use.rs index 78f5167fa543..8c892b7085b7 100644 --- a/src/tools/clippy/clippy_lints/src/return_self_not_must_use.rs +++ b/src/tools/clippy/clippy_lints/src/return_self_not_must_use.rs @@ -70,7 +70,7 @@ fn check_method(cx: &LateContext<'_>, decl: &FnDecl<'_>, fn_def: LocalDefId, span: Span, owner_id: OwnerId) { if !span.in_external_macro(cx.sess().source_map()) // If it comes from an external macro, better ignore it. - && decl.implicit_self.has_implicit_self() + && decl.implicit_self().has_implicit_self() // We only show this warning for public exported methods. && cx.effective_visibilities.is_exported(fn_def) // We don't want to emit this lint if the `#[must_use]` attribute is already there. diff --git a/src/tools/clippy/clippy_lints/src/returns/let_and_return.rs b/src/tools/clippy/clippy_lints/src/returns/let_and_return.rs index b19935959c4d..57f33632a5bc 100644 --- a/src/tools/clippy/clippy_lints/src/returns/let_and_return.rs +++ b/src/tools/clippy/clippy_lints/src/returns/let_and_return.rs @@ -1,6 +1,6 @@ use clippy_utils::diagnostics::span_lint_hir_and_then; use clippy_utils::res::MaybeResPath; -use clippy_utils::source::SpanRangeExt; +use clippy_utils::source::snippet_with_context; use clippy_utils::sugg::has_enclosing_paren; use clippy_utils::visitors::for_each_expr; use clippy_utils::{binary_expr_needs_parentheses, fn_def_id, span_contains_non_whitespace}; @@ -19,6 +19,7 @@ pub(super) fn check_block<'tcx>(cx: &LateContext<'tcx>, block: &'tcx Block<'_>) && let Some(stmt) = block.stmts.last() && let StmtKind::Let(local) = &stmt.kind && local.ty.is_none() + && local.els.is_none() && cx.tcx.hir_attrs(local.hir_id).is_empty() && let Some(initexpr) = &local.init && let PatKind::Binding(_, local_id, _, _) = local.pat.kind @@ -38,30 +39,29 @@ pub(super) fn check_block<'tcx>(cx: &LateContext<'tcx>, block: &'tcx Block<'_>) |err| { err.span_label(local.span, "unnecessary `let` binding"); - if let Some(src) = initexpr.span.get_source_text(cx) { - let sugg = if binary_expr_needs_parentheses(initexpr) { - if has_enclosing_paren(&src) { - src.to_owned() - } else { - format!("({src})") - } - } else if !cx.typeck_results().expr_adjustments(retexpr).is_empty() { - if has_enclosing_paren(&src) { - format!("{src} as _") - } else { - format!("({src}) as _") - } + let mut app = Applicability::MachineApplicable; + let (src, _) = snippet_with_context(cx, initexpr.span, local.span.ctxt(), "..", &mut app); + + let sugg = if binary_expr_needs_parentheses(initexpr) { + if has_enclosing_paren(&src) { + src.to_string() } else { - src.to_owned() - }; - err.multipart_suggestion( - "return the expression directly", - vec![(local.span, String::new()), (retexpr.span, sugg)], - Applicability::MachineApplicable, - ); + format!("({src})") + } + } else if !cx.typeck_results().expr_adjustments(retexpr).is_empty() { + if has_enclosing_paren(&src) { + format!("{src} as _") + } else { + format!("({src}) as _") + } } else { - err.span_help(initexpr.span, "this expression can be directly returned"); - } + src.to_string() + }; + err.multipart_suggestion( + "return the expression directly", + vec![(local.span, String::new()), (retexpr.span, sugg)], + app, + ); }, ); } diff --git a/src/tools/clippy/clippy_lints/src/returns/needless_return.rs b/src/tools/clippy/clippy_lints/src/returns/needless_return.rs index aab6adf5d19a..619a70cd8dd1 100644 --- a/src/tools/clippy/clippy_lints/src/returns/needless_return.rs +++ b/src/tools/clippy/clippy_lints/src/returns/needless_return.rs @@ -4,11 +4,11 @@ binary_expr_needs_parentheses, is_from_proc_macro, leaks_droppable_temporary_with_limited_lifetime, span_contains_cfg, span_find_starting_semi, sym, }; +use rustc_ast::MetaItemInner; use rustc_errors::Applicability; -use rustc_hir::attrs::{AttributeKind, LintAttributeKind}; use rustc_hir::intravisit::FnKind; -use rustc_hir::{Attribute, Body, Expr, ExprKind, HirId, LangItem, MatchSource, StmtKind}; -use rustc_lint::{LateContext, LintContext}; +use rustc_hir::{Body, Expr, ExprKind, HirId, LangItem, MatchSource, StmtKind}; +use rustc_lint::{LateContext, Level, LintContext}; use rustc_middle::ty::{self, Ty}; use rustc_span::{BytePos, Pos, Span}; use std::borrow::Cow; @@ -180,18 +180,20 @@ fn check_final_expr<'tcx>( // actually fulfill the expectation (clippy::#12998) match cx.tcx.hir_attrs(expr.hir_id) { [] => {}, - [Attribute::Parsed(AttributeKind::LintAttributes(sub_attrs))] => { - if !sub_attrs - .into_iter() - .filter(|attr| attr.kind == LintAttributeKind::Expect) - .flat_map(|attr| &attr.lint_instances) - .any(|lint| { - matches!( - lint.original_name_without_tool(), - sym::needless_return | sym::style | sym::all | sym::warnings - ) - }) + [attr] => { + if matches!(Level::from_attr(attr), Some((Level::Expect, _))) + && let metas = attr.meta_item_list() + && let Some(lst) = metas + && let [MetaItemInner::MetaItem(meta_item), ..] = lst.as_slice() + && let [tool, lint_name] = meta_item.path.segments.as_slice() + && tool.ident.name == sym::clippy + && matches!( + lint_name.ident.name, + sym::needless_return | sym::style | sym::all | sym::warnings + ) { + // This is an expectation of the `needless_return` lint + } else { return; } }, @@ -257,7 +259,7 @@ fn emit_return_lint( // Go backwards while encountering whitespace and extend the given Span to that point. fn extend_span_to_previous_non_ws(cx: &LateContext<'_>, sp: Span) -> Span { if let Ok(prev_source) = cx.sess().source_map().span_to_prev_source(sp) { - let ws = [b' ', b'\t', b'\n']; + let ws = *b" \t\n"; if let Some(non_ws_pos) = prev_source.bytes().rposition(|c| !ws.contains(&c)) { let len = prev_source.len() - non_ws_pos - 1; return sp.with_lo(sp.lo() - BytePos::from_usize(len)); diff --git a/src/tools/clippy/clippy_lints/src/self_named_constructors.rs b/src/tools/clippy/clippy_lints/src/self_named_constructors.rs index 534ba3a50c6b..e32cf944536b 100644 --- a/src/tools/clippy/clippy_lints/src/self_named_constructors.rs +++ b/src/tools/clippy/clippy_lints/src/self_named_constructors.rs @@ -44,7 +44,7 @@ impl<'tcx> LateLintPass<'tcx> for SelfNamedConstructors { fn check_impl_item(&mut self, cx: &LateContext<'tcx>, impl_item: &'tcx ImplItem<'_>) { match impl_item.kind { ImplItemKind::Fn(ref sig, _) => { - if sig.decl.implicit_self.has_implicit_self() { + if sig.decl.implicit_self().has_implicit_self() { return; } }, diff --git a/src/tools/clippy/clippy_lints/src/swap.rs b/src/tools/clippy/clippy_lints/src/swap.rs index 01482b2475f7..262612a2a2d3 100644 --- a/src/tools/clippy/clippy_lints/src/swap.rs +++ b/src/tools/clippy/clippy_lints/src/swap.rs @@ -112,7 +112,7 @@ fn generate_swap_warning<'tcx>( || ty.is_diag_item(cx, sym::Vec) || ty.is_diag_item(cx, sym::VecDeque) { - let slice = Sugg::hir_with_applicability(cx, lhs1, "", &mut applicability); + let slice = Sugg::hir_with_context(cx, lhs1, ctxt, "", &mut applicability); span_lint_and_sugg( cx, diff --git a/src/tools/clippy/clippy_lints/src/trait_bounds.rs b/src/tools/clippy/clippy_lints/src/trait_bounds.rs index e7a785289f39..4cd3707854c4 100644 --- a/src/tools/clippy/clippy_lints/src/trait_bounds.rs +++ b/src/tools/clippy/clippy_lints/src/trait_bounds.rs @@ -115,7 +115,7 @@ fn check_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx Item<'tcx>) { // special handling for self trait bounds as these are not considered generics // i.e. trait Foo: Display {} if let Item { - kind: ItemKind::Trait(_, _, _, _, _, bounds, ..), + kind: ItemKind::Trait(_, _, _, _, _, _, bounds, ..), .. } = item { @@ -136,7 +136,7 @@ fn check_trait_item(&mut self, cx: &LateContext<'tcx>, item: &'tcx TraitItem<'tc .. }) = segments.first() && let Some(Node::Item(Item { - kind: ItemKind::Trait(_, _, _, _, _, self_bounds, _), + kind: ItemKind::Trait(_, _, _, _, _, _, self_bounds, _), .. })) = cx.tcx.hir_get_if_local(*def_id) { diff --git a/src/tools/clippy/clippy_lints/src/transmute/transmute_undefined_repr.rs b/src/tools/clippy/clippy_lints/src/transmute/transmute_undefined_repr.rs index 3e6aae475ecc..c097f7773099 100644 --- a/src/tools/clippy/clippy_lints/src/transmute/transmute_undefined_repr.rs +++ b/src/tools/clippy/clippy_lints/src/transmute/transmute_undefined_repr.rs @@ -242,6 +242,10 @@ fn reduce_ty<'tcx>(cx: &LateContext<'tcx>, mut ty: Ty<'tcx>) -> ReducedTy<'tcx> loop { ty = cx.tcx.try_normalize_erasing_regions(cx.typing_env(), ty).unwrap_or(ty); return match *ty.kind() { + ty::Pat(base, _) => { + ty = base; + continue; + }, ty::Array(sub_ty, _) if matches!(sub_ty.kind(), ty::Int(_) | ty::Uint(_)) => { ReducedTy::TypeErasure { raw_ptr_only: false } }, diff --git a/src/tools/clippy/clippy_lints/src/unconditional_recursion.rs b/src/tools/clippy/clippy_lints/src/unconditional_recursion.rs index 297f4c2df040..3df16bf71ce7 100644 --- a/src/tools/clippy/clippy_lints/src/unconditional_recursion.rs +++ b/src/tools/clippy/clippy_lints/src/unconditional_recursion.rs @@ -376,7 +376,7 @@ fn check_default_new<'tcx>( method_def_id: LocalDefId, ) { // We're only interested into static methods. - if decl.implicit_self.has_implicit_self() { + if decl.implicit_self().has_implicit_self() { return; } // We don't check trait implementations. diff --git a/src/tools/clippy/clippy_lints/src/unnested_or_patterns.rs b/src/tools/clippy/clippy_lints/src/unnested_or_patterns.rs index 712dcf60e695..d1096a02fd63 100644 --- a/src/tools/clippy/clippy_lints/src/unnested_or_patterns.rs +++ b/src/tools/clippy/clippy_lints/src/unnested_or_patterns.rs @@ -10,7 +10,6 @@ use rustc_ast::{self as ast, DUMMY_NODE_ID, Mutability, Pat, PatKind, Pinnedness}; use rustc_ast_pretty::pprust; use rustc_data_structures::thin_vec::{ThinVec, thin_vec}; -use rustc_data_structures::thinvec::ExtractIf; use rustc_errors::Applicability; use rustc_lint::{EarlyContext, EarlyLintPass}; use rustc_session::impl_lint_pass; @@ -422,9 +421,7 @@ fn drain_matching( let mut tail_or = ThinVec::new(); let mut idx = 0; - // FIXME: once `thin-vec` releases a new version, change this to `alternatives.extract_if()` - // See https://github.com/mozilla/thin-vec/issues/77 - for pat in ExtractIf::new(alternatives, |p| { + for pat in alternatives.extract_if(.., |p| { // Check if we should extract, but only if `idx >= start`. idx += 1; idx > start && predicate(&p.kind) diff --git a/src/tools/clippy/clippy_lints/src/unsafe_removed_from_name.rs b/src/tools/clippy/clippy_lints/src/unsafe_removed_from_name.rs index 90fac7bc0da0..d92e98d04de8 100644 --- a/src/tools/clippy/clippy_lints/src/unsafe_removed_from_name.rs +++ b/src/tools/clippy/clippy_lints/src/unsafe_removed_from_name.rs @@ -40,6 +40,9 @@ fn check_item(&mut self, cx: &EarlyContext<'_>, item: &Item) { fn check_use_tree(use_tree: &UseTree, cx: &EarlyContext<'_>, span: Span) { match use_tree.kind { UseTreeKind::Simple(Some(new_name)) => { + if new_name.as_str() == "_" { + return; + } let old_name = use_tree .prefix .segments diff --git a/src/tools/clippy/clippy_lints/src/unused_async.rs b/src/tools/clippy/clippy_lints/src/unused_async.rs index a4ebd8860dc0..f5e903426d57 100644 --- a/src/tools/clippy/clippy_lints/src/unused_async.rs +++ b/src/tools/clippy/clippy_lints/src/unused_async.rs @@ -211,7 +211,6 @@ fn async_fn_contains_todo_unimplemented_macro(cx: &LateContext<'_>, body: &Body< && let ClosureKind::Coroutine(CoroutineKind::Desugared(CoroutineDesugaring::Async, _)) = closure.kind && let body = cx.tcx.hir_body(closure.body) && let ExprKind::Block(block, _) = body.value.kind - && block.stmts.is_empty() && let Some(expr) = block.expr && let ExprKind::DropTemps(inner) = expr.kind { diff --git a/src/tools/clippy/clippy_lints/src/unwrap.rs b/src/tools/clippy/clippy_lints/src/unwrap.rs index cfd3f420db5a..d87289e1362d 100644 --- a/src/tools/clippy/clippy_lints/src/unwrap.rs +++ b/src/tools/clippy/clippy_lints/src/unwrap.rs @@ -308,18 +308,15 @@ fn extract_local(cx: &LateContext<'_>, mut expr: &Expr<'_>) -> Option { field_indices.push(field_idx); expr = recv; } - if let Some(local_id) = expr.res_local_id() { - if field_indices.is_empty() { - Some(Local::Pure { local_id }) - } else { - Some(Local::WithFieldAccess { - local_id, - field_indices, - span, - }) - } + let local_id = expr.res_local_id()?; + if field_indices.is_empty() { + Some(Local::Pure { local_id }) } else { - None + Some(Local::WithFieldAccess { + local_id, + field_indices, + span, + }) } } diff --git a/src/tools/clippy/clippy_lints/src/upper_case_acronyms.rs b/src/tools/clippy/clippy_lints/src/upper_case_acronyms.rs index 6ea6a0ad85aa..52dfcab363db 100644 --- a/src/tools/clippy/clippy_lints/src/upper_case_acronyms.rs +++ b/src/tools/clippy/clippy_lints/src/upper_case_acronyms.rs @@ -131,7 +131,7 @@ fn check_item(&mut self, cx: &LateContext<'_>, it: &Item<'_>) { return; } match it.kind { - ItemKind::TyAlias(ident, ..) | ItemKind::Struct(ident, ..) | ItemKind::Trait(_, _, _, ident, ..) => { + ItemKind::TyAlias(ident, ..) | ItemKind::Struct(ident, ..) | ItemKind::Trait(_, _, _, _, ident, ..) => { check_ident(cx, &ident, it.hir_id(), self.upper_case_acronyms_aggressive); }, ItemKind::Enum(ident, _, ref enumdef) => { diff --git a/src/tools/clippy/clippy_lints/src/write/empty_string.rs b/src/tools/clippy/clippy_lints/src/write/empty_string.rs index fa2ad4ba94a2..31869e0d2cda 100644 --- a/src/tools/clippy/clippy_lints/src/write/empty_string.rs +++ b/src/tools/clippy/clippy_lints/src/write/empty_string.rs @@ -1,6 +1,6 @@ use clippy_utils::diagnostics::span_lint_and_then; use clippy_utils::macros::MacroCall; -use clippy_utils::source::expand_past_previous_comma; +use clippy_utils::source::{expand_past_previous_comma, snippet_opt}; use clippy_utils::{span_extract_comments, sym}; use rustc_ast::{FormatArgs, FormatArgsPiece}; use rustc_errors::Applicability; @@ -23,17 +23,23 @@ pub(super) fn check(cx: &LateContext<'_>, format_args: &FormatArgs, macro_call: format!("empty string literal in `{name}!`"), |diag| { if span_extract_comments(cx, macro_call.span).is_empty() { - let closing_paren = cx.sess().source_map().span_extend_to_prev_char_before( - macro_call.span.shrink_to_hi(), - ')', - false, - ); - let mut span = format_args.span.with_hi(closing_paren.lo()); - if is_writeln { - span = expand_past_previous_comma(cx, span); - } + let closing_delim = snippet_opt(cx, macro_call.span) + .and_then(|snippet| snippet.chars().last()) + .filter(|ch| matches!(ch, ')' | ']' | '}')); - diag.span_suggestion(span, "remove the empty string", "", Applicability::MachineApplicable); + if let Some(closing_delim) = closing_delim { + let closing_paren = cx.sess().source_map().span_extend_to_prev_char_before( + macro_call.span.shrink_to_hi(), + closing_delim, + false, + ); + let mut span = format_args.span.with_hi(closing_paren.lo()); + if is_writeln { + span = expand_past_previous_comma(cx, span); + } + + diag.span_suggestion(span, "remove the empty string", "", Applicability::MachineApplicable); + } } else { // If there is a comment in the span of macro call, we don't provide an auto-fix suggestion. diag.span_note(format_args.span, "remove the empty string"); diff --git a/src/tools/clippy/clippy_utils/Cargo.toml b/src/tools/clippy/clippy_utils/Cargo.toml index 9800a75035fa..3d87129e8953 100644 --- a/src/tools/clippy/clippy_utils/Cargo.toml +++ b/src/tools/clippy/clippy_utils/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "clippy_utils" -version = "0.1.96" +version = "0.1.97" edition = "2024" description = "Helpful tools for writing lints, provided as they are used in Clippy" repository = "https://github.com/rust-lang/rust-clippy" diff --git a/src/tools/clippy/clippy_utils/README.md b/src/tools/clippy/clippy_utils/README.md index 683ca090e92a..99489cb11e73 100644 --- a/src/tools/clippy/clippy_utils/README.md +++ b/src/tools/clippy/clippy_utils/README.md @@ -8,7 +8,7 @@ This crate is only guaranteed to build with this `nightly` toolchain: ``` -nightly-2026-04-02 +nightly-2026-04-16 ``` diff --git a/src/tools/clippy/clippy_utils/src/ast_utils/mod.rs b/src/tools/clippy/clippy_utils/src/ast_utils/mod.rs index cfff7da60a6a..c96c0649753f 100644 --- a/src/tools/clippy/clippy_utils/src/ast_utils/mod.rs +++ b/src/tools/clippy/clippy_utils/src/ast_utils/mod.rs @@ -339,6 +339,7 @@ pub fn eq_item_kind(l: &ItemKind, r: &ItemKind) -> bool { expr: le, safety: ls, define_opaque: _, + eii_impls: _, }), Static(box StaticItem { ident: ri, @@ -347,6 +348,7 @@ pub fn eq_item_kind(l: &ItemKind, r: &ItemKind) -> bool { expr: re, safety: rs, define_opaque: _, + eii_impls: _, }), ) => eq_id(*li, *ri) && lm == rm && ls == rs && eq_ty(lt, rt) && eq_expr_opt(le.as_deref(), re.as_deref()), ( @@ -540,6 +542,7 @@ pub fn eq_foreign_item_kind(l: &ForeignItemKind, r: &ForeignItemKind) -> bool { expr: le, safety: ls, define_opaque: _, + eii_impls: _, }), Static(box StaticItem { ident: ri, @@ -548,6 +551,7 @@ pub fn eq_foreign_item_kind(l: &ForeignItemKind, r: &ForeignItemKind) -> bool { expr: re, safety: rs, define_opaque: _, + eii_impls: _, }), ) => eq_id(*li, *ri) && eq_ty(lt, rt) && lm == rm && eq_expr_opt(le.as_deref(), re.as_deref()) && ls == rs, ( diff --git a/src/tools/clippy/clippy_utils/src/hir_utils.rs b/src/tools/clippy/clippy_utils/src/hir_utils.rs index a4d8fd20e4d3..4d9ddb388f3c 100644 --- a/src/tools/clippy/clippy_utils/src/hir_utils.rs +++ b/src/tools/clippy/clippy_utils/src/hir_utils.rs @@ -257,9 +257,9 @@ fn eq_fn_decl(&mut self, left: &FnDecl<'_>, right: &FnDecl<'_>) -> bool { (FnRetTy::Return(l_ty), FnRetTy::Return(r_ty)) => self.eq_ty(l_ty, r_ty), _ => false, }) - && left.c_variadic == right.c_variadic - && left.implicit_self == right.implicit_self - && left.lifetime_elision_allowed == right.lifetime_elision_allowed + && left.c_variadic() == right.c_variadic() + && left.implicit_self() == right.implicit_self() + && left.lifetime_elision_allowed() == right.lifetime_elision_allowed() } fn eq_generics(&mut self, left: &Generics<'_>, right: &Generics<'_>) -> bool { @@ -1571,7 +1571,7 @@ pub fn hash_tykind(&mut self, ty: &TyKind<'_>) { self.hash_ty(ty); }, } - fn_ptr.decl.c_variadic.hash(&mut self.s); + fn_ptr.decl.c_variadic().hash(&mut self.s); }, TyKind::Tup(ty_list) => { for ty in *ty_list { diff --git a/src/tools/clippy/clippy_utils/src/lib.rs b/src/tools/clippy/clippy_utils/src/lib.rs index a8ff9b4cf6fb..a1860adb4407 100644 --- a/src/tools/clippy/clippy_utils/src/lib.rs +++ b/src/tools/clippy/clippy_utils/src/lib.rs @@ -1,6 +1,5 @@ #![feature(box_patterns)] #![feature(macro_metavar_expr)] -#![feature(never_type)] #![feature(rustc_private)] #![feature(unwrap_infallible)] #![recursion_limit = "512"] @@ -94,11 +93,12 @@ use rustc_hir::hir_id::{HirIdMap, HirIdSet}; use rustc_hir::intravisit::{Visitor, walk_expr}; use rustc_hir::{ - self as hir, Arm, BindingMode, Block, BlockCheckMode, Body, ByRef, Closure, ConstArgKind, CoroutineDesugaring, - CoroutineKind, CoroutineSource, Destination, Expr, ExprField, ExprKind, FnDecl, FnRetTy, GenericArg, GenericArgs, - HirId, Impl, ImplItem, ImplItemKind, Item, ItemKind, LangItem, LetStmt, MatchSource, Mutability, Node, OwnerId, - OwnerNode, Param, Pat, PatExpr, PatExprKind, PatKind, Path, PathSegment, QPath, Stmt, StmtKind, TraitFn, TraitItem, - TraitItemKind, TraitRef, TyKind, UnOp, def, find_attr, + self as hir, AnonConst, Arm, BindingMode, Block, BlockCheckMode, Body, ByRef, CRATE_HIR_ID, Closure, ConstArg, + ConstArgKind, CoroutineDesugaring, CoroutineKind, CoroutineSource, Destination, Expr, ExprField, ExprKind, + FieldDef, FnDecl, FnRetTy, GenericArg, GenericArgs, HirId, Impl, ImplItem, ImplItemKind, Item, ItemKind, LangItem, + LetStmt, MatchSource, Mutability, Node, OwnerId, OwnerNode, Param, Pat, PatExpr, PatExprKind, PatKind, Path, + PathSegment, QPath, Stmt, StmtKind, TraitFn, TraitItem, TraitItemKind, TraitRef, TyKind, UnOp, Variant, def, + find_attr, }; use rustc_lexer::{FrontmatterAllowed, TokenKind, tokenize}; use rustc_lint::{LateContext, Level, Lint, LintContext}; @@ -110,12 +110,12 @@ use rustc_middle::ty::layout::IntegerExt; use rustc_middle::ty::{ self as rustc_ty, Binder, BorrowKind, ClosureKind, EarlyBinder, GenericArgKind, GenericArgsRef, IntTy, Ty, TyCtxt, - TypeFlags, TypeVisitableExt, UintTy, UpvarCapture, + TypeFlags, TypeVisitableExt, TypeckResults, UintTy, UpvarCapture, }; use rustc_span::hygiene::{ExpnKind, MacroKind}; use rustc_span::source_map::SourceMap; use rustc_span::symbol::{Ident, Symbol, kw}; -use rustc_span::{InnerSpan, Span}; +use rustc_span::{InnerSpan, Span, SyntaxContext}; use source::{SpanRangeExt, walk_span_to_context}; use visitors::{Visitable, for_each_unconsumed_temporary}; @@ -840,11 +840,10 @@ fn pat_capture_kind(cx: &LateContext<'_>, pat: &Pat<'_>) -> CaptureKind { ExprKind::Path(QPath::Resolved(None, Path { res: Res::Local(_), .. })) )); - let mut child_id = e.hir_id; let mut capture = CaptureKind::Value; let mut capture_expr_ty = e; - for (parent_id, parent) in cx.tcx.hir_parent_iter(e.hir_id) { + for (parent, child_id) in hir_parent_with_src_iter(cx.tcx, e.hir_id) { if let [ Adjustment { kind: Adjust::Deref(_) | Adjust::Borrow(AutoBorrow::Ref(..)), @@ -900,8 +899,6 @@ fn pat_capture_kind(cx: &LateContext<'_>, pat: &Pat<'_>) -> CaptureKind { }, _ => break, } - - child_id = parent_id; } if capture == CaptureKind::Value && is_copy(cx, cx.typeck_results().expr_ty(capture_expr_ty)) { @@ -1297,38 +1294,28 @@ pub fn is_else_clause(tcx: TyCtxt<'_>, expr: &Expr<'_>) -> bool { /// Checks if the given expression is a part of `let else` /// returns `true` for both the `init` and the `else` part pub fn is_inside_let_else(tcx: TyCtxt<'_>, expr: &Expr<'_>) -> bool { - let mut child_id = expr.hir_id; - for (parent_id, node) in tcx.hir_parent_iter(child_id) { - if let Node::LetStmt(LetStmt { - init: Some(init), - els: Some(els), - .. - }) = node - && (init.hir_id == child_id || els.hir_id == child_id) - { - return true; - } - - child_id = parent_id; - } - - false + hir_parent_with_src_iter(tcx, expr.hir_id).any(|(node, child_id)| { + matches!( + node, + Node::LetStmt(LetStmt { + init: Some(init), + els: Some(els), + .. + }) + if init.hir_id == child_id || els.hir_id == child_id + ) + }) } /// Checks if the given expression is the else clause of a `let else` expression pub fn is_else_clause_in_let_else(tcx: TyCtxt<'_>, expr: &Expr<'_>) -> bool { - let mut child_id = expr.hir_id; - for (parent_id, node) in tcx.hir_parent_iter(child_id) { - if let Node::LetStmt(LetStmt { els: Some(els), .. }) = node - && els.hir_id == child_id - { - return true; - } - - child_id = parent_id; - } - - false + hir_parent_with_src_iter(tcx, expr.hir_id).any(|(node, child_id)| { + matches!( + node, + Node::LetStmt(LetStmt { els: Some(els), .. }) + if els.hir_id == child_id + ) + }) } /// Checks whether the given `Expr` is a range equivalent to a `RangeFull`. @@ -2048,22 +2035,20 @@ pub fn is_expr_identity_function(cx: &LateContext<'_>, expr: &Expr<'_>) -> bool /// Gets the node where an expression is either used, or it's type is unified with another branch. /// Returns both the node and the `HirId` of the closest child node. pub fn get_expr_use_or_unification_node<'tcx>(tcx: TyCtxt<'tcx>, expr: &Expr<'_>) -> Option<(Node<'tcx>, HirId)> { - let mut child_id = expr.hir_id; - let mut iter = tcx.hir_parent_iter(child_id); - loop { - match iter.next() { - None => break None, - Some((id, Node::Block(_))) => child_id = id, - Some((id, Node::Arm(arm))) if arm.body.hir_id == child_id => child_id = id, - Some((_, Node::Expr(expr))) => match expr.kind { - ExprKind::Match(_, [arm], _) if arm.hir_id == child_id => child_id = expr.hir_id, - ExprKind::Block(..) | ExprKind::DropTemps(_) => child_id = expr.hir_id, - ExprKind::If(_, then_expr, None) if then_expr.hir_id == child_id => break None, - _ => break Some((Node::Expr(expr), child_id)), + for (node, child_id) in hir_parent_with_src_iter(tcx, expr.hir_id) { + match node { + Node::Block(_) => {}, + Node::Arm(arm) if arm.body.hir_id == child_id => {}, + Node::Expr(expr) => match expr.kind { + ExprKind::Block(..) | ExprKind::DropTemps(_) => {}, + ExprKind::Match(_, [arm], _) if arm.hir_id == child_id => {}, + ExprKind::If(_, then_expr, None) if then_expr.hir_id == child_id => return None, + _ => return Some((Node::Expr(expr), child_id)), }, - Some((_, node)) => break Some((node, child_id)), + node => return Some((node, child_id)), } } + None } /// Checks if the result of an expression is used, or it's type is unified with another branch. @@ -2400,8 +2385,7 @@ pub fn is_hir_ty_cfg_dependant(cx: &LateContext<'_>, ty: &hir::Ty<'_>) -> bool { if let TyKind::Path(QPath::Resolved(_, path)) = ty.kind && let Res::Def(_, def_id) = path.res { - #[allow(deprecated)] - return cx.tcx.has_attr(def_id, sym::cfg) || cx.tcx.has_attr(def_id, sym::cfg_attr); + return find_attr!(cx.tcx, def_id, CfgTrace(..) | CfgAttrTrace); } false } @@ -2508,60 +2492,12 @@ pub fn is_in_test(tcx: TyCtxt<'_>, hir_id: HirId) -> bool { pub fn inherits_cfg(tcx: TyCtxt<'_>, def_id: LocalDefId) -> bool { find_attr!(tcx, def_id, CfgTrace(..)) || find_attr!( - tcx.hir_parent_iter(tcx.local_def_id_to_hir_id(def_id)) - .flat_map(|(parent_id, _)| tcx.hir_attrs(parent_id)), + tcx.hir_parent_id_iter(tcx.local_def_id_to_hir_id(def_id)) + .flat_map(|parent_id| tcx.hir_attrs(parent_id)), CfgTrace(..) ) } -/// Walks up the HIR tree from the given expression in an attempt to find where the value is -/// consumed. -/// -/// Termination has three conditions: -/// - The given function returns `Break`. This function will return the value. -/// - The consuming node is found. This function will return `Continue(use_node, child_id)`. -/// - No further parent nodes are found. This will trigger a debug assert or return `None`. -/// -/// This allows walking through `if`, `match`, `break`, and block expressions to find where the -/// value produced by the expression is consumed. -pub fn walk_to_expr_usage<'tcx, T>( - cx: &LateContext<'tcx>, - e: &Expr<'tcx>, - mut f: impl FnMut(HirId, Node<'tcx>, HirId) -> ControlFlow, -) -> Option, HirId)>> { - let mut iter = cx.tcx.hir_parent_iter(e.hir_id); - let mut child_id = e.hir_id; - - while let Some((parent_id, parent)) = iter.next() { - if let ControlFlow::Break(x) = f(parent_id, parent, child_id) { - return Some(ControlFlow::Break(x)); - } - let parent_expr = match parent { - Node::Expr(e) => e, - Node::Block(Block { expr: Some(body), .. }) | Node::Arm(Arm { body, .. }) if body.hir_id == child_id => { - child_id = parent_id; - continue; - }, - Node::Arm(a) if a.body.hir_id == child_id => { - child_id = parent_id; - continue; - }, - _ => return Some(ControlFlow::Continue((parent, child_id))), - }; - match parent_expr.kind { - ExprKind::If(child, ..) | ExprKind::Match(child, ..) if child.hir_id != child_id => child_id = parent_id, - ExprKind::Break(Destination { target_id: Ok(id), .. }, _) => { - child_id = id; - iter = cx.tcx.hir_parent_iter(id); - }, - ExprKind::Block(..) | ExprKind::DropTemps(_) => child_id = parent_id, - _ => return Some(ControlFlow::Continue((parent, child_id))), - } - } - debug_assert!(false, "no parent node found for `{child_id:?}`"); - None -} - /// A type definition as it would be viewed from within a function. #[derive(Clone, Copy)] pub enum DefinedTy<'tcx> { @@ -2580,11 +2516,11 @@ pub enum DefinedTy<'tcx> { }, } -/// The context an expressions value is used in. -pub struct ExprUseCtxt<'tcx> { +/// The location that recives the value of an expression. +pub struct ExprUseSite<'tcx> { /// The parent node which consumes the value. pub node: Node<'tcx>, - /// The child id of the node the value came from. + /// The ID of the immediate child of the use node. pub child_id: HirId, /// Any adjustments applied to the type. pub adjustments: &'tcx [Adjustment<'tcx>], @@ -2595,7 +2531,7 @@ pub struct ExprUseCtxt<'tcx> { /// Whether the use site has the same `SyntaxContext` as the value. pub same_ctxt: bool, } -impl<'tcx> ExprUseCtxt<'tcx> { +impl<'tcx> ExprUseSite<'tcx> { pub fn use_node(&self, cx: &LateContext<'tcx>) -> ExprUseNode<'tcx> { match self.node { Node::LetStmt(l) => ExprUseNode::LetStmt(l), @@ -2761,54 +2697,178 @@ pub fn defined_ty(&self, cx: &LateContext<'tcx>) -> Option> { } } -/// Gets the context an expression's value is used in. -pub fn expr_use_ctxt<'tcx>(cx: &LateContext<'tcx>, e: &Expr<'tcx>) -> ExprUseCtxt<'tcx> { - let mut adjustments = [].as_slice(); +struct ReplacingFilterMap(I, F); +impl Iterator for ReplacingFilterMap +where + I: Iterator, + F: FnMut(&mut I, I::Item) -> Option, +{ + type Item = U; + fn next(&mut self) -> Option { + while let Some(x) = self.0.next() { + if let Some(x) = (self.1)(&mut self.0, x) { + return Some(x); + } + } + None + } +} + +/// Returns an iterator which walks successive value using parent nodes skipping any node +/// which simply moves a value. +#[expect(clippy::too_many_lines)] +pub fn expr_use_sites<'tcx>( + tcx: TyCtxt<'tcx>, + typeck: &'tcx TypeckResults<'tcx>, + mut ctxt: SyntaxContext, + e: &'tcx Expr<'tcx>, +) -> impl Iterator> { + let mut adjustments: &[_] = typeck.expr_adjustments(e); let mut is_ty_unified = false; let mut moved_before_use = false; let mut same_ctxt = true; - let ctxt = e.span.ctxt(); - let node = walk_to_expr_usage(cx, e, &mut |parent_id, parent, child_id| -> ControlFlow { - if adjustments.is_empty() - && let Node::Expr(e) = cx.tcx.hir_node(child_id) - { - adjustments = cx.typeck_results().expr_adjustments(e); - } - same_ctxt &= cx.tcx.hir_span(parent_id).ctxt() == ctxt; - if let Node::Expr(e) = parent { - match e.kind { - ExprKind::If(e, _, _) | ExprKind::Match(e, _, _) if e.hir_id != child_id => { - is_ty_unified = true; - moved_before_use = true; + ReplacingFilterMap( + hir_parent_with_src_iter(tcx, e.hir_id), + move |iter: &mut _, (parent, child_id)| { + let parent_ctxt; + let mut parent_adjustments: &[_] = &[]; + match parent { + Node::Expr(parent_expr) => { + parent_ctxt = parent_expr.span.ctxt(); + same_ctxt &= parent_ctxt == ctxt; + parent_adjustments = typeck.expr_adjustments(parent_expr); + match parent_expr.kind { + ExprKind::Match(scrutinee, arms, _) if scrutinee.hir_id != child_id => { + is_ty_unified |= arms.len() != 1; + moved_before_use = true; + if adjustments.is_empty() { + adjustments = parent_adjustments; + } + return None; + }, + ExprKind::If(cond, _, else_) if cond.hir_id != child_id => { + is_ty_unified |= else_.is_some(); + moved_before_use = true; + if adjustments.is_empty() { + adjustments = parent_adjustments; + } + return None; + }, + ExprKind::Break(Destination { target_id: Ok(id), .. }, _) => { + is_ty_unified = true; + moved_before_use = true; + *iter = hir_parent_with_src_iter(tcx, id); + if adjustments.is_empty() { + adjustments = parent_adjustments; + } + return None; + }, + ExprKind::Block(b, _) => { + is_ty_unified |= b.targeted_by_break; + moved_before_use = true; + if adjustments.is_empty() { + adjustments = parent_adjustments; + } + return None; + }, + ExprKind::DropTemps(_) | ExprKind::Type(..) => { + if adjustments.is_empty() { + adjustments = parent_adjustments; + } + return None; + }, + _ => {}, + } }, - ExprKind::Block(_, Some(_)) | ExprKind::Break(..) => { - is_ty_unified = true; - moved_before_use = true; + Node::Arm(arm) => { + parent_ctxt = arm.span.ctxt(); + same_ctxt &= parent_ctxt == ctxt; + if arm.body.hir_id == child_id { + return None; + } + }, + Node::Block(b) => { + same_ctxt &= b.span.ctxt() == ctxt; + return None; + }, + Node::ConstBlock(_) => parent_ctxt = ctxt, + Node::ExprField(&ExprField { span, .. }) => { + parent_ctxt = span.ctxt(); + same_ctxt &= parent_ctxt == ctxt; + }, + Node::AnonConst(&AnonConst { span, .. }) + | Node::ConstArg(&ConstArg { span, .. }) + | Node::Field(&FieldDef { span, .. }) + | Node::ImplItem(&ImplItem { span, .. }) + | Node::Item(&Item { span, .. }) + | Node::LetStmt(&LetStmt { span, .. }) + | Node::Stmt(&Stmt { span, .. }) + | Node::TraitItem(&TraitItem { span, .. }) + | Node::Variant(&Variant { span, .. }) => { + parent_ctxt = span.ctxt(); + same_ctxt &= parent_ctxt == ctxt; + *iter = hir_parent_with_src_iter(tcx, CRATE_HIR_ID); + }, + Node::AssocItemConstraint(_) + | Node::ConstArgExprField(_) + | Node::Crate(_) + | Node::Ctor(_) + | Node::Err(_) + | Node::ForeignItem(_) + | Node::GenericParam(_) + | Node::Infer(_) + | Node::Lifetime(_) + | Node::OpaqueTy(_) + | Node::Param(_) + | Node::Pat(_) + | Node::PatExpr(_) + | Node::PatField(_) + | Node::PathSegment(_) + | Node::PreciseCapturingNonLifetimeArg(_) + | Node::Synthetic + | Node::TraitRef(_) + | Node::Ty(_) + | Node::TyPat(_) + | Node::WherePredicate(_) => { + // This shouldn't be possible to hit; the inner iterator should have + // been moved to the end before we hit any of these nodes. + debug_assert!(false, "found {parent:?} which is after the final use node"); + return None; }, - ExprKind::Block(..) => moved_before_use = true, - _ => {}, } - } - ControlFlow::Continue(()) - }); - match node { - Some(ControlFlow::Continue((node, child_id))) => ExprUseCtxt { - node, - child_id, - adjustments, - is_ty_unified, - moved_before_use, - same_ctxt, + + ctxt = parent_ctxt; + Some(ExprUseSite { + node: parent, + child_id, + adjustments: mem::replace(&mut adjustments, parent_adjustments), + is_ty_unified: mem::replace(&mut is_ty_unified, false), + moved_before_use: mem::replace(&mut moved_before_use, false), + same_ctxt: mem::replace(&mut same_ctxt, true), + }) }, - None => ExprUseCtxt { - node: Node::Crate(cx.tcx.hir_root_module()), - child_id: HirId::INVALID, + ) +} + +pub fn get_expr_use_site<'tcx>( + tcx: TyCtxt<'tcx>, + typeck: &'tcx TypeckResults<'tcx>, + ctxt: SyntaxContext, + e: &'tcx Expr<'tcx>, +) -> ExprUseSite<'tcx> { + // The value in `unwrap_or` doesn't actually matter; an expression always + // has a use site. + expr_use_sites(tcx, typeck, ctxt, e).next().unwrap_or_else(|| { + debug_assert!(false, "failed to find a use site for expr {e:?}"); + ExprUseSite { + node: Node::Synthetic, // The crate root would also work. + child_id: CRATE_HIR_ID, adjustments: &[], - is_ty_unified: true, - moved_before_use: true, + is_ty_unified: false, + moved_before_use: false, same_ctxt: false, - }, - } + } + }) } /// Tokenizes the input while keeping the text associated with each token. @@ -3643,3 +3703,11 @@ pub fn is_expr_async_block(expr: &Expr<'_>) -> bool { pub fn can_use_if_let_chains(cx: &LateContext<'_>, msrv: Msrv) -> bool { cx.tcx.sess.edition().at_least_rust_2024() && msrv.meets(cx, msrvs::LET_CHAINS) } + +/// Returns an iterator over successive parent nodes paired with the ID of the node which +/// immediatly preceeded them. +#[inline] +pub fn hir_parent_with_src_iter(tcx: TyCtxt<'_>, mut id: HirId) -> impl Iterator, HirId)> { + tcx.hir_parent_id_iter(id) + .map(move |parent| (tcx.hir_node(parent), mem::replace(&mut id, parent))) +} diff --git a/src/tools/clippy/clippy_utils/src/msrvs.rs b/src/tools/clippy/clippy_utils/src/msrvs.rs index 4f9a064bf7a6..a56e729c70bb 100644 --- a/src/tools/clippy/clippy_utils/src/msrvs.rs +++ b/src/tools/clippy/clippy_utils/src/msrvs.rs @@ -28,7 +28,7 @@ macro_rules! msrv_aliases { 1,88,0 { LET_CHAINS } 1,87,0 { OS_STR_DISPLAY, INT_MIDPOINT, CONST_CHAR_IS_DIGIT, UNSIGNED_IS_MULTIPLE_OF, INTEGER_SIGN_CAST } 1,86,0 { VEC_POP_IF } - 1,85,0 { UINT_FLOAT_MIDPOINT, CONST_SIZE_OF_VAL } + 1,85,0 { UINT_FLOAT_MIDPOINT, CONST_SIZE_OF_VAL, WAKER_NOOP } 1,84,0 { CONST_OPTION_AS_SLICE, MANUAL_DANGLING_PTR } 1,83,0 { CONST_EXTERN_FN, CONST_FLOAT_BITS_CONV, CONST_FLOAT_CLASSIFY, CONST_MUT_REFS, CONST_UNWRAP } 1,82,0 { IS_NONE_OR, REPEAT_N, RAW_REF_OP, SPECIALIZED_TO_STRING_FOR_REFS } diff --git a/src/tools/clippy/clippy_utils/src/sugg.rs b/src/tools/clippy/clippy_utils/src/sugg.rs index 641c6684a0bd..9df2baa0d39a 100644 --- a/src/tools/clippy/clippy_utils/src/sugg.rs +++ b/src/tools/clippy/clippy_utils/src/sugg.rs @@ -335,6 +335,11 @@ pub fn blockify(self) -> Sugg<'static> { Sugg::NonParen(Cow::Owned(format!("{{ {self} }}"))) } + /// Convenience method to wrap the expression in an `unsafe` block. + pub fn unsafeify(self) -> Sugg<'static> { + Sugg::NonParen(Cow::Owned(format!("unsafe {{ {self} }}"))) + } + /// Convenience method to prefix the expression with the `async` keyword. /// Can be used after `blockify` to create an async block. pub fn asyncify(self) -> Sugg<'static> { diff --git a/src/tools/clippy/clippy_utils/src/sym.rs b/src/tools/clippy/clippy_utils/src/sym.rs index 03d81e010f7b..4eaeafe12707 100644 --- a/src/tools/clippy/clippy_utils/src/sym.rs +++ b/src/tools/clippy/clippy_utils/src/sym.rs @@ -50,7 +50,6 @@ macro_rules! generate { Cargo_toml: "Cargo.toml", Child, Command, - Cow, Current, DOUBLE_QUOTE: "\"", DebugStruct, diff --git a/src/tools/clippy/clippy_utils/src/ty/mod.rs b/src/tools/clippy/clippy_utils/src/ty/mod.rs index ac807c0382fe..7f22df27f5c1 100644 --- a/src/tools/clippy/clippy_utils/src/ty/mod.rs +++ b/src/tools/clippy/clippy_utils/src/ty/mod.rs @@ -1265,17 +1265,14 @@ pub fn deref_chain<'cx, 'tcx>(cx: &'cx LateContext<'tcx>, ty: Ty<'tcx>) -> impl /// This does not look for impls in the type's `Deref::Target` type. /// If you need this, you should wrap this call in `clippy_utils::ty::deref_chain().any(...)`. pub fn get_adt_inherent_method<'a>(cx: &'a LateContext<'_>, ty: Ty<'_>, method_name: Symbol) -> Option<&'a AssocItem> { - if let Some(ty_did) = ty.ty_adt_def().map(AdtDef::did) { - cx.tcx.inherent_impls(ty_did).iter().find_map(|&did| { - cx.tcx - .associated_items(did) - .filter_by_name_unhygienic(method_name) - .next() - .filter(|item| item.tag() == AssocTag::Fn) - }) - } else { - None - } + let ty_did = ty.ty_adt_def().map(AdtDef::did)?; + cx.tcx.inherent_impls(ty_did).iter().find_map(|&did| { + cx.tcx + .associated_items(did) + .filter_by_name_unhygienic(method_name) + .next() + .filter(|item| item.tag() == AssocTag::Fn) + }) } /// Gets the type of a field by name. diff --git a/src/tools/clippy/clippy_utils/src/visitors.rs b/src/tools/clippy/clippy_utils/src/visitors.rs index 6ac979d595f4..28449a75a8fc 100644 --- a/src/tools/clippy/clippy_utils/src/visitors.rs +++ b/src/tools/clippy/clippy_utils/src/visitors.rs @@ -437,7 +437,7 @@ fn visit_expr(&mut self, e: &'tcx Expr<'_>) -> Self::Result { ty::FnDef(id, _) if self.cx.tcx.fn_sig(id).skip_binder().safety().is_unsafe() => { ControlFlow::Break(()) }, - ty::FnPtr(_, hdr) if hdr.safety.is_unsafe() => ControlFlow::Break(()), + ty::FnPtr(_, hdr) if hdr.safety().is_unsafe() => ControlFlow::Break(()), _ => walk_expr(self, e), }, ExprKind::Path(ref p) diff --git a/src/tools/clippy/declare_clippy_lint/Cargo.toml b/src/tools/clippy/declare_clippy_lint/Cargo.toml index c55e084ad52f..d350af46d97a 100644 --- a/src/tools/clippy/declare_clippy_lint/Cargo.toml +++ b/src/tools/clippy/declare_clippy_lint/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "declare_clippy_lint" -version = "0.1.96" +version = "0.1.97" edition = "2024" repository = "https://github.com/rust-lang/rust-clippy" license = "MIT OR Apache-2.0" diff --git a/src/tools/clippy/lintcheck/Cargo.toml b/src/tools/clippy/lintcheck/Cargo.toml index 34281f9f721b..197a8574af2d 100644 --- a/src/tools/clippy/lintcheck/Cargo.toml +++ b/src/tools/clippy/lintcheck/Cargo.toml @@ -11,7 +11,7 @@ publish = false default-run = "lintcheck" [dependencies] -cargo_metadata = "0.15.3" +cargo_metadata = "0.23" clap = { version = "4.4", features = ["derive", "env"] } crossbeam-channel = "0.5.6" diff = "0.1.13" diff --git a/src/tools/clippy/rust-toolchain.toml b/src/tools/clippy/rust-toolchain.toml index 22b548848805..97c8cf260cad 100644 --- a/src/tools/clippy/rust-toolchain.toml +++ b/src/tools/clippy/rust-toolchain.toml @@ -1,6 +1,6 @@ [toolchain] # begin autogenerated nightly -channel = "nightly-2026-04-02" +channel = "nightly-2026-04-16" # end autogenerated nightly components = ["cargo", "llvm-tools", "rust-src", "rust-std", "rustc", "rustc-dev", "rustfmt"] profile = "minimal" diff --git a/src/tools/clippy/tests/ui/bind_instead_of_map.fixed b/src/tools/clippy/tests/ui/bind_instead_of_map.fixed index fa35a01242d1..a1c4cb5a4823 100644 --- a/src/tools/clippy/tests/ui/bind_instead_of_map.fixed +++ b/src/tools/clippy/tests/ui/bind_instead_of_map.fixed @@ -1,4 +1,5 @@ #![deny(clippy::bind_instead_of_map)] +#![allow(clippy::manual_filter)] // need a main anyway, use it get rid of unused warnings too pub fn main() { diff --git a/src/tools/clippy/tests/ui/bind_instead_of_map.rs b/src/tools/clippy/tests/ui/bind_instead_of_map.rs index 403077e72ff9..1308fa9f416b 100644 --- a/src/tools/clippy/tests/ui/bind_instead_of_map.rs +++ b/src/tools/clippy/tests/ui/bind_instead_of_map.rs @@ -1,4 +1,5 @@ #![deny(clippy::bind_instead_of_map)] +#![allow(clippy::manual_filter)] // need a main anyway, use it get rid of unused warnings too pub fn main() { diff --git a/src/tools/clippy/tests/ui/bind_instead_of_map.stderr b/src/tools/clippy/tests/ui/bind_instead_of_map.stderr index 3f8d631591e9..08f85fb58549 100644 --- a/src/tools/clippy/tests/ui/bind_instead_of_map.stderr +++ b/src/tools/clippy/tests/ui/bind_instead_of_map.stderr @@ -1,5 +1,5 @@ error: using `Option.and_then(Some)`, which is a no-op - --> tests/ui/bind_instead_of_map.rs:7:13 + --> tests/ui/bind_instead_of_map.rs:8:13 | LL | let _ = x.and_then(Some); | ^^^^^^^^^^^^^^^^ help: use the expression directly: `x` @@ -11,13 +11,13 @@ LL | #![deny(clippy::bind_instead_of_map)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ error: using `Option.and_then(|x| Some(y))`, which is more succinctly expressed as `map(|x| y)` - --> tests/ui/bind_instead_of_map.rs:9:13 + --> tests/ui/bind_instead_of_map.rs:10:13 | LL | let _ = x.and_then(|o| Some(o + 1)); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `x.map(|o| o + 1)` error: using `Result.and_then(Ok)`, which is a no-op - --> tests/ui/bind_instead_of_map.rs:16:13 + --> tests/ui/bind_instead_of_map.rs:17:13 | LL | let _ = x.and_then(Ok); | ^^^^^^^^^^^^^^ help: use the expression directly: `x` diff --git a/src/tools/clippy/tests/ui/bit_masks.rs b/src/tools/clippy/tests/ui/bit_masks.rs index 87dcdb3084d0..bca5b2ec34e1 100644 --- a/src/tools/clippy/tests/ui/bit_masks.rs +++ b/src/tools/clippy/tests/ui/bit_masks.rs @@ -89,3 +89,13 @@ fn ineffective() { x | 3 > 4; // not an error (yet), better written as x >= 4 x | 4 <= 19; } + +mod issue16781 { + fn unsigned(x: u8) -> bool { + x & 0xf0 == 0x11 << 4 + } + + fn signed(x: i8) -> bool { + x & 0x70 == 0x11 << 4 + } +} diff --git a/src/tools/clippy/tests/ui/blocks_in_conditions.stderr b/src/tools/clippy/tests/ui/blocks_in_conditions.stderr index 282c42a98bfc..975716deccee 100644 --- a/src/tools/clippy/tests/ui/blocks_in_conditions.stderr +++ b/src/tools/clippy/tests/ui/blocks_in_conditions.stderr @@ -29,10 +29,15 @@ error: this boolean expression can be simplified --> tests/ui/blocks_in_conditions.rs:48:8 | LL | if true && x == 3 { 6 } else { 10 } - | ^^^^^^^^^^^^^^ help: try: `x == 3` + | ^^^^^^^^^^^^^^ | = note: `-D clippy::nonminimal-bool` implied by `-D warnings` = help: to override `-D warnings` add `#[allow(clippy::nonminimal_bool)]` +help: try + | +LL - if true && x == 3 { 6 } else { 10 } +LL + if x == 3 { 6 } else { 10 } + | error: aborting due to 3 previous errors diff --git a/src/tools/clippy/tests/ui/byte_char_slices.fixed b/src/tools/clippy/tests/ui/byte_char_slices.fixed index 87934d6362f7..661ae8fc85fe 100644 --- a/src/tools/clippy/tests/ui/byte_char_slices.fixed +++ b/src/tools/clippy/tests/ui/byte_char_slices.fixed @@ -1,4 +1,5 @@ #![warn(clippy::byte_char_slices)] +#![allow(clippy::useless_vec)] fn main() { let bad = b"abc"; @@ -11,7 +12,40 @@ fn main() { //~^ byte_char_slices let good = &[b'a', 0x42]; - let good = [b'a', b'a']; - //~^ useless_vec - let good: u8 = [b'a', b'c'].into_iter().sum(); + let good = vec![b'a', b'a']; +} + +fn takes_array_ref(_: &[u8; 2]) {} + +fn takes_array_ref_ref(_: &&[u8; 2]) {} + +fn issue16759(bytes: [u32; 3]) { + const START: u32 = u32::from_le_bytes(*b"WORK"); + //~^ byte_char_slices + + let auto_deref_to_slice: u8 = b"ac".iter().copied().sum(); + //~^ byte_char_slices + + let with_comment = [ + // 1 2 3 + b'a', b'b', b'c', // x + b'd', b'e', b'f', // 2x + b'g', b'h', b'i', // 3x + ]; + let with_cfg = [ + b'a', + b'b', + b'c', + #[cfg(feature = "foo")] + b'd', + ]; + + let with_escape: u8 = b"'\"\x00\n\\".iter().copied().sum(); + //~^ byte_char_slices + + takes_array_ref(b"ab"); + //~^ byte_char_slices + + takes_array_ref_ref(&b"ab"); + //~^ byte_char_slices } diff --git a/src/tools/clippy/tests/ui/byte_char_slices.rs b/src/tools/clippy/tests/ui/byte_char_slices.rs index 0de7cf66fda8..e8dc9e9611de 100644 --- a/src/tools/clippy/tests/ui/byte_char_slices.rs +++ b/src/tools/clippy/tests/ui/byte_char_slices.rs @@ -1,4 +1,5 @@ #![warn(clippy::byte_char_slices)] +#![allow(clippy::useless_vec)] fn main() { let bad = &[b'a', b'b', b'c']; @@ -12,6 +13,39 @@ fn main() { let good = &[b'a', 0x42]; let good = vec![b'a', b'a']; - //~^ useless_vec - let good: u8 = [b'a', b'c'].into_iter().sum(); +} + +fn takes_array_ref(_: &[u8; 2]) {} + +fn takes_array_ref_ref(_: &&[u8; 2]) {} + +fn issue16759(bytes: [u32; 3]) { + const START: u32 = u32::from_le_bytes([b'W', b'O', b'R', b'K']); + //~^ byte_char_slices + + let auto_deref_to_slice: u8 = [b'a', b'c'].iter().copied().sum(); + //~^ byte_char_slices + + let with_comment = [ + // 1 2 3 + b'a', b'b', b'c', // x + b'd', b'e', b'f', // 2x + b'g', b'h', b'i', // 3x + ]; + let with_cfg = [ + b'a', + b'b', + b'c', + #[cfg(feature = "foo")] + b'd', + ]; + + let with_escape: u8 = [b'\'', b'"', b'\x00', b'\n', b'\\'].iter().copied().sum(); + //~^ byte_char_slices + + takes_array_ref(&[b'a', b'b']); + //~^ byte_char_slices + + takes_array_ref_ref(&&[b'a', b'b']); + //~^ byte_char_slices } diff --git a/src/tools/clippy/tests/ui/byte_char_slices.stderr b/src/tools/clippy/tests/ui/byte_char_slices.stderr index c1b7e4ca2f17..0f72cf13a0b6 100644 --- a/src/tools/clippy/tests/ui/byte_char_slices.stderr +++ b/src/tools/clippy/tests/ui/byte_char_slices.stderr @@ -1,5 +1,5 @@ error: can be more succinctly written as a byte str - --> tests/ui/byte_char_slices.rs:4:15 + --> tests/ui/byte_char_slices.rs:5:15 | LL | let bad = &[b'a', b'b', b'c']; | ^^^^^^^^^^^^^^^^^^^ help: try: `b"abc"` @@ -8,31 +8,52 @@ LL | let bad = &[b'a', b'b', b'c']; = help: to override `-D warnings` add `#[allow(clippy::byte_char_slices)]` error: can be more succinctly written as a byte str - --> tests/ui/byte_char_slices.rs:6:18 + --> tests/ui/byte_char_slices.rs:7:18 | LL | let quotes = &[b'"', b'H', b'i']; | ^^^^^^^^^^^^^^^^^^^ help: try: `b"\"Hi"` error: can be more succinctly written as a byte str - --> tests/ui/byte_char_slices.rs:8:18 + --> tests/ui/byte_char_slices.rs:9:18 | LL | let quotes = &[b'\'', b'S', b'u', b'p']; | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `b"'Sup"` error: can be more succinctly written as a byte str - --> tests/ui/byte_char_slices.rs:10:19 + --> tests/ui/byte_char_slices.rs:11:19 | LL | let escapes = &[b'\x42', b'E', b's', b'c']; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `b"\x42Esc"` -error: useless use of `vec!` - --> tests/ui/byte_char_slices.rs:14:16 +error: can be more succinctly written as a byte str + --> tests/ui/byte_char_slices.rs:23:43 | -LL | let good = vec![b'a', b'a']; - | ^^^^^^^^^^^^^^^^ help: you can use an array directly: `[b'a', b'a']` +LL | const START: u32 = u32::from_le_bytes([b'W', b'O', b'R', b'K']); + | ^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `*b"WORK"` + +error: can be more succinctly written as a byte str + --> tests/ui/byte_char_slices.rs:26:35 | - = note: `-D clippy::useless-vec` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(clippy::useless_vec)]` +LL | let auto_deref_to_slice: u8 = [b'a', b'c'].iter().copied().sum(); + | ^^^^^^^^^^^^ help: try: `b"ac"` -error: aborting due to 5 previous errors +error: can be more succinctly written as a byte str + --> tests/ui/byte_char_slices.rs:43:27 + | +LL | let with_escape: u8 = [b'\'', b'"', b'\x00', b'\n', b'\\'].iter().copied().sum(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `b"'\"\x00\n\\"` + +error: can be more succinctly written as a byte str + --> tests/ui/byte_char_slices.rs:46:21 + | +LL | takes_array_ref(&[b'a', b'b']); + | ^^^^^^^^^^^^^ help: try: `b"ab"` + +error: can be more succinctly written as a byte str + --> tests/ui/byte_char_slices.rs:49:26 + | +LL | takes_array_ref_ref(&&[b'a', b'b']); + | ^^^^^^^^^^^^^ help: try: `b"ab"` + +error: aborting due to 9 previous errors diff --git a/src/tools/clippy/tests/ui/crashes/ice-96721.stderr b/src/tools/clippy/tests/ui/crashes/ice-96721.stderr index 23f7300178ec..70f3d48379fd 100644 --- a/src/tools/clippy/tests/ui/crashes/ice-96721.stderr +++ b/src/tools/clippy/tests/ui/crashes/ice-96721.stderr @@ -2,9 +2,14 @@ error: malformed `path` attribute input --> tests/ui/crashes/ice-96721.rs:7:1 | LL | #[path = foo!()] - | ^^^^^^^^^^^^^^^^ help: must be of the form: `#[path = "file"]` + | ^^^^^^^^^^^^^^^^ | = note: for more information, visit +help: must be of the form + | +LL - #[path = foo!()] +LL + #[path = "file"] + | error: aborting due to 1 previous error diff --git a/src/tools/clippy/tests/ui/expect_fun_call.fixed b/src/tools/clippy/tests/ui/expect_fun_call.fixed index b923521afde1..cc407adc75ad 100644 --- a/src/tools/clippy/tests/ui/expect_fun_call.fixed +++ b/src/tools/clippy/tests/ui/expect_fun_call.fixed @@ -147,3 +147,13 @@ fn main() { return; }); } + +fn issue16747() { + let x = 42; + let _c = char::from_u32(x).unwrap_or_else(|| panic!("{}", &format!("Illegal: {x}")[..])); + //~^ expect_fun_call + + let s = "hello"; + let _c = char::from_u32(x).unwrap_or_else(|| panic!("{}", &s.to_lowercase()[..2])); + //~^ expect_fun_call +} diff --git a/src/tools/clippy/tests/ui/expect_fun_call.rs b/src/tools/clippy/tests/ui/expect_fun_call.rs index bc58d24bc812..ab3b43686552 100644 --- a/src/tools/clippy/tests/ui/expect_fun_call.rs +++ b/src/tools/clippy/tests/ui/expect_fun_call.rs @@ -147,3 +147,13 @@ const fn const_evaluable() -> &'static str { return; }); } + +fn issue16747() { + let x = 42; + let _c = char::from_u32(x).expect(&format!("Illegal: {x}")[..]); + //~^ expect_fun_call + + let s = "hello"; + let _c = char::from_u32(x).expect(&s.to_lowercase()[..2]); + //~^ expect_fun_call +} diff --git a/src/tools/clippy/tests/ui/expect_fun_call.stderr b/src/tools/clippy/tests/ui/expect_fun_call.stderr index 0692ecb4862e..4ef114ac406b 100644 --- a/src/tools/clippy/tests/ui/expect_fun_call.stderr +++ b/src/tools/clippy/tests/ui/expect_fun_call.stderr @@ -97,5 +97,17 @@ error: function call inside of `expect` LL | format_capture_and_value.expect(&format!("{error_code}, {}", 1)); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `unwrap_or_else(|| panic!("{error_code}, {}", 1))` -error: aborting due to 16 previous errors +error: function call inside of `expect` + --> tests/ui/expect_fun_call.rs:153:32 + | +LL | let _c = char::from_u32(x).expect(&format!("Illegal: {x}")[..]); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `unwrap_or_else(|| panic!("{}", &format!("Illegal: {x}")[..]))` + +error: function call inside of `expect` + --> tests/ui/expect_fun_call.rs:157:32 + | +LL | let _c = char::from_u32(x).expect(&s.to_lowercase()[..2]); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `unwrap_or_else(|| panic!("{}", &s.to_lowercase()[..2]))` + +error: aborting due to 18 previous errors diff --git a/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.rs b/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.rs index 68271048fcb9..82ac4db172d8 100644 --- a/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.rs +++ b/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.rs @@ -36,6 +36,8 @@ pub fn rustc_lints() { #[expect(invalid_nan_comparisons)] //~^ ERROR: this lint expectation is unfulfilled + //~| NOTE: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + //~| ERROR: this lint expectation is unfulfilled let _b = x == 5; } } diff --git a/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.stderr b/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.stderr index aa187f351f45..b274d5c23693 100644 --- a/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.stderr +++ b/src/tools/clippy/tests/ui/expect_tool_lint_rfc_2383.stderr @@ -14,28 +14,36 @@ LL | #[expect(invalid_nan_comparisons)] | ^^^^^^^^^^^^^^^^^^^^^^^ error: this lint expectation is unfulfilled - --> tests/ui/expect_tool_lint_rfc_2383.rs:108:14 + --> tests/ui/expect_tool_lint_rfc_2383.rs:37:18 + | +LL | #[expect(invalid_nan_comparisons)] + | ^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: this lint expectation is unfulfilled + --> tests/ui/expect_tool_lint_rfc_2383.rs:110:14 | LL | #[expect(clippy::almost_swapped)] | ^^^^^^^^^^^^^^^^^^^^^^ error: this lint expectation is unfulfilled - --> tests/ui/expect_tool_lint_rfc_2383.rs:116:14 + --> tests/ui/expect_tool_lint_rfc_2383.rs:118:14 | LL | #[expect(clippy::bytes_nth)] | ^^^^^^^^^^^^^^^^^ error: this lint expectation is unfulfilled - --> tests/ui/expect_tool_lint_rfc_2383.rs:122:14 + --> tests/ui/expect_tool_lint_rfc_2383.rs:124:14 | LL | #[expect(clippy::if_same_then_else)] | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: this lint expectation is unfulfilled - --> tests/ui/expect_tool_lint_rfc_2383.rs:128:14 + --> tests/ui/expect_tool_lint_rfc_2383.rs:130:14 | LL | #[expect(clippy::overly_complex_bool_expr)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -error: aborting due to 6 previous errors +error: aborting due to 7 previous errors diff --git a/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.rs b/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.rs index 83c1e9a8387e..2884dcb367f0 100644 --- a/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.rs +++ b/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.rs @@ -82,7 +82,7 @@ fn closure_to_fn_to_integer() { fn fn_to_raw_ptr() { let _ = foo as *const (); - //~^ fn_to_numeric_cast_any + let _ = foo as *mut (); } fn cast_fn_to_self() { diff --git a/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.stderr b/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.stderr index f7c49b8ff88b..251c55395bd1 100644 --- a/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.stderr +++ b/src/tools/clippy/tests/ui/fn_to_numeric_cast_any.stderr @@ -176,16 +176,5 @@ help: did you mean to invoke the function? LL | let _ = (clos as fn(u32) -> u32)() as usize; | ++ -error: casting function pointer `foo` to `*const ()` - --> tests/ui/fn_to_numeric_cast_any.rs:84:13 - | -LL | let _ = foo as *const (); - | ^^^^^^^^^^^^^^^^ - | -help: did you mean to invoke the function? - | -LL | let _ = foo() as *const (); - | ++ - -error: aborting due to 17 previous errors +error: aborting due to 16 previous errors diff --git a/src/tools/clippy/tests/ui/if_then_some_else_none.fixed b/src/tools/clippy/tests/ui/if_then_some_else_none.fixed index ce122ac69b12..6bf636bb2b0b 100644 --- a/src/tools/clippy/tests/ui/if_then_some_else_none.fixed +++ b/src/tools/clippy/tests/ui/if_then_some_else_none.fixed @@ -1,5 +1,9 @@ #![warn(clippy::if_then_some_else_none)] -#![allow(clippy::redundant_pattern_matching, clippy::unnecessary_lazy_evaluations)] +#![allow( + clippy::redundant_pattern_matching, + clippy::unnecessary_lazy_evaluations, + clippy::manual_filter +)] fn main() { // Should issue an error. diff --git a/src/tools/clippy/tests/ui/if_then_some_else_none.rs b/src/tools/clippy/tests/ui/if_then_some_else_none.rs index 1d6c86d94492..2cb14ea4d1bc 100644 --- a/src/tools/clippy/tests/ui/if_then_some_else_none.rs +++ b/src/tools/clippy/tests/ui/if_then_some_else_none.rs @@ -1,5 +1,9 @@ #![warn(clippy::if_then_some_else_none)] -#![allow(clippy::redundant_pattern_matching, clippy::unnecessary_lazy_evaluations)] +#![allow( + clippy::redundant_pattern_matching, + clippy::unnecessary_lazy_evaluations, + clippy::manual_filter +)] fn main() { // Should issue an error. diff --git a/src/tools/clippy/tests/ui/if_then_some_else_none.stderr b/src/tools/clippy/tests/ui/if_then_some_else_none.stderr index eff5f8c82dcb..112f8221b59d 100644 --- a/src/tools/clippy/tests/ui/if_then_some_else_none.stderr +++ b/src/tools/clippy/tests/ui/if_then_some_else_none.stderr @@ -1,5 +1,5 @@ error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:6:13 + --> tests/ui/if_then_some_else_none.rs:10:13 | LL | let _ = if foo() { | _____________^ @@ -24,7 +24,7 @@ LL ~ }); | error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:16:13 + --> tests/ui/if_then_some_else_none.rs:20:13 | LL | let _ = if matches!(true, true) { | _____________^ @@ -47,19 +47,19 @@ LL ~ }); | error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:27:28 + --> tests/ui/if_then_some_else_none.rs:31:28 | LL | let _ = x.and_then(|o| if o < 32 { Some(o) } else { None }); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `(o < 32).then_some(o)` error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:32:13 + --> tests/ui/if_then_some_else_none.rs:36:13 | LL | let _ = if !x { Some(0) } else { None }; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `(!x).then_some(0)` error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:88:13 + --> tests/ui/if_then_some_else_none.rs:92:13 | LL | let _ = if foo() { | _____________^ @@ -82,13 +82,13 @@ LL ~ }); | error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:138:5 + --> tests/ui/if_then_some_else_none.rs:142:5 | LL | if s == "1" { Some(true) } else { None } | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `(s == "1").then(|| true)` error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:154:9 + --> tests/ui/if_then_some_else_none.rs:158:9 | LL | / if rs.len() == 1 && rs[0].start == rs[0].end { LL | | @@ -99,7 +99,7 @@ LL | | } | |_________^ help: try: `(rs.len() == 1 && rs[0].start == rs[0].end).then(|| vec![rs[0].start])` error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:164:9 + --> tests/ui/if_then_some_else_none.rs:168:9 | LL | / if modulo == 0 { LL | | @@ -110,7 +110,7 @@ LL | | } | |_________^ help: try: `(modulo == 0).then_some(i)` error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:181:22 + --> tests/ui/if_then_some_else_none.rs:185:22 | LL | do_something(if i % 2 == 0 { | ______________________^ @@ -122,7 +122,7 @@ LL | | }); | |_________^ help: try: `(i % 2 == 0).then_some(item_fn)` error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:198:22 + --> tests/ui/if_then_some_else_none.rs:202:22 | LL | do_something(if i % 2 == 0 { | ______________________^ @@ -134,7 +134,7 @@ LL | | }); | |_________^ help: try: `(i % 2 == 0).then_some(item_fn)` error: this could be simplified with `bool::then_some` - --> tests/ui/if_then_some_else_none.rs:206:22 + --> tests/ui/if_then_some_else_none.rs:210:22 | LL | do_something(if i % 2 == 0 { | ______________________^ @@ -146,7 +146,7 @@ LL | | }); | |_________^ help: try: `(i % 2 == 0).then_some(closure_fn)` error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:231:13 + --> tests/ui/if_then_some_else_none.rs:235:13 | LL | / if self.count < 5 { LL | | self.count += 1; @@ -165,7 +165,7 @@ LL + }) | error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:249:13 + --> tests/ui/if_then_some_else_none.rs:253:13 | LL | let _ = if true { | _____________^ @@ -185,7 +185,7 @@ LL ~ }); | error: this could be simplified with `bool::then` - --> tests/ui/if_then_some_else_none.rs:292:5 + --> tests/ui/if_then_some_else_none.rs:296:5 | LL | / if 1 <= 3 { LL | | let a = UnsafeCell::new(1); diff --git a/src/tools/clippy/tests/ui/implicit_saturating_sub.fixed b/src/tools/clippy/tests/ui/implicit_saturating_sub.fixed index 22e59bbd2705..85f67bb2381e 100644 --- a/src/tools/clippy/tests/ui/implicit_saturating_sub.fixed +++ b/src/tools/clippy/tests/ui/implicit_saturating_sub.fixed @@ -260,3 +260,21 @@ fn issue16307() { println!("{y}"); } + +fn wrongly_unmangled_macros() { + macro_rules! test_big { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + macro_rules! test_little { + ($val:expr) => { + ($val * 2 + 0) + }; + } + + let a = 15u64; + let b = 20u64; + let _ = test_big!(a).saturating_sub(test_little!(b)); +} diff --git a/src/tools/clippy/tests/ui/implicit_saturating_sub.rs b/src/tools/clippy/tests/ui/implicit_saturating_sub.rs index 7fa19f0c8ad2..81f19b3000f7 100644 --- a/src/tools/clippy/tests/ui/implicit_saturating_sub.rs +++ b/src/tools/clippy/tests/ui/implicit_saturating_sub.rs @@ -334,3 +334,26 @@ fn issue16307() { println!("{y}"); } + +fn wrongly_unmangled_macros() { + macro_rules! test_big { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + macro_rules! test_little { + ($val:expr) => { + ($val * 2 + 0) + }; + } + + let a = 15u64; + let b = 20u64; + let _ = if test_big!(a) > test_little!(b) { + //~^ implicit_saturating_sub + test_big!(a) - test_little!(b) + } else { + 0 + }; +} diff --git a/src/tools/clippy/tests/ui/implicit_saturating_sub.stderr b/src/tools/clippy/tests/ui/implicit_saturating_sub.stderr index 2f3d2ba787e8..c7a4330603a2 100644 --- a/src/tools/clippy/tests/ui/implicit_saturating_sub.stderr +++ b/src/tools/clippy/tests/ui/implicit_saturating_sub.stderr @@ -244,5 +244,17 @@ error: manual arithmetic check found LL | let y = if x >= 100 { 0 } else { 100 - x }; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: replace it with: `100_u8.saturating_sub(x)` -error: aborting due to 28 previous errors +error: manual arithmetic check found + --> tests/ui/implicit_saturating_sub.rs:353:13 + | +LL | let _ = if test_big!(a) > test_little!(b) { + | _____________^ +LL | | +LL | | test_big!(a) - test_little!(b) +LL | | } else { +LL | | 0 +LL | | }; + | |_____^ help: replace it with: `test_big!(a).saturating_sub(test_little!(b))` + +error: aborting due to 29 previous errors diff --git a/src/tools/clippy/tests/ui/int_plus_one.fixed b/src/tools/clippy/tests/ui/int_plus_one.fixed index cdd19515e9a7..02087a0720e7 100644 --- a/src/tools/clippy/tests/ui/int_plus_one.fixed +++ b/src/tools/clippy/tests/ui/int_plus_one.fixed @@ -16,4 +16,18 @@ fn main() { let _ = x > y; // should be ok let _ = y < x; // should be ok + + // When the suggestion replaces `<=`/`>=` with `<`, an `as` cast on + // the LHS must be parenthesized to avoid parser ambiguity + // (e.g., `x as usize < y` is parsed as `x as usize`). + let z = 0usize; + let _ = (x as usize) < z; //~ int_plus_one + let _ = z > x as usize; //~ int_plus_one + // No parentheses needed when the replacement operator is `>`. + let _ = x as usize > z; //~ int_plus_one + let _ = z < x as usize; //~ int_plus_one + + // Nested and parenthesized casts on the LHS. + let _ = ((x as usize) as u8) < 5u8; //~ int_plus_one + let _ = (x as usize) < z; //~ int_plus_one } diff --git a/src/tools/clippy/tests/ui/int_plus_one.rs b/src/tools/clippy/tests/ui/int_plus_one.rs index 8d7d2e8982d8..235175e63ee0 100644 --- a/src/tools/clippy/tests/ui/int_plus_one.rs +++ b/src/tools/clippy/tests/ui/int_plus_one.rs @@ -16,4 +16,18 @@ fn main() { let _ = x > y; // should be ok let _ = y < x; // should be ok + + // When the suggestion replaces `<=`/`>=` with `<`, an `as` cast on + // the LHS must be parenthesized to avoid parser ambiguity + // (e.g., `x as usize < y` is parsed as `x as usize`). + let z = 0usize; + let _ = x as usize + 1 <= z; //~ int_plus_one + let _ = z >= x as usize + 1; //~ int_plus_one + // No parentheses needed when the replacement operator is `>`. + let _ = x as usize - 1 >= z; //~ int_plus_one + let _ = z <= x as usize - 1; //~ int_plus_one + + // Nested and parenthesized casts on the LHS. + let _ = ((x as usize) as u8) + 1 <= 5u8; //~ int_plus_one + let _ = (x as usize) + 1 <= z; //~ int_plus_one } diff --git a/src/tools/clippy/tests/ui/int_plus_one.stderr b/src/tools/clippy/tests/ui/int_plus_one.stderr index 8bdff5680bdc..4081b7a76367 100644 --- a/src/tools/clippy/tests/ui/int_plus_one.stderr +++ b/src/tools/clippy/tests/ui/int_plus_one.stderr @@ -49,5 +49,41 @@ error: unnecessary `>= y + 1` or `x - 1 >=` LL | let _ = y <= -1 + x; | ^^^^^^^^^^^ help: change it to: `y < x` -error: aborting due to 8 previous errors +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:24:13 + | +LL | let _ = x as usize + 1 <= z; + | ^^^^^^^^^^^^^^^^^^^ help: change it to: `(x as usize) < z` + +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:25:13 + | +LL | let _ = z >= x as usize + 1; + | ^^^^^^^^^^^^^^^^^^^ help: change it to: `z > x as usize` + +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:27:13 + | +LL | let _ = x as usize - 1 >= z; + | ^^^^^^^^^^^^^^^^^^^ help: change it to: `x as usize > z` + +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:28:13 + | +LL | let _ = z <= x as usize - 1; + | ^^^^^^^^^^^^^^^^^^^ help: change it to: `z < x as usize` + +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:31:13 + | +LL | let _ = ((x as usize) as u8) + 1 <= 5u8; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: change it to: `((x as usize) as u8) < 5u8` + +error: unnecessary `>= y + 1` or `x - 1 >=` + --> tests/ui/int_plus_one.rs:32:13 + | +LL | let _ = (x as usize) + 1 <= z; + | ^^^^^^^^^^^^^^^^^^^^^ help: change it to: `(x as usize) < z` + +error: aborting due to 14 previous errors diff --git a/src/tools/clippy/tests/ui/let_and_return.edition2021.fixed b/src/tools/clippy/tests/ui/let_and_return.edition2021.fixed index 6ca0febc2b8d..1c814f54c939 100644 --- a/src/tools/clippy/tests/ui/let_and_return.edition2021.fixed +++ b/src/tools/clippy/tests/ui/let_and_return.edition2021.fixed @@ -279,4 +279,27 @@ fn has_comment() -> Vec { v } +fn wrongly_unmangled_macros() -> i32 { + let x = 1; + macro_rules! plus_one { + ($e:expr) => { + $e + 1 + }; + } + + + plus_one!(x) + //~^ let_and_return +} + +fn issue16820() -> Option { + let value = Some(42); + + let v @ None = value else { + panic!("uh oh!"); + }; + + v +} + fn main() {} diff --git a/src/tools/clippy/tests/ui/let_and_return.edition2021.stderr b/src/tools/clippy/tests/ui/let_and_return.edition2021.stderr index f9536d1b5477..2203dc3377b5 100644 --- a/src/tools/clippy/tests/ui/let_and_return.edition2021.stderr +++ b/src/tools/clippy/tests/ui/let_and_return.edition2021.stderr @@ -148,5 +148,19 @@ LL ~ LL ~ ({ true } || { false } && { 2 <= 3 }) | -error: aborting due to 10 previous errors +error: returning the result of a `let` binding from a block + --> tests/ui/let_and_return.rs:291:5 + | +LL | let y = plus_one!(x); + | --------------------- unnecessary `let` binding +LL | y + | ^ + | +help: return the expression directly + | +LL ~ +LL ~ plus_one!(x) + | + +error: aborting due to 11 previous errors diff --git a/src/tools/clippy/tests/ui/let_and_return.edition2024.fixed b/src/tools/clippy/tests/ui/let_and_return.edition2024.fixed index 0fce22936ae6..b0c5a8359b7a 100644 --- a/src/tools/clippy/tests/ui/let_and_return.edition2024.fixed +++ b/src/tools/clippy/tests/ui/let_and_return.edition2024.fixed @@ -279,4 +279,27 @@ fn has_comment() -> Vec { v } +fn wrongly_unmangled_macros() -> i32 { + let x = 1; + macro_rules! plus_one { + ($e:expr) => { + $e + 1 + }; + } + + + plus_one!(x) + //~^ let_and_return +} + +fn issue16820() -> Option { + let value = Some(42); + + let v @ None = value else { + panic!("uh oh!"); + }; + + v +} + fn main() {} diff --git a/src/tools/clippy/tests/ui/let_and_return.edition2024.stderr b/src/tools/clippy/tests/ui/let_and_return.edition2024.stderr index ca378fa43232..6ea8b9dafc9e 100644 --- a/src/tools/clippy/tests/ui/let_and_return.edition2024.stderr +++ b/src/tools/clippy/tests/ui/let_and_return.edition2024.stderr @@ -224,5 +224,19 @@ LL + None => Ok(Ok(0)), LL + }? | -error: aborting due to 15 previous errors +error: returning the result of a `let` binding from a block + --> tests/ui/let_and_return.rs:291:5 + | +LL | let y = plus_one!(x); + | --------------------- unnecessary `let` binding +LL | y + | ^ + | +help: return the expression directly + | +LL ~ +LL ~ plus_one!(x) + | + +error: aborting due to 16 previous errors diff --git a/src/tools/clippy/tests/ui/let_and_return.rs b/src/tools/clippy/tests/ui/let_and_return.rs index 301f153ca8b1..57660f7e031a 100644 --- a/src/tools/clippy/tests/ui/let_and_return.rs +++ b/src/tools/clippy/tests/ui/let_and_return.rs @@ -279,4 +279,27 @@ fn has_comment() -> Vec { v } +fn wrongly_unmangled_macros() -> i32 { + let x = 1; + macro_rules! plus_one { + ($e:expr) => { + $e + 1 + }; + } + + let y = plus_one!(x); + y + //~^ let_and_return +} + +fn issue16820() -> Option { + let value = Some(42); + + let v @ None = value else { + panic!("uh oh!"); + }; + + v +} + fn main() {} diff --git a/src/tools/clippy/tests/ui/manual_div_ceil.fixed b/src/tools/clippy/tests/ui/manual_div_ceil.fixed index 8ffd107dd42e..db46f6720891 100644 --- a/src/tools/clippy/tests/ui/manual_div_ceil.fixed +++ b/src/tools/clippy/tests/ui/manual_div_ceil.fixed @@ -16,6 +16,12 @@ macro_rules! eight { }; } +macro_rules! plus_one { + ($val:expr) => { + ($val + 1) + }; +} + fn main() { let x = 7_u32; let y = 4_u32; @@ -55,6 +61,9 @@ fn main() { // Also test if RHS should be result of macro expansion let _ = 33u32.div_ceil(eight!()); //~^ manual_div_ceil + + let _ = plus_one!(x).div_ceil(y); + //~^ manual_div_ceil } fn issue_13843() { diff --git a/src/tools/clippy/tests/ui/manual_div_ceil.rs b/src/tools/clippy/tests/ui/manual_div_ceil.rs index 859fb5a13c44..d60ecaa2af7a 100644 --- a/src/tools/clippy/tests/ui/manual_div_ceil.rs +++ b/src/tools/clippy/tests/ui/manual_div_ceil.rs @@ -16,6 +16,12 @@ macro_rules! eight { }; } +macro_rules! plus_one { + ($val:expr) => { + ($val + 1) + }; +} + fn main() { let x = 7_u32; let y = 4_u32; @@ -55,6 +61,9 @@ fn main() { // Also test if RHS should be result of macro expansion let _ = (33u32 + 7) / eight!(); //~^ manual_div_ceil + + let _ = (plus_one!(x) + (y - 1)) / y; + //~^ manual_div_ceil } fn issue_13843() { diff --git a/src/tools/clippy/tests/ui/manual_div_ceil.stderr b/src/tools/clippy/tests/ui/manual_div_ceil.stderr index 0efc114c7078..1ebcbc04eeb9 100644 --- a/src/tools/clippy/tests/ui/manual_div_ceil.stderr +++ b/src/tools/clippy/tests/ui/manual_div_ceil.stderr @@ -1,5 +1,5 @@ error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:25:13 + --> tests/ui/manual_div_ceil.rs:31:13 | LL | let _ = (x + (y - 1)) / y; | ^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(y)` @@ -8,25 +8,25 @@ LL | let _ = (x + (y - 1)) / y; = help: to override `-D warnings` add `#[allow(clippy::manual_div_ceil)]` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:27:13 + --> tests/ui/manual_div_ceil.rs:33:13 | LL | let _ = ((y - 1) + x) / y; | ^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(y)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:29:13 + --> tests/ui/manual_div_ceil.rs:35:13 | LL | let _ = (x + y - 1) / y; | ^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(y)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:32:13 + --> tests/ui/manual_div_ceil.rs:38:13 | LL | let _ = (7_u32 + (4 - 1)) / 4; | ^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `7_u32.div_ceil(4)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:34:13 + --> tests/ui/manual_div_ceil.rs:40:13 | LL | let _ = (7_i32 as u32 + (4 - 1)) / 4; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `(7_i32 as u32).div_ceil(4)` @@ -54,100 +54,106 @@ LL | y!(); = note: this error originates in the macro `y` (in Nightly builds, run with -Z macro-backtrace for more info) error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:56:13 + --> tests/ui/manual_div_ceil.rs:62:13 | LL | let _ = (33u32 + 7) / eight!(); | ^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `33u32.div_ceil(eight!())` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:62:13 + --> tests/ui/manual_div_ceil.rs:65:13 + | +LL | let _ = (plus_one!(x) + (y - 1)) / y; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `plus_one!(x).div_ceil(y)` + +error: manually reimplementing `div_ceil` + --> tests/ui/manual_div_ceil.rs:71:13 | LL | let _ = (2048 + x - 1) / x; | ^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048_usize.div_ceil(x)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:66:13 + --> tests/ui/manual_div_ceil.rs:75:13 | LL | let _ = (2048usize + x - 1) / x; | ^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048usize.div_ceil(x)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:70:13 + --> tests/ui/manual_div_ceil.rs:79:13 | LL | let _ = (2048_usize + x - 1) / x; | ^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048_usize.div_ceil(x)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:74:13 + --> tests/ui/manual_div_ceil.rs:83:13 | LL | let _ = (x + 4 - 1) / 4; | ^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(4)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:77:18 + --> tests/ui/manual_div_ceil.rs:86:18 | LL | let _: u32 = (2048 + 6 - 1) / 6; | ^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048_u32.div_ceil(6)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:79:20 + --> tests/ui/manual_div_ceil.rs:88:20 | LL | let _: usize = (2048 + 6 - 1) / 6; | ^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048_usize.div_ceil(6)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:81:18 + --> tests/ui/manual_div_ceil.rs:90:18 | LL | let _: u32 = (0x2048 + 0x6 - 1) / 0x6; | ^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `0x2048_u32.div_ceil(0x6)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:84:13 + --> tests/ui/manual_div_ceil.rs:93:13 | LL | let _ = (2048 + 6u32 - 1) / 6u32; | ^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `2048_u32.div_ceil(6u32)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:87:13 + --> tests/ui/manual_div_ceil.rs:96:13 | LL | let _ = (1_000_000 + 6u32 - 1) / 6u32; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `1_000_000_u32.div_ceil(6u32)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:93:13 + --> tests/ui/manual_div_ceil.rs:102:13 | LL | let _ = (x + 7) / 8; | ^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(8)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:95:13 + --> tests/ui/manual_div_ceil.rs:104:13 | LL | let _ = (7 + x) / 8; | ^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(8)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:105:13 + --> tests/ui/manual_div_ceil.rs:114:13 | LL | let _ = (size + c - 1) / c; | ^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `size.div_ceil(*c)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:121:13 + --> tests/ui/manual_div_ceil.rs:130:13 | LL | let _ = x.next_multiple_of(8) / 8; | ^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(8)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:123:13 + --> tests/ui/manual_div_ceil.rs:132:13 | LL | let _ = u32::next_multiple_of(x, 8) / 8; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `x.div_ceil(8)` error: manually reimplementing `div_ceil` - --> tests/ui/manual_div_ceil.rs:127:13 + --> tests/ui/manual_div_ceil.rs:136:13 | LL | let _ = y.next_multiple_of(8) / 8; | ^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.div_ceil()`: `y.div_ceil(8)` -error: aborting due to 23 previous errors +error: aborting due to 24 previous errors diff --git a/src/tools/clippy/tests/ui/manual_filter.fixed b/src/tools/clippy/tests/ui/manual_filter.fixed index a0fb0e32d601..3e2cebee40fe 100644 --- a/src/tools/clippy/tests/ui/manual_filter.fixed +++ b/src/tools/clippy/tests/ui/manual_filter.fixed @@ -1,5 +1,10 @@ #![warn(clippy::manual_filter)] -#![allow(unused_variables, dead_code, clippy::useless_vec)] +#![allow( + unused_variables, + clippy::question_mark, + clippy::useless_vec, + clippy::nonminimal_bool +)] fn main() { Some(0).filter(|&x| x <= 0); @@ -156,3 +161,24 @@ fn main() { fn maybe_some() -> Option { Some(0) } + +fn issue14440(opt: Option) { + opt.filter(|&x| x != 0); + //~^ manual_filter + + let y = 1i32; + opt.filter(move |&x| x == y); + //~^ manual_filter + + let opt1 = Some("123".to_string()); + opt1.filter(|s| s.len() > 2); + //~^ manual_filter + + unsafe fn f(x: u32) -> bool { + true + } + opt.filter(|&x| unsafe { f(x as u32) }); + //~^ manual_filter + opt.filter(|&x| unsafe { f(x as u32) }); + //~^ manual_filter +} diff --git a/src/tools/clippy/tests/ui/manual_filter.rs b/src/tools/clippy/tests/ui/manual_filter.rs index a9d0c35f8bb7..2b80cb450e05 100644 --- a/src/tools/clippy/tests/ui/manual_filter.rs +++ b/src/tools/clippy/tests/ui/manual_filter.rs @@ -1,5 +1,10 @@ #![warn(clippy::manual_filter)] -#![allow(unused_variables, dead_code, clippy::useless_vec)] +#![allow( + unused_variables, + clippy::question_mark, + clippy::useless_vec, + clippy::nonminimal_bool +)] fn main() { match Some(0) { @@ -293,3 +298,24 @@ struct NamedTuple { fn maybe_some() -> Option { Some(0) } + +fn issue14440(opt: Option) { + opt.and_then(|x| if x == 0 { None } else { Some(x) }); + //~^ manual_filter + + let y = 1i32; + opt.and_then(move |x| if x == y { Some(x) } else { None }); + //~^ manual_filter + + let opt1 = Some("123".to_string()); + opt1.and_then(|s| if s.len() > 2 { Some(s) } else { None }); + //~^ manual_filter + + unsafe fn f(x: u32) -> bool { + true + } + opt.and_then(|x| if unsafe { f(x as u32) } { Some(x) } else { None }); + //~^ manual_filter + opt.and_then(|x| unsafe { if f(x as u32) { Some(x) } else { None } }); + //~^ manual_filter +} diff --git a/src/tools/clippy/tests/ui/manual_filter.stderr b/src/tools/clippy/tests/ui/manual_filter.stderr index 63463997f435..c5fdf14a9b43 100644 --- a/src/tools/clippy/tests/ui/manual_filter.stderr +++ b/src/tools/clippy/tests/ui/manual_filter.stderr @@ -1,5 +1,5 @@ error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:5:5 + --> tests/ui/manual_filter.rs:10:5 | LL | / match Some(0) { LL | | @@ -14,7 +14,7 @@ LL | | }; = help: to override `-D warnings` add `#[allow(clippy::manual_filter)]` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:17:5 + --> tests/ui/manual_filter.rs:22:5 | LL | / match Some(1) { LL | | @@ -26,7 +26,7 @@ LL | | }; | |_____^ help: try: `Some(1).filter(|&x| x <= 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:29:5 + --> tests/ui/manual_filter.rs:34:5 | LL | / match Some(2) { LL | | @@ -38,7 +38,7 @@ LL | | }; | |_____^ help: try: `Some(2).filter(|&x| x <= 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:41:5 + --> tests/ui/manual_filter.rs:46:5 | LL | / match Some(3) { LL | | @@ -50,7 +50,7 @@ LL | | }; | |_____^ help: try: `Some(3).filter(|&x| x > 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:54:5 + --> tests/ui/manual_filter.rs:59:5 | LL | / match y { LL | | @@ -62,7 +62,7 @@ LL | | }; | |_____^ help: try: `y.filter(|&x| x <= 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:67:5 + --> tests/ui/manual_filter.rs:72:5 | LL | / match Some(5) { LL | | @@ -74,7 +74,7 @@ LL | | }; | |_____^ help: try: `Some(5).filter(|&x| x > 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:79:5 + --> tests/ui/manual_filter.rs:84:5 | LL | / match Some(6) { LL | | @@ -86,7 +86,7 @@ LL | | }; | |_____^ help: try: `Some(6).as_ref().filter(|&x| x > &0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:92:5 + --> tests/ui/manual_filter.rs:97:5 | LL | / match Some(String::new()) { LL | | @@ -98,7 +98,7 @@ LL | | }; | |_____^ help: try: `Some(String::new()).filter(|x| external_cond)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:104:5 + --> tests/ui/manual_filter.rs:109:5 | LL | / if let Some(x) = Some(7) { LL | | @@ -109,7 +109,7 @@ LL | | }; | |_____^ help: try: `Some(7).filter(|&x| external_cond)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:111:5 + --> tests/ui/manual_filter.rs:116:5 | LL | / match &Some(8) { LL | | @@ -121,7 +121,7 @@ LL | | }; | |_____^ help: try: `Some(8).filter(|&x| x != 0)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:123:5 + --> tests/ui/manual_filter.rs:128:5 | LL | / match Some(9) { LL | | @@ -133,7 +133,7 @@ LL | | }; | |_____^ help: try: `Some(9).filter(|&x| x > 10 && x < 100)` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:150:5 + --> tests/ui/manual_filter.rs:155:5 | LL | / match Some(11) { LL | | @@ -153,7 +153,7 @@ LL ~ }); | error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:195:13 + --> tests/ui/manual_filter.rs:200:13 | LL | let _ = match Some(14) { | _____________^ @@ -166,7 +166,7 @@ LL | | }; | |_____^ help: try: `Some(14).filter(|&x| unsafe { f(x) })` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:206:13 + --> tests/ui/manual_filter.rs:211:13 | LL | let _ = match Some(15) { | _____________^ @@ -177,7 +177,7 @@ LL | | }; | |_____^ help: try: `Some(15).filter(|&x| unsafe { f(x) })` error: manual implementation of `Option::filter` - --> tests/ui/manual_filter.rs:215:12 + --> tests/ui/manual_filter.rs:220:12 | LL | } else if let Some(x) = Some(16) { | ____________^ @@ -189,5 +189,35 @@ LL | | None LL | | }; | |_____^ help: try: `{ Some(16).filter(|&x| x % 2 == 0) }` -error: aborting due to 15 previous errors +error: manual implementation of `Option::filter` + --> tests/ui/manual_filter.rs:303:9 + | +LL | opt.and_then(|x| if x == 0 { None } else { Some(x) }); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `filter(|&x| x != 0)` + +error: manual implementation of `Option::filter` + --> tests/ui/manual_filter.rs:307:9 + | +LL | opt.and_then(move |x| if x == y { Some(x) } else { None }); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `filter(move |&x| x == y)` + +error: manual implementation of `Option::filter` + --> tests/ui/manual_filter.rs:311:10 + | +LL | opt1.and_then(|s| if s.len() > 2 { Some(s) } else { None }); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `filter(|s| s.len() > 2)` + +error: manual implementation of `Option::filter` + --> tests/ui/manual_filter.rs:317:9 + | +LL | opt.and_then(|x| if unsafe { f(x as u32) } { Some(x) } else { None }); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `filter(|&x| unsafe { f(x as u32) })` + +error: manual implementation of `Option::filter` + --> tests/ui/manual_filter.rs:319:9 + | +LL | opt.and_then(|x| unsafe { if f(x as u32) { Some(x) } else { None } }); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `filter(|&x| unsafe { f(x as u32) })` + +error: aborting due to 20 previous errors diff --git a/src/tools/clippy/tests/ui/manual_is_power_of_two.fixed b/src/tools/clippy/tests/ui/manual_is_power_of_two.fixed index 8a1ab785dfbf..8c0074b562a6 100644 --- a/src/tools/clippy/tests/ui/manual_is_power_of_two.fixed +++ b/src/tools/clippy/tests/ui/manual_is_power_of_two.fixed @@ -58,3 +58,15 @@ const fn high_msrv(a: u32) -> bool { a.is_power_of_two() //~^ manual_is_power_of_two } + +fn wrongly_unmangled_macros() { + macro_rules! test_val { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + let a = 16_u64; + let _ = test_val!(a).is_power_of_two(); + //~^ manual_is_power_of_two +} diff --git a/src/tools/clippy/tests/ui/manual_is_power_of_two.rs b/src/tools/clippy/tests/ui/manual_is_power_of_two.rs index 57a3b05e0336..580a1d0f7281 100644 --- a/src/tools/clippy/tests/ui/manual_is_power_of_two.rs +++ b/src/tools/clippy/tests/ui/manual_is_power_of_two.rs @@ -58,3 +58,15 @@ const fn high_msrv(a: u32) -> bool { a & (a - 1) == 0 //~^ manual_is_power_of_two } + +fn wrongly_unmangled_macros() { + macro_rules! test_val { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + let a = 16_u64; + let _ = test_val!(a).count_ones() == 1; + //~^ manual_is_power_of_two +} diff --git a/src/tools/clippy/tests/ui/manual_is_power_of_two.stderr b/src/tools/clippy/tests/ui/manual_is_power_of_two.stderr index 5781a093d5f2..e84cd6f42726 100644 --- a/src/tools/clippy/tests/ui/manual_is_power_of_two.stderr +++ b/src/tools/clippy/tests/ui/manual_is_power_of_two.stderr @@ -55,5 +55,11 @@ error: manually reimplementing `is_power_of_two` LL | a & (a - 1) == 0 | ^^^^^^^^^^^^^^^^ help: consider using `.is_power_of_two()`: `a.is_power_of_two()` -error: aborting due to 9 previous errors +error: manually reimplementing `is_power_of_two` + --> tests/ui/manual_is_power_of_two.rs:70:13 + | +LL | let _ = test_val!(a).count_ones() == 1; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `.is_power_of_two()`: `test_val!(a).is_power_of_two()` + +error: aborting due to 10 previous errors diff --git a/src/tools/clippy/tests/ui/manual_noop_waker.rs b/src/tools/clippy/tests/ui/manual_noop_waker.rs index 9b4dd90e273c..ecfbffeb008f 100644 --- a/src/tools/clippy/tests/ui/manual_noop_waker.rs +++ b/src/tools/clippy/tests/ui/manual_noop_waker.rs @@ -38,3 +38,28 @@ fn wake(self: Arc) {} fn wake_by_ref(self: &Arc) {} } } + +#[clippy::msrv = "1.84"] +mod msrv_1_84 { + use std::sync::Arc; + use std::task::Wake; + + struct CustomWaker; + impl Wake for CustomWaker { + fn wake(self: Arc) {} + fn wake_by_ref(self: &Arc) {} + } +} + +#[clippy::msrv = "1.85"] +mod msrv_1_85 { + use std::sync::Arc; + use std::task::Wake; + + struct CustomWaker; + impl Wake for CustomWaker { + //~^ manual_noop_waker + fn wake(self: Arc) {} + fn wake_by_ref(self: &Arc) {} + } +} diff --git a/src/tools/clippy/tests/ui/manual_noop_waker.stderr b/src/tools/clippy/tests/ui/manual_noop_waker.stderr index b3b30f96a08f..4a01a4d0b47a 100644 --- a/src/tools/clippy/tests/ui/manual_noop_waker.stderr +++ b/src/tools/clippy/tests/ui/manual_noop_waker.stderr @@ -16,5 +16,13 @@ LL | impl Wake for MyWakerPartial { | = help: use `std::task::Waker::noop()` instead -error: aborting due to 2 previous errors +error: manual implementation of a no-op waker + --> tests/ui/manual_noop_waker.rs:60:10 + | +LL | impl Wake for CustomWaker { + | ^^^^ + | + = help: use `std::task::Waker::noop()` instead + +error: aborting due to 3 previous errors diff --git a/src/tools/clippy/tests/ui/manual_rotate.fixed b/src/tools/clippy/tests/ui/manual_rotate.fixed index 1012ffc1aa2d..17fb4a3122f3 100644 --- a/src/tools/clippy/tests/ui/manual_rotate.fixed +++ b/src/tools/clippy/tests/ui/manual_rotate.fixed @@ -61,3 +61,26 @@ fn issue13028() { // don't lint, because `s` and `u` are different variables, albeit with the same value let _ = (x << s) | (x >> (32 - u)); } + +fn wrongly_unmangled_macros() { + macro_rules! test_expr { + ($val:expr) => { + $val.inner + }; + } + + struct Wrapper { + inner: u32, + } + + let x = Wrapper { inner: 42 }; + let _ = test_expr!(x).rotate_left(3); + //~^ manual_rotate + + let y = Wrapper { inner: 100 }; + + let _ = x.inner.rotate_left(test_expr!(y)); + //~^ manual_rotate + + let _ = (test_expr!(x) << 3) | (x.inner >> 29); +} diff --git a/src/tools/clippy/tests/ui/manual_rotate.rs b/src/tools/clippy/tests/ui/manual_rotate.rs index 3cdc79673c81..5899166f51f7 100644 --- a/src/tools/clippy/tests/ui/manual_rotate.rs +++ b/src/tools/clippy/tests/ui/manual_rotate.rs @@ -61,3 +61,26 @@ fn issue13028() { // don't lint, because `s` and `u` are different variables, albeit with the same value let _ = (x << s) | (x >> (32 - u)); } + +fn wrongly_unmangled_macros() { + macro_rules! test_expr { + ($val:expr) => { + $val.inner + }; + } + + struct Wrapper { + inner: u32, + } + + let x = Wrapper { inner: 42 }; + let _ = (test_expr!(x) << 3) | (test_expr!(x) >> 29); + //~^ manual_rotate + + let y = Wrapper { inner: 100 }; + + let _ = (x.inner << test_expr!(y)) | (x.inner >> (32 - test_expr!(y))); + //~^ manual_rotate + + let _ = (test_expr!(x) << 3) | (x.inner >> 29); +} diff --git a/src/tools/clippy/tests/ui/manual_rotate.stderr b/src/tools/clippy/tests/ui/manual_rotate.stderr index ea04ee028db6..76af443ae89e 100644 --- a/src/tools/clippy/tests/ui/manual_rotate.stderr +++ b/src/tools/clippy/tests/ui/manual_rotate.stderr @@ -91,5 +91,17 @@ error: there is no need to manually implement bit rotation LL | let _ = (x >> 9) | (x << (32 - 9)); | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: this expression can be rewritten as: `x.rotate_right(9)` -error: aborting due to 15 previous errors +error: there is no need to manually implement bit rotation + --> tests/ui/manual_rotate.rs:77:13 + | +LL | let _ = (test_expr!(x) << 3) | (test_expr!(x) >> 29); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: this expression can be rewritten as: `test_expr!(x).rotate_left(3)` + +error: there is no need to manually implement bit rotation + --> tests/ui/manual_rotate.rs:82:13 + | +LL | let _ = (x.inner << test_expr!(y)) | (x.inner >> (32 - test_expr!(y))); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: this expression can be rewritten as: `x.inner.rotate_left(test_expr!(y))` + +error: aborting due to 17 previous errors diff --git a/src/tools/clippy/tests/ui/manual_try_fold.rs b/src/tools/clippy/tests/ui/manual_try_fold.rs index c91ea41bb84c..cd2b0720f5bf 100644 --- a/src/tools/clippy/tests/ui/manual_try_fold.rs +++ b/src/tools/clippy/tests/ui/manual_try_fold.rs @@ -2,8 +2,9 @@ #![allow(clippy::unnecessary_fold, unused)] #![warn(clippy::manual_try_fold)] #![feature(try_trait_v2)] +#![feature(try_trait_v2_residual)] //@no-rustfix -use std::ops::{ControlFlow, FromResidual, Try}; +use std::ops::{ControlFlow, FromResidual, Residual, Try}; #[macro_use] extern crate proc_macros; @@ -11,15 +12,21 @@ // Test custom `Try` with more than 1 argument struct NotOption(i32, i32); +struct NotOptionResidual; + impl FromResidual for NotOption { fn from_residual(_: R) -> Self { todo!() } } +impl Residual<()> for NotOptionResidual { + type TryType = NotOption; +} + impl Try for NotOption { type Output = (); - type Residual = (); + type Residual = NotOptionResidual; fn from_output(_: Self::Output) -> Self { todo!() @@ -34,15 +41,21 @@ fn branch(self) -> ControlFlow { #[derive(Default)] struct NotOptionButWorse(i32); +struct NotOptionButWorseResidual; + impl FromResidual for NotOptionButWorse { fn from_residual(_: R) -> Self { todo!() } } +impl Residual<()> for NotOptionButWorseResidual { + type TryType = NotOptionButWorse; +} + impl Try for NotOptionButWorse { type Output = (); - type Residual = (); + type Residual = NotOptionButWorseResidual; fn from_output(_: Self::Output) -> Self { todo!() diff --git a/src/tools/clippy/tests/ui/manual_try_fold.stderr b/src/tools/clippy/tests/ui/manual_try_fold.stderr index f2740187878f..80e1e76cd955 100644 --- a/src/tools/clippy/tests/ui/manual_try_fold.stderr +++ b/src/tools/clippy/tests/ui/manual_try_fold.stderr @@ -1,5 +1,5 @@ error: usage of `Iterator::fold` on a type that implements `Try` - --> tests/ui/manual_try_fold.rs:59:10 + --> tests/ui/manual_try_fold.rs:72:10 | LL | .fold(Some(0i32), |sum, i| sum?.checked_add(*i)) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: use `try_fold` instead: `try_fold(0i32, |sum, i| ...)` @@ -8,19 +8,19 @@ LL | .fold(Some(0i32), |sum, i| sum?.checked_add(*i)) = help: to override `-D warnings` add `#[allow(clippy::manual_try_fold)]` error: usage of `Iterator::fold` on a type that implements `Try` - --> tests/ui/manual_try_fold.rs:64:10 + --> tests/ui/manual_try_fold.rs:77:10 | LL | .fold(NotOption(0i32, 0i32), |sum, i| NotOption(0i32, 0i32)); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: use `try_fold` instead: `try_fold(..., |sum, i| ...)` error: usage of `Iterator::fold` on a type that implements `Try` - --> tests/ui/manual_try_fold.rs:68:10 + --> tests/ui/manual_try_fold.rs:81:10 | LL | .fold(NotOptionButWorse(0i32), |sum, i| NotOptionButWorse(0i32)); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: use `try_fold` instead: `try_fold(0i32, |sum, i| ...)` error: usage of `Iterator::fold` on a type that implements `Try` - --> tests/ui/manual_try_fold.rs:99:10 + --> tests/ui/manual_try_fold.rs:112:10 | LL | .fold(Some(0i32), |sum, i| sum?.checked_add(*i)) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: use `try_fold` instead: `try_fold(0i32, |sum, i| ...)` diff --git a/src/tools/clippy/tests/ui/map_flatten.fixed b/src/tools/clippy/tests/ui/map_flatten.fixed index 12fca6706e41..a1af89139e36 100644 --- a/src/tools/clippy/tests/ui/map_flatten.fixed +++ b/src/tools/clippy/tests/ui/map_flatten.fixed @@ -1,5 +1,5 @@ #![warn(clippy::map_flatten)] -#![allow(clippy::unnecessary_filter_map)] +#![allow(clippy::unnecessary_filter_map, clippy::manual_filter)] // issue #8506, multi-line #[rustfmt::skip] diff --git a/src/tools/clippy/tests/ui/map_flatten.rs b/src/tools/clippy/tests/ui/map_flatten.rs index 3f1b7a268822..563d39a96639 100644 --- a/src/tools/clippy/tests/ui/map_flatten.rs +++ b/src/tools/clippy/tests/ui/map_flatten.rs @@ -1,5 +1,5 @@ #![warn(clippy::map_flatten)] -#![allow(clippy::unnecessary_filter_map)] +#![allow(clippy::unnecessary_filter_map, clippy::manual_filter)] // issue #8506, multi-line #[rustfmt::skip] diff --git a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.fixed b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.fixed index 254c46ecae38..97cb72748839 100644 --- a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.fixed +++ b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.fixed @@ -89,3 +89,17 @@ fn msrv_1_82() { std::iter::repeat(3).take(10); //~^ map_with_unused_argument_over_ranges } + +fn wrongly_unmangled_macros() { + macro_rules! test { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + std::iter::repeat_with(|| do_something()).take(test!(10)); + //~^ map_with_unused_argument_over_ranges + + std::iter::repeat_n(test!(3), 10); + //~^ map_with_unused_argument_over_ranges +} diff --git a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.rs b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.rs index 05c8d64f8012..f0222f407b8c 100644 --- a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.rs +++ b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.rs @@ -89,3 +89,17 @@ fn msrv_1_82() { (0..10).map(|_| 3); //~^ map_with_unused_argument_over_ranges } + +fn wrongly_unmangled_macros() { + macro_rules! test { + ($val:expr) => { + ($val * 2 + 1) + }; + } + + (0..test!(10)).map(|_| do_something()); + //~^ map_with_unused_argument_over_ranges + + (0..10).map(|_| test!(3)); + //~^ map_with_unused_argument_over_ranges +} diff --git a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.stderr b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.stderr index e5c93ceac02a..ba72a6b9d89f 100644 --- a/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.stderr +++ b/src/tools/clippy/tests/ui/map_with_unused_argument_over_ranges.stderr @@ -223,5 +223,29 @@ LL - (0..10).map(|_| 3); LL + std::iter::repeat(3).take(10); | -error: aborting due to 18 previous errors +error: map of a closure that does not depend on its parameter over a range + --> tests/ui/map_with_unused_argument_over_ranges.rs:100:5 + | +LL | (0..test!(10)).map(|_| do_something()); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +help: remove the explicit range and use `repeat_with` and `take` + | +LL - (0..test!(10)).map(|_| do_something()); +LL + std::iter::repeat_with(|| do_something()).take(test!(10)); + | + +error: map of a closure that does not depend on its parameter over a range + --> tests/ui/map_with_unused_argument_over_ranges.rs:103:5 + | +LL | (0..10).map(|_| test!(3)); + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +help: remove the explicit range and use `repeat_n` + | +LL - (0..10).map(|_| test!(3)); +LL + std::iter::repeat_n(test!(3), 10); + | + +error: aborting due to 20 previous errors diff --git a/src/tools/clippy/tests/ui/needless_bitwise_bool.fixed b/src/tools/clippy/tests/ui/needless_bitwise_bool.fixed index 751d3d257000..eedeecd8a8cb 100644 --- a/src/tools/clippy/tests/ui/needless_bitwise_bool.fixed +++ b/src/tools/clippy/tests/ui/needless_bitwise_bool.fixed @@ -40,3 +40,16 @@ fn main() { println!("true") // This is a BinOp with no side effects } } + +fn wrongly_unmangled_macros() { + let (x, y) = (false, true); + macro_rules! inverse { + ($e:expr) => { + !$e + }; + } + if inverse!(y) && inverse!(x) { + //~^ needless_bitwise_bool + println!("true") + } +} diff --git a/src/tools/clippy/tests/ui/needless_bitwise_bool.rs b/src/tools/clippy/tests/ui/needless_bitwise_bool.rs index 5d3ff3b2079c..5c0a4ccf266c 100644 --- a/src/tools/clippy/tests/ui/needless_bitwise_bool.rs +++ b/src/tools/clippy/tests/ui/needless_bitwise_bool.rs @@ -40,3 +40,16 @@ fn main() { println!("true") // This is a BinOp with no side effects } } + +fn wrongly_unmangled_macros() { + let (x, y) = (false, true); + macro_rules! inverse { + ($e:expr) => { + !$e + }; + } + if inverse!(y) & inverse!(x) { + //~^ needless_bitwise_bool + println!("true") + } +} diff --git a/src/tools/clippy/tests/ui/needless_bitwise_bool.stderr b/src/tools/clippy/tests/ui/needless_bitwise_bool.stderr index 4f64c7136916..7ee792d90e89 100644 --- a/src/tools/clippy/tests/ui/needless_bitwise_bool.stderr +++ b/src/tools/clippy/tests/ui/needless_bitwise_bool.stderr @@ -13,5 +13,11 @@ error: use of bitwise operator instead of lazy operator between booleans LL | if y & (0 < 1) { | ^^^^^^^^^^^ help: try: `y && (0 < 1)` -error: aborting due to 2 previous errors +error: use of bitwise operator instead of lazy operator between booleans + --> tests/ui/needless_bitwise_bool.rs:51:8 + | +LL | if inverse!(y) & inverse!(x) { + | ^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `inverse!(y) && inverse!(x)` + +error: aborting due to 3 previous errors diff --git a/src/tools/clippy/tests/ui/needless_bool/fixable.fixed b/src/tools/clippy/tests/ui/needless_bool/fixable.fixed index 2589819f019b..0af4f87bec67 100644 --- a/src/tools/clippy/tests/ui/needless_bool/fixable.fixed +++ b/src/tools/clippy/tests/ui/needless_bool/fixable.fixed @@ -167,3 +167,15 @@ fn issue12846() { let _x = a.then(|| todo!()); //~^ needless_bool } + +fn wrongly_unmangled_macros() { + macro_rules! test_expr { + ($val:expr) => { + ($val + 1 > 0) + }; + } + + let x = 42; + test_expr!(x); + //~^^^^^ needless_bool +} diff --git a/src/tools/clippy/tests/ui/needless_bool/fixable.rs b/src/tools/clippy/tests/ui/needless_bool/fixable.rs index f9cc0122f5e7..2e8719bd041e 100644 --- a/src/tools/clippy/tests/ui/needless_bool/fixable.rs +++ b/src/tools/clippy/tests/ui/needless_bool/fixable.rs @@ -227,3 +227,19 @@ fn issue12846() { let _x = if a { true } else { false }.then(|| todo!()); //~^ needless_bool } + +fn wrongly_unmangled_macros() { + macro_rules! test_expr { + ($val:expr) => { + ($val + 1 > 0) + }; + } + + let x = 42; + if test_expr!(x) { + true + } else { + false + }; + //~^^^^^ needless_bool +} diff --git a/src/tools/clippy/tests/ui/needless_bool/fixable.stderr b/src/tools/clippy/tests/ui/needless_bool/fixable.stderr index 9404d07ba0e0..e15260242f4d 100644 --- a/src/tools/clippy/tests/ui/needless_bool/fixable.stderr +++ b/src/tools/clippy/tests/ui/needless_bool/fixable.stderr @@ -209,5 +209,15 @@ error: this if-then-else expression returns a bool literal LL | let _x = if a { true } else { false }.then(|| todo!()); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: you can reduce it to: `a` -error: aborting due to 24 previous errors +error: this if-then-else expression returns a bool literal + --> tests/ui/needless_bool/fixable.rs:239:5 + | +LL | / if test_expr!(x) { +LL | | true +LL | | } else { +LL | | false +LL | | }; + | |_____^ help: you can reduce it to: `test_expr!(x)` + +error: aborting due to 25 previous errors diff --git a/src/tools/clippy/tests/ui/needless_borrowed_ref.fixed b/src/tools/clippy/tests/ui/needless_borrowed_ref.fixed index 6d7489921812..94f801118583 100644 --- a/src/tools/clippy/tests/ui/needless_borrowed_ref.fixed +++ b/src/tools/clippy/tests/ui/needless_borrowed_ref.fixed @@ -4,7 +4,8 @@ irrefutable_let_patterns, non_shorthand_field_patterns, clippy::needless_borrow, - clippy::needless_ifs + clippy::needless_ifs, + clippy::unneeded_wildcard_pattern )] fn main() {} diff --git a/src/tools/clippy/tests/ui/needless_borrowed_ref.rs b/src/tools/clippy/tests/ui/needless_borrowed_ref.rs index a4cb89923164..77334e07b25e 100644 --- a/src/tools/clippy/tests/ui/needless_borrowed_ref.rs +++ b/src/tools/clippy/tests/ui/needless_borrowed_ref.rs @@ -4,7 +4,8 @@ irrefutable_let_patterns, non_shorthand_field_patterns, clippy::needless_borrow, - clippy::needless_ifs + clippy::needless_ifs, + clippy::unneeded_wildcard_pattern )] fn main() {} diff --git a/src/tools/clippy/tests/ui/needless_borrowed_ref.stderr b/src/tools/clippy/tests/ui/needless_borrowed_ref.stderr index bfa3cafdedeb..f29789c66334 100644 --- a/src/tools/clippy/tests/ui/needless_borrowed_ref.stderr +++ b/src/tools/clippy/tests/ui/needless_borrowed_ref.stderr @@ -1,5 +1,5 @@ error: this pattern takes a reference on something that is being dereferenced - --> tests/ui/needless_borrowed_ref.rs:30:34 + --> tests/ui/needless_borrowed_ref.rs:31:34 | LL | let _ = v.iter_mut().filter(|&ref a| a.is_empty()); | ^^^^^^ @@ -13,7 +13,7 @@ LL + let _ = v.iter_mut().filter(|a| a.is_empty()); | error: this pattern takes a reference on something that is being dereferenced - --> tests/ui/needless_borrowed_ref.rs:35:17 + --> tests/ui/needless_borrowed_ref.rs:36:17 | LL | if let Some(&ref v) = thingy {} | ^^^^^^ @@ -25,7 +25,7 @@ LL + if let Some(v) = thingy {} | error: this pattern takes a reference on something that is being dereferenced - --> tests/ui/needless_borrowed_ref.rs:38:14 + --> tests/ui/needless_borrowed_ref.rs:39:14 | LL | if let &[&ref a, ref b] = slice_of_refs {} | ^^^^^^ @@ -37,7 +37,7 @@ LL + if let &[a, ref b] = slice_of_refs {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:41:9 + --> tests/ui/needless_borrowed_ref.rs:42:9 | LL | let &[ref a, ..] = &array; | ^^^^^^^^^^^^ @@ -49,7 +49,7 @@ LL + let [a, ..] = &array; | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:43:9 + --> tests/ui/needless_borrowed_ref.rs:44:9 | LL | let &[ref a, ref b, ..] = &array; | ^^^^^^^^^^^^^^^^^^^ @@ -61,7 +61,7 @@ LL + let [a, b, ..] = &array; | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:46:12 + --> tests/ui/needless_borrowed_ref.rs:47:12 | LL | if let &[ref a, ref b] = slice {} | ^^^^^^^^^^^^^^^ @@ -73,7 +73,7 @@ LL + if let [a, b] = slice {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:48:12 + --> tests/ui/needless_borrowed_ref.rs:49:12 | LL | if let &[ref a, ref b] = &vec[..] {} | ^^^^^^^^^^^^^^^ @@ -85,7 +85,7 @@ LL + if let [a, b] = &vec[..] {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:51:12 + --> tests/ui/needless_borrowed_ref.rs:52:12 | LL | if let &[ref a, ref b, ..] = slice {} | ^^^^^^^^^^^^^^^^^^^ @@ -97,7 +97,7 @@ LL + if let [a, b, ..] = slice {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:53:12 + --> tests/ui/needless_borrowed_ref.rs:54:12 | LL | if let &[ref a, .., ref b] = slice {} | ^^^^^^^^^^^^^^^^^^^ @@ -109,7 +109,7 @@ LL + if let [a, .., b] = slice {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:55:12 + --> tests/ui/needless_borrowed_ref.rs:56:12 | LL | if let &[.., ref a, ref b] = slice {} | ^^^^^^^^^^^^^^^^^^^ @@ -121,7 +121,7 @@ LL + if let [.., a, b] = slice {} | error: dereferencing a slice pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:58:12 + --> tests/ui/needless_borrowed_ref.rs:59:12 | LL | if let &[ref a, _] = slice {} | ^^^^^^^^^^^ @@ -133,7 +133,7 @@ LL + if let [a, _] = slice {} | error: dereferencing a tuple pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:61:12 + --> tests/ui/needless_borrowed_ref.rs:62:12 | LL | if let &(ref a, ref b, ref c) = &tuple {} | ^^^^^^^^^^^^^^^^^^^^^^ @@ -145,7 +145,7 @@ LL + if let (a, b, c) = &tuple {} | error: dereferencing a tuple pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:63:12 + --> tests/ui/needless_borrowed_ref.rs:64:12 | LL | if let &(ref a, _, ref c) = &tuple {} | ^^^^^^^^^^^^^^^^^^ @@ -157,7 +157,7 @@ LL + if let (a, _, c) = &tuple {} | error: dereferencing a tuple pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:65:12 + --> tests/ui/needless_borrowed_ref.rs:66:12 | LL | if let &(ref a, ..) = &tuple {} | ^^^^^^^^^^^^ @@ -169,7 +169,7 @@ LL + if let (a, ..) = &tuple {} | error: dereferencing a tuple pattern where every element takes a reference - --> tests/ui/needless_borrowed_ref.rs:68:12 + --> tests/ui/needless_borrowed_ref.rs:69:12 | LL | if let &TupleStruct(ref a, ..) = &tuple_struct {} | ^^^^^^^^^^^^^^^^^^^^^^^ @@ -181,7 +181,7 @@ LL + if let TupleStruct(a, ..) = &tuple_struct {} | error: dereferencing a struct pattern where every field's pattern takes a reference - --> tests/ui/needless_borrowed_ref.rs:71:12 + --> tests/ui/needless_borrowed_ref.rs:72:12 | LL | if let &Struct { | ____________^ @@ -202,7 +202,7 @@ LL ~ c: renamed, | error: dereferencing a struct pattern where every field's pattern takes a reference - --> tests/ui/needless_borrowed_ref.rs:79:12 + --> tests/ui/needless_borrowed_ref.rs:80:12 | LL | if let &Struct { ref a, b: _, .. } = &s {} | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/src/tools/clippy/tests/ui/needless_match.fixed b/src/tools/clippy/tests/ui/needless_match.fixed index 57273012a192..2d7b0fa2bb2c 100644 --- a/src/tools/clippy/tests/ui/needless_match.fixed +++ b/src/tools/clippy/tests/ui/needless_match.fixed @@ -1,5 +1,5 @@ #![warn(clippy::needless_match)] -#![allow(clippy::manual_map)] +#![allow(clippy::manual_map, clippy::question_mark)] #![allow(dead_code)] #![allow(unused)] #[derive(Clone, Copy)] diff --git a/src/tools/clippy/tests/ui/needless_match.rs b/src/tools/clippy/tests/ui/needless_match.rs index 3eb577868f2b..83e3e73feb6c 100644 --- a/src/tools/clippy/tests/ui/needless_match.rs +++ b/src/tools/clippy/tests/ui/needless_match.rs @@ -1,5 +1,5 @@ #![warn(clippy::needless_match)] -#![allow(clippy::manual_map)] +#![allow(clippy::manual_map, clippy::question_mark)] #![allow(dead_code)] #![allow(unused)] #[derive(Clone, Copy)] diff --git a/src/tools/clippy/tests/ui/nonminimal_bool.stderr b/src/tools/clippy/tests/ui/nonminimal_bool.stderr index 6a20b9216da5..29387cf31ee8 100644 --- a/src/tools/clippy/tests/ui/nonminimal_bool.stderr +++ b/src/tools/clippy/tests/ui/nonminimal_bool.stderr @@ -2,46 +2,87 @@ error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:17:13 | LL | let _ = !true; - | ^^^^^ help: try: `false` + | ^^^^^ | = note: `-D clippy::nonminimal-bool` implied by `-D warnings` = help: to override `-D warnings` add `#[allow(clippy::nonminimal_bool)]` +help: try + | +LL - let _ = !true; +LL + let _ = false; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:20:13 | LL | let _ = !false; - | ^^^^^^ help: try: `true` + | ^^^^^^ + | +help: try + | +LL - let _ = !false; +LL + let _ = true; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:23:13 | LL | let _ = !!a; - | ^^^ help: try: `a` + | ^^^ + | +help: try + | +LL - let _ = !!a; +LL + let _ = a; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:26:13 | LL | let _ = false || a; - | ^^^^^^^^^^ help: try: `a` + | ^^^^^^^^^^ + | +help: try + | +LL - let _ = false || a; +LL + let _ = a; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:32:13 | LL | let _ = !(!a && b); - | ^^^^^^^^^^ help: try: `a || !b` + | ^^^^^^^^^^ + | +help: try + | +LL - let _ = !(!a && b); +LL + let _ = a || !b; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:35:13 | LL | let _ = !(!a || b); - | ^^^^^^^^^^ help: try: `a && !b` + | ^^^^^^^^^^ + | +help: try + | +LL - let _ = !(!a || b); +LL + let _ = a && !b; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:38:13 | LL | let _ = !a && !(b && c); - | ^^^^^^^^^^^^^^^ help: try: `!(a || b && c)` + | ^^^^^^^^^^^^^^^ + | +help: try + | +LL - let _ = !a && !(b && c); +LL + let _ = !(a || b && c); + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:47:13 @@ -122,7 +163,13 @@ error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:90:8 | LL | if matches!(true, true) && true { - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `matches!(true, true)` + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +help: try + | +LL - if matches!(true, true) && true { +LL + if matches!(true, true) { + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:171:8 @@ -215,13 +262,25 @@ error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:212:8 | LL | if !(a < 2.0 && !b) { - | ^^^^^^^^^^^^^^^^ help: try: `a >= 2.0 || b` + | ^^^^^^^^^^^^^^^^ + | +help: try + | +LL - if !(a < 2.0 && !b) { +LL + if a >= 2.0 || b { + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:231:12 | LL | if !(matches!(ty, TyKind::Ref(_, _, _)) && !is_mutable(&expr)) { - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `!matches!(ty, TyKind::Ref(_, _, _)) || is_mutable(&expr)` + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +help: try + | +LL - if !(matches!(ty, TyKind::Ref(_, _, _)) && !is_mutable(&expr)) { +LL + if !matches!(ty, TyKind::Ref(_, _, _)) || is_mutable(&expr) { + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool.rs:251:8 diff --git a/src/tools/clippy/tests/ui/nonminimal_bool_methods.stderr b/src/tools/clippy/tests/ui/nonminimal_bool_methods.stderr index 568e88007727..948c28dcb537 100644 --- a/src/tools/clippy/tests/ui/nonminimal_bool_methods.stderr +++ b/src/tools/clippy/tests/ui/nonminimal_bool_methods.stderr @@ -29,13 +29,25 @@ error: this boolean expression can be simplified --> tests/ui/nonminimal_bool_methods.rs:20:13 | LL | let _ = !(a.is_some() && !c); - | ^^^^^^^^^^^^^^^^^^^^ help: try: `a.is_none() || c` + | ^^^^^^^^^^^^^^^^^^^^ + | +help: try + | +LL - let _ = !(a.is_some() && !c); +LL + let _ = a.is_none() || c; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool_methods.rs:22:13 | LL | let _ = !(a.is_some() || !c); - | ^^^^^^^^^^^^^^^^^^^^ help: try: `a.is_none() && c` + | ^^^^^^^^^^^^^^^^^^^^ + | +help: try + | +LL - let _ = !(a.is_some() || !c); +LL + let _ = a.is_none() && c; + | error: this boolean expression can be simplified --> tests/ui/nonminimal_bool_methods.rs:24:26 diff --git a/src/tools/clippy/tests/ui/println_empty_string.fixed b/src/tools/clippy/tests/ui/println_empty_string.fixed index 2c2901bc715a..3a31cbc04134 100644 --- a/src/tools/clippy/tests/ui/println_empty_string.fixed +++ b/src/tools/clippy/tests/ui/println_empty_string.fixed @@ -39,3 +39,28 @@ fn issue_16167() { //~^ println_empty_string } } + +#[rustfmt::skip] +fn issue_16843() { + println!{}; + //~^ println_empty_string + + println![]; + //~^ println_empty_string + + eprintln!{}; + //~^ println_empty_string + + eprintln![]; + //~^ println_empty_string + + match "a" { + _ => println!{}, + //~^ println_empty_string + } + + match "a" { + _ => println![], + //~^ println_empty_string + } +} diff --git a/src/tools/clippy/tests/ui/println_empty_string.rs b/src/tools/clippy/tests/ui/println_empty_string.rs index bc2971f54f2c..79309080131f 100644 --- a/src/tools/clippy/tests/ui/println_empty_string.rs +++ b/src/tools/clippy/tests/ui/println_empty_string.rs @@ -43,3 +43,28 @@ fn issue_16167() { //~^ println_empty_string } } + +#[rustfmt::skip] +fn issue_16843() { + println!{""}; + //~^ println_empty_string + + println![""]; + //~^ println_empty_string + + eprintln!{""}; + //~^ println_empty_string + + eprintln![""]; + //~^ println_empty_string + + match "a" { + _ => println!{""}, + //~^ println_empty_string + } + + match "a" { + _ => println![""], + //~^ println_empty_string + } +} diff --git a/src/tools/clippy/tests/ui/println_empty_string.stderr b/src/tools/clippy/tests/ui/println_empty_string.stderr index bdac1bb3b8ef..82ef3378f110 100644 --- a/src/tools/clippy/tests/ui/println_empty_string.stderr +++ b/src/tools/clippy/tests/ui/println_empty_string.stderr @@ -70,5 +70,53 @@ LL | _ => eprintln!("" ,), // tab and space between "" and comma | | | help: remove the empty string -error: aborting due to 8 previous errors +error: empty string literal in `println!` + --> tests/ui/println_empty_string.rs:49:5 + | +LL | println!{""}; + | ^^^^^^^^^--^ + | | + | help: remove the empty string + +error: empty string literal in `println!` + --> tests/ui/println_empty_string.rs:52:5 + | +LL | println![""]; + | ^^^^^^^^^--^ + | | + | help: remove the empty string + +error: empty string literal in `eprintln!` + --> tests/ui/println_empty_string.rs:55:5 + | +LL | eprintln!{""}; + | ^^^^^^^^^^--^ + | | + | help: remove the empty string + +error: empty string literal in `eprintln!` + --> tests/ui/println_empty_string.rs:58:5 + | +LL | eprintln![""]; + | ^^^^^^^^^^--^ + | | + | help: remove the empty string + +error: empty string literal in `println!` + --> tests/ui/println_empty_string.rs:62:14 + | +LL | _ => println!{""}, + | ^^^^^^^^^--^ + | | + | help: remove the empty string + +error: empty string literal in `println!` + --> tests/ui/println_empty_string.rs:67:14 + | +LL | _ => println![""], + | ^^^^^^^^^--^ + | | + | help: remove the empty string + +error: aborting due to 14 previous errors diff --git a/src/tools/clippy/tests/ui/ptr_offset_by_literal.fixed b/src/tools/clippy/tests/ui/ptr_offset_by_literal.fixed index bd9e41def938..174616b1e151 100644 --- a/src/tools/clippy/tests/ui/ptr_offset_by_literal.fixed +++ b/src/tools/clippy/tests/ui/ptr_offset_by_literal.fixed @@ -1,5 +1,5 @@ #![warn(clippy::ptr_offset_by_literal)] -#![allow(clippy::inconsistent_digit_grouping)] +#![allow(clippy::inconsistent_digit_grouping, clippy::byte_char_slices)] fn main() { let arr = [b'a', b'b', b'c']; diff --git a/src/tools/clippy/tests/ui/ptr_offset_by_literal.rs b/src/tools/clippy/tests/ui/ptr_offset_by_literal.rs index b8e3f9b26c68..d3202cbff982 100644 --- a/src/tools/clippy/tests/ui/ptr_offset_by_literal.rs +++ b/src/tools/clippy/tests/ui/ptr_offset_by_literal.rs @@ -1,5 +1,5 @@ #![warn(clippy::ptr_offset_by_literal)] -#![allow(clippy::inconsistent_digit_grouping)] +#![allow(clippy::inconsistent_digit_grouping, clippy::byte_char_slices)] fn main() { let arr = [b'a', b'b', b'c']; diff --git a/src/tools/clippy/tests/ui/question_mark.fixed b/src/tools/clippy/tests/ui/question_mark.fixed index e209da5c8258..bf4b4ff0a21e 100644 --- a/src/tools/clippy/tests/ui/question_mark.fixed +++ b/src/tools/clippy/tests/ui/question_mark.fixed @@ -1,5 +1,10 @@ #![feature(try_blocks)] -#![allow(clippy::unnecessary_wraps, clippy::no_effect)] +#![allow( + clippy::unnecessary_wraps, + clippy::no_effect, + clippy::needless_return, + clippy::toplevel_ref_arg +)] use std::sync::MutexGuard; @@ -110,10 +115,7 @@ fn func() -> Option { let _val = f()?; - let s: &str = match &Some(String::new()) { - Some(v) => v, - None => return None, - }; + let s: &str = &Some(String::new())?; f()?; @@ -124,12 +126,10 @@ fn func() -> Option { None => return opt_none!(), }; - match f() { - Some(val) => { - println!("{val}"); - val - }, - None => return None, + { + let val = f()?; + println!("{val}"); + val }; Some(0) @@ -537,3 +537,30 @@ fn issue16654() -> Result<(), i32> { Ok(()) } + +#[rustfmt::skip] +fn issue16751(mut v: Option) -> Option { + let _ = { + let n = &v?; + println!("{n}"); + Some(42) + }; + + let _ = { + let ref mut n = v?; + println!("{n}"); + Some(42) + }; + + let _ = { + let ref mut n = v?; + //~^ question_mark + println!("{n}"); + 42 + }; + + { + let n = v?; + if n > 10 { Some(42) } else { None } + } +} diff --git a/src/tools/clippy/tests/ui/question_mark.rs b/src/tools/clippy/tests/ui/question_mark.rs index 579b51461d13..93f76f16576c 100644 --- a/src/tools/clippy/tests/ui/question_mark.rs +++ b/src/tools/clippy/tests/ui/question_mark.rs @@ -1,5 +1,10 @@ #![feature(try_blocks)] -#![allow(clippy::unnecessary_wraps, clippy::no_effect)] +#![allow( + clippy::unnecessary_wraps, + clippy::no_effect, + clippy::needless_return, + clippy::toplevel_ref_arg +)] use std::sync::MutexGuard; @@ -156,6 +161,7 @@ fn f() -> Option { }; let s: &str = match &Some(String::new()) { + //~^ question_mark Some(v) => v, None => return None, }; @@ -178,6 +184,7 @@ fn f() -> Option { }; match f() { + //~^ question_mark Some(val) => { println!("{val}"); val @@ -668,3 +675,38 @@ fn issue16654() -> Result<(), i32> { Ok(()) } + +#[rustfmt::skip] +fn issue16751(mut v: Option) -> Option { + let _ = match &v { + //~^ question_mark + Some(n) => { + println!("{n}"); + Some(42) + } + None => return None, + }; + + let _ = match v { + //~^ question_mark + Some(ref mut n) => { + println!("{n}"); + Some(42) + } + None => return None, + }; + + let _ = if let Some(ref mut n) = v { + //~^ question_mark + println!("{n}"); + 42 + } else { + return None; + }; + + match v { + //~^ question_mark + Some(n) => if n > 10 { Some(42) } else { None }, + None => return None, + } +} diff --git a/src/tools/clippy/tests/ui/question_mark.stderr b/src/tools/clippy/tests/ui/question_mark.stderr index 1d7f665a2662..9d7cfc205764 100644 --- a/src/tools/clippy/tests/ui/question_mark.stderr +++ b/src/tools/clippy/tests/ui/question_mark.stderr @@ -1,5 +1,5 @@ error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:7:5 + --> tests/ui/question_mark.rs:12:5 | LL | / if a.is_none() { LL | | @@ -11,7 +11,7 @@ LL | | } = help: to override `-D warnings` add `#[allow(clippy::question_mark)]` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:53:9 + --> tests/ui/question_mark.rs:58:9 | LL | / if (self.opt).is_none() { LL | | @@ -20,7 +20,7 @@ LL | | } | |_________^ help: replace it with: `(self.opt)?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:58:9 + --> tests/ui/question_mark.rs:63:9 | LL | / if self.opt.is_none() { LL | | @@ -29,7 +29,7 @@ LL | | } | |_________^ help: replace it with: `self.opt?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:63:17 + --> tests/ui/question_mark.rs:68:17 | LL | let _ = if self.opt.is_none() { | _________________^ @@ -41,7 +41,7 @@ LL | | }; | |_________^ help: replace it with: `Some(self.opt?)` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:70:17 + --> tests/ui/question_mark.rs:75:17 | LL | let _ = if let Some(x) = self.opt { | _________________^ @@ -53,7 +53,7 @@ LL | | }; | |_________^ help: replace it with: `self.opt?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:88:9 + --> tests/ui/question_mark.rs:93:9 | LL | / if self.opt.is_none() { LL | | @@ -62,7 +62,7 @@ LL | | } | |_________^ help: replace it with: `self.opt.as_ref()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:97:9 + --> tests/ui/question_mark.rs:102:9 | LL | / if self.opt.is_none() { LL | | @@ -71,7 +71,7 @@ LL | | } | |_________^ help: replace it with: `self.opt.as_ref()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:106:9 + --> tests/ui/question_mark.rs:111:9 | LL | / if self.opt.is_none() { LL | | @@ -80,7 +80,7 @@ LL | | } | |_________^ help: replace it with: `self.opt.as_ref()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:114:26 + --> tests/ui/question_mark.rs:119:26 | LL | let v: &Vec<_> = if let Some(ref v) = self.opt { | __________________________^ @@ -92,7 +92,7 @@ LL | | }; | |_________^ help: replace it with: `self.opt.as_ref()?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:125:17 + --> tests/ui/question_mark.rs:130:17 | LL | let v = if let Some(v) = self.opt { | _________________^ @@ -104,7 +104,7 @@ LL | | }; | |_________^ help: replace it with: `self.opt?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:147:5 + --> tests/ui/question_mark.rs:152:5 | LL | / if f().is_none() { LL | | @@ -113,7 +113,7 @@ LL | | } | |_____^ help: replace it with: `f()?;` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:152:16 + --> tests/ui/question_mark.rs:157:16 | LL | let _val = match f() { | ________________^ @@ -124,7 +124,18 @@ LL | | }; | |_____^ help: try instead: `f()?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:163:5 + --> tests/ui/question_mark.rs:163:19 + | +LL | let s: &str = match &Some(String::new()) { + | ___________________^ +LL | | +LL | | Some(v) => v, +LL | | None => return None, +LL | | }; + | |_____^ help: try instead: `&Some(String::new())?` + +error: this `match` expression can be replaced with `?` + --> tests/ui/question_mark.rs:169:5 | LL | / match f() { LL | | @@ -134,7 +145,7 @@ LL | | }; | |_____^ help: try instead: `f()?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:169:5 + --> tests/ui/question_mark.rs:175:5 | LL | / match opt_none!() { LL | | @@ -143,14 +154,35 @@ LL | | None => return None, LL | | }; | |_____^ help: try instead: `opt_none!()?` +error: this `match` expression can be replaced with `?` + --> tests/ui/question_mark.rs:186:5 + | +LL | / match f() { +LL | | +LL | | Some(val) => { +LL | | println!("{val}"); +... | +LL | | None => return None, +LL | | }; + | |_____^ + | +help: try instead + | +LL ~ { +LL + let val = f()?; +LL + println!("{val}"); +LL + val +LL ~ }; + | + error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:196:13 + --> tests/ui/question_mark.rs:203:13 | LL | let _ = if let Ok(x) = x { x } else { return x }; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: replace it with: `x?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:199:5 + --> tests/ui/question_mark.rs:206:5 | LL | / if x.is_err() { LL | | @@ -159,7 +191,7 @@ LL | | } | |_____^ help: replace it with: `x?;` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:204:16 + --> tests/ui/question_mark.rs:211:16 | LL | let _val = match func_returning_result() { | ________________^ @@ -170,7 +202,7 @@ LL | | }; | |_____^ help: try instead: `func_returning_result()?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:210:5 + --> tests/ui/question_mark.rs:217:5 | LL | / match func_returning_result() { LL | | @@ -180,7 +212,7 @@ LL | | }; | |_____^ help: try instead: `func_returning_result()?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:302:5 + --> tests/ui/question_mark.rs:309:5 | LL | / if let Err(err) = func_returning_result() { LL | | @@ -189,7 +221,7 @@ LL | | } | |_____^ help: replace it with: `func_returning_result()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:310:5 + --> tests/ui/question_mark.rs:317:5 | LL | / if let Err(err) = func_returning_result() { LL | | @@ -198,7 +230,7 @@ LL | | } | |_____^ help: replace it with: `func_returning_result()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:393:13 + --> tests/ui/question_mark.rs:400:13 | LL | / if a.is_none() { LL | | @@ -208,7 +240,7 @@ LL | | } | |_____________^ help: replace it with: `a?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:454:5 + --> tests/ui/question_mark.rs:461:5 | LL | / let Some(v) = bar.foo.owned.clone() else { LL | | return None; @@ -216,7 +248,7 @@ LL | | }; | |______^ help: replace it with: `let v = bar.foo.owned.clone()?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:469:5 + --> tests/ui/question_mark.rs:476:5 | LL | / let Some(ref x) = foo.opt_x else { LL | | return None; @@ -224,7 +256,7 @@ LL | | }; | |______^ help: replace it with: `let x = foo.opt_x.as_ref()?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:479:5 + --> tests/ui/question_mark.rs:486:5 | LL | / let Some(ref mut x) = foo.opt_x else { LL | | return None; @@ -232,7 +264,7 @@ LL | | }; | |______^ help: replace it with: `let x = foo.opt_x.as_mut()?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:490:5 + --> tests/ui/question_mark.rs:497:5 | LL | / let Some(ref x @ ref y) = foo.opt_x else { LL | | return None; @@ -240,7 +272,7 @@ LL | | }; | |______^ help: replace it with: `let x @ y = foo.opt_x.as_ref()?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:494:5 + --> tests/ui/question_mark.rs:501:5 | LL | / let Some(ref x @ WrapperStructWithString(_)) = bar else { LL | | return None; @@ -248,7 +280,7 @@ LL | | }; | |______^ help: replace it with: `let x @ &WrapperStructWithString(_) = bar.as_ref()?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:498:5 + --> tests/ui/question_mark.rs:505:5 | LL | / let Some(ref mut x @ WrapperStructWithString(_)) = bar else { LL | | return None; @@ -256,7 +288,7 @@ LL | | }; | |______^ help: replace it with: `let x @ &mut WrapperStructWithString(_) = bar.as_mut()?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:520:5 + --> tests/ui/question_mark.rs:527:5 | LL | / if arg.is_none() { LL | | @@ -265,7 +297,7 @@ LL | | } | |_____^ help: replace it with: `arg?;` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:524:15 + --> tests/ui/question_mark.rs:531:15 | LL | let val = match arg { | _______________^ @@ -276,7 +308,7 @@ LL | | }; | |_____^ help: try instead: `arg?` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:534:5 + --> tests/ui/question_mark.rs:541:5 | LL | / let Some(a) = *a else { LL | | return None; @@ -284,7 +316,7 @@ LL | | }; | |______^ help: replace it with: `let a = (*a)?;` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:566:5 + --> tests/ui/question_mark.rs:573:5 | LL | / match some_result { LL | | @@ -294,7 +326,7 @@ LL | | }; | |_____^ help: try instead: `some_result?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:572:5 + --> tests/ui/question_mark.rs:579:5 | LL | / match some_result { LL | | @@ -304,7 +336,7 @@ LL | | }; | |_____^ help: try instead: `some_result?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:578:5 + --> tests/ui/question_mark.rs:585:5 | LL | / match some_result { LL | | @@ -314,7 +346,7 @@ LL | | }; | |_____^ help: try instead: `some_result?` error: this `match` expression can be replaced with `?` - --> tests/ui/question_mark.rs:596:17 + --> tests/ui/question_mark.rs:603:17 | LL | let x = match result { | _________________^ @@ -325,7 +357,7 @@ LL | | }; | |_________^ help: try instead: `result?` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:609:9 + --> tests/ui/question_mark.rs:616:9 | LL | / if let Err(reason) = result { LL | | @@ -334,7 +366,7 @@ LL | | } | |_________^ help: replace it with: `result?;` error: this `let...else` may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:626:5 + --> tests/ui/question_mark.rs:633:5 | LL | / let Some(x) = test_expr!(42) else { LL | | return None; @@ -342,7 +374,7 @@ LL | | }; | |______^ help: replace it with: `let x = test_expr!(42)?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:632:5 + --> tests/ui/question_mark.rs:639:5 | LL | / if test_expr!(42).is_none() { LL | | @@ -351,7 +383,7 @@ LL | | } | |_____^ help: replace it with: `test_expr!(42)?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:643:12 + --> tests/ui/question_mark.rs:650:12 | LL | } else if let Some(x) = a { | ____________^ @@ -363,7 +395,7 @@ LL | | }; | |_____^ help: replace it with: `{ a? }` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:658:9 + --> tests/ui/question_mark.rs:665:9 | LL | / if let Err(err) = result { LL | | @@ -372,7 +404,7 @@ LL | | } | |_________^ help: replace it with: `result?;` error: this block may be rewritten with the `?` operator - --> tests/ui/question_mark.rs:664:10 + --> tests/ui/question_mark.rs:671:10 | LL | _ = [if let Err(err) = result { | __________^ @@ -381,5 +413,90 @@ LL | | return Err(err); LL | | }]; | |_____^ help: replace it with: `{ result?; }` -error: aborting due to 40 previous errors +error: this `match` expression can be replaced with `?` + --> tests/ui/question_mark.rs:681:13 + | +LL | let _ = match &v { + | _____________^ +LL | | +LL | | Some(n) => { +LL | | println!("{n}"); +... | +LL | | None => return None, +LL | | }; + | |_____^ + | +help: try instead + | +LL ~ let _ = { +LL + let n = &v?; +LL + println!("{n}"); +LL + Some(42) +LL ~ }; + | + +error: this `match` expression can be replaced with `?` + --> tests/ui/question_mark.rs:690:13 + | +LL | let _ = match v { + | _____________^ +LL | | +LL | | Some(ref mut n) => { +LL | | println!("{n}"); +... | +LL | | None => return None, +LL | | }; + | |_____^ + | +help: try instead + | +LL ~ let _ = { +LL + let ref mut n = v?; +LL + println!("{n}"); +LL + Some(42) +LL ~ }; + | + +error: this block may be rewritten with the `?` operator + --> tests/ui/question_mark.rs:699:13 + | +LL | let _ = if let Some(ref mut n) = v { + | _____________^ +LL | | +LL | | println!("{n}"); +LL | | 42 +LL | | } else { +LL | | return None; +LL | | }; + | |_____^ + | +help: replace it with + | +LL ~ let _ = { +LL + let ref mut n = v?; +LL + +LL + println!("{n}"); +LL + 42 +LL ~ }; + | + +error: this `match` expression can be replaced with `?` + --> tests/ui/question_mark.rs:707:5 + | +LL | / match v { +LL | | +LL | | Some(n) => if n > 10 { Some(42) } else { None }, +LL | | None => return None, +LL | | } + | |_____^ + | +help: try instead + | +LL ~ { +LL + let n = v?; +LL + if n > 10 { Some(42) } else { None } +LL + } + | + +error: aborting due to 46 previous errors diff --git a/src/tools/clippy/tests/ui/range_plus_minus_one.fixed b/src/tools/clippy/tests/ui/range_plus_minus_one.fixed index 5c6da6d5aed3..e07a0e07368b 100644 --- a/src/tools/clippy/tests/ui/range_plus_minus_one.fixed +++ b/src/tools/clippy/tests/ui/range_plus_minus_one.fixed @@ -180,3 +180,16 @@ fn issue9908_2(n: usize) -> usize { (1..n).sum() //~^ range_minus_one } + +fn wrongly_unmangled_macros() { + macro_rules! test { + ($val:expr) => { + ($val * 2 + 0) + }; + } + + let x = 5usize; + for _ in test!(x)..=test!(x) { + //~^ range_plus_one + } +} diff --git a/src/tools/clippy/tests/ui/range_plus_minus_one.rs b/src/tools/clippy/tests/ui/range_plus_minus_one.rs index 7172da6034b8..3e6e4f629a51 100644 --- a/src/tools/clippy/tests/ui/range_plus_minus_one.rs +++ b/src/tools/clippy/tests/ui/range_plus_minus_one.rs @@ -180,3 +180,16 @@ fn issue9908_2(n: usize) -> usize { (1..=n - 1).sum() //~^ range_minus_one } + +fn wrongly_unmangled_macros() { + macro_rules! test { + ($val:expr) => { + ($val * 2 + 0) + }; + } + + let x = 5usize; + for _ in test!(x)..test!(x) + 1 { + //~^ range_plus_one + } +} diff --git a/src/tools/clippy/tests/ui/range_plus_minus_one.stderr b/src/tools/clippy/tests/ui/range_plus_minus_one.stderr index 60abe50efa10..79c482aeaa6b 100644 --- a/src/tools/clippy/tests/ui/range_plus_minus_one.stderr +++ b/src/tools/clippy/tests/ui/range_plus_minus_one.stderr @@ -88,5 +88,11 @@ LL | (1..=n - 1).sum() = note: `-D clippy::range-minus-one` implied by `-D warnings` = help: to override `-D warnings` add `#[allow(clippy::range_minus_one)]` -error: aborting due to 14 previous errors +error: an inclusive range would be more readable + --> tests/ui/range_plus_minus_one.rs:192:14 + | +LL | for _ in test!(x)..test!(x) + 1 { + | ^^^^^^^^^^^^^^^^^^^^^^ help: use: `test!(x)..=test!(x)` + +error: aborting due to 15 previous errors diff --git a/src/tools/clippy/tests/ui/return_and_then.fixed b/src/tools/clippy/tests/ui/return_and_then.fixed index 8ee259b97f3d..be9a8e1da5c6 100644 --- a/src/tools/clippy/tests/ui/return_and_then.fixed +++ b/src/tools/clippy/tests/ui/return_and_then.fixed @@ -1,4 +1,5 @@ #![warn(clippy::return_and_then)] +#![allow(clippy::manual_filter)] fn main() { fn test_opt_block(opt: Option) -> Option { diff --git a/src/tools/clippy/tests/ui/return_and_then.rs b/src/tools/clippy/tests/ui/return_and_then.rs index dcb344f142bb..5d8372e418bf 100644 --- a/src/tools/clippy/tests/ui/return_and_then.rs +++ b/src/tools/clippy/tests/ui/return_and_then.rs @@ -1,4 +1,5 @@ #![warn(clippy::return_and_then)] +#![allow(clippy::manual_filter)] fn main() { fn test_opt_block(opt: Option) -> Option { diff --git a/src/tools/clippy/tests/ui/return_and_then.stderr b/src/tools/clippy/tests/ui/return_and_then.stderr index 33867ea818aa..37d92a22bf8b 100644 --- a/src/tools/clippy/tests/ui/return_and_then.stderr +++ b/src/tools/clippy/tests/ui/return_and_then.stderr @@ -1,5 +1,5 @@ error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:5:9 + --> tests/ui/return_and_then.rs:6:9 | LL | / opt.and_then(|n| { LL | | @@ -21,7 +21,7 @@ LL + if n > 1 { Some(ret) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:14:9 + --> tests/ui/return_and_then.rs:15:9 | LL | opt.and_then(|n| test_opt_block(Some(n))) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -33,7 +33,7 @@ LL + test_opt_block(Some(n)) | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:19:9 + --> tests/ui/return_and_then.rs:20:9 | LL | gen_option(1).and_then(|n| test_opt_block(Some(n))) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -45,7 +45,7 @@ LL + test_opt_block(Some(n)) | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:24:9 + --> tests/ui/return_and_then.rs:25:9 | LL | opt.and_then(|n| if n > 1 { Ok(n + 1) } else { Err(n) }) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -57,7 +57,7 @@ LL + if n > 1 { Ok(n + 1) } else { Err(n) } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:29:9 + --> tests/ui/return_and_then.rs:30:9 | LL | opt.and_then(|n| test_res_block(Ok(n))) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -69,7 +69,7 @@ LL + test_res_block(Ok(n)) | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:35:9 + --> tests/ui/return_and_then.rs:36:9 | LL | Some("").and_then(|x| if x.len() > 2 { Some(3) } else { None }) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -81,7 +81,7 @@ LL + if x.len() > 2 { Some(3) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:41:9 + --> tests/ui/return_and_then.rs:42:9 | LL | / Some(match (vec![1, 2, 3], vec![1, 2, 4]) { LL | | @@ -102,7 +102,7 @@ LL + if x.len() > 2 { Some(3) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:69:13 + --> tests/ui/return_and_then.rs:70:13 | LL | Some("").and_then(|x| if x.len() > 2 { Some(3) } else { None }) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -114,7 +114,7 @@ LL + if x.len() > 2 { Some(3) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:77:20 + --> tests/ui/return_and_then.rs:78:20 | LL | return Some("").and_then(|x| if x.len() > 2 { Some(3) } else { None }); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -128,7 +128,7 @@ LL ~ }; | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:85:20 + --> tests/ui/return_and_then.rs:86:20 | LL | return Some("").and_then(|mut x| { | ____________________^ @@ -147,7 +147,7 @@ LL ~ }; | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:97:20 + --> tests/ui/return_and_then.rs:98:20 | LL | return Some("").and_then(|x| if x.len() > 2 { Some(3) } else { None }), | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -161,7 +161,7 @@ LL ~ }, | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:105:13 + --> tests/ui/return_and_then.rs:106:13 | LL | i.and_then(|i| if i > 3 { Some(i) } else { None }) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -173,7 +173,7 @@ LL + if i > 3 { Some(i) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:114:22 + --> tests/ui/return_and_then.rs:115:22 | LL | 1 | 2 => i.and_then(|i| if i > 3 { Some(i) } else { None }), | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -187,7 +187,7 @@ LL ~ }, | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:126:21 + --> tests/ui/return_and_then.rs:127:21 | LL | i.and_then(|i| if i > 3 { Some(i) } else { None }) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -199,7 +199,7 @@ LL + if i > 3 { Some(i) } else { None } | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:141:23 + --> tests/ui/return_and_then.rs:142:23 | LL | break i.and_then(|i| if i > 3 { Some(i) } else { None }); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -213,7 +213,7 @@ LL ~ }); | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:146:32 + --> tests/ui/return_and_then.rs:147:32 | LL | break 'foo i.and_then(|i| if i > 3 { Some(i) } else { None }); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -227,7 +227,7 @@ LL ~ }); | error: use the `?` operator instead of an `and_then` call - --> tests/ui/return_and_then.rs:151:28 + --> tests/ui/return_and_then.rs:152:28 | LL | break 'bar i.and_then(|i| if i > 3 { Some(i) } else { None }); | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/src/tools/clippy/tests/ui/swap.fixed b/src/tools/clippy/tests/ui/swap.fixed index 6a64e64e98fa..0d968e96ff79 100644 --- a/src/tools/clippy/tests/ui/swap.fixed +++ b/src/tools/clippy/tests/ui/swap.fixed @@ -195,3 +195,14 @@ const fn issue_10421(x: u32) -> u32 { let a = a; a } + +fn wrongly_unmangled_macros() { + macro_rules! test_slice { + ($val:expr) => { + *&mut $val + }; + } + + let mut foo = [1, 2]; + test_slice!(foo).swap(0, 1); +} diff --git a/src/tools/clippy/tests/ui/swap.rs b/src/tools/clippy/tests/ui/swap.rs index e2d89c47382d..c78c320332fb 100644 --- a/src/tools/clippy/tests/ui/swap.rs +++ b/src/tools/clippy/tests/ui/swap.rs @@ -241,3 +241,17 @@ const fn issue_10421(x: u32) -> u32 { let a = a; a } + +fn wrongly_unmangled_macros() { + macro_rules! test_slice { + ($val:expr) => { + *&mut $val + }; + } + + let mut foo = [1, 2]; + let temp = test_slice!(foo)[0]; + //~^ manual_swap + test_slice!(foo)[0] = test_slice!(foo)[1]; + test_slice!(foo)[1] = temp; +} diff --git a/src/tools/clippy/tests/ui/swap.stderr b/src/tools/clippy/tests/ui/swap.stderr index 195b888187e6..e730be40e349 100644 --- a/src/tools/clippy/tests/ui/swap.stderr +++ b/src/tools/clippy/tests/ui/swap.stderr @@ -173,5 +173,14 @@ LL | | s.0.y = t; | = note: or maybe you should use `std::mem::replace`? -error: aborting due to 17 previous errors +error: this looks like you are swapping elements of `test_slice!(foo)` manually + --> tests/ui/swap.rs:253:5 + | +LL | / let temp = test_slice!(foo)[0]; +LL | | +LL | | test_slice!(foo)[0] = test_slice!(foo)[1]; +LL | | test_slice!(foo)[1] = temp; + | |_______________________________^ help: try: `test_slice!(foo).swap(0, 1);` + +error: aborting due to 18 previous errors diff --git a/src/tools/clippy/tests/ui/unknown_clippy_lints.stderr b/src/tools/clippy/tests/ui/unknown_clippy_lints.stderr index 974c24bdc3bf..592fdfbebd43 100644 --- a/src/tools/clippy/tests/ui/unknown_clippy_lints.stderr +++ b/src/tools/clippy/tests/ui/unknown_clippy_lints.stderr @@ -1,11 +1,23 @@ +error: unknown lint: `clippy::All` + --> tests/ui/unknown_clippy_lints.rs:3:10 + | +LL | #![allow(clippy::All)] + | ^^^^^^^^^^^ help: did you mean: `clippy::all` + | + = note: `-D unknown-lints` implied by `-D warnings` + = help: to override `-D warnings` add `#[allow(unknown_lints)]` + +error: unknown lint: `clippy::CMP_OWNED` + --> tests/ui/unknown_clippy_lints.rs:5:9 + | +LL | #![warn(clippy::CMP_OWNED)] + | ^^^^^^^^^^^^^^^^^ help: did you mean: `clippy::cmp_owned` + error: unknown lint: `clippy::if_not_els` --> tests/ui/unknown_clippy_lints.rs:9:8 | LL | #[warn(clippy::if_not_els)] | ^^^^^^^^^^^^^^^^^^ help: did you mean: `clippy::if_not_else` - | - = note: `-D unknown-lints` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(unknown_lints)]` error: unknown lint: `clippy::UNNecsaRy_cAst` --> tests/ui/unknown_clippy_lints.rs:11:8 @@ -55,17 +67,5 @@ LL - #[warn(clippy::missing_docs)] LL + #[warn(missing_docs)] | -error: unknown lint: `clippy::All` - --> tests/ui/unknown_clippy_lints.rs:3:10 - | -LL | #![allow(clippy::All)] - | ^^^^^^^^^^^ help: did you mean: `clippy::all` - -error: unknown lint: `clippy::CMP_OWNED` - --> tests/ui/unknown_clippy_lints.rs:5:9 - | -LL | #![warn(clippy::CMP_OWNED)] - | ^^^^^^^^^^^^^^^^^ help: did you mean: `clippy::cmp_owned` - error: aborting due to 9 previous errors diff --git a/src/tools/clippy/tests/ui/unnecessary_cast.fixed b/src/tools/clippy/tests/ui/unnecessary_cast.fixed index 2b34111c9357..1ecc3ecf57a0 100644 --- a/src/tools/clippy/tests/ui/unnecessary_cast.fixed +++ b/src/tools/clippy/tests/ui/unnecessary_cast.fixed @@ -284,6 +284,369 @@ mod fixable { let _ = 5i32 as i64; //~^ unnecessary_cast } + + mod issue_16449_support { + use std::marker::PhantomData; + use std::ops::{Add, Mul}; + + pub trait PowLike { + type Output; + fn pow_like(self, rhs: Rhs) -> Self::Output; + } + + impl PowLike for f64 { + type Output = f64; + fn pow_like(self, rhs: f64) -> f64 { + self.powf(rhs) + } + } + + impl PowLike for f64 { + type Output = f64; + fn pow_like(self, _: i32) -> f64 { + self + } + } + + impl PowLike for f64 { + type Output = f32; + fn pow_like(self, _: u32) -> f32 { + self as f32 + } + } + + pub struct Mat(pub PhantomData); + + pub fn mat(_: &[[T; 1]; 1]) -> Mat { + Mat(PhantomData) + } + + pub struct Out(pub PhantomData); + + impl Out { + pub fn view(self) {} + } + + impl Out { + pub fn view(self) {} + } + + impl Mul<&Mat> for f64 { + type Output = Out; + + fn mul(self, _: &Mat) -> Self::Output { + Out(PhantomData) + } + } + + impl Mul<&Mat> for f32 { + type Output = Out; + + fn mul(self, _: &Mat) -> Self::Output { + Out(PhantomData) + } + } + + pub fn id(x: T) -> T { + x + } + + pub fn id_with(x: T, _: U) -> T { + x + } + + pub struct Wrap { + pub inner: T, + } + + pub fn wrap(inner: T) -> Wrap { + Wrap { inner } + } + + pub struct MethodWrap; + + impl MethodWrap { + pub fn id(&self, x: T) -> T { + x + } + + pub fn id_with(&self, x: T, _: U) -> T { + x + } + + pub fn wrap(&self, inner: T) -> Wrap { + Wrap { inner } + } + } + + pub struct X; + + impl Add for X { + type Output = f64; + fn add(self, _: i32) -> f64 { + 1.0 + } + } + + impl Add for X { + type Output = f32; + fn add(self, _: u32) -> f32 { + 1.0 + } + } + + pub struct Y; + + impl Add for Y { + type Output = f64; + fn add(self, _: i32) -> f64 { + 1.0 + } + } + + pub trait PowLikeSingleImpl { + type Output; + fn pow_like_single_impl(self, rhs: Rhs) -> Self::Output; + } + + impl PowLikeSingleImpl for f64 { + type Output = f64; + + fn pow_like_single_impl(self, _: i32) -> f64 { + self + } + } + } + + // Issue #16449: removing the cast still affects inference / impl selection, + // so these must not lint. + + // Minimal reproduction of the original issue. + fn issue_16449_minimal_original_reproduction() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (1.0_f64.pow_like(2) as f64 * &a).view(); + } + + // Wrappers that preserve the inference sensitive path. + fn issue_16449_struct_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + Wrap { + inner: 1.0_f64.pow_like(2) as f64 * &a, + } + .inner + .view(); + } + + fn issue_16449_free_identity_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + id(1.0_f64.pow_like(2) as f64 * &a).view(); + } + + fn issue_16449_method_identity_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + s.id(1.0_f64.pow_like(2) as f64 * &a).view(); + } + + fn issue_16449_free_wrap_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + wrap(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + } + + fn issue_16449_method_wrap_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + s.wrap(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + } + + fn issue_16449_block_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ({ 1.0_f64.pow_like(2) as f64 * &a }).view(); + } + + #[allow(clippy::if_same_then_else)] + fn issue_16449_if_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (if true { + 1.0_f64.pow_like(2) as f64 * &a + } else { + 1.0_f64.pow_like(2) as f64 * &a + }) + .view(); + } + + fn issue_16449_match_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (match 0 { + 0 => 1.0_f64.pow_like(2) as f64 * &a, + _ => 1.0_f64.pow_like(2) as f64 * &a, + }) + .view(); + } + + #[allow(clippy::let_and_return)] + fn issue_16449_let_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ({ + let x = 1.0_f64.pow_like(2) as f64 * &a; + x + }) + .view(); + } + + #[allow(clippy::never_loop)] + fn issue_16449_loop_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (loop { + break 1.0_f64.pow_like(2) as f64 * &a; + }) + .view(); + } + + #[allow(clippy::double_parens)] + fn issue_16449_operator_reproduction() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ((X + 2) as f64 * &a).view(); + } + + // Placeholder generic arguments still leave inference active, + // so these must not lint. + fn issue_16449_placeholder_generics_do_not_lint() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + // placeholder call + id::<_>(1.0_f64.pow_like(2) as f64 * &a).view(); + // placeholder method call + s.id::<_>(1.0_f64.pow_like(2) as f64 * &a).view(); + // mixed placeholder call + id_with::<_, u8>(1.0_f64.pow_like(2) as f64 * &a, 0).view(); + // mixed placeholder method call + s.id_with::<_, u8>(1.0_f64.pow_like(2) as f64 * &a, 0).view(); + } + + // These look similar, but inference no longer depends on the cast, so they should lint. + + fn issue_16449_explicit_generics_still_lint() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + // explicit call + id::>(1.0_f64.pow_like(2) * &a).view(); + //~^ unnecessary_cast + + // explicit method call + s.id::>(1.0_f64.pow_like(2) * &a).view(); + //~^ unnecessary_cast + + // explicit free wrap + wrap::>(1.0_f64.pow_like(2) * &a).inner.view(); + //~^ unnecessary_cast + + // explicit method wrap + s.wrap::>(1.0_f64.pow_like(2) * &a).inner.view(); + //~^ unnecessary_cast + } + + // A nonprimitive method receiver alone should not suppress the lint. + fn issue_16449_nonprimitive_receiver_should_still_lint() { + use self::issue_16449_support::PowLikeSingleImpl; + struct Receiver; + + impl Receiver { + fn take(&self, x: f64) -> f64 { + x + } + } + + let receiver = Receiver; + let _ = receiver.take(1.0_f64.pow_like_single_impl(2)).abs(); + //~^ unnecessary_cast + } + + fn issue_16449_wrapper_still_lints() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + let _ = id(1.0_f64.powi(2)).abs(); + //~^ unnecessary_cast + + let _ = wrap(1.0_f64.powi(2)).inner.abs(); + //~^ unnecessary_cast + + let _ = s.id(1.0_f64.powi(2)).abs(); + //~^ unnecessary_cast + + let _ = s.wrap(1.0_f64.powi(2)).inner.abs(); + //~^ unnecessary_cast + + let _ = id(1.0_f64.powi(2) * &a); + //~^ unnecessary_cast + + let _ = s.id(1.0_f64.powi(2) * &a); + //~^ unnecessary_cast + } + + // To guarantee that good suggestions given before continue + // to be given even after the fix. + #[allow(clippy::double_parens)] + fn issue_16449_still_lints() { + use self::issue_16449_support::*; + + const ONE: f64 = 1.0; + let one = 1.0_f64; + + let _ = 1.0_f64.pow_like(0.5); + //~^ unnecessary_cast + + let _ = 1.0_f64.pow_like(2); + //~^ unnecessary_cast + + let _ = 1.0_f64.powi(2).abs(); + //~^ unnecessary_cast + + let _ = ((Y + 2)).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) + 1.0_f64).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) + ONE).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) + one).abs(); + //~^ unnecessary_cast + } } fn issue16475() -> *const u8 { diff --git a/src/tools/clippy/tests/ui/unnecessary_cast.rs b/src/tools/clippy/tests/ui/unnecessary_cast.rs index 213b6bac3d2b..1a6cc831aa4b 100644 --- a/src/tools/clippy/tests/ui/unnecessary_cast.rs +++ b/src/tools/clippy/tests/ui/unnecessary_cast.rs @@ -284,6 +284,369 @@ fn issue_14640() { let _ = 5i32 as i64 as i64; //~^ unnecessary_cast } + + mod issue_16449_support { + use std::marker::PhantomData; + use std::ops::{Add, Mul}; + + pub trait PowLike { + type Output; + fn pow_like(self, rhs: Rhs) -> Self::Output; + } + + impl PowLike for f64 { + type Output = f64; + fn pow_like(self, rhs: f64) -> f64 { + self.powf(rhs) + } + } + + impl PowLike for f64 { + type Output = f64; + fn pow_like(self, _: i32) -> f64 { + self + } + } + + impl PowLike for f64 { + type Output = f32; + fn pow_like(self, _: u32) -> f32 { + self as f32 + } + } + + pub struct Mat(pub PhantomData); + + pub fn mat(_: &[[T; 1]; 1]) -> Mat { + Mat(PhantomData) + } + + pub struct Out(pub PhantomData); + + impl Out { + pub fn view(self) {} + } + + impl Out { + pub fn view(self) {} + } + + impl Mul<&Mat> for f64 { + type Output = Out; + + fn mul(self, _: &Mat) -> Self::Output { + Out(PhantomData) + } + } + + impl Mul<&Mat> for f32 { + type Output = Out; + + fn mul(self, _: &Mat) -> Self::Output { + Out(PhantomData) + } + } + + pub fn id(x: T) -> T { + x + } + + pub fn id_with(x: T, _: U) -> T { + x + } + + pub struct Wrap { + pub inner: T, + } + + pub fn wrap(inner: T) -> Wrap { + Wrap { inner } + } + + pub struct MethodWrap; + + impl MethodWrap { + pub fn id(&self, x: T) -> T { + x + } + + pub fn id_with(&self, x: T, _: U) -> T { + x + } + + pub fn wrap(&self, inner: T) -> Wrap { + Wrap { inner } + } + } + + pub struct X; + + impl Add for X { + type Output = f64; + fn add(self, _: i32) -> f64 { + 1.0 + } + } + + impl Add for X { + type Output = f32; + fn add(self, _: u32) -> f32 { + 1.0 + } + } + + pub struct Y; + + impl Add for Y { + type Output = f64; + fn add(self, _: i32) -> f64 { + 1.0 + } + } + + pub trait PowLikeSingleImpl { + type Output; + fn pow_like_single_impl(self, rhs: Rhs) -> Self::Output; + } + + impl PowLikeSingleImpl for f64 { + type Output = f64; + + fn pow_like_single_impl(self, _: i32) -> f64 { + self + } + } + } + + // Issue #16449: removing the cast still affects inference / impl selection, + // so these must not lint. + + // Minimal reproduction of the original issue. + fn issue_16449_minimal_original_reproduction() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (1.0_f64.pow_like(2) as f64 * &a).view(); + } + + // Wrappers that preserve the inference sensitive path. + fn issue_16449_struct_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + Wrap { + inner: 1.0_f64.pow_like(2) as f64 * &a, + } + .inner + .view(); + } + + fn issue_16449_free_identity_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + id(1.0_f64.pow_like(2) as f64 * &a).view(); + } + + fn issue_16449_method_identity_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + s.id(1.0_f64.pow_like(2) as f64 * &a).view(); + } + + fn issue_16449_free_wrap_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + wrap(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + } + + fn issue_16449_method_wrap_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + s.wrap(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + } + + fn issue_16449_block_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ({ 1.0_f64.pow_like(2) as f64 * &a }).view(); + } + + #[allow(clippy::if_same_then_else)] + fn issue_16449_if_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (if true { + 1.0_f64.pow_like(2) as f64 * &a + } else { + 1.0_f64.pow_like(2) as f64 * &a + }) + .view(); + } + + fn issue_16449_match_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (match 0 { + 0 => 1.0_f64.pow_like(2) as f64 * &a, + _ => 1.0_f64.pow_like(2) as f64 * &a, + }) + .view(); + } + + #[allow(clippy::let_and_return)] + fn issue_16449_let_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ({ + let x = 1.0_f64.pow_like(2) as f64 * &a; + x + }) + .view(); + } + + #[allow(clippy::never_loop)] + fn issue_16449_loop_wrapper() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + (loop { + break 1.0_f64.pow_like(2) as f64 * &a; + }) + .view(); + } + + #[allow(clippy::double_parens)] + fn issue_16449_operator_reproduction() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + ((X + 2) as f64 * &a).view(); + } + + // Placeholder generic arguments still leave inference active, + // so these must not lint. + fn issue_16449_placeholder_generics_do_not_lint() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + // placeholder call + id::<_>(1.0_f64.pow_like(2) as f64 * &a).view(); + // placeholder method call + s.id::<_>(1.0_f64.pow_like(2) as f64 * &a).view(); + // mixed placeholder call + id_with::<_, u8>(1.0_f64.pow_like(2) as f64 * &a, 0).view(); + // mixed placeholder method call + s.id_with::<_, u8>(1.0_f64.pow_like(2) as f64 * &a, 0).view(); + } + + // These look similar, but inference no longer depends on the cast, so they should lint. + + fn issue_16449_explicit_generics_still_lint() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + // explicit call + id::>(1.0_f64.pow_like(2) as f64 * &a).view(); + //~^ unnecessary_cast + + // explicit method call + s.id::>(1.0_f64.pow_like(2) as f64 * &a).view(); + //~^ unnecessary_cast + + // explicit free wrap + wrap::>(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + //~^ unnecessary_cast + + // explicit method wrap + s.wrap::>(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + //~^ unnecessary_cast + } + + // A nonprimitive method receiver alone should not suppress the lint. + fn issue_16449_nonprimitive_receiver_should_still_lint() { + use self::issue_16449_support::PowLikeSingleImpl; + struct Receiver; + + impl Receiver { + fn take(&self, x: f64) -> f64 { + x + } + } + + let receiver = Receiver; + let _ = receiver.take(1.0_f64.pow_like_single_impl(2) as f64).abs(); + //~^ unnecessary_cast + } + + fn issue_16449_wrapper_still_lints() { + use self::issue_16449_support::*; + + let a = mat(&[[1.0]]); + let s = MethodWrap; + + let _ = id(1.0_f64.powi(2) as f64).abs(); + //~^ unnecessary_cast + + let _ = wrap(1.0_f64.powi(2) as f64).inner.abs(); + //~^ unnecessary_cast + + let _ = s.id(1.0_f64.powi(2) as f64).abs(); + //~^ unnecessary_cast + + let _ = s.wrap(1.0_f64.powi(2) as f64).inner.abs(); + //~^ unnecessary_cast + + let _ = id(1.0_f64.powi(2) as f64 * &a); + //~^ unnecessary_cast + + let _ = s.id(1.0_f64.powi(2) as f64 * &a); + //~^ unnecessary_cast + } + + // To guarantee that good suggestions given before continue + // to be given even after the fix. + #[allow(clippy::double_parens)] + fn issue_16449_still_lints() { + use self::issue_16449_support::*; + + const ONE: f64 = 1.0; + let one = 1.0_f64; + + let _ = 1.0_f64.pow_like(0.5) as f64; + //~^ unnecessary_cast + + let _ = 1.0_f64.pow_like(2) as f64; + //~^ unnecessary_cast + + let _ = (1.0_f64.powi(2) as f64).abs(); + //~^ unnecessary_cast + + let _ = ((Y + 2) as f64).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) as f64 + 1.0_f64).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) as f64 + ONE).abs(); + //~^ unnecessary_cast + + let _ = (1.0_f64.pow_like_single_impl(2) as f64 + one).abs(); + //~^ unnecessary_cast + } } fn issue16475() -> *const u8 { diff --git a/src/tools/clippy/tests/ui/unnecessary_cast.stderr b/src/tools/clippy/tests/ui/unnecessary_cast.stderr index 14c14e583134..19d2afcb4f25 100644 --- a/src/tools/clippy/tests/ui/unnecessary_cast.stderr +++ b/src/tools/clippy/tests/ui/unnecessary_cast.stderr @@ -277,11 +277,119 @@ error: casting to the same type is unnecessary (`i64` -> `i64`) LL | let _ = 5i32 as i64 as i64; | ^^^^^^^^^^^^^^^^^^ help: try: `5i32 as i64` +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:563:24 + | +LL | id::>(1.0_f64.pow_like(2) as f64 * &a).view(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:567:26 + | +LL | s.id::>(1.0_f64.pow_like(2) as f64 * &a).view(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:571:26 + | +LL | wrap::>(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:575:28 + | +LL | s.wrap::>(1.0_f64.pow_like(2) as f64 * &a).inner.view(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:591:31 + | +LL | let _ = receiver.take(1.0_f64.pow_like_single_impl(2) as f64).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like_single_impl(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:601:20 + | +LL | let _ = id(1.0_f64.powi(2) as f64).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:604:22 + | +LL | let _ = wrap(1.0_f64.powi(2) as f64).inner.abs(); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:607:22 + | +LL | let _ = s.id(1.0_f64.powi(2) as f64).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:610:24 + | +LL | let _ = s.wrap(1.0_f64.powi(2) as f64).inner.abs(); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:613:20 + | +LL | let _ = id(1.0_f64.powi(2) as f64 * &a); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:616:22 + | +LL | let _ = s.id(1.0_f64.powi(2) as f64 * &a); + | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:629:17 + | +LL | let _ = 1.0_f64.pow_like(0.5) as f64; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(0.5)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:632:17 + | +LL | let _ = 1.0_f64.pow_like(2) as f64; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:635:17 + | +LL | let _ = (1.0_f64.powi(2) as f64).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.powi(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:638:17 + | +LL | let _ = ((Y + 2) as f64).abs(); + | ^^^^^^^^^^^^^^^^ help: try: `((Y + 2))` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:641:18 + | +LL | let _ = (1.0_f64.pow_like_single_impl(2) as f64 + 1.0_f64).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like_single_impl(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:644:18 + | +LL | let _ = (1.0_f64.pow_like_single_impl(2) as f64 + ONE).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like_single_impl(2)` + +error: casting to the same type is unnecessary (`f64` -> `f64`) + --> tests/ui/unnecessary_cast.rs:647:18 + | +LL | let _ = (1.0_f64.pow_like_single_impl(2) as f64 + one).abs(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `1.0_f64.pow_like_single_impl(2)` + error: casting raw pointers to the same type and constness is unnecessary (`*const *const u8` -> `*const *const u8`) - --> tests/ui/unnecessary_cast.rs:292:10 + --> tests/ui/unnecessary_cast.rs:655:10 | LL | *(&NONE as *const _ as *const _ as *const *const u8 as *const *const u8) | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: try: `(&NONE as *const _ as *const _ as *const *const u8)` -error: aborting due to 47 previous errors +error: aborting due to 65 previous errors diff --git a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.fixed b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.fixed index 32494435fff5..ff99e436c661 100644 --- a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.fixed +++ b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.fixed @@ -64,4 +64,30 @@ fn main() { let t = (0, 1, 2, 3); if let (0, _, ..) = t {}; } + + struct Struct4 { + a: u32, + b: u32, + c: u32, + d: u32, + } + + let fourval = Struct4 { + a: 5, + b: 10, + c: 15, + d: 20, + }; + + // unlike the tuple forms, the struct form can only have the `..` at the end of the list + let Struct4 { mut a, mut b, .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { mut b, .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { mut a, b, c, d: _ } = fourval; + let Struct4 { mut c, d, .. } = fourval; + let Struct4 { .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { .. } = fourval; + //~^ unneeded_wildcard_pattern } diff --git a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.rs b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.rs index b3a0fb6098d6..5913735d3b4b 100644 --- a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.rs +++ b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.rs @@ -64,4 +64,30 @@ fn main() { let t = (0, 1, 2, 3); if let (0, _, ..) = t {}; } + + struct Struct4 { + a: u32, + b: u32, + c: u32, + d: u32, + } + + let fourval = Struct4 { + a: 5, + b: 10, + c: 15, + d: 20, + }; + + // unlike the tuple forms, the struct form can only have the `..` at the end of the list + let Struct4 { mut a, mut b, c: _, .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { mut b, c: _, d: _, .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { mut a, b, c, d: _ } = fourval; + let Struct4 { mut c, d, .. } = fourval; + let Struct4 { b: _, c: _, .. } = fourval; + //~^ unneeded_wildcard_pattern + let Struct4 { c: _, .. } = fourval; + //~^ unneeded_wildcard_pattern } diff --git a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.stderr b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.stderr index 20666268a8ca..bfdceb53f7d4 100644 --- a/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.stderr +++ b/src/tools/clippy/tests/ui/unneeded_wildcard_pattern.stderr @@ -88,5 +88,29 @@ error: these patterns are unneeded as the `..` pattern can match those elements LL | if let S(0, .., _, _,) = s {}; | ^^^^^^ help: remove them -error: aborting due to 14 previous errors +error: this pattern is unneeded as the `..` pattern can match that element + --> tests/ui/unneeded_wildcard_pattern.rs:83:33 + | +LL | let Struct4 { mut a, mut b, c: _, .. } = fourval; + | ^^^^^^ help: remove it + +error: these patterns are unneeded as the `..` pattern can match those elements + --> tests/ui/unneeded_wildcard_pattern.rs:85:26 + | +LL | let Struct4 { mut b, c: _, d: _, .. } = fourval; + | ^^^^^^^^^^^^ help: remove them + +error: these patterns are unneeded as the `..` pattern can match those elements + --> tests/ui/unneeded_wildcard_pattern.rs:89:19 + | +LL | let Struct4 { b: _, c: _, .. } = fourval; + | ^^^^^^^^^^^^ help: remove them + +error: this pattern is unneeded as the `..` pattern can match that element + --> tests/ui/unneeded_wildcard_pattern.rs:91:19 + | +LL | let Struct4 { c: _, .. } = fourval; + | ^^^^^^ help: remove it + +error: aborting due to 18 previous errors diff --git a/src/tools/clippy/tests/ui/unsafe_removed_from_name.rs b/src/tools/clippy/tests/ui/unsafe_removed_from_name.rs index 2e1d8b60a0e2..f3d318815c10 100644 --- a/src/tools/clippy/tests/ui/unsafe_removed_from_name.rs +++ b/src/tools/clippy/tests/ui/unsafe_removed_from_name.rs @@ -22,6 +22,7 @@ mod mod_with_some_unsafe_things { pub struct Safe; pub struct Unsafe; + pub trait UnsafeTrait {} } use mod_with_some_unsafe_things::Unsafe as LieAboutModSafety; @@ -40,4 +41,10 @@ mod mod_with_some_unsafe_things { #[allow(clippy::unsafe_removed_from_name)] use mod_with_some_unsafe_things::Unsafe as SuperSafeThing; +// issue #16768, don't lint when "renaming" to '_' +use mod_with_some_unsafe_things::UnsafeTrait as _; + +use mod_with_some_unsafe_things::UnsafeTrait as FakeSafeTrait; +//~^ unsafe_removed_from_name + fn main() {} diff --git a/src/tools/clippy/tests/ui/unsafe_removed_from_name.stderr b/src/tools/clippy/tests/ui/unsafe_removed_from_name.stderr index 5268c16ec9ba..cd3c1f80a300 100644 --- a/src/tools/clippy/tests/ui/unsafe_removed_from_name.stderr +++ b/src/tools/clippy/tests/ui/unsafe_removed_from_name.stderr @@ -14,22 +14,28 @@ LL | use std::cell::UnsafeCell as TotallySafeCellAgain; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ error: removed `unsafe` from the name of `Unsafe` in use as `LieAboutModSafety` - --> tests/ui/unsafe_removed_from_name.rs:27:1 + --> tests/ui/unsafe_removed_from_name.rs:28:1 | LL | use mod_with_some_unsafe_things::Unsafe as LieAboutModSafety; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ error: removed `unsafe` from the name of `Unsafe` in use as `A` - --> tests/ui/unsafe_removed_from_name.rs:31:1 + --> tests/ui/unsafe_removed_from_name.rs:32:1 | LL | use mod_with_some_unsafe_things::{Unsafe as A, Unsafe as B}; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ error: removed `unsafe` from the name of `Unsafe` in use as `B` - --> tests/ui/unsafe_removed_from_name.rs:31:1 + --> tests/ui/unsafe_removed_from_name.rs:32:1 | LL | use mod_with_some_unsafe_things::{Unsafe as A, Unsafe as B}; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -error: aborting due to 5 previous errors +error: removed `unsafe` from the name of `UnsafeTrait` in use as `FakeSafeTrait` + --> tests/ui/unsafe_removed_from_name.rs:47:1 + | +LL | use mod_with_some_unsafe_things::UnsafeTrait as FakeSafeTrait; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 6 previous errors diff --git a/src/tools/clippy/tests/ui/unused_async.rs b/src/tools/clippy/tests/ui/unused_async.rs index 3f9244ab4970..b6780d240b17 100644 --- a/src/tools/clippy/tests/ui/unused_async.rs +++ b/src/tools/clippy/tests/ui/unused_async.rs @@ -134,3 +134,14 @@ async fn unimplemented_task() -> Result<(), String> { unimplemented!("Implement task"); } } + +mod issue16835 { + async fn todo_task(_arg: i32) { + todo!() + } + + async fn unimplemented_task(_arg: i32) { + let a = 1; + unimplemented!() + } +} diff --git a/src/tools/compiletest/src/common.rs b/src/tools/compiletest/src/common.rs index c167580d99d9..f73d7c96f7e8 100644 --- a/src/tools/compiletest/src/common.rs +++ b/src/tools/compiletest/src/common.rs @@ -603,6 +603,10 @@ pub(crate) struct Config { /// FIXME: this is *way* too coarse; the user can't select *which* info to verbosely dump. pub(crate) verbose: bool, + /// Whether to enable verbose subprocess output for run-make tests. + /// Set to false to suppress output for passing tests (e.g. for cg_clif with --no-capture). + pub verbose_run_make_subprocess_output: bool, + /// Where to find the remote test client process, if we're using it. /// /// Note: this is *only* used for target platform executables created by `run-make` test diff --git a/src/tools/compiletest/src/directives.rs b/src/tools/compiletest/src/directives.rs index 036495130f81..e2a84eb76d9e 100644 --- a/src/tools/compiletest/src/directives.rs +++ b/src/tools/compiletest/src/directives.rs @@ -185,8 +185,6 @@ pub(crate) struct TestProps { // If true, `rustfix` will only apply `MachineApplicable` suggestions. pub(crate) rustfix_only_machine_applicable: bool, pub(crate) assembly_output: Option, - // If true, the test is expected to ICE - pub(crate) should_ice: bool, // If true, the stderr is expected to be different across bit-widths. pub(crate) stderr_per_bitwidth: bool, // The MIR opt to unit test, if any @@ -220,7 +218,6 @@ mod directives { pub(crate) const COMPILE_FLAGS: &str = "compile-flags"; pub(crate) const RUN_FLAGS: &str = "run-flags"; pub(crate) const DOC_FLAGS: &str = "doc-flags"; - pub(crate) const SHOULD_ICE: &str = "should-ice"; pub(crate) const BUILD_AUX_DOCS: &str = "build-aux-docs"; pub(crate) const UNIQUE_DOC_OUT_DIR: &str = "unique-doc-out-dir"; pub(crate) const FORCE_HOST: &str = "force-host"; @@ -307,7 +304,6 @@ pub(crate) fn new() -> Self { run_rustfix: false, rustfix_only_machine_applicable: false, assembly_output: None, - should_ice: false, stderr_per_bitwidth: false, mir_unit_test: None, remap_src_base: false, @@ -377,10 +373,6 @@ fn load_from(&mut self, testfile: &Utf8Path, test_revision: Option<&str>, config ); } - if self.should_ice { - self.failure_status = Some(101); - } - if config.mode == TestMode::Incremental { self.incremental = true; } diff --git a/src/tools/compiletest/src/directives/directive_names.rs b/src/tools/compiletest/src/directives/directive_names.rs index 5421a9720173..34c6c1374b63 100644 --- a/src/tools/compiletest/src/directives/directive_names.rs +++ b/src/tools/compiletest/src/directives/directive_names.rs @@ -286,7 +286,6 @@ "rustc-env", "rustfix-only-machine-applicable", "should-fail", - "should-ice", "stderr-per-bitwidth", "test-mir-pass", "unique-doc-out-dir", diff --git a/src/tools/compiletest/src/directives/handlers.rs b/src/tools/compiletest/src/directives/handlers.rs index b53bda90f626..5e6d2d49d7dc 100644 --- a/src/tools/compiletest/src/directives/handlers.rs +++ b/src/tools/compiletest/src/directives/handlers.rs @@ -115,9 +115,6 @@ fn make_directive_handlers_map() -> HashMap<&'static str, Handler> { props.pp_exact = config.parse_pp_exact(ln); } }), - handler(SHOULD_ICE, |config, ln, props| { - config.set_name_directive(ln, SHOULD_ICE, &mut props.should_ice); - }), handler(BUILD_AUX_DOCS, |config, ln, props| { config.set_name_directive(ln, BUILD_AUX_DOCS, &mut props.build_aux_docs); }), diff --git a/src/tools/compiletest/src/lib.rs b/src/tools/compiletest/src/lib.rs index a23e3bb9a90e..dcea79b18e6a 100644 --- a/src/tools/compiletest/src/lib.rs +++ b/src/tools/compiletest/src/lib.rs @@ -134,6 +134,11 @@ fn parse_config(args: Vec) -> Config { ) .optflag("", "optimize-tests", "run tests with optimizations enabled") .optflag("", "verbose", "run tests verbosely, showing all output") + .optflag( + "", + "verbose-run-make-subprocess-output", + "show verbose subprocess output for successful run-make tests", + ) .optflag( "", "bless", @@ -471,6 +476,8 @@ fn opt_path(m: &getopts::Matches, nm: &str) -> Utf8PathBuf { adb_test_dir, adb_device_status, verbose: matches.opt_present("verbose"), + verbose_run_make_subprocess_output: matches + .opt_present("verbose-run-make-subprocess-output"), only_modified: matches.opt_present("only-modified"), remote_test_client: matches.opt_str("remote-test-client").map(Utf8PathBuf::from), compare_mode, diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs index 5fc3dbbfbc54..6b0ac39a357e 100644 --- a/src/tools/compiletest/src/runtest.rs +++ b/src/tools/compiletest/src/runtest.rs @@ -266,12 +266,6 @@ impl<'test> TestCx<'test> { /// Code executed for each revision in turn (or, if there are no /// revisions, exactly once, with revision == None). fn run_revision(&self) { - if self.props.should_ice - && self.config.mode != TestMode::Incremental - && self.config.mode != TestMode::Crashes - { - self.fatal("cannot use should-ice in a test that is not cfail"); - } // Run the test multiple times if requested. // This is useful for catching flaky tests under the parallel frontend. for _ in 0..self.config.iteration_count { @@ -452,6 +446,7 @@ fn print_source(&self, read_from: ReadFrom, pretty_type: &str) -> ProcRes { rustc .arg(input) .args(&["-Z", &format!("unpretty={}", pretty_type)]) + .arg("-Zunstable-options") .args(&["--target", &self.config.target]) .arg("-L") .arg(&aux_dir) @@ -557,6 +552,7 @@ fn typecheck_source(&self, src: String) -> ProcRes { rustc .arg("-") .arg("-Zno-codegen") + .arg("-Zunstable-options") .arg("--out-dir") .arg(&out_dir) .arg(&format!("--target={}", target)) @@ -670,16 +666,6 @@ fn check_regex_error_patterns( } } - fn check_no_compiler_crash(&self, proc_res: &ProcRes, should_ice: bool) { - match proc_res.status.code() { - Some(101) if !should_ice => { - self.fatal_proc_rec("compiler encountered internal error", proc_res) - } - None => self.fatal_proc_rec("compiler terminated by signal", proc_res), - _ => (), - } - } - fn check_forbid_output(&self, output_to_check: &str, proc_res: &ProcRes) { for pat in &self.props.forbid_output { if output_to_check.contains(pat) { @@ -993,6 +979,7 @@ fn compile_test_general( AllowUnused::No } } + TestMode::Incremental => AllowUnused::Yes, _ => AllowUnused::No, }; diff --git a/src/tools/compiletest/src/runtest/codegen_units.rs b/src/tools/compiletest/src/runtest/codegen_units.rs index 16c251c3c9e2..e4c924ed18a3 100644 --- a/src/tools/compiletest/src/runtest/codegen_units.rs +++ b/src/tools/compiletest/src/runtest/codegen_units.rs @@ -14,8 +14,6 @@ pub(super) fn run_codegen_units_test(&self) { self.fatal_proc_rec("compilation failed!", &proc_res); } - self.check_no_compiler_crash(&proc_res, self.props.should_ice); - const PREFIX: &str = "MONO_ITEM "; const CGU_MARKER: &str = "@@"; diff --git a/src/tools/compiletest/src/runtest/incremental.rs b/src/tools/compiletest/src/runtest/incremental.rs index 75e43006486e..47097c024246 100644 --- a/src/tools/compiletest/src/runtest/incremental.rs +++ b/src/tools/compiletest/src/runtest/incremental.rs @@ -1,5 +1,4 @@ -use super::{FailMode, TestCx, WillExecute}; -use crate::errors; +use super::{FailMode, ProcRes, TestCx, WillExecute}; impl TestCx<'_> { pub(super) fn run_incremental_test(&self) { @@ -33,14 +32,8 @@ pub(super) fn run_incremental_test(&self) { } if revision.starts_with("cpass") { - if self.props.should_ice { - self.fatal("can only use should-ice in cfail tests"); - } self.run_cpass_test(); } else if revision.starts_with("rpass") { - if self.props.should_ice { - self.fatal("can only use should-ice in cfail tests"); - } self.run_rpass_test(); } else if revision.starts_with("cfail") { self.run_cfail_test(); @@ -57,10 +50,7 @@ fn run_cpass_test(&self) { self.fatal_proc_rec("compilation failed!", &proc_res); } - // FIXME(#41968): Move this check to tidy? - if !errors::load_errors(&self.testpaths.file, self.revision).is_empty() { - self.fatal("build-pass tests with expected warnings should be moved to ui/"); - } + self.check_compiler_output_for_incr(&proc_res); } fn run_rpass_test(&self) { @@ -72,10 +62,7 @@ fn run_rpass_test(&self) { self.fatal_proc_rec("compilation failed!", &proc_res); } - // FIXME(#41968): Move this check to tidy? - if !errors::load_errors(&self.testpaths.file, self.revision).is_empty() { - self.fatal("run-pass tests with expected warnings should be moved to ui/"); - } + self.check_compiler_output_for_incr(&proc_res); if let WillExecute::Disabled = should_run { return; @@ -91,18 +78,13 @@ fn run_cfail_test(&self) { let pm = self.pass_mode(); let proc_res = self.compile_test(WillExecute::No, self.should_emit_metadata(pm)); self.check_if_test_should_compile(Some(FailMode::Build), pm, &proc_res); - self.check_no_compiler_crash(&proc_res, self.props.should_ice); + self.check_compiler_output_for_incr(&proc_res); + } - let output_to_check = self.get_output(&proc_res); + fn check_compiler_output_for_incr(&self, proc_res: &ProcRes) { + let output_to_check = self.get_output(proc_res); self.check_expected_errors(&proc_res); - self.check_all_error_patterns(&output_to_check, &proc_res); - if self.props.should_ice { - match proc_res.status.code() { - Some(101) => (), - _ => self.fatal("expected ICE"), - } - } - - self.check_forbid_output(&output_to_check, &proc_res); + self.check_all_error_patterns(&output_to_check, proc_res); + self.check_forbid_output(&output_to_check, proc_res); } } diff --git a/src/tools/compiletest/src/runtest/run_make.rs b/src/tools/compiletest/src/runtest/run_make.rs index ac8846a263c0..1044683ae642 100644 --- a/src/tools/compiletest/src/runtest/run_make.rs +++ b/src/tools/compiletest/src/runtest/run_make.rs @@ -231,6 +231,13 @@ pub(super) fn run_rmake_test(&self) { } // Guard against externally-set env vars. + // Set env var to enable verbose output for successful commands. + // Only set when --verbose-run-make-subprocess-output is passed. + cmd.env_remove("__RMAKE_VERBOSE_SUBPROCESS_OUTPUT"); + if self.config.verbose_run_make_subprocess_output { + cmd.env("__RMAKE_VERBOSE_SUBPROCESS_OUTPUT", "1"); + } + cmd.env_remove("__RUSTC_DEBUG_ASSERTIONS_ENABLED"); if self.config.with_rustc_debug_assertions { // Used for `run_make_support::env::rustc_debug_assertions_enabled`. diff --git a/src/tools/compiletest/src/rustdoc_gui_test.rs b/src/tools/compiletest/src/rustdoc_gui_test.rs index c71fd714aa66..57ce0c5a6d5f 100644 --- a/src/tools/compiletest/src/rustdoc_gui_test.rs +++ b/src/tools/compiletest/src/rustdoc_gui_test.rs @@ -109,6 +109,7 @@ fn incomplete_config_for_rustdoc_gui_test() -> Config { adb_test_dir: Default::default(), adb_device_status: Default::default(), verbose: Default::default(), + verbose_run_make_subprocess_output: Default::default(), remote_test_client: Default::default(), compare_mode: Default::default(), rustfix_coverage: Default::default(), diff --git a/src/tools/lint-docs/src/lib.rs b/src/tools/lint-docs/src/lib.rs index bc38e931fe51..f7d487333e32 100644 --- a/src/tools/lint-docs/src/lib.rs +++ b/src/tools/lint-docs/src/lib.rs @@ -332,7 +332,6 @@ fn generate_output_example(&self, lint: &mut Lint) -> Result<(), Box> if matches!( lint.name.as_str(), "unused_features" // broken lint - | "soft_unstable" // cannot have a stable example ) { return Ok(()); } diff --git a/src/tools/miri/src/bin/miri.rs b/src/tools/miri/src/bin/miri.rs index bb52bde6fe7b..273ac90068b0 100644 --- a/src/tools/miri/src/bin/miri.rs +++ b/src/tools/miri/src/bin/miri.rs @@ -7,7 +7,6 @@ )] // The rustc crates we need -extern crate rustc_abi; extern crate rustc_codegen_ssa; extern crate rustc_data_structures; extern crate rustc_driver; @@ -47,7 +46,6 @@ BacktraceStyle, BorrowTrackerMethod, GenmcConfig, GenmcCtx, MiriConfig, MiriEntryFnType, ProvenanceMode, TreeBorrowsParams, ValidationMode, run_genmc_mode, }; -use rustc_abi::ExternAbi; use rustc_codegen_ssa::traits::CodegenBackend; use rustc_data_structures::sync::{self, DynSync}; use rustc_driver::Compilation; @@ -98,12 +96,9 @@ fn entry_fn(tcx: TyCtxt<'_>) -> (DefId, MiriEntryFnType) { let start_def_id = id.expect_local(); let start_span = tcx.def_span(start_def_id); - let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig( + let expected_sig = ty::Binder::dummy(tcx.mk_fn_sig_safe_rust_abi( [tcx.types.isize, Ty::new_imm_ptr(tcx, Ty::new_imm_ptr(tcx, tcx.types.u8))], tcx.types.isize, - false, - hir::Safety::Safe, - ExternAbi::Rust, )); let correct_func_sig = check_function_signature( diff --git a/src/tools/miri/src/helpers.rs b/src/tools/miri/src/helpers.rs index a40ad4b55317..2a6520ffc2ba 100644 --- a/src/tools/miri/src/helpers.rs +++ b/src/tools/miri/src/helpers.rs @@ -6,14 +6,13 @@ use rand::RngCore; use rustc_abi::{Align, ExternAbi, FieldIdx, FieldsShape, Size, Variants}; use rustc_data_structures::fx::{FxBuildHasher, FxHashSet}; -use rustc_hir::Safety; use rustc_hir::def::{DefKind, Namespace}; use rustc_hir::def_id::{CRATE_DEF_INDEX, CrateNum, DefId, LOCAL_CRATE}; use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags; use rustc_middle::middle::dependency_format::Linkage; use rustc_middle::middle::exported_symbols::ExportedSymbol; use rustc_middle::ty::layout::{LayoutOf, MaybeResult, TyAndLayout}; -use rustc_middle::ty::{self, IntTy, Ty, TyCtxt, UintTy}; +use rustc_middle::ty::{self, FnSigKind, IntTy, Ty, TyCtxt, UintTy}; use rustc_session::config::CrateType; use rustc_span::{Span, Symbol}; use rustc_symbol_mangling::mangle_internal_symbol; @@ -408,9 +407,7 @@ fn call_function( let sig = this.tcx.mk_fn_sig( args.iter().map(|a| a.layout.ty), dest.layout.ty, - /*c_variadic*/ false, - Safety::Safe, - caller_abi, + FnSigKind::default().set_abi(caller_abi).set_safe(true), ); let caller_fn_abi = this.fn_abi_of_fn_ptr(ty::Binder::dummy(sig), ty::List::empty())?; diff --git a/src/tools/miri/src/shims/sig.rs b/src/tools/miri/src/shims/sig.rs index 43b913edbebf..ddfde35f47c4 100644 --- a/src/tools/miri/src/shims/sig.rs +++ b/src/tools/miri/src/shims/sig.rs @@ -1,8 +1,7 @@ //! Everything related to checking the signature of shim invocations. use rustc_abi::{CanonAbi, ExternAbi}; -use rustc_hir::Safety; -use rustc_middle::ty::{Binder, FnSig, Ty}; +use rustc_middle::ty::{Binder, FnSig, FnSigKind, Ty}; use rustc_span::Symbol; use rustc_target::callconv::FnAbi; @@ -275,10 +274,8 @@ fn check_shim_sig<'a, const N: usize>( inputs_and_output.push(shim_sig.ret); let fn_sig_binder = Binder::dummy(FnSig { inputs_and_output: this.machine.tcx.mk_type_list(&inputs_and_output), - c_variadic: false, - // This does not matter for the ABI. - safety: Safety::Safe, - abi: shim_sig.abi, + // Safety does not matter for the ABI. + fn_sig_kind: FnSigKind::default().set_abi(shim_sig.abi).set_safe(true), }); let callee_fn_abi = this.fn_abi_of_fn_ptr(fn_sig_binder, Default::default())?; diff --git a/src/tools/run-make-support/src/external_deps/rustc.rs b/src/tools/run-make-support/src/external_deps/rustc.rs index 2fa680a8e233..e8645e00e185 100644 --- a/src/tools/run-make-support/src/external_deps/rustc.rs +++ b/src/tools/run-make-support/src/external_deps/rustc.rs @@ -449,6 +449,16 @@ pub fn codegen_source_order(&mut self) -> &mut Self { self.cmd.arg("-Zcodegen-source-order"); self } + + /// Specify `-Z function-sections={yes, no}`. + pub fn function_sections(&mut self, enable: bool) -> &mut Self { + let flag = match enable { + true => "-Zfunction-sections=yes", + false => "-Zfunction-sections=no", + }; + self.cmd.arg(flag); + self + } } /// Query the sysroot path corresponding `rustc --print=sysroot`. diff --git a/src/tools/run-make-support/src/util.rs b/src/tools/run-make-support/src/util.rs index f44b3861d11d..93ec44d58d79 100644 --- a/src/tools/run-make-support/src/util.rs +++ b/src/tools/run-make-support/src/util.rs @@ -4,7 +4,7 @@ use crate::env::env_var; use crate::path_helpers::cwd; -pub(crate) fn verbose_print_command(cmd: &Command, output: &CompletedProcess) { +fn print_command_output(cmd: &Command, output: &CompletedProcess) { cmd.inspect(|std_cmd| { eprintln!("{std_cmd:?}"); }); @@ -16,6 +16,15 @@ pub(crate) fn verbose_print_command(cmd: &Command, output: &CompletedProcess) { } } +pub(crate) fn verbose_print_command(cmd: &Command, output: &CompletedProcess) { + // Only prints when `--verbose-run-make-subprocess-output` is active (env var set), + // so that passing tests don't flood the terminal when using `--no-capture`. + if std::env::var_os("__RMAKE_VERBOSE_SUBPROCESS_OUTPUT").is_none() { + return; + } + print_command_output(cmd, output); +} + /// If a given [`Command`] failed (as indicated by its [`CompletedProcess`]), verbose print the /// executed command, failure location, output status and stdout/stderr, and abort the process with /// exit code `1`. @@ -29,7 +38,7 @@ pub(crate) fn handle_failed_output( } else { eprintln!("command failed at line {caller_line_number}"); } - verbose_print_command(cmd, &output); + print_command_output(cmd, &output); std::process::exit(1) } diff --git a/src/tools/rust-analyzer/.github/workflows/gen-lints.yml b/src/tools/rust-analyzer/.github/workflows/gen-lints.yml new file mode 100644 index 000000000000..c978e3571c40 --- /dev/null +++ b/src/tools/rust-analyzer/.github/workflows/gen-lints.yml @@ -0,0 +1,44 @@ +name: Generate lints and feature flags + +on: + workflow_dispatch: + schedule: + - cron: '50 23 * * 6' + +defaults: + run: + shell: bash + +jobs: + lints-gen: + name: Generate lints + runs-on: ubuntu-latest + permissions: + pull-requests: write + steps: + - name: Checkout repository + uses: actions/checkout@v6 + + - name: Install nightly + run: rustup default nightly + + - name: Generate lints/feature flags + run: cargo codegen lint-definitions + + - uses: actions/create-github-app-token@f8d387b68d61c58ab83c6c016672934102569859 # v3.0.0 + id: app-token + with: + app-id: ${{ vars.APP_CLIENT_ID }} + private-key: ${{ secrets.APP_PRIVATE_KEY }} + + - name: Submit PR + uses: peter-evans/create-pull-request@c0f553fe549906ede9cf27b5156039d195d2ece0 # v8.1.0 + with: + token: ${{ steps.app-token.outputs.token }} + commit-message: "internal: update generated lints" + branch: "ci/gen-lints" + delete-branch: true + sign-commits: true + title: "Update generated lints" + body: "Weekly lint updates for `crates/ide-db/src/generated/lints.rs`." + labels: "A-infra" diff --git a/src/tools/rust-analyzer/.github/workflows/release.yaml b/src/tools/rust-analyzer/.github/workflows/release.yaml index b35614f91b2d..ef61e397fcfa 100644 --- a/src/tools/rust-analyzer/.github/workflows/release.yaml +++ b/src/tools/rust-analyzer/.github/workflows/release.yaml @@ -264,8 +264,6 @@ jobs: name: ${{ env.TAG }} token: ${{ secrets.GITHUB_TOKEN }} - - run: rm dist/rust-analyzer-no-server.vsix - - run: npm ci working-directory: ./editors/code diff --git a/src/tools/rust-analyzer/.github/workflows/rustc-pull.yml b/src/tools/rust-analyzer/.github/workflows/rustc-pull.yml index 37cf5f3726b2..be3362b79bbf 100644 --- a/src/tools/rust-analyzer/.github/workflows/rustc-pull.yml +++ b/src/tools/rust-analyzer/.github/workflows/rustc-pull.yml @@ -12,6 +12,7 @@ jobs: uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main with: github-app-id: ${{ vars.APP_CLIENT_ID }} + pr-author: "workflows-rust-analyzer[bot]" zulip-stream-id: 185405 zulip-bot-email: "rust-analyzer-ci-bot@rust-lang.zulipchat.com" pr-base-branch: master diff --git a/src/tools/rust-analyzer/Cargo.lock b/src/tools/rust-analyzer/Cargo.lock index 5370127ddc8e..da530b3a9304 100644 --- a/src/tools/rust-analyzer/Cargo.lock +++ b/src/tools/rust-analyzer/Cargo.lock @@ -234,7 +234,6 @@ dependencies = [ "intern", "oorandom", "rustc-hash 2.1.1", - "span", "syntax", "syntax-bridge", "tracing", @@ -846,7 +845,6 @@ dependencies = [ name = "hir-expand" version = "0.0.0" dependencies = [ - "arrayvec", "base-db", "cfg", "cov-mark", @@ -1731,9 +1729,9 @@ checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220" [[package]] name = "perf-event" -version = "0.4.7" +version = "0.4.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5396562cd2eaa828445d6d34258ae21ee1eb9d40fe626ca7f51c8dccb4af9d66" +checksum = "b4d6393d9238342159080d79b78cb59c67399a8e7ecfa5d410bd614169e4e823" dependencies = [ "libc", "perf-event-open-sys", @@ -1741,9 +1739,9 @@ dependencies = [ [[package]] name = "perf-event-open-sys" -version = "1.0.1" +version = "4.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ce9bedf5da2c234fdf2391ede2b90fabf585355f33100689bc364a3ea558561a" +checksum = "7c44fb1c7651a45a3652c4afc6e754e40b3d6e6556f1487e2b230bfc4f33c2a8" dependencies = [ "libc", ] @@ -2283,9 +2281,9 @@ checksum = "7a2d987857b319362043e95f5353c0535c1f58eec5336fdfcf626430af7def58" [[package]] name = "rowan" -version = "0.15.17" +version = "0.15.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d4f1e4a001f863f41ea8d0e6a0c34b356d5b733db50dadab3efef640bafb779b" +checksum = "62f509095fc8cc0c8c8564016771d458079c11a8d857e65861f045145c0d3208" dependencies = [ "countme", "hashbrown 0.14.5", @@ -2733,6 +2731,7 @@ dependencies = [ "rustc-hash 2.1.1", "rustc-literal-escaper 0.0.4", "rustc_apfloat", + "smallvec", "smol_str 0.3.2", "stdx", "test-utils", diff --git a/src/tools/rust-analyzer/Cargo.toml b/src/tools/rust-analyzer/Cargo.toml index 9f31e1903af5..3b3929df0dfb 100644 --- a/src/tools/rust-analyzer/Cargo.toml +++ b/src/tools/rust-analyzer/Cargo.toml @@ -132,7 +132,7 @@ process-wrap = { version = "8.2.1", features = ["std"] } pulldown-cmark-to-cmark = "10.0.4" pulldown-cmark = { version = "0.9.6", default-features = false } rayon = "1.10.0" -rowan = "=0.15.17" +rowan = "=0.15.18" # Ideally we'd not enable the macros feature but unfortunately the `tracked` attribute does not work # on impls without it salsa = { version = "0.25.2", default-features = false, features = [ diff --git a/src/tools/rust-analyzer/crates/base-db/src/change.rs b/src/tools/rust-analyzer/crates/base-db/src/change.rs index c728f3e5ca83..4d4bf78cbc0b 100644 --- a/src/tools/rust-analyzer/crates/base-db/src/change.rs +++ b/src/tools/rust-analyzer/crates/base-db/src/change.rs @@ -9,7 +9,8 @@ use vfs::FileId; use crate::{ - CrateGraphBuilder, CratesIdMap, LibraryRoots, LocalRoots, RootQueryDb, SourceRoot, SourceRootId, + CrateGraphBuilder, CratesIdMap, LibraryRoots, LocalRoots, SourceDatabase, SourceRoot, + SourceRootId, }; /// Encapsulate a bunch of raw `.set` calls on the database. @@ -49,7 +50,7 @@ pub fn set_crate_graph(&mut self, graph: CrateGraphBuilder) { self.crate_graph = Some(graph); } - pub fn apply(self, db: &mut dyn RootQueryDb) -> Option { + pub fn apply(self, db: &mut dyn SourceDatabase) -> Option { let _p = tracing::info_span!("FileChange::apply").entered(); if let Some(roots) = self.roots { let mut local_roots = FxHashSet::default(); diff --git a/src/tools/rust-analyzer/crates/base-db/src/editioned_file_id.rs b/src/tools/rust-analyzer/crates/base-db/src/editioned_file_id.rs index 8721f3a0ff3b..a77b45f8ae68 100644 --- a/src/tools/rust-analyzer/crates/base-db/src/editioned_file_id.rs +++ b/src/tools/rust-analyzer/crates/base-db/src/editioned_file_id.rs @@ -5,14 +5,71 @@ use salsa::Database; use span::Edition; +use syntax::{SyntaxError, ast}; use vfs::FileId; +use crate::SourceDatabase; + #[salsa::interned(debug, constructor = from_span_file_id, no_lifetime)] #[derive(PartialOrd, Ord)] pub struct EditionedFileId { field: span::EditionedFileId, } +// Currently does not work due to a salsa bug +// #[salsa::tracked] +// impl EditionedFileId { +// #[salsa::tracked(lru = 128)] +// pub fn parse(self, db: &dyn SourceDatabase) -> syntax::Parse { +// let _p = tracing::info_span!("parse", ?self).entered(); +// let (file_id, edition) = self.unpack(db); +// let text = db.file_text(file_id).text(db); +// ast::SourceFile::parse(text, edition) +// } + +// // firewall query +// #[salsa::tracked(returns(as_deref))] +// pub fn parse_errors(self, db: &dyn SourceDatabase) -> Option> { +// let errors = self.parse(db).errors(); +// match &*errors { +// [] => None, +// [..] => Some(errors.into()), +// } +// } +// } + +impl EditionedFileId { + pub fn parse(self, db: &dyn SourceDatabase) -> syntax::Parse { + #[salsa::tracked(lru = 128)] + pub fn parse( + db: &dyn SourceDatabase, + file_id: EditionedFileId, + ) -> syntax::Parse { + let _p = tracing::info_span!("parse", ?file_id).entered(); + let (file_id, edition) = file_id.unpack(db); + let text = db.file_text(file_id).text(db); + ast::SourceFile::parse(text, edition) + } + parse(db, self) + } + + // firewall query + pub fn parse_errors(self, db: &dyn SourceDatabase) -> Option<&[SyntaxError]> { + #[salsa::tracked(returns(as_deref))] + pub fn parse_errors( + db: &dyn SourceDatabase, + file_id: EditionedFileId, + ) -> Option> { + let errors = file_id.parse(db).errors(); + match &*errors { + [] => None, + [..] => Some(errors.into()), + } + } + parse_errors(db, self) + } +} + impl EditionedFileId { #[inline] pub fn new(db: &dyn Database, file_id: FileId, edition: Edition) -> Self { diff --git a/src/tools/rust-analyzer/crates/base-db/src/input.rs b/src/tools/rust-analyzer/crates/base-db/src/input.rs index 246c57edc2df..38f9c5a5a14c 100644 --- a/src/tools/rust-analyzer/crates/base-db/src/input.rs +++ b/src/tools/rust-analyzer/crates/base-db/src/input.rs @@ -21,7 +21,10 @@ use triomphe::Arc; use vfs::{AbsPathBuf, AnchoredPath, FileId, VfsPath, file_set::FileSet}; -use crate::{CrateWorkspaceData, EditionedFileId, FxIndexSet, RootQueryDb}; +use crate::{ + CrateWorkspaceData, EditionedFileId, FxIndexSet, SourceDatabase, all_crates, + set_all_crates_with_durability, +}; pub type ProcMacroPaths = FxHashMap>; @@ -490,13 +493,13 @@ pub fn transitive_deps(self, db: &dyn salsa::Database) -> Vec { /// including the crate itself. /// /// **Warning**: do not use this query in `hir-*` crates! It kills incrementality across crate metadata modifications. - pub fn transitive_rev_deps(self, db: &dyn RootQueryDb) -> Box<[Crate]> { + pub fn transitive_rev_deps(self, db: &dyn SourceDatabase) -> Box<[Crate]> { let mut worklist = vec![self]; let mut rev_deps = FxHashSet::default(); rev_deps.insert(self); let mut inverted_graph = FxHashMap::<_, Vec<_>>::default(); - db.all_crates().iter().for_each(|&krate| { + all_crates(db).iter().for_each(|&krate| { krate .data(db) .dependencies @@ -586,15 +589,15 @@ pub fn add_dep( Ok(()) } - pub fn set_in_db(self, db: &mut dyn RootQueryDb) -> CratesIdMap { + pub fn set_in_db(self, db: &mut dyn SourceDatabase) -> CratesIdMap { + let old_all_crates = all_crates(db); + // For some reason in some repositories we have duplicate crates, so we use a set and not `Vec`. // We use an `IndexSet` because the list needs to be topologically sorted. let mut all_crates = FxIndexSet::with_capacity_and_hasher(self.arena.len(), FxBuildHasher); let mut visited = FxHashMap::default(); let mut visited_root_files = FxHashSet::default(); - let old_all_crates = db.all_crates(); - let crates_map = db.crates_map(); // salsa doesn't compare new input to old input to see if they are the same, so here we are doing all the work ourselves. for krate in self.iter() { @@ -612,17 +615,14 @@ pub fn set_in_db(self, db: &mut dyn RootQueryDb) -> CratesIdMap { if old_all_crates.len() != all_crates.len() || old_all_crates.iter().any(|&krate| !all_crates.contains(&krate)) { - db.set_all_crates_with_durability( - Arc::new(Vec::from_iter(all_crates).into_boxed_slice()), - Durability::MEDIUM, - ); + set_all_crates_with_durability(db, all_crates, Durability::MEDIUM); } return visited; fn go( graph: &CrateGraphBuilder, - db: &mut dyn RootQueryDb, + db: &mut dyn SourceDatabase, crates_map: &CratesMap, visited: &mut FxHashMap, visited_root_files: &mut FxHashSet, @@ -929,6 +929,27 @@ fn into_iter(self) -> Self::IntoIter { } } +/// The crate graph had a cycle. This is typically a bug, and +/// rust-analyzer logs a warning when it encounters a cycle. Generally +/// rust-analyzer will continue working OK in the presence of cycle, +/// but it's better to have an accurate crate graph. +/// +/// ## dev-dependencies +/// +/// Note that it's actually legal for a cargo package (i.e. a thing +/// with a Cargo.toml) to depend on itself in dev-dependencies. This +/// can enable additional features, and is typically used when a +/// project wants features to be enabled in tests. Dev-dependencies +/// are not propagated, so they aren't visible to package that depend +/// on this one. +/// +/// +/// +/// However, rust-analyzer constructs its crate graph from Cargo +/// metadata, so it can end up producing a cyclic crate graph from a +/// well-formed package graph. +/// +/// #[derive(Debug)] pub struct CyclicDependenciesError { path: Vec<(CrateBuilderId, Option)>, diff --git a/src/tools/rust-analyzer/crates/base-db/src/lib.rs b/src/tools/rust-analyzer/crates/base-db/src/lib.rs index 5baf4ce6f907..e438505c07e4 100644 --- a/src/tools/rust-analyzer/crates/base-db/src/lib.rs +++ b/src/tools/rust-analyzer/crates/base-db/src/lib.rs @@ -36,7 +36,6 @@ use rustc_hash::{FxHashSet, FxHasher}; use salsa::{Durability, Setter}; pub use semver::{BuildMetadata, Prerelease, Version, VersionReq}; -use syntax::{Parse, SyntaxError, ast}; use triomphe::Arc; pub use vfs::{AnchoredPath, AnchoredPathBuf, FileId, VfsPath, file_set::FileSet}; @@ -236,36 +235,6 @@ pub struct SourceRootInput { pub source_root: Arc, } -/// Database which stores all significant input facts: source code and project -/// model. Everything else in rust-analyzer is derived from these queries. -#[query_group::query_group] -pub trait RootQueryDb: SourceDatabase + salsa::Database { - /// Parses the file into the syntax tree. - #[salsa::invoke(parse)] - #[salsa::lru(128)] - fn parse(&self, file_id: EditionedFileId) -> Parse; - - /// Returns the set of errors obtained from parsing the file including validation errors. - #[salsa::transparent] - fn parse_errors(&self, file_id: EditionedFileId) -> Option<&[SyntaxError]>; - - #[salsa::transparent] - fn toolchain_channel(&self, krate: Crate) -> Option; - - /// Crates whose root file is in `id`. - #[salsa::invoke_interned(source_root_crates)] - fn source_root_crates(&self, id: SourceRootId) -> Arc<[Crate]>; - - #[salsa::transparent] - fn relevant_crates(&self, file_id: FileId) -> Arc<[Crate]>; - - /// Returns the crates in topological order. - /// - /// **Warning**: do not use this query in `hir-*` crates! It kills incrementality across crate metadata modifications. - #[salsa::input] - fn all_crates(&self) -> Arc>; -} - #[salsa_macros::db] pub trait SourceDatabase: salsa::Database { /// Text of the file. @@ -353,46 +322,67 @@ pub fn is_atleast_187(&self) -> bool { } } -fn toolchain_channel(db: &dyn RootQueryDb, krate: Crate) -> Option { +pub fn toolchain_channel(db: &dyn salsa::Database, krate: Crate) -> Option { krate.workspace_data(db).toolchain.as_ref().and_then(|v| ReleaseChannel::from_str(&v.pre)) } -fn parse(db: &dyn RootQueryDb, file_id: EditionedFileId) -> Parse { - let _p = tracing::info_span!("parse", ?file_id).entered(); - let (file_id, edition) = file_id.unpack(db.as_dyn_database()); - let text = db.file_text(file_id).text(db); - ast::SourceFile::parse(text, edition) +#[salsa::input(singleton, debug)] +struct AllCrates { + crates: std::sync::Arc<[Crate]>, } -fn parse_errors(db: &dyn RootQueryDb, file_id: EditionedFileId) -> Option<&[SyntaxError]> { - #[salsa_macros::tracked(returns(ref))] - fn parse_errors(db: &dyn RootQueryDb, file_id: EditionedFileId) -> Option> { - let errors = db.parse(file_id).errors(); - match &*errors { - [] => None, - [..] => Some(errors.into()), - } +pub fn set_all_crates_with_durability( + db: &mut dyn salsa::Database, + crates: impl IntoIterator, + durability: Durability, +) { + AllCrates::try_get(db) + .unwrap_or_else(|| AllCrates::new(db, std::sync::Arc::default())) + .set_crates(db) + .with_durability(durability) + .to(crates.into_iter().collect()); +} + +/// Returns the crates in topological order. +/// +/// **Warning**: do not use this query in `hir-*` crates! It kills incrementality across crate metadata modifications. +pub fn all_crates(db: &dyn salsa::Database) -> std::sync::Arc<[Crate]> { + AllCrates::try_get(db).map_or(std::sync::Arc::default(), |all_crates| all_crates.crates(db)) +} + +// FIXME: VFS rewrite should allow us to get rid of this wrapper +#[doc(hidden)] +#[salsa::interned] +pub struct InternedSourceRootId { + pub id: SourceRootId, +} + +/// Crates whose root file is in `id`. +pub fn source_root_crates(db: &dyn SourceDatabase, id: SourceRootId) -> &[Crate] { + #[salsa::tracked(returns(deref))] + pub fn source_root_crates<'db>( + db: &'db dyn SourceDatabase, + id: InternedSourceRootId<'db>, + ) -> Box<[Crate]> { + let crates = AllCrates::get(db).crates(db); + let id = id.id(db); + crates + .iter() + .copied() + .filter(|&krate| { + let root_file = krate.data(db).root_file_id; + db.file_source_root(root_file).source_root_id(db) == id + }) + .collect() } - parse_errors(db, file_id).as_ref().map(|it| &**it) + source_root_crates(db, InternedSourceRootId::new(db, id)) } -fn source_root_crates(db: &dyn RootQueryDb, id: SourceRootId) -> Arc<[Crate]> { - let crates = db.all_crates(); - crates - .iter() - .copied() - .filter(|&krate| { - let root_file = krate.data(db).root_file_id; - db.file_source_root(root_file).source_root_id(db) == id - }) - .collect() -} - -fn relevant_crates(db: &dyn RootQueryDb, file_id: FileId) -> Arc<[Crate]> { +pub fn relevant_crates(db: &dyn SourceDatabase, file_id: FileId) -> &[Crate] { let _p = tracing::info_span!("relevant_crates").entered(); let source_root = db.file_source_root(file_id); - db.source_root_crates(source_root.source_root_id(db)) + source_root_crates(db, source_root.source_root_id(db)) } #[must_use] diff --git a/src/tools/rust-analyzer/crates/cfg/Cargo.toml b/src/tools/rust-analyzer/crates/cfg/Cargo.toml index cf2a7607b019..15de1f329385 100644 --- a/src/tools/rust-analyzer/crates/cfg/Cargo.toml +++ b/src/tools/rust-analyzer/crates/cfg/Cargo.toml @@ -19,7 +19,6 @@ tracing.workspace = true # locals deps tt = { workspace = true, optional = true } syntax = { workspace = true, optional = true } -span = { path = "../span", version = "0.0", optional = true } intern.workspace = true [dev-dependencies] @@ -36,7 +35,7 @@ cfg = { path = ".", default-features = false, features = ["tt"] } [features] default = [] -syntax = ["dep:syntax", "dep:span"] +syntax = ["dep:syntax"] tt = ["dep:tt"] in-rust-tree = [] diff --git a/src/tools/rust-analyzer/crates/cfg/src/cfg_expr.rs b/src/tools/rust-analyzer/crates/cfg/src/cfg_expr.rs index d253f6f492c7..7af3ed5dc9a6 100644 --- a/src/tools/rust-analyzer/crates/cfg/src/cfg_expr.rs +++ b/src/tools/rust-analyzer/crates/cfg/src/cfg_expr.rs @@ -106,10 +106,54 @@ pub fn parse_from_iter(tt: &mut tt::iter::TtIter<'_>) -> CfgExpr { } #[cfg(feature = "syntax")] - pub fn parse_from_ast( - ast: &mut std::iter::Peekable, - ) -> CfgExpr { - next_cfg_expr_from_ast(ast).unwrap_or(CfgExpr::Invalid) + pub fn parse_from_ast(ast: syntax::ast::CfgPredicate) -> CfgExpr { + use intern::sym; + use syntax::ast::{self, AstToken}; + + match ast { + ast::CfgPredicate::CfgAtom(atom) => { + let atom = match atom.key() { + Some(ast::CfgAtomKey::True) => CfgAtom::Flag(sym::true_), + Some(ast::CfgAtomKey::False) => CfgAtom::Flag(sym::false_), + Some(ast::CfgAtomKey::Ident(key)) => { + let key = Symbol::intern(key.text()); + match atom.string_token().and_then(ast::String::cast) { + Some(value) => { + if let Ok(value) = value.value() { + CfgAtom::KeyValue { key, value: Symbol::intern(&value) } + } else { + return CfgExpr::Invalid; + } + } + None => CfgAtom::Flag(key), + } + } + None => return CfgExpr::Invalid, + }; + CfgExpr::Atom(atom) + } + ast::CfgPredicate::CfgComposite(composite) => { + let Some(keyword) = composite.keyword() else { + return CfgExpr::Invalid; + }; + match keyword.text() { + "all" => CfgExpr::All( + composite.cfg_predicates().map(CfgExpr::parse_from_ast).collect(), + ), + "any" => CfgExpr::Any( + composite.cfg_predicates().map(CfgExpr::parse_from_ast).collect(), + ), + "not" => { + let mut inner = composite.cfg_predicates(); + let (Some(inner), None) = (inner.next(), inner.next()) else { + return CfgExpr::Invalid; + }; + CfgExpr::Not(Box::new(CfgExpr::parse_from_ast(inner))) + } + _ => CfgExpr::Invalid, + } + } + } } /// Fold the cfg by querying all basic `Atom` and `KeyValue` predicates. @@ -128,65 +172,6 @@ pub fn fold(&self, query: &dyn Fn(&CfgAtom) -> bool) -> Option { } } -#[cfg(feature = "syntax")] -fn next_cfg_expr_from_ast( - it: &mut std::iter::Peekable, -) -> Option { - use intern::sym; - use syntax::{NodeOrToken, SyntaxKind, T, ast}; - - let name = match it.next() { - None => return None, - Some(NodeOrToken::Token(ident)) if ident.kind().is_any_identifier() => { - Symbol::intern(ident.text()) - } - Some(_) => return Some(CfgExpr::Invalid), - }; - - let ret = match it.peek() { - Some(NodeOrToken::Token(eq)) if eq.kind() == T![=] => { - it.next(); - if let Some(NodeOrToken::Token(literal)) = it.peek() - && matches!(literal.kind(), SyntaxKind::STRING) - { - let dummy_span = span::Span { - range: span::TextRange::empty(span::TextSize::new(0)), - anchor: span::SpanAnchor { - file_id: span::EditionedFileId::from_raw(0), - ast_id: span::FIXUP_ERASED_FILE_AST_ID_MARKER, - }, - ctx: span::SyntaxContext::root(span::Edition::Edition2015), - }; - let literal = - Symbol::intern(tt::token_to_literal(literal.text(), dummy_span).text()); - it.next(); - CfgAtom::KeyValue { key: name, value: literal.clone() }.into() - } else { - return Some(CfgExpr::Invalid); - } - } - Some(NodeOrToken::Node(subtree)) => { - let mut subtree_iter = ast::TokenTreeChildren::new(subtree).peekable(); - it.next(); - let mut subs = std::iter::from_fn(|| next_cfg_expr_from_ast(&mut subtree_iter)); - match name { - s if s == sym::all => CfgExpr::All(subs.collect()), - s if s == sym::any => CfgExpr::Any(subs.collect()), - s if s == sym::not => { - CfgExpr::Not(Box::new(subs.next().unwrap_or(CfgExpr::Invalid))) - } - _ => CfgExpr::Invalid, - } - } - _ => CfgAtom::Flag(name).into(), - }; - - // Eat comma separator - while it.next().is_some_and(|it| it.as_token().is_none_or(|it| it.kind() != T![,])) {} - - Some(ret) -} - #[cfg(feature = "tt")] fn next_cfg_expr(it: &mut tt::iter::TtIter<'_>) -> Option { use intern::sym; diff --git a/src/tools/rust-analyzer/crates/cfg/src/tests.rs b/src/tools/rust-analyzer/crates/cfg/src/tests.rs index 52c581dbbd3a..bfc9220a05d9 100644 --- a/src/tools/rust-analyzer/crates/cfg/src/tests.rs +++ b/src/tools/rust-analyzer/crates/cfg/src/tests.rs @@ -1,10 +1,7 @@ use arbitrary::{Arbitrary, Unstructured}; use expect_test::{Expect, expect}; use intern::Symbol; -use syntax::{ - AstNode, Edition, - ast::{self, TokenTreeChildren}, -}; +use syntax::{AstNode, Edition, ast}; use syntax_bridge::{ DocCommentDesugarMode, dummy_test_span_utils::{DUMMY, DummyTestSpanMap}, @@ -14,32 +11,32 @@ use crate::{CfgAtom, CfgExpr, CfgOptions, DnfExpr}; #[track_caller] -fn parse_ast_cfg(tt: &ast::TokenTree) -> CfgExpr { - CfgExpr::parse_from_ast(&mut TokenTreeChildren::new(tt).peekable()) +fn parse_ast_cfg(pred: ast::CfgPredicate) -> CfgExpr { + CfgExpr::parse_from_ast(pred) } #[track_caller] fn assert_parse_result(input: &str, expected: CfgExpr) { - let source_file = ast::SourceFile::parse(input, Edition::CURRENT).ok().unwrap(); - let tt_ast = source_file.syntax().descendants().find_map(ast::TokenTree::cast).unwrap(); + let source_file = ast::SourceFile::parse(input, Edition::CURRENT).syntax_node(); + let pred_ast = source_file.descendants().find_map(ast::CfgPredicate::cast).unwrap(); let tt = syntax_node_to_token_tree( - tt_ast.syntax(), + pred_ast.syntax(), DummyTestSpanMap, DUMMY, DocCommentDesugarMode::ProcMacro, ); let cfg = CfgExpr::parse(&tt); assert_eq!(cfg, expected); - let cfg = parse_ast_cfg(&tt_ast); + let cfg = parse_ast_cfg(pred_ast); assert_eq!(cfg, expected); } #[track_caller] fn check_dnf(input: &str, expect: Expect) { let source_file = ast::SourceFile::parse(input, Edition::CURRENT).ok().unwrap(); - let tt_ast = source_file.syntax().descendants().find_map(ast::TokenTree::cast).unwrap(); + let pred_ast = source_file.syntax().descendants().find_map(ast::CfgPredicate::cast).unwrap(); let tt = syntax_node_to_token_tree( - tt_ast.syntax(), + pred_ast.syntax(), DummyTestSpanMap, DUMMY, DocCommentDesugarMode::ProcMacro, @@ -47,7 +44,7 @@ fn check_dnf(input: &str, expect: Expect) { let cfg = CfgExpr::parse(&tt); let actual = format!("#![cfg({})]", DnfExpr::new(&cfg)); expect.assert_eq(&actual); - let cfg = parse_ast_cfg(&tt_ast); + let cfg = parse_ast_cfg(pred_ast); let actual = format!("#![cfg({})]", DnfExpr::new(&cfg)); expect.assert_eq(&actual); } @@ -55,9 +52,9 @@ fn check_dnf(input: &str, expect: Expect) { #[track_caller] fn check_why_inactive(input: &str, opts: &CfgOptions, expect: Expect) { let source_file = ast::SourceFile::parse(input, Edition::CURRENT).ok().unwrap(); - let tt_ast = source_file.syntax().descendants().find_map(ast::TokenTree::cast).unwrap(); + let pred_ast = source_file.syntax().descendants().find_map(ast::CfgPredicate::cast).unwrap(); let tt = syntax_node_to_token_tree( - tt_ast.syntax(), + pred_ast.syntax(), DummyTestSpanMap, DUMMY, DocCommentDesugarMode::ProcMacro, @@ -66,7 +63,7 @@ fn check_why_inactive(input: &str, opts: &CfgOptions, expect: Expect) { let dnf = DnfExpr::new(&cfg); let why_inactive = dnf.why_inactive(opts).unwrap().to_string(); expect.assert_eq(&why_inactive); - let cfg = parse_ast_cfg(&tt_ast); + let cfg = parse_ast_cfg(pred_ast); let dnf = DnfExpr::new(&cfg); let why_inactive = dnf.why_inactive(opts).unwrap().to_string(); expect.assert_eq(&why_inactive); @@ -75,9 +72,9 @@ fn check_why_inactive(input: &str, opts: &CfgOptions, expect: Expect) { #[track_caller] fn check_enable_hints(input: &str, opts: &CfgOptions, expected_hints: &[&str]) { let source_file = ast::SourceFile::parse(input, Edition::CURRENT).ok().unwrap(); - let tt_ast = source_file.syntax().descendants().find_map(ast::TokenTree::cast).unwrap(); + let pred_ast = source_file.syntax().descendants().find_map(ast::CfgPredicate::cast).unwrap(); let tt = syntax_node_to_token_tree( - tt_ast.syntax(), + pred_ast.syntax(), DummyTestSpanMap, DUMMY, DocCommentDesugarMode::ProcMacro, @@ -86,7 +83,7 @@ fn check_enable_hints(input: &str, opts: &CfgOptions, expected_hints: &[&str]) { let dnf = DnfExpr::new(&cfg); let hints = dnf.compute_enable_hints(opts).map(|diff| diff.to_string()).collect::>(); assert_eq!(hints, expected_hints); - let cfg = parse_ast_cfg(&tt_ast); + let cfg = parse_ast_cfg(pred_ast); let dnf = DnfExpr::new(&cfg); let hints = dnf.compute_enable_hints(opts).map(|diff| diff.to_string()).collect::>(); assert_eq!(hints, expected_hints); @@ -119,20 +116,6 @@ fn test_cfg_expr_parser() { .into_boxed_slice(), ), ); - - assert_parse_result( - r#"#![cfg(any(not(), all(), , bar = "baz",))]"#, - CfgExpr::Any( - vec![ - CfgExpr::Not(Box::new(CfgExpr::Invalid)), - CfgExpr::All(Box::new([])), - CfgExpr::Invalid, - CfgAtom::KeyValue { key: Symbol::intern("bar"), value: Symbol::intern("baz") } - .into(), - ] - .into_boxed_slice(), - ), - ); } #[test] diff --git a/src/tools/rust-analyzer/crates/hir-def/src/attrs.rs b/src/tools/rust-analyzer/crates/hir-def/src/attrs.rs index e3e1aac7090a..b560d08492ff 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/attrs.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/attrs.rs @@ -12,25 +12,17 @@ //! its value. This way, queries are only called on items that have the attribute, which is //! usually only a few. //! -//! An exception to this model that is also defined in this module is documentation (doc -//! comments and `#[doc = "..."]` attributes). But it also has a more compact form than -//! the attribute: a concatenated string of the full docs as well as a source map -//! to map it back to AST (which is needed for things like resolving links in doc comments -//! and highlight injection). The lowering and upmapping of doc comments is a bit complicated, -//! but it is encapsulated in the [`Docs`] struct. +//! Documentation (doc comments and `#[doc = "..."]` attributes) is handled by the [`docs`] +//! submodule. -use std::{ - convert::Infallible, - iter::Peekable, - ops::{ControlFlow, Range}, -}; +use std::{convert::Infallible, iter::Peekable, ops::ControlFlow}; use base_db::Crate; use cfg::{CfgExpr, CfgOptions}; use either::Either; use hir_expand::{ - HirFileId, InFile, Lookup, - attrs::{Meta, expand_cfg_attr, expand_cfg_attr_with_doc_comments}, + InFile, Lookup, + attrs::{AstKeyValueMetaExt, AstPathExt, expand_cfg_attr}, }; use intern::Symbol; use itertools::Itertools; @@ -39,10 +31,10 @@ use rustc_hash::FxHashSet; use smallvec::SmallVec; use syntax::{ - AstNode, AstToken, NodeOrToken, SmolStr, SourceFile, SyntaxNode, SyntaxToken, T, - ast::{self, AttrDocCommentIter, HasAttrs, IsString, TokenTreeChildren}, + AstNode, AstToken, NodeOrToken, SmolStr, SourceFile, T, + ast::{self, HasAttrs, TokenTreeChildren}, }; -use tt::{TextRange, TextSize}; +use tt::TextSize; use crate::{ AdtId, AstIdLoc, AttrDefId, FieldId, FunctionId, GenericDefId, HasModule, LifetimeParamId, @@ -50,9 +42,14 @@ db::DefDatabase, hir::generics::{GenericParams, LocalLifetimeParamId, LocalTypeOrConstParamId}, nameres::ModuleOrigin, + resolver::{HasResolver, Resolver}, src::{HasChildSource, HasSource}, }; +pub mod docs; + +pub use self::docs::{Docs, IsInnerDoc}; + #[inline] fn attrs_from_ast_id_loc>( db: &dyn DefDatabase, @@ -131,63 +128,89 @@ fn extract_rustc_skip_during_method_dispatch(attr_flags: &mut AttrFlags, tt: ast } #[inline] -fn match_attr_flags(attr_flags: &mut AttrFlags, attr: Meta) -> ControlFlow { +fn match_attr_flags(attr_flags: &mut AttrFlags, attr: ast::Meta) -> ControlFlow { match attr { - Meta::NamedKeyValue { name: Some(name), value, .. } => match name.text() { - "deprecated" => attr_flags.insert(AttrFlags::IS_DEPRECATED), - "ignore" => attr_flags.insert(AttrFlags::IS_IGNORE), - "lang" => attr_flags.insert(AttrFlags::LANG_ITEM), - "path" => attr_flags.insert(AttrFlags::HAS_PATH), - "unstable" => attr_flags.insert(AttrFlags::IS_UNSTABLE), - "export_name" => { - if let Some(value) = value - && let Some(value) = ast::String::cast(value) - && let Ok(value) = value.value() - && *value == *"main" - { - attr_flags.insert(AttrFlags::IS_EXPORT_NAME_MAIN); - } - } - _ => {} - }, - Meta::TokenTree { path, tt } => match path.segments.len() { - 1 => match path.segments[0].text() { + ast::Meta::CfgMeta(_) => attr_flags.insert(AttrFlags::HAS_CFG), + ast::Meta::KeyValueMeta(attr) => { + let Some(key) = attr.path().as_one_segment() else { return ControlFlow::Continue(()) }; + match &*key { "deprecated" => attr_flags.insert(AttrFlags::IS_DEPRECATED), - "cfg" => attr_flags.insert(AttrFlags::HAS_CFG), - "doc" => extract_doc_tt_attr(attr_flags, tt), - "repr" => attr_flags.insert(AttrFlags::HAS_REPR), - "target_feature" => attr_flags.insert(AttrFlags::HAS_TARGET_FEATURE), - "proc_macro_derive" | "rustc_builtin_macro" => { - attr_flags.insert(AttrFlags::IS_DERIVE_OR_BUILTIN_MACRO) - } + "ignore" => attr_flags.insert(AttrFlags::IS_IGNORE), + "lang" => attr_flags.insert(AttrFlags::LANG_ITEM), + "path" => attr_flags.insert(AttrFlags::HAS_PATH), "unstable" => attr_flags.insert(AttrFlags::IS_UNSTABLE), - "rustc_layout_scalar_valid_range_start" | "rustc_layout_scalar_valid_range_end" => { - attr_flags.insert(AttrFlags::RUSTC_LAYOUT_SCALAR_VALID_RANGE) - } - "rustc_legacy_const_generics" => { - attr_flags.insert(AttrFlags::HAS_LEGACY_CONST_GENERICS) - } - "rustc_skip_during_method_dispatch" => { - extract_rustc_skip_during_method_dispatch(attr_flags, tt) - } - "rustc_deprecated_safe_2024" => { - attr_flags.insert(AttrFlags::RUSTC_DEPRECATED_SAFE_2024) + "export_name" => { + if let Some(value) = attr.value_string() + && *value == *"main" + { + attr_flags.insert(AttrFlags::IS_EXPORT_NAME_MAIN); + } } _ => {} - }, - 2 => match path.segments[0].text() { - "rust_analyzer" => match path.segments[1].text() { - "completions" => extract_ra_completions(attr_flags, tt), - "macro_style" => extract_ra_macro_style(attr_flags, tt), + } + } + ast::Meta::TokenTreeMeta(attr) => { + let (Some((first_segment, second_segment)), Some(tt)) = + (attr.path().as_up_to_two_segment(), attr.token_tree()) + else { + return ControlFlow::Continue(()); + }; + match second_segment { + None => match &*first_segment { + "deprecated" => attr_flags.insert(AttrFlags::IS_DEPRECATED), + "doc" => extract_doc_tt_attr(attr_flags, tt), + "repr" => attr_flags.insert(AttrFlags::HAS_REPR), + "target_feature" => attr_flags.insert(AttrFlags::HAS_TARGET_FEATURE), + "proc_macro_derive" | "rustc_builtin_macro" => { + attr_flags.insert(AttrFlags::IS_DERIVE_OR_BUILTIN_MACRO) + } + "unstable" => attr_flags.insert(AttrFlags::IS_UNSTABLE), + "rustc_layout_scalar_valid_range_start" + | "rustc_layout_scalar_valid_range_end" => { + attr_flags.insert(AttrFlags::RUSTC_LAYOUT_SCALAR_VALID_RANGE) + } + "rustc_legacy_const_generics" => { + attr_flags.insert(AttrFlags::HAS_LEGACY_CONST_GENERICS) + } + "rustc_skip_during_method_dispatch" => { + extract_rustc_skip_during_method_dispatch(attr_flags, tt) + } + "rustc_deprecated_safe_2024" => { + attr_flags.insert(AttrFlags::RUSTC_DEPRECATED_SAFE_2024) + } _ => {} }, - _ => {} - }, - _ => {} - }, - Meta::Path { path } => { - match path.segments.len() { - 1 => match path.segments[0].text() { + Some(second_segment) => match &*first_segment { + "rust_analyzer" => match &*second_segment { + "completions" => extract_ra_completions(attr_flags, tt), + "macro_style" => extract_ra_macro_style(attr_flags, tt), + _ => {} + }, + _ => {} + }, + } + } + ast::Meta::PathMeta(attr) => { + let is_test = attr.path().is_some_and(|path| { + let Some(segment1) = (|| path.segment()?.name_ref())() else { return false }; + let segment2 = path.qualifier(); + let segment3 = segment2.as_ref().and_then(|it| it.qualifier()); + let segment4 = segment3.as_ref().and_then(|it| it.qualifier()); + let segment3 = segment3.and_then(|it| it.segment()?.name_ref()); + let segment4 = segment4.and_then(|it| it.segment()?.name_ref()); + segment1.text() == "test" + && segment3.is_none_or(|it| it.text() == "prelude") + && segment4.is_none_or(|it| it.text() == "core") + }); + if is_test { + attr_flags.insert(AttrFlags::IS_TEST); + } + + let Some((first_segment, second_segment)) = attr.path().as_up_to_two_segment() else { + return ControlFlow::Continue(()); + }; + match second_segment { + None => match &*first_segment { "rustc_has_incoherent_inherent_impls" => { attr_flags.insert(AttrFlags::RUSTC_HAS_INCOHERENT_INHERENT_IMPLS) } @@ -231,18 +254,13 @@ fn match_attr_flags(attr_flags: &mut AttrFlags, attr: Meta) -> ControlFlow {} }, - 2 => match path.segments[0].text() { - "rust_analyzer" => match path.segments[1].text() { + Some(second_segment) => match &*first_segment { + "rust_analyzer" => match &*second_segment { "skip" => attr_flags.insert(AttrFlags::RUST_ANALYZER_SKIP), _ => {} }, _ => {} }, - _ => {} - } - - if path.is_test { - attr_flags.insert(AttrFlags::IS_TEST); } } _ => {} @@ -354,13 +372,13 @@ fn attrs_source( let krate = def_map.krate(); let (definition, declaration, extra_crate_attrs) = match def_map[id].origin { ModuleOrigin::CrateRoot { definition } => { - let definition_source = db.parse(definition).tree(); + let definition_source = definition.parse(db).tree(); let definition = InFile::new(definition.into(), definition_source.into()); let extra_crate_attrs = parse_extra_crate_attrs(db, krate); (definition, None, extra_crate_attrs) } ModuleOrigin::File { declaration, declaration_tree_id, definition, .. } => { - let definition_source = db.parse(definition).tree(); + let definition_source = definition.parse(db).tree(); let definition = InFile::new(definition.into(), definition_source.into()); let declaration = InFile::new(declaration_tree_id.file_id(), declaration); let declaration = declaration.with_value(declaration.to_node(db)); @@ -398,10 +416,32 @@ fn attrs_source( (owner, None, None, krate) } +fn resolver_for_attr_def_id(db: &dyn DefDatabase, owner: AttrDefId) -> Resolver<'_> { + match owner { + AttrDefId::ModuleId(id) => id.resolver(db), + AttrDefId::AdtId(AdtId::StructId(id)) => id.resolver(db), + AttrDefId::AdtId(AdtId::UnionId(id)) => id.resolver(db), + AttrDefId::AdtId(AdtId::EnumId(id)) => id.resolver(db), + AttrDefId::FunctionId(id) => id.resolver(db), + AttrDefId::EnumVariantId(id) => id.resolver(db), + AttrDefId::StaticId(id) => id.resolver(db), + AttrDefId::ConstId(id) => id.resolver(db), + AttrDefId::TraitId(id) => id.resolver(db), + AttrDefId::TypeAliasId(id) => id.resolver(db), + AttrDefId::MacroId(MacroId::Macro2Id(id)) => id.resolver(db), + AttrDefId::MacroId(MacroId::MacroRulesId(id)) => id.resolver(db), + AttrDefId::MacroId(MacroId::ProcMacroId(id)) => id.resolver(db), + AttrDefId::ImplId(id) => id.resolver(db), + AttrDefId::ExternBlockId(id) => id.resolver(db), + AttrDefId::ExternCrateId(id) => id.resolver(db), + AttrDefId::UseId(id) => id.resolver(db), + } +} + fn collect_attrs( db: &dyn DefDatabase, owner: AttrDefId, - mut callback: impl FnMut(Meta) -> ControlFlow, + mut callback: impl FnMut(ast::Meta) -> ControlFlow, ) -> Option { let (source, outer_mod_decl, extra_crate_attrs, krate) = attrs_source(db, owner); let extra_attrs = extra_crate_attrs @@ -413,7 +453,7 @@ fn collect_attrs( expand_cfg_attr( extra_attrs.chain(ast::attrs_including_inner(&source.value)), || cfg_options.get_or_insert_with(|| krate.cfg_options(db)), - move |meta, _, _, _| callback(meta), + move |meta, _| callback(meta), ) } @@ -475,291 +515,16 @@ pub struct RustcLayoutScalarValidRange { pub end: Option, } -#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] -struct DocsSourceMapLine { - /// The offset in [`Docs::docs`]. - string_offset: TextSize, - /// The offset in the AST of the text. - ast_offset: TextSize, -} - -#[derive(Debug, Clone, PartialEq, Eq, Hash)] -pub struct Docs { - /// The concatenated string of all `#[doc = "..."]` attributes and documentation comments. - docs: String, - /// A sorted map from an offset in `docs` to an offset in the source code. - docs_source_map: Vec, - /// If the item is an outlined module (`mod foo;`), `docs_source_map` store the concatenated - /// list of the outline and inline docs (outline first). Then, this field contains the [`HirFileId`] - /// of the outline declaration, and the index in `docs` from which the inline docs - /// begin. - outline_mod: Option<(HirFileId, usize)>, - inline_file: HirFileId, - /// The size the prepended prefix, which does not map to real doc comments. - prefix_len: TextSize, - /// The offset in `docs` from which the docs are inner attributes/comments. - inline_inner_docs_start: Option, - /// Like `inline_inner_docs_start`, but for `outline_mod`. This can happen only when merging `Docs` - /// (as outline modules don't have inner attributes). - outline_inner_docs_start: Option, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -pub enum IsInnerDoc { - No, - Yes, -} - -impl IsInnerDoc { - #[inline] - pub fn yes(self) -> bool { - self == IsInnerDoc::Yes - } -} - -impl Docs { - #[inline] - pub fn docs(&self) -> &str { - &self.docs - } - - #[inline] - pub fn into_docs(self) -> String { - self.docs - } - - pub fn find_ast_range( - &self, - mut string_range: TextRange, - ) -> Option<(InFile, IsInnerDoc)> { - if string_range.start() < self.prefix_len { - return None; - } - string_range -= self.prefix_len; - - let mut file = self.inline_file; - let mut inner_docs_start = self.inline_inner_docs_start; - // Check whether the range is from the outline, the inline, or both. - let source_map = if let Some((outline_mod_file, outline_mod_end)) = self.outline_mod { - if let Some(first_inline) = self.docs_source_map.get(outline_mod_end) { - if string_range.end() <= first_inline.string_offset { - // The range is completely in the outline. - file = outline_mod_file; - inner_docs_start = self.outline_inner_docs_start; - &self.docs_source_map[..outline_mod_end] - } else if string_range.start() >= first_inline.string_offset { - // The range is completely in the inline. - &self.docs_source_map[outline_mod_end..] - } else { - // The range is combined from the outline and the inline - cannot map it back. - return None; - } - } else { - // There is no inline. - file = outline_mod_file; - inner_docs_start = self.outline_inner_docs_start; - &self.docs_source_map - } - } else { - // There is no outline. - &self.docs_source_map - }; - - let after_range = - source_map.partition_point(|line| line.string_offset <= string_range.start()) - 1; - let after_range = &source_map[after_range..]; - let line = after_range.first()?; - if after_range.get(1).is_some_and(|next_line| next_line.string_offset < string_range.end()) - { - // The range is combined from two lines - cannot map it back. - return None; - } - let ast_range = string_range - line.string_offset + line.ast_offset; - let is_inner = if inner_docs_start - .is_some_and(|inner_docs_start| string_range.start() >= inner_docs_start) - { - IsInnerDoc::Yes - } else { - IsInnerDoc::No - }; - Some((InFile::new(file, ast_range), is_inner)) - } - - #[inline] - pub fn shift_by(&mut self, offset: TextSize) { - self.prefix_len += offset; - } - - pub fn prepend_str(&mut self, s: &str) { - self.prefix_len += TextSize::of(s); - self.docs.insert_str(0, s); - } - - pub fn append_str(&mut self, s: &str) { - self.docs.push_str(s); - } - - pub fn append(&mut self, other: &Docs) { - let other_offset = TextSize::of(&self.docs); - - assert!( - self.outline_mod.is_none() && other.outline_mod.is_none(), - "cannot merge `Docs` that have `outline_mod` set" - ); - self.outline_mod = Some((self.inline_file, self.docs_source_map.len())); - self.inline_file = other.inline_file; - self.outline_inner_docs_start = self.inline_inner_docs_start; - self.inline_inner_docs_start = other.inline_inner_docs_start.map(|it| it + other_offset); - - self.docs.push_str(&other.docs); - self.docs_source_map.extend(other.docs_source_map.iter().map( - |&DocsSourceMapLine { string_offset, ast_offset }| DocsSourceMapLine { - ast_offset, - string_offset: string_offset + other_offset, - }, - )); - } - - fn extend_with_doc_comment(&mut self, comment: ast::Comment, indent: &mut usize) { - let Some((doc, offset)) = comment.doc_comment() else { return }; - self.extend_with_doc_str(doc, comment.syntax().text_range().start() + offset, indent); - } - - fn extend_with_doc_attr(&mut self, value: SyntaxToken, indent: &mut usize) { - let Some(value) = ast::String::cast(value) else { return }; - let Some(value_offset) = value.text_range_between_quotes() else { return }; - let value_offset = value_offset.start(); - let Ok(value) = value.value() else { return }; - // FIXME: Handle source maps for escaped text. - self.extend_with_doc_str(&value, value_offset, indent); - } - - fn extend_with_doc_str(&mut self, doc: &str, mut offset_in_ast: TextSize, indent: &mut usize) { - for line in doc.split('\n') { - self.docs_source_map.push(DocsSourceMapLine { - string_offset: TextSize::of(&self.docs), - ast_offset: offset_in_ast, - }); - offset_in_ast += TextSize::of(line) + TextSize::of("\n"); - - let line = line.trim_end(); - if let Some(line_indent) = line.chars().position(|ch| !ch.is_whitespace()) { - // Empty lines are handled because `position()` returns `None` for them. - *indent = std::cmp::min(*indent, line_indent); - } - self.docs.push_str(line); - self.docs.push('\n'); - } - } - - fn remove_indent(&mut self, indent: usize, start_source_map_index: usize) { - /// In case of panics, we want to avoid corrupted UTF-8 in `self.docs`, so we clear it. - struct Guard<'a>(&'a mut Docs); - impl Drop for Guard<'_> { - fn drop(&mut self) { - let Docs { - docs, - docs_source_map, - outline_mod, - inline_file: _, - prefix_len: _, - inline_inner_docs_start: _, - outline_inner_docs_start: _, - } = self.0; - // Don't use `String::clear()` here because it's not guaranteed to not do UTF-8-dependent things, - // and we may have temporarily broken the string's encoding. - unsafe { docs.as_mut_vec() }.clear(); - // This is just to avoid panics down the road. - docs_source_map.clear(); - *outline_mod = None; - } - } - - if self.docs.is_empty() { - return; - } - - let guard = Guard(self); - let source_map = &mut guard.0.docs_source_map[start_source_map_index..]; - let Some(&DocsSourceMapLine { string_offset: mut copy_into, .. }) = source_map.first() - else { - return; - }; - // We basically want to remove multiple ranges from a string. Doing this efficiently (without O(N^2) - // or allocations) requires unsafe. Basically, for each line, we copy the line minus the indent into - // consecutive to the previous line (which may have moved). Then at the end we truncate. - let mut accumulated_offset = TextSize::new(0); - for idx in 0..source_map.len() { - let string_end_offset = source_map - .get(idx + 1) - .map_or_else(|| TextSize::of(&guard.0.docs), |next_attr| next_attr.string_offset); - let line_source = &mut source_map[idx]; - let line_docs = - &guard.0.docs[TextRange::new(line_source.string_offset, string_end_offset)]; - let line_docs_len = TextSize::of(line_docs); - let indent_size = line_docs.char_indices().nth(indent).map_or_else( - || TextSize::of(line_docs) - TextSize::of("\n"), - |(offset, _)| TextSize::new(offset as u32), - ); - unsafe { guard.0.docs.as_bytes_mut() }.copy_within( - Range::::from(TextRange::new( - line_source.string_offset + indent_size, - string_end_offset, - )), - copy_into.into(), - ); - copy_into += line_docs_len - indent_size; - - if let Some(inner_attrs_start) = &mut guard.0.inline_inner_docs_start - && *inner_attrs_start == line_source.string_offset - { - *inner_attrs_start -= accumulated_offset; - } - // The removals in the string accumulate, but in the AST not, because it already points - // to the beginning of each attribute. - // Also, we need to shift the AST offset of every line, but the string offset of the first - // line should not get shifted (in general, the shift for the string offset is by the - // number of lines until the current one, excluding the current one). - line_source.string_offset -= accumulated_offset; - line_source.ast_offset += indent_size; - - accumulated_offset += indent_size; - } - // Don't use `String::truncate()` here because it's not guaranteed to not do UTF-8-dependent things, - // and we may have temporarily broken the string's encoding. - unsafe { guard.0.docs.as_mut_vec() }.truncate(copy_into.into()); - - std::mem::forget(guard); - } - - fn remove_last_newline(&mut self) { - self.docs.truncate(self.docs.len().saturating_sub(1)); - } - - fn shrink_to_fit(&mut self) { - let Docs { - docs, - docs_source_map, - outline_mod: _, - inline_file: _, - prefix_len: _, - inline_inner_docs_start: _, - outline_inner_docs_start: _, - } = self; - docs.shrink_to_fit(); - docs_source_map.shrink_to_fit(); - } -} - #[derive(Debug, PartialEq, Eq, Hash)] pub struct DeriveInfo { pub trait_name: Symbol, pub helpers: Box<[Symbol]>, } -fn extract_doc_aliases(result: &mut Vec, attr: Meta) -> ControlFlow { - if let Meta::TokenTree { path, tt } = attr - && path.is1("doc") +fn extract_doc_aliases(result: &mut Vec, attr: ast::Meta) -> ControlFlow { + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("doc") + && let Some(tt) = attr.token_tree() { for atom in DocAtom::parse(tt) { match atom { @@ -776,85 +541,15 @@ fn extract_doc_aliases(result: &mut Vec, attr: Meta) -> ControlFlow, attr: Meta) -> ControlFlow { - if let Meta::TokenTree { path, tt } = attr - && path.is1("cfg") +fn extract_cfgs(result: &mut Vec, attr: ast::Meta) -> ControlFlow { + if let ast::Meta::CfgMeta(attr) = attr + && let Some(cfg_predicate) = attr.cfg_predicate() { - result.push(CfgExpr::parse_from_ast(&mut TokenTreeChildren::new(&tt).peekable())); + result.push(CfgExpr::parse_from_ast(cfg_predicate)); } ControlFlow::Continue(()) } -fn extract_docs<'a>( - get_cfg_options: &dyn Fn() -> &'a CfgOptions, - source: InFile, - outer_mod_decl: Option>, - inner_attrs_node: Option, -) -> Option> { - let mut result = Docs { - docs: String::new(), - docs_source_map: Vec::new(), - outline_mod: None, - inline_file: source.file_id, - prefix_len: TextSize::new(0), - inline_inner_docs_start: None, - outline_inner_docs_start: None, - }; - - let mut cfg_options = None; - let mut extend_with_attrs = - |result: &mut Docs, node: &SyntaxNode, expect_inner_attrs, indent: &mut usize| { - expand_cfg_attr_with_doc_comments::<_, Infallible>( - AttrDocCommentIter::from_syntax_node(node).filter(|attr| match attr { - Either::Left(attr) => attr.kind().is_inner() == expect_inner_attrs, - Either::Right(comment) => comment.kind().doc.is_some_and(|kind| { - (kind == ast::CommentPlacement::Inner) == expect_inner_attrs - }), - }), - || cfg_options.get_or_insert_with(get_cfg_options), - |attr| { - match attr { - Either::Right(doc_comment) => { - result.extend_with_doc_comment(doc_comment, indent) - } - Either::Left((attr, _, _, _)) => match attr { - // FIXME: Handle macros: `#[doc = concat!("foo", "bar")]`. - Meta::NamedKeyValue { - name: Some(name), value: Some(value), .. - } if name.text() == "doc" => { - result.extend_with_doc_attr(value, indent); - } - _ => {} - }, - } - ControlFlow::Continue(()) - }, - ); - }; - - if let Some(outer_mod_decl) = outer_mod_decl { - let mut indent = usize::MAX; - extend_with_attrs(&mut result, outer_mod_decl.value.syntax(), false, &mut indent); - result.remove_indent(indent, 0); - result.outline_mod = Some((outer_mod_decl.file_id, result.docs_source_map.len())); - } - - let inline_source_map_start = result.docs_source_map.len(); - let mut indent = usize::MAX; - extend_with_attrs(&mut result, source.value.syntax(), false, &mut indent); - if let Some(inner_attrs_node) = &inner_attrs_node { - result.inline_inner_docs_start = Some(TextSize::of(&result.docs)); - extend_with_attrs(&mut result, inner_attrs_node, true, &mut indent); - } - result.remove_indent(indent, inline_source_map_start); - - result.remove_last_newline(); - - result.shrink_to_fit(); - - if result.docs.is_empty() { None } else { Some(Box::new(result)) } -} - #[salsa::tracked] impl AttrFlags { #[salsa::tracked] @@ -881,7 +576,7 @@ fn field_attr_flags( expand_cfg_attr( field.value.attrs(), || cfg_options, - |attr, _, _, _| match_attr_flags(&mut attr_flags, attr), + |attr, _| match_attr_flags(&mut attr_flags, attr), ); attr_flags }) @@ -918,7 +613,7 @@ fn generic_params_attr_flags( let lifetimes_source = HasChildSource::::child_source(&def, db); for (lifetime_id, lifetime) in lifetimes_source.value.iter() { let mut attr_flags = AttrFlags::empty(); - expand_cfg_attr(lifetime.attrs(), &mut cfg_options, |attr, _, _, _| { + expand_cfg_attr(lifetime.attrs(), &mut cfg_options, |attr, _| { match_attr_flags(&mut attr_flags, attr) }); if !attr_flags.is_empty() { @@ -930,7 +625,7 @@ fn generic_params_attr_flags( HasChildSource::::child_source(&def, db); for (type_or_const_id, type_or_const) in type_and_consts_source.value.iter() { let mut attr_flags = AttrFlags::empty(); - expand_cfg_attr(type_or_const.attrs(), &mut cfg_options, |attr, _, _, _| { + expand_cfg_attr(type_or_const.attrs(), &mut cfg_options, |attr, _| { match_attr_flags(&mut attr_flags, attr) }); if !attr_flags.is_empty() { @@ -969,11 +664,10 @@ pub(crate) fn is_cfg_enabled_for( let result = expand_cfg_attr( attrs, || cfg_options, - |attr, _, _, _| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("cfg") - && let cfg = - CfgExpr::parse_from_ast(&mut TokenTreeChildren::new(&tt).peekable()) + |attr, _| { + if let ast::Meta::CfgMeta(attr) = attr + && let Some(cfg_predicate) = attr.cfg_predicate() + && let cfg = CfgExpr::parse_from_ast(cfg_predicate) && cfg_options.check(&cfg) == Some(false) { ControlFlow::Break(cfg) @@ -1005,10 +699,9 @@ pub fn lang_item_with_attrs(self, db: &dyn DefDatabase, owner: AttrDefId) -> Opt #[salsa::tracked] fn lang_item(db: &dyn DefDatabase, owner: AttrDefId) -> Option { collect_attrs(db, owner, |attr| { - if let Meta::NamedKeyValue { name: Some(name), value: Some(value), .. } = attr - && name.text() == "lang" - && let Some(value) = ast::String::cast(value) - && let Ok(value) = value.value() + if let ast::Meta::KeyValueMeta(attr) = attr + && attr.path().is1("lang") + && let Some(value) = attr.value_string() { ControlFlow::Break(Symbol::intern(&value)) } else { @@ -1031,8 +724,9 @@ pub fn repr(db: &dyn DefDatabase, owner: AdtId) -> Option { fn repr(db: &dyn DefDatabase, owner: AdtId) -> Option { let mut result = None; collect_attrs::(db, owner.into(), |attr| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("repr") + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("repr") + && let Some(tt) = attr.token_tree() && let Some(repr) = parse_repr_tt(&tt) { match &mut result { @@ -1053,8 +747,9 @@ pub(crate) fn legacy_const_generic_indices( owner: FunctionId, ) -> Option> { let result = collect_attrs(db, owner.into(), |attr| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("rustc_legacy_const_generics") + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("rustc_legacy_const_generics") + && let Some(tt) = attr.token_tree() { let result = parse_rustc_legacy_const_generics(tt); ControlFlow::Break(result) @@ -1069,7 +764,7 @@ pub(crate) fn legacy_const_generic_indices( #[salsa::tracked(returns(ref))] pub fn doc_html_root_url(db: &dyn DefDatabase, krate: Crate) -> Option { let root_file_id = krate.root_file_id(db); - let syntax = db.parse(root_file_id).tree(); + let syntax = root_file_id.parse(db).tree(); let extra_crate_attrs = parse_extra_crate_attrs(db, krate).into_iter().flat_map(|src| src.attrs()); @@ -1077,9 +772,10 @@ pub fn doc_html_root_url(db: &dyn DefDatabase, krate: Crate) -> Option expand_cfg_attr( extra_crate_attrs.chain(syntax.attrs()), || cfg_options.get_or_insert(krate.cfg_options(db)), - |attr, _, _, _| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("doc") + |attr, _| { + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("doc") + && let Some(tt) = attr.token_tree() && let Some(result) = DocAtom::parse(tt).into_iter().find_map(|atom| { if let DocAtom::KeyValue { key, value } = atom && key == "html_root_url" @@ -1110,8 +806,9 @@ pub fn target_features(db: &dyn DefDatabase, owner: FunctionId) -> &FxHashSet FxHashSet { let mut result = FxHashSet::default(); collect_attrs::(db, owner.into(), |attr| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("target_feature") + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("target_feature") + && let Some(tt) = attr.token_tree() { let mut tt = TokenTreeChildren::new(&tt); while let Some(NodeOrToken::Token(enable_ident)) = tt.next() @@ -1158,9 +855,11 @@ fn rustc_layout_scalar_valid_range( ) -> RustcLayoutScalarValidRange { let mut result = RustcLayoutScalarValidRange::default(); collect_attrs::(db, owner.into(), |attr| { - if let Meta::TokenTree { path, tt } = attr + if let ast::Meta::TokenTreeMeta(attr) = attr + && let path = attr.path() && (path.is1("rustc_layout_scalar_valid_range_start") || path.is1("rustc_layout_scalar_valid_range_end")) + && let Some(tt) = attr.token_tree() && let tt = TokenTreeChildren::new(&tt) && let Ok(NodeOrToken::Token(value)) = Itertools::exactly_one(tt) && let Some(value) = ast::IntNumber::cast(value) @@ -1208,7 +907,7 @@ fn fields_doc_aliases( expand_cfg_attr( field.value.attrs(), || cfg_options, - |attr, _, _, _| extract_doc_aliases(&mut result, attr), + |attr, _| extract_doc_aliases(&mut result, attr), ); result.into_boxed_slice() }) @@ -1250,7 +949,7 @@ fn fields_cfgs( expand_cfg_attr( field.value.attrs(), || cfg_options, - |attr, _, _, _| extract_cfgs(&mut result, attr), + |attr, _| extract_cfgs(&mut result, attr), ); match result.len() { 0 => None, @@ -1271,8 +970,9 @@ pub fn doc_keyword(db: &dyn DefDatabase, owner: ModuleId) -> Option { #[salsa::tracked] fn doc_keyword(db: &dyn DefDatabase, owner: ModuleId) -> Option { collect_attrs(db, AttrDefId::ModuleId(owner), |attr| { - if let Meta::TokenTree { path, tt } = attr - && path.is1("doc") + if let ast::Meta::TokenTreeMeta(attr) = attr + && attr.path().is1("doc") + && let Some(tt) = attr.token_tree() { for atom in DocAtom::parse(tt) { if let DocAtom::KeyValue { key, value } = atom @@ -1295,7 +995,15 @@ pub fn docs(db: &dyn DefDatabase, owner: AttrDefId) -> Option> { // Note: we don't have to pass down `_extra_crate_attrs` here, since `extract_docs` // does not handle crate-level attributes related to docs. // See: https://doc.rust-lang.org/rustdoc/write-documentation/the-doc-attribute.html#at-the-crate-level - extract_docs(&|| krate.cfg_options(db), source, outer_mod_decl, inner_attrs_node) + self::docs::extract_docs( + db, + krate, + &|| resolver_for_attr_def_id(db, owner), + &|| krate.cfg_options(db), + source, + outer_mod_decl, + inner_attrs_node, + ) } #[inline] @@ -1308,8 +1016,17 @@ pub fn fields_docs( db: &dyn DefDatabase, variant: VariantId, ) -> ArenaMap>> { + let krate = variant.module(db).krate(db); collect_field_attrs(db, variant, |cfg_options, field| { - extract_docs(&|| cfg_options, field, None, None) + self::docs::extract_docs( + db, + krate, + &|| variant.resolver(db), + &|| cfg_options, + field, + None, + None, + ) }) } } @@ -1325,12 +1042,10 @@ pub fn derive_info(db: &dyn DefDatabase, owner: MacroId) -> Option<&DeriveInfo> #[salsa::tracked(returns(ref))] fn derive_info(db: &dyn DefDatabase, owner: MacroId) -> Option { collect_attrs(db, owner.into(), |attr| { - if let Meta::TokenTree { path, tt } = attr - && path.segments.len() == 1 - && matches!( - path.segments[0].text(), - "proc_macro_derive" | "rustc_builtin_macro" - ) + if let ast::Meta::TokenTreeMeta(attr) = attr + && (attr.path().is1("proc_macro_derive") + || attr.path().is1("rustc_builtin_macro")) + && let Some(tt) = attr.token_tree() && let mut tt = TokenTreeChildren::new(&tt) && let Some(NodeOrToken::Token(trait_name)) = tt.next() && trait_name.kind().is_any_identifier() @@ -1537,150 +1252,12 @@ fn next_doc_expr(it: &mut Peekable) -> Option { #[cfg(test)] mod tests { - use expect_test::expect; - use hir_expand::InFile; use test_fixture::WithFixture; - use tt::{TextRange, TextSize}; use crate::AttrDefId; - use crate::attrs::{AttrFlags, Docs, IsInnerDoc}; + use crate::attrs::AttrFlags; use crate::test_db::TestDB; - #[test] - fn docs() { - let (_db, file_id) = TestDB::with_single_file(""); - let mut docs = Docs { - docs: String::new(), - docs_source_map: Vec::new(), - outline_mod: None, - inline_file: file_id.into(), - prefix_len: TextSize::new(0), - inline_inner_docs_start: None, - outline_inner_docs_start: None, - }; - let mut indent = usize::MAX; - - let outer = " foo\n\tbar baz"; - let mut ast_offset = TextSize::new(123); - for line in outer.split('\n') { - docs.extend_with_doc_str(line, ast_offset, &mut indent); - ast_offset += TextSize::of(line) + TextSize::of("\n"); - } - - docs.inline_inner_docs_start = Some(TextSize::of(&docs.docs)); - ast_offset += TextSize::new(123); - let inner = " bar \n baz"; - for line in inner.split('\n') { - docs.extend_with_doc_str(line, ast_offset, &mut indent); - ast_offset += TextSize::of(line) + TextSize::of("\n"); - } - - assert_eq!(indent, 1); - expect![[r#" - [ - DocsSourceMapLine { - string_offset: 0, - ast_offset: 123, - }, - DocsSourceMapLine { - string_offset: 5, - ast_offset: 128, - }, - DocsSourceMapLine { - string_offset: 15, - ast_offset: 261, - }, - DocsSourceMapLine { - string_offset: 20, - ast_offset: 267, - }, - ] - "#]] - .assert_debug_eq(&docs.docs_source_map); - - docs.remove_indent(indent, 0); - - assert_eq!(docs.inline_inner_docs_start, Some(TextSize::new(13))); - - assert_eq!(docs.docs, "foo\nbar baz\nbar\nbaz\n"); - expect![[r#" - [ - DocsSourceMapLine { - string_offset: 0, - ast_offset: 124, - }, - DocsSourceMapLine { - string_offset: 4, - ast_offset: 129, - }, - DocsSourceMapLine { - string_offset: 13, - ast_offset: 262, - }, - DocsSourceMapLine { - string_offset: 17, - ast_offset: 268, - }, - ] - "#]] - .assert_debug_eq(&docs.docs_source_map); - - docs.append(&docs.clone()); - docs.prepend_str("prefix---"); - assert_eq!(docs.docs, "prefix---foo\nbar baz\nbar\nbaz\nfoo\nbar baz\nbar\nbaz\n"); - expect![[r#" - [ - DocsSourceMapLine { - string_offset: 0, - ast_offset: 124, - }, - DocsSourceMapLine { - string_offset: 4, - ast_offset: 129, - }, - DocsSourceMapLine { - string_offset: 13, - ast_offset: 262, - }, - DocsSourceMapLine { - string_offset: 17, - ast_offset: 268, - }, - DocsSourceMapLine { - string_offset: 21, - ast_offset: 124, - }, - DocsSourceMapLine { - string_offset: 25, - ast_offset: 129, - }, - DocsSourceMapLine { - string_offset: 34, - ast_offset: 262, - }, - DocsSourceMapLine { - string_offset: 38, - ast_offset: 268, - }, - ] - "#]] - .assert_debug_eq(&docs.docs_source_map); - - let range = |start, end| TextRange::new(TextSize::new(start), TextSize::new(end)); - let in_file = |range| InFile::new(file_id.into(), range); - assert_eq!(docs.find_ast_range(range(0, 2)), None); - assert_eq!(docs.find_ast_range(range(8, 10)), None); - assert_eq!( - docs.find_ast_range(range(9, 10)), - Some((in_file(range(124, 125)), IsInnerDoc::No)) - ); - assert_eq!(docs.find_ast_range(range(20, 23)), None); - assert_eq!( - docs.find_ast_range(range(23, 25)), - Some((in_file(range(263, 265)), IsInnerDoc::Yes)) - ); - } - #[test] fn crate_attrs() { let fixture = r#" diff --git a/src/tools/rust-analyzer/crates/hir-def/src/attrs/docs.rs b/src/tools/rust-analyzer/crates/hir-def/src/attrs/docs.rs new file mode 100644 index 000000000000..9a715b19688e --- /dev/null +++ b/src/tools/rust-analyzer/crates/hir-def/src/attrs/docs.rs @@ -0,0 +1,736 @@ +//! Documentation extraction and source mapping. +//! +//! This module handles the extraction and processing of doc comments and `#[doc = "..."]` +//! attributes, including macro expansion for `#[doc = macro!()]` patterns. +//! It builds a concatenated string of the full docs as well as a source map +//! to map it back to AST (which is needed for things like resolving links in doc comments +//! and highlight injection). + +use std::{ + convert::Infallible, + ops::{ControlFlow, Range}, +}; + +use base_db::Crate; +use cfg::CfgOptions; +use either::Either; +use hir_expand::{ + AstId, ExpandTo, HirFileId, InFile, + attrs::{AstPathExt, expand_cfg_attr_with_doc_comments}, + mod_path::ModPath, + span_map::SpanMap, +}; +use span::AstIdMap; +use syntax::{ + AstNode, AstToken, SyntaxNode, + ast::{self, AttrDocCommentIter, IsString}, +}; +use tt::{TextRange, TextSize}; + +use crate::{db::DefDatabase, macro_call_as_call_id, nameres::MacroSubNs, resolver::Resolver}; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub(crate) struct DocsSourceMapLine { + /// The offset in [`Docs::docs`]. + string_offset: TextSize, + /// The offset in the AST of the text. `None` for macro-expanded doc strings + /// where we cannot provide a faithful source mapping. + ast_offset: Option, +} + +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct Docs { + /// The concatenated string of all `#[doc = "..."]` attributes and documentation comments. + docs: String, + /// A sorted map from an offset in `docs` to an offset in the source code. + docs_source_map: Vec, + /// If the item is an outlined module (`mod foo;`), `docs_source_map` store the concatenated + /// list of the outline and inline docs (outline first). Then, this field contains the [`HirFileId`] + /// of the outline declaration, and the index in `docs` from which the inline docs + /// begin. + outline_mod: Option<(HirFileId, usize)>, + inline_file: HirFileId, + /// The size the prepended prefix, which does not map to real doc comments. + prefix_len: TextSize, + /// The offset in `docs` from which the docs are inner attributes/comments. + inline_inner_docs_start: Option, + /// Like `inline_inner_docs_start`, but for `outline_mod`. This can happen only when merging `Docs` + /// (as outline modules don't have inner attributes). + outline_inner_docs_start: Option, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum IsInnerDoc { + No, + Yes, +} + +impl IsInnerDoc { + #[inline] + pub fn yes(self) -> bool { + self == IsInnerDoc::Yes + } +} + +impl Docs { + #[inline] + pub fn docs(&self) -> &str { + &self.docs + } + + #[inline] + pub fn into_docs(self) -> String { + self.docs + } + + pub fn find_ast_range( + &self, + mut string_range: TextRange, + ) -> Option<(InFile, IsInnerDoc)> { + if string_range.start() < self.prefix_len { + return None; + } + string_range -= self.prefix_len; + + let mut file = self.inline_file; + let mut inner_docs_start = self.inline_inner_docs_start; + // Check whether the range is from the outline, the inline, or both. + let source_map = if let Some((outline_mod_file, outline_mod_end)) = self.outline_mod { + if let Some(first_inline) = self.docs_source_map.get(outline_mod_end) { + if string_range.end() <= first_inline.string_offset { + // The range is completely in the outline. + file = outline_mod_file; + inner_docs_start = self.outline_inner_docs_start; + &self.docs_source_map[..outline_mod_end] + } else if string_range.start() >= first_inline.string_offset { + // The range is completely in the inline. + &self.docs_source_map[outline_mod_end..] + } else { + // The range is combined from the outline and the inline - cannot map it back. + return None; + } + } else { + // There is no inline. + file = outline_mod_file; + inner_docs_start = self.outline_inner_docs_start; + &self.docs_source_map + } + } else { + // There is no outline. + &self.docs_source_map + }; + + let after_range = + source_map.partition_point(|line| line.string_offset <= string_range.start()) - 1; + let after_range = &source_map[after_range..]; + let line = after_range.first()?; + // Unmapped lines (from macro-expanded docs) cannot be mapped back to AST. + let ast_offset = line.ast_offset?; + if after_range.get(1).is_some_and(|next_line| next_line.string_offset < string_range.end()) + { + // The range is combined from two lines - cannot map it back. + return None; + } + let ast_range = string_range - line.string_offset + ast_offset; + let is_inner = if inner_docs_start + .is_some_and(|inner_docs_start| string_range.start() >= inner_docs_start) + { + IsInnerDoc::Yes + } else { + IsInnerDoc::No + }; + Some((InFile::new(file, ast_range), is_inner)) + } + + #[inline] + pub fn shift_by(&mut self, offset: TextSize) { + self.prefix_len += offset; + } + + pub fn prepend_str(&mut self, s: &str) { + self.prefix_len += TextSize::of(s); + self.docs.insert_str(0, s); + } + + pub fn append_str(&mut self, s: &str) { + self.docs.push_str(s); + } + + pub fn append(&mut self, other: &Docs) { + let other_offset = TextSize::of(&self.docs); + + assert!( + self.outline_mod.is_none() && other.outline_mod.is_none(), + "cannot merge `Docs` that have `outline_mod` set" + ); + self.outline_mod = Some((self.inline_file, self.docs_source_map.len())); + self.inline_file = other.inline_file; + self.outline_inner_docs_start = self.inline_inner_docs_start; + self.inline_inner_docs_start = other.inline_inner_docs_start.map(|it| it + other_offset); + + self.docs.push_str(&other.docs); + self.docs_source_map.extend(other.docs_source_map.iter().map( + |&DocsSourceMapLine { string_offset, ast_offset }| DocsSourceMapLine { + ast_offset, + string_offset: string_offset + other_offset, + }, + )); + } + + fn extend_with_doc_comment(&mut self, comment: ast::Comment, indent: &mut usize) { + let Some((doc, offset)) = comment.doc_comment() else { return }; + self.extend_with_doc_str(doc, comment.syntax().text_range().start() + offset, indent); + } + + fn extend_with_doc_attr(&mut self, value: ast::String, indent: &mut usize) { + let Some(value_offset) = value.text_range_between_quotes() else { return }; + let value_offset = value_offset.start(); + let Ok(value) = value.value() else { return }; + // FIXME: Handle source maps for escaped text. + self.extend_with_doc_str(&value, value_offset, indent); + } + + pub(crate) fn extend_with_doc_str( + &mut self, + doc: &str, + offset_in_ast: TextSize, + indent: &mut usize, + ) { + self.push_doc_lines(doc, Some(offset_in_ast), indent); + } + + fn extend_with_unmapped_doc_str(&mut self, doc: &str, indent: &mut usize) { + self.push_doc_lines(doc, None, indent); + } + + fn push_doc_lines(&mut self, doc: &str, mut ast_offset: Option, indent: &mut usize) { + for line in doc.split('\n') { + self.docs_source_map + .push(DocsSourceMapLine { string_offset: TextSize::of(&self.docs), ast_offset }); + if let Some(ref mut offset) = ast_offset { + *offset += TextSize::of(line) + TextSize::of("\n"); + } + + let line = line.trim_end(); + if let Some(line_indent) = line.chars().position(|ch| !ch.is_whitespace()) { + // Empty lines are handled because `position()` returns `None` for them. + *indent = std::cmp::min(*indent, line_indent); + } + self.docs.push_str(line); + self.docs.push('\n'); + } + } + + fn remove_indent(&mut self, indent: usize, start_source_map_index: usize) { + /// In case of panics, we want to avoid corrupted UTF-8 in `self.docs`, so we clear it. + struct Guard<'a>(&'a mut Docs); + impl Drop for Guard<'_> { + fn drop(&mut self) { + let Docs { + docs, + docs_source_map, + outline_mod, + inline_file: _, + prefix_len: _, + inline_inner_docs_start: _, + outline_inner_docs_start: _, + } = self.0; + // Don't use `String::clear()` here because it's not guaranteed to not do UTF-8-dependent things, + // and we may have temporarily broken the string's encoding. + unsafe { docs.as_mut_vec() }.clear(); + // This is just to avoid panics down the road. + docs_source_map.clear(); + *outline_mod = None; + } + } + + if self.docs.is_empty() { + return; + } + + let guard = Guard(self); + let source_map = &mut guard.0.docs_source_map[start_source_map_index..]; + let Some(&DocsSourceMapLine { string_offset: mut copy_into, .. }) = source_map.first() + else { + return; + }; + // We basically want to remove multiple ranges from a string. Doing this efficiently (without O(N^2) + // or allocations) requires unsafe. Basically, for each line, we copy the line minus the indent into + // consecutive to the previous line (which may have moved). Then at the end we truncate. + let mut accumulated_offset = TextSize::new(0); + for idx in 0..source_map.len() { + let string_end_offset = source_map + .get(idx + 1) + .map_or_else(|| TextSize::of(&guard.0.docs), |next_attr| next_attr.string_offset); + let line_source = &mut source_map[idx]; + let line_docs = + &guard.0.docs[TextRange::new(line_source.string_offset, string_end_offset)]; + let line_docs_len = TextSize::of(line_docs); + let indent_size = line_docs.char_indices().nth(indent).map_or_else( + || TextSize::of(line_docs) - TextSize::of("\n"), + |(offset, _)| TextSize::new(offset as u32), + ); + unsafe { guard.0.docs.as_bytes_mut() }.copy_within( + Range::::from(TextRange::new( + line_source.string_offset + indent_size, + string_end_offset, + )), + copy_into.into(), + ); + copy_into += line_docs_len - indent_size; + + if let Some(inner_attrs_start) = &mut guard.0.inline_inner_docs_start + && *inner_attrs_start == line_source.string_offset + { + *inner_attrs_start -= accumulated_offset; + } + // The removals in the string accumulate, but in the AST not, because it already points + // to the beginning of each attribute. + // Also, we need to shift the AST offset of every line, but the string offset of the first + // line should not get shifted (in general, the shift for the string offset is by the + // number of lines until the current one, excluding the current one). + line_source.string_offset -= accumulated_offset; + if let Some(ref mut ast_offset) = line_source.ast_offset { + *ast_offset += indent_size; + } + + accumulated_offset += indent_size; + } + // Don't use `String::truncate()` here because it's not guaranteed to not do UTF-8-dependent things, + // and we may have temporarily broken the string's encoding. + unsafe { guard.0.docs.as_mut_vec() }.truncate(copy_into.into()); + + std::mem::forget(guard); + } + + fn remove_last_newline(&mut self) { + self.docs.truncate(self.docs.len().saturating_sub(1)); + } + + fn shrink_to_fit(&mut self) { + let Docs { + docs, + docs_source_map, + outline_mod: _, + inline_file: _, + prefix_len: _, + inline_inner_docs_start: _, + outline_inner_docs_start: _, + } = self; + docs.shrink_to_fit(); + docs_source_map.shrink_to_fit(); + } +} + +struct DocMacroExpander<'db> { + db: &'db dyn DefDatabase, + krate: Crate, + recursion_depth: usize, + recursion_limit: usize, +} + +struct DocExprSourceCtx<'db> { + resolver: Resolver<'db>, + file_id: HirFileId, + ast_id_map: &'db AstIdMap, + span_map: SpanMap, +} + +fn expand_doc_expr_via_macro_pipeline<'db>( + expander: &mut DocMacroExpander<'db>, + source_ctx: &DocExprSourceCtx<'db>, + expr: ast::Expr, +) -> Option { + match expr { + ast::Expr::ParenExpr(paren_expr) => { + expand_doc_expr_via_macro_pipeline(expander, source_ctx, paren_expr.expr()?) + } + ast::Expr::Literal(literal) => match literal.kind() { + ast::LiteralKind::String(string) => string.value().ok().map(Into::into), + _ => None, + }, + ast::Expr::MacroExpr(macro_expr) => { + let macro_call = macro_expr.macro_call()?; + let (expr, new_source_ctx) = expand_doc_macro_call(expander, source_ctx, macro_call)?; + // After expansion, the expr lives in the expansion file; use its source context. + expand_doc_expr_via_macro_pipeline(expander, &new_source_ctx, expr) + } + _ => None, + } +} + +fn expand_doc_macro_call<'db>( + expander: &mut DocMacroExpander<'db>, + source_ctx: &DocExprSourceCtx<'db>, + macro_call: ast::MacroCall, +) -> Option<(ast::Expr, DocExprSourceCtx<'db>)> { + if expander.recursion_depth >= expander.recursion_limit { + return None; + } + + let path = macro_call.path()?; + let mod_path = ModPath::from_src(expander.db, path, &mut |range| { + source_ctx.span_map.span_for_range(range).ctx + })?; + let call_site = source_ctx.span_map.span_for_range(macro_call.syntax().text_range()); + let ast_id = AstId::new(source_ctx.file_id, source_ctx.ast_id_map.ast_id(¯o_call)); + let call_id = macro_call_as_call_id( + expander.db, + ast_id, + &mod_path, + call_site.ctx, + ExpandTo::Expr, + expander.krate, + |path| { + source_ctx.resolver.resolve_path_as_macro_def(expander.db, path, Some(MacroSubNs::Bang)) + }, + &mut |_, _| (), + ) + .ok()? + .value?; + + expander.recursion_depth += 1; + let parse = expander.db.parse_macro_expansion(call_id).value.0; + let expr = parse.cast::().map(|parse| parse.tree())?; + expander.recursion_depth -= 1; + + // Build a new source context for the expansion file so that any further + // recursive expansion (e.g. a user macro expanding to `concat!(...)`) + // correctly resolves AstIds and spans in the expansion. + let expansion_file_id: HirFileId = call_id.into(); + let new_source_ctx = DocExprSourceCtx { + resolver: source_ctx.resolver.clone(), + file_id: expansion_file_id, + ast_id_map: expander.db.ast_id_map(expansion_file_id), + span_map: expander.db.span_map(expansion_file_id), + }; + Some((expr, new_source_ctx)) +} + +fn extend_with_attrs<'a, 'db>( + result: &mut Docs, + db: &'db dyn DefDatabase, + krate: Crate, + node: &SyntaxNode, + file_id: HirFileId, + expect_inner_attrs: bool, + indent: &mut usize, + get_cfg_options: &dyn Fn() -> &'a CfgOptions, + cfg_options: &mut Option<&'a CfgOptions>, + make_resolver: &dyn Fn() -> Resolver<'db>, +) { + // Lazily initialised when we first encounter a `#[doc = macro!()]`. + let mut expander: Option<(DocMacroExpander<'db>, DocExprSourceCtx<'db>)> = None; + + expand_cfg_attr_with_doc_comments::<_, Infallible>( + AttrDocCommentIter::from_syntax_node(node).filter(|attr| match attr { + Either::Left(attr) => attr.kind().is_inner() == expect_inner_attrs, + Either::Right(comment) => comment + .kind() + .doc + .is_some_and(|kind| (kind == ast::CommentPlacement::Inner) == expect_inner_attrs), + }), + || *cfg_options.get_or_insert_with(get_cfg_options), + |attr| { + match attr { + Either::Right(doc_comment) => result.extend_with_doc_comment(doc_comment, indent), + Either::Left((attr, _)) => match attr { + ast::Meta::KeyValueMeta(attr) if attr.path().is1("doc") => { + if let Some(value) = attr.expr() { + if let ast::Expr::Literal(value) = &value + && let ast::LiteralKind::String(value) = value.kind() + { + result.extend_with_doc_attr(value, indent); + } else { + let (exp, ctx) = expander.get_or_insert_with(|| { + let resolver = make_resolver(); + let def_map = resolver.top_level_def_map(); + let recursion_limit = def_map.recursion_limit() as usize; + ( + DocMacroExpander { + db, + krate, + recursion_depth: 0, + recursion_limit, + }, + DocExprSourceCtx { + resolver, + file_id, + ast_id_map: db.ast_id_map(file_id), + span_map: db.span_map(file_id), + }, + ) + }); + if let Some(expanded) = + expand_doc_expr_via_macro_pipeline(exp, ctx, value) + { + result.extend_with_unmapped_doc_str(&expanded, indent); + } + } + } + } + _ => {} + }, + } + ControlFlow::Continue(()) + }, + ); +} + +pub(crate) fn extract_docs<'a, 'db>( + db: &'db dyn DefDatabase, + krate: Crate, + resolver: &dyn Fn() -> Resolver<'db>, + get_cfg_options: &dyn Fn() -> &'a CfgOptions, + source: InFile, + outer_mod_decl: Option>, + inner_attrs_node: Option, +) -> Option> { + let mut result = Docs { + docs: String::new(), + docs_source_map: Vec::new(), + outline_mod: None, + inline_file: source.file_id, + prefix_len: TextSize::new(0), + inline_inner_docs_start: None, + outline_inner_docs_start: None, + }; + + let mut cfg_options = None; + + if let Some(outer_mod_decl) = outer_mod_decl { + let mut indent = usize::MAX; + // For outer docs (the `mod foo;` declaration), use the module's own resolver. + extend_with_attrs( + &mut result, + db, + krate, + outer_mod_decl.value.syntax(), + outer_mod_decl.file_id, + false, + &mut indent, + get_cfg_options, + &mut cfg_options, + resolver, + ); + result.remove_indent(indent, 0); + result.outline_mod = Some((outer_mod_decl.file_id, result.docs_source_map.len())); + } + + let inline_source_map_start = result.docs_source_map.len(); + let mut indent = usize::MAX; + // For inline docs, use the item's own resolver. + extend_with_attrs( + &mut result, + db, + krate, + source.value.syntax(), + source.file_id, + false, + &mut indent, + get_cfg_options, + &mut cfg_options, + resolver, + ); + if let Some(inner_attrs_node) = &inner_attrs_node { + result.inline_inner_docs_start = Some(TextSize::of(&result.docs)); + extend_with_attrs( + &mut result, + db, + krate, + inner_attrs_node, + source.file_id, + true, + &mut indent, + get_cfg_options, + &mut cfg_options, + resolver, + ); + } + result.remove_indent(indent, inline_source_map_start); + + result.remove_last_newline(); + + result.shrink_to_fit(); + + if result.docs.is_empty() { None } else { Some(Box::new(result)) } +} + +#[cfg(test)] +mod tests { + use expect_test::expect; + use hir_expand::InFile; + use test_fixture::WithFixture; + use tt::{TextRange, TextSize}; + + use crate::test_db::TestDB; + + use super::{Docs, IsInnerDoc}; + + #[test] + fn docs() { + let (_db, file_id) = TestDB::with_single_file(""); + let mut docs = Docs { + docs: String::new(), + docs_source_map: Vec::new(), + outline_mod: None, + inline_file: file_id.into(), + prefix_len: TextSize::new(0), + inline_inner_docs_start: None, + outline_inner_docs_start: None, + }; + let mut indent = usize::MAX; + + let outer = " foo\n\tbar baz"; + let mut ast_offset = TextSize::new(123); + for line in outer.split('\n') { + docs.extend_with_doc_str(line, ast_offset, &mut indent); + ast_offset += TextSize::of(line) + TextSize::of("\n"); + } + + docs.inline_inner_docs_start = Some(TextSize::of(&docs.docs)); + ast_offset += TextSize::new(123); + let inner = " bar \n baz"; + for line in inner.split('\n') { + docs.extend_with_doc_str(line, ast_offset, &mut indent); + ast_offset += TextSize::of(line) + TextSize::of("\n"); + } + + assert_eq!(indent, 1); + expect![[r#" + [ + DocsSourceMapLine { + string_offset: 0, + ast_offset: Some( + 123, + ), + }, + DocsSourceMapLine { + string_offset: 5, + ast_offset: Some( + 128, + ), + }, + DocsSourceMapLine { + string_offset: 15, + ast_offset: Some( + 261, + ), + }, + DocsSourceMapLine { + string_offset: 20, + ast_offset: Some( + 267, + ), + }, + ] + "#]] + .assert_debug_eq(&docs.docs_source_map); + + docs.remove_indent(indent, 0); + + assert_eq!(docs.inline_inner_docs_start, Some(TextSize::new(13))); + + assert_eq!(docs.docs, "foo\nbar baz\nbar\nbaz\n"); + expect![[r#" + [ + DocsSourceMapLine { + string_offset: 0, + ast_offset: Some( + 124, + ), + }, + DocsSourceMapLine { + string_offset: 4, + ast_offset: Some( + 129, + ), + }, + DocsSourceMapLine { + string_offset: 13, + ast_offset: Some( + 262, + ), + }, + DocsSourceMapLine { + string_offset: 17, + ast_offset: Some( + 268, + ), + }, + ] + "#]] + .assert_debug_eq(&docs.docs_source_map); + + docs.append(&docs.clone()); + docs.prepend_str("prefix---"); + assert_eq!(docs.docs, "prefix---foo\nbar baz\nbar\nbaz\nfoo\nbar baz\nbar\nbaz\n"); + expect![[r#" + [ + DocsSourceMapLine { + string_offset: 0, + ast_offset: Some( + 124, + ), + }, + DocsSourceMapLine { + string_offset: 4, + ast_offset: Some( + 129, + ), + }, + DocsSourceMapLine { + string_offset: 13, + ast_offset: Some( + 262, + ), + }, + DocsSourceMapLine { + string_offset: 17, + ast_offset: Some( + 268, + ), + }, + DocsSourceMapLine { + string_offset: 21, + ast_offset: Some( + 124, + ), + }, + DocsSourceMapLine { + string_offset: 25, + ast_offset: Some( + 129, + ), + }, + DocsSourceMapLine { + string_offset: 34, + ast_offset: Some( + 262, + ), + }, + DocsSourceMapLine { + string_offset: 38, + ast_offset: Some( + 268, + ), + }, + ] + "#]] + .assert_debug_eq(&docs.docs_source_map); + + let range = |start, end| TextRange::new(TextSize::new(start), TextSize::new(end)); + let in_file = |range| InFile::new(file_id.into(), range); + assert_eq!(docs.find_ast_range(range(0, 2)), None); + assert_eq!(docs.find_ast_range(range(8, 10)), None); + assert_eq!( + docs.find_ast_range(range(9, 10)), + Some((in_file(range(124, 125)), IsInnerDoc::No)) + ); + assert_eq!(docs.find_ast_range(range(20, 23)), None); + assert_eq!( + docs.find_ast_range(range(23, 25)), + Some((in_file(range(263, 265)), IsInnerDoc::Yes)) + ); + } +} diff --git a/src/tools/rust-analyzer/crates/hir-def/src/db.rs b/src/tools/rust-analyzer/crates/hir-def/src/db.rs index 5d5d43539822..9dd7768ead86 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/db.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/db.rs @@ -1,5 +1,5 @@ //! Defines database & queries for name resolution. -use base_db::{Crate, RootQueryDb, SourceDatabase}; +use base_db::{Crate, SourceDatabase}; use hir_expand::{ EditionedFileId, HirFileId, InFile, Lookup, MacroCallId, MacroDefId, MacroDefKind, db::ExpandDatabase, @@ -22,7 +22,7 @@ use salsa::plumbing::AsId; #[query_group::query_group(InternDatabaseStorage)] -pub trait InternDatabase: RootQueryDb { +pub trait InternDatabase: SourceDatabase { // region: items #[salsa::interned] fn intern_use(&self, loc: UseLoc) -> UseId; diff --git a/src/tools/rust-analyzer/crates/hir-def/src/dyn_map.rs b/src/tools/rust-analyzer/crates/hir-def/src/dyn_map.rs index 4308d0ef1c29..c38ceccd1fc0 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/dyn_map.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/dyn_map.rs @@ -68,7 +68,7 @@ pub mod keys { pub const MACRO_CALL: Key = Key::new(); pub const ATTR_MACRO_CALL: Key = Key::new(); pub const DERIVE_MACRO_CALL: Key< - ast::Attr, + ast::Meta, ( AttrId, /* derive() */ MacroCallId, diff --git a/src/tools/rust-analyzer/crates/hir-def/src/expr_store.rs b/src/tools/rust-analyzer/crates/hir-def/src/expr_store.rs index ca523622ec84..62a17168b18e 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/expr_store.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/expr_store.rs @@ -520,7 +520,7 @@ pub fn expr_roots(&self) -> impl Iterator { self.const_expr_origins().iter().map(|&(id, _)| id) } - /// Like [`Self::signature_const_expr_roots`], but also returns the origin + /// Like [`Self::expr_roots`], but also returns the origin /// of each expression. pub fn expr_roots_with_origins(&self) -> impl Iterator { self.const_expr_origins().iter().map(|&(id, origin)| (id, origin)) diff --git a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/lower.rs b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/lower.rs index 74006c603703..7fe91a3d02db 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/lower.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/lower.rs @@ -1465,7 +1465,15 @@ fn maybe_collect_expr(&mut self, expr: ast::Expr) -> Option { match kind { ArrayExprKind::ElementList(e) => { - let elements = e.map(|expr| self.collect_expr(expr)).collect(); + let elements = e + .filter_map(|expr| { + if self.check_cfg(&expr) { + Some(self.collect_expr(expr)) + } else { + None + } + }) + .collect(); self.alloc_expr(Expr::Array(Array::ElementList { elements }), syntax_ptr) } ArrayExprKind::Repeat { initializer, repeat } => { diff --git a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/scope.rs b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/scope.rs index 40ae0b7de462..9738ac5c44c9 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/scope.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/scope.rs @@ -371,7 +371,6 @@ fn compute_expr_scopes( #[cfg(test)] mod tests { - use base_db::RootQueryDb; use hir_expand::{InFile, name::AsName}; use span::FileId; use syntax::{AstNode, algo::find_node_at_offset, ast}; @@ -414,7 +413,7 @@ fn do_check(#[rust_analyzer::rust_fixture] ra_fixture: &str, expected: &[&str]) let (file_id, _) = editioned_file_id.unpack(&db); - let file_syntax = db.parse(editioned_file_id).syntax_node(); + let file_syntax = editioned_file_id.parse(&db).syntax_node(); let marker: ast::PathExpr = find_node_at_offset(&file_syntax, offset).unwrap(); let function = find_function(&db, file_id); @@ -570,7 +569,7 @@ fn do_check_local_name(#[rust_analyzer::rust_fixture] ra_fixture: &str, expected let (file_id, _) = editioned_file_id.unpack(&db); - let file = db.parse(editioned_file_id).ok().unwrap(); + let file = editioned_file_id.parse(&db).ok().unwrap(); let expected_name = find_node_at_offset::(file.syntax(), expected_offset.into()) .expect("failed to find a name at the target offset"); let name_ref: ast::NameRef = find_node_at_offset(file.syntax(), offset).unwrap(); diff --git a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body.rs b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body.rs index 985cd9666267..4e5f2ca89327 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body.rs @@ -660,3 +660,24 @@ fn main(self, param1, mut param2, mut 0, param4 @ _, mut 1 }"#]], ) } + +#[test] +fn array_element_cfg() { + pretty_print( + r#" +fn foo() { + [ + (), + #[cfg(false)] + () + ]; +} + "#, + expect![[r#" + fn foo() { + [ + (), + ]; + }"#]], + ); +} diff --git a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body/block.rs b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body/block.rs index 83594ee02169..71fcced2d85b 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body/block.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/expr_store/tests/body/block.rs @@ -190,13 +190,13 @@ fn f() { "#, expect![[r#" ModuleIdLt { - [salsa id]: Id(3803), + [salsa id]: Id(3403), krate: Crate( - Id(2400), + Id(2000), ), block: Some( BlockId( - 4801, + 4401, ), ), }"#]], diff --git a/src/tools/rust-analyzer/crates/hir-def/src/import_map.rs b/src/tools/rust-analyzer/crates/hir-def/src/import_map.rs index 0014e1af5c0d..ba077b1b2ef5 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/import_map.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/import_map.rs @@ -499,7 +499,7 @@ fn search_maps( #[cfg(test)] mod tests { - use base_db::RootQueryDb; + use base_db::all_crates; use expect_test::{Expect, expect}; use test_fixture::WithFixture; @@ -536,7 +536,7 @@ fn check_search( expect: Expect, ) { let db = TestDB::with_files(ra_fixture); - let all_crates = db.all_crates(); + let all_crates = all_crates(&db); let krate = all_crates .iter() .copied() @@ -616,7 +616,7 @@ fn assoc_item_path( fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str, expect: Expect) { let db = TestDB::with_files(ra_fixture); - let all_crates = db.all_crates(); + let all_crates = all_crates(&db); let actual = all_crates .iter() diff --git a/src/tools/rust-analyzer/crates/hir-def/src/item_tree/attrs.rs b/src/tools/rust-analyzer/crates/hir-def/src/item_tree/attrs.rs index 79076112847b..867d813e3f2b 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/item_tree/attrs.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/item_tree/attrs.rs @@ -13,12 +13,12 @@ use cfg::{CfgExpr, CfgOptions}; use either::Either; use hir_expand::{ - attrs::{Attr, AttrId, AttrInput, Meta, collect_item_tree_attrs}, + attrs::{Attr, AttrId, AttrInput, collect_item_tree_attrs}, mod_path::ModPath, name::Name, }; use intern::{Interned, Symbol, sym}; -use syntax::{AstNode, T, ast}; +use syntax::{AstNode, ast}; use syntax_bridge::DocCommentDesugarMode; use tt::token_to_literal; @@ -51,58 +51,62 @@ pub(crate) fn lower<'a, S>( S: syntax_bridge::SpanMapper + Copy, { let mut attrs = Vec::new(); - let result = - collect_item_tree_attrs::(owner, cfg_options, |meta, container, _, _| { - // NOTE: We cannot early return from this function, *every* attribute must be pushed, otherwise we'll mess the `AttrId` - // tracking. - let (span, path_range, input) = match meta { - Meta::NamedKeyValue { path_range, name: _, value } => { - let span = span_map.span_for(path_range); - let input = value.map(|value| { - Box::new(AttrInput::Literal(token_to_literal( - value.text(), - span_map.span_for(value.text_range()), - ))) - }); - (span, path_range, input) - } - Meta::TokenTree { path, tt } => { - let span = span_map.span_for(path.range); - let tt = syntax_bridge::syntax_node_to_token_tree( - tt.syntax(), - span_map, - span, - DocCommentDesugarMode::ProcMacro, - ); - let input = Some(Box::new(AttrInput::TokenTree(tt))); - (span, path.range, input) - } - Meta::Path { path } => { - let span = span_map.span_for(path.range); - (span, path.range, None) - } - }; + let result = collect_item_tree_attrs::(owner, cfg_options, |meta, _| { + // NOTE: We cannot early return from this function, *every* attribute must be pushed, otherwise we'll mess the `AttrId` + // tracking. + let path = meta.path(); + let path_range = path + .as_ref() + .map(|path| path.syntax().text_range()) + .unwrap_or_else(|| meta.syntax().text_range()); + let (span, input) = match &meta { + ast::Meta::KeyValueMeta(meta) => { + let span = span_map.span_for(path_range); + let input = meta.expr().and_then(|value| { + if let ast::Expr::Literal(value) = value { + Some(Box::new(AttrInput::Literal(token_to_literal( + value.token().text(), + span_map.span_for(value.syntax().text_range()), + )))) + } else { + None + } + }); + (span, input) + } + ast::Meta::TokenTreeMeta(meta) => { + let span = span_map.span_for(path_range); + let tt = syntax_bridge::syntax_node_to_token_tree( + &meta + .token_tree() + .map(|it| it.syntax().clone()) + .unwrap_or_else(|| meta.syntax().clone()), + span_map, + span, + DocCommentDesugarMode::ProcMacro, + ); + let input = Some(Box::new(AttrInput::TokenTree(tt))); + (span, input) + } + ast::Meta::PathMeta(_) => { + let span = span_map.span_for(path_range); + (span, None) + } + ast::Meta::CfgMeta(_) | ast::Meta::CfgAttrMeta(_) | ast::Meta::UnsafeMeta(_) => { + unreachable!( + "`cfg`, `cfg_attr` and `unsafe(...)` are handled in `collect_item_tree_attrs()`" + ) + } + }; - let path = container.token_at_offset(path_range.start()).right_biased().and_then( - |first_path_token| { - let is_abs = matches!(first_path_token.kind(), T![:] | T![::]); - let segments = - std::iter::successors(Some(first_path_token), |it| it.next_token()) - .take_while(|it| it.text_range().end() <= path_range.end()) - .filter(|it| it.kind().is_any_identifier()); - ModPath::from_tokens( - db, - &mut |range| span_map.span_for(range).ctx, - is_abs, - segments, - ) - }, - ); - let path = path.unwrap_or_else(|| Name::missing().into()); - - attrs.push(Attr { path: Interned::new(path), input, ctxt: span.ctx }); - ControlFlow::Continue(()) + let path = path.and_then(|path| { + ModPath::from_src(db, path, &mut |range| span_map.span_for(range).ctx) }); + let path = path.unwrap_or_else(|| Name::missing().into()); + + attrs.push(Attr { path: Interned::new(path), input, ctxt: span.ctx }); + ControlFlow::Continue(()) + }); let attrs = AttrsOwned(attrs.into_boxed_slice()); match result { Some(Either::Right(cfg)) => AttrsOrCfg::CfgDisabled(Box::new((cfg, attrs))), diff --git a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe.rs b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe.rs index d93df7af6a73..e75c96b63039 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe.rs @@ -35,9 +35,9 @@ struct $ident { }; } -struct#0:MacroRules[BE8F, 0]@58..64#18432# MyTraitMap2#0:MacroCall[BE8F, 0]@31..42#ROOT2024# {#0:MacroRules[BE8F, 0]@72..73#18432# - map#0:MacroRules[BE8F, 0]@86..89#18432#:#0:MacroRules[BE8F, 0]@89..90#18432# #0:MacroRules[BE8F, 0]@89..90#18432#::#0:MacroRules[BE8F, 0]@91..93#18432#std#0:MacroRules[BE8F, 0]@93..96#18432#::#0:MacroRules[BE8F, 0]@96..98#18432#collections#0:MacroRules[BE8F, 0]@98..109#18432#::#0:MacroRules[BE8F, 0]@109..111#18432#HashSet#0:MacroRules[BE8F, 0]@111..118#18432#<#0:MacroRules[BE8F, 0]@118..119#18432#(#0:MacroRules[BE8F, 0]@119..120#18432#)#0:MacroRules[BE8F, 0]@120..121#18432#>#0:MacroRules[BE8F, 0]@121..122#18432#,#0:MacroRules[BE8F, 0]@122..123#18432# -}#0:MacroRules[BE8F, 0]@132..133#18432# +struct#0:MacroRules[BE8F, 0]@58..64#17408# MyTraitMap2#0:MacroCall[BE8F, 0]@31..42#ROOT2024# {#0:MacroRules[BE8F, 0]@72..73#17408# + map#0:MacroRules[BE8F, 0]@86..89#17408#:#0:MacroRules[BE8F, 0]@89..90#17408# #0:MacroRules[BE8F, 0]@89..90#17408#::#0:MacroRules[BE8F, 0]@91..93#17408#std#0:MacroRules[BE8F, 0]@93..96#17408#::#0:MacroRules[BE8F, 0]@96..98#17408#collections#0:MacroRules[BE8F, 0]@98..109#17408#::#0:MacroRules[BE8F, 0]@109..111#17408#HashSet#0:MacroRules[BE8F, 0]@111..118#17408#<#0:MacroRules[BE8F, 0]@118..119#17408#(#0:MacroRules[BE8F, 0]@119..120#17408#)#0:MacroRules[BE8F, 0]@120..121#17408#>#0:MacroRules[BE8F, 0]@121..122#17408#,#0:MacroRules[BE8F, 0]@122..123#17408# +}#0:MacroRules[BE8F, 0]@132..133#17408# "#]], ); } @@ -197,7 +197,7 @@ macro_rules! mk_struct { #[macro_use] mod foo; -struct#1:MacroRules[DB0C, 0]@59..65#18432# Foo#0:MacroCall[DB0C, 0]@32..35#ROOT2024#(#1:MacroRules[DB0C, 0]@70..71#18432#u32#0:MacroCall[DB0C, 0]@41..44#ROOT2024#)#1:MacroRules[DB0C, 0]@74..75#18432#;#1:MacroRules[DB0C, 0]@75..76#18432# +struct#1:MacroRules[DB0C, 0]@59..65#17408# Foo#0:MacroCall[DB0C, 0]@32..35#ROOT2024#(#1:MacroRules[DB0C, 0]@70..71#17408#u32#0:MacroCall[DB0C, 0]@41..44#ROOT2024#)#1:MacroRules[DB0C, 0]@74..75#17408#;#1:MacroRules[DB0C, 0]@75..76#17408# "#]], ); } @@ -423,10 +423,10 @@ macro_rules! m { macro_rules! m { ($($i:ident),*) => ( impl Bar { $(fn $i() {})* } ); } -impl#\18432# Bar#\18432# {#\18432# - fn#\18432# foo#\ROOT2024#(#\18432#)#\18432# {#\18432#}#\18432# - fn#\18432# bar#\ROOT2024#(#\18432#)#\18432# {#\18432#}#\18432# -}#\18432# +impl#\17408# Bar#\17408# {#\17408# + fn#\17408# foo#\ROOT2024#(#\17408#)#\17408# {#\17408#}#\17408# + fn#\17408# bar#\ROOT2024#(#\17408#)#\17408# {#\17408#}#\17408# +}#\17408# "#]], ); } @@ -1198,7 +1198,7 @@ macro_rules! m { macro_rules! m { ($m:meta) => ( #[$m] fn bar() {} ) } -#[cfg(target_os = "windows")] fn bar() {} +#[cfg (target_os = "windows")] fn bar() {} #[hello::world] fn bar() {} "#]], ); diff --git a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe/regression.rs b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe/regression.rs index ddabb50251a4..cac248f47fff 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe/regression.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mbe/regression.rs @@ -205,7 +205,7 @@ impl Clone for D3DVSHADERCAPS2_0 { *self } } -#[cfg(feature = "impl-default")] impl Default for D3DVSHADERCAPS2_0 { +#[cfg (feature = "impl-default")] impl Default for D3DVSHADERCAPS2_0 { #[inline] fn default() -> D3DVSHADERCAPS2_0 { unsafe { $crate::_core::mem::zeroed() @@ -215,7 +215,7 @@ impl Clone for D3DVSHADERCAPS2_0 { #[repr(C)] #[derive(Copy)] -#[cfg_attr(target_arch = "x86", repr(packed))] pub struct D3DCONTENTPROTECTIONCAPS { +#[cfg_attr (target_arch = "x86", repr(packed))] pub struct D3DCONTENTPROTECTIONCAPS { pub Caps: u8, } impl Clone for D3DCONTENTPROTECTIONCAPS { @@ -223,7 +223,7 @@ impl Clone for D3DCONTENTPROTECTIONCAPS { *self } } -#[cfg(feature = "impl-default")] impl Default for D3DCONTENTPROTECTIONCAPS { +#[cfg (feature = "impl-default")] impl Default for D3DCONTENTPROTECTIONCAPS { #[inline] fn default() -> D3DCONTENTPROTECTIONCAPS { unsafe { $crate::_core::mem::zeroed() @@ -1001,8 +1001,8 @@ macro_rules! with_std { ($($i:item)*) => ($(#[cfg(feature = "std")]$i)*) } -#[cfg(feature = "std")] mod m; -#[cfg(feature = "std")] mod f; +#[cfg (feature = "std")] mod m; +#[cfg (feature = "std")] mod f; "#]], ) } diff --git a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mod.rs b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mod.rs index 8317c56caf76..eabdada67c2a 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mod.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/mod.rs @@ -16,7 +16,6 @@ use std::{any::TypeId, iter, ops::Range, sync}; -use base_db::RootQueryDb; use expect_test::Expect; use hir_expand::{ AstId, ExpansionInfo, InFile, MacroCallId, MacroCallKind, MacroKind, @@ -75,7 +74,7 @@ fn check_errors(#[rust_analyzer::rust_fixture] ra_fixture: &str, expect: Expect) let editioned_file_id = ast_id.file_id.file_id().expect("macros inside macros are not supported"); - let ast = db.parse(editioned_file_id).syntax_node(); + let ast = editioned_file_id.parse(&db).syntax_node(); let ast_id_map = db.ast_id_map(ast_id.file_id); let node = ast_id_map.get_erased(ast_id.value).to_node(&ast); Some((node.text_range(), errors)) diff --git a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/proc_macros.rs b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/proc_macros.rs index bf04a500a57d..8c91cf6793a5 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/proc_macros.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/macro_expansion_tests/proc_macros.rs @@ -55,8 +55,8 @@ fn bar() {} # ![doc = "123..."] # ![attr2] # ![attr3] - #[cfg_attr(true , cfg(false ))] fn foo() {} - #[cfg(true )] fn bar() {} + #[cfg_attr (true , cfg (false ))] fn foo() {} + #[cfg (true )] fn bar() {} }"##]], ); } diff --git a/src/tools/rust-analyzer/crates/hir-def/src/nameres.rs b/src/tools/rust-analyzer/crates/hir-def/src/nameres.rs index 5fda1beab413..56b3f03f7b60 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/nameres.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/nameres.rs @@ -346,7 +346,7 @@ pub fn definition_source(&self, db: &dyn DefDatabase) -> InFile { match self { &ModuleOrigin::File { definition: editioned_file_id, .. } | &ModuleOrigin::CrateRoot { definition: editioned_file_id } => { - let sf = db.parse(editioned_file_id).tree(); + let sf = editioned_file_id.parse(db).tree(); InFile::new(editioned_file_id.into(), ModuleSource::SourceFile(sf)) } &ModuleOrigin::Inline { definition, definition_tree_id } => InFile::new( diff --git a/src/tools/rust-analyzer/crates/hir-def/src/nameres/collector.rs b/src/tools/rust-analyzer/crates/hir-def/src/nameres/collector.rs index 9c101c127b41..703f070dbaea 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/nameres/collector.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/nameres/collector.rs @@ -22,7 +22,7 @@ use la_arena::Idx; use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::SmallVec; -use span::{Edition, FileAstId, SyntaxContext}; +use span::{Edition, FileAstId, ROOT_ERASED_FILE_AST_ID, SyntaxContext}; use stdx::always; use syntax::ast; use triomphe::Arc; @@ -369,7 +369,14 @@ fn seed_with_top_level(&mut self) { self.inject_prelude(); - if matches!(item_tree.top_level_attrs(), AttrsOrCfg::CfgDisabled(_)) { + if let AttrsOrCfg::CfgDisabled(attrs) = item_tree.top_level_attrs() { + let (cfg_expr, _) = &**attrs; + self.def_map.diagnostics.push(DefDiagnostic::unconfigured_code( + self.def_map.root, + InFile::new(file_id.into(), ROOT_ERASED_FILE_AST_ID), + cfg_expr.clone(), + self.cfg_options.clone(), + )); return; } diff --git a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests.rs b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests.rs index fe55252e2540..08d98dff33d3 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests.rs @@ -4,7 +4,6 @@ mod macros; mod mod_resolution; -use base_db::RootQueryDb; use expect_test::{Expect, expect}; use test_fixture::WithFixture; diff --git a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/incremental.rs b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/incremental.rs index 5b75c078ecfa..0f1828abcead 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/incremental.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/incremental.rs @@ -1,6 +1,6 @@ use base_db::{ CrateDisplayName, CrateGraphBuilder, CrateName, CrateOrigin, CrateWorkspaceData, - DependencyBuilder, Env, RootQueryDb, SourceDatabase, + DependencyBuilder, Env, SourceDatabase, all_crates, }; use expect_test::{Expect, expect}; use intern::Symbol; @@ -56,11 +56,11 @@ pub fn foo() {} "#, ); - for &krate in db.all_crates().iter() { + for &krate in all_crates(&db).iter() { crate_def_map(&db, krate); } - let all_crates_before = db.all_crates(); + let all_crates_before = all_crates(&db); { // Add dependencies: c -> b, b -> a. @@ -100,15 +100,15 @@ pub fn foo() {} new_crate_graph.set_in_db(&mut db); } - let all_crates_after = db.all_crates(); + let all_crates_after = all_crates(&db); assert!( - Arc::ptr_eq(&all_crates_before, &all_crates_after), + std::sync::Arc::ptr_eq(&all_crates_before, &all_crates_after), "the all_crates list should not have been invalidated" ); execute_assert_events( &db, || { - for &krate in db.all_crates().iter() { + for &krate in all_crates(&db).iter() { crate_def_map(&db, krate); } }, @@ -167,22 +167,22 @@ fn no() {} "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "EnumVariants::of_", ] "#]], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -225,16 +225,16 @@ pub struct S {} "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "decl_macro_expander_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "macro_def_shim", "file_item_tree_query", @@ -245,7 +245,7 @@ pub struct S {} "#]], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -283,21 +283,21 @@ fn f() { foo } "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "crate_local_def_map", "proc_macros_for_crate_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "macro_def_shim", "file_item_tree_query", @@ -310,7 +310,7 @@ fn f() { foo } "#]], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -407,22 +407,22 @@ pub struct S {} "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "crate_local_def_map", "proc_macros_for_crate_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "decl_macro_expander_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "macro_def_shim", "file_item_tree_query", @@ -446,7 +446,7 @@ pub struct S {} "#]], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -524,16 +524,16 @@ fn quux() { 1$0 } "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "decl_macro_expander_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "macro_def_shim", "file_item_tree_query", @@ -571,7 +571,7 @@ fn quux() { 92 } &[("file_item_tree_query", 1), ("parse_macro_expansion_shim", 0)], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -611,7 +611,7 @@ impl Tr for () {} [ "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", ] "#]], @@ -629,7 +629,7 @@ impl Tr for () {} &[("file_item_tree_query", 1), ("parse", 1)], expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", diff --git a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/macros.rs b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/macros.rs index a013f8b2bc1a..f073cf777dda 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/macros.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/nameres/tests/macros.rs @@ -1,3 +1,4 @@ +use base_db::all_crates; use expect_test::expect; use itertools::Itertools; @@ -1129,7 +1130,7 @@ pub fn derive_macro_2(_item: TokenStream) -> TokenStream { } "#, ); - let krate = *db.all_crates().last().expect("no crate graph present"); + let krate = *all_crates(&db).last().expect("no crate graph present"); let def_map = crate_def_map(&db, krate); assert_eq!(def_map.data.exported_derives.len(), 1); @@ -1497,7 +1498,7 @@ macro_rules! legacy { () => () } fn proc_attr(a: TokenStream, b: TokenStream) -> TokenStream { a } "#, ); - let krate = *db.all_crates().last().expect("no crate graph present"); + let krate = *all_crates(&db).last().expect("no crate graph present"); let def_map = crate_def_map(&db, krate); let root_module = &def_map[def_map.root].scope; diff --git a/src/tools/rust-analyzer/crates/hir-def/src/test_db.rs b/src/tools/rust-analyzer/crates/hir-def/src/test_db.rs index 0d260279f98c..b854d2aa218d 100644 --- a/src/tools/rust-analyzer/crates/hir-def/src/test_db.rs +++ b/src/tools/rust-analyzer/crates/hir-def/src/test_db.rs @@ -3,8 +3,9 @@ use std::{fmt, panic, sync::Mutex}; use base_db::{ - Crate, CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Nonce, RootQueryDb, - SourceDatabase, SourceRoot, SourceRootId, SourceRootInput, + Crate, CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Nonce, SourceDatabase, + SourceRoot, SourceRootId, SourceRootInput, all_crates, relevant_crates, + set_all_crates_with_durability, }; use hir_expand::{InFile, files::FilePosition}; use salsa::Durability; @@ -49,7 +50,7 @@ fn default() -> Self { }; this.set_expand_proc_attr_macros_with_durability(true, Durability::HIGH); // This needs to be here otherwise `CrateGraphBuilder` panics. - this.set_all_crates(Arc::new(Box::new([]))); + set_all_crates_with_durability(&mut this, std::iter::empty(), Durability::HIGH); _ = base_db::LibraryRoots::builder(Default::default()) .durability(Durability::MEDIUM) .new(&this); @@ -145,7 +146,7 @@ fn nonce_and_revision(&self) -> (Nonce, salsa::Revision) { impl TestDB { pub(crate) fn fetch_test_crate(&self) -> Crate { - let all_crates = self.all_crates(); + let all_crates = all_crates(self); all_crates .iter() .copied() @@ -157,7 +158,7 @@ pub(crate) fn fetch_test_crate(&self) -> Crate { } pub(crate) fn module_for_file(&self, file_id: FileId) -> ModuleId { - for &krate in self.relevant_crates(file_id).iter() { + for &krate in relevant_crates(self, file_id).iter() { let crate_def_map = crate_def_map(self, krate); for (local_id, data) in crate_def_map.modules() { if data.origin.file_id().map(|file_id| file_id.file_id(self)) == Some(file_id) { @@ -288,7 +289,7 @@ fn block_at_position(&self, def_map: &DefMap, position: FilePosition) -> Option< let source_map = &Body::with_source_map(self, def_with_body).1; let scopes = ExprScopes::body_expr_scopes(self, def_with_body); - let root_syntax_node = self.parse(file_id).syntax_node(); + let root_syntax_node = file_id.parse(self).syntax_node(); let scope_iter = algo::ancestors_at_offset(&root_syntax_node, position.offset).filter_map(|node| { let block = ast::BlockExpr::cast(node)?; diff --git a/src/tools/rust-analyzer/crates/hir-expand/Cargo.toml b/src/tools/rust-analyzer/crates/hir-expand/Cargo.toml index 4fa476afb64a..43b0bea891e3 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/Cargo.toml +++ b/src/tools/rust-analyzer/crates/hir-expand/Cargo.toml @@ -23,7 +23,6 @@ triomphe.workspace = true query-group.workspace = true salsa.workspace = true salsa-macros.workspace = true -arrayvec.workspace = true thin-vec.workspace = true # local deps diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/attrs.rs b/src/tools/rust-analyzer/crates/hir-expand/src/attrs.rs index e3f10b212904..49baecb90cd5 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/attrs.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/attrs.rs @@ -4,20 +4,8 @@ //! [`expand_cfg_attr_with_doc_comments()`]. It is used to implement all attribute lowering //! in r-a. Its basic job is to list attributes; however, attributes do not necessarily map //! into [`ast::Attr`], because `cfg_attr` can map to zero, one, or more attributes -//! (`#[cfg_attr(predicate, attr1, attr2, ...)]`). To bridge this gap, this module defines -//! [`Meta`], which represents a desugared attribute. Various bits of r-a need different -//! things from [`Meta`], therefore it contains many parts. The basic idea is: -//! -//! - There are three kinds of attributes, `path = value`, `path`, and `path(token_tree)`. -//! - Most bits of rust-analyzer only need to deal with some paths. Therefore, we keep -//! the path only if it has up to 2 segments, or one segment for `path = value`. -//! We also only keep the value in `path = value` if it is a literal. However, we always -//! save the all relevant ranges of attributes (the path range, and the full attribute range) -//! for parts of r-a (e.g. name resolution) that need a faithful representation of the -//! attribute. -//! -//! [`expand_cfg_attr()`] expands `cfg_attr`s as it goes (as its name implies), to list -//! all attributes. +//! (`#[cfg_attr(predicate, attr1, attr2, ...)]`). [`expand_cfg_attr()`] expands `cfg_attr`s +//! as it goes (as its name implies), to list all attributes. //! //! Another thing to note is that we need to be able to map an attribute back to a range //! (for diagnostic purposes etc.). This is only ever needed for attributes that participate @@ -26,26 +14,18 @@ //! place (here) and one function ([`is_item_tree_filtered_attr()`]) that decides whether //! an attribute participate in name resolution. -use std::{ - borrow::Cow, cell::OnceCell, convert::Infallible, fmt, iter::Peekable, ops::ControlFlow, -}; +use std::{borrow::Cow, cell::OnceCell, convert::Infallible, fmt, ops::ControlFlow}; -use ::tt::{TextRange, TextSize}; -use arrayvec::ArrayVec; +use ::tt::TextRange; use base_db::Crate; use cfg::{CfgExpr, CfgOptions}; use either::Either; use intern::Interned; use itertools::Itertools; use mbe::{DelimiterKind, Punct}; -use parser::T; use smallvec::SmallVec; use span::{RealSpanMap, Span, SyntaxContext}; -use syntax::{ - AstNode, NodeOrToken, SyntaxNode, SyntaxToken, - ast::{self, TokenTreeChildren}, - unescape, -}; +use syntax::{AstNode, SmolStr, ast, unescape}; use syntax_bridge::DocCommentDesugarMode; use crate::{ @@ -56,207 +36,75 @@ tt::{self, TopSubtree}, }; -#[derive(Debug)] -pub struct AttrPath { - /// This can be empty if the path is not of 1 or 2 segments exactly. - pub segments: ArrayVec, - pub range: TextRange, - // FIXME: This shouldn't be textual, `#[test]` needs name resolution. - // And if textual, it shouldn't be here, it should be in hir-def/src/attrs.rs. But some macros - // fully qualify `test` as `core::prelude::vX::test`, and this is more than 2 segments, so hir-def - // attrs can't find it. But this will mean we have to push every up-to-4-segments path, which - // may impact perf. So it was easier to just hack it here. - pub is_test: bool, +pub trait AstPathExt { + fn is1(&self, segment: &str) -> bool; + + fn as_one_segment(&self) -> Option; + + fn as_up_to_two_segment(&self) -> Option<(SmolStr, Option)>; } -impl AttrPath { - #[inline] - fn extract(path: &ast::Path) -> Self { - let mut is_test = false; - let segments = (|| { - let mut segments = ArrayVec::new(); - let segment2 = path.segment()?.name_ref()?.syntax().first_token()?; - if segment2.text() == "test" { - // `#[test]` or `#[core::prelude::vX::test]`. - is_test = true; - } - let segment1 = path.qualifier(); - if let Some(segment1) = segment1 { - if segment1.qualifier().is_some() { - None - } else { - let segment1 = segment1.segment()?.name_ref()?.syntax().first_token()?; - segments.push(segment1); - segments.push(segment2); - Some(segments) - } - } else { - segments.push(segment2); - Some(segments) - } - })(); - AttrPath { - segments: segments.unwrap_or(ArrayVec::new()), - range: path.syntax().text_range(), - is_test, - } +impl AstPathExt for ast::Path { + fn is1(&self, segment: &str) -> bool { + self.as_one_segment().is_some_and(|it| it == segment) } - #[inline] - pub fn is1(&self, segment: &str) -> bool { - self.segments.len() == 1 && self.segments[0].text() == segment + fn as_one_segment(&self) -> Option { + Some(self.as_single_name_ref()?.text().into()) + } + + fn as_up_to_two_segment(&self) -> Option<(SmolStr, Option)> { + let parent = self.qualifier().as_one_segment(); + let this = self.segment()?.name_ref()?.text().into(); + if let Some(parent) = parent { Some((parent, Some(this))) } else { Some((this, None)) } } } -#[derive(Debug)] -pub enum Meta { - /// `name` is `None` if not a single token. `value` is a literal or `None`. - NamedKeyValue { - path_range: TextRange, - name: Option, - value: Option, - }, - TokenTree { - path: AttrPath, - tt: ast::TokenTree, - }, - Path { - path: AttrPath, - }, -} - -impl Meta { - #[inline] - pub fn path_range(&self) -> TextRange { - match self { - Meta::NamedKeyValue { path_range, .. } => *path_range, - Meta::TokenTree { path, .. } | Meta::Path { path } => path.range, - } +impl AstPathExt for Option { + fn is1(&self, segment: &str) -> bool { + self.as_ref().is_some_and(|it| it.is1(segment)) } - fn extract(iter: &mut Peekable) -> Option<(Self, TextSize)> { - let mut start_offset = None; - if let Some(NodeOrToken::Token(colon1)) = iter.peek() - && colon1.kind() == T![:] + fn as_one_segment(&self) -> Option { + self.as_ref().and_then(|it| it.as_one_segment()) + } + + fn as_up_to_two_segment(&self) -> Option<(SmolStr, Option)> { + self.as_ref().and_then(|it| it.as_up_to_two_segment()) + } +} + +pub trait AstKeyValueMetaExt { + fn value_string(&self) -> Option; +} + +impl AstKeyValueMetaExt for ast::KeyValueMeta { + fn value_string(&self) -> Option { + if let Some(ast::Expr::Literal(value)) = self.expr() + && let ast::LiteralKind::String(value) = value.kind() + && let Ok(value) = value.value() { - start_offset = Some(colon1.text_range().start()); - iter.next(); - iter.next_if(|it| it.as_token().is_some_and(|it| it.kind() == T![:])); - } - let first_segment = iter - .next_if(|it| it.as_token().is_some_and(|it| it.kind().is_any_identifier()))? - .into_token()?; - let mut is_test = first_segment.text() == "test"; - let start_offset = start_offset.unwrap_or_else(|| first_segment.text_range().start()); - - let mut segments_len = 1; - let mut second_segment = None; - let mut path_range = first_segment.text_range(); - while iter.peek().and_then(NodeOrToken::as_token).is_some_and(|it| it.kind() == T![:]) - && let _ = iter.next() - && iter.peek().and_then(NodeOrToken::as_token).is_some_and(|it| it.kind() == T![:]) - && let _ = iter.next() - && let Some(NodeOrToken::Token(segment)) = iter.peek() - && segment.kind().is_any_identifier() - { - segments_len += 1; - is_test = segment.text() == "test"; - second_segment = Some(segment.clone()); - path_range = TextRange::new(path_range.start(), segment.text_range().end()); - iter.next(); - } - - let segments = |first, second| { - let mut segments = ArrayVec::new(); - if segments_len <= 2 { - segments.push(first); - if let Some(second) = second { - segments.push(second); - } - } - segments - }; - let meta = match iter.peek() { - Some(NodeOrToken::Token(eq)) if eq.kind() == T![=] => { - iter.next(); - let value = match iter.peek() { - Some(NodeOrToken::Token(token)) if token.kind().is_literal() => { - // No need to consume it, it will be consumed by `extract_and_eat_comma()`. - Some(token.clone()) - } - _ => None, - }; - let name = if second_segment.is_none() { Some(first_segment) } else { None }; - Meta::NamedKeyValue { path_range, name, value } - } - Some(NodeOrToken::Node(tt)) => Meta::TokenTree { - path: AttrPath { - segments: segments(first_segment, second_segment), - range: path_range, - is_test, - }, - tt: tt.clone(), - }, - _ => Meta::Path { - path: AttrPath { - segments: segments(first_segment, second_segment), - range: path_range, - is_test, - }, - }, - }; - Some((meta, start_offset)) - } - - fn extract_possibly_unsafe( - iter: &mut Peekable, - container: &ast::TokenTree, - ) -> Option<(Self, TextRange)> { - if iter.peek().is_some_and(|it| it.as_token().is_some_and(|it| it.kind() == T![unsafe])) { - iter.next(); - let tt = iter.next()?.into_node()?; - let result = Self::extract(&mut TokenTreeChildren::new(&tt).peekable()).map( - |(meta, start_offset)| (meta, TextRange::new(start_offset, tt_end_offset(&tt))), - ); - while iter.next().is_some_and(|it| it.as_token().is_none_or(|it| it.kind() != T![,])) {} - result + Some((*value).into()) } else { - Self::extract(iter).map(|(meta, start_offset)| { - let end_offset = 'find_end_offset: { - for it in iter { - if let NodeOrToken::Token(it) = it - && it.kind() == T![,] - { - break 'find_end_offset it.text_range().start(); - } - } - tt_end_offset(container) - }; - (meta, TextRange::new(start_offset, end_offset)) - }) + None } } } -fn tt_end_offset(tt: &ast::TokenTree) -> TextSize { - tt.syntax().last_token().unwrap().text_range().start() -} - -/// The callback is passed a desugared form of the attribute ([`Meta`]), a [`SyntaxNode`] fully containing it -/// (note: it may not be the direct parent), the range within the [`SyntaxNode`] bounding the attribute, -/// and the outermost `ast::Attr`. Note that one node may map to multiple [`Meta`]s due to `cfg_attr`. +/// The callback is passed the attribute and the outermost `ast::Attr`. +/// Note that one node may map to multiple [`Meta`]s due to `cfg_attr`. +/// +/// `unsafe(attr)` are passed the inner attribute for now. #[inline] pub fn expand_cfg_attr<'a, BreakValue>( attrs: impl Iterator, cfg_options: impl FnMut() -> &'a CfgOptions, - mut callback: impl FnMut(Meta, &SyntaxNode, TextRange, &ast::Attr) -> ControlFlow, + mut callback: impl FnMut(ast::Meta, ast::Attr) -> ControlFlow, ) -> Option { expand_cfg_attr_with_doc_comments::( attrs.map(Either::Left), cfg_options, - move |Either::Left((meta, container, range, top_attr))| { - callback(meta, container, range, top_attr) - }, + move |Either::Left((meta, top_attr))| callback(meta, top_attr), ) } @@ -264,66 +112,47 @@ pub fn expand_cfg_attr<'a, BreakValue>( pub fn expand_cfg_attr_with_doc_comments<'a, DocComment, BreakValue>( mut attrs: impl Iterator>, mut cfg_options: impl FnMut() -> &'a CfgOptions, - mut callback: impl FnMut( - Either<(Meta, &SyntaxNode, TextRange, &ast::Attr), DocComment>, - ) -> ControlFlow, + mut callback: impl FnMut(Either<(ast::Meta, ast::Attr), DocComment>) -> ControlFlow, ) -> Option { let mut stack = SmallVec::<[_; 1]>::new(); - let result = attrs.try_for_each(|top_attr| { - let top_attr = match top_attr { - Either::Left(it) => it, - Either::Right(comment) => return callback(Either::Right(comment)), - }; - if let Some((attr_name, tt)) = top_attr.as_simple_call() - && attr_name == "cfg_attr" - { - let mut tt_iter = TokenTreeChildren::new(&tt).peekable(); - let cfg = cfg::CfgExpr::parse_from_ast(&mut tt_iter); - if cfg_options().check(&cfg) != Some(false) { - stack.push((tt_iter, tt)); - while let Some((tt_iter, tt)) = stack.last_mut() { - let Some((attr, range)) = Meta::extract_possibly_unsafe(tt_iter, tt) else { - stack.pop(); - continue; - }; - if let Meta::TokenTree { path, tt: nested_tt } = &attr - && path.is1("cfg_attr") - { - let mut nested_tt_iter = TokenTreeChildren::new(nested_tt).peekable(); - let cfg = cfg::CfgExpr::parse_from_ast(&mut nested_tt_iter); - if cfg_options().check(&cfg) != Some(false) { - stack.push((nested_tt_iter, nested_tt.clone())); - } - } else { - callback(Either::Left((attr, tt.syntax(), range, &top_attr)))?; + loop { + let (mut meta, top_attr) = if let Some(it) = stack.pop() { + it + } else { + let attr = attrs.next()?; + match attr { + Either::Left(attr) => { + let Some(meta) = attr.meta() else { continue }; + stack.push((meta, attr)); + } + Either::Right(doc_comment) => { + if let ControlFlow::Break(break_value) = callback(Either::Right(doc_comment)) { + return Some(break_value); } } } - } else if let Some(ast_meta) = top_attr.meta() - && let Some(path) = ast_meta.path() - { - let path = AttrPath::extract(&path); - let meta = if let Some(tt) = ast_meta.token_tree() { - Meta::TokenTree { path, tt } - } else if let Some(value) = ast_meta.expr() { - let value = - if let ast::Expr::Literal(value) = value { Some(value.token()) } else { None }; - let name = - if path.segments.len() == 1 { Some(path.segments[0].clone()) } else { None }; - Meta::NamedKeyValue { name, value, path_range: path.range } - } else { - Meta::Path { path } - }; - callback(Either::Left(( - meta, - ast_meta.syntax(), - ast_meta.syntax().text_range(), - &top_attr, - )))?; + continue; + }; + + while let ast::Meta::UnsafeMeta(unsafe_meta) = &meta { + let Some(inner) = unsafe_meta.meta() else { continue }; + meta = inner; } - ControlFlow::Continue(()) - }); - result.break_value() + + if let ast::Meta::CfgAttrMeta(meta) = meta { + let Some(cfg_predicate) = meta.cfg_predicate() else { continue }; + let cfg_predicate = CfgExpr::parse_from_ast(cfg_predicate); + if cfg_options().check(&cfg_predicate) != Some(false) { + let prev_stack_len = stack.len(); + stack.extend(meta.metas().map(|meta| (meta, top_attr.clone()))); + stack[prev_stack_len..].reverse(); + } + } else { + if let ControlFlow::Break(break_value) = callback(Either::Left((meta, top_attr))) { + return Some(break_value); + } + } + } } #[inline] @@ -351,39 +180,33 @@ pub(crate) fn is_item_tree_filtered_attr(name: &str) -> bool { pub fn collect_item_tree_attrs<'a, BreakValue>( owner: &dyn ast::HasAttrs, cfg_options: impl Fn() -> &'a CfgOptions, - mut on_attr: impl FnMut(Meta, &SyntaxNode, &ast::Attr, TextRange) -> ControlFlow, + mut on_attr: impl FnMut(ast::Meta, ast::Attr) -> ControlFlow, ) -> Option> { let attrs = ast::attrs_including_inner(owner); expand_cfg_attr( attrs, || cfg_options(), - |attr, container, range, top_attr| { + |attr, top_attr| { // We filter builtin attributes that we don't need for nameres, because this saves memory. // I only put the most common attributes, but if some attribute becomes common feel free to add it. // Notice, however: for an attribute to be filtered out, it *must* not be shadowable with a macro! let filter = match &attr { - Meta::NamedKeyValue { name: Some(name), .. } => { - is_item_tree_filtered_attr(name.text()) - } - Meta::TokenTree { path, tt } if path.segments.len() == 1 => { - let name = path.segments[0].text(); - if name == "cfg" { - let cfg = - CfgExpr::parse_from_ast(&mut TokenTreeChildren::new(tt).peekable()); - if cfg_options().check(&cfg) == Some(false) { - return ControlFlow::Break(Either::Right(cfg)); - } - true - } else { - is_item_tree_filtered_attr(name) + ast::Meta::CfgMeta(attr) => { + let Some(cfg_predicate) = attr.cfg_predicate() else { + return ControlFlow::Continue(()); + }; + let cfg = CfgExpr::parse_from_ast(cfg_predicate); + if cfg_options().check(&cfg) == Some(false) { + return ControlFlow::Break(Either::Right(cfg)); } + true } - Meta::Path { path } => { - path.segments.len() == 1 && is_item_tree_filtered_attr(path.segments[0].text()) - } - _ => false, + _ => attr + .path() + .and_then(|path| path.as_one_segment()) + .is_some_and(|segment| is_item_tree_filtered_attr(&segment)), }; - if !filter && let ControlFlow::Break(v) = on_attr(attr, container, top_attr, range) { + if !filter && let ControlFlow::Break(v) = on_attr(attr, top_attr) { return ControlFlow::Break(Either::Left(v)); } ControlFlow::Continue(()) @@ -540,34 +363,32 @@ pub fn item_tree_index(self) -> u32 { } /// Returns the containing `ast::Attr` (note that it may contain other attributes as well due - /// to `cfg_attr`), a `SyntaxNode` guaranteed to contain the attribute, the full range of the - /// attribute, and its desugared [`Meta`]. + /// to `cfg_attr`) and its [`ast::Meta`]. pub fn find_attr_range( self, db: &dyn ExpandDatabase, krate: Crate, owner: AstId, - ) -> (ast::Attr, SyntaxNode, TextRange, Meta) { + ) -> (ast::Attr, ast::Meta) { self.find_attr_range_with_source(db, krate, &owner.to_node(db)) } /// Returns the containing `ast::Attr` (note that it may contain other attributes as well due - /// to `cfg_attr`), a `SyntaxNode` guaranteed to contain the attribute, the full range of the - /// attribute, and its desugared [`Meta`]. + /// to `cfg_attr`) and its [`ast::Meta`]. pub fn find_attr_range_with_source( self, db: &dyn ExpandDatabase, krate: Crate, owner: &dyn ast::HasAttrs, - ) -> (ast::Attr, SyntaxNode, TextRange, Meta) { + ) -> (ast::Attr, ast::Meta) { let cfg_options = OnceCell::new(); let mut index = 0; let result = collect_item_tree_attrs( owner, || cfg_options.get_or_init(|| krate.cfg_options(db)), - |meta, container, top_attr, range| { + |meta, top_attr| { if index == self.id { - return ControlFlow::Break((top_attr.clone(), container.clone(), range, meta)); + return ControlFlow::Break((top_attr, meta)); } index += 1; ControlFlow::Continue(()) @@ -588,9 +409,12 @@ pub fn find_derive_range( owner: AstId, derive_index: u32, ) -> TextRange { - let (_, _, derive_attr_range, derive_attr) = self.find_attr_range(db, krate, owner); - let Meta::TokenTree { tt, .. } = derive_attr else { - return derive_attr_range; + let (_, derive_attr) = self.find_attr_range(db, krate, owner); + let ast::Meta::TokenTreeMeta(derive_attr) = derive_attr else { + return derive_attr.syntax().text_range(); + }; + let Some(tt) = derive_attr.token_tree() else { + return derive_attr.syntax().text_range(); }; // Fake the span map, as we don't really need spans here, just the offsets of the node in the file. let span_map = RealSpanMap::absolute(span::EditionedFileId::current_edition( @@ -605,11 +429,11 @@ pub fn find_derive_range( let Some((_, _, derive_tts)) = parse_path_comma_token_tree(db, &tt).nth(derive_index as usize) else { - return derive_attr_range; + return derive_attr.syntax().text_range(); }; let (Some(first_span), Some(last_span)) = (derive_tts.first_span(), derive_tts.last_span()) else { - return derive_attr_range; + return derive_attr.syntax().text_range(); }; let start = first_span.range.start(); let end = last_span.range.end(); diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/builtin/fn_macro.rs b/src/tools/rust-analyzer/crates/hir-expand/src/builtin/fn_macro.rs index b3572a1cefcc..9962677a9da6 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/builtin/fn_macro.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/builtin/fn_macro.rs @@ -828,7 +828,7 @@ fn include_expand( let span_map = db.real_span_map(editioned_file_id); // FIXME: Parse errors ExpandResult::ok(syntax_node_to_token_tree( - &db.parse(editioned_file_id).syntax_node(), + &editioned_file_id.parse(db).syntax_node(), SpanMap::RealSpanMap(span_map), span, syntax_bridge::DocCommentDesugarMode::ProcMacro, diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/cfg_process.rs b/src/tools/rust-analyzer/crates/hir-expand/src/cfg_process.rs index ccef9168ac3a..6258fac0e992 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/cfg_process.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/cfg_process.rs @@ -8,12 +8,12 @@ use smallvec::SmallVec; use syntax::{ AstNode, PreorderWithTokens, SyntaxElement, SyntaxNode, SyntaxToken, WalkEvent, - ast::{self, HasAttrs, TokenTreeChildren}, + ast::{self, HasAttrs}, }; use syntax_bridge::DocCommentDesugarMode; use crate::{ - attrs::{AttrId, Meta, expand_cfg_attr, is_item_tree_filtered_attr}, + attrs::{AstPathExt, AttrId, expand_cfg_attr, is_item_tree_filtered_attr}, db::ExpandDatabase, fixup::{self, SyntaxFixupUndoInfo}, span_map::SpanMapRef, @@ -24,7 +24,7 @@ #[derive(Debug)] struct ExpandedAttrToProcess { - range: TextRange, + attr: ast::Meta, } #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -143,42 +143,29 @@ fn macro_input_callback( }); attrs_idx = 0; - let strip_current_item = expand_cfg_attr( - node_attrs, - &cfg_options, - |attr, _container, range, top_attr| { + let strip_current_item = + expand_cfg_attr(node_attrs, &cfg_options, |attr, top_attr| { // Find the attr. while attrs[attrs_idx].range != top_attr.syntax().text_range() { attrs_idx += 1; } let mut strip_current_attr = false; - match attr { - Meta::NamedKeyValue { name, .. } => { - if name - .is_none_or(|name| !is_item_tree_filtered_attr(name.text())) - { - strip_current_attr = should_strip_attr(); - } - } - Meta::TokenTree { path, tt } => { - if path.is1("cfg") { - let cfg_expr = CfgExpr::parse_from_ast( - &mut TokenTreeChildren::new(&tt).peekable(), - ); + match &attr { + ast::Meta::CfgMeta(attr) => { + if let Some(cfg_predicate) = attr.cfg_predicate() { + let cfg_expr = CfgExpr::parse_from_ast(cfg_predicate); if cfg_options().check(&cfg_expr) == Some(false) { return ControlFlow::Break(ItemIsCfgedOut); } strip_current_attr = true; - } else if path.segments.len() != 1 - || !is_item_tree_filtered_attr(path.segments[0].text()) - { - strip_current_attr = should_strip_attr(); } } - Meta::Path { path } => { - if path.segments.len() != 1 - || !is_item_tree_filtered_attr(path.segments[0].text()) + _ => { + if attr + .path() + .as_one_segment() + .is_none_or(|name| !is_item_tree_filtered_attr(&name)) { strip_current_attr = should_strip_attr(); } @@ -188,12 +175,11 @@ fn macro_input_callback( if !strip_current_attr { attrs[attrs_idx] .expanded_attrs - .push(ExpandedAttrToProcess { range }); + .push(ExpandedAttrToProcess { attr }); } ControlFlow::Continue(()) - }, - ); + }); attrs_idx = 0; if strip_current_item.is_some() { @@ -248,7 +234,7 @@ fn macro_input_callback( }; match ast_attr.next_expanded_attr { NextExpandedAttrState::NotStarted => { - if token_range.start() >= expanded_attr.range.start() { + if token_range.start() >= expanded_attr.attr.syntax().text_range().start() { // We started the next attribute. let mut insert_tokens = Vec::with_capacity(3); insert_tokens.push(tt::Leaf::Punct(tt::Punct { @@ -278,7 +264,7 @@ fn macro_input_callback( } } NextExpandedAttrState::InTheMiddle => { - if token_range.start() >= expanded_attr.range.end() { + if token_range.start() >= expanded_attr.attr.syntax().text_range().end() { // Finished the current attribute. let insert_tokens = vec![tt::Leaf::Punct(tt::Punct { char: ']', @@ -329,12 +315,3 @@ pub(crate) fn attr_macro_input_to_token_tree( fixups.undo_info, ) } - -pub fn check_cfg_attr_value( - db: &dyn ExpandDatabase, - attr: &ast::TokenTree, - krate: Crate, -) -> Option { - let cfg_expr = CfgExpr::parse_from_ast(&mut TokenTreeChildren::new(attr).peekable()); - krate.cfg_options(db).check(&cfg_expr) -} diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/db.rs b/src/tools/rust-analyzer/crates/hir-expand/src/db.rs index 020731cf9aca..8dddddfabb7a 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/db.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/db.rs @@ -1,6 +1,6 @@ //! Defines database & queries for macro expansion. -use base_db::{Crate, RootQueryDb}; +use base_db::{Crate, SourceDatabase}; use mbe::MatchedArmIndex; use span::{AstIdMap, Edition, Span, SyntaxContext}; use syntax::{AstNode, Parse, SyntaxError, SyntaxNode, SyntaxToken, T, ast}; @@ -11,7 +11,6 @@ AstId, BuiltinAttrExpander, BuiltinDeriveExpander, BuiltinFnLikeExpander, EagerCallInfo, EagerExpander, EditionedFileId, ExpandError, ExpandResult, ExpandTo, FileRange, HirFileId, MacroCallId, MacroCallKind, MacroCallLoc, MacroDefId, MacroDefKind, - attrs::Meta, builtin::pseudo_derive_attr_expansion, cfg_process::attr_macro_input_to_token_tree, declarative::DeclarativeMacroExpander, @@ -48,7 +47,7 @@ pub enum TokenExpander { } #[query_group::query_group] -pub trait ExpandDatabase: RootQueryDb { +pub trait ExpandDatabase: SourceDatabase { /// The proc macros. Do not use this! Use `proc_macros_for_crate()` instead. #[salsa::input] fn proc_macros(&self) -> Arc; @@ -239,8 +238,15 @@ pub fn expand_speculative( MacroCallKind::Attr { censored_attr_ids: attr_ids, .. } => { if loc.def.is_attribute_derive() { // for pseudo-derive expansion we actually pass the attribute itself only - ast::Attr::cast(speculative_args.clone()).and_then(|attr| attr.token_tree()).map( - |token_tree| { + ast::Attr::cast(speculative_args.clone()) + .and_then(|attr| { + if let ast::Meta::TokenTreeMeta(meta) = attr.meta()? { + meta.token_tree() + } else { + None + } + }) + .map(|token_tree| { let mut tree = syntax_node_to_token_tree( token_tree.syntax(), span_map, @@ -250,26 +256,26 @@ pub fn expand_speculative( tree.set_top_subtree_delimiter_kind(tt::DelimiterKind::Invisible); tree.set_top_subtree_delimiter_span(tt::DelimSpan::from_single(span)); tree - }, - ) + }) } else { // Attributes may have an input token tree, build the subtree and map for this as well // then try finding a token id for our token if it is inside this input subtree. let item = ast::Item::cast(speculative_args.clone())?; - let (_, _, _, meta) = + let (_, meta) = attr_ids.invoc_attr().find_attr_range_with_source(db, loc.krate, &item); - match meta { - Meta::TokenTree { tt, .. } => { - let mut attr_arg = syntax_bridge::syntax_node_to_token_tree( - tt.syntax(), - span_map, - span, - DocCommentDesugarMode::ProcMacro, - ); - attr_arg.set_top_subtree_delimiter_kind(tt::DelimiterKind::Invisible); - Some(attr_arg) - } - _ => None, + if let ast::Meta::TokenTreeMeta(meta) = meta + && let Some(tt) = meta.token_tree() + { + let mut attr_arg = syntax_bridge::syntax_node_to_token_tree( + tt.syntax(), + span_map, + span, + DocCommentDesugarMode::ProcMacro, + ); + attr_arg.set_top_subtree_delimiter_kind(tt::DelimiterKind::Invisible); + Some(attr_arg) + } else { + None } } } @@ -343,7 +349,7 @@ fn ast_id_map(db: &dyn ExpandDatabase, file_id: HirFileId) -> AstIdMap { /// file or a macro expansion. fn parse_or_expand(db: &dyn ExpandDatabase, file_id: HirFileId) -> SyntaxNode { match file_id { - HirFileId::FileId(file_id) => db.parse(file_id).syntax_node(), + HirFileId::FileId(file_id) => file_id.parse(db).syntax_node(), HirFileId::MacroFile(macro_file) => { db.parse_macro_expansion(macro_file).value.0.syntax_node() } @@ -389,7 +395,7 @@ pub(crate) fn parse_with_map( ) -> (Parse, SpanMap) { match file_id { HirFileId::FileId(file_id) => { - (db.parse(file_id).to_syntax(), SpanMap::RealSpanMap(db.real_span_map(file_id))) + (file_id.parse(db).to_syntax(), SpanMap::RealSpanMap(db.real_span_map(file_id))) } HirFileId::MacroFile(macro_file) => { let (parse, map) = db.parse_macro_expansion(macro_file).value; @@ -501,11 +507,11 @@ fn macro_arg(db: &dyn ExpandDatabase, id: MacroCallId) -> MacroArgResult { } MacroCallKind::Attr { ast_id, censored_attr_ids: attr_ids, .. } => { let node = ast_id.to_ptr(db).to_node(&root); - let range = attr_ids - .invoc_attr() - .find_attr_range_with_source(db, loc.krate, &node) - .3 - .path_range(); + let (_, attr) = attr_ids.invoc_attr().find_attr_range_with_source(db, loc.krate, &node); + let range = attr + .path() + .map(|path| path.syntax().text_range()) + .unwrap_or_else(|| attr.syntax().text_range()); let span = map.span_for_range(range); let is_derive = matches!(loc.def.kind, MacroDefKind::BuiltInAttr(_, expander) if expander.is_derive()); diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/declarative.rs b/src/tools/rust-analyzer/crates/hir-expand/src/declarative.rs index 172641227599..4b2c6e73517b 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/declarative.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/declarative.rs @@ -6,7 +6,7 @@ use span::{Edition, Span, SyntaxContext}; use stdx::TupleExt; use syntax::{ - AstNode, AstToken, + AstNode, ast::{self, HasAttrs}, }; use syntax_bridge::DocCommentDesugarMode; @@ -15,7 +15,7 @@ use crate::{ AstId, ExpandError, ExpandErrorKind, ExpandResult, HirFileId, Lookup, MacroCallId, MacroCallStyle, - attrs::{Meta, expand_cfg_attr}, + attrs::{AstKeyValueMetaExt, AstPathExt, expand_cfg_attr}, db::ExpandDatabase, hygiene::{Transparency, apply_mark}, tt, @@ -92,11 +92,10 @@ pub(crate) fn expander( expand_cfg_attr( node.attrs(), || cfg_options.get_or_init(|| def_crate.cfg_options(db)), - |attr, _, _, _| { - if let Meta::NamedKeyValue { name: Some(name), value, .. } = attr - && name.text() == "rustc_macro_transparency" - && let Some(value) = value.and_then(ast::String::cast) - && let Ok(value) = value.value() + |attr, _| { + if let ast::Meta::KeyValueMeta(attr) = attr + && attr.path().is1("rustc_macro_transparency") + && let Some(value) = attr.value_string() { match &*value { "transparent" => ControlFlow::Break(Transparency::Transparent), diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/files.rs b/src/tools/rust-analyzer/crates/hir-expand/src/files.rs index fce92c8a3e5e..71da560b15f1 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/files.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/files.rs @@ -198,7 +198,7 @@ trait FileIdToSyntax: Copy { impl FileIdToSyntax for EditionedFileId { fn file_syntax(self, db: &dyn db::ExpandDatabase) -> SyntaxNode { - db.parse(self).syntax_node() + self.parse(db).syntax_node() } } impl FileIdToSyntax for MacroCallId { @@ -333,8 +333,8 @@ pub fn original_syntax_node_rooted( )?; let kind = self.kind(); - let value = db - .parse(editioned_file_id) + let value = editioned_file_id + .parse(db) .syntax_node() .covering_element(range) .ancestors() @@ -521,7 +521,7 @@ pub fn original_ast_node_rooted(self, db: &dyn db::ExpandDatabase) -> Option InFile { ast_id.with_value(ast_id.to_node(db).syntax().clone()) } MacroCallKind::Derive { ast_id, derive_attr_index, .. } => { - // FIXME: handle `cfg_attr` - let (attr, _, _, _) = derive_attr_index.find_attr_range(db, self.krate, *ast_id); + let (_, attr) = derive_attr_index.find_attr_range(db, self.krate, *ast_id); ast_id.with_value(attr.syntax().clone()) } MacroCallKind::Attr { ast_id, censored_attr_ids: attr_ids, .. } => { if self.def.is_attribute_derive() { - let (attr, _, _, _) = - attr_ids.invoc_attr().find_attr_range(db, self.krate, *ast_id); + let (_, attr) = attr_ids.invoc_attr().find_attr_range(db, self.krate, *ast_id); ast_id.with_value(attr.syntax().clone()) } else { ast_id.with_value(ast_id.to_node(db).syntax().clone()) @@ -770,11 +767,11 @@ pub fn original_call_range(self, db: &dyn ExpandDatabase, krate: Crate) -> FileR } MacroCallKind::Derive { ast_id, derive_attr_index, .. } => { // FIXME: should be the range of the macro name, not the whole derive - derive_attr_index.find_attr_range(db, krate, ast_id).2 + derive_attr_index.find_attr_range(db, krate, ast_id).1.syntax().text_range() } // FIXME: handle `cfg_attr` MacroCallKind::Attr { ast_id, censored_attr_ids: attr_ids, .. } => { - attr_ids.invoc_attr().find_attr_range(db, krate, ast_id).2 + attr_ids.invoc_attr().find_attr_range(db, krate, ast_id).1.syntax().text_range() } }; diff --git a/src/tools/rust-analyzer/crates/hir-expand/src/span_map.rs b/src/tools/rust-analyzer/crates/hir-expand/src/span_map.rs index 71d0b880caa1..aa8603341b3b 100644 --- a/src/tools/rust-analyzer/crates/hir-expand/src/span_map.rs +++ b/src/tools/rust-analyzer/crates/hir-expand/src/span_map.rs @@ -86,7 +86,7 @@ pub(crate) fn real_span_map( let mut pairs = vec![(syntax::TextSize::new(0), span::ROOT_ERASED_FILE_AST_ID)]; let ast_id_map = db.ast_id_map(editioned_file_id.into()); - let tree = db.parse(editioned_file_id).tree(); + let tree = editioned_file_id.parse(db).tree(); // This is an incrementality layer. Basically we can't use absolute ranges for our spans as that // would mean we'd invalidate everything whenever we type. So instead we make the text ranges // relative to some AstIds reducing the risk of invalidation as typing somewhere no longer diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/builtin_derive.rs b/src/tools/rust-analyzer/crates/hir-ty/src/builtin_derive.rs index 92629b7a0532..eb3922f4b623 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/builtin_derive.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/builtin_derive.rs @@ -174,8 +174,11 @@ pub fn predicates<'db>(db: &'db dyn HirDatabase, impl_: BuiltinDeriveImplId) -> if matches!(loc.adt, AdtId::EnumId(_)) { // Enums don't have extra bounds. GenericPredicates::from_explicit_own_predicates(StoredEarlyBinder::bind( - Clauses::new_from_slice(adt_predicates.explicit_predicates().skip_binder()) - .store(), + Clauses::new_from_iter( + interner, + adt_predicates.own_explicit_predicates().skip_binder(), + ) + .store(), )) } else { simple_trait_predicates(interner, loc, generic_params, adt_predicates, trait_id) @@ -191,7 +194,7 @@ pub fn predicates<'db>(db: &'db dyn HirDatabase, impl_: BuiltinDeriveImplId) -> )); }; let duplicated_bounds = - adt_predicates.explicit_predicates().iter_identity_copied().filter_map(|pred| { + adt_predicates.explicit_predicates().iter_identity().filter_map(|pred| { let mentions_pointee = pred.visit_with(&mut MentionsPointee { pointee_param_idx }).is_break(); if !mentions_pointee { @@ -212,7 +215,7 @@ pub fn predicates<'db>(db: &'db dyn HirDatabase, impl_: BuiltinDeriveImplId) -> interner, adt_predicates .explicit_predicates() - .iter_identity_copied() + .iter_identity() .chain(duplicated_bounds) .chain(unsize_bound), ) @@ -313,7 +316,7 @@ fn simple_trait_predicates<'db>( interner, adt_predicates .explicit_predicates() - .iter_identity_copied() + .iter_identity() .chain(extra_predicates) .chain(assoc_type_bounds), ) @@ -440,7 +443,7 @@ fn check_predicates(#[rust_analyzer::rust_fixture] ra_fixture: &str, expectation format_to!( predicates, "{}\n\n", - preds.iter().format_with("\n", |pred, formatter| formatter(&format_args!( + preds.format_with("\n", |pred, formatter| formatter(&format_args!( "{pred:?}" ))), ); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/consteval/tests.rs b/src/tools/rust-analyzer/crates/hir-ty/src/consteval/tests.rs index 31cf86476f9a..aee27dcfdef9 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/consteval/tests.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/consteval/tests.rs @@ -1,4 +1,4 @@ -use base_db::RootQueryDb; +use base_db::all_crates; use hir_def::signatures::ConstSignature; use hir_expand::EditionedFileId; use rustc_apfloat::{ @@ -108,7 +108,7 @@ fn pretty_print_err(e: ConstEvalError, db: &TestDB) -> String { let mut err = String::new(); let span_formatter = |file, range| format!("{file:?} {range:?}"); let display_target = - DisplayTarget::from_crate(db, *db.all_crates().last().expect("no crate graph present")); + DisplayTarget::from_crate(db, *all_crates(db).last().expect("no crate graph present")); match e { ConstEvalError::MirLowerError(e) => { e.pretty_print(&mut err, db, span_formatter, display_target) diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/display.rs b/src/tools/rust-analyzer/crates/hir-ty/src/display.rs index d68058864564..0c4e34db7db0 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/display.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/display.rs @@ -640,7 +640,7 @@ fn write_projection<'db>( // FIXME: We shouldn't use `param.id`, it should be removed. We should know the // `GenericDefId` from the formatted type (store it inside the `HirFormatter`). let bounds = GenericPredicates::query_all(f.db, param.id.parent()) - .iter_identity_copied() + .iter_identity() .filter(|wc| { let ty = match wc.kind().skip_binder() { ClauseKind::Trait(tr) => tr.self_ty(), @@ -1466,7 +1466,7 @@ fn hir_fmt(&self, f @ &mut HirFormatter { db, .. }: &mut HirFormatter<'_, 'db>) } TypeParamProvenance::ArgumentImplTrait => { let bounds = GenericPredicates::query_all(f.db, param.id.parent()) - .iter_identity_copied() + .iter_identity() .filter(|wc| match wc.kind().skip_binder() { ClauseKind::Trait(tr) => tr.self_ty() == *self, ClauseKind::Projection(proj) => proj.self_ty() == *self, diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/dyn_compatibility.rs b/src/tools/rust-analyzer/crates/hir-ty/src/dyn_compatibility.rs index 4c300affd8a2..e70918f8e112 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/dyn_compatibility.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/dyn_compatibility.rs @@ -141,7 +141,7 @@ pub fn generics_require_sized_self(db: &dyn HirDatabase, def: GenericDefId) -> b // FIXME: We should use `explicit_predicates_of` here, which hasn't been implemented to // rust-analyzer yet // https://github.com/rust-lang/rust/blob/ddaf12390d3ffb7d5ba74491a48f3cd528e5d777/compiler/rustc_hir_analysis/src/collect/predicates_of.rs#L490 - elaborate::elaborate(interner, predicates.iter_identity_copied()).any(|pred| { + elaborate::elaborate(interner, predicates.iter_identity()).any(|pred| { match pred.kind().skip_binder() { ClauseKind::Trait(trait_pred) => { if sized == trait_pred.def_id().0 @@ -164,7 +164,7 @@ pub fn generics_require_sized_self(db: &dyn HirDatabase, def: GenericDefId) -> b // So, just return single boolean value for existence of such `Self` reference fn predicates_reference_self(db: &dyn HirDatabase, trait_: TraitId) -> bool { GenericPredicates::query_explicit(db, trait_.into()) - .iter_identity_copied() + .iter_identity() .any(|pred| predicate_references_self(db, trait_, pred, AllowSelfProjection::No)) } @@ -360,8 +360,8 @@ fn virtual_call_violations_for_method( cb(MethodViolationCode::UndispatchableReceiver)?; } - let predicates = GenericPredicates::query_own(db, func.into()); - for pred in predicates.iter_identity_copied() { + let predicates = GenericPredicates::query_own_explicit(db, func.into()); + for pred in predicates.iter_identity() { let pred = pred.kind().skip_binder(); if matches!(pred, ClauseKind::TypeOutlives(_)) { @@ -459,7 +459,7 @@ fn receiver_is_dispatchable<'db>( clauses: Clauses::new_from_iter( interner, generic_predicates - .iter_identity_copied() + .iter_identity() .chain([unsize_predicate.upcast(interner), trait_predicate.upcast(interner)]) .chain(meta_sized_predicate), ), diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/infer.rs b/src/tools/rust-analyzer/crates/hir-ty/src/infer.rs index d14e9d652654..bd897113bf0e 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/infer.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/infer.rs @@ -1706,6 +1706,61 @@ fn resolve_variant( self.generic_def, LifetimeElisionKind::Infer, ); + + if let Some(type_anchor) = path.type_anchor() { + let mut segments = path.segments(); + if segments.is_empty() { + return (self.err_ty(), None); + } + let (mut ty, type_ns) = ctx.lower_ty_ext(type_anchor); + ty = self.table.process_user_written_ty(ty); + + if let Some(TypeNs::SelfType(impl_)) = type_ns + && let Some(trait_ref) = self.db.impl_trait(impl_) + && let trait_ref = trait_ref.instantiate_identity() + && let Some(assoc_type) = trait_ref + .def_id + .0 + .trait_items(self.db) + .associated_type_by_name(segments.first().unwrap().name) + { + // `::AssocType` + let args = self.infcx().fill_rest_fresh_args(assoc_type.into(), trait_ref.args); + let alias = Ty::new_alias( + self.interner(), + AliasTyKind::Projection, + AliasTy::new_from_args(self.interner(), assoc_type.into(), args), + ); + ty = self.table.try_structurally_resolve_type(alias); + segments = segments.skip(1); + } + + let variant = match ty.as_adt() { + Some((AdtId::StructId(id), _)) => id.into(), + Some((AdtId::UnionId(id), _)) => id.into(), + Some((AdtId::EnumId(id), _)) => { + if let Some(segment) = segments.first() + && let enum_data = id.enum_variants(self.db) + && let Some(variant) = enum_data.variant(segment.name) + { + // FIXME: Report error if there are generics on the variant. + segments = segments.skip(1); + variant.into() + } else { + return (self.err_ty(), None); + } + } + None => return (self.err_ty(), None), + }; + + if !segments.is_empty() { + // FIXME: Report an error. + return (self.err_ty(), None); + } else { + return (ty, Some(variant)); + } + } + let mut path_ctx = ctx.at_path(path, node); let interner = DbInterner::conjure(); let (resolution, unresolved) = if value_ns { @@ -1838,6 +1893,46 @@ fn resolve_variant( }); (ty, variant) } + TypeNs::TraitId(_) => { + let Some(remaining_idx) = unresolved else { + return (self.err_ty(), None); + }; + + let remaining_segments = path.segments().skip(remaining_idx); + + if remaining_segments.len() >= 2 { + path_ctx.ignore_last_segment(); + } + + let (mut ty, _) = path_ctx.lower_partly_resolved_path(resolution, true); + ty = self.table.process_user_written_ty(ty); + + if let Some(segment) = remaining_segments.get(1) + && let Some((AdtId::EnumId(id), _)) = ty.as_adt() + { + let enum_data = id.enum_variants(self.db); + if let Some(variant) = enum_data.variant(segment.name) { + return if remaining_segments.len() == 2 { + (ty, Some(variant.into())) + } else { + // We still have unresolved paths, but enum variants never have + // associated types! + // FIXME: Report an error. + (self.err_ty(), None) + }; + } + } + + let variant = ty.as_adt().and_then(|(id, _)| match id { + AdtId::StructId(s) => Some(VariantId::StructId(s)), + AdtId::UnionId(u) => Some(VariantId::UnionId(u)), + AdtId::EnumId(_) => { + // FIXME Error E0071, expected struct, variant or union type, found enum `Foo` + None + } + }); + (ty, variant) + } TypeNs::TypeAliasId(it) => { let Some(mod_path) = path.mod_path() else { never!("resolver should always resolve lang item paths"); @@ -1859,10 +1954,7 @@ fn resolve_variant( // FIXME potentially resolve assoc type (self.err_ty(), None) } - TypeNs::AdtId(AdtId::EnumId(_)) - | TypeNs::BuiltinType(_) - | TypeNs::TraitId(_) - | TypeNs::ModuleId(_) => { + TypeNs::AdtId(AdtId::EnumId(_)) | TypeNs::BuiltinType(_) | TypeNs::ModuleId(_) => { // FIXME diagnostic (self.err_ty(), None) } diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/infer/closure.rs b/src/tools/rust-analyzer/crates/hir-ty/src/infer/closure.rs index ce99016470c1..b868f0234209 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/infer/closure.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/infer/closure.rs @@ -164,13 +164,7 @@ pub(super) fn infer_closure( let coroutine_captures_by_ref_ty = Ty::new_fn_ptr( interner, Binder::bind_with_vars( - interner.mk_fn_sig( - [], - self.types.types.unit, - false, - Safety::Safe, - FnAbi::Rust, - ), + interner.mk_fn_sig_safe_rust_abi([], self.types.types.unit), self.types.coroutine_captures_by_ref_bound_var_kinds, ), ); @@ -484,13 +478,8 @@ fn extract_sig_from_projection( let ret_param_ty = projection.skip_binder().term.expect_type(); debug!(?ret_param_ty); - let sig = projection.rebind(self.interner().mk_fn_sig( - input_tys, - ret_param_ty, - false, - Safety::Safe, - FnAbi::Rust, - )); + let sig = + projection.rebind(self.interner().mk_fn_sig_safe_rust_abi(input_tys, ret_param_ty)); Some(sig) } @@ -572,13 +561,8 @@ fn extract_sig_from_projection_and_future_bound( // that does not misuse a `FnSig` type, but that can be done separately. let return_ty = return_ty.unwrap_or_else(|| self.table.next_ty_var()); - let sig = projection.rebind(self.interner().mk_fn_sig( - input_tys, - return_ty, - false, - Safety::Safe, - FnAbi::Rust, - )); + let sig = + projection.rebind(self.interner().mk_fn_sig_safe_rust_abi(input_tys, return_ty)); Some(sig) } diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/infer/expr.rs b/src/tools/rust-analyzer/crates/hir-ty/src/infer/expr.rs index dc57b1d1c215..ee34a30ebaaf 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/infer/expr.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/infer/expr.rs @@ -2158,7 +2158,7 @@ fn register_obligations_for_call(&mut self, callable_ty: Ty<'db>) { ); let param_env = self.table.param_env; self.table.register_predicates(clauses_as_obligations( - generic_predicates.iter_instantiated_copied(self.interner(), parameters.as_slice()), + generic_predicates.iter_instantiated(self.interner(), parameters.as_slice()), ObligationCause::new(), param_env, )); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/infer/path.rs b/src/tools/rust-analyzer/crates/hir-ty/src/infer/path.rs index 71d68ccd47a6..3cadc8e93359 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/infer/path.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/infer/path.rs @@ -228,7 +228,7 @@ fn add_required_obligations_for_value_path( let predicates = GenericPredicates::query_all(self.db, def); let param_env = self.table.param_env; self.table.register_predicates(clauses_as_obligations( - predicates.iter_instantiated_copied(interner, subst.as_slice()), + predicates.iter_instantiated(interner, subst.as_slice()), ObligationCause::new(), param_env, )); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/lower.rs b/src/tools/rust-analyzer/crates/hir-ty/src/lower.rs index 7259099107ca..71a7db6559a8 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/lower.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/lower.rs @@ -2016,17 +2016,21 @@ pub fn type_alias_bounds_with_diagnostics_query<'db>( #[derive(Debug, Clone, PartialEq, Eq, Hash)] pub struct GenericPredicates { - // The order is the following: first, if `parent_is_trait == true`, comes the implicit trait - // predicate for the parent. Then come the bounds of the associated types of the parents, - // then the explicit, self-only predicates for the parent, then the explicit, self-only trait - // predicate for the child, then the bounds of the associated types of the child, - // then the implicit trait predicate for the child, if `is_trait` is `true`. + // The order is the following: + // + // 1. If `has_trait_implied_predicate == true`, the implicit trait predicate. + // 2. The bounds of the associated types of the parents, coming from `Trait`. + // Note: associated type bounds from `Self::Assoc: Trait` on traits *won't* be included + // here, they are in 3. + // 3. The explicit, self-only predicates for the parent. + // 4. The explicit, self-only trait predicate for the child, + // 5. The bounds of the associated types of the child. predicates: StoredEarlyBinder, + // Keep this ordered according to the above. + has_trait_implied_predicate: bool, parent_explicit_self_predicates_start: u32, own_predicates_start: u32, own_assoc_ty_bounds_start: u32, - is_trait: bool, - parent_is_trait: bool, } #[salsa::tracked] @@ -2065,11 +2069,10 @@ pub(crate) fn from_explicit_own_predicates( let len = predicates.get().skip_binder().len() as u32; Self { predicates, + has_trait_implied_predicate: false, parent_explicit_self_predicates_start: 0, own_predicates_start: 0, own_assoc_ty_bounds_start: len, - is_trait: false, - parent_is_trait: false, } } @@ -2082,58 +2085,68 @@ pub fn query(db: &dyn HirDatabase, def: GenericDefId) -> &GenericPredicates { pub fn query_all<'db>( db: &'db dyn HirDatabase, def: GenericDefId, - ) -> EarlyBinder<'db, &'db [Clause<'db>]> { + ) -> EarlyBinder<'db, impl Iterator>> { Self::query(db, def).all_predicates() } #[inline] - pub fn query_own<'db>( + pub fn query_own_explicit<'db>( db: &'db dyn HirDatabase, def: GenericDefId, - ) -> EarlyBinder<'db, &'db [Clause<'db>]> { - Self::query(db, def).own_predicates() + ) -> EarlyBinder<'db, impl Iterator>> { + Self::query(db, def).own_explicit_predicates() } #[inline] pub fn query_explicit<'db>( db: &'db dyn HirDatabase, def: GenericDefId, - ) -> EarlyBinder<'db, &'db [Clause<'db>]> { + ) -> EarlyBinder<'db, impl Iterator>> { Self::query(db, def).explicit_predicates() } #[inline] - pub fn query_explicit_implied<'db>( - db: &'db dyn HirDatabase, - def: GenericDefId, - ) -> EarlyBinder<'db, &'db [Clause<'db>]> { - Self::query(db, def).explicit_implied_predicates() + pub fn all_predicates(&self) -> EarlyBinder<'_, impl Iterator>> { + self.predicates.get().map_bound(|it| it.as_slice().iter().copied()) } #[inline] - pub fn all_predicates(&self) -> EarlyBinder<'_, &[Clause<'_>]> { - self.predicates.get().map_bound(|it| it.as_slice()) + pub fn own_explicit_predicates(&self) -> EarlyBinder<'_, impl Iterator>> { + self.predicates + .get() + .map_bound(|it| it.as_slice()[self.own_predicates_start as usize..].iter().copied()) } #[inline] - pub fn own_predicates(&self) -> EarlyBinder<'_, &[Clause<'_>]> { - self.predicates.get().map_bound(|it| &it.as_slice()[self.own_predicates_start as usize..]) - } - - /// Returns the predicates, minus the implicit `Self: Trait` predicate and bounds of the - /// associated types for a trait. - #[inline] - pub fn explicit_predicates(&self) -> EarlyBinder<'_, &[Clause<'_>]> { + pub fn explicit_predicates(&self) -> EarlyBinder<'_, impl Iterator>> { self.predicates.get().map_bound(|it| { - &it.as_slice()[self.parent_explicit_self_predicates_start as usize - ..self.own_assoc_ty_bounds_start as usize] + it.as_slice()[usize::from(self.has_trait_implied_predicate)..].iter().copied() }) } #[inline] - pub fn explicit_implied_predicates(&self) -> EarlyBinder<'_, &[Clause<'_>]> { + pub fn explicit_non_assoc_types_predicates( + &self, + ) -> EarlyBinder<'_, impl Iterator>> { self.predicates.get().map_bound(|it| { - &it.as_slice()[usize::from(self.parent_is_trait)..it.len() - usize::from(self.is_trait)] + it.as_slice()[self.parent_explicit_self_predicates_start as usize + ..self.own_assoc_ty_bounds_start as usize] + .iter() + .copied() + }) + } + + #[inline] + pub fn explicit_assoc_types_predicates( + &self, + ) -> EarlyBinder<'_, impl Iterator>> { + self.predicates.get().map_bound(|predicates| { + let predicates = predicates.as_slice(); + predicates[usize::from(self.has_trait_implied_predicate) + ..self.parent_explicit_self_predicates_start as usize] + .iter() + .copied() + .chain(predicates[self.own_assoc_ty_bounds_start as usize..].iter().copied()) }) } } @@ -2142,10 +2155,8 @@ pub(crate) fn param_env_from_predicates<'db>( interner: DbInterner<'db>, predicates: &'db GenericPredicates, ) -> ParamEnv<'db> { - let clauses = rustc_type_ir::elaborate::elaborate( - interner, - predicates.all_predicates().iter_identity_copied(), - ); + let clauses = + rustc_type_ir::elaborate::elaborate(interner, predicates.all_predicates().iter_identity()); let clauses = Clauses::new_from_iter(interner, clauses); // FIXME: We should normalize projections here, like rustc does. @@ -2290,42 +2301,28 @@ fn generic_predicates(db: &dyn HirDatabase, def: GenericDefId) -> (GenericPredic let diagnostics = create_diagnostics(ctx.diagnostics); - // The order is: - // - // 1. parent implicit trait pred - // 2. parent assoc bounds - // 3. parent self only preds - // 4. own self only preds - // 5. own assoc ty bounds - // 6. own implicit trait pred - // - // The purpose of this is to index the slice of the followings, without making extra `Vec`s or - // iterators: - // - explicit self only predicates, of own or own + self - // - explicit predicates, of own or own + self let predicates = parent_implicit_trait_predicate .iter() + .chain(own_implicit_trait_predicate.iter()) .chain(parent_assoc_ty_bounds.iter()) .chain(parent_predicates.iter()) .chain(own_predicates.iter()) .chain(own_assoc_ty_bounds.iter()) - .chain(own_implicit_trait_predicate.iter()) .copied() .collect::>(); - let parent_is_trait = parent_implicit_trait_predicate.is_some(); - let is_trait = own_implicit_trait_predicate.is_some(); + let has_trait_implied_predicate = + parent_implicit_trait_predicate.is_some() || own_implicit_trait_predicate.is_some(); let parent_explicit_self_predicates_start = - parent_is_trait as u32 + parent_assoc_ty_bounds.len() as u32; + has_trait_implied_predicate as u32 + parent_assoc_ty_bounds.len() as u32; let own_predicates_start = parent_explicit_self_predicates_start + parent_predicates.len() as u32; let own_assoc_ty_bounds_start = own_predicates_start + own_predicates.len() as u32; let predicates = GenericPredicates { + has_trait_implied_predicate, parent_explicit_self_predicates_start, own_predicates_start, own_assoc_ty_bounds_start, - is_trait, - parent_is_trait, predicates: StoredEarlyBinder::bind(Clauses::new_from_slice(&predicates).store()), }; return (predicates, diagnostics); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution.rs b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution.rs index 05b9ea5d748f..b18e48c1fed3 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution.rs @@ -324,7 +324,7 @@ pub(super) fn lookup_method_for_operator( // any late-bound regions appearing in its bounds. let bounds = GenericPredicates::query_all(self.db, method_item.into()); let bounds = clauses_as_obligations( - bounds.iter_instantiated_copied(interner, args.as_slice()), + bounds.iter_instantiated(interner, args.as_slice()), ObligationCause::new(), self.param_env, ); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/confirm.rs b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/confirm.rs index ec589085a88d..94c70c29f74b 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/confirm.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/confirm.rs @@ -136,7 +136,7 @@ fn confirm( ); let illegal_sized_bound = self.predicates_require_illegal_sized_bound( GenericPredicates::query_all(self.db(), self.candidate.into()) - .iter_instantiated_copied(self.interner(), filler_args.as_slice()), + .iter_instantiated(self.interner(), filler_args.as_slice()), ); // Unify the (adjusted) self type with what the method expects. @@ -509,7 +509,7 @@ fn instantiate_method_sig<'c>( let def_id = self.candidate; let method_predicates = clauses_as_obligations( GenericPredicates::query_all(self.db(), def_id.into()) - .iter_instantiated_copied(self.interner(), all_args), + .iter_instantiated(self.interner(), all_args), ObligationCause::new(), self.ctx.table.param_env, ); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/probe.rs b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/probe.rs index 8c76bfbc076b..3604076ccdc7 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/probe.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/method_resolution/probe.rs @@ -1595,7 +1595,7 @@ fn consider_probe( // Check whether the impl imposes obligations we have to worry about. let impl_bounds = GenericPredicates::query_all(self.db(), impl_def_id.into()); let impl_bounds = clauses_as_obligations( - impl_bounds.iter_instantiated_copied(self.interner(), impl_args.as_slice()), + impl_bounds.iter_instantiated(self.interner(), impl_args.as_slice()), ObligationCause::new(), self.param_env(), ); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/mir/eval/shim.rs b/src/tools/rust-analyzer/crates/hir-ty/src/mir/eval/shim.rs index ff6c99ca53b3..2aed76ec9091 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/mir/eval/shim.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/mir/eval/shim.rs @@ -518,7 +518,7 @@ fn exec_extern_c( "sched_getaffinity" => { let [_pid, _set_size, set] = args else { return Err(MirEvalError::InternalError( - "libc::write args are not provided".into(), + "sched_getaffinity args are not provided".into(), )); }; let set = Address::from_bytes(set.get(self)?)?; @@ -530,9 +530,7 @@ fn exec_extern_c( } "getenv" => { let [name] = args else { - return Err(MirEvalError::InternalError( - "libc::write args are not provided".into(), - )); + return Err(MirEvalError::InternalError("getenv args are not provided".into())); }; let mut name_buf = vec![]; let name = { diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/interner.rs b/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/interner.rs index 5b81c7675dbb..5d7ad84e1fe2 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/interner.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/interner.rs @@ -1439,81 +1439,55 @@ fn item_non_self_bounds( } } - #[tracing::instrument(level = "debug", skip(self), ret)] fn predicates_of( self, def_id: Self::DefId, ) -> EarlyBinder> { - predicates_of(self.db, def_id).all_predicates().map_bound(|it| it.iter().copied()) + predicates_of(self.db, def_id).all_predicates() } - #[tracing::instrument(level = "debug", skip(self), ret)] fn own_predicates_of( self, def_id: Self::DefId, ) -> EarlyBinder> { - predicates_of(self.db, def_id).own_predicates().map_bound(|it| it.iter().copied()) + predicates_of(self.db, def_id).own_explicit_predicates() } - #[tracing::instrument(skip(self), ret)] fn explicit_super_predicates_of( self, def_id: Self::TraitId, ) -> EarlyBinder> { - let is_self = |ty: Ty<'db>| match ty.kind() { - rustc_type_ir::TyKind::Param(param) => param.index == 0, - _ => false, - }; - - GenericPredicates::query_explicit(self.db, def_id.0.into()).map_bound(move |predicates| { - predicates - .iter() - .copied() - .filter(move |p| match p.kind().skip_binder() { - // rustc has the following assertion: - // https://github.com/rust-lang/rust/blob/52618eb338609df44978b0ca4451ab7941fd1c7a/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs#L525-L608 - ClauseKind::Trait(it) => is_self(it.self_ty()), - ClauseKind::TypeOutlives(it) => is_self(it.0), - ClauseKind::Projection(it) => is_self(it.self_ty()), - ClauseKind::HostEffect(it) => is_self(it.self_ty()), - _ => false, - }) - .map(|p| (p, Span::dummy())) - }) + GenericPredicates::query(self.db, def_id.0.into()) + .explicit_non_assoc_types_predicates() + .map_bound(move |predicates| { + predicates.filter(|p| is_clause_at_ty(p, is_ty_self)).map(|p| (p, Span::dummy())) + }) } - #[tracing::instrument(skip(self), ret)] fn explicit_implied_predicates_of( self, def_id: Self::DefId, ) -> EarlyBinder> { - fn is_self_or_assoc(ty: Ty<'_>) -> bool { - match ty.kind() { - rustc_type_ir::TyKind::Param(param) => param.index == 0, - rustc_type_ir::TyKind::Alias(rustc_type_ir::AliasTyKind::Projection, alias) => { - is_self_or_assoc(alias.self_ty()) - } - _ => false, + fn is_ty_assoc_of_self(ty: Ty<'_>) -> bool { + // FIXME: Is this correct wrt. combined kind of assoc type bounds, i.e. `where Self::Assoc: Trait` + // wrt. `Assoc2`, which we should exclude? + if let TyKind::Alias(AliasTyKind::Projection, alias) = ty.kind() { + is_ty_assoc_of_self(alias.self_ty()) + } else { + is_ty_self(ty) } } - predicates_of(self.db, def_id).explicit_implied_predicates().map_bound(|predicates| { - predicates - .iter() - .copied() - .filter(|p| match p.kind().skip_binder() { - ClauseKind::Trait(it) => is_self_or_assoc(it.self_ty()), - ClauseKind::TypeOutlives(it) => is_self_or_assoc(it.0), - ClauseKind::Projection(it) => is_self_or_assoc(it.self_ty()), - ClauseKind::HostEffect(it) => is_self_or_assoc(it.self_ty()), - // FIXME: Not sure is this correct to allow other clauses but we might replace - // `generic_predicates_ns` query here with something closer to rustc's - // `implied_bounds_with_filter`, which is more granular lowering than this - // "lower at once and then filter" implementation. - _ => true, - }) - .map(|p| (p, Span::dummy())) - }) + let predicates = predicates_of(self.db, def_id); + let non_assoc_types = predicates + .explicit_non_assoc_types_predicates() + .skip_binder() + .filter(|p| is_clause_at_ty(p, is_ty_self)); + let assoc_types = predicates + .explicit_assoc_types_predicates() + .skip_binder() + .filter(|p| is_clause_at_ty(p, is_ty_assoc_of_self)); + EarlyBinder::bind(non_assoc_types.chain(assoc_types).map(|it| (it, Span::dummy()))) } fn impl_super_outlives( @@ -2294,6 +2268,24 @@ fn const_of_item(self, def_id: Self::DefId) -> rustc_type_ir::EarlyBinder) -> bool { + match ty.kind() { + TyKind::Param(param) => param.index == 0, + _ => false, + } +} +fn is_clause_at_ty(p: &Clause<'_>, filter: impl FnOnce(Ty<'_>) -> bool) -> bool { + match p.kind().skip_binder() { + // rustc has the following assertion: + // https://github.com/rust-lang/rust/blob/52618eb338609df44978b0ca4451ab7941fd1c7a/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs#L525-L608 + ClauseKind::Trait(it) => filter(it.self_ty()), + ClauseKind::TypeOutlives(it) => filter(it.0), + ClauseKind::Projection(it) => filter(it.self_ty()), + ClauseKind::HostEffect(it) => filter(it.self_ty()), + _ => false, + } +} + impl<'db> DbInterner<'db> { pub fn shift_bound_var_indices(self, bound_vars: usize, value: T) -> T where @@ -2366,6 +2358,22 @@ pub fn mk_fn_sig( abi, } } + + /// `mk_fn_sig`, but with a safe Rust ABI, and no C-variadic argument. + pub fn mk_fn_sig_safe_rust_abi(self, inputs: I, output: Ty<'db>) -> FnSig<'db> + where + I: IntoIterator>, + { + FnSig { + inputs_and_output: Tys::new_from_iter( + self, + inputs.into_iter().chain(std::iter::once(output)), + ), + c_variadic: false, + safety: Safety::Safe, + abi: FnAbi::Rust, + } + } } fn predicates_of(db: &dyn HirDatabase, def_id: SolverDefId) -> &GenericPredicates { diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/ty.rs b/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/ty.rs index 192cdb70aee5..8e892b65ea38 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/ty.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/next_solver/ty.rs @@ -696,7 +696,7 @@ pub fn impl_trait_bounds(self, db: &'db dyn HirDatabase) -> Option match p.provenance { TypeParamProvenance::ArgumentImplTrait => { let predicates = GenericPredicates::query_all(db, param.id.parent()) - .iter_identity_copied() + .iter_identity() .filter(|wc| match wc.kind().skip_binder() { ClauseKind::Trait(tr) => tr.self_ty() == self, ClauseKind::Projection(pred) => pred.self_ty() == self, diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/specialization.rs b/src/tools/rust-analyzer/crates/hir-ty/src/specialization.rs index 90cbcfea6abe..8bc6c51fae6f 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/specialization.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/specialization.rs @@ -109,7 +109,7 @@ fn specializes_query( // only be referenced via projection predicates. ocx.register_obligations(clauses_as_obligations( GenericPredicates::query_all(db, parent_impl_def_id.into()) - .iter_instantiated_copied(interner, parent_args.as_slice()), + .iter_instantiated(interner, parent_args.as_slice()), cause.clone(), param_env, )); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/test_db.rs b/src/tools/rust-analyzer/crates/hir-ty/src/test_db.rs index 243456c85fc4..e19e26ebc406 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/test_db.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/test_db.rs @@ -3,8 +3,8 @@ use std::{fmt, panic, sync::Mutex}; use base_db::{ - CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Nonce, RootQueryDb, - SourceDatabase, SourceRoot, SourceRootId, SourceRootInput, + CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Nonce, SourceDatabase, SourceRoot, + SourceRootId, SourceRootInput, all_crates, relevant_crates, set_all_crates_with_durability, }; use hir_def::{ModuleId, db::DefDatabase, nameres::crate_def_map}; @@ -45,7 +45,7 @@ fn default() -> Self { }; this.set_expand_proc_attr_macros_with_durability(true, Durability::HIGH); // This needs to be here otherwise `CrateGraphBuilder` panics. - this.set_all_crates(Arc::new(Box::new([]))); + set_all_crates_with_durability(&mut this, std::iter::empty(), Durability::HIGH); _ = base_db::LibraryRoots::builder(Default::default()) .durability(Durability::MEDIUM) .new(&this); @@ -142,7 +142,7 @@ impl panic::RefUnwindSafe for TestDB {} impl TestDB { pub(crate) fn module_for_file_opt(&self, file_id: impl Into) -> Option { let file_id = file_id.into(); - for &krate in self.relevant_crates(file_id).iter() { + for &krate in relevant_crates(self, file_id).iter() { let crate_def_map = crate_def_map(self, krate); for (module_id, data) in crate_def_map.modules() { if data.origin.file_id().map(|file_id| file_id.file_id(self)) == Some(file_id) { @@ -161,7 +161,7 @@ pub(crate) fn extract_annotations( &self, ) -> FxHashMap> { let mut files = Vec::new(); - for &krate in self.all_crates().iter() { + for &krate in all_crates(self).iter() { let crate_def_map = crate_def_map(self, krate); for (module_id, _) in crate_def_map.modules() { let file_id = crate_def_map[module_id].origin.file_id(); diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/tests/incremental.rs b/src/tools/rust-analyzer/crates/hir-ty/src/tests/incremental.rs index e806999cb44e..7cda259664c1 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/tests/incremental.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/tests/incremental.rs @@ -31,11 +31,11 @@ fn foo() -> i32 { &[("InferenceResult::for_body_", 1)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "InferenceResult::for_body_", "FunctionSignature::of_", @@ -76,7 +76,7 @@ fn foo() -> i32 { &[("InferenceResult::for_body_", 0)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -119,11 +119,11 @@ fn baz() -> i32 { &[("InferenceResult::for_body_", 3)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "InferenceResult::for_body_", "FunctionSignature::of_", @@ -189,7 +189,7 @@ fn baz() -> i32 { &[("InferenceResult::for_body_", 1)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -239,11 +239,11 @@ fn bar() -> f32 { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "TraitImpls::for_crate_", "lang_items", @@ -278,7 +278,7 @@ pub struct NewStruct { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -314,11 +314,11 @@ fn bar() -> f32 { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "TraitImpls::for_crate_", "lang_items", @@ -354,7 +354,7 @@ pub enum SomeEnum { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -390,11 +390,11 @@ fn bar() -> f32 { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "TraitImpls::for_crate_", "lang_items", @@ -427,7 +427,7 @@ fn bar() -> f32 { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -467,11 +467,11 @@ pub struct SomeStruct { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "TraitImpls::for_crate_", "lang_items", @@ -512,7 +512,7 @@ pub fn new(value: i32) -> Self { &[("TraitImpls::for_crate_", 1)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", @@ -568,11 +568,11 @@ fn main() { &[("trait_solve_shim", 0)], expect_test::expect![[r#" [ - "source_root_crates_shim", + "source_root_crates", "crate_local_def_map", "file_item_tree_query", "ast_id_map", - "parse_shim", + "parse", "real_span_map_shim", "TraitItems::query_with_diagnostics_", "Body::of_", @@ -664,7 +664,7 @@ fn main() { &[("trait_solve_shim", 0)], expect_test::expect![[r#" [ - "parse_shim", + "parse", "ast_id_map", "file_item_tree_query", "real_span_map_shim", diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/tests/regression.rs b/src/tools/rust-analyzer/crates/hir-ty/src/tests/regression.rs index e4fc7e56c6ae..d3dfc44c227f 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/tests/regression.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/tests/regression.rs @@ -2841,3 +2841,18 @@ fn wrapped_abs>(v: T) -> T { "#, ); } + +#[test] +fn regression_21899() { + check_no_mismatches( + r#" +trait B where + Self::T: B, +{ + type T; +} + +fn foo(v: T::T) {} + "#, + ); +} diff --git a/src/tools/rust-analyzer/crates/hir-ty/src/tests/traits.rs b/src/tools/rust-analyzer/crates/hir-ty/src/tests/traits.rs index 22359d8f1f1d..1d27d52a3660 100644 --- a/src/tools/rust-analyzer/crates/hir-ty/src/tests/traits.rs +++ b/src/tools/rust-analyzer/crates/hir-ty/src/tests/traits.rs @@ -4449,14 +4449,14 @@ fn f() { let a = Self::Assoc { x }; // ^ S let a = ::Assoc { x }; // unstable - // ^ {unknown} + // ^ S // should be `Copy` but we don't track ownership anyway. let value = S { x }; if let Self::Assoc { x } = value {} // ^ u32 if let ::Assoc { x } = value {} // unstable - // ^ {unknown} + // ^ u32 } } "#, @@ -4508,22 +4508,22 @@ fn f() { let a = Self::Assoc::Struct { x }; // ^ E let a = ::Assoc::Struct { x }; // unstable - // ^ {unknown} + // ^ E let a = ::Struct { x }; // unstable - // ^ {unknown} + // ^ E let a = <::Assoc>::Struct { x }; // unstable - // ^ {unknown} + // ^ E // should be `Copy` but we don't track ownership anyway. let value = E::Struct { x: 42 }; if let Self::Assoc::Struct { x } = value {} // ^ u32 if let ::Assoc::Struct { x } = value {} // unstable - // ^ {unknown} + // ^ u32 if let ::Struct { x } = value {} // unstable - // ^ {unknown} + // ^ u32 if let <::Assoc>::Struct { x } = value {} // unstable - // ^ {unknown} + // ^ u32 } } "#, @@ -5148,3 +5148,98 @@ fn foo(v: Struct) { "#, ); } + +#[test] +fn more_qualified_paths() { + check_infer( + r#" +struct T; +struct S { + a: u32, +} + +trait Trait { + type Assoc; + + fn foo(); +} + +impl Trait for T { + type Assoc = S; + + fn foo() { + let ::Assoc { a } = ::Assoc { a: 0 }; + } +} + +enum E { + ES { a: u32 }, + ET(u32), +} + +impl Trait for E { + type Assoc = Self; + + fn foo() { + let ::Assoc::ES { a } = ::Assoc::ES { a: 0 }; + } +} + +fn foo() { + let ::Assoc { a } = ::Assoc { a: 0 }; + + let ::ES { a } = (::ES { a: 0 }) else { loop {} }; + let ::ET(a) = ::ET(0) else { loop {} }; + let ::Assoc::ES { a } = (::Assoc::ES { a: 0 }) else { loop {} }; + let ::Assoc::ET(a) = ::Assoc::ET(0) else { loop {} }; +} + "#, + expect![[r#" + 137..202 '{ ... }': () + 151..170 '... { a }': S + 167..168 'a': u32 + 173..195 '...a: 0 }': S + 192..193 '0': u32 + 306..379 '{ ... }': () + 320..343 '... { a }': E + 340..341 'a': u32 + 346..372 '...a: 0 }': E + 369..370 '0': u32 + 392..748 '{ ...} }; }': () + 402..427 '::ES { a }': E + 479..480 'a': u32 + 486..502 '::E...a: 0 }': E + 499..500 '0': u32 + 509..520 '{ loop {} }': ! + 511..518 'loop {}': ! + 516..518 '{}': () + 530..540 '::ET(a)': E + 538..539 'a': u32 + 543..550 '::ET': fn ET(u32) -> E + 543..553 '::ET(0)': E + 551..552 '0': u32 + 559..570 '{ loop {} }': ! + 561..568 'loop {}': ! + 566..568 '{}': () + 580..609 ' E + 702..728 '>, pub field_list_parent_path: Option>, - pub missed_fields: Vec, + pub missed_fields: Vec<(Name, Field)>, } #[derive(Debug)] @@ -476,7 +476,12 @@ pub(crate) fn body_validation_diagnostic( let variant_data = variant.fields(db); let missed_fields = missed_fields .into_iter() - .map(|idx| variant_data.fields()[idx].name.clone()) + .map(|idx| { + ( + variant_data.fields()[idx].name.clone(), + Field { parent: variant.into(), id: idx }, + ) + }) .collect(); let record = match record { diff --git a/src/tools/rust-analyzer/crates/hir/src/display.rs b/src/tools/rust-analyzer/crates/hir/src/display.rs index 4bfdd239f937..53f24713cdcc 100644 --- a/src/tools/rust-analyzer/crates/hir/src/display.rs +++ b/src/tools/rust-analyzer/crates/hir/src/display.rs @@ -76,7 +76,7 @@ fn write_builtin_derive_impl_method<'db>( let predicates = hir_ty::builtin_derive::predicates(db, impl_).explicit_predicates().skip_binder(); - write_params_bounds(f, predicates)?; + write_params_bounds(f, &Vec::from_iter(predicates))?; } Ok(()) @@ -578,7 +578,7 @@ fn hir_fmt(&self, f: &mut HirFormatter<'_, 'db>) -> Result { let ty = self.ty(f.db).ty; let predicates = GenericPredicates::query_all(f.db, self.id.parent()); let predicates = predicates - .iter_identity_copied() + .iter_identity() .filter(|wc| match wc.kind().skip_binder() { ClauseKind::Trait(tr) => tr.self_ty() == ty, ClauseKind::Projection(proj) => proj.self_ty() == ty, diff --git a/src/tools/rust-analyzer/crates/hir/src/lib.rs b/src/tools/rust-analyzer/crates/hir/src/lib.rs index bc5e16483054..282990203598 100644 --- a/src/tools/rust-analyzer/crates/hir/src/lib.rs +++ b/src/tools/rust-analyzer/crates/hir/src/lib.rs @@ -45,7 +45,7 @@ }; use arrayvec::ArrayVec; -use base_db::{CrateDisplayName, CrateOrigin, LangCrateOrigin}; +use base_db::{CrateDisplayName, CrateOrigin, LangCrateOrigin, all_crates}; use either::Either; use hir_def::{ AdtId, AssocItemId, AssocItemLoc, BuiltinDeriveImplId, CallableDefId, ConstId, ConstParamId, @@ -243,7 +243,7 @@ pub fn dependencies(self, db: &dyn HirDatabase) -> Vec { } pub fn reverse_dependencies(self, db: &dyn HirDatabase) -> Vec { - let all_crates = db.all_crates(); + let all_crates = all_crates(db); all_crates .iter() .copied() @@ -310,7 +310,7 @@ pub fn query_external_importables( } pub fn all(db: &dyn HirDatabase) -> Vec { - db.all_crates().iter().map(|&id| Crate { id }).collect() + all_crates(db).iter().map(|&id| Crate { id }).collect() } /// Try to get the root URL of the documentation of a crate. @@ -334,7 +334,7 @@ pub fn to_display_target(self, db: &dyn HirDatabase) -> DisplayTarget { } fn core(db: &dyn HirDatabase) -> Option { - db.all_crates() + all_crates(db) .iter() .copied() .find(|&krate| { @@ -547,7 +547,7 @@ impl HasCrate for ModuleDef { fn krate(&self, db: &dyn HirDatabase) -> Crate { match self.module(db) { Some(module) => module.krate(db), - None => Crate::core(db).unwrap_or_else(|| db.all_crates()[0].into()), + None => Crate::core(db).unwrap_or_else(|| all_crates(db)[0].into()), } } } @@ -1239,11 +1239,15 @@ fn emit_def_diagnostic_<'db>( ); } DefDiagnosticKind::InvalidDeriveTarget { ast, id } => { - let derive = id.find_attr_range(db, krate, *ast).3.path_range(); + let (_, attr) = id.find_attr_range(db, krate, *ast); + let derive = attr + .path() + .map(|path| path.syntax().text_range()) + .unwrap_or_else(|| attr.syntax().text_range()); acc.push(InvalidDeriveTarget { range: ast.with_value(derive) }.into()); } DefDiagnosticKind::MalformedDerive { ast, id } => { - let derive = id.find_attr_range(db, krate, *ast).2; + let derive = id.find_attr_range(db, krate, *ast).1.syntax().text_range(); acc.push(MalformedDerive { range: ast.with_value(derive) }.into()); } DefDiagnosticKind::MacroDefError { ast, message } => { @@ -1283,7 +1287,8 @@ fn precise_macro_call_location( ast_id.with_value(range) } MacroCallKind::Attr { ast_id, censored_attr_ids: attr_ids, .. } => { - let attr_range = attr_ids.invoc_attr().find_attr_range(db, krate, *ast_id).2; + let attr_range = + attr_ids.invoc_attr().find_attr_range(db, krate, *ast_id).1.syntax().text_range(); ast_id.with_value(attr_range) } } @@ -3394,7 +3399,7 @@ pub fn i32() -> BuiltinType { } pub fn ty<'db>(self, db: &'db dyn HirDatabase) -> Type<'db> { - let core = Crate::core(db).map(|core| core.id).unwrap_or_else(|| db.all_crates()[0]); + let core = Crate::core(db).map(|core| core.id).unwrap_or_else(|| all_crates(db)[0]); let interner = DbInterner::new_no_crate(db); Type::new_for_crate(core, Ty::from_builtin_type(interner, self.inner)) } @@ -4680,7 +4685,7 @@ pub fn ty(self, db: &dyn HirDatabase) -> Type<'_> { pub fn trait_bounds(self, db: &dyn HirDatabase) -> Vec { let self_ty = self.ty(db).ty; GenericPredicates::query_explicit(db, self.id.parent()) - .iter_identity_copied() + .iter_identity() .filter_map(|pred| match &pred.kind().skip_binder() { ClauseKind::Trait(trait_ref) if trait_ref.self_ty() == self_ty => { Some(Trait::from(trait_ref.def_id().0)) @@ -4898,12 +4903,12 @@ pub fn all_for_type<'db>(db: &'db dyn HirDatabase, Type { ty, env }: Type<'db>) std::iter::successors(module.block(db), |block| block.loc(db).module.block(db)) .filter_map(|block| TraitImpls::for_block(db, block).as_deref()) .for_each(|impls| impls.for_self_ty(&simplified_ty, &mut extend_with_impls)); - for &krate in &**db.all_crates() { + for &krate in &*all_crates(db) { TraitImpls::for_crate(db, krate) .for_self_ty(&simplified_ty, &mut extend_with_impls); } } else { - for &krate in &**db.all_crates() { + for &krate in &*all_crates(db) { TraitImpls::for_crate(db, krate) .for_self_ty(&simplified_ty, &mut extend_with_impls); } @@ -7175,7 +7180,7 @@ pub fn resolve_absolute_path<'a, I: Iterator + Clone + 'a>( .next() .into_iter() .flat_map(move |crate_name| { - db.all_crates() + all_crates(db) .iter() .filter(|&krate| { krate diff --git a/src/tools/rust-analyzer/crates/hir/src/semantics.rs b/src/tools/rust-analyzer/crates/hir/src/semantics.rs index 4e9e3c44be11..999616248591 100644 --- a/src/tools/rust-analyzer/crates/hir/src/semantics.rs +++ b/src/tools/rust-analyzer/crates/hir/src/semantics.rs @@ -10,7 +10,7 @@ ops::{self, ControlFlow, Not}, }; -use base_db::FxIndexSet; +use base_db::{FxIndexSet, all_crates, toolchain_channel}; use either::Either; use hir_def::{ BuiltinDeriveImplId, DefWithBodyId, ExpressionStoreOwnerId, HasModule, MacroId, StructId, @@ -24,6 +24,7 @@ }; use hir_expand::{ EditionedFileId, ExpandResult, FileRange, HirFileId, InMacroFile, MacroCallId, + attrs::AstPathExt, builtin::{BuiltinFnLikeExpander, EagerExpander}, db::ExpandDatabase, files::{FileRangeWrapper, HirFileRange, InRealFile}, @@ -298,14 +299,15 @@ pub fn lint_attrs( hir_expand::attrs::expand_cfg_attr::( extra_crate_attrs.chain(ast::attrs_including_inner(&item)), cfg_options, - |attr, _, _, _| { - let hir_expand::attrs::Meta::TokenTree { path, tt } = attr else { + |attr, _| { + let ast::Meta::TokenTreeMeta(attr) = attr else { return ControlFlow::Continue(()); }; - if path.segments.len() != 1 { + let (Some(segment), Some(tt)) = (attr.path().as_one_segment(), attr.token_tree()) + else { return ControlFlow::Continue(()); - } - let lint_attr = match path.segments[0].text() { + }; + let lint_attr = match &*segment { "allow" => LintAttr::Allow, "expect" => LintAttr::Expect, "warn" => LintAttr::Warn, @@ -392,7 +394,7 @@ pub fn hir_file_to_module_defs( } pub fn is_nightly(&self, krate: Crate) -> bool { - let toolchain = self.db.toolchain_channel(krate.into()); + let toolchain = toolchain_channel(self.db.as_dyn_database(), krate.into()); // `toolchain == None` means we're in some detached files. Since we have no information on // the toolchain being used, let's just allow unstable items to be listed. matches!(toolchain, Some(base_db::ReleaseChannel::Nightly) | None) @@ -458,7 +460,7 @@ fn new(db: &'db dyn HirDatabase) -> Self { pub fn parse(&self, file_id: EditionedFileId) -> ast::SourceFile { let hir_file_id = file_id.into(); - let tree = self.db.parse(file_id).tree(); + let tree = file_id.parse(self.db).tree(); self.cache(tree.syntax().clone(), hir_file_id); tree } @@ -467,7 +469,7 @@ pub fn parse(&self, file_id: EditionedFileId) -> ast::SourceFile { pub fn first_crate(&self, file: FileId) -> Option { match self.file_to_module_defs(file).next() { Some(module) => Some(module.krate(self.db)), - None => self.db.all_crates().last().copied().map(Into::into), + None => all_crates(self.db).last().copied().map(Into::into), } } @@ -484,7 +486,7 @@ pub fn attach_first_edition(&self, file: FileId) -> EditionedFileId { pub fn parse_guess_edition(&self, file_id: FileId) -> ast::SourceFile { let file_id = self.attach_first_edition(file_id); - let tree = self.db.parse(file_id).tree(); + let tree = file_id.parse(self.db).tree(); self.cache(tree.syntax().clone(), file_id.into()); tree } @@ -554,17 +556,6 @@ pub fn expand_macro_call(&self, macro_call: &ast::MacroCall) -> Option Option { - let file_id = self.find_file(attr.syntax()).file_id; - let krate = match file_id { - HirFileId::FileId(file_id) => { - self.file_to_module_defs(file_id.file_id(self.db)).next()?.krate(self.db).id - } - HirFileId::MacroFile(macro_file) => self.db.lookup_intern_macro_call(macro_file).krate, - }; - hir_expand::check_cfg_attr_value(self.db, attr, krate) - } - /// Expands the macro if it isn't one of the built-in ones that expand to custom syntax or dummy /// expansions. pub fn expand_allowed_builtins( @@ -608,8 +599,8 @@ pub fn expand_attr_macro(&self, item: &ast::Item) -> Option Option { - let adt = attr.syntax().parent().and_then(ast::Adt::cast)?; + pub fn expand_derive_as_pseudo_attr_macro(&self, attr: &ast::Meta) -> Option { + let adt = attr.parent_attr()?.syntax().parent().and_then(ast::Adt::cast)?; let src = self.wrap_node_infile(attr.clone()); let call_id = self.with_ctx(|ctx| { ctx.attr_to_derive_macro_call(src.with_value(&adt), src).map(|(_, it, _)| it) @@ -617,7 +608,7 @@ pub fn expand_derive_as_pseudo_attr_macro(&self, attr: &ast::Attr) -> Option Option>> { + pub fn resolve_derive_macro(&self, attr: &ast::Meta) -> Option>> { let calls = self.derive_macro_calls(attr)?; self.with_ctx(|ctx| { Some( @@ -644,7 +635,7 @@ pub fn resolve_derive_macro(&self, attr: &ast::Attr) -> Option pub fn expand_derive_macro( &self, - attr: &ast::Attr, + attr: &ast::Meta, ) -> Option>>> { let res: Vec<_> = self .derive_macro_calls(attr)? @@ -662,9 +653,9 @@ pub fn expand_derive_macro( fn derive_macro_calls( &self, - attr: &ast::Attr, + attr: &ast::Meta, ) -> Option>>> { - let adt = attr.syntax().parent().and_then(ast::Adt::cast)?; + let adt = attr.parent_attr()?.syntax().parent().and_then(ast::Adt::cast)?; let file_id = self.find_file(adt.syntax()).file_id; let adt = InFile::new(file_id, &adt); let src = InFile::new(file_id, attr.clone()); @@ -773,7 +764,11 @@ pub fn speculative_expand_derive_as_pseudo_attr_macro( let attr = self.wrap_node_infile(actual_macro_call.clone()); let adt = actual_macro_call.syntax().parent().and_then(ast::Adt::cast)?; let macro_call_id = self.with_ctx(|ctx| { - ctx.attr_to_derive_macro_call(attr.with_value(&adt), attr).map(|(_, it, _)| it) + ctx.attr_to_derive_macro_call( + attr.with_value(&adt), + attr.with_value(attr.value.meta()?), + ) + .map(|(_, it, _)| it) })?; hir_expand::db::expand_speculative( self.db, @@ -1328,7 +1323,7 @@ fn descend_into_macros_impl( // text ranges of the outer ones, and then all of the inner ones up // to the invoking attribute so that the inbetween is ignored. // FIXME: Should cfg_attr be handled differently? - let (attr, _, _, _) = attr_ids + let (attr, _) = attr_ids .invoc_attr() .find_attr_range_with_source(db, loc.krate, &item); let start = attr.syntax().text_range().start(); @@ -1435,7 +1430,7 @@ fn descend_into_macros_impl( let derive_call = ctx .attr_to_derive_macro_call( InFile::new(expansion, &adt), - InFile::new(expansion, attr.clone()), + InFile::new(expansion, meta.clone()), )? .1; @@ -2461,7 +2456,7 @@ fn macro_call_to_macro_id( Either::Left(it) => { let node = match it.file_id { HirFileId::FileId(file_id) => { - it.to_ptr(db).to_node(&db.parse(file_id).syntax_node()) + it.to_ptr(db).to_node(&file_id.parse(db).syntax_node()) } HirFileId::MacroFile(macro_file) => { let expansion_info = ctx.cache.get_or_insert_expansion(ctx.db, macro_file); @@ -2473,7 +2468,7 @@ fn macro_call_to_macro_id( Either::Right(it) => { let node = match it.file_id { HirFileId::FileId(file_id) => { - it.to_ptr(db).to_node(&db.parse(file_id).syntax_node()) + it.to_ptr(db).to_node(&file_id.parse(db).syntax_node()) } HirFileId::MacroFile(macro_file) => { let expansion_info = ctx.cache.get_or_insert_expansion(ctx.db, macro_file); diff --git a/src/tools/rust-analyzer/crates/hir/src/semantics/child_by_source.rs b/src/tools/rust-analyzer/crates/hir/src/semantics/child_by_source.rs index f6d1bec5754c..babeb3591345 100644 --- a/src/tools/rust-analyzer/crates/hir/src/semantics/child_by_source.rs +++ b/src/tools/rust-analyzer/crates/hir/src/semantics/child_by_source.rs @@ -126,8 +126,7 @@ fn child_by_source_to(&self, db: &dyn DefDatabase, res: &mut DynMap, file_id: Hi calls.for_each(|(attr_id, call_id, calls)| { // FIXME: Is this the right crate? let krate = call_id.lookup(db).krate; - // FIXME: Fix cfg_attr handling. - let (attr, _, _, _) = attr_id.find_attr_range_with_source(db, krate, &adt); + let (_, attr) = attr_id.find_attr_range_with_source(db, krate, &adt); res[keys::DERIVE_MACRO_CALL] .insert(AstPtr::new(&attr), (attr_id, call_id, calls.into())); }); diff --git a/src/tools/rust-analyzer/crates/hir/src/semantics/source_to_def.rs b/src/tools/rust-analyzer/crates/hir/src/semantics/source_to_def.rs index a9a779a287d6..d932198b43a7 100644 --- a/src/tools/rust-analyzer/crates/hir/src/semantics/source_to_def.rs +++ b/src/tools/rust-analyzer/crates/hir/src/semantics/source_to_def.rs @@ -85,6 +85,7 @@ //! active crate for a given position, and then provide an API to resolve all //! syntax nodes against this specific crate. +use base_db::relevant_crates; use either::Either; use hir_def::{ AdtId, BlockId, BuiltinDeriveImplId, ConstId, ConstParamId, DefWithBodyId, EnumId, @@ -145,7 +146,7 @@ pub(super) fn get_or_insert_include_for( return m; } self.included_file_cache.insert(file, None); - for &crate_id in db.relevant_crates(file.file_id(db)).iter() { + for &crate_id in relevant_crates(db, file.file_id(db)).iter() { db.include_macro_invoc(crate_id).iter().for_each(|&(macro_call_id, file_id)| { self.included_file_cache.insert(file_id, Some(macro_call_id)); }); @@ -180,7 +181,7 @@ impl SourceToDefCtx<'_, '_> { self.cache.file_to_def_cache.entry(file).or_insert_with(|| { let mut mods = SmallVec::new(); - for &crate_id in self.db.relevant_crates(file).iter() { + for &crate_id in relevant_crates(self.db, file).iter() { // Note: `mod` declarations in block modules cannot be supported here let crate_def_map = crate_def_map(self.db, crate_id); let n_mods = mods.len(); @@ -397,7 +398,7 @@ pub(super) fn label_ref_to_def( pub(super) fn attr_to_derive_macro_call( &mut self, item: InFile<&ast::Adt>, - src: InFile, + src: InFile, ) -> Option<(AttrId, MacroCallId, &[Option>])> { let map = self.dyn_map(item)?; map[keys::DERIVE_MACRO_CALL] @@ -422,6 +423,7 @@ impl Iterator< let dyn_map = &map[keys::DERIVE_MACRO_CALL]; adt.value .attrs() + .flat_map(|attr| attr.skip_cfg_attrs()) .filter_map(move |attr| dyn_map.get(&AstPtr::new(&attr))) .map(|&(attr_id, call_id, ref ids)| (attr_id, call_id, &**ids)) }) diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_impl_members.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_impl_members.rs index afdced4215f9..44b367059eca 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_impl_members.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_impl_members.rs @@ -1,7 +1,7 @@ use hir::HasSource; use syntax::{ Edition, - ast::{self, AstNode, make}, + ast::{self, AstNode, syntax_factory::SyntaxFactory}, syntax_editor::{Position, SyntaxEditor}, }; @@ -148,7 +148,9 @@ fn add_missing_impl_members_inner( let target = impl_def.syntax().text_range(); acc.add(AssistId::quick_fix(assist_id), label, target, |edit| { + let make = SyntaxFactory::with_mappings(); let new_item = add_trait_assoc_items_to_impl( + &make, &ctx.sema, ctx.config, &missing_items, @@ -164,6 +166,7 @@ fn add_missing_impl_members_inner( let mut first_new_item = if let DefaultMethods::No = mode && let ast::AssocItem::Fn(func) = &first_new_item && let Some(body) = try_gen_trait_body( + &make, ctx, func, trait_ref, @@ -172,7 +175,7 @@ fn add_missing_impl_members_inner( ) && let Some(func_body) = func.body() { - let mut func_editor = SyntaxEditor::new(first_new_item.syntax().clone_subtree()); + let (mut func_editor, _) = SyntaxEditor::new(first_new_item.syntax().clone()); func_editor.replace(func_body.syntax(), body.syntax()); ast::AssocItem::cast(func_editor.finish().new_root().clone()) } else { @@ -189,10 +192,10 @@ fn add_missing_impl_members_inner( if let Some(assoc_item_list) = impl_def.assoc_item_list() { assoc_item_list.add_items(&mut editor, new_assoc_items); } else { - let assoc_item_list = make::assoc_item_list(Some(new_assoc_items)).clone_for_update(); + let assoc_item_list = make.assoc_item_list(new_assoc_items); editor.insert_all( Position::after(impl_def.syntax()), - vec![make::tokens::whitespace(" ").into(), assoc_item_list.syntax().clone().into()], + vec![make.whitespace(" ").into(), assoc_item_list.syntax().clone().into()], ); first_new_item = assoc_item_list.assoc_items().next(); } @@ -215,23 +218,24 @@ fn add_missing_impl_members_inner( editor.add_annotation(first_new_item.syntax(), tabstop); }; }; + editor.add_mappings(make.finish_with_mappings()); edit.add_file_edits(ctx.vfs_file_id(), editor); }) } fn try_gen_trait_body( + make: &SyntaxFactory, ctx: &AssistContext<'_>, func: &ast::Fn, trait_ref: hir::TraitRef<'_>, impl_def: &ast::Impl, edition: Edition, ) -> Option { - let trait_path = make::ext::ident_path( - &trait_ref.trait_().name(ctx.db()).display(ctx.db(), edition).to_string(), - ); + let trait_path = + make.ident_path(&trait_ref.trait_().name(ctx.db()).display(ctx.db(), edition).to_string()); let hir_ty = ctx.sema.resolve_type(&impl_def.self_ty()?)?; let adt = hir_ty.as_adt()?.source(ctx.db())?; - gen_trait_fn_body(func, &trait_path, &adt.value, Some(trait_ref)) + gen_trait_fn_body(make, func, &trait_path, &adt.value, Some(trait_ref)) } #[cfg(test)] diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_match_arms.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_match_arms.rs index b063e5ffce87..b7510bb82676 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_match_arms.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/add_missing_match_arms.rs @@ -1,4 +1,4 @@ -use std::iter::{self, Peekable}; +use std::iter; use either::Either; use hir::{Adt, AsAssocItem, Crate, FindPathConfig, HasAttrs, ModuleDef, Semantics}; @@ -93,8 +93,8 @@ pub(crate) fn add_missing_match_arms(acc: &mut Assists, ctx: &AssistContext<'_>) } else { None }; - let (mut missing_pats, is_non_exhaustive, has_hidden_variants): ( - Peekable>>, + let (missing_pats, is_non_exhaustive, has_hidden_variants): ( + Vec<(ast::Pat, bool)>, bool, bool, ) = if let Some(enum_def) = resolve_enum_def(&ctx.sema, &expr, self_ty.as_ref()) { @@ -117,15 +117,15 @@ pub(crate) fn add_missing_match_arms(acc: &mut Assists, ctx: &AssistContext<'_>) .filter(|(variant_pat, _)| is_variant_missing(&top_lvl_pats, variant_pat)); let option_enum = FamousDefs(&ctx.sema, module.krate(ctx.db())).core_option_Option(); - let missing_pats: Box> = if matches!(enum_def, ExtendedEnum::Enum { enum_: e, .. } if Some(e) == option_enum) + let missing_pats: Vec<_> = if matches!(enum_def, ExtendedEnum::Enum { enum_: e, .. } if Some(e) == option_enum) { // Match `Some` variant first. cov_mark::hit!(option_order); - Box::new(missing_pats.rev()) + missing_pats.rev().collect() } else { - Box::new(missing_pats) + missing_pats.collect() }; - (missing_pats.peekable(), is_non_exhaustive, has_hidden_variants) + (missing_pats, is_non_exhaustive, has_hidden_variants) } else if let Some(enum_defs) = resolve_tuple_of_enum_def(&ctx.sema, &expr, self_ty.as_ref()) { let is_non_exhaustive = enum_defs .iter() @@ -169,12 +169,9 @@ pub(crate) fn add_missing_match_arms(acc: &mut Assists, ctx: &AssistContext<'_>) (ast::Pat::from(make.tuple_pat(patterns)), is_hidden) }) - .filter(|(variant_pat, _)| is_variant_missing(&top_lvl_pats, variant_pat)); - ( - (Box::new(missing_pats) as Box>).peekable(), - is_non_exhaustive, - has_hidden_variants, - ) + .filter(|(variant_pat, _)| is_variant_missing(&top_lvl_pats, variant_pat)) + .collect(); + (missing_pats, is_non_exhaustive, has_hidden_variants) } else if let Some((enum_def, len)) = resolve_array_of_enum_def(&ctx.sema, &expr, self_ty.as_ref()) { @@ -205,12 +202,9 @@ pub(crate) fn add_missing_match_arms(acc: &mut Assists, ctx: &AssistContext<'_>) (ast::Pat::from(make.slice_pat(patterns)), is_hidden) }) - .filter(|(variant_pat, _)| is_variant_missing(&top_lvl_pats, variant_pat)); - ( - (Box::new(missing_pats) as Box>).peekable(), - is_non_exhaustive, - has_hidden_variants, - ) + .filter(|(variant_pat, _)| is_variant_missing(&top_lvl_pats, variant_pat)) + .collect(); + (missing_pats, is_non_exhaustive, has_hidden_variants) } else { return None; }; @@ -218,20 +212,31 @@ pub(crate) fn add_missing_match_arms(acc: &mut Assists, ctx: &AssistContext<'_>) let mut needs_catch_all_arm = is_non_exhaustive && !has_catch_all_arm; if !needs_catch_all_arm - && ((has_hidden_variants && has_catch_all_arm) || missing_pats.peek().is_none()) + && ((has_hidden_variants && has_catch_all_arm) || missing_pats.is_empty()) { return None; } + let visible_count = missing_pats.iter().filter(|(_, hidden)| !hidden).count(); + let label = if visible_count == 0 { + "Add missing catch-all match arm `_`".to_owned() + } else if visible_count == 1 { + let pat = &missing_pats.iter().find(|(_, hidden)| !hidden).unwrap().0; + format!("Add missing match arm `{pat}`") + } else { + format!("Add {visible_count} missing match arms") + }; + acc.add( AssistId::quick_fix("add_missing_match_arms"), - "Fill match arms", + label, ctx.sema.original_range(match_expr.syntax()).range, |builder| { // having any hidden variants means that we need a catch-all arm needs_catch_all_arm |= has_hidden_variants; let mut missing_arms = missing_pats + .into_iter() .filter(|(_, hidden)| { // filter out hidden patterns because they're handled by the catch-all arm !hidden @@ -635,7 +640,7 @@ mod tests { use crate::AssistConfig; use crate::tests::{ TEST_CONFIG, check_assist, check_assist_not_applicable, check_assist_target, - check_assist_unresolved, check_assist_with_config, + check_assist_unresolved, check_assist_with_config, check_assist_with_label, }; use super::add_missing_match_arms; @@ -1828,8 +1833,10 @@ fn foo(t: Test) { #[test] fn lazy_computation() { - // Computing a single missing arm is enough to determine applicability of the assist. - cov_mark::check_count!(add_missing_match_arms_lazy_computation, 1); + // We now collect all missing arms eagerly, so we can show the count + // of missing arms. + cov_mark::check_count!(add_missing_match_arms_lazy_computation, 4); + check_assist_unresolved( add_missing_match_arms, r#" @@ -1841,6 +1848,54 @@ fn foo(tuple: (A, A)) { ); } + #[test] + fn label_single_missing_arm() { + check_assist_with_label( + add_missing_match_arms, + r#" +enum A { One, Two } +fn foo(a: A) { + match $0a { + A::One => {} + } +} +"#, + "Add missing match arm `A::Two`", + ); + } + + #[test] + fn label_multiple_missing_arms() { + check_assist_with_label( + add_missing_match_arms, + r#" +enum A { One, Two, Three } +fn foo(a: A) { + match $0a {} +} +"#, + "Add 3 missing match arms", + ); + } + + #[test] + fn label_catch_all_only() { + check_assist_with_label( + add_missing_match_arms, + r#" +//- /main.rs crate:main deps:e +fn foo(t: ::e::E) { + match $0t { + e::E::A => {} + } +} +//- /e.rs crate:e +pub enum E { A, #[doc(hidden)] B, } +"#, + "Add missing catch-all match arm `_`", + ); + } + #[test] fn adds_comma_before_new_arms() { check_assist( diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/apply_demorgan.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/apply_demorgan.rs index 4ee49702489d..2ea0d76b0161 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/apply_demorgan.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/apply_demorgan.rs @@ -82,8 +82,7 @@ pub(crate) fn apply_demorgan(acc: &mut Assists, ctx: &AssistContext<'_>) -> Opti let make = SyntaxFactory::with_mappings(); - let demorganed = bin_expr.clone_subtree(); - let mut editor = SyntaxEditor::new(demorganed.syntax().clone()); + let (mut editor, demorganed) = SyntaxEditor::with_ast_node(&bin_expr); editor.replace(demorganed.op_token()?, make.token(inv_token)); let mut exprs = VecDeque::from([ diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/auto_import.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/auto_import.rs index de5dfdf4d954..adeb191719fb 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/auto_import.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/auto_import.rs @@ -1928,4 +1928,33 @@ fn f() { "#; check_auto_import_order(before, &["Import `foo::wanted`", "Import `quux::wanted`"]); } + + #[test] + fn consider_definition_kind() { + check_assist( + auto_import, + r#" +//- /eyre.rs crate:eyre +#[macro_export] +macro_rules! eyre { + () => {}; +} + +//- /color-eyre.rs crate:color-eyre deps:eyre +pub use eyre; + +//- /main.rs crate:main deps:color-eyre +fn main() { + ey$0re!(); +} + "#, + r#" +use color_eyre::eyre::eyre; + +fn main() { + eyre!(); +} + "#, + ); + } } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_bool_then.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_bool_then.rs index b3bfe5b8c41a..c36c79ee998b 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_bool_then.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_bool_then.rs @@ -77,8 +77,7 @@ pub(crate) fn convert_if_to_bool_then(acc: &mut Assists, ctx: &AssistContext<'_> "Convert `if` expression to `bool::then` call", target, |builder| { - let closure_body = closure_body.clone_subtree(); - let mut editor = SyntaxEditor::new(closure_body.syntax().clone()); + let (mut editor, closure_body) = SyntaxEditor::with_ast_node(&closure_body); // Rewrite all `Some(e)` in tail position to `e` for_each_tail_expr(&closure_body, &mut |e| { let e = match e { @@ -188,8 +187,7 @@ pub(crate) fn convert_bool_then_to_if(acc: &mut Assists, ctx: &AssistContext<'_> e => mapless_make.block_expr(None, Some(e)), }; - let closure_body = closure_body.clone_subtree(); - let mut editor = SyntaxEditor::new(closure_body.syntax().clone()); + let (mut editor, closure_body) = SyntaxEditor::with_ast_node(&closure_body); // Wrap all tails in `Some(...)` let none_path = mapless_make.expr_path(mapless_make.ident_path("None")); let some_path = mapless_make.expr_path(mapless_make.ident_path("Some")); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_for_to_while_let.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_for_to_while_let.rs index 15f324eff329..a5c29a45a51f 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_for_to_while_let.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_for_to_while_let.rs @@ -81,14 +81,14 @@ pub(crate) fn convert_for_loop_to_while_let( let indent = IndentLevel::from_node(for_loop.syntax()); if let Some(label) = for_loop.label() { - let label = label.syntax().clone_for_update(); + let label = label.syntax(); editor.insert(Position::before(for_loop.syntax()), make.whitespace(" ")); editor.insert(Position::before(for_loop.syntax()), label); } crate::utils::insert_attributes( for_loop.syntax(), &mut editor, - for_loop.attrs().map(|it| it.clone_for_update()), + for_loop.attrs(), &make, ); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_let_else_to_match.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_let_else_to_match.rs index d2336a4a5d8d..9a9808e270fa 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_let_else_to_match.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_let_else_to_match.rs @@ -32,10 +32,12 @@ pub(crate) fn convert_let_else_to_match(acc: &mut Assists, ctx: &AssistContext<' .or_else(|| ctx.find_token_syntax_at_offset(T![let])?.parent())?; let let_stmt = LetStmt::cast(let_stmt)?; let else_block = let_stmt.let_else()?.block_expr()?; - let else_expr = if else_block.statements().next().is_none() { - else_block.tail_expr()? + let else_expr = if else_block.statements().next().is_none() + && let Some(tail_expr) = else_block.tail_expr() + { + tail_expr.reset_indent() } else { - else_block.into() + else_block.reset_indent().into() }; let init = let_stmt.initializer()?; // Ignore let stmt with type annotation @@ -91,8 +93,8 @@ pub(crate) fn convert_let_else_to_match(acc: &mut Assists, ctx: &AssistContext<' }, ); let else_arm = make.match_arm(make.wildcard_pat().into(), None, else_expr); - let match_ = make.expr_match(init, make.match_arm_list([binding_arm, else_arm])); - let match_ = match_.reset_indent(); + let arms = [binding_arm, else_arm].map(|arm| arm.indent(1.into())); + let match_ = make.expr_match(init, make.match_arm_list(arms)); let match_ = match_.indent(let_stmt.indent_level()); if bindings.is_empty() { @@ -190,7 +192,7 @@ fn remove_mut_and_collect_idents( let inner = p.pat()?; if let ast::Pat::IdentPat(ident) = inner { acc.push(ident); - p.clone_for_update().into() + p.clone().into() } else { make.ref_pat(remove_mut_and_collect_idents(make, &inner, acc)?).into() } @@ -298,6 +300,81 @@ fn main() { ); } + #[test] + fn convert_let_else_to_match_with_empty_else_block() { + check_assist( + convert_let_else_to_match, + r" +fn main() { + let Ok(x) = f() else$0 {}; +}", + r" +fn main() { + let x = match f() { + Ok(x) => x, + _ => {} + }; +}", + ); + } + + #[test] + fn convert_let_else_to_match_with_some_indent() { + check_assist( + convert_let_else_to_match, + r#" +mod indent { + fn main() { + let Ok(x) = f() else$0 { + log(); + unreachable!( + "..." + ); + }; + } +}"#, + r#" +mod indent { + fn main() { + let x = match f() { + Ok(x) => x, + _ => { + log(); + unreachable!( + "..." + ); + } + }; + } +}"#, + ); + + check_assist( + convert_let_else_to_match, + r#" +mod indent { + fn main() { + let Ok(x) = f() else$0 { + unreachable!( + "..." + ) + }; + } +}"#, + r#" +mod indent { + fn main() { + let x = match f() { + Ok(x) => x, + _ => unreachable!( + "..." + ), + }; + } +}"#, + ); + } + #[test] fn convert_let_else_to_match_const_ref() { check_assist( diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_match_to_let_else.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_match_to_let_else.rs index 1a6d176c9054..4b132d68ee3a 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_match_to_let_else.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_match_to_let_else.rs @@ -121,8 +121,7 @@ fn find_extracted_variable(ctx: &AssistContext<'_>, arm: &ast::MatchArm) -> Opti // Rename `extracted` with `binding` in `pat`. fn rename_variable(pat: &ast::Pat, extracted: &[Name], binding: ast::Pat) -> SyntaxNode { - let syntax = pat.syntax().clone_subtree(); - let mut editor = SyntaxEditor::new(syntax.clone()); + let (mut editor, syntax) = SyntaxEditor::new(pat.syntax().clone()); let make = SyntaxFactory::with_mappings(); let extracted = extracted .iter() @@ -138,15 +137,12 @@ fn rename_variable(pat: &ast::Pat, extracted: &[Name], binding: ast::Pat) -> Syn if let Some(name_ref) = record_pat_field.field_name() { editor.replace( record_pat_field.syntax(), - make.record_pat_field( - make.name_ref(&name_ref.text()), - binding.clone_for_update(), - ) - .syntax(), + make.record_pat_field(make.name_ref(&name_ref.text()), binding.clone()) + .syntax(), ); } } else { - editor.replace(extracted_syntax, binding.syntax().clone_for_update()); + editor.replace(extracted_syntax, binding.syntax()); } } editor.add_mappings(make.finish_with_mappings()); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_named_struct_to_tuple_struct.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_named_struct_to_tuple_struct.rs index aaf727058cf1..4ea56e3e613f 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_named_struct_to_tuple_struct.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_named_struct_to_tuple_struct.rs @@ -102,11 +102,11 @@ fn edit_struct_def( // Note that we don't need to consider macro files in this function because this is // currently not triggered for struct definitions inside macro calls. let tuple_fields = record_fields.fields().filter_map(|f| { - let field = ast::make::tuple_field(f.visibility(), f.ty()?); - let mut editor = SyntaxEditor::new(field.syntax().clone()); + let (mut editor, field) = + SyntaxEditor::with_ast_node(&ast::make::tuple_field(f.visibility(), f.ty()?)); editor.insert_all( Position::first_child_of(field.syntax()), - f.attrs().map(|attr| attr.syntax().clone_subtree().clone_for_update().into()).collect(), + f.attrs().map(|attr| attr.syntax().clone().into()).collect(), ); let field_syntax = editor.finish().new_root().clone(); let field = ast::TupleField::cast(field_syntax)?; @@ -328,8 +328,7 @@ fn delete_whitespace(edit: &mut SyntaxEditor, whitespace: Option) } fn remove_trailing_comma(w: ast::WhereClause) -> SyntaxNode { - let w = w.syntax().clone_subtree(); - let mut editor = SyntaxEditor::new(w.clone()); + let (mut editor, w) = SyntaxEditor::new(w.syntax().clone()); if let Some(last) = w.last_child_or_token() && last.kind() == T![,] { diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_range_for_to_while.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_range_for_to_while.rs index 2e649f14be26..61393950767f 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_range_for_to_while.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_range_for_to_while.rs @@ -133,7 +133,7 @@ fn process_loop_body( ) -> Option<()> { let last = previous_non_trivia_token(body.r_curly_token()?)?.syntax_element(); - let new_body = body.indent(1.into()).clone_subtree(); + let new_body = body.indent(1.into()); let mut continues = vec![]; collect_continue_to( &mut continues, @@ -155,15 +155,15 @@ fn process_loop_body( let block_content = first.clone()..=children.last().unwrap_or(first); let continue_label = make::lifetime("'cont"); - let break_expr = make::expr_break(Some(continue_label.clone()), None).clone_for_update(); - let mut new_edit = SyntaxEditor::new(new_body.syntax().clone()); + let break_expr = make::expr_break(Some(continue_label.clone()), None); + let (mut new_edit, _) = SyntaxEditor::new(new_body.syntax().clone()); for continue_expr in &continues { new_edit.replace(continue_expr.syntax(), break_expr.syntax()); } let new_body = new_edit.finish().new_root().clone(); let elements = itertools::chain( [ - continue_label.syntax().clone_for_update().syntax_element(), + continue_label.syntax().syntax_element(), make::token(T![:]).syntax_element(), make::tokens::single_space().syntax_element(), new_body.syntax_element(), diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_to_guarded_return.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_to_guarded_return.rs index db4591679220..004d09acac6e 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_to_guarded_return.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_to_guarded_return.rs @@ -1,17 +1,19 @@ use std::iter::once; use either::Either; -use hir::{Semantics, TypeInfo}; +use hir::Semantics; use ide_db::{RootDatabase, ty_filter::TryEnum}; use syntax::{ AstNode, - SyntaxKind::{CLOSURE_EXPR, FN, FOR_EXPR, LOOP_EXPR, WHILE_EXPR, WHITESPACE}, + SyntaxKind::WHITESPACE, SyntaxNode, T, ast::{ self, edit::{AstNodeEdit, IndentLevel}, syntax_factory::SyntaxFactory, }, + match_ast, + syntax_editor::SyntaxEditor, }; use crate::{ @@ -71,9 +73,7 @@ fn if_expr_to_guarded_return( ) -> Option<()> { let make = SyntaxFactory::without_mappings(); let else_block = match if_expr.else_branch() { - Some(ast::ElseBranch::Block(block_expr)) if is_never_block(&ctx.sema, &block_expr) => { - Some(block_expr) - } + Some(ast::ElseBranch::Block(block_expr)) => Some(block_expr), Some(_) => return None, _ => None, }; @@ -96,25 +96,20 @@ fn if_expr_to_guarded_return( let parent_block = if_expr.syntax().parent()?.ancestors().find_map(ast::BlockExpr::cast)?; - if parent_block.tail_expr() != Some(if_expr.clone().into()) - && !(else_block.is_some() && ast::ExprStmt::can_cast(if_expr.syntax().parent()?.kind())) - { - return None; - } - // check for early return and continue if is_early_block(&then_block) || is_never_block(&ctx.sema, &then_branch) { return None; } - let parent_container = parent_block.syntax().parent()?; + let container = container_of(&parent_block)?; + let else_block = ElseBlock::new(&ctx.sema, else_block, &container)?; - let early_expression = else_block - .or_else(|| { - early_expression(parent_container, &ctx.sema, &make) - .map(ast::make::tail_only_block_expr) - })? - .reset_indent(); + if parent_block.tail_expr() != Some(if_expr.clone().into()) + && !(else_block.is_never_block + && ast::ExprStmt::can_cast(if_expr.syntax().parent()?.kind())) + { + return None; + } then_block.syntax().first_child_or_token().map(|t| t.kind() == T!['{'])?; @@ -137,6 +132,7 @@ fn if_expr_to_guarded_return( |edit| { let make = SyntaxFactory::without_mappings(); let if_indent_level = IndentLevel::from_node(if_expr.syntax()); + let early_expression = else_block.make_early_block(&ctx.sema, &make); let replacement = let_chains.into_iter().map(|expr| { if let ast::Expr::LetExpr(let_expr) = &expr && let (Some(pat), Some(expr)) = (let_expr.pat(), let_expr.expr()) @@ -204,14 +200,9 @@ fn let_stmt_to_guarded_return( let happy_pattern = try_enum.happy_pattern(pat); let target = let_stmt.syntax().text_range(); - let make = SyntaxFactory::without_mappings(); - let early_expression: ast::Expr = { - let parent_block = - let_stmt.syntax().parent()?.ancestors().find_map(ast::BlockExpr::cast)?; - let parent_container = parent_block.syntax().parent()?; - - early_expression(parent_container, &ctx.sema, &make)? - }; + let parent_block = let_stmt.syntax().parent()?.ancestors().find_map(ast::BlockExpr::cast)?; + let container = container_of(&parent_block)?; + let else_block = ElseBlock::new(&ctx.sema, None, &container)?; acc.add( AssistId::refactor_rewrite("convert_to_guarded_return"), @@ -226,7 +217,7 @@ fn let_stmt_to_guarded_return( happy_pattern, let_stmt.ty(), expr.reset_indent(), - ast::make::tail_only_block_expr(early_expression), + else_block.make_early_block(&ctx.sema, &make), ); let let_else_stmt = let_else_stmt.indent(let_indent_level); let_else_stmt.syntax().clone() @@ -239,33 +230,130 @@ fn let_stmt_to_guarded_return( ) } -fn early_expression( - parent_container: SyntaxNode, - sema: &Semantics<'_, RootDatabase>, - make: &SyntaxFactory, -) -> Option { - let return_none_expr = || { - let none_expr = make.expr_path(make.ident_path("None")); - make.expr_return(Some(none_expr)) - }; - if let Some(fn_) = ast::Fn::cast(parent_container.clone()) - && let Some(fn_def) = sema.to_def(&fn_) - && let Some(TryEnum::Option) = TryEnum::from_ty(sema, &fn_def.ret_type(sema.db)) - { - return Some(return_none_expr().into()); +fn container_of(block: &ast::BlockExpr) -> Option { + if block.label().is_some() { + return Some(block.syntax().clone()); } - if let Some(body) = ast::ClosureExpr::cast(parent_container.clone()).and_then(|it| it.body()) - && let Some(ret_ty) = sema.type_of_expr(&body).map(TypeInfo::original) - && let Some(TryEnum::Option) = TryEnum::from_ty(sema, &ret_ty) - { - return Some(return_none_expr().into()); + block.syntax().parent() +} + +struct ElseBlock<'db> { + exist_else_block: Option, + is_never_block: bool, + kind: EarlyKind<'db>, +} + +impl<'db> ElseBlock<'db> { + fn new( + sema: &Semantics<'db, RootDatabase>, + exist_else_block: Option, + parent_container: &SyntaxNode, + ) -> Option { + let is_never_block = exist_else_block.as_ref().is_some_and(|it| is_never_block(sema, it)); + let kind = EarlyKind::from_node(parent_container, sema)?; + + Some(Self { exist_else_block, is_never_block, kind }) } - Some(match parent_container.kind() { - WHILE_EXPR | LOOP_EXPR | FOR_EXPR => make.expr_continue(None).into(), - FN | CLOSURE_EXPR => make.expr_return(None).into(), - _ => return None, - }) + fn make_early_block( + self, + sema: &Semantics<'_, RootDatabase>, + make: &SyntaxFactory, + ) -> ast::BlockExpr { + let Some(block_expr) = self.exist_else_block else { + return make.tail_only_block_expr(self.kind.make_early_expr(sema, make, None)); + }; + + if self.is_never_block { + return block_expr.reset_indent(); + } + + let (mut edit, block_expr) = SyntaxEditor::with_ast_node(&block_expr.reset_indent()); + + let last_stmt = block_expr.statements().last().map(|it| it.syntax().clone()); + let tail_expr = block_expr.tail_expr().map(|it| it.syntax().clone()); + let Some(last_element) = tail_expr.clone().or(last_stmt.clone()) else { + return make.tail_only_block_expr(self.kind.make_early_expr(sema, make, None)); + }; + let whitespace = last_element.prev_sibling_or_token().filter(|it| it.kind() == WHITESPACE); + + let make = SyntaxFactory::without_mappings(); + + if let Some(tail_expr) = block_expr.tail_expr() + && !self.kind.is_unit() + { + let early_expr = self.kind.make_early_expr(sema, &make, Some(tail_expr.clone())); + edit.replace(tail_expr.syntax(), early_expr.syntax()); + } else { + let last_stmt = match block_expr.tail_expr() { + Some(expr) => make.expr_stmt(expr).syntax().clone(), + None => last_element.clone(), + }; + let whitespace = + make.whitespace(&whitespace.map_or(String::new(), |it| it.to_string())); + let early_expr = self.kind.make_early_expr(sema, &make, None).syntax().clone().into(); + edit.replace_with_many( + last_element, + vec![last_stmt.into(), whitespace.into(), early_expr], + ); + } + + ast::BlockExpr::cast(edit.finish().new_root().clone()).unwrap() + } +} + +enum EarlyKind<'db> { + Continue, + Break(ast::Lifetime, hir::Type<'db>), + Return(hir::Type<'db>), +} + +impl<'db> EarlyKind<'db> { + fn from_node( + parent_container: &SyntaxNode, + sema: &Semantics<'db, RootDatabase>, + ) -> Option { + match_ast! { + match parent_container { + ast::Fn(it) => Some(Self::Return(sema.to_def(&it)?.ret_type(sema.db))), + ast::ClosureExpr(it) => Some(Self::Return(sema.type_of_expr(&it.body()?)?.original)), + ast::BlockExpr(it) => Some(Self::Break(it.label()?.lifetime()?, sema.type_of_expr(&it.into())?.original)), + ast::WhileExpr(_) => Some(Self::Continue), + ast::LoopExpr(_) => Some(Self::Continue), + ast::ForExpr(_) => Some(Self::Continue), + _ => None + } + } + } + + fn make_early_expr( + &self, + sema: &Semantics<'_, RootDatabase>, + make: &SyntaxFactory, + ret: Option, + ) -> ast::Expr { + match self { + EarlyKind::Continue => make.expr_continue(None).into(), + EarlyKind::Break(label, _) => make.expr_break(Some(label.clone()), ret).into(), + EarlyKind::Return(ty) => { + let expr = match TryEnum::from_ty(sema, ty) { + Some(TryEnum::Option) => { + ret.or_else(|| Some(make.expr_path(make.ident_path("None")))) + } + _ => ret, + }; + make.expr_return(expr).into() + } + } + } + + fn is_unit(&self) -> bool { + match self { + EarlyKind::Continue => true, + EarlyKind::Break(_, ty) => ty.is_unit(), + EarlyKind::Return(ty) => ty.is_unit(), + } + } } fn flat_let_chain(mut expr: ast::Expr, make: &SyntaxFactory) -> Vec { @@ -464,6 +552,74 @@ fn main() { ); } + #[test] + fn convert_if_let_has_else_block() { + check_assist( + convert_to_guarded_return, + r#" +fn main() -> i32 { + if$0 true { + foo(); + } else { + bar() + } +} +"#, + r#" +fn main() -> i32 { + if false { + return bar(); + } + foo(); +} +"#, + ); + + check_assist( + convert_to_guarded_return, + r#" +fn main() { + if$0 true { + foo(); + } else { + bar() + } +} +"#, + r#" +fn main() { + if false { + bar(); + return + } + foo(); +} +"#, + ); + + check_assist( + convert_to_guarded_return, + r#" +fn main() { + if$0 true { + foo(); + } else { + bar(); + } +} +"#, + r#" +fn main() { + if false { + bar(); + return + } + foo(); +} +"#, + ); + } + #[test] fn convert_if_let_has_never_type_else_block() { check_assist( @@ -512,7 +668,7 @@ fn main() { } #[test] - fn convert_if_let_has_else_block_in_statement() { + fn convert_if_let_has_never_type_else_block_in_statement() { check_assist( convert_to_guarded_return, r#" @@ -922,6 +1078,63 @@ fn main() { ); } + #[test] + fn convert_let_inside_labeled_block() { + check_assist( + convert_to_guarded_return, + r#" +fn main() { + 'l: { + if$0 let Some(n) = n { + foo(n); + bar(); + } + } +} +"#, + r#" +fn main() { + 'l: { + let Some(n) = n else { break 'l }; + foo(n); + bar(); + } +} +"#, + ); + } + + #[test] + fn convert_let_inside_for_with_else() { + check_assist( + convert_to_guarded_return, + r#" +fn main() { + for n in ns { + if$0 let Some(n) = n { + foo(n); + bar(); + } else { + baz() + } + } +} +"#, + r#" +fn main() { + for n in ns { + let Some(n) = n else { + baz(); + continue + }; + foo(n); + bar(); + } +} +"#, + ); + } + #[test] fn convert_let_stmt_inside_fn() { check_assist( @@ -1186,16 +1399,18 @@ fn main() { } #[test] - fn ignore_else_branch() { + fn ignore_else_branch_has_non_never_types_in_statement() { check_assist_not_applicable( convert_to_guarded_return, r#" fn main() { + some_statements(); if$0 true { foo(); } else { bar() } + some_statements(); } "#, ); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_tuple_struct_to_named_struct.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_tuple_struct_to_named_struct.rs index ae41e6c015ce..4ce7a9d866a9 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_tuple_struct_to_named_struct.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/convert_tuple_struct_to_named_struct.rs @@ -103,11 +103,11 @@ fn edit_struct_def( names: Vec, ) { let record_fields = tuple_fields.fields().zip(names).filter_map(|(f, name)| { - let field = ast::make::record_field(f.visibility(), name, f.ty()?); - let mut field_editor = SyntaxEditor::new(field.syntax().clone()); + let (mut field_editor, field) = + SyntaxEditor::with_ast_node(&ast::make::record_field(f.visibility(), name, f.ty()?)); field_editor.insert_all( Position::first_child_of(field.syntax()), - f.attrs().map(|attr| attr.syntax().clone_subtree().clone_for_update().into()).collect(), + f.attrs().map(|attr| attr.syntax().clone().into()).collect(), ); ast::RecordField::cast(field_editor.finish().new_root().clone()) }); @@ -120,7 +120,7 @@ fn edit_struct_def( editor.delete(w.syntax()); let mut insert_element = Vec::new(); insert_element.push(ast::make::tokens::single_newline().syntax_element()); - insert_element.push(w.syntax().clone_for_update().syntax_element()); + insert_element.push(w.syntax().syntax_element()); if w.syntax().last_token().is_none_or(|t| t.kind() != SyntaxKind::COMMA) { insert_element.push(ast::make::token(T![,]).into()); } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_function.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_function.rs index 124ef509fb89..fa5bb39c54ba 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_function.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_function.rs @@ -92,11 +92,13 @@ pub(crate) fn extract_function(acc: &mut Assists, ctx: &AssistContext<'_>) -> Op let anchor = if self_param.is_some() { Anchor::Method } else { Anchor::Freestanding }; let insert_after = node_to_insert_after(&body, anchor)?; + let trait_name = ast::Trait::cast(insert_after.clone()).and_then(|trait_| trait_.name()); let semantics_scope = ctx.sema.scope(&insert_after)?; let module = semantics_scope.module(); let edition = semantics_scope.krate().edition(ctx.db()); - let (container_info, contains_tail_expr) = body.analyze_container(&ctx.sema, edition)?; + let (container_info, contains_tail_expr) = + body.analyze_container(&ctx.sema, edition, trait_name)?; let ret_ty = body.return_ty(ctx)?; let control_flow = body.external_control_flow(ctx, &container_info)?; @@ -181,6 +183,7 @@ pub(crate) fn extract_function(acc: &mut Assists, ctx: &AssistContext<'_>) -> Op builder.add_tabstop_before(cap, name); } + // FIXME: wrap non-adt types let fn_def = match fun.self_param_adt(ctx) { Some(adt) if anchor == Anchor::Method && !has_impl_wrapper => { fn_def.indent(1.into()); @@ -377,6 +380,7 @@ struct ControlFlow<'db> { struct ContainerInfo<'db> { is_const: bool, parent_loop: Option, + trait_name: Option, /// The function's return type, const's type etc. ret_type: Option>, generic_param_lists: Vec, @@ -838,6 +842,7 @@ fn analyze_container<'db>( &self, sema: &Semantics<'db, RootDatabase>, edition: Edition, + trait_name: Option, ) -> Option<(ContainerInfo<'db>, bool)> { let mut ancestors = self.parent()?.ancestors(); let infer_expr_opt = |expr| sema.type_of_expr(&expr?).map(TypeInfo::adjusted); @@ -924,6 +929,9 @@ fn analyze_container<'db>( false }; + // FIXME: make trait arguments + let trait_name = trait_name.map(|name| make::ty_path(make::ext::ident_path(&name.text()))); + let parent = self.parent()?; let parents = generic_parents(&parent); let generic_param_lists = parents.iter().filter_map(|it| it.generic_param_list()).collect(); @@ -934,6 +942,7 @@ fn analyze_container<'db>( ContainerInfo { is_const, parent_loop, + trait_name, ret_type: ty, generic_param_lists, where_clauses, @@ -1419,14 +1428,18 @@ fn fixup_call_site(builder: &mut SourceChangeBuilder, body: &FunctionBody) { fn make_call(ctx: &AssistContext<'_>, fun: &Function<'_>, indent: IndentLevel) -> SyntaxNode { let ret_ty = fun.return_type(ctx); - let args = make::arg_list(fun.params.iter().map(|param| param.to_arg(ctx, fun.mods.edition))); let name = fun.name.clone(); - let mut call_expr = if fun.self_param.is_some() { + let args = fun.params.iter().map(|param| param.to_arg(ctx, fun.mods.edition)); + let mut call_expr = if fun.make_this_param().is_some() { let self_arg = make::expr_path(make::ext::ident_path("self")); - make::expr_method_call(self_arg, name, args).into() + let func = make::expr_path(make::path_unqualified(make::path_segment(name))); + make::expr_call(func, make::arg_list(Some(self_arg).into_iter().chain(args))).into() + } else if fun.self_param.is_some() { + let self_arg = make::expr_path(make::ext::ident_path("self")); + make::expr_method_call(self_arg, name, make::arg_list(args)).into() } else { let func = make::expr_path(make::path_unqualified(make::path_segment(name))); - make::expr_call(func, args).into() + make::expr_call(func, make::arg_list(args)).into() }; let handler = FlowHandler::from_ret_ty(fun, &ret_ty); @@ -1729,9 +1742,28 @@ fn make_param_list( module: hir::Module, edition: Edition, ) -> ast::ParamList { - let self_param = self.self_param.clone(); + let this_param = self.make_this_param().map(|f| f()); + let self_param = self.self_param.clone().filter(|_| this_param.is_none()); let params = self.params.iter().map(|param| param.to_param(ctx, module, edition)); - make::param_list(self_param, params) + make::param_list(self_param, this_param.into_iter().chain(params)) + } + + fn make_this_param(&self) -> Option ast::Param> { + if let Some(name) = self.mods.trait_name.clone() + && let Some(self_param) = &self.self_param + { + Some(|| { + let bounds = make::type_bound_list([make::type_bound(name)]); + let pat = make::path_pat(make::ext::ident_path("this")); + let mut ty = make::impl_trait_type(bounds.unwrap()).into(); + if self_param.amp_token().is_some() { + ty = make::ty_ref(ty, self_param.mut_token().is_some()); + } + make::param(pat, ty) + }) + } else { + None + } } fn make_ret_ty(&self, ctx: &AssistContext<'_>, module: hir::Module) -> Option { @@ -1806,10 +1838,12 @@ fn make_body( ) -> ast::BlockExpr { let ret_ty = fun.return_type(ctx); let handler = FlowHandler::from_ret_ty(fun, &ret_ty); + let to_this_param = fun.self_param.clone().filter(|_| fun.make_this_param().is_some()); let block = match &fun.body { FunctionBody::Expr(expr) => { - let expr = rewrite_body_segment(ctx, &fun.params, &handler, expr.syntax()); + let expr = + rewrite_body_segment(ctx, to_this_param, &fun.params, &handler, expr.syntax()); let expr = ast::Expr::cast(expr).expect("Body segment should be an expr"); match expr { ast::Expr::BlockExpr(block) => { @@ -1847,7 +1881,7 @@ fn make_body( .filter(|it| text_range.contains_range(it.text_range())) .map(|it| match &it { syntax::NodeOrToken::Node(n) => syntax::NodeOrToken::Node( - rewrite_body_segment(ctx, &fun.params, &handler, n), + rewrite_body_segment(ctx, to_this_param.clone(), &fun.params, &handler, n), ), _ => it, }) @@ -1997,11 +2031,13 @@ fn make_ty(ty: &hir::Type<'_>, ctx: &AssistContext<'_>, module: hir::Module) -> fn rewrite_body_segment( ctx: &AssistContext<'_>, + to_this_param: Option, params: &[Param<'_>], handler: &FlowHandler<'_>, syntax: &SyntaxNode, ) -> SyntaxNode { - let syntax = fix_param_usages(ctx, params, syntax); + let to_this_param = to_this_param.and_then(|it| ctx.sema.to_def(&it)); + let syntax = fix_param_usages(ctx, to_this_param, params, syntax); update_external_control_flow(handler, &syntax); syntax } @@ -2009,30 +2045,46 @@ fn rewrite_body_segment( /// change all usages to account for added `&`/`&mut` for some params fn fix_param_usages( ctx: &AssistContext<'_>, + to_this_param: Option, params: &[Param<'_>], syntax: &SyntaxNode, ) -> SyntaxNode { let mut usages_for_param: Vec<(&Param<'_>, Vec)> = Vec::new(); + let mut usages_for_self_param: Vec = Vec::new(); let tm = TreeMutator::new(syntax); + let reference_filter = |reference: &FileReference| { + syntax + .text_range() + .contains_range(reference.range) + .then_some(()) + .and_then(|_| path_element_of_reference(syntax, reference)) + .map(|expr| tm.make_mut(&expr)) + }; + if let Some(self_param) = to_this_param { + usages_for_self_param = LocalUsages::find_local_usages(ctx, self_param) + .iter() + .filter_map(reference_filter) + .collect(); + } for param in params { if !param.kind().is_ref() { continue; } let usages = LocalUsages::find_local_usages(ctx, param.var); - let usages = usages - .iter() - .filter(|reference| syntax.text_range().contains_range(reference.range)) - .filter_map(|reference| path_element_of_reference(syntax, reference)) - .map(|expr| tm.make_mut(&expr)); + let usages = usages.iter().filter_map(reference_filter); usages_for_param.push((param, usages.unique().collect())); } let res = tm.make_syntax_mut(syntax); + for self_usage in usages_for_self_param { + let this_expr = make::expr_path(make::ext::ident_path("this")).clone_for_update(); + ted::replace(self_usage.syntax(), this_expr.syntax()); + } for (param, usages) in usages_for_param { for usage in usages { match usage.syntax().ancestors().skip(1).find_map(ast::Expr::cast) { @@ -2939,6 +2991,35 @@ fn $0fun_name(&mut self) { ); } + #[test] + fn method_in_trait() { + check_assist( + extract_function, + r#" +trait Foo { + fn f(&self) -> i32; + + fn foo(&self) -> i32 { + $0self.f()+self.f()$0 + } +} +"#, + r#" +trait Foo { + fn f(&self) -> i32; + + fn foo(&self) -> i32 { + fun_name(self) + } +} + +fn $0fun_name(this: &impl Foo) -> i32 { + this.f()+this.f() +} +"#, + ); + } + #[test] fn variable_defined_inside_and_used_after_no_ret() { check_assist( diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_struct_from_enum_variant.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_struct_from_enum_variant.rs index 4c46a51bef58..3bbf9a0ad3a2 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_struct_from_enum_variant.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_struct_from_enum_variant.rs @@ -6,7 +6,7 @@ FxHashSet, RootDatabase, defs::Definition, helpers::mod_path_to_ast, - imports::insert_use::{ImportScope, InsertUseConfig, insert_use}, + imports::insert_use::{ImportScope, InsertUseConfig, insert_use_with_editor}, path_transform::PathTransform, search::FileReference, }; @@ -16,12 +16,14 @@ SyntaxKind::*, SyntaxNode, T, ast::{ - self, AstNode, HasAttrs, HasGenericParams, HasName, HasVisibility, edit::AstNodeEdit, make, + self, AstNode, HasAttrs, HasGenericParams, HasName, HasVisibility, edit::AstNodeEdit, + syntax_factory::SyntaxFactory, }, - match_ast, ted, + match_ast, + syntax_editor::{Position, SyntaxEditor}, }; -use crate::{AssistContext, AssistId, Assists, assist_context::SourceChangeBuilder}; +use crate::{AssistContext, AssistId, Assists}; // Assist: extract_struct_from_enum_variant // @@ -58,6 +60,8 @@ pub(crate) fn extract_struct_from_enum_variant( "Extract struct from enum variant", target, |builder| { + let make = SyntaxFactory::with_mappings(); + let mut editor = builder.make_editor(variant.syntax()); let edition = enum_hir.krate(ctx.db()).edition(ctx.db()); let variant_hir_name = variant_hir.name(ctx.db()); let enum_module_def = ModuleDef::from(enum_hir); @@ -73,40 +77,56 @@ pub(crate) fn extract_struct_from_enum_variant( def_file_references = Some(references); continue; } - builder.edit_file(file_id.file_id(ctx.db())); let processed = process_references( ctx, - builder, &mut visited_modules_set, &enum_module_def, &variant_hir_name, references, ); + if processed.is_empty() { + continue; + } + let mut file_editor = builder.make_editor(processed[0].0.syntax()); processed.into_iter().for_each(|(path, node, import)| { - apply_references(ctx.config.insert_use, path, node, import, edition) + apply_references( + ctx.config.insert_use, + path, + node, + import, + edition, + &mut file_editor, + &make, + ) }); + file_editor.add_mappings(make.take()); + builder.add_file_edits(file_id.file_id(ctx.db()), file_editor); } - builder.edit_file(ctx.vfs_file_id()); - let variant = builder.make_mut(variant.clone()); if let Some(references) = def_file_references { let processed = process_references( ctx, - builder, &mut visited_modules_set, &enum_module_def, &variant_hir_name, references, ); processed.into_iter().for_each(|(path, node, import)| { - apply_references(ctx.config.insert_use, path, node, import, edition) + apply_references( + ctx.config.insert_use, + path, + node, + import, + edition, + &mut editor, + &make, + ) }); } - let generic_params = enum_ast - .generic_param_list() - .and_then(|known_generics| extract_generic_params(&known_generics, &field_list)); - let generics = generic_params.as_ref().map(|generics| generics.clone_for_update()); + let generic_params = enum_ast.generic_param_list().and_then(|known_generics| { + extract_generic_params(&make, &known_generics, &field_list) + }); // resolve GenericArg in field_list to actual type let field_list = if let Some((target_scope, source_scope)) = @@ -124,25 +144,45 @@ pub(crate) fn extract_struct_from_enum_variant( } } } else { - field_list.clone_for_update() + field_list.clone() }; - let def = - create_struct_def(variant_name.clone(), &variant, &field_list, generics, &enum_ast); + let (comments_for_struct, comments_to_delete) = + collect_variant_comments(&make, variant.syntax()); + for element in &comments_to_delete { + editor.delete(element.clone()); + } + + let def = create_struct_def( + &make, + variant_name.clone(), + &field_list, + generic_params.clone(), + &enum_ast, + ); let enum_ast = variant.parent_enum(); let indent = enum_ast.indent_level(); let def = def.indent(indent); - ted::insert_all( - ted::Position::before(enum_ast.syntax()), - vec![ - def.syntax().clone().into(), - make::tokens::whitespace(&format!("\n\n{indent}")).into(), - ], + let mut insert_items: Vec = Vec::new(); + for attr in enum_ast.attrs() { + insert_items.push(attr.syntax().clone().into()); + insert_items.push(make.whitespace("\n").into()); + } + insert_items.extend(comments_for_struct); + insert_items.push(def.syntax().clone().into()); + insert_items.push(make.whitespace(&format!("\n\n{indent}")).into()); + editor.insert_all_with_whitespace( + Position::before(enum_ast.syntax()), + insert_items, + &make, ); - update_variant(&variant, generic_params.map(|g| g.clone_for_update())); + update_variant(&make, &mut editor, &variant, generic_params); + + editor.add_mappings(make.finish_with_mappings()); + builder.add_file_edits(ctx.vfs_file_id(), editor); }, ) } @@ -184,6 +224,7 @@ fn existing_definition(db: &RootDatabase, variant_name: &ast::Name, variant: &En } fn extract_generic_params( + make: &SyntaxFactory, known_generics: &ast::GenericParamList, field_list: &Either, ) -> Option { @@ -201,7 +242,7 @@ fn extract_generic_params( }; let generics = generics.into_iter().filter_map(|(param, tag)| tag.then_some(param)); - tagged_one.then(|| make::generic_param_list(generics)) + tagged_one.then(|| make.generic_param_list(generics)) } fn tag_generics_in_variant(ty: &ast::Type, generics: &mut [(ast::GenericParam, bool)]) -> bool { @@ -250,82 +291,74 @@ fn tag_generics_in_variant(ty: &ast::Type, generics: &mut [(ast::GenericParam, b } fn create_struct_def( + make: &SyntaxFactory, name: ast::Name, - variant: &ast::Variant, field_list: &Either, generics: Option, enum_: &ast::Enum, ) -> ast::Struct { let enum_vis = enum_.visibility(); - let insert_vis = |node: &'_ SyntaxNode, vis: &'_ SyntaxNode| { - let vis = vis.clone_for_update(); - ted::insert(ted::Position::before(node), vis); - }; - // for fields without any existing visibility, use visibility of enum let field_list: ast::FieldList = match field_list { Either::Left(field_list) => { if let Some(vis) = &enum_vis { - field_list - .fields() - .filter(|field| field.visibility().is_none()) - .filter_map(|field| field.name()) - .for_each(|it| insert_vis(it.syntax(), vis.syntax())); + let new_fields = field_list.fields().map(|field| { + if field.visibility().is_none() + && let Some(name) = field.name() + && let Some(ty) = field.ty() + { + make.record_field(Some(vis.clone()), name, ty) + } else { + field + } + }); + make.record_field_list(new_fields).into() + } else { + field_list.clone().into() } - - field_list.clone().into() } Either::Right(field_list) => { if let Some(vis) = &enum_vis { - field_list - .fields() - .filter(|field| field.visibility().is_none()) - .filter_map(|field| field.ty()) - .for_each(|it| insert_vis(it.syntax(), vis.syntax())); + let new_fields = field_list.fields().map(|field| { + if field.visibility().is_none() + && let Some(ty) = field.ty() + { + make.tuple_field(Some(vis.clone()), ty) + } else { + field + } + }); + make.tuple_field_list(new_fields).into() + } else { + field_list.clone().into() } - - field_list.clone().into() } }; - let strukt = make::struct_(enum_vis, name, generics, field_list).clone_for_update(); - - // take comments from variant - ted::insert_all( - ted::Position::first_child_of(strukt.syntax()), - take_all_comments(variant.syntax()), - ); - - // copy attributes from enum - ted::insert_all( - ted::Position::first_child_of(strukt.syntax()), - enum_ - .attrs() - .flat_map(|it| { - vec![it.syntax().clone_for_update().into(), make::tokens::single_newline().into()] - }) - .collect(), - ); - - strukt + make.struct_(enum_vis, name, generics, field_list) } -fn update_variant(variant: &ast::Variant, generics: Option) -> Option<()> { +fn update_variant( + make: &SyntaxFactory, + editor: &mut SyntaxEditor, + variant: &ast::Variant, + generics: Option, +) -> Option<()> { let name = variant.name()?; let generic_args = generics .filter(|generics| generics.generic_params().count() > 0) .map(|generics| generics.to_generic_args()); // FIXME: replace with a `ast::make` constructor let ty = match generic_args { - Some(generic_args) => make::ty(&format!("{name}{generic_args}")), - None => make::ty(&name.text()), + Some(generic_args) => make.ty(&format!("{name}{generic_args}")), + None => make.ty(&name.text()), }; // change from a record to a tuple field list - let tuple_field = make::tuple_field(None, ty); - let field_list = make::tuple_field_list(iter::once(tuple_field)).clone_for_update(); - ted::replace(variant.field_list()?.syntax(), field_list.syntax()); + let tuple_field = make.tuple_field(None, ty); + let field_list = make.tuple_field_list(iter::once(tuple_field)); + editor.replace(variant.field_list()?.syntax(), field_list.syntax()); // remove any ws after the name if let Some(ws) = name @@ -333,35 +366,39 @@ fn update_variant(variant: &ast::Variant, generics: Option Vec { - let mut remove_next_ws = false; - node.children_with_tokens() - .filter_map(move |child| match child.kind() { +fn collect_variant_comments( + make: &SyntaxFactory, + node: &SyntaxNode, +) -> (Vec, Vec) { + let mut to_insert: Vec = Vec::new(); + let mut to_delete: Vec = Vec::new(); + let mut after_comment = false; + + for child in node.children_with_tokens() { + match child.kind() { COMMENT => { - remove_next_ws = true; - child.detach(); - Some(child) + after_comment = true; + to_insert.push(child.clone()); + to_delete.push(child); } - WHITESPACE if remove_next_ws => { - remove_next_ws = false; - child.detach(); - Some(make::tokens::single_newline().into()) + WHITESPACE if after_comment => { + after_comment = false; + to_insert.push(make.whitespace("\n").into()); + to_delete.push(child); } _ => { - remove_next_ws = false; - None + after_comment = false; } - }) - .collect() + } + } + + (to_insert, to_delete) } fn apply_references( @@ -370,20 +407,27 @@ fn apply_references( node: SyntaxNode, import: Option<(ImportScope, hir::ModPath)>, edition: Edition, + editor: &mut SyntaxEditor, + make: &SyntaxFactory, ) { if let Some((scope, path)) = import { - insert_use(&scope, mod_path_to_ast(&path, edition), &insert_use_cfg); + insert_use_with_editor( + &scope, + mod_path_to_ast(&path, edition), + &insert_use_cfg, + editor, + make, + ); } // deep clone to prevent cycle - let path = make::path_from_segments(iter::once(segment.clone_subtree()), false); - ted::insert_raw(ted::Position::before(segment.syntax()), path.clone_for_update().syntax()); - ted::insert_raw(ted::Position::before(segment.syntax()), make::token(T!['('])); - ted::insert_raw(ted::Position::after(&node), make::token(T![')'])); + let path = make.path_from_segments(iter::once(segment.clone()), false); + editor.insert(Position::before(segment.syntax()), make.token(T!['('])); + editor.insert(Position::before(segment.syntax()), path.syntax()); + editor.insert(Position::after(&node), make.token(T![')'])); } fn process_references( ctx: &AssistContext<'_>, - builder: &mut SourceChangeBuilder, visited_modules: &mut FxHashSet, enum_module_def: &ModuleDef, variant_hir_name: &Name, @@ -394,8 +438,6 @@ fn process_references( refs.into_iter() .flat_map(|reference| { let (segment, scope_node, module) = reference_to_node(&ctx.sema, reference)?; - let segment = builder.make_mut(segment); - let scope_node = builder.make_syntax_mut(scope_node); if !visited_modules.contains(&module) { let cfg = ctx.config.find_path_config(ctx.sema.is_nightly(module.krate(ctx.sema.db))); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_variable.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_variable.rs index e5ce02cf5357..1556339d8df4 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_variable.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/extract_variable.rs @@ -283,13 +283,17 @@ fn peel_parens(mut expr: ast::Expr) -> ast::Expr { /// Check whether the node is a valid expression which can be extracted to a variable. /// In general that's true for any expression, but in some cases that would produce invalid code. fn valid_target_expr(ctx: &AssistContext<'_>) -> impl Fn(SyntaxNode) -> Option { - |node| match node.kind() { + let selection = ctx.selection_trimmed(); + move |node| match node.kind() { SyntaxKind::LOOP_EXPR | SyntaxKind::LET_EXPR => None, SyntaxKind::BREAK_EXPR => ast::BreakExpr::cast(node).and_then(|e| e.expr()), SyntaxKind::RETURN_EXPR => ast::ReturnExpr::cast(node).and_then(|e| e.expr()), SyntaxKind::BLOCK_EXPR => { ast::BlockExpr::cast(node).filter(|it| it.is_standalone()).map(ast::Expr::from) } + SyntaxKind::ARG_LIST => ast::ArgList::cast(node)? + .args() + .find(|expr| crate::utils::is_selected(expr, selection, false)), SyntaxKind::PATH_EXPR => { let path_expr = ast::PathExpr::cast(node)?; let path_resolution = ctx.sema.resolve_path(&path_expr.path()?)?; @@ -1285,6 +1289,33 @@ fn main() { ); } + #[test] + fn extract_var_in_arglist_with_comma() { + check_assist_by_label( + extract_variable, + r#" +fn main() { + let x = 2; + foo( + x + x, + $0x - x,$0 + ) +} +"#, + r#" +fn main() { + let x = 2; + let $0var_name = x - x; + foo( + x + x, + var_name, + ) +} +"#, + "Extract into variable", + ); + } + #[test] fn extract_var_path_simple() { check_assist_by_label( diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/flip_binexpr.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/flip_binexpr.rs index 8f2306e9037e..922a61bf3a85 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/flip_binexpr.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/flip_binexpr.rs @@ -142,11 +142,11 @@ pub(crate) fn flip_range_expr(acc: &mut Assists, ctx: &AssistContext<'_>) -> Opt } (Some(start), None) => { edit.delete(start.syntax()); - edit.insert(Position::after(&op), start.syntax().clone_for_update()); + edit.insert(Position::after(&op), start.syntax()); } (None, Some(end)) => { edit.delete(end.syntax()); - edit.insert(Position::before(&op), end.syntax().clone_for_update()); + edit.insert(Position::before(&op), end.syntax()); } (None, None) => (), } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_blanket_trait_impl.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_blanket_trait_impl.rs index e022a27e519a..fccc04770e89 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_blanket_trait_impl.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_blanket_trait_impl.rs @@ -279,7 +279,7 @@ fn todo_fn(f: &ast::Fn, config: &AssistConfig) -> ast::Fn { } fn cfg_attrs(node: &impl HasAttrs) -> impl Iterator { - node.attrs().filter(|attr| attr.as_simple_call().is_some_and(|(name, _arg)| name == "cfg")) + node.attrs().filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))) } #[cfg(test)] diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_delegate_trait.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_delegate_trait.rs index f703e4dc4ab2..abe447d9d9b7 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_delegate_trait.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_delegate_trait.rs @@ -363,9 +363,9 @@ fn generate_impl( ast_strukt, &old_impl, &transform_args, - trait_args.clone_subtree(), + trait_args.clone(), ) { - *trait_args = new_args.clone_subtree(); + *trait_args = new_args.clone(); Some(new_args) } else { None @@ -563,7 +563,7 @@ fn finalize_delegate( return Some(delegate.clone()); } - let mut editor = SyntaxEditor::new(delegate.syntax().clone_subtree()); + let (mut editor, delegate) = SyntaxEditor::with_ast_node(delegate); // 1. Replace assoc_item_list if we have new items if let Some(items) = assoc_items @@ -577,7 +577,7 @@ fn finalize_delegate( // 2. Remove useless where clauses if remove_where_clauses { - remove_useless_where_clauses(&mut editor, delegate); + remove_useless_where_clauses(&mut editor, &delegate); } ast::Impl::cast(editor.finish().new_root().clone()) @@ -703,7 +703,7 @@ fn resolve_name_conflicts( } } p @ ast::GenericParam::LifetimeParam(_) => { - new_params.push(p.clone_for_update()); + new_params.push(p); } ast::GenericParam::TypeParam(t) => { let type_bounds = t.type_bound_list(); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_derive.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_derive.rs index 3ef68f06e499..7aeb5e339696 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_derive.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_derive.rs @@ -68,9 +68,11 @@ pub(crate) fn generate_derive(acc: &mut Assists, ctx: &AssistContext<'_>) -> Opt ], ); - let delimiter = derive - .meta() - .expect("make::attr_outer was expected to have Meta") + let meta = derive.meta().expect("make::attr_outer was expected to have Meta"); + let ast::Meta::TokenTreeMeta(meta) = meta else { + unreachable!("make::attr_outer was passed a token tree meta"); + }; + let delimiter = meta .token_tree() .expect("failed to get token tree out of Meta") .r_paren_token() diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_getter_or_setter.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_getter_or_setter.rs index 62ffd3d9656b..4cd018d02d02 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_getter_or_setter.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_getter_or_setter.rs @@ -429,7 +429,7 @@ fn build_source_change( generate_getter_from_info(ctx, &assist_info, record_field_info, &syntax_factory) } }; - let new_fn = method.clone_for_update(); + let new_fn = method; let new_fn = new_fn.indent(1.into()); new_fn.into() }) diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_impl.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_impl.rs index 2d1235792dcf..af123eeaa0ce 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_impl.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_impl.rs @@ -8,8 +8,8 @@ use crate::{ AssistContext, AssistId, Assists, utils::{ - self, DefaultMethods, IgnoreAssocItems, generate_impl_with_factory, - generate_trait_impl_intransitive, + self, DefaultMethods, IgnoreAssocItems, add_trait_assoc_items_to_impl, + generate_impl_with_factory, generate_trait_impl_intransitive, }, }; @@ -212,7 +212,8 @@ pub(crate) fn generate_impl_trait(acc: &mut Assists, ctx: &AssistContext<'_>) -> make_impl_(None) } else { let impl_ = make_impl_(None); - let assoc_items = utils::add_trait_assoc_items_to_impl( + let assoc_items = add_trait_assoc_items_to_impl( + &make, &ctx.sema, ctx.config, &missing_items, diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_mut_trait_impl.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_mut_trait_impl.rs index 3a62a8853e3a..31e49c8ce48e 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_mut_trait_impl.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_mut_trait_impl.rs @@ -67,8 +67,7 @@ pub(crate) fn generate_mut_trait_impl(acc: &mut Assists, ctx: &AssistContext<'_> format!("Generate `{trait_new}` impl from this `{trait_name}` trait"), target, |edit| { - let impl_clone = impl_def.reset_indent().clone_subtree(); - let mut editor = SyntaxEditor::new(impl_clone.syntax().clone()); + let (mut editor, impl_clone) = SyntaxEditor::with_ast_node(&impl_def.reset_indent()); let factory = SyntaxFactory::without_mappings(); apply_generate_mut_impl(&mut editor, &factory, &impl_clone, trait_new); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_single_field_struct_from.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_single_field_struct_from.rs index d3022ceda379..7746cdc068a1 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_single_field_struct_from.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_single_field_struct_from.rs @@ -1,14 +1,16 @@ -use ast::make; use hir::next_solver::{DbInterner, TypingMode}; use hir::{HasCrate, ModuleDef, Semantics}; use ide_db::{ RootDatabase, famous_defs::FamousDefs, helpers::mod_path_to_ast, imports::import_assets::item_for_path_search, use_trivial_constructor::use_trivial_constructor, }; -use syntax::syntax_editor::{Element, Position}; +use syntax::syntax_editor::{Position, SyntaxEditor}; use syntax::{ TokenText, - ast::{self, AstNode, HasAttrs, HasGenericParams, HasName, edit::AstNodeEdit}, + ast::{ + self, AstNode, HasAttrs, HasGenericParams, HasName, edit::AstNodeEdit, + syntax_factory::SyntaxFactory, + }, }; use crate::{ @@ -78,47 +80,51 @@ pub(crate) fn generate_single_field_struct_from( "Generate single field `From`", strukt.syntax().text_range(), |builder| { + let make = SyntaxFactory::with_mappings(); + let mut editor = builder.make_editor(strukt.syntax()); + let indent = strukt.indent_level(); let ty_where_clause = strukt.where_clause(); let type_gen_params = strukt.generic_param_list(); let type_gen_args = type_gen_params.as_ref().map(|params| params.to_generic_args()); - let trait_gen_args = Some(make::generic_arg_list([ast::GenericArg::TypeArg( - make::type_arg(main_field_ty.clone()), - )])); + let trait_gen_args = Some(make.generic_arg_list( + [ast::GenericArg::TypeArg(make.type_arg(main_field_ty.clone()))], + false, + )); - let ty = make::ty(&strukt_name.text()); + let ty = make.ty(&strukt_name.text()); let constructor = - make_adt_constructor(names.as_deref(), constructors, &main_field_name); - let body = make::block_expr([], Some(constructor)); + make_adt_constructor(names.as_deref(), constructors, &main_field_name, &make); + let body = make.block_expr([], Some(constructor)); - let fn_ = make::fn_( - None, - None, - make::name("from"), - None, - None, - make::param_list( + let fn_ = make + .fn_( + [], None, - [make::param( - make::path_pat(make::path_from_text(&main_field_name)), - main_field_ty, - )], - ), - body, - Some(make::ret_type(make::ty("Self"))), - false, - false, - false, - false, - ) - .indent(1.into()); + make.name("from"), + None, + None, + make.param_list( + None, + [make.param( + make.path_pat(make.path_from_text(&main_field_name)), + main_field_ty, + )], + ), + body, + Some(make.ret_type(make.ty("Self"))), + false, + false, + false, + false, + ) + .indent_with_mapping(1.into(), &make); - let cfg_attrs = strukt - .attrs() - .filter(|attr| attr.as_simple_call().is_some_and(|(name, _arg)| name == "cfg")); + let cfg_attrs = + strukt.attrs().filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))); - let impl_ = make::impl_trait( + let impl_ = make.impl_trait( cfg_attrs, false, None, @@ -126,28 +132,31 @@ pub(crate) fn generate_single_field_struct_from( type_gen_params, type_gen_args, false, - make::ty("From"), + make.ty("From"), ty.clone(), None, ty_where_clause.map(|wc| wc.reset_indent()), None, - ) - .clone_for_update(); + ); - impl_.get_or_create_assoc_item_list().add_item(fn_.into()); - let impl_ = impl_.indent(indent); + let (mut impl_editor, impl_root) = SyntaxEditor::with_ast_node(&impl_); + let assoc_list = + impl_root.get_or_create_assoc_item_list_with_editor(&mut impl_editor, &make); + assoc_list.add_items(&mut impl_editor, vec![fn_.into()]); + let impl_ = ast::Impl::cast(impl_editor.finish().new_root().clone()) + .unwrap() + .indent_with_mapping(indent, &make); - let mut edit = builder.make_editor(strukt.syntax()); - - edit.insert_all( + editor.insert_all( Position::after(strukt.syntax()), vec![ - make::tokens::whitespace(&format!("\n\n{indent}")).syntax_element(), - impl_.syntax().syntax_element(), + make.whitespace(&format!("\n\n{indent}")).into(), + impl_.syntax().clone().into(), ], ); - builder.add_file_edits(ctx.vfs_file_id(), edit); + editor.add_mappings(make.finish_with_mappings()); + builder.add_file_edits(ctx.vfs_file_id(), editor); }, ) } @@ -156,19 +165,18 @@ fn make_adt_constructor( names: Option<&[ast::Name]>, constructors: Vec>, main_field_name: &TokenText<'_>, + make: &SyntaxFactory, ) -> ast::Expr { if let Some(names) = names { - let fields = make::record_expr_field_list(names.iter().zip(constructors).map( - |(name, initializer)| { - make::record_expr_field(make::name_ref(&name.text()), initializer) - }, + let fields = make.record_expr_field_list(names.iter().zip(constructors).map( + |(name, initializer)| make.record_expr_field(make.name_ref(&name.text()), initializer), )); - make::record_expr(make::path_from_text("Self"), fields).into() + make.record_expr(make.path_from_text("Self"), fields).into() } else { - let arg_list = make::arg_list(constructors.into_iter().map(|expr| { - expr.unwrap_or_else(|| make::expr_path(make::path_from_text(main_field_name))) + let arg_list = make.arg_list(constructors.into_iter().map(|expr| { + expr.unwrap_or_else(|| make.expr_path(make.path_from_text(main_field_name))) })); - make::expr_call(make::expr_path(make::path_from_text("Self")), arg_list).into() + make.expr_call(make.expr_path(make.path_from_text("Self")), arg_list).into() } } @@ -177,6 +185,7 @@ fn make_constructors( module: hir::Module, types: &[ast::Type], ) -> Vec> { + let make = SyntaxFactory::without_mappings(); let (db, sema) = (ctx.db(), &ctx.sema); let cfg = ctx.config.find_path_config(ctx.sema.is_nightly(module.krate(ctx.sema.db))); types @@ -184,7 +193,7 @@ fn make_constructors( .map(|ty| { let ty = sema.resolve_type(ty)?; if ty.is_unit() { - return Some(make::expr_tuple([]).into()); + return Some(make.expr_tuple([]).into()); } let item_in_ns = ModuleDef::Adt(ty.as_adt()?).into(); let edition = module.krate(db).edition(db); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_trait_from_impl.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_trait_from_impl.rs index 1286abe3565e..2d3d05849b0b 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_trait_from_impl.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/generate_trait_from_impl.rs @@ -4,6 +4,7 @@ AstNode, AstToken, SyntaxKind, T, ast::{ self, HasDocComments, HasGenericParams, HasName, HasVisibility, edit::AstNodeEdit, make, + syntax_factory::SyntaxFactory, }, syntax_editor::{Position, SyntaxEditor}, }; @@ -98,8 +99,8 @@ pub(crate) fn generate_trait_from_impl(acc: &mut Assists, ctx: &AssistContext<'_ impl_ast.syntax().text_range(), |builder| { let trait_items: ast::AssocItemList = { - let trait_items = impl_assoc_items.clone_subtree(); - let mut trait_items_editor = SyntaxEditor::new(trait_items.syntax().clone()); + let (mut trait_items_editor, trait_items) = + SyntaxEditor::with_ast_node(&impl_assoc_items); trait_items.assoc_items().for_each(|item| { strip_body(&mut trait_items_editor, &item); @@ -107,17 +108,18 @@ pub(crate) fn generate_trait_from_impl(acc: &mut Assists, ctx: &AssistContext<'_ }); ast::AssocItemList::cast(trait_items_editor.finish().new_root().clone()).unwrap() }; - let trait_ast = make::trait_( + + let factory = SyntaxFactory::with_mappings(); + let trait_ast = factory.trait_( false, &trait_name(&impl_assoc_items).text(), impl_ast.generic_param_list(), impl_ast.where_clause(), trait_items, - ) - .clone_for_update(); + ); let trait_name = trait_ast.name().expect("new trait should have a name"); - let trait_name_ref = make::name_ref(&trait_name.to_string()).clone_for_update(); + let trait_name_ref = factory.name_ref(&trait_name.to_string()); // Change `impl Foo` to `impl NewTrait for Foo` let mut elements = vec![ @@ -128,7 +130,7 @@ pub(crate) fn generate_trait_from_impl(acc: &mut Assists, ctx: &AssistContext<'_ ]; if let Some(params) = impl_ast.generic_param_list() { - let gen_args = ¶ms.to_generic_args().clone_for_update(); + let gen_args = ¶ms.to_generic_args(); elements.insert(1, gen_args.syntax().clone().into()); } @@ -156,6 +158,7 @@ pub(crate) fn generate_trait_from_impl(acc: &mut Assists, ctx: &AssistContext<'_ editor.add_annotation(trait_name_ref.syntax(), placeholder); } + editor.add_mappings(factory.finish_with_mappings()); builder.add_file_edits(ctx.vfs_file_id(), editor); }, ); diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/inline_type_alias.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/inline_type_alias.rs index f3ebe6107819..4b60f0ac1e3c 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/inline_type_alias.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/inline_type_alias.rs @@ -170,7 +170,7 @@ fn replace_generic(&self, concrete_type: &ast::Type) -> SyntaxNode { Replacement::Generic { lifetime_map, const_and_type_map } => { create_replacement(lifetime_map, const_and_type_map, concrete_type) } - Replacement::Plain => concrete_type.syntax().clone_subtree().clone_for_update(), + Replacement::Plain => concrete_type.syntax().clone(), } } } @@ -312,8 +312,7 @@ fn create_replacement( const_and_type_map: &ConstAndTypeMap, concrete_type: &ast::Type, ) -> SyntaxNode { - let updated_concrete_type = concrete_type.syntax().clone_subtree(); - let mut editor = SyntaxEditor::new(updated_concrete_type.clone()); + let (mut editor, updated_concrete_type) = SyntaxEditor::new(concrete_type.syntax().clone()); let mut replacements: Vec<(SyntaxNode, SyntaxNode)> = Vec::new(); let mut removals: Vec> = Vec::new(); @@ -361,7 +360,7 @@ fn create_replacement( continue; } - replacements.push((syntax.clone(), new_lifetime.syntax().clone_for_update())); + replacements.push((syntax.clone(), new_lifetime.syntax().clone())); } } else if let Some(name_ref) = ast::NameRef::cast(syntax.clone()) { let Some(replacement_syntax) = const_and_type_map.0.get(&name_ref.to_string()) else { @@ -449,15 +448,12 @@ fn replacement_key(&self) -> Option { } fn replacement_value(&self) -> Option { - Some( - match self { - ConstOrTypeGeneric::ConstArg(ca) => ca.expr()?.syntax().clone(), - ConstOrTypeGeneric::TypeArg(ta) => ta.syntax().clone(), - ConstOrTypeGeneric::ConstParam(cp) => cp.default_val()?.syntax().clone(), - ConstOrTypeGeneric::TypeParam(tp) => tp.default_type()?.syntax().clone(), - } - .clone_for_update(), - ) + Some(match self { + ConstOrTypeGeneric::ConstArg(ca) => ca.expr()?.syntax().clone(), + ConstOrTypeGeneric::TypeArg(ta) => ta.syntax().clone(), + ConstOrTypeGeneric::ConstParam(cp) => cp.default_val()?.syntax().clone(), + ConstOrTypeGeneric::TypeParam(tp) => tp.default_type()?.syntax().clone(), + }) } } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/introduce_named_lifetime.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/introduce_named_lifetime.rs index 854e9561d29a..5e8ea7daff90 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/introduce_named_lifetime.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/introduce_named_lifetime.rs @@ -97,8 +97,7 @@ fn generate_fn_def_assist( }; acc.add(AssistId::refactor(ASSIST_NAME), ASSIST_LABEL, lifetime_loc, |edit| { - let root = fn_def.syntax().ancestors().last().unwrap().clone(); - let mut editor = SyntaxEditor::new(root); + let mut editor = edit.make_editor(fn_def.syntax()); let factory = SyntaxFactory::with_mappings(); if let Some(generic_list) = fn_def.generic_param_list() { @@ -167,8 +166,7 @@ fn generate_impl_def_assist( let new_lifetime_name = generate_unique_lifetime_param_name(impl_def.generic_param_list())?; acc.add(AssistId::refactor(ASSIST_NAME), ASSIST_LABEL, lifetime_loc, |edit| { - let root = impl_def.syntax().ancestors().last().unwrap().clone(); - let mut editor = SyntaxEditor::new(root); + let mut editor = edit.make_editor(impl_def.syntax()); let factory = SyntaxFactory::without_mappings(); if let Some(generic_list) = impl_def.generic_param_list() { diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/pull_assignment_up.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/pull_assignment_up.rs index 812ebf6c6e28..74ed2e14fa23 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/pull_assignment_up.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/pull_assignment_up.rs @@ -75,7 +75,8 @@ pub(crate) fn pull_assignment_up(acc: &mut Assists, ctx: &AssistContext<'_>) -> } let target = tgt.syntax().text_range(); - let edit_tgt = tgt.syntax().clone_subtree(); + let (mut editor, edit_tgt) = SyntaxEditor::new(tgt.syntax().clone()); + let assignments: Vec<_> = collector .assignments .into_iter() @@ -93,7 +94,6 @@ pub(crate) fn pull_assignment_up(acc: &mut Assists, ctx: &AssistContext<'_>) -> }) .collect(); - let mut editor = SyntaxEditor::new(edit_tgt); for (stmt, rhs) in assignments { let mut stmt = stmt.syntax().clone(); if let Some(parent) = stmt.parent() diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/remove_dbg.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/remove_dbg.rs index 08779a3ed1f7..f4c354b8a21d 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/remove_dbg.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/remove_dbg.rs @@ -50,7 +50,7 @@ pub(crate) fn remove_dbg(acc: &mut Assists, ctx: &AssistContext<'_>) -> Option<( let mut editor = builder.make_editor(ctx.source_file().syntax()); for (range, expr) in replacements { if let Some(expr) = expr { - editor.insert(Position::before(range[0].clone()), expr.syntax().clone_for_update()); + editor.insert(Position::before(range[0].clone()), expr.syntax()); } for node_or_token in range { editor.delete(node_or_token); @@ -163,7 +163,7 @@ fn compute_dbg_replacement( None => false, }; let expr = replace_nested_dbgs(expr.clone()); - let expr = if wrap { make::expr_paren(expr).into() } else { expr.clone_subtree() }; + let expr = if wrap { make::expr_paren(expr).into() } else { expr }; (vec![macro_call.syntax().clone().into()], Some(expr)) } // dbg!(expr0, expr1, ...) @@ -209,8 +209,7 @@ fn replace_nested_dbgs(expanded: ast::Expr) -> ast::Expr { return replaced; } - let expanded = expanded.clone_subtree(); - let mut editor = SyntaxEditor::new(expanded.syntax().clone()); + let (mut editor, expanded) = SyntaxEditor::with_ast_node(&expanded); // We need to collect to avoid mutation during traversal. let macro_exprs: Vec<_> = expanded.syntax().descendants().filter_map(ast::MacroExpr::cast).collect(); @@ -222,7 +221,7 @@ fn replace_nested_dbgs(expanded: ast::Expr) -> ast::Expr { }; if let Some(expr) = expr_opt { - editor.replace(mac.syntax(), expr.syntax().clone_for_update()); + editor.replace(mac.syntax(), expr.syntax()); } else { editor.delete(mac.syntax()); } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_derive_with_manual_impl.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_derive_with_manual_impl.rs index f54f7a02d2b3..5e595218f6b1 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_derive_with_manual_impl.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_derive_with_manual_impl.rs @@ -12,8 +12,8 @@ AssistConfig, AssistId, assist_context::{AssistContext, Assists}, utils::{ - DefaultMethods, IgnoreAssocItems, add_trait_assoc_items_to_impl_with_factory, - filter_assoc_items, gen_trait_fn_body, generate_trait_impl, + DefaultMethods, IgnoreAssocItems, add_trait_assoc_items_to_impl, filter_assoc_items, + gen_trait_fn_body, generate_trait_impl, generate_trait_impl_with_item, }, }; @@ -64,9 +64,10 @@ pub(crate) fn replace_derive_with_manual_impl( .filter_map(|attr| attr.path()) .collect::>(); - let adt = value.parent().and_then(ast::Adt::cast)?; - let attr = ast::Attr::cast(value)?; - let args = attr.token_tree()?; + let attr = ast::Meta::cast(value)?.parent_attr()?; + let adt = attr.syntax().parent().and_then(ast::Adt::cast)?; + let ast::Meta::TokenTreeMeta(meta) = attr.meta()? else { return None }; + let args = meta.token_tree()?; let current_module = ctx.sema.scope(adt.syntax())?.module(); let current_crate = current_module.krate(ctx.db()); @@ -127,7 +128,7 @@ fn add_assist( let label = format!("Convert to manual `impl {replace_trait_path} for {annotated_name}`"); acc.add(AssistId::refactor("replace_derive_with_manual_impl"), label, target, |builder| { - let make = SyntaxFactory::without_mappings(); + let make = SyntaxFactory::with_mappings(); let insert_after = Position::after(adt.syntax()); let impl_is_unsafe = trait_.map(|s| s.is_unsafe(ctx.db())).unwrap_or(false); let impl_def = impl_def_from_trait( @@ -141,7 +142,7 @@ fn add_assist( ); let mut editor = builder.make_editor(attr.syntax()); - update_attribute(&mut editor, old_derives, old_tree, old_trait_path, attr); + update_attribute(&make, &mut editor, old_derives, old_tree, old_trait_path, attr); let trait_path = make.ty_path(replace_trait_path.clone()).into(); @@ -177,6 +178,7 @@ fn add_assist( insert_after, vec![make.whitespace("\n\n").into(), impl_def.syntax().clone().into()], ); + editor.add_mappings(make.finish_with_mappings()); builder.add_file_edits(ctx.vfs_file_id(), editor); }) } @@ -207,10 +209,10 @@ fn impl_def_from_trait( return None; } let make = SyntaxFactory::without_mappings(); - let trait_ty = make.ty_path(trait_path.clone()).into(); - let impl_def = generate_trait_impl(&make, impl_is_unsafe, adt, trait_ty); + let trait_ty: ast::Type = make.ty_path(trait_path.clone()).into(); + let impl_def = generate_trait_impl(&make, impl_is_unsafe, adt, trait_ty.clone()); - let assoc_items = add_trait_assoc_items_to_impl_with_factory( + let assoc_items = add_trait_assoc_items_to_impl( &make, sema, config, @@ -219,14 +221,12 @@ fn impl_def_from_trait( &impl_def, &target_scope, ); - let assoc_item_list = if let Some((first, other)) = - assoc_items.split_first().map(|(first, other)| (first.clone_subtree(), other)) - { - let first_item = if let ast::AssocItem::Fn(ref func) = first - && let Some(body) = gen_trait_fn_body(func, trait_path, adt, None) + let assoc_item_list = if let Some((first, other)) = assoc_items.split_first() { + let first_item = if let ast::AssocItem::Fn(func) = first + && let Some(body) = gen_trait_fn_body(&make, func, trait_path, adt, None) && let Some(func_body) = func.body() { - let mut editor = SyntaxEditor::new(first.syntax().clone()); + let (mut editor, _) = SyntaxEditor::new(first.syntax().clone()); editor.replace(func_body.syntax(), body.syntax()); ast::AssocItem::cast(editor.finish().new_root().clone()) } else { @@ -239,21 +239,17 @@ fn impl_def_from_trait( make.assoc_item_list_empty() }; - let impl_def = impl_def.clone_subtree(); - let mut editor = SyntaxEditor::new(impl_def.syntax().clone()); - editor.replace(impl_def.assoc_item_list()?.syntax(), assoc_item_list.syntax()); - let impl_def = ast::Impl::cast(editor.finish().new_root().clone())?; - Some(impl_def) + Some(generate_trait_impl_with_item(&make, impl_is_unsafe, adt, trait_ty, assoc_item_list)) } fn update_attribute( + make: &SyntaxFactory, editor: &mut SyntaxEditor, old_derives: &[ast::Path], old_tree: &ast::TokenTree, old_trait_path: &ast::Path, attr: &ast::Attr, ) { - let make = SyntaxFactory::without_mappings(); let new_derives = old_derives .iter() .filter(|t| t.to_string() != old_trait_path.to_string()) diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_if_let_with_match.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_if_let_with_match.rs index 8ff30fce5b5d..ada2fd9b217a 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_if_let_with_match.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_if_let_with_match.rs @@ -13,7 +13,10 @@ use crate::{ AssistContext, AssistId, Assists, - utils::{does_pat_match_variant, does_pat_variant_nested_or_literal, unwrap_trivial_block}, + utils::{ + does_pat_match_variant, does_pat_variant_nested_or_literal, unwrap_trivial_block, + wrap_paren, + }, }; // Assist: replace_if_let_with_match @@ -289,6 +292,7 @@ pub(crate) fn replace_match_with_if_let(acc: &mut Assists, ctx: &AssistContext<' _ => make.expr_let(if_let_pat, scrutinee).into(), }; let condition = if let Some(guard) = guard { + let guard = wrap_paren(guard, &make, ast::prec::ExprPrecedence::LAnd); make.expr_bin(condition, ast::BinaryOp::LogicOp(ast::LogicOp::And), guard).into() } else { condition @@ -398,8 +402,7 @@ fn let_and_guard(cond: &ast::Expr) -> (Option, Option) } else if let ast::Expr::BinExpr(bin_expr) = cond && let Some(ast::Expr::LetExpr(let_expr)) = and_bin_expr_left(bin_expr).lhs() { - let new_expr = bin_expr.clone_subtree(); - let mut edit = SyntaxEditor::new(new_expr.syntax().clone()); + let (mut edit, new_expr) = SyntaxEditor::with_ast_node(bin_expr); let left_bin = and_bin_expr_left(&new_expr); if let Some(rhs) = left_bin.rhs() { @@ -2268,14 +2271,35 @@ fn main() { "#, r#" fn main() { - if let Some(n) = Some(0) && n % 2 == 0 && n != 6 { + if let Some(n) = Some(0) && (n % 2 == 0 && n != 6) { () } else { code() } } "#, - ) + ); + + check_assist( + replace_match_with_if_let, + r#" +fn main() { + match$0 Some(0) { + Some(n) if n % 2 == 0 || n == 7 => (), + _ => code(), + } +} +"#, + r#" +fn main() { + if let Some(n) = Some(0) && (n % 2 == 0 || n == 7) { + () + } else { + code() + } +} +"#, + ); } #[test] diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_qualified_name_with_use.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_qualified_name_with_use.rs index cdf20586ef15..fd090cc081fa 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_qualified_name_with_use.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/replace_qualified_name_with_use.rs @@ -111,8 +111,7 @@ fn target_path(ctx: &AssistContext<'_>, mut original_path: ast::Path) -> Option< } fn drop_generic_args(path: &ast::Path) -> ast::Path { - let path = path.clone_subtree(); - let mut editor = SyntaxEditor::new(path.syntax().clone()); + let (mut editor, path) = SyntaxEditor::with_ast_node(path); if let Some(segment) = path.segment() && let Some(generic_args) = segment.generic_arg_list() { diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/unwrap_block.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/unwrap_block.rs index e029d7884fd5..5593ca3eb88f 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/unwrap_block.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/unwrap_block.rs @@ -103,8 +103,7 @@ fn delete_else_before(container: SyntaxNode, edit: &mut SyntaxEditor) { fn wrap_let(assign: &ast::LetStmt, replacement: ast::BlockExpr) -> ast::BlockExpr { let try_wrap_assign = || { let initializer = assign.initializer()?.syntax().syntax_element(); - let replacement = replacement.clone_subtree(); - let assign = assign.clone_for_update(); + let (mut edit, replacement) = SyntaxEditor::with_ast_node(&replacement); let tail_expr = replacement.tail_expr()?; let before = assign.syntax().children_with_tokens().take_while(|it| *it != initializer).collect(); @@ -115,7 +114,6 @@ fn wrap_let(assign: &ast::LetStmt, replacement: ast::BlockExpr) -> ast::BlockExp .skip(1) .collect(); - let mut edit = SyntaxEditor::new(replacement.syntax().clone()); edit.insert_all(Position::before(tail_expr.syntax()), before); edit.insert_all(Position::after(tail_expr.syntax()), after); ast::BlockExpr::cast(edit.finish().new_root().clone()) diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/wrap_unwrap_cfg_attr.rs b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/wrap_unwrap_cfg_attr.rs index 36df4af31d5e..3b8988db7aae 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/handlers/wrap_unwrap_cfg_attr.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/handlers/wrap_unwrap_cfg_attr.rs @@ -19,7 +19,7 @@ // ``` // -> // ``` -// #[cfg_attr($0, derive(Debug))] +// #[cfg_attr(${0:cfg}, derive(Debug))] // struct S { // field: i32 // } @@ -147,12 +147,15 @@ pub(crate) fn wrap_unwrap_cfg_attr(acc: &mut Assists, ctx: &AssistContext<'_>) - } }?; match option { - WrapUnwrapOption::WrapAttr(attrs) => match &attrs[..] { - [attr] if attr.simple_name().as_deref() == Some("cfg_attr") => { - unwrap_cfg_attr(acc, attrs.into_iter().next().unwrap()) + WrapUnwrapOption::WrapAttr(attrs) => { + if let [attr] = &attrs[..] + && let Some(ast::Meta::CfgAttrMeta(meta)) = attr.meta() + { + unwrap_cfg_attr(acc, meta) + } else { + wrap_cfg_attrs(acc, ctx, attrs) } - _ => wrap_cfg_attrs(acc, ctx, attrs), - }, + } WrapUnwrapOption::WrapDerive { derive, attr } => wrap_derive(acc, ctx, attr, derive), } } @@ -164,7 +167,8 @@ fn wrap_derive( derive_element: TextRange, ) -> Option<()> { let range = attr.syntax().text_range(); - let token_tree = attr.token_tree()?; + let ast::Meta::TokenTreeMeta(meta) = attr.meta()? else { return None }; + let token_tree = meta.token_tree()?; let mut path_text = String::new(); let mut cfg_derive_tokens = Vec::new(); @@ -193,20 +197,15 @@ fn wrap_derive( let new_derive = make.attr_outer( make.meta_token_tree(make.ident_path("derive"), make.token_tree(T!['('], new_derive)), ); - let meta = make.meta_token_tree( - make.ident_path("cfg_attr"), - make.token_tree( - T!['('], - vec![ - NodeOrToken::Token(make.token(T![,])), - NodeOrToken::Token(make.whitespace(" ")), - NodeOrToken::Token(make.ident("derive")), - NodeOrToken::Node(make.token_tree(T!['('], cfg_derive_tokens)), - ], - ), + let meta = make.cfg_attr_meta( + make.cfg_flag("cfg"), + [make.meta_token_tree( + make.ident_path("derive"), + make.token_tree(T!['('], cfg_derive_tokens), + )], ); - let cfg_attr = make.attr_outer(meta); + let cfg_attr = make.attr_outer(meta.clone().into()); editor.replace_with_many( attr.syntax(), vec![ @@ -217,11 +216,10 @@ fn wrap_derive( ); if let Some(snippet_cap) = ctx.config.snippet_cap - && let Some(first_meta) = - cfg_attr.meta().and_then(|meta| meta.token_tree()).and_then(|tt| tt.l_paren_token()) + && let Some(cfg_predicate) = meta.cfg_predicate() { - let tabstop = edit.make_tabstop_after(snippet_cap); - editor.add_annotation(first_meta, tabstop); + let tabstop = edit.make_placeholder_snippet(snippet_cap); + editor.add_annotation(cfg_predicate.syntax(), tabstop); } editor.add_mappings(make.finish_with_mappings()); @@ -236,58 +234,29 @@ fn wrap_derive( ); Some(()) } + fn wrap_cfg_attrs(acc: &mut Assists, ctx: &AssistContext<'_>, attrs: Vec) -> Option<()> { let (first_attr, last_attr) = (attrs.first()?, attrs.last()?); let range = first_attr.syntax().text_range().cover(last_attr.syntax().text_range()); - let path_attrs = - attrs.iter().map(|attr| Some((attr.path()?, attr.clone()))).collect::>>()?; let handle_source_change = |edit: &mut SourceChangeBuilder| { let make = SyntaxFactory::with_mappings(); let mut editor = edit.make_editor(first_attr.syntax()); - let mut raw_tokens = vec![]; - for (path, attr) in path_attrs { - raw_tokens.extend([ - NodeOrToken::Token(make.token(T![,])), - NodeOrToken::Token(make.whitespace(" ")), - ]); - path.syntax().descendants_with_tokens().for_each(|it| { - if let NodeOrToken::Token(token) = it { - raw_tokens.push(NodeOrToken::Token(token)); - } - }); - if let Some(meta) = attr.meta() { - if let (Some(eq), Some(expr)) = (meta.eq_token(), meta.expr()) { - raw_tokens.push(NodeOrToken::Token(make.whitespace(" "))); - raw_tokens.push(NodeOrToken::Token(eq)); - raw_tokens.push(NodeOrToken::Token(make.whitespace(" "))); - - expr.syntax().descendants_with_tokens().for_each(|it| { - if let NodeOrToken::Token(token) = it { - raw_tokens.push(NodeOrToken::Token(token)); - } - }); - } else if let Some(tt) = meta.token_tree() { - raw_tokens.extend(tt.token_trees_and_tokens()); - } - } - } let meta = - make.meta_token_tree(make.ident_path("cfg_attr"), make.token_tree(T!['('], raw_tokens)); + make.cfg_attr_meta(make.cfg_flag("cfg"), attrs.iter().filter_map(|attr| attr.meta())); let cfg_attr = if first_attr.excl_token().is_some() { - make.attr_inner(meta) + make.attr_inner(meta.clone().into()) } else { - make.attr_outer(meta) + make.attr_outer(meta.clone().into()) }; let syntax_range = first_attr.syntax().clone().into()..=last_attr.syntax().clone().into(); editor.replace_all(syntax_range, vec![cfg_attr.syntax().clone().into()]); if let Some(snippet_cap) = ctx.config.snippet_cap - && let Some(first_meta) = - cfg_attr.meta().and_then(|meta| meta.token_tree()).and_then(|tt| tt.l_paren_token()) + && let Some(cfg_flag) = meta.cfg_predicate() { - let tabstop = edit.make_tabstop_after(snippet_cap); - editor.add_annotation(first_meta, tabstop); + let tabstop = edit.make_placeholder_snippet(snippet_cap); + editor.add_annotation(cfg_flag.syntax(), tabstop); } editor.add_mappings(make.finish_with_mappings()); @@ -301,66 +270,28 @@ fn wrap_cfg_attrs(acc: &mut Assists, ctx: &AssistContext<'_>, attrs: Vec Option<()> { - let range = attr.syntax().text_range(); - let meta = attr.meta()?; - let meta_tt = meta.token_tree()?; - let mut inner_attrs = Vec::with_capacity(1); - let mut found_comma = false; - let mut iter = meta_tt.token_trees_and_tokens().skip(1).peekable(); - while let Some(tt) = iter.next() { - if let NodeOrToken::Token(token) = &tt { - if token.kind() == T![')'] { - break; + +fn unwrap_cfg_attr(acc: &mut Assists, meta: ast::CfgAttrMeta) -> Option<()> { + let top_attr = ast::Meta::from(meta.clone()).parent_attr()?; + let range = top_attr.syntax().text_range(); + let inner_attrs = meta + .metas() + .map(|meta| { + if top_attr.excl_token().is_some() { + make::attr_inner(meta) + } else { + make::attr_outer(meta) } - if token.kind() == T![,] { - found_comma = true; - continue; - } - } - if !found_comma { - continue; - } - let Some(attr_name) = tt.into_token().and_then(|token| { - if token.kind() == T![ident] { Some(make::ext::ident_path(token.text())) } else { None } - }) else { - continue; - }; - let next_tt = iter.next()?; - let meta = match next_tt { - NodeOrToken::Node(tt) => make::meta_token_tree(attr_name, tt), - NodeOrToken::Token(token) if token.kind() == T![,] || token.kind() == T![')'] => { - make::meta_path(attr_name) - } - NodeOrToken::Token(token) => { - let equals = algo::skip_trivia_token(token, syntax::Direction::Next)?; - if equals.kind() != T![=] { - return None; - } - let expr_token = - algo::skip_trivia_token(equals.next_token()?, syntax::Direction::Next) - .and_then(|it| { - if it.kind().is_literal() { - Some(make::expr_literal(it.text())) - } else { - None - } - })?; - make::meta_expr(attr_name, ast::Expr::Literal(expr_token)) - } - }; - if attr.excl_token().is_some() { - inner_attrs.push(make::attr_inner(meta)); - } else { - inner_attrs.push(make::attr_outer(meta)); - } - } + }) + .collect::>(); if inner_attrs.is_empty() { return None; } let handle_source_change = |f: &mut SourceChangeBuilder| { - let inner_attrs = - inner_attrs.iter().map(|it| it.to_string()).join(&format!("\n{}", attr.indent_level())); + let inner_attrs = inner_attrs + .iter() + .map(|it| it.to_string()) + .join(&format!("\n{}", top_attr.indent_level())); f.replace(range, inner_attrs); }; acc.add( @@ -388,7 +319,7 @@ pub struct Test { } "#, r#" - #[cfg_attr($0, derive(Debug))] + #[cfg_attr(${0:cfg}, derive(Debug))] pub struct Test { test: u32, } @@ -422,7 +353,7 @@ pub struct Test { "#, r#" pub struct Test { - #[cfg_attr($0, foo)] + #[cfg_attr(${0:cfg}, foo)] test: u32, } "#, @@ -456,7 +387,7 @@ pub struct Test { r#" pub struct Test { #[other_attr] - #[cfg_attr($0, foo, bar)] + #[cfg_attr(${0:cfg}, foo, bar)] #[other_attr] test: u32, } @@ -491,7 +422,7 @@ pub struct Test { "#, r#" pub struct Test { - #[cfg_attr($0, foo = "bar")] + #[cfg_attr(${0:cfg}, foo = "bar")] test: u32, } "#, @@ -520,7 +451,7 @@ fn inner_attrs() { #![no_std$0] "#, r#" - #![cfg_attr($0, no_std)] + #![cfg_attr(${0:cfg}, no_std)] "#, ); check_assist( @@ -545,7 +476,7 @@ pub struct Test { "#, r#" #[derive( Clone, Copy)] - #[cfg_attr($0, derive(Debug))] + #[cfg_attr(${0:cfg}, derive(Debug))] pub struct Test { test: u32, } @@ -561,7 +492,7 @@ pub struct Test { "#, r#" #[derive(Clone, Copy)] - #[cfg_attr($0, derive(Debug))] + #[cfg_attr(${0:cfg}, derive(Debug))] pub struct Test { test: u32, } @@ -580,7 +511,7 @@ pub struct Test { "#, r#" #[derive( Clone, Copy)] - #[cfg_attr($0, derive(std::fmt::Debug))] + #[cfg_attr(${0:cfg}, derive(std::fmt::Debug))] pub struct Test { test: u32, } @@ -596,7 +527,7 @@ pub struct Test { "#, r#" #[derive(Clone, Copy)] - #[cfg_attr($0, derive(std::fmt::Debug))] + #[cfg_attr(${0:cfg}, derive(std::fmt::Debug))] pub struct Test { test: u32, } @@ -615,7 +546,7 @@ pub struct Test { "#, r#" #[derive(std::fmt::Debug, Clone)] - #[cfg_attr($0, derive(Copy))] + #[cfg_attr(${0:cfg}, derive(Copy))] pub struct Test { test: u32, } @@ -631,7 +562,7 @@ pub struct Test { "#, r#" #[derive(Clone, Copy)] - #[cfg_attr($0, derive(std::fmt::Debug))] + #[cfg_attr(${0:cfg}, derive(std::fmt::Debug))] pub struct Test { test: u32, } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/tests.rs b/src/tools/rust-analyzer/crates/ide-assists/src/tests.rs index a52bd74d146a..135e750ca066 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/tests.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/tests.rs @@ -207,6 +207,15 @@ pub(crate) fn check_assist_target( check(assist, ra_fixture, ExpectedResult::Target(target), None); } +#[track_caller] +pub(crate) fn check_assist_with_label( + assist: Handler, + #[rust_analyzer::rust_fixture] ra_fixture: &str, + label: &str, +) { + check(assist, ra_fixture, ExpectedResult::Label(label), None); +} + #[track_caller] pub(crate) fn check_assist_not_applicable( assist: Handler, @@ -307,6 +316,7 @@ enum ExpectedResult<'a> { Unresolved, After(&'a str), Target(&'a str), + Label(&'a str), } #[track_caller] @@ -335,7 +345,7 @@ fn check_with_config( let ctx = AssistContext::new(sema, &config, frange); let resolve = match expected { - ExpectedResult::Unresolved => AssistResolveStrategy::None, + ExpectedResult::Unresolved | ExpectedResult::Label(_) => AssistResolveStrategy::None, _ => AssistResolveStrategy::All, }; let mut acc = Assists::new(&ctx, resolve); @@ -404,6 +414,9 @@ fn check_with_config( let range = assist.target; assert_eq_text!(&text_without_caret[range], target); } + (Some(assist), ExpectedResult::Label(label)) => { + assert_eq!(assist.label.to_string(), label); + } (Some(assist), ExpectedResult::Unresolved) => assert!( assist.source_change.is_none(), "unresolved assist should not contain source changes" @@ -411,7 +424,10 @@ fn check_with_config( (Some(_), ExpectedResult::NotApplicable) => panic!("assist should not be applicable!"), ( None, - ExpectedResult::After(_) | ExpectedResult::Target(_) | ExpectedResult::Unresolved, + ExpectedResult::After(_) + | ExpectedResult::Target(_) + | ExpectedResult::Label(_) + | ExpectedResult::Unresolved, ) => { panic!("code action is not applicable") } @@ -479,6 +495,7 @@ pub fn test_some_range(a: int) -> bool { expect![[r#" Extract into... Replace if let with match + Convert to guarded return "#]] .assert_eq(&expected); } @@ -511,6 +528,7 @@ pub fn test_some_range(a: int) -> bool { expect![[r#" Extract into... Replace if let with match + Convert to guarded return "#]] .assert_eq(&expected); } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/tests/generated.rs b/src/tools/rust-analyzer/crates/ide-assists/src/tests/generated.rs index 66d5cf834f17..a499607c1f71 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/tests/generated.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/tests/generated.rs @@ -3852,7 +3852,7 @@ struct S { } "#####, r#####" -#[cfg_attr($0, derive(Debug))] +#[cfg_attr(${0:cfg}, derive(Debug))] struct S { field: i32 } diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/utils.rs b/src/tools/rust-analyzer/crates/ide-assists/src/utils.rs index 10057f868152..896743342c1a 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/utils.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/utils.rs @@ -203,11 +203,9 @@ fn has_def_name(item: &InFile) -> bool { /// [`filter_assoc_items()`]), clones each item for update and applies path transformation to it, /// then inserts into `impl_`. Returns the modified `impl_` and the first associated item that got /// inserted. -/// -/// Legacy: prefer [`add_trait_assoc_items_to_impl_with_factory`] when a [`SyntaxFactory`] is -/// available. #[must_use] pub fn add_trait_assoc_items_to_impl( + make: &SyntaxFactory, sema: &Semantics<'_, RootDatabase>, config: &AssistConfig, original_items: &[InFile], @@ -250,95 +248,23 @@ pub fn add_trait_assoc_items_to_impl( }) .filter_map(|item| match item { ast::AssocItem::Fn(fn_) if fn_.body().is_none() => { - let fn_ = fn_.clone_subtree(); - let new_body = make::block_expr(None, Some(expr_fill_default(config))); - let mut fn_editor = SyntaxEditor::new(fn_.syntax().clone()); - fn_.replace_or_insert_body(&mut fn_editor, new_body.clone_for_update()); - let new_fn_ = fn_editor.finish().new_root().clone(); - ast::AssocItem::cast(new_fn_) - } - ast::AssocItem::TypeAlias(type_alias) => { - let type_alias = type_alias.clone_subtree(); - if let Some(type_bound_list) = type_alias.type_bound_list() { - let mut type_alias_editor = SyntaxEditor::new(type_alias.syntax().clone()); - type_bound_list.remove(&mut type_alias_editor); - let type_alias = type_alias_editor.finish().new_root().clone(); - ast::AssocItem::cast(type_alias) - } else { - Some(ast::AssocItem::TypeAlias(type_alias)) - } - } - item => Some(item), - }) - .map(|item| AstNodeEdit::indent(&item, new_indent_level)) - .collect() -} - -/// [`SyntaxFactory`]-based variant of [`add_trait_assoc_items_to_impl`]. -#[must_use] -pub fn add_trait_assoc_items_to_impl_with_factory( - make: &SyntaxFactory, - sema: &Semantics<'_, RootDatabase>, - config: &AssistConfig, - original_items: &[InFile], - trait_: hir::Trait, - impl_: &ast::Impl, - target_scope: &hir::SemanticsScope<'_>, -) -> Vec { - let new_indent_level = IndentLevel::from_node(impl_.syntax()) + 1; - original_items - .iter() - .map(|InFile { file_id, value: original_item }| { - let mut cloned_item = { - if let Some(macro_file) = file_id.macro_file() { - let span_map = sema.db.expansion_span_map(macro_file); - let item_prettified = prettify_macro_expansion( - sema.db, - original_item.syntax().clone(), - &span_map, - target_scope.krate().into(), - ); - if let Some(formatted) = ast::AssocItem::cast(item_prettified) { - return formatted; - } else { - stdx::never!("formatted `AssocItem` could not be cast back to `AssocItem`"); - } - } - original_item - } - .reset_indent(); - - if let Some(source_scope) = sema.scope(original_item.syntax()) { - let transform = - PathTransform::trait_impl(target_scope, &source_scope, trait_, impl_.clone()); - cloned_item = ast::AssocItem::cast(transform.apply(cloned_item.syntax())).unwrap(); - } - cloned_item.remove_attrs_and_docs(); - cloned_item - }) - .filter_map(|item| match item { - ast::AssocItem::Fn(fn_) if fn_.body().is_none() => { - let fn_ = fn_.clone_subtree(); + let (mut fn_editor, fn_) = SyntaxEditor::with_ast_node(&fn_); let fill_expr: ast::Expr = match config.expr_fill_default { ExprFillDefaultMode::Todo | ExprFillDefaultMode::Default => make.expr_todo(), ExprFillDefaultMode::Underscore => make.expr_underscore().into(), }; let new_body = make.block_expr(None::, Some(fill_expr)); - let mut fn_editor = SyntaxEditor::new(fn_.syntax().clone()); fn_.replace_or_insert_body(&mut fn_editor, new_body); let new_fn_ = fn_editor.finish().new_root().clone(); ast::AssocItem::cast(new_fn_) } ast::AssocItem::TypeAlias(type_alias) => { - let type_alias = type_alias.clone_subtree(); + let (mut type_alias_editor, type_alias) = SyntaxEditor::with_ast_node(&type_alias); if let Some(type_bound_list) = type_alias.type_bound_list() { - let mut type_alias_editor = SyntaxEditor::new(type_alias.syntax().clone()); type_bound_list.remove(&mut type_alias_editor); - let type_alias = type_alias_editor.finish().new_root().clone(); - ast::AssocItem::cast(type_alias) - } else { - Some(ast::AssocItem::TypeAlias(type_alias)) - } + }; + let type_alias = type_alias_editor.finish().new_root().clone(); + ast::AssocItem::cast(type_alias) } item => Some(item), }) @@ -404,10 +330,8 @@ fn invert_special_case(make: &SyntaxFactory, expr: &ast::Expr) -> Option match pe.expr()? { - ast::Expr::ParenExpr(parexpr) => { - parexpr.expr().map(|e| e.clone_subtree().clone_for_update()) - } - _ => pe.expr().map(|e| e.clone_subtree().clone_for_update()), + ast::Expr::ParenExpr(parexpr) => parexpr.expr(), + _ => pe.expr(), }, ast::Expr::Literal(lit) => match lit.kind() { ast::LiteralKind::Bool(b) => match b { @@ -674,9 +598,7 @@ fn generate_impl_text_inner( // Copy any cfg attrs from the original adt buf.push_str("\n\n"); - let cfg_attrs = adt - .attrs() - .filter(|attr| attr.as_simple_call().map(|(name, _arg)| name == "cfg").unwrap_or(false)); + let cfg_attrs = adt.attrs().filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))); cfg_attrs.for_each(|attr| buf.push_str(&format!("{attr}\n"))); // `impl{generic_params} {trait_text} for {name}{generic_params.to_generic_args()}` @@ -758,6 +680,16 @@ pub(crate) fn generate_trait_impl_intransitive_with_item( generate_impl_inner_with_factory(make, false, adt, Some(trait_), false, Some(body)) } +pub(crate) fn generate_trait_impl_with_item( + make: &SyntaxFactory, + is_unsafe: bool, + adt: &ast::Adt, + trait_: ast::Type, + body: ast::AssocItemList, +) -> ast::Impl { + generate_impl_inner_with_factory(make, is_unsafe, adt, Some(trait_), true, Some(body)) +} + fn generate_impl_inner( is_unsafe: bool, adt: &ast::Adt, @@ -806,8 +738,7 @@ fn generate_impl_inner( let ty = make::ty_path(make::ext::ident_path(&adt.name().unwrap().text())); - let cfg_attrs = - adt.attrs().filter(|attr| attr.as_simple_call().is_some_and(|(name, _arg)| name == "cfg")); + let cfg_attrs = adt.attrs().filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))); match trait_ { Some(trait_) => make::impl_trait( cfg_attrs, @@ -877,8 +808,7 @@ fn generate_impl_inner_with_factory( let ty: ast::Type = make.ty_path(make.ident_path(&adt.name().unwrap().text())).into(); - let cfg_attrs = - adt.attrs().filter(|attr| attr.as_simple_call().is_some_and(|(name, _arg)| name == "cfg")); + let cfg_attrs = adt.attrs().filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))); match trait_ { Some(trait_) => make.impl_trait( cfg_attrs, diff --git a/src/tools/rust-analyzer/crates/ide-assists/src/utils/gen_trait_fn_body.rs b/src/tools/rust-analyzer/crates/ide-assists/src/utils/gen_trait_fn_body.rs index 87e90e85193c..b0d88737fe0f 100644 --- a/src/tools/rust-analyzer/crates/ide-assists/src/utils/gen_trait_fn_body.rs +++ b/src/tools/rust-analyzer/crates/ide-assists/src/utils/gen_trait_fn_body.rs @@ -1,7 +1,10 @@ //! This module contains functions to generate default trait impl function bodies where possible. use hir::TraitRef; -use syntax::ast::{self, AstNode, BinaryOp, CmpOp, HasName, LogicOp, edit::AstNodeEdit, make}; +use syntax::ast::{ + self, AstNode, BinaryOp, CmpOp, HasName, LogicOp, edit::AstNodeEdit, + syntax_factory::SyntaxFactory, +}; /// Generate custom trait bodies without default implementation where possible. /// @@ -11,6 +14,7 @@ /// `None` means that generating a custom trait body failed, and the body will remain /// as `todo!` instead. pub(crate) fn gen_trait_fn_body( + make: &SyntaxFactory, func: &ast::Fn, trait_path: &ast::Path, adt: &ast::Adt, @@ -20,32 +24,32 @@ pub(crate) fn gen_trait_fn_body( match trait_path.segment()?.name_ref()?.text().as_str() { "Clone" => { stdx::always!(func.name().is_some_and(|name| name.text() == "clone")); - gen_clone_impl(adt) + gen_clone_impl(make, adt) } - "Debug" => gen_debug_impl(adt), - "Default" => gen_default_impl(adt), + "Debug" => gen_debug_impl(make, adt), + "Default" => gen_default_impl(make, adt), "Hash" => { stdx::always!(func.name().is_some_and(|name| name.text() == "hash")); - gen_hash_impl(adt) + gen_hash_impl(make, adt) } "PartialEq" => { stdx::always!(func.name().is_some_and(|name| name.text() == "eq")); - gen_partial_eq(adt, trait_ref) + gen_partial_eq(make, adt, trait_ref) } "PartialOrd" => { stdx::always!(func.name().is_some_and(|name| name.text() == "partial_cmp")); - gen_partial_ord(adt, trait_ref) + gen_partial_ord(make, adt, trait_ref) } _ => None, } } /// Generate a `Clone` impl based on the fields and members of the target type. -fn gen_clone_impl(adt: &ast::Adt) -> Option { - fn gen_clone_call(target: ast::Expr) -> ast::Expr { - let method = make::name_ref("clone"); - make::expr_method_call(target, method, make::arg_list(None)).into() - } +fn gen_clone_impl(make: &SyntaxFactory, adt: &ast::Adt) -> Option { + let gen_clone_call = |target: ast::Expr| -> ast::Expr { + let method = make.name_ref("clone"); + make.expr_method_call(target, method, make.arg_list([])).into() + }; let expr = match adt { // `Clone` cannot be derived for unions, so no default impl can be provided. ast::Adt::Union(_) => return None, @@ -54,7 +58,7 @@ fn gen_clone_call(target: ast::Expr) -> ast::Expr { let mut arms = vec![]; for variant in list.variants() { let name = variant.name()?; - let variant_name = make::ext::path_from_idents(["Self", &format!("{name}")])?; + let variant_name = make.path_from_idents(["Self", &format!("{name}")])?; match variant.field_list() { // => match self { Self::Name { x } => Self::Name { x: x.clone() } } @@ -63,19 +67,20 @@ fn gen_clone_call(target: ast::Expr) -> ast::Expr { let mut fields = vec![]; for field in list.fields() { let field_name = field.name()?; - let pat = make::ident_pat(false, false, field_name.clone()); - pats.push(pat.into()); + let pat = make.ident_pat(false, false, field_name.clone()); + pats.push(make.record_pat_field_shorthand(pat.into())); - let path = make::ext::ident_path(&field_name.to_string()); - let method_call = gen_clone_call(make::expr_path(path)); - let name_ref = make::name_ref(&field_name.to_string()); - let field = make::record_expr_field(name_ref, Some(method_call)); + let path = make.ident_path(&field_name.to_string()); + let method_call = gen_clone_call(make.expr_path(path)); + let name_ref = make.name_ref(&field_name.to_string()); + let field = make.record_expr_field(name_ref, Some(method_call)); fields.push(field); } - let pat = make::record_pat(variant_name.clone(), pats.into_iter()); - let fields = make::record_expr_field_list(fields); - let record_expr = make::record_expr(variant_name, fields).into(); - arms.push(make::match_arm(pat.into(), None, record_expr)); + let pat_field_list = make.record_pat_field_list(pats, None); + let pat = make.record_pat_with_fields(variant_name.clone(), pat_field_list); + let fields = make.record_expr_field_list(fields); + let record_expr = make.record_expr(variant_name, fields).into(); + arms.push(make.match_arm(pat.into(), None, record_expr)); } // => match self { Self::Name(arg1) => Self::Name(arg1.clone()) } @@ -84,31 +89,30 @@ fn gen_clone_call(target: ast::Expr) -> ast::Expr { let mut fields = vec![]; for (i, _) in list.fields().enumerate() { let field_name = format!("arg{i}"); - let pat = make::ident_pat(false, false, make::name(&field_name)); + let pat = make.ident_pat(false, false, make.name(&field_name)); pats.push(pat.into()); - let f_path = make::expr_path(make::ext::ident_path(&field_name)); + let f_path = make.expr_path(make.ident_path(&field_name)); fields.push(gen_clone_call(f_path)); } - let pat = make::tuple_struct_pat(variant_name.clone(), pats.into_iter()); - let struct_name = make::expr_path(variant_name); - let tuple_expr = - make::expr_call(struct_name, make::arg_list(fields)).into(); - arms.push(make::match_arm(pat.into(), None, tuple_expr)); + let pat = make.tuple_struct_pat(variant_name.clone(), pats.into_iter()); + let struct_name = make.expr_path(variant_name); + let tuple_expr = make.expr_call(struct_name, make.arg_list(fields)).into(); + arms.push(make.match_arm(pat.into(), None, tuple_expr)); } // => match self { Self::Name => Self::Name } None => { - let pattern = make::path_pat(variant_name.clone()); - let variant_expr = make::expr_path(variant_name); - arms.push(make::match_arm(pattern, None, variant_expr)); + let pattern = make.path_pat(variant_name.clone()); + let variant_expr = make.expr_path(variant_name); + arms.push(make.match_arm(pattern, None, variant_expr)); } } } - let match_target = make::expr_path(make::ext::ident_path("self")); - let list = make::match_arm_list(arms).indent(ast::edit::IndentLevel(1)); - make::expr_match(match_target, list).into() + let match_target = make.expr_path(make.ident_path("self")); + let list = make.match_arm_list(arms).indent(ast::edit::IndentLevel(1)); + make.expr_match(match_target, list).into() } ast::Adt::Struct(strukt) => { match strukt.field_list() { @@ -116,43 +120,43 @@ fn gen_clone_call(target: ast::Expr) -> ast::Expr { Some(ast::FieldList::RecordFieldList(field_list)) => { let mut fields = vec![]; for field in field_list.fields() { - let base = make::expr_path(make::ext::ident_path("self")); - let target = make::expr_field(base, &field.name()?.to_string()); + let base = make.expr_path(make.ident_path("self")); + let target = make.expr_field(base, &field.name()?.to_string()).into(); let method_call = gen_clone_call(target); - let name_ref = make::name_ref(&field.name()?.to_string()); - let field = make::record_expr_field(name_ref, Some(method_call)); + let name_ref = make.name_ref(&field.name()?.to_string()); + let field = make.record_expr_field(name_ref, Some(method_call)); fields.push(field); } - let struct_name = make::ext::ident_path("Self"); - let fields = make::record_expr_field_list(fields); - make::record_expr(struct_name, fields).into() + let struct_name = make.ident_path("Self"); + let fields = make.record_expr_field_list(fields); + make.record_expr(struct_name, fields).into() } // => Self(self.0.clone(), self.1.clone()) Some(ast::FieldList::TupleFieldList(field_list)) => { let mut fields = vec![]; for (i, _) in field_list.fields().enumerate() { - let f_path = make::expr_path(make::ext::ident_path("self")); - let target = make::expr_field(f_path, &format!("{i}")); + let f_path = make.expr_path(make.ident_path("self")); + let target = make.expr_field(f_path, &format!("{i}")).into(); fields.push(gen_clone_call(target)); } - let struct_name = make::expr_path(make::ext::ident_path("Self")); - make::expr_call(struct_name, make::arg_list(fields)).into() + let struct_name = make.expr_path(make.ident_path("Self")); + make.expr_call(struct_name, make.arg_list(fields)).into() } // => Self { } None => { - let struct_name = make::ext::ident_path("Self"); - let fields = make::record_expr_field_list(None); - make::record_expr(struct_name, fields).into() + let struct_name = make.ident_path("Self"); + let fields = make.record_expr_field_list([]); + make.record_expr(struct_name, fields).into() } } } }; - let body = make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)); + let body = make.block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)); Some(body) } /// Generate a `Debug` impl based on the fields and members of the target type. -fn gen_debug_impl(adt: &ast::Adt) -> Option { +fn gen_debug_impl(make: &SyntaxFactory, adt: &ast::Adt) -> Option { let annotated_name = adt.name()?; match adt { // `Debug` cannot be derived for unions, so no default impl can be provided. @@ -164,156 +168,154 @@ fn gen_debug_impl(adt: &ast::Adt) -> Option { let mut arms = vec![]; for variant in list.variants() { let name = variant.name()?; - let variant_name = make::ext::path_from_idents(["Self", &format!("{name}")])?; - let target = make::expr_path(make::ext::ident_path("f")); + let variant_name = make.path_from_idents(["Self", &format!("{name}")])?; + let target = make.expr_path(make.ident_path("f")); match variant.field_list() { Some(ast::FieldList::RecordFieldList(list)) => { // => f.debug_struct(name) - let target = make::expr_path(make::ext::ident_path("f")); - let method = make::name_ref("debug_struct"); + let target = make.expr_path(make.ident_path("f")); + let method = make.name_ref("debug_struct"); let struct_name = format!("\"{name}\""); - let args = make::arg_list(Some(make::expr_literal(&struct_name).into())); - let mut expr = make::expr_method_call(target, method, args).into(); + let args = make.arg_list([make.expr_literal(&struct_name).into()]); + let mut expr = make.expr_method_call(target, method, args).into(); let mut pats = vec![]; for field in list.fields() { let field_name = field.name()?; // create a field pattern for use in `MyStruct { fields.. }` - let pat = make::ident_pat(false, false, field_name.clone()); - pats.push(pat.into()); + let pat = make.ident_pat(false, false, field_name.clone()); + pats.push(make.record_pat_field_shorthand(pat.into())); // => .field("field_name", field) - let method_name = make::name_ref("field"); - let name = make::expr_literal(&(format!("\"{field_name}\""))).into(); + let method_name = make.name_ref("field"); + let name = make.expr_literal(&(format!("\"{field_name}\""))).into(); let path = &format!("{field_name}"); - let path = make::expr_path(make::ext::ident_path(path)); - let args = make::arg_list(vec![name, path]); - expr = make::expr_method_call(expr, method_name, args).into(); + let path = make.expr_path(make.ident_path(path)); + let args = make.arg_list([name, path]); + expr = make.expr_method_call(expr, method_name, args).into(); } // => .finish() - let method = make::name_ref("finish"); - let expr = - make::expr_method_call(expr, method, make::arg_list(None)).into(); + let method = make.name_ref("finish"); + let expr = make.expr_method_call(expr, method, make.arg_list([])).into(); // => MyStruct { fields.. } => f.debug_struct("MyStruct")...finish(), - let pat = make::record_pat(variant_name.clone(), pats.into_iter()); - arms.push(make::match_arm(pat.into(), None, expr)); + let pat_field_list = make.record_pat_field_list(pats, None); + let pat = make.record_pat_with_fields(variant_name.clone(), pat_field_list); + arms.push(make.match_arm(pat.into(), None, expr)); } Some(ast::FieldList::TupleFieldList(list)) => { // => f.debug_tuple(name) - let target = make::expr_path(make::ext::ident_path("f")); - let method = make::name_ref("debug_tuple"); + let target = make.expr_path(make.ident_path("f")); + let method = make.name_ref("debug_tuple"); let struct_name = format!("\"{name}\""); - let args = make::arg_list(Some(make::expr_literal(&struct_name).into())); - let mut expr = make::expr_method_call(target, method, args).into(); + let args = make.arg_list([make.expr_literal(&struct_name).into()]); + let mut expr = make.expr_method_call(target, method, args).into(); let mut pats = vec![]; for (i, _) in list.fields().enumerate() { let name = format!("arg{i}"); // create a field pattern for use in `MyStruct(fields..)` - let field_name = make::name(&name); - let pat = make::ident_pat(false, false, field_name.clone()); + let field_name = make.name(&name); + let pat = make.ident_pat(false, false, field_name.clone()); pats.push(pat.into()); // => .field(field) - let method_name = make::name_ref("field"); + let method_name = make.name_ref("field"); let field_path = &name.to_string(); - let field_path = make::expr_path(make::ext::ident_path(field_path)); - let args = make::arg_list(vec![field_path]); - expr = make::expr_method_call(expr, method_name, args).into(); + let field_path = make.expr_path(make.ident_path(field_path)); + let args = make.arg_list([field_path]); + expr = make.expr_method_call(expr, method_name, args).into(); } // => .finish() - let method = make::name_ref("finish"); - let expr = - make::expr_method_call(expr, method, make::arg_list(None)).into(); + let method = make.name_ref("finish"); + let expr = make.expr_method_call(expr, method, make.arg_list([])).into(); // => MyStruct (fields..) => f.debug_tuple("MyStruct")...finish(), - let pat = make::tuple_struct_pat(variant_name.clone(), pats.into_iter()); - arms.push(make::match_arm(pat.into(), None, expr)); + let pat = make.tuple_struct_pat(variant_name.clone(), pats.into_iter()); + arms.push(make.match_arm(pat.into(), None, expr)); } None => { - let fmt_string = make::expr_literal(&(format!("\"{name}\""))).into(); - let args = make::ext::token_tree_from_node( - make::arg_list([target, fmt_string]).syntax(), - ); - let macro_name = make::ext::ident_path("write"); - let macro_call = make::expr_macro(macro_name, args); + let fmt_string = make.expr_literal(&(format!("\"{name}\""))).into(); + let args = + make.token_tree_from_node(make.arg_list([target, fmt_string]).syntax()); + let macro_name = make.ident_path("write"); + let macro_call = make.expr_macro(macro_name, args); - let variant_name = make::path_pat(variant_name); - arms.push(make::match_arm(variant_name, None, macro_call.into())); + let variant_name = make.path_pat(variant_name); + arms.push(make.match_arm(variant_name, None, macro_call.into())); } } } - let match_target = make::expr_path(make::ext::ident_path("self")); - let list = make::match_arm_list(arms).indent(ast::edit::IndentLevel(1)); - let match_expr = make::expr_match(match_target, list); + let match_target = make.expr_path(make.ident_path("self")); + let list = make.match_arm_list(arms).indent(ast::edit::IndentLevel(1)); + let match_expr = make.expr_match(match_target, list); - let body = make::block_expr(None, Some(match_expr.into())); + let body = make.block_expr(None::, Some(match_expr.into())); let body = body.indent(ast::edit::IndentLevel(1)); Some(body) } ast::Adt::Struct(strukt) => { let name = format!("\"{annotated_name}\""); - let args = make::arg_list(Some(make::expr_literal(&name).into())); - let target = make::expr_path(make::ext::ident_path("f")); + let args = make.arg_list([make.expr_literal(&name).into()]); + let target = make.expr_path(make.ident_path("f")); let expr = match strukt.field_list() { // => f.debug_struct("Name").finish() - None => make::expr_method_call(target, make::name_ref("debug_struct"), args).into(), + None => make.expr_method_call(target, make.name_ref("debug_struct"), args).into(), // => f.debug_struct("Name").field("foo", &self.foo).finish() Some(ast::FieldList::RecordFieldList(field_list)) => { - let method = make::name_ref("debug_struct"); - let mut expr = make::expr_method_call(target, method, args).into(); + let method = make.name_ref("debug_struct"); + let mut expr = make.expr_method_call(target, method, args).into(); for field in field_list.fields() { let name = field.name()?; - let f_name = make::expr_literal(&(format!("\"{name}\""))).into(); - let f_path = make::expr_path(make::ext::ident_path("self")); - let f_path = make::expr_ref(f_path, false); - let f_path = make::expr_field(f_path, &format!("{name}")); - let args = make::arg_list([f_name, f_path]); - expr = make::expr_method_call(expr, make::name_ref("field"), args).into(); + let f_name = make.expr_literal(&(format!("\"{name}\""))).into(); + let f_path = make.expr_path(make.ident_path("self")); + let f_path = make.expr_field(f_path, &format!("{name}")).into(); + let f_path = make.expr_ref(f_path, false); + let args = make.arg_list([f_name, f_path]); + expr = make.expr_method_call(expr, make.name_ref("field"), args).into(); } expr } - // => f.debug_tuple("Name").field(self.0).finish() + // => f.debug_tuple("Name").field(&self.0).finish() Some(ast::FieldList::TupleFieldList(field_list)) => { - let method = make::name_ref("debug_tuple"); - let mut expr = make::expr_method_call(target, method, args).into(); + let method = make.name_ref("debug_tuple"); + let mut expr = make.expr_method_call(target, method, args).into(); for (i, _) in field_list.fields().enumerate() { - let f_path = make::expr_path(make::ext::ident_path("self")); - let f_path = make::expr_ref(f_path, false); - let f_path = make::expr_field(f_path, &format!("{i}")); - let method = make::name_ref("field"); - expr = make::expr_method_call(expr, method, make::arg_list(Some(f_path))) - .into(); + let f_path = make.expr_path(make.ident_path("self")); + let f_path = make.expr_field(f_path, &format!("{i}")).into(); + let f_path = make.expr_ref(f_path, false); + let method = make.name_ref("field"); + expr = make.expr_method_call(expr, method, make.arg_list([f_path])).into(); } expr } }; - let method = make::name_ref("finish"); - let expr = make::expr_method_call(expr, method, make::arg_list(None)).into(); - let body = make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)); + let method = make.name_ref("finish"); + let expr = make.expr_method_call(expr, method, make.arg_list([])).into(); + let body = + make.block_expr(None::, Some(expr)).indent(ast::edit::IndentLevel(1)); Some(body) } } } -/// Generate a `Debug` impl based on the fields and members of the target type. -fn gen_default_impl(adt: &ast::Adt) -> Option { - fn gen_default_call() -> Option { - let fn_name = make::ext::path_from_idents(["Default", "default"])?; - Some(make::expr_call(make::expr_path(fn_name), make::arg_list(None)).into()) - } +/// Generate a `Default` impl based on the fields and members of the target type. +fn gen_default_impl(make: &SyntaxFactory, adt: &ast::Adt) -> Option { + let gen_default_call = || -> Option { + let fn_name = make.path_from_idents(["Default", "default"])?; + Some(make.expr_call(make.expr_path(fn_name), make.arg_list([])).into()) + }; match adt { // `Debug` cannot be derived for unions, so no default impl can be provided. ast::Adt::Union(_) => None, @@ -325,42 +327,43 @@ fn gen_default_call() -> Option { let mut fields = vec![]; for field in field_list.fields() { let method_call = gen_default_call()?; - let name_ref = make::name_ref(&field.name()?.to_string()); - let field = make::record_expr_field(name_ref, Some(method_call)); + let name_ref = make.name_ref(&field.name()?.to_string()); + let field = make.record_expr_field(name_ref, Some(method_call)); fields.push(field); } - let struct_name = make::ext::ident_path("Self"); - let fields = make::record_expr_field_list(fields); - make::record_expr(struct_name, fields).into() + let struct_name = make.ident_path("Self"); + let fields = make.record_expr_field_list(fields); + make.record_expr(struct_name, fields).into() } Some(ast::FieldList::TupleFieldList(field_list)) => { - let struct_name = make::expr_path(make::ext::ident_path("Self")); + let struct_name = make.expr_path(make.ident_path("Self")); let fields = field_list .fields() .map(|_| gen_default_call()) .collect::>>()?; - make::expr_call(struct_name, make::arg_list(fields)).into() + make.expr_call(struct_name, make.arg_list(fields)).into() } None => { - let struct_name = make::ext::ident_path("Self"); - let fields = make::record_expr_field_list(None); - make::record_expr(struct_name, fields).into() + let struct_name = make.ident_path("Self"); + let fields = make.record_expr_field_list([]); + make.record_expr(struct_name, fields).into() } }; - let body = make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)); + let body = + make.block_expr(None::, Some(expr)).indent(ast::edit::IndentLevel(1)); Some(body) } } } /// Generate a `Hash` impl based on the fields and members of the target type. -fn gen_hash_impl(adt: &ast::Adt) -> Option { - fn gen_hash_call(target: ast::Expr) -> ast::Stmt { - let method = make::name_ref("hash"); - let arg = make::expr_path(make::ext::ident_path("state")); - let expr = make::expr_method_call(target, method, make::arg_list(Some(arg))).into(); - make::expr_stmt(expr).into() - } +fn gen_hash_impl(make: &SyntaxFactory, adt: &ast::Adt) -> Option { + let gen_hash_call = |target: ast::Expr| -> ast::Stmt { + let method = make.name_ref("hash"); + let arg = make.expr_path(make.ident_path("state")); + let expr = make.expr_method_call(target, method, make.arg_list([arg])).into(); + make.expr_stmt(expr).into() + }; let body = match adt { // `Hash` cannot be derived for unions, so no default impl can be provided. @@ -368,35 +371,35 @@ fn gen_hash_call(target: ast::Expr) -> ast::Stmt { // => std::mem::discriminant(self).hash(state); ast::Adt::Enum(_) => { - let fn_name = make_discriminant()?; + let fn_name = make_discriminant(make)?; - let arg = make::expr_path(make::ext::ident_path("self")); - let fn_call = make::expr_call(fn_name, make::arg_list(Some(arg))).into(); + let arg = make.expr_path(make.ident_path("self")); + let fn_call: ast::Expr = make.expr_call(fn_name, make.arg_list([arg])).into(); let stmt = gen_hash_call(fn_call); - make::block_expr(Some(stmt), None).indent(ast::edit::IndentLevel(1)) + make.block_expr([stmt], None).indent(ast::edit::IndentLevel(1)) } ast::Adt::Struct(strukt) => match strukt.field_list() { // => self..hash(state); Some(ast::FieldList::RecordFieldList(field_list)) => { let mut stmts = vec![]; for field in field_list.fields() { - let base = make::expr_path(make::ext::ident_path("self")); - let target = make::expr_field(base, &field.name()?.to_string()); + let base = make.expr_path(make.ident_path("self")); + let target = make.expr_field(base, &field.name()?.to_string()).into(); stmts.push(gen_hash_call(target)); } - make::block_expr(stmts, None).indent(ast::edit::IndentLevel(1)) + make.block_expr(stmts, None).indent(ast::edit::IndentLevel(1)) } // => self..hash(state); Some(ast::FieldList::TupleFieldList(field_list)) => { let mut stmts = vec![]; for (i, _) in field_list.fields().enumerate() { - let base = make::expr_path(make::ext::ident_path("self")); - let target = make::expr_field(base, &format!("{i}")); + let base = make.expr_path(make.ident_path("self")); + let target = make.expr_field(base, &format!("{i}")).into(); stmts.push(gen_hash_call(target)); } - make::block_expr(stmts, None).indent(ast::edit::IndentLevel(1)) + make.block_expr(stmts, None).indent(ast::edit::IndentLevel(1)) } // No fields in the body means there's nothing to hash. @@ -408,32 +411,37 @@ fn gen_hash_call(target: ast::Expr) -> ast::Stmt { } /// Generate a `PartialEq` impl based on the fields and members of the target type. -fn gen_partial_eq(adt: &ast::Adt, trait_ref: Option>) -> Option { - fn gen_eq_chain(expr: Option, cmp: ast::Expr) -> Option { +fn gen_partial_eq( + make: &SyntaxFactory, + adt: &ast::Adt, + trait_ref: Option>, +) -> Option { + let gen_eq_chain = |expr: Option, cmp: ast::Expr| -> Option { match expr { - Some(expr) => Some(make::expr_bin_op(expr, BinaryOp::LogicOp(LogicOp::And), cmp)), + Some(expr) => Some(make.expr_bin_op(expr, BinaryOp::LogicOp(LogicOp::And), cmp)), None => Some(cmp), } - } + }; - fn gen_record_pat_field(field_name: &str, pat_name: &str) -> ast::RecordPatField { - let pat = make::ext::simple_ident_pat(make::name(pat_name)); - let name_ref = make::name_ref(field_name); - make::record_pat_field(name_ref, pat.into()) - } + let gen_record_pat_field = |field_name: &str, pat_name: &str| -> ast::RecordPatField { + let pat = make.ident_pat(false, false, make.name(pat_name)); + let name_ref = make.name_ref(field_name); + make.record_pat_field(name_ref, pat.into()) + }; - fn gen_record_pat(record_name: ast::Path, fields: Vec) -> ast::RecordPat { - let list = make::record_pat_field_list(fields, None); - make::record_pat_with_fields(record_name, list) - } + let gen_record_pat = + |record_name: ast::Path, fields: Vec| -> ast::RecordPat { + let list = make.record_pat_field_list(fields, None); + make.record_pat_with_fields(record_name, list) + }; - fn gen_variant_path(variant: &ast::Variant) -> Option { - make::ext::path_from_idents(["Self", &variant.name()?.to_string()]) - } + let gen_variant_path = |variant: &ast::Variant| -> Option { + make.path_from_idents(["Self", &variant.name()?.to_string()]) + }; - fn gen_tuple_field(field_name: &str) -> ast::Pat { - ast::Pat::IdentPat(make::ident_pat(false, false, make::name(field_name))) - } + let gen_tuple_field = |field_name: &str| -> ast::Pat { + ast::Pat::IdentPat(make.ident_pat(false, false, make.name(field_name))) + }; // Check that self type and rhs type match. We don't know how to implement the method // automatically otherwise. @@ -451,14 +459,14 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { ast::Adt::Enum(enum_) => { // => std::mem::discriminant(self) == std::mem::discriminant(other) - let lhs_name = make::expr_path(make::ext::ident_path("self")); - let lhs = make::expr_call(make_discriminant()?, make::arg_list(Some(lhs_name.clone()))) - .into(); - let rhs_name = make::expr_path(make::ext::ident_path("other")); - let rhs = make::expr_call(make_discriminant()?, make::arg_list(Some(rhs_name.clone()))) - .into(); + let lhs_name = make.expr_path(make.ident_path("self")); + let lhs = + make.expr_call(make_discriminant(make)?, make.arg_list([lhs_name.clone()])).into(); + let rhs_name = make.expr_path(make.ident_path("other")); + let rhs = + make.expr_call(make_discriminant(make)?, make.arg_list([rhs_name.clone()])).into(); let eq_check = - make::expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); + make.expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); let mut n_cases = 0; let mut arms = vec![]; @@ -480,9 +488,9 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { let r_name = &format!("r_{field_name}"); r_fields.push(gen_record_pat_field(&field_name, r_name)); - let lhs = make::expr_path(make::ext::ident_path(l_name)); - let rhs = make::expr_path(make::ext::ident_path(r_name)); - let cmp = make::expr_bin_op( + let lhs = make.expr_path(make.ident_path(l_name)); + let rhs = make.expr_path(make.ident_path(r_name)); + let cmp = make.expr_bin_op( lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs, @@ -492,10 +500,10 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { let left = gen_record_pat(gen_variant_path(&variant)?, l_fields); let right = gen_record_pat(gen_variant_path(&variant)?, r_fields); - let tuple = make::tuple_pat(vec![left.into(), right.into()]); + let tuple = make.tuple_pat(vec![left.into(), right.into()]); if let Some(expr) = expr { - arms.push(make::match_arm(tuple.into(), None, expr)); + arms.push(make.match_arm(tuple.into(), None, expr)); } } @@ -513,9 +521,9 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { let r_name = format!("r{field_name}"); r_fields.push(gen_tuple_field(&r_name)); - let lhs = make::expr_path(make::ext::ident_path(&l_name)); - let rhs = make::expr_path(make::ext::ident_path(&r_name)); - let cmp = make::expr_bin_op( + let lhs = make.expr_path(make.ident_path(&l_name)); + let rhs = make.expr_path(make.ident_path(&r_name)); + let cmp = make.expr_bin_op( lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs, @@ -523,12 +531,12 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { expr = gen_eq_chain(expr, cmp); } - let left = make::tuple_struct_pat(gen_variant_path(&variant)?, l_fields); - let right = make::tuple_struct_pat(gen_variant_path(&variant)?, r_fields); - let tuple = make::tuple_pat(vec![left.into(), right.into()]); + let left = make.tuple_struct_pat(gen_variant_path(&variant)?, l_fields); + let right = make.tuple_struct_pat(gen_variant_path(&variant)?, r_fields); + let tuple = make.tuple_pat(vec![left.into(), right.into()]); if let Some(expr) = expr { - arms.push(make::match_arm(tuple.into(), None, expr)); + arms.push(make.match_arm(tuple.into(), None, expr)); } } None => continue, @@ -542,57 +550,57 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { // The fallback arm will be `_ => false,` if we've already gone through every case where the variants of self and other match, // and `_ => std::mem::discriminant(self) == std::mem::discriminant(other),` otherwise. if n_cases > 1 { - let lhs = make::wildcard_pat().into(); + let lhs = make.wildcard_pat().into(); let rhs = if arms_len == n_cases { - make::expr_literal("false").into() + make.expr_literal("false").into() } else { eq_check }; - arms.push(make::match_arm(lhs, None, rhs)); + arms.push(make.match_arm(lhs, None, rhs)); } - let match_target = make::expr_tuple([lhs_name, rhs_name]).into(); - let list = make::match_arm_list(arms).indent(ast::edit::IndentLevel(1)); - make::expr_match(match_target, list).into() + let match_target = make.expr_tuple([lhs_name, rhs_name]).into(); + let list = make.match_arm_list(arms).indent(ast::edit::IndentLevel(1)); + make.expr_match(match_target, list).into() } }; - make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)) + make.block_expr(None::, Some(expr)).indent(ast::edit::IndentLevel(1)) } ast::Adt::Struct(strukt) => match strukt.field_list() { Some(ast::FieldList::RecordFieldList(field_list)) => { let mut expr = None; for field in field_list.fields() { - let lhs = make::expr_path(make::ext::ident_path("self")); - let lhs = make::expr_field(lhs, &field.name()?.to_string()); - let rhs = make::expr_path(make::ext::ident_path("other")); - let rhs = make::expr_field(rhs, &field.name()?.to_string()); + let lhs = make.expr_path(make.ident_path("self")); + let lhs = make.expr_field(lhs, &field.name()?.to_string()).into(); + let rhs = make.expr_path(make.ident_path("other")); + let rhs = make.expr_field(rhs, &field.name()?.to_string()).into(); let cmp = - make::expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); + make.expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); expr = gen_eq_chain(expr, cmp); } - make::block_expr(None, expr).indent(ast::edit::IndentLevel(1)) + make.block_expr(None, expr).indent(ast::edit::IndentLevel(1)) } Some(ast::FieldList::TupleFieldList(field_list)) => { let mut expr = None; for (i, _) in field_list.fields().enumerate() { let idx = format!("{i}"); - let lhs = make::expr_path(make::ext::ident_path("self")); - let lhs = make::expr_field(lhs, &idx); - let rhs = make::expr_path(make::ext::ident_path("other")); - let rhs = make::expr_field(rhs, &idx); + let lhs = make.expr_path(make.ident_path("self")); + let lhs = make.expr_field(lhs, &idx).into(); + let rhs = make.expr_path(make.ident_path("other")); + let rhs = make.expr_field(rhs, &idx).into(); let cmp = - make::expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); + make.expr_bin_op(lhs, BinaryOp::CmpOp(CmpOp::Eq { negated: false }), rhs); expr = gen_eq_chain(expr, cmp); } - make::block_expr(None, expr).indent(ast::edit::IndentLevel(1)) + make.block_expr(None::, expr).indent(ast::edit::IndentLevel(1)) } // No fields in the body means there's nothing to compare. None => { - let expr = make::expr_literal("true").into(); - make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)) + let expr = make.expr_literal("true").into(); + make.block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)) } }, }; @@ -600,29 +608,33 @@ fn gen_tuple_field(field_name: &str) -> ast::Pat { Some(body) } -fn gen_partial_ord(adt: &ast::Adt, trait_ref: Option>) -> Option { - fn gen_partial_eq_match(match_target: ast::Expr) -> Option { +fn gen_partial_ord( + make: &SyntaxFactory, + adt: &ast::Adt, + trait_ref: Option>, +) -> Option { + let gen_partial_eq_match = |match_target: ast::Expr| -> Option { let mut arms = vec![]; let variant_name = - make::path_pat(make::ext::path_from_idents(["core", "cmp", "Ordering", "Equal"])?); - let lhs = make::tuple_struct_pat(make::ext::path_from_idents(["Some"])?, [variant_name]); - arms.push(make::match_arm(lhs.into(), None, make::expr_empty_block().into())); + make.path_pat(make.path_from_idents(["core", "cmp", "Ordering", "Equal"])?); + let lhs = make.tuple_struct_pat(make.path_from_idents(["Some"])?, [variant_name]); + arms.push(make.match_arm(lhs.into(), None, make.expr_empty_block().into())); - arms.push(make::match_arm( - make::ident_pat(false, false, make::name("ord")).into(), + arms.push(make.match_arm( + make.ident_pat(false, false, make.name("ord")).into(), None, - make::expr_return(Some(make::expr_path(make::ext::ident_path("ord")))), + make.expr_return(Some(make.expr_path(make.ident_path("ord")))).into(), )); - let list = make::match_arm_list(arms).indent(ast::edit::IndentLevel(1)); - Some(make::expr_stmt(make::expr_match(match_target, list).into()).into()) - } + let list = make.match_arm_list(arms).indent(ast::edit::IndentLevel(1)); + Some(make.expr_stmt(make.expr_match(match_target, list).into()).into()) + }; - fn gen_partial_cmp_call(lhs: ast::Expr, rhs: ast::Expr) -> ast::Expr { - let rhs = make::expr_ref(rhs, false); - let method = make::name_ref("partial_cmp"); - make::expr_method_call(lhs, method, make::arg_list(Some(rhs))).into() - } + let gen_partial_cmp_call = |lhs: ast::Expr, rhs: ast::Expr| -> ast::Expr { + let rhs = make.expr_ref(rhs, false); + let method = make.name_ref("partial_cmp"); + make.expr_method_call(lhs, method, make.arg_list([rhs])).into() + }; // Check that self type and rhs type match. We don't know how to implement the method // automatically otherwise. @@ -643,10 +655,10 @@ fn gen_partial_cmp_call(lhs: ast::Expr, rhs: ast::Expr) -> ast::Expr { Some(ast::FieldList::RecordFieldList(field_list)) => { let mut exprs = vec![]; for field in field_list.fields() { - let lhs = make::expr_path(make::ext::ident_path("self")); - let lhs = make::expr_field(lhs, &field.name()?.to_string()); - let rhs = make::expr_path(make::ext::ident_path("other")); - let rhs = make::expr_field(rhs, &field.name()?.to_string()); + let lhs = make.expr_path(make.ident_path("self")); + let lhs = make.expr_field(lhs, &field.name()?.to_string()).into(); + let rhs = make.expr_path(make.ident_path("other")); + let rhs = make.expr_field(rhs, &field.name()?.to_string()).into(); let ord = gen_partial_cmp_call(lhs, rhs); exprs.push(ord); } @@ -656,17 +668,17 @@ fn gen_partial_cmp_call(lhs: ast::Expr, rhs: ast::Expr) -> ast::Expr { .into_iter() .map(gen_partial_eq_match) .collect::>>()?; - make::block_expr(stmts, tail).indent(ast::edit::IndentLevel(1)) + make.block_expr(stmts, tail).indent(ast::edit::IndentLevel(1)) } Some(ast::FieldList::TupleFieldList(field_list)) => { let mut exprs = vec![]; for (i, _) in field_list.fields().enumerate() { let idx = format!("{i}"); - let lhs = make::expr_path(make::ext::ident_path("self")); - let lhs = make::expr_field(lhs, &idx); - let rhs = make::expr_path(make::ext::ident_path("other")); - let rhs = make::expr_field(rhs, &idx); + let lhs = make.expr_path(make.ident_path("self")); + let lhs = make.expr_field(lhs, &idx).into(); + let rhs = make.expr_path(make.ident_path("other")); + let rhs = make.expr_field(rhs, &idx).into(); let ord = gen_partial_cmp_call(lhs, rhs); exprs.push(ord); } @@ -675,13 +687,13 @@ fn gen_partial_cmp_call(lhs: ast::Expr, rhs: ast::Expr) -> ast::Expr { .into_iter() .map(gen_partial_eq_match) .collect::>>()?; - make::block_expr(stmts, tail).indent(ast::edit::IndentLevel(1)) + make.block_expr(stmts, tail).indent(ast::edit::IndentLevel(1)) } // No fields in the body means there's nothing to compare. None => { - let expr = make::expr_literal("true").into(); - make::block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)) + let expr = make.expr_literal("true").into(); + make.block_expr(None, Some(expr)).indent(ast::edit::IndentLevel(1)) } }, }; @@ -689,6 +701,6 @@ fn gen_partial_cmp_call(lhs: ast::Expr, rhs: ast::Expr) -> ast::Expr { Some(body) } -fn make_discriminant() -> Option { - Some(make::expr_path(make::ext::path_from_idents(["core", "mem", "discriminant"])?)) +fn make_discriminant(make: &SyntaxFactory) -> Option { + Some(make.expr_path(make.path_from_idents(["core", "mem", "discriminant"])?)) } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions.rs index 1fb1fd4e579d..9a09e9bd4a20 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions.rs @@ -34,7 +34,7 @@ CompletionContext, CompletionItem, CompletionItemKind, context::{ DotAccess, ItemListKind, NameContext, NameKind, NameRefContext, NameRefKind, - PathCompletionCtx, PathKind, PatternContext, TypeLocation, Visible, + PathCompletionCtx, PathKind, PatternContext, TypeAscriptionTarget, TypeLocation, Visible, }, item::Builder, render::{ @@ -45,7 +45,7 @@ macro_::render_macro, pattern::{render_struct_pat, render_variant_pat}, render_expr, render_field, render_path_resolution, render_pattern_resolution, - render_tuple_field, + render_tuple_field, render_type_keyword_snippet, type_alias::{render_type_alias, render_type_alias_with_eq}, union_literal::render_union_literal, }, @@ -104,6 +104,21 @@ pub(crate) fn add_nameref_keywords_with_colon(&mut self, ctx: &CompletionContext } } + pub(crate) fn add_nameref_keywords_with_type_like( + &mut self, + ctx: &CompletionContext<'_>, + path_ctx: &PathCompletionCtx<'_>, + ) { + let mut add_keyword = |kw| { + render_type_keyword_snippet(ctx, path_ctx, kw, kw).add_to(self, ctx.db); + }; + ["self::", "crate::"].into_iter().for_each(&mut add_keyword); + + if ctx.depth_from_crate_root > 0 { + add_keyword("super::"); + } + } + pub(crate) fn add_nameref_keywords(&mut self, ctx: &CompletionContext<'_>) { ["self", "crate"].into_iter().for_each(|kw| self.add_keyword(ctx, kw)); @@ -112,11 +127,19 @@ pub(crate) fn add_nameref_keywords(&mut self, ctx: &CompletionContext<'_>) { } } - pub(crate) fn add_type_keywords(&mut self, ctx: &CompletionContext<'_>) { - self.add_keyword_snippet(ctx, "fn", "fn($1)"); - self.add_keyword_snippet(ctx, "dyn", "dyn $0"); - self.add_keyword_snippet(ctx, "impl", "impl $0"); - self.add_keyword_snippet(ctx, "for", "for<$1>"); + pub(crate) fn add_type_keywords( + &mut self, + ctx: &CompletionContext<'_>, + path_ctx: &PathCompletionCtx<'_>, + ) { + let mut add_keyword = |kw, snippet| { + render_type_keyword_snippet(ctx, path_ctx, kw, snippet).add_to(self, ctx.db); + }; + + add_keyword("fn", "fn($1)"); + add_keyword("dyn", "dyn $0"); + add_keyword("impl", "impl $0"); + add_keyword("for", "for<$1>"); } pub(crate) fn add_super_keyword( @@ -733,7 +756,7 @@ pub(super) fn complete_name_ref( match &path_ctx.kind { PathKind::Expr { expr_ctx } => { expr::complete_expr_path(acc, ctx, path_ctx, expr_ctx); - expr::complete_expr(acc, ctx); + expr::complete_expr(acc, ctx, path_ctx); dot::complete_undotted_self(acc, ctx, path_ctx, expr_ctx); item_list::complete_item_list_in_expr(acc, ctx, path_ctx, expr_ctx); @@ -747,6 +770,12 @@ pub(super) fn complete_name_ref( field::complete_field_list_tuple_variant(acc, ctx, path_ctx); } TypeLocation::TypeAscription(ascription) => { + if let TypeAscriptionTarget::RetType { item: Some(item), .. } = + ascription + && path_ctx.required_thin_arrow().is_some() + { + keyword::complete_for_and_where(acc, ctx, &item.clone().into()); + } r#type::complete_ascribed_type(acc, ctx, path_ctx, ascription); } TypeLocation::GenericArg { .. } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/attribute.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/attribute.rs index 20776f6c49f6..da1e664f961c 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/attribute.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/attribute.rs @@ -30,6 +30,7 @@ mod macro_use; mod repr; +pub(crate) use self::cfg::complete_cfg; pub(crate) use self::derive::complete_derive_path; /// Complete inputs to known builtin attributes as well as derive attributes @@ -37,7 +38,7 @@ pub(crate) fn complete_known_attribute_input( acc: &mut Completions, ctx: &CompletionContext<'_>, &colon_prefix: &bool, - fake_attribute_under_caret: &ast::Attr, + fake_attribute_under_caret: &ast::TokenTreeMeta, extern_crate: Option<&ast::ExternCrate>, ) -> Option<()> { let attribute = fake_attribute_under_caret; @@ -70,7 +71,6 @@ pub(crate) fn complete_known_attribute_input( lint::complete_lint(acc, ctx, colon_prefix, &existing_lints, &lints); } - ["cfg"] | ["cfg_attr"] => cfg::complete_cfg(acc, ctx), ["macro_use"] => macro_use::complete_macro_use( acc, ctx, diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/env_vars.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/env_vars.rs index 92cbf411c1e3..885d1a30750f 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/env_vars.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/env_vars.rs @@ -51,11 +51,10 @@ pub(crate) fn complete_cargo_env_vars( original: &ast::String, expanded: &ast::String, ) -> Option<()> { - let is_in_env_expansion = ctx - .sema - .hir_file_for(&expanded.syntax().parent()?) - .macro_file() - .is_some_and(|it| it.is_env_or_option_env(ctx.sema.db)); + let descends = ctx.sema.descend_into_macros_exact_with_file(original.syntax().clone()); + let macro_file = descends.first()?.file_id.macro_file(); + + let is_in_env_expansion = macro_file.is_some_and(|it| it.is_env_or_option_env(ctx.sema.db)); if !is_in_env_expansion { let call = macro_call_for_string_token(expanded)?; let makro = ctx.sema.resolve_macro_call(&call)?; @@ -116,6 +115,47 @@ fn main() { ); } + #[test] + fn complete_in_expanded_env_macro() { + check_edit( + "CARGO_BIN_NAME", + r#" +//- minicore: env +macro_rules! bar { + ($($arg:tt)*) => { $($arg)* } +} + +fn main() { + let foo = bar!(env!("CA$0")); +} + "#, + r#" +macro_rules! bar { + ($($arg:tt)*) => { $($arg)* } +} + +fn main() { + let foo = bar!(env!("CARGO_BIN_NAME")); +} + "#, + ); + + check_edit( + "CARGO_BIN_NAME", + r#" +//- minicore: env, fmt +fn main() { + let foo = format_args!("{}", env!("CA$0")); +} + "#, + r#" +fn main() { + let foo = format_args!("{}", env!("CARGO_BIN_NAME")); +} + "#, + ); + } + #[test] fn doesnt_complete_in_random_strings() { let fixture = r#" diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/expr.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/expr.rs index 8c532e0f4d04..99ca55bdaf74 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/expr.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/expr.rs @@ -451,7 +451,11 @@ pub(crate) fn complete_expr_path( } } -pub(crate) fn complete_expr(acc: &mut Completions, ctx: &CompletionContext<'_>) { +pub(crate) fn complete_expr( + acc: &mut Completions, + ctx: &CompletionContext<'_>, + PathCompletionCtx { qualified, .. }: &PathCompletionCtx<'_>, +) { let _p = tracing::info_span!("complete_expr").entered(); if !ctx.config.enable_term_search { @@ -462,6 +466,10 @@ pub(crate) fn complete_expr(acc: &mut Completions, ctx: &CompletionContext<'_>) return; } + if !matches!(qualified, Qualified::No) { + return; + } + if let Some(ty) = &ctx.expected_type { // Ignore unit types as they are not very interesting if ty.is_unit() || ty.is_unknown() { diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/flyimport.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/flyimport.rs index 20d01485a45a..2cf87baf3307 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/flyimport.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/flyimport.rs @@ -133,9 +133,15 @@ pub(crate) fn import_on_the_fly_path( let potential_import_name = import_name(ctx); let qualifier = match qualified { Qualified::With { path, .. } => Some(path.clone()), - _ => None, + Qualified::TypeAnchor { .. } => return None, + Qualified::No | Qualified::Absolute => None, }; - let import_assets = import_assets_for_path(ctx, &potential_import_name, qualifier.clone())?; + let import_assets = import_assets_for_path( + ctx, + Some(&path_ctx.path), + &potential_import_name, + qualifier.clone(), + )?; import_on_the_fly( acc, @@ -160,7 +166,7 @@ pub(crate) fn import_on_the_fly_pat( } let potential_import_name = import_name(ctx); - let import_assets = import_assets_for_path(ctx, &potential_import_name, None)?; + let import_assets = import_assets_for_path(ctx, None, &potential_import_name, None)?; import_on_the_fly_pat_( acc, @@ -402,6 +408,7 @@ fn import_name(ctx: &CompletionContext<'_>) -> String { fn import_assets_for_path<'db>( ctx: &CompletionContext<'db>, + path: Option<&ast::Path>, potential_import_name: &str, qualifier: Option, ) -> Option> { @@ -411,6 +418,7 @@ fn import_assets_for_path<'db>( let fuzzy_name_length = potential_import_name.len(); let mut assets_for_path = ImportAssets::for_fuzzy_path( ctx.module, + path, qualifier, potential_import_name.to_owned(), &ctx.sema, diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix.rs index 5b91e7c456a5..82baf885ddc6 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix.rs @@ -310,7 +310,7 @@ pub(crate) fn complete_postfix( if let ast::Expr::Literal(literal) = dot_receiver.clone() && let Some(literal_text) = ast::String::cast(literal.token()) { - add_format_like_completions(acc, ctx, &dot_receiver_including_refs, cap, &literal_text); + add_format_like_completions(acc, ctx, dot_receiver, cap, &literal_text, semi); } postfix_snippet("return", "return expr", &format!("return {receiver_text}{semi}")) @@ -402,7 +402,7 @@ fn receiver_accessor(receiver: &ast::Expr) -> ast::Expr { .unwrap_or_else(|| receiver.clone()) } -/// Given an `initial_element`, tries to expand it to include deref(s), and then references. +/// Given an `initial_element`, tries to expand it to include deref(s), not(s), and then references. /// Returns the expanded expressions, and the added prefix as a string /// /// For example, if called with the `42` in `&&mut *42`, would return `(&&mut *42, "&&mut *")`. @@ -410,22 +410,23 @@ fn include_references(initial_element: &ast::Expr) -> (ast::Expr, String) { let mut resulting_element = initial_element.clone(); let mut prefix = String::new(); - let mut found_ref_or_deref = false; - - while let Some(parent_deref_element) = - resulting_element.syntax().parent().and_then(ast::PrefixExpr::cast) - && parent_deref_element.op_kind() == Some(ast::UnaryOp::Deref) + while let Some(parent) = resulting_element.syntax().parent().and_then(ast::PrefixExpr::cast) + && parent.op_kind() == Some(ast::UnaryOp::Deref) { - found_ref_or_deref = true; - resulting_element = ast::Expr::from(parent_deref_element); - + resulting_element = ast::Expr::from(parent); prefix.insert(0, '*'); } + while let Some(parent) = resulting_element.syntax().parent().and_then(ast::PrefixExpr::cast) + && parent.op_kind() == Some(ast::UnaryOp::Not) + { + resulting_element = ast::Expr::from(parent); + prefix.insert(0, '!'); + } + while let Some(parent_ref_element) = resulting_element.syntax().parent().and_then(ast::RefExpr::cast) { - found_ref_or_deref = true; let last_child_or_token = parent_ref_element.syntax().last_child_or_token(); prefix.insert_str( 0, @@ -440,13 +441,6 @@ fn include_references(initial_element: &ast::Expr) -> (ast::Expr, String) { resulting_element = ast::Expr::from(parent_ref_element); } - if !found_ref_or_deref { - // If we do not find any ref/deref expressions, restore - // all the progress of tree climbing - prefix.clear(); - resulting_element = initial_element.clone(); - } - (resulting_element, prefix) } @@ -1132,6 +1126,27 @@ fn main() { ) } + #[test] + fn postfix_completion_for_nots() { + check_edit( + "if", + r#" +fn main() { + let is_foo = true; + !is_foo.$0 +} +"#, + r#" +fn main() { + let is_foo = true; + if !is_foo { + $0 +} +} +"#, + ) + } + #[test] fn postfix_completion_for_unsafe() { postfix_completion_for_block("unsafe"); @@ -1287,34 +1302,42 @@ fn postfix_completion_for_format_like_strings() { check_edit( "panic", r#"fn main() { "Panic with {a}".$0 }"#, - r#"fn main() { panic!("Panic with {a}") }"#, + r#"fn main() { panic!("Panic with {a}"); }"#, ); check_edit( "println", r#"fn main() { "{ 2+2 } { SomeStruct { val: 1, other: 32 } :?}".$0 }"#, - r#"fn main() { println!("{} {:?}", 2+2, SomeStruct { val: 1, other: 32 }) }"#, + r#"fn main() { println!("{} {:?}", 2+2, SomeStruct { val: 1, other: 32 }); }"#, ); check_edit( "loge", r#"fn main() { "{2+2}".$0 }"#, - r#"fn main() { log::error!("{}", 2+2) }"#, + r#"fn main() { log::error!("{}", 2+2); }"#, ); check_edit( "logt", r#"fn main() { "{2+2}".$0 }"#, - r#"fn main() { log::trace!("{}", 2+2) }"#, + r#"fn main() { log::trace!("{}", 2+2); }"#, ); check_edit( "logd", r#"fn main() { "{2+2}".$0 }"#, - r#"fn main() { log::debug!("{}", 2+2) }"#, + r#"fn main() { log::debug!("{}", 2+2); }"#, + ); + check_edit( + "logi", + r#"fn main() { "{2+2}".$0 }"#, + r#"fn main() { log::info!("{}", 2+2); }"#, + ); + check_edit( + "logw", + r#"fn main() { "{2+2}".$0 }"#, + r#"fn main() { log::warn!("{}", 2+2); }"#, ); - check_edit("logi", r#"fn main() { "{2+2}".$0 }"#, r#"fn main() { log::info!("{}", 2+2) }"#); - check_edit("logw", r#"fn main() { "{2+2}".$0 }"#, r#"fn main() { log::warn!("{}", 2+2) }"#); check_edit( "loge", r#"fn main() { "{2+2}".$0 }"#, - r#"fn main() { log::error!("{}", 2+2) }"#, + r#"fn main() { log::error!("{}", 2+2); }"#, ); } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix/format_like.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix/format_like.rs index 7faa1139595f..85a8899fd10b 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix/format_like.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/postfix/format_like.rs @@ -40,6 +40,7 @@ ("logw", "log::warn!"), ("loge", "log::error!"), ]; +static SNIPPET_RETURNS_NON_UNIT: &[&str] = &["format"]; pub(crate) fn add_format_like_completions( acc: &mut Completions, @@ -47,6 +48,7 @@ pub(crate) fn add_format_like_completions( dot_receiver: &ast::Expr, cap: SnippetCap, receiver_text: &ast::String, + semi: &str, ) { let postfix_snippet = match build_postfix_snippet_builder(ctx, cap, dot_receiver) { Some(it) => it, @@ -64,10 +66,11 @@ pub(crate) fn add_format_like_completions( let exprs = with_placeholders(exprs); for (label, macro_name) in KINDS { + let semi = if SNIPPET_RETURNS_NON_UNIT.contains(label) { "" } else { semi }; let snippet = if exprs.is_empty() { - format!(r#"{macro_name}({out})"#) + format!(r#"{macro_name}({out}){semi}"#) } else { - format!(r#"{}({}, {})"#, macro_name, out, exprs.join(", ")) + format!(r#"{}({}, {}){semi}"#, macro_name, out, exprs.join(", ")) }; postfix_snippet(label, macro_name, &snippet).add_to(acc, ctx.db); diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/ra_fixture.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/ra_fixture.rs index b44c90757f68..5a8881edc73e 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/ra_fixture.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/ra_fixture.rs @@ -22,7 +22,7 @@ pub(crate) fn complete_ra_fixture( &ctx.sema, original.clone(), expanded, - ctx.config.minicore, + &ctx.config.ra_fixture, &mut |_| {}, )?; let (virtual_file_id, virtual_offset) = analysis.map_offset_down(ctx.position.offset)?; diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/completions/type.rs b/src/tools/rust-analyzer/crates/ide-completion/src/completions/type.rs index 8ff9c3258e8e..e2125a967823 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/completions/type.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/completions/type.rs @@ -206,8 +206,8 @@ pub(crate) fn complete_type_path( _ => {} }; - acc.add_nameref_keywords_with_colon(ctx); - acc.add_type_keywords(ctx); + acc.add_nameref_keywords_with_type_like(ctx, path_ctx); + acc.add_type_keywords(ctx, path_ctx); ctx.process_all_names(&mut |name, def, doc_aliases| { if scope_def_applicable(def) { acc.add_path_resolution(ctx, path_ctx, name, def, doc_aliases); @@ -230,14 +230,14 @@ pub(crate) fn complete_ascribed_type( TypeAscriptionTarget::Let(pat) | TypeAscriptionTarget::FnParam(pat) => { ctx.sema.type_of_pat(pat.as_ref()?) } - TypeAscriptionTarget::Const(exp) | TypeAscriptionTarget::RetType(exp) => { + TypeAscriptionTarget::Const(exp) | TypeAscriptionTarget::RetType { body: exp, .. } => { ctx.sema.type_of_expr(exp.as_ref()?) } }? .adjusted(); if !ty.is_unknown() { let ty_string = ty.display_source_code(ctx.db, ctx.module.into(), true).ok()?; - acc.add(render_type_inference(ty_string, ctx)); + acc.add(render_type_inference(ty_string, ctx, path_ctx)); } None } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/config.rs b/src/tools/rust-analyzer/crates/ide-completion/src/config.rs index 5623257a2792..80c1572972ce 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/config.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/config.rs @@ -6,8 +6,9 @@ use hir::FindPathConfig; use ide_db::{ - MiniCore, SnippetCap, + SnippetCap, imports::{import_assets::ImportPathConfig, insert_use::InsertUseConfig}, + ra_fixture::RaFixtureConfig, }; use crate::{CompletionFieldsToResolve, snippet::Snippet}; @@ -35,7 +36,7 @@ pub struct CompletionConfig<'a> { pub fields_to_resolve: CompletionFieldsToResolve, pub exclude_flyimport: Vec<(String, AutoImportExclusionType)>, pub exclude_traits: &'a [String], - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } #[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)] diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/context.rs b/src/tools/rust-analyzer/crates/ide-completion/src/context.rs index 4fd0348156a5..485e5f0cafd7 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/context.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/context.rs @@ -6,7 +6,7 @@ use std::iter; -use base_db::RootQueryDb as _; +use base_db::toolchain_channel; use hir::{ DisplayTarget, HasAttrs, InFile, Local, ModuleDef, ModuleSource, Name, PathResolution, ScopeDef, Semantics, SemanticsScope, Symbol, Type, TypeInfo, @@ -102,6 +102,28 @@ pub(crate) fn is_trivial_path(&self) -> bool { } ) } + + pub(crate) fn required_thin_arrow(&self) -> Option<(&'static str, TextSize)> { + let PathKind::Type { + location: + TypeLocation::TypeAscription(TypeAscriptionTarget::RetType { + item: Some(ref fn_item), + .. + }), + } = self.kind + else { + return None; + }; + if fn_item.ret_type().is_some_and(|it| it.thin_arrow_token().is_some()) { + return None; + } + let ret_type = fn_item.ret_type().and_then(|it| it.ty()); + match (ret_type, fn_item.param_list()) { + (Some(ty), _) => Some(("-> ", ty.syntax().text_range().start())), + (None, Some(param)) => Some((" ->", param.syntax().text_range().end())), + (None, None) => None, + } + } } /// The kind of path we are completing right now. @@ -231,7 +253,7 @@ pub(crate) fn complete_self_type(&self) -> bool { pub(crate) enum TypeAscriptionTarget { Let(Option), FnParam(Option), - RetType(Option), + RetType { body: Option, item: Option }, Const(Option), } @@ -386,9 +408,11 @@ pub(crate) enum CompletionAnalysis<'db> { /// Set if we are currently completing in an unexpanded attribute, this usually implies a builtin attribute like `allow($0)` UnexpandedAttrTT { colon_prefix: bool, - fake_attribute_under_caret: Option, + fake_attribute_under_caret: Option, extern_crate: Option, }, + /// Set if we are inside the predicate of a #[cfg] or #[cfg_attr]. + CfgPredicate, MacroSegment, } @@ -715,7 +739,7 @@ pub(crate) fn new( // actual completion. let file_with_fake_ident = { let (_, edition) = editioned_file_id.unpack(db); - let parse = db.parse(editioned_file_id); + let parse = editioned_file_id.parse(db); parse.reparse(TextRange::empty(offset), COMPLETION_MARKER, edition).tree() }; @@ -768,7 +792,7 @@ pub(crate) fn new( let containing_function = scope.containing_function(); let edition = krate.edition(db); - let toolchain = db.toolchain_channel(krate.into()); + let toolchain = toolchain_channel(db, krate.into()); // `toolchain == None` means we're in some detached files. Since we have no information on // the toolchain being used, let's just allow unstable items to be listed. let is_nightly = matches!(toolchain, Some(base_db::ReleaseChannel::Nightly) | None); diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/context/analysis.rs b/src/tools/rust-analyzer/crates/ide-completion/src/context/analysis.rs index a3494b964f89..2a293313f2c9 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/context/analysis.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/context/analysis.rs @@ -284,9 +284,12 @@ fn expand( }; // Expand pseudo-derive expansion aka `derive(Debug$0)` - if let Some((orig_attr, spec_attr)) = attrs { + if let Some((orig_attr, spec_attr)) = attrs + && let Some(orig_meta) = orig_attr.meta() + { + // FIXME: Support speculative expansion with `cfg_attr`. if let (Some(actual_expansion), Some((fake_expansion, fake_mapped_tokens))) = ( - sema.expand_derive_as_pseudo_attr_macro(&orig_attr), + sema.expand_derive_as_pseudo_attr_macro(&orig_meta), sema.speculative_expand_derive_as_pseudo_attr_macro( &orig_attr, &spec_attr, @@ -463,7 +466,9 @@ fn analyze<'db>( } // Overwrite the path kind for derives - if let Some((original_file, file_with_fake_ident, offset, origin_attr)) = derive_ctx { + if let Some((original_file, file_with_fake_ident, offset, origin_attr)) = derive_ctx + && let Some(origin_meta) = origin_attr.meta() + { if let Some(ast::NameLike::NameRef(name_ref)) = find_node_at_offset(&file_with_fake_ident, offset) { @@ -473,7 +478,7 @@ fn analyze<'db>( if let NameRefKind::Path(path_ctx) = &mut nameref_ctx.kind { path_ctx.kind = PathKind::Derive { existing_derives: sema - .resolve_derive_macro(&origin_attr) + .resolve_derive_macro(&origin_meta) .into_iter() .flatten() .flatten() @@ -498,7 +503,7 @@ fn analyze<'db>( let token = syntax::algo::skip_trivia_token(self_token.clone(), Direction::Prev)?; let p = token.parent()?; if p.kind() == SyntaxKind::TOKEN_TREE - && p.ancestors().any(|it| it.kind() == SyntaxKind::META) + && p.ancestors().any(|it| it.kind() == SyntaxKind::TOKEN_TREE_META) { let colon_prefix = previous_non_trivia_token(self_token.clone()) .is_some_and(|it| T![:] == it.kind()); @@ -506,7 +511,7 @@ fn analyze<'db>( CompletionAnalysis::UnexpandedAttrTT { fake_attribute_under_caret: fake_ident_token .parent_ancestors() - .find_map(ast::Attr::cast), + .find_map(ast::TokenTreeMeta::cast), colon_prefix, extern_crate: p.ancestors().find_map(ast::ExternCrate::cast), } @@ -525,6 +530,13 @@ fn analyze<'db>( } else { return None; } + } else if find_node_at_offset::( + &speculative_file, + speculative_offset, + ) + .is_some() + { + CompletionAnalysis::CfgPredicate } else { return None; } @@ -827,6 +839,19 @@ fn expected_type_and_name<'db>( .map(|c| (Some(c.return_type()), None)) .unwrap_or((None, None)) }, + ast::Variant(it) => { + let is_simple_field = |field: ast::TupleField| { + let Some(ty) = field.ty() else { return true }; + matches!(ty, ast::Type::PathType(_)) && ty.generic_arg_list().is_none() + }; + let is_simple_variant = matches!( + it.field_list(), + Some(ast::FieldList::TupleFieldList(list)) + if list.syntax().children_with_tokens().all(|it| it.kind() != T![,]) + && list.fields().next().is_none_or(is_simple_field) + ); + (None, it.name().filter(|_| is_simple_variant).map(NameOrNameRef::Name)) + }, ast::Stmt(_) => (None, None), ast::Item(_) => (None, None), _ => { @@ -1265,15 +1290,14 @@ fn classify_name_ref<'db>( let original = ast::Static::cast(name.syntax().parent()?)?; TypeLocation::TypeAscription(TypeAscriptionTarget::Const(original.body())) }, - ast::RetType(it) => { - it.thin_arrow_token()?; + ast::RetType(_) => { let parent = match ast::Fn::cast(parent.parent()?) { Some(it) => it.param_list(), None => ast::ClosureExpr::cast(parent.parent()?)?.param_list(), }; let parent = find_opt_node_in_file(original_file, parent)?.syntax().parent()?; - TypeLocation::TypeAscription(TypeAscriptionTarget::RetType(match_ast! { + let body = match_ast! { match parent { ast::ClosureExpr(it) => { it.body() @@ -1283,7 +1307,9 @@ fn classify_name_ref<'db>( }, _ => return None, } - })) + }; + let item = ast::Fn::cast(parent); + TypeLocation::TypeAscription(TypeAscriptionTarget::RetType { body, item }) }, ast::Param(it) => { it.colon_token()?; diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/item.rs b/src/tools/rust-analyzer/crates/ide-completion/src/item.rs index 1a9139d8553b..e6dd1d37d933 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/item.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/item.rs @@ -450,6 +450,7 @@ pub(crate) fn new( ref_match: None, imports_to_add: Default::default(), doc_aliases: vec![], + adds_text: None, edition, } } @@ -480,12 +481,13 @@ pub fn ref_match(&self) -> Option<(String, ide_db::text_edit::Indel, CompletionR /// A helper to make `CompletionItem`s. #[must_use] -#[derive(Clone)] +#[derive(Debug, Clone)] pub(crate) struct Builder { source_range: TextRange, imports_to_add: SmallVec<[LocatedImport; 1]>, trait_name: Option, doc_aliases: Vec, + adds_text: Option, label: SmolStr, insert_text: Option, is_snippet: bool, @@ -526,9 +528,16 @@ pub(crate) fn build(self, db: &RootDatabase) -> CompletionItem { let insert_text = self.insert_text.unwrap_or_else(|| label.to_string()); let mut detail_left = None; + let mut to_detail_left = |args: fmt::Arguments<'_>| { + let detail_left = detail_left.get_or_insert_with(String::new); + if !detail_left.is_empty() { + detail_left.push(' '); + } + format_to!(detail_left, "{args}") + }; if !self.doc_aliases.is_empty() { let doc_aliases = self.doc_aliases.iter().join(", "); - detail_left = Some(format!("(alias {doc_aliases})")); + to_detail_left(format_args!("(alias {doc_aliases})")); let lookup_doc_aliases = self .doc_aliases .iter() @@ -548,22 +557,17 @@ pub(crate) fn build(self, db: &RootDatabase) -> CompletionItem { lookup = format_smolstr!("{lookup}{lookup_doc_aliases}"); } } + if let Some(adds_text) = self.adds_text { + to_detail_left(format_args!("(adds {})", adds_text.trim())); + } if let [import_edit] = &*self.imports_to_add { // snippets can have multiple imports, but normal completions only have up to one - let detail_left = detail_left.get_or_insert_with(String::new); - format_to!( - detail_left, - "{}(use {})", - if detail_left.is_empty() { "" } else { " " }, + to_detail_left(format_args!( + "(use {})", import_edit.import_path.display(db, self.edition) - ); + )); } else if let Some(trait_name) = self.trait_name { - let detail_left = detail_left.get_or_insert_with(String::new); - format_to!( - detail_left, - "{}(as {trait_name})", - if detail_left.is_empty() { "" } else { " " }, - ); + to_detail_left(format_args!("(as {trait_name})")); } let text_edit = match self.text_edit { @@ -613,6 +617,10 @@ pub(crate) fn doc_aliases(&mut self, doc_aliases: Vec) -> &mut Builder self.doc_aliases = doc_aliases; self } + pub(crate) fn adds_text(&mut self, adds_text: SmolStr) -> &mut Builder { + self.adds_text = Some(adds_text); + self + } pub(crate) fn insert_text(&mut self, insert_text: impl Into) -> &mut Builder { self.insert_text = Some(insert_text.into()); self diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/lib.rs b/src/tools/rust-analyzer/crates/ide-completion/src/lib.rs index 69ca2af7721b..3867e65ae57e 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/lib.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/lib.rs @@ -263,6 +263,7 @@ pub fn completions( extern_crate.as_ref(), ); } + CompletionAnalysis::CfgPredicate => completions::attribute::complete_cfg(acc, ctx), CompletionAnalysis::MacroSegment => { completions::macro_def::complete_macro_segment(acc, ctx); } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/render.rs b/src/tools/rust-analyzer/crates/ide-completion/src/render.rs index d77e79329541..b6da6fba638f 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/render.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/render.rs @@ -220,13 +220,15 @@ pub(crate) fn render_tuple_field( pub(crate) fn render_type_inference( ty_string: String, ctx: &CompletionContext<'_>, + path_ctx: &PathCompletionCtx<'_>, ) -> CompletionItem { let mut builder = CompletionItem::new( CompletionItemKind::InferredType, ctx.source_range(), - ty_string, + &ty_string, ctx.edition, ); + adds_ret_type_arrow(ctx, path_ctx, &mut builder, ty_string); builder.set_relevance(CompletionRelevance { type_match: Some(CompletionRelevanceTypeMatch::Exact), exact_name_match: true, @@ -425,11 +427,10 @@ fn render_resolution_path( let config = completion.config; let requires_import = import_to_add.is_some(); - let name = local_name.display_no_db(ctx.completion.edition).to_smolstr(); + let name = local_name.display(db, completion.edition).to_smolstr(); let mut item = render_resolution_simple_(ctx, &local_name, import_to_add, resolution); - if local_name.needs_escape(completion.edition) { - item.insert_text(local_name.display_no_db(completion.edition).to_smolstr()); - } + let mut insert_text = name.clone(); + // Add `<>` for generic types let type_path_no_ty_args = matches!( path_ctx, @@ -446,12 +447,14 @@ fn render_resolution_path( if has_non_default_type_params { cov_mark::hit!(inserts_angle_brackets_for_generics); + insert_text = format_smolstr!("{insert_text}<$0>"); item.lookup_by(name.clone()) .label(SmolStr::from_iter([&name, "<…>"])) .trigger_call_info() - .insert_snippet(cap, format!("{}<$0>", local_name.display(db, completion.edition))); + .insert_snippet(cap, ""); // set is snippet } } + adds_ret_type_arrow(completion, path_ctx, &mut item, insert_text.into()); let mut set_item_relevance = |ty: Type<'_>| { if !ty.is_unknown() { @@ -577,6 +580,48 @@ fn scope_def_is_deprecated(ctx: &RenderContext<'_>, resolution: ScopeDef) -> boo } } +pub(crate) fn render_type_keyword_snippet( + ctx: &CompletionContext<'_>, + path_ctx: &PathCompletionCtx<'_>, + label: &str, + snippet: &str, +) -> Builder { + let source_range = ctx.source_range(); + let mut item = + CompletionItem::new(CompletionItemKind::Keyword, source_range, label, ctx.edition); + + let insert_text = if !snippet.contains('$') { + item.insert_text(snippet); + snippet + } else if let Some(cap) = ctx.config.snippet_cap { + item.insert_snippet(cap, snippet); + snippet + } else { + label + }; + + adds_ret_type_arrow(ctx, path_ctx, &mut item, insert_text.to_owned()); + item +} + +fn adds_ret_type_arrow( + ctx: &CompletionContext<'_>, + path_ctx: &PathCompletionCtx<'_>, + item: &mut Builder, + insert_text: String, +) { + if let Some((arrow, at)) = path_ctx.required_thin_arrow() { + let mut edit = TextEdit::builder(); + + edit.insert(at, arrow.to_owned()); + edit.replace(ctx.source_range(), insert_text); + + item.text_edit(edit.finish()).adds_text(SmolStr::new_static(arrow)); + } else { + item.insert_text(insert_text); + } +} + // FIXME: This checks types without possible coercions which some completions might want to do fn match_types( ctx: &CompletionContext<'_>, @@ -2166,7 +2211,6 @@ fn bb()-> &'static aa { } "#, expect![[r#" - ex bb() [type] fn from_bytes(…) fn(&[u8]) -> &aa [type_could_unify] "#]], ); @@ -3044,6 +3088,57 @@ fn main() { ); } + #[test] + fn enum_variant_name_exact_match_is_high_priority() { + check_relevance( + r#" +struct Other; +struct String; +enum Foo { + String($0) +} + "#, + expect![[r#" + st String String [name] + en Foo Foo [] + st Other Other [] + sp Self Foo [] + "#]], + ); + + check_relevance( + r#" +struct Other; +struct String; +enum Foo { + String(String, $0) +} + "#, + expect![[r#" + en Foo Foo [] + st Other Other [] + sp Self Foo [] + st String String [] + "#]], + ); + + check_relevance( + r#" +struct Other; +struct Vec(T); +enum Foo { + Vec(Vec<$0>) +} + "#, + expect![[r#" + en Foo Foo [] + st Other Other [] + sp Self Foo [] + st Vec<…> Vec<{unknown}> [] + "#]], + ); + } + #[test] fn postfix_inexact_match_is_low_priority() { cov_mark::check!(postfix_inexact_match_is_low_priority); diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests.rs index cb1adfcfb65e..02e299b2a9c1 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests.rs @@ -29,8 +29,9 @@ use hir::db::HirDatabase; use hir::{PrefixKind, setup_tracing}; use ide_db::{ - FilePosition, MiniCore, RootDatabase, SnippetCap, + FilePosition, RootDatabase, SnippetCap, imports::insert_use::{ImportGranularity, InsertUseConfig}, + ra_fixture::RaFixtureConfig, }; use itertools::Itertools; use stdx::{format_to, trim_indent}; @@ -90,7 +91,7 @@ union Union { field: i32 } exclude_traits: &[], enable_auto_await: true, enable_auto_iter: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; pub(crate) fn completion_list(#[rust_analyzer::rust_fixture] ra_fixture: &str) -> String { diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests/expression.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests/expression.rs index 8e50ef10eca6..4a5983097a12 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests/expression.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests/expression.rs @@ -1030,8 +1030,6 @@ fn main() { "#, expect![[r#" fn test() fn() -> Zulu - ex Zulu - ex Zulu::test() "#]], ); } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests/flyimport.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests/flyimport.rs index d7db896679df..5391e6c9ce6e 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests/flyimport.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests/flyimport.rs @@ -1242,6 +1242,39 @@ impl Bar for Foo { ); } +#[test] +fn no_flyimports_type_anchor() { + check( + r#" +mod m { + pub fn foo() {} +} +struct Bar; +trait Foo {} +impl Foo for Bar {} +fn main() { + ::foo$0 +} + "#, + expect![[r#""#]], + ); + + check( + r#" +mod m { + pub fn foo() {} +} +struct Bar; +trait Foo {} +impl Foo for Bar {} +fn main() { + ::foo$0 +} + "#, + expect![[r#""#]], + ); +} + #[test] fn no_inherent_candidates_proposed() { check( diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests/item.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests/item.rs index 61a9da8c278a..2f032c3f4ca5 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests/item.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests/item.rs @@ -116,8 +116,23 @@ fn completes_where() { check_with_base_items( r"fn func() $0", expect![[r#" - kw where - "#]], + en Enum (adds ->) Enum + ma makro!(…) macro_rules! makro + md module (adds ->) + st Record (adds ->) Record + st Tuple (adds ->) Tuple + st Unit (adds ->) Unit + tt Trait (adds ->) + un Union (adds ->) Union + bt u32 (adds ->) u32 + kw crate:: (adds ->) + kw dyn (adds ->) + kw fn (adds ->) + kw for (adds ->) + kw impl (adds ->) + kw self:: (adds ->) + kw where + "#]], ); check_with_base_items( r"enum Enum $0", @@ -243,6 +258,19 @@ impl Copy for S where $0 ); } +#[test] +fn fn_item_where_kw() { + check_edit( + "where", + r#" +fn foo() $0 +"#, + r#" +fn foo() where $0 +"#, + ); +} + #[test] fn test_is_not_considered_macro() { check_with_base_items( diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests/special.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests/special.rs index b82b23541c5c..55059a4035e7 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests/special.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests/special.rs @@ -896,9 +896,6 @@ fn bar() -> Bar { "#, expect![[r#" fn foo() (as Foo) fn() -> Self - ex Bar - ex Bar::foo() - ex bar() "#]], ); } @@ -926,9 +923,6 @@ fn bar() -> Bar { expect![[r#" fn bar() fn() fn foo() (as Foo) fn() -> Self - ex Bar - ex Bar::foo() - ex bar() "#]], ); } @@ -955,9 +949,6 @@ fn bar() -> Bar { "#, expect![[r#" fn foo() (as Foo) fn() -> Self - ex Bar - ex Bar::foo() - ex bar() "#]], ); } diff --git a/src/tools/rust-analyzer/crates/ide-completion/src/tests/type_pos.rs b/src/tools/rust-analyzer/crates/ide-completion/src/tests/type_pos.rs index 7c6b7370aafd..7d4a7fe6b887 100644 --- a/src/tools/rust-analyzer/crates/ide-completion/src/tests/type_pos.rs +++ b/src/tools/rust-analyzer/crates/ide-completion/src/tests/type_pos.rs @@ -1,7 +1,7 @@ //! Completion tests for type position. use expect_test::expect; -use crate::tests::{check, check_with_base_items}; +use crate::tests::{check, check_edit, check_with_base_items}; #[test] fn record_field_ty() { @@ -93,6 +93,230 @@ fn x<'lt, T, const C: usize>() -> $0 ); } +#[test] +fn fn_return_type_missing_thin_arrow() { + check_with_base_items( + r#" +fn x() u$0 +"#, + expect![[r#" + en Enum (adds ->) Enum + ma makro!(…) macro_rules! makro + md module (adds ->) + st Record (adds ->) Record + st Tuple (adds ->) Tuple + st Unit (adds ->) Unit + tt Trait (adds ->) + un Union (adds ->) Union + bt u32 (adds ->) u32 + kw crate:: (adds ->) + kw dyn (adds ->) + kw fn (adds ->) + kw for (adds ->) + kw impl (adds ->) + kw self:: (adds ->) + kw where + "#]], + ); + + check_with_base_items( + r#" +fn x() $0 +"#, + expect![[r#" + en Enum (adds ->) Enum + ma makro!(…) macro_rules! makro + md module (adds ->) + st Record (adds ->) Record + st Tuple (adds ->) Tuple + st Unit (adds ->) Unit + tt Trait (adds ->) + un Union (adds ->) Union + bt u32 (adds ->) u32 + kw crate:: (adds ->) + kw dyn (adds ->) + kw fn (adds ->) + kw for (adds ->) + kw impl (adds ->) + kw self:: (adds ->) + kw where + "#]], + ); +} + +#[test] +fn fn_return_type_missing_thin_arrow_path_completion() { + check_edit( + "u32", + r#" +fn foo() u$0 +"#, + r#" +fn foo() -> u32 +"#, + ); + + check_edit( + "u32", + r#" +fn foo() $0 +"#, + r#" +fn foo() -> u32 +"#, + ); + + check_edit( + "Num", + r#" +type Num = u32; +fn foo() $0 +"#, + r#" +type Num = u32; +fn foo() -> Num +"#, + ); + + check_edit( + "impl", + r#" +fn foo() $0 +"#, + r#" +fn foo() -> impl $0 +"#, + ); + + check_edit( + "foo", + r#" +mod foo { pub type Num = u32; } +fn foo() $0 +"#, + r#" +mod foo { pub type Num = u32; } +fn foo() -> foo +"#, + ); + + check_edit( + "crate::", + r#" +mod foo { pub type Num = u32; } +fn foo() $0 +"#, + r#" +mod foo { pub type Num = u32; } +fn foo() -> crate:: +"#, + ); + + check_edit( + "Num", + r#" +mod foo { pub type Num = u32; } +fn foo() foo::$0 +"#, + r#" +mod foo { pub type Num = u32; } +fn foo() -> foo::Num +"#, + ); + + // no spaces, test edit order + check_edit( + "foo", + r#" +mod foo { pub type Num = u32; } +fn foo()$0 +"#, + r#" +mod foo { pub type Num = u32; } +fn foo() ->foo +"#, + ); +} + +#[test] +fn fn_return_type_missing_thin_arrow_path_completion_with_generic_args() { + check_edit( + "Foo", + r#" +struct Foo(T); +fn foo() F$0 +"#, + r#" +struct Foo(T); +fn foo() -> Foo<$0> +"#, + ); + + check_edit( + "Foo", + r#" +struct Foo(T); +fn foo() $0 +"#, + r#" +struct Foo(T); +fn foo() -> Foo<$0> +"#, + ); + + check_edit( + "Foo", + r#" +type Foo = T; +fn foo() $0 +"#, + r#" +type Foo = T; +fn foo() -> Foo<$0> +"#, + ); +} + +#[test] +fn fn_return_type_missing_thin_arrow_infer_ref_type() { + check_with_base_items( + r#" +fn x() u$0 {&2u32} +"#, + expect![[r#" + en Enum (adds ->) Enum + ma makro!(…) macro_rules! makro + md module (adds ->) + st Record (adds ->) Record + st Tuple (adds ->) Tuple + st Unit (adds ->) Unit + tt Trait (adds ->) + un Union (adds ->) Union + bt u32 (adds ->) u32 + it &u32 (adds ->) + kw crate:: (adds ->) + kw dyn (adds ->) + kw fn (adds ->) + kw for (adds ->) + kw impl (adds ->) + kw self:: (adds ->) + kw where + "#]], + ); + + check_edit( + "&u32", + r#" +struct Foo(T); +fn x() u$0 {&2u32} +"#, + r#" +struct Foo(T); +fn x() -> &u32 {&2u32} +"#, + ); +} + #[test] fn fn_return_type_after_reference() { check_with_base_items( diff --git a/src/tools/rust-analyzer/crates/ide-db/src/generated/lints.rs b/src/tools/rust-analyzer/crates/ide-db/src/generated/lints.rs index 9e6d58600888..c25feceb4157 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/generated/lints.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/generated/lints.rs @@ -1,4 +1,4 @@ -//! Generated by `cargo codegen lint-definitions`, do not edit by hand. +//! Generated by `cargo xtask codegen lint-definitions`, do not edit by hand. use span::Edition; @@ -20,8 +20,8 @@ pub struct LintGroup { pub const DEFAULT_LINTS: &[Lint] = &[ Lint { - label: "abi_unsupported_vector_types", - description: r##"this function call or definition uses a vector type which is not enabled"##, + label: "aarch64_softfloat_neon", + description: r##"detects code that could be affected by ABI issues on aarch64 softfloat targets"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -40,10 +40,24 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "ambiguous_derive_helpers", + description: r##"detects derive helper attributes that are ambiguous with built-in attributes"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "ambiguous_glob_imported_traits", + description: r##"detects uses of ambiguously glob imported traits"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "ambiguous_glob_imports", description: r##"detects certain glob imports that require reporting an ambiguity error"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, deny_since: None, }, @@ -54,6 +68,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "ambiguous_import_visibilities", + description: r##"detects certain glob imports that require reporting an ambiguity error"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "ambiguous_negative_literals", description: r##"ambiguous negative literals operations"##, @@ -61,6 +82,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "ambiguous_panic_imports", + description: r##"detects ambiguous core and std panic imports"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "ambiguous_wide_pointer_comparisons", description: r##"detects ambiguous wide pointer comparisons"##, @@ -145,13 +173,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "cenum_impl_drop_cast", - description: r##"a C-like enum implementing Drop is cast"##, - default_severity: Severity::Error, - warn_since: None, - deny_since: None, - }, Lint { label: "clashing_extern_declarations", description: r##"detects when an extern fn has been declared with the same name but different types"##, @@ -194,6 +215,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "const_item_interior_mutations", + description: r##"checks for calls which mutates a interior mutable const-item"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "const_item_mutation", description: r##"detects attempts to mutate a `const` item"##, @@ -201,6 +229,20 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "dangerous_implicit_autorefs", + description: r##"implicit reference to a dereference of a raw pointer"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, + Lint { + label: "dangling_pointers_from_locals", + description: r##"detects returning a pointer from a local variable"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "dangling_pointers_from_temporaries", description: r##"detects getting a pointer from a temporary"##, @@ -215,10 +257,17 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "default_overrides_default_fields", + description: r##"detect `Default` impl that should use the type's default field values"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, Lint { label: "dependency_on_unit_never_type_fallback", description: r##"never type fallback affecting unsafe function calls"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, deny_since: None, }, @@ -252,14 +301,21 @@ pub struct LintGroup { }, Lint { label: "deref_into_dyn_supertrait", - description: r##"`Deref` implementation usage with a supertrait trait object for output might be shadowed in the future"##, - default_severity: Severity::Warning, + description: r##"`Deref` implementation with a supertrait trait object for output is shadowed by trait upcasting"##, + default_severity: Severity::Allow, warn_since: None, deny_since: None, }, Lint { label: "deref_nullptr", description: r##"detects when an null pointer is dereferenced"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, + Lint { + label: "double_negations", + description: r##"detects expressions of the form `--x`"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -285,6 +341,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "duplicate_features", + description: r##"duplicate features found in crate-level `#[feature]` directives"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, Lint { label: "duplicate_macro_attributes", description: r##"duplicated attribute"##, @@ -320,13 +383,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "elided_named_lifetimes", - description: r##"detects when an elided lifetime gets resolved to be `'static` or some named parameter"##, - default_severity: Severity::Warning, - warn_since: None, - deny_since: None, - }, Lint { label: "ellipsis_inclusive_range_patterns", description: r##"`...` range patterns are deprecated"##, @@ -397,6 +453,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "function_casts_as_integer", + description: r##"casting a function into an integer"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "function_item_references", description: r##"suggest casting to a function pointer when attempting to take references to function items"##, @@ -442,7 +505,7 @@ pub struct LintGroup { Lint { label: "impl_trait_redundant_captures", description: r##"redundant precise-capturing `use<...>` syntax on an `impl Trait`"##, - default_severity: Severity::Warning, + default_severity: Severity::Allow, warn_since: None, deny_since: None, }, @@ -460,6 +523,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "improper_gpu_kernel_arg", + description: r##"GPU kernel entry points have a limited ABI"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "incomplete_features", description: r##"incomplete features that may function improperly in some or all cases"##, @@ -481,9 +551,30 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "inline_always_mismatching_target_features", + description: r##"detects when a function annotated with `#[inline(always)]` and `#[target_feature(enable = "..")]` is inlined into a caller without the required target feature"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "inline_no_sanitize", - description: r##"detects incompatible use of `#[inline(always)]` and `#[no_sanitize(...)]`"##, + description: r##"detects incompatible use of `#[inline(always)]` and `#[sanitize(... = "off")]`"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "integer_to_ptr_transmutes", + description: r##"detects integer to pointer transmutes"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "internal_eq_trait_method_impls", + description: r##"manual implementation of the internal `Eq::assert_receiver_is_total_eq` method"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -505,7 +596,7 @@ pub struct LintGroup { Lint { label: "invalid_doc_attributes", description: r##"detects invalid `#[doc(...)]` attributes"##, - default_severity: Severity::Error, + default_severity: Severity::Warning, warn_since: None, deny_since: None, }, @@ -526,7 +617,7 @@ pub struct LintGroup { Lint { label: "invalid_macro_export_arguments", description: r##""invalid_parameter" isn't a valid argument for `#[macro_export]`"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, deny_since: None, }, @@ -537,6 +628,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "invalid_null_arguments", + description: r##"invalid null pointer in arguments"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, Lint { label: "invalid_reference_casting", description: r##"casts of `&T` to `&mut T` without interior mutability"##, @@ -596,7 +694,7 @@ pub struct LintGroup { Lint { label: "legacy_derive_helpers", description: r##"detects derive helper attributes that are used before they are introduced"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, deny_since: None, }, @@ -614,6 +712,20 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "linker_info", + description: r##"linker warnings known to be informational-only and not indicative of a problem"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "linker_messages", + description: r##"warnings emitted at runtime by the target-specific linker program"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, Lint { label: "long_running_const_eval", description: r##"detects long const eval operations"##, @@ -642,6 +754,20 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "malformed_diagnostic_attributes", + description: r##"detects malformed diagnostic attributes"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "malformed_diagnostic_format_literals", + description: r##"detects diagnostic attribute with malformed diagnostic format literals"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "map_unit_fn", description: r##"`Iterator::map` call that discard the iterator's values"##, @@ -656,10 +782,24 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "mismatched_lifetime_syntaxes", + description: r##"detects when a lifetime uses different syntax between arguments and return values"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "misplaced_diagnostic_attributes", + description: r##"detects diagnostic attributes that are placed on the wrong item"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "missing_abi", description: r##"No declared ABI for extern declaration"##, - default_severity: Severity::Allow, + default_severity: Severity::Warning, warn_since: None, deny_since: None, }, @@ -685,9 +825,9 @@ pub struct LintGroup { deny_since: None, }, Lint { - label: "missing_fragment_specifier", - description: r##"detects missing fragment specifiers in unused `macro_rules!` patterns"##, - default_severity: Severity::Error, + label: "missing_gpu_kernel_export_name", + description: r##"mangled gpu-kernel function"##, + default_severity: Severity::Warning, warn_since: None, deny_since: None, }, @@ -743,9 +883,9 @@ pub struct LintGroup { Lint { label: "never_type_fallback_flowing_into_unsafe", description: r##"never type fallback affecting unsafe function calls"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, - deny_since: Some(Edition::Edition2024), + deny_since: None, }, Lint { label: "no_mangle_const_items", @@ -838,17 +978,10 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "order_dependent_trait_objects", - description: r##"trait-object types were treated as different depending on marker-trait order"##, - default_severity: Severity::Error, - warn_since: None, - deny_since: None, - }, Lint { label: "out_of_scope_macro_calls", description: r##"detects out of scope calls to `macro_rules` in key-value attributes"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, warn_since: None, deny_since: None, }, @@ -901,13 +1034,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "ptr_cast_add_auto_to_object", - description: r##"detects `as` casts from pointers to `dyn Trait` to pointers to `dyn Trait + Auto`"##, - default_severity: Severity::Warning, - warn_since: None, - deny_since: None, - }, Lint { label: "ptr_to_integer_transmute_in_consts", description: r##"detects pointer to integer transmutes in const functions and associated constants"##, @@ -965,8 +1091,29 @@ pub struct LintGroup { deny_since: None, }, Lint { - label: "repr_transparent_external_private_fields", + label: "repr_c_enums_larger_than_int", + description: r##"repr(C) enums with discriminant values that do not fit into a C int"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "repr_transparent_non_zst_fields", description: r##"transparent type contains an external ZST that is marked #[non_exhaustive] or contains private fields"##, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, + Lint { + label: "resolving_to_items_shadowing_supertrait_items", + description: r##"detects when a supertrait item is shadowed by a subtrait item"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "rtsan_nonblocking_async", + description: r##"detects incompatible uses of `#[sanitize(realtime = "nonblocking")]` on async functions"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -1030,7 +1177,14 @@ pub struct LintGroup { Lint { label: "semicolon_in_expressions_from_macros", description: r##"trailing semicolon in macro body used as expression"##, - default_severity: Severity::Warning, + default_severity: Severity::Error, + warn_since: None, + deny_since: None, + }, + Lint { + label: "shadowing_supertrait_items", + description: r##"detects when a supertrait item is shadowed by a subtrait item"##, + default_severity: Severity::Allow, warn_since: None, deny_since: None, }, @@ -1041,13 +1195,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "soft_unstable", - description: r##"a feature gate that doesn't break dependent crates"##, - default_severity: Severity::Error, - warn_since: None, - deny_since: None, - }, Lint { label: "special_module_name", description: r##"module declarations for files with a special meaning"##, @@ -1064,7 +1211,7 @@ pub struct LintGroup { }, Lint { label: "static_mut_refs", - description: r##"shared references or mutable references of mutable static is discouraged"##, + description: r##"creating a shared reference to mutable static"##, default_severity: Severity::Warning, warn_since: None, deny_since: Some(Edition::Edition2024), @@ -1167,13 +1314,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "undefined_naked_function_abi", - description: r##"undefined naked function ABI"##, - default_severity: Severity::Warning, - warn_since: None, - deny_since: None, - }, Lint { label: "undropped_manually_drops", description: r##"calls to `std::mem::drop` with `std::mem::ManuallyDrop` instead of it's inner value"##, @@ -1224,15 +1364,15 @@ pub struct LintGroup { deny_since: None, }, Lint { - label: "unknown_lints", - description: r##"unrecognized lint attribute"##, + label: "unknown_diagnostic_attributes", + description: r##"detects unknown diagnostic attributes"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, }, Lint { - label: "unknown_or_malformed_diagnostic_attributes", - description: r##"unrecognized or malformed diagnostic attribute"##, + label: "unknown_lints", + description: r##"unrecognized lint attribute"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -1251,6 +1391,20 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "unnecessary_transmutes", + description: r##"detects transmutes that can also be achieved by other operations"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unpredictable_function_pointer_comparisons", + description: r##"detects unpredictable function pointer comparisons"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "unqualified_local_imports", description: r##"`use` of a local item without leading `self::`, `super::`, or `crate::`"##, @@ -1258,6 +1412,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "unreachable_cfg_select_predicates", + description: r##"detects unreachable configuration predicates in the cfg_select macro"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "unreachable_code", description: r##"detects unreachable code paths"##, @@ -1322,8 +1483,8 @@ pub struct LintGroup { deny_since: None, }, Lint { - label: "unsupported_fn_ptr_calling_conventions", - description: r##"use of unsupported calling convention for function pointer"##, + label: "unsupported_calling_conventions", + description: r##"use of unsupported calling convention"##, default_severity: Severity::Warning, warn_since: None, deny_since: None, @@ -1489,6 +1650,13 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "unused_visibilities", + description: r##"detect visibility qualifiers on `const _` items"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "useless_deprecated", description: r##"detects deprecation attributes with no effect"##, @@ -1503,6 +1671,20 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "uses_power_alignment", + description: r##"Structs do not follow the power alignment rule under repr(C)"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, + Lint { + label: "varargs_without_pattern", + description: r##"detects usage of `...` arguments without a pattern in non-foreign items"##, + default_severity: Severity::Warning, + warn_since: None, + deny_since: None, + }, Lint { label: "variant_size_differences", description: r##"detects enums with widely varying variant sizes"##, @@ -1517,13 +1699,6 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "wasm_c_abi", - description: r##"detects dependencies that are incompatible with the Wasm C ABI"##, - default_severity: Severity::Error, - warn_since: None, - deny_since: None, - }, Lint { label: "while_true", description: r##"suggest using `loop { }` instead of `while true { }`"##, @@ -1540,7 +1715,7 @@ pub struct LintGroup { }, Lint { label: "future_incompatible", - description: r##"lint group for: deref-into-dyn-supertrait, abi-unsupported-vector-types, ambiguous-associated-items, ambiguous-glob-imports, cenum-impl-drop-cast, coherence-leak-check, conflicting-repr-hints, const-evaluatable-unchecked, elided-lifetimes-in-associated-constant, forbidden-lint-groups, ill-formed-attribute-input, invalid-type-param-default, late-bound-lifetime-arguments, legacy-derive-helpers, macro-expanded-macro-exports-accessed-by-absolute-paths, missing-fragment-specifier, order-dependent-trait-objects, out-of-scope-macro-calls, patterns-in-fns-without-body, proc-macro-derive-resolution-fallback, ptr-cast-add-auto-to-object, pub-use-of-private-extern-crate, repr-transparent-external-private-fields, self-constructor-from-outer-item, semicolon-in-expressions-from-macros, soft-unstable, uncovered-param-in-projection, uninhabited-static, unstable-name-collisions, unstable-syntax-pre-expansion, unsupported-fn-ptr-calling-conventions, wasm-c-abi"##, + description: r##"lint group for: internal-eq-trait-method-impls, aarch64-softfloat-neon, ambiguous-associated-items, ambiguous-derive-helpers, ambiguous-glob-imported-traits, ambiguous-glob-imports, ambiguous-import-visibilities, ambiguous-panic-imports, coherence-leak-check, conflicting-repr-hints, const-evaluatable-unchecked, elided-lifetimes-in-associated-constant, forbidden-lint-groups, ill-formed-attribute-input, invalid-macro-export-arguments, invalid-type-param-default, late-bound-lifetime-arguments, legacy-derive-helpers, macro-expanded-macro-exports-accessed-by-absolute-paths, out-of-scope-macro-calls, patterns-in-fns-without-body, proc-macro-derive-resolution-fallback, pub-use-of-private-extern-crate, repr-c-enums-larger-than-int, repr-transparent-non-zst-fields, self-constructor-from-outer-item, semicolon-in-expressions-from-macros, uncovered-param-in-projection, uninhabited-static, unstable-name-collisions, unstable-syntax-pre-expansion, unsupported-calling-conventions, varargs-without-pattern"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, @@ -1601,9 +1776,16 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, + Lint { + label: "unknown_or_malformed_diagnostic_attributes", + description: r##"lint group for: malformed-diagnostic-attributes, malformed-diagnostic-format-literals, misplaced-diagnostic-attributes, unknown-diagnostic-attributes"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, Lint { label: "unused", - description: r##"lint group for: unused-imports, unused-variables, unused-assignments, dead-code, unused-mut, unreachable-code, unreachable-patterns, unused-must-use, unused-unsafe, path-statements, unused-attributes, unused-macros, unused-macro-rules, unused-allocation, unused-doc-comments, unused-extern-crates, unused-features, unused-labels, unused-parens, unused-braces, redundant-semicolons, map-unit-fn"##, + description: r##"lint group for: unused-imports, unused-variables, unused-visibilities, unused-assignments, dead-code, unused-mut, unreachable-code, unreachable-patterns, unused-must-use, unused-unsafe, path-statements, unused-attributes, unused-macros, unused-macro-rules, unused-allocation, unused-doc-comments, unused-extern-crates, unused-features, unused-labels, unused-parens, unused-braces, redundant-semicolons, map-unit-fn"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, @@ -1631,44 +1813,45 @@ pub struct LintGroup { LintGroup { lint: Lint { label: "future_incompatible", - description: r##"lint group for: deref-into-dyn-supertrait, abi-unsupported-vector-types, ambiguous-associated-items, ambiguous-glob-imports, cenum-impl-drop-cast, coherence-leak-check, conflicting-repr-hints, const-evaluatable-unchecked, elided-lifetimes-in-associated-constant, forbidden-lint-groups, ill-formed-attribute-input, invalid-type-param-default, late-bound-lifetime-arguments, legacy-derive-helpers, macro-expanded-macro-exports-accessed-by-absolute-paths, missing-fragment-specifier, order-dependent-trait-objects, out-of-scope-macro-calls, patterns-in-fns-without-body, proc-macro-derive-resolution-fallback, ptr-cast-add-auto-to-object, pub-use-of-private-extern-crate, repr-transparent-external-private-fields, self-constructor-from-outer-item, semicolon-in-expressions-from-macros, soft-unstable, uncovered-param-in-projection, uninhabited-static, unstable-name-collisions, unstable-syntax-pre-expansion, unsupported-fn-ptr-calling-conventions, wasm-c-abi"##, + description: r##"lint group for: internal-eq-trait-method-impls, aarch64-softfloat-neon, ambiguous-associated-items, ambiguous-derive-helpers, ambiguous-glob-imported-traits, ambiguous-glob-imports, ambiguous-import-visibilities, ambiguous-panic-imports, coherence-leak-check, conflicting-repr-hints, const-evaluatable-unchecked, elided-lifetimes-in-associated-constant, forbidden-lint-groups, ill-formed-attribute-input, invalid-macro-export-arguments, invalid-type-param-default, late-bound-lifetime-arguments, legacy-derive-helpers, macro-expanded-macro-exports-accessed-by-absolute-paths, out-of-scope-macro-calls, patterns-in-fns-without-body, proc-macro-derive-resolution-fallback, pub-use-of-private-extern-crate, repr-c-enums-larger-than-int, repr-transparent-non-zst-fields, self-constructor-from-outer-item, semicolon-in-expressions-from-macros, uncovered-param-in-projection, uninhabited-static, unstable-name-collisions, unstable-syntax-pre-expansion, unsupported-calling-conventions, varargs-without-pattern"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, }, children: &[ - "deref_into_dyn_supertrait", - "abi_unsupported_vector_types", + "internal_eq_trait_method_impls", + "aarch64_softfloat_neon", "ambiguous_associated_items", + "ambiguous_derive_helpers", + "ambiguous_glob_imported_traits", "ambiguous_glob_imports", - "cenum_impl_drop_cast", + "ambiguous_import_visibilities", + "ambiguous_panic_imports", "coherence_leak_check", "conflicting_repr_hints", "const_evaluatable_unchecked", "elided_lifetimes_in_associated_constant", "forbidden_lint_groups", "ill_formed_attribute_input", + "invalid_macro_export_arguments", "invalid_type_param_default", "late_bound_lifetime_arguments", "legacy_derive_helpers", "macro_expanded_macro_exports_accessed_by_absolute_paths", - "missing_fragment_specifier", - "order_dependent_trait_objects", "out_of_scope_macro_calls", "patterns_in_fns_without_body", "proc_macro_derive_resolution_fallback", - "ptr_cast_add_auto_to_object", "pub_use_of_private_extern_crate", - "repr_transparent_external_private_fields", + "repr_c_enums_larger_than_int", + "repr_transparent_non_zst_fields", "self_constructor_from_outer_item", "semicolon_in_expressions_from_macros", - "soft_unstable", "uncovered_param_in_projection", "uninhabited_static", "unstable_name_collisions", "unstable_syntax_pre_expansion", - "unsupported_fn_ptr_calling_conventions", - "wasm_c_abi", + "unsupported_calling_conventions", + "varargs_without_pattern", ], }, LintGroup { @@ -1788,10 +1971,25 @@ pub struct LintGroup { "unsafe_op_in_unsafe_fn", ], }, + LintGroup { + lint: Lint { + label: "unknown_or_malformed_diagnostic_attributes", + description: r##"lint group for: malformed-diagnostic-attributes, malformed-diagnostic-format-literals, misplaced-diagnostic-attributes, unknown-diagnostic-attributes"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + children: &[ + "malformed_diagnostic_attributes", + "malformed_diagnostic_format_literals", + "misplaced_diagnostic_attributes", + "unknown_diagnostic_attributes", + ], + }, LintGroup { lint: Lint { label: "unused", - description: r##"lint group for: unused-imports, unused-variables, unused-assignments, dead-code, unused-mut, unreachable-code, unreachable-patterns, unused-must-use, unused-unsafe, path-statements, unused-attributes, unused-macros, unused-macro-rules, unused-allocation, unused-doc-comments, unused-extern-crates, unused-features, unused-labels, unused-parens, unused-braces, redundant-semicolons, map-unit-fn"##, + description: r##"lint group for: unused-imports, unused-variables, unused-visibilities, unused-assignments, dead-code, unused-mut, unreachable-code, unreachable-patterns, unused-must-use, unused-unsafe, path-statements, unused-attributes, unused-macros, unused-macro-rules, unused-allocation, unused-doc-comments, unused-extern-crates, unused-features, unused-labels, unused-parens, unused-braces, redundant-semicolons, map-unit-fn"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, @@ -1799,6 +1997,7 @@ pub struct LintGroup { children: &[ "unused_imports", "unused_variables", + "unused_visibilities", "unused_assignments", "dead_code", "unused_mut", @@ -1901,16 +2100,9 @@ pub struct LintGroup { warn_since: None, deny_since: None, }, - Lint { - label: "rustdoc::unportable_markdown", - description: r##"detects markdown that is interpreted differently in different parser"##, - default_severity: Severity::Warning, - warn_since: None, - deny_since: None, - }, Lint { label: "rustdoc::all", - description: r##"lint group for: rustdoc::broken-intra-doc-links, rustdoc::private-intra-doc-links, rustdoc::private-doc-tests, rustdoc::invalid-codeblock-attributes, rustdoc::invalid-rust-codeblocks, rustdoc::invalid-html-tags, rustdoc::bare-urls, rustdoc::missing-crate-level-docs, rustdoc::unescaped-backticks, rustdoc::redundant-explicit-links, rustdoc::unportable-markdown"##, + description: r##"lint group for: rustdoc::broken-intra-doc-links, rustdoc::private-intra-doc-links, rustdoc::private-doc-tests, rustdoc::invalid-codeblock-attributes, rustdoc::invalid-rust-codeblocks, rustdoc::invalid-html-tags, rustdoc::bare-urls, rustdoc::missing-crate-level-docs, rustdoc::unescaped-backticks, rustdoc::redundant-explicit-links"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, @@ -1920,7 +2112,7 @@ pub struct LintGroup { pub const RUSTDOC_LINT_GROUPS: &[LintGroup] = &[LintGroup { lint: Lint { label: "rustdoc::all", - description: r##"lint group for: rustdoc::broken-intra-doc-links, rustdoc::private-intra-doc-links, rustdoc::private-doc-tests, rustdoc::invalid-codeblock-attributes, rustdoc::invalid-rust-codeblocks, rustdoc::invalid-html-tags, rustdoc::bare-urls, rustdoc::missing-crate-level-docs, rustdoc::unescaped-backticks, rustdoc::redundant-explicit-links, rustdoc::unportable-markdown"##, + description: r##"lint group for: rustdoc::broken-intra-doc-links, rustdoc::private-intra-doc-links, rustdoc::private-doc-tests, rustdoc::invalid-codeblock-attributes, rustdoc::invalid-rust-codeblocks, rustdoc::invalid-html-tags, rustdoc::bare-urls, rustdoc::missing-crate-level-docs, rustdoc::unescaped-backticks, rustdoc::redundant-explicit-links"##, default_severity: Severity::Allow, warn_since: None, deny_since: None, @@ -1936,7 +2128,6 @@ pub struct LintGroup { "rustdoc::missing_crate_level_docs", "rustdoc::unescaped_backticks", "rustdoc::redundant_explicit_links", - "rustdoc::unportable_markdown", ], }]; @@ -1945,9 +2136,11 @@ pub struct LintGroup { label: "aarch64_unstable_target_feature", description: r##"# `aarch64_unstable_target_feature` -The tracking issue for this feature is: [#44839] +The remaining unstable target features on aarch64. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150244] + +[#150244]: https://github.com/rust-lang/rust/issues/150244 ------------------------ "##, @@ -1959,9 +2152,11 @@ pub struct LintGroup { label: "aarch64_ver_target_feature", description: r##"# `aarch64_ver_target_feature` -The tracking issue for this feature is: [#44839] +Instruction set "version" target features on aarch64. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150245] + +[#150245]: https://github.com/rust-lang/rust/issues/150245 ------------------------ "##, @@ -1973,6 +2168,8 @@ pub struct LintGroup { label: "abi_avr_interrupt", description: r##"# `abi_avr_interrupt` +Allows `extern "avr-interrupt" fn()` and `extern "avr-non-blocking-interrupt" fn()`. + The tracking issue for this feature is: [#69664] [#69664]: https://github.com/rust-lang/rust/issues/69664 @@ -1984,8 +2181,8 @@ pub struct LintGroup { deny_since: None, }, Lint { - label: "abi_c_cmse_nonsecure_call", - description: r##"# `abi_c_cmse_nonsecure_call` + label: "abi_cmse_nonsecure_call", + description: r##"# `abi_cmse_nonsecure_call` The tracking issue for this feature is: [#81391] @@ -2001,10 +2198,9 @@ pub struct LintGroup { [support](https://developer.arm.com/documentation/ecm0359818/latest/) for the TrustZone-M feature. -One of the things provided, with this unstable feature, is the -`C-cmse-nonsecure-call` function ABI. This ABI is used on function pointers to -non-secure code to mark a non-secure function call (see [section -5.5](https://developer.arm.com/documentation/ecm0359818/latest/) for details). +One of the things provided with this unstable feature is the "cmse-nonsecure-call" function ABI. +This ABI is used on function pointers to non-secure code to mark a non-secure function call +(see [section 5.5](https://developer.arm.com/documentation/ecm0359818/latest/) for details). With this ABI, the compiler will do the following to perform the call: * save registers needed after the call to Secure memory @@ -2015,19 +2211,16 @@ pub struct LintGroup { To avoid using the non-secure stack, the compiler will constrain the number and type of parameters/return value. -The `extern "C-cmse-nonsecure-call"` ABI is otherwise equivalent to the -`extern "C"` ABI. - ``` rust,ignore #![no_std] -#![feature(abi_c_cmse_nonsecure_call)] +#![feature(abi_cmse_nonsecure_call)] #[no_mangle] pub fn call_nonsecure_function(addr: usize) -> u32 { let non_secure_function = - unsafe { core::mem::transmute:: u32>(addr) }; + unsafe { core::mem::transmute:: u32>(addr) }; non_secure_function() } ``` @@ -2073,6 +2266,38 @@ pub fn call_nonsecure_function(addr: usize) -> u32 { add sp, #16 pop {r7, pc} ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "abi_custom", + description: r##"# `abi_custom` + +Allows `extern "custom" fn()`. + +The tracking issue for this feature is: [#140829] + +[#140829]: https://github.com/rust-lang/rust/issues/140829 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "abi_gpu_kernel", + description: r##"# `abi_gpu_kernel` + +Allows `extern "gpu-kernel" fn()`. + +The tracking issue for this feature is: [#135467] + +[#135467]: https://github.com/rust-lang/rust/issues/135467 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -2198,6 +2423,8 @@ pub fn device_function() { label: "abi_riscv_interrupt", description: r##"# `abi_riscv_interrupt` +Allows `extern "riscv-interrupt-m" fn()` and `extern "riscv-interrupt-s" fn()`. + The tracking issue for this feature is: [#111889] [#111889]: https://github.com/rust-lang/rust/issues/111889 @@ -2212,6 +2439,8 @@ pub fn device_function() { label: "abi_unadjusted", description: r##"# `abi_unadjusted` +Allows using the `unadjusted` ABI; perma-unstable. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -2250,6 +2479,8 @@ fn main() { label: "abi_x86_interrupt", description: r##"# `abi_x86_interrupt` +Allows `extern "x86-interrupt" fn()`. + The tracking issue for this feature is: [#40180] [#40180]: https://github.com/rust-lang/rust/issues/40180 @@ -2264,6 +2495,8 @@ fn main() { label: "abort_unwind", description: r##"# `abort_unwind` + + The tracking issue for this feature is: [#130338] [#130338]: https://github.com/rust-lang/rust/issues/130338 @@ -2278,6 +2511,8 @@ fn main() { label: "acceptfilter", description: r##"# `acceptfilter` + + The tracking issue for this feature is: [#121891] [#121891]: https://github.com/rust-lang/rust/issues/121891 @@ -2292,6 +2527,8 @@ fn main() { label: "addr_parse_ascii", description: r##"# `addr_parse_ascii` + + The tracking issue for this feature is: [#101035] [#101035]: https://github.com/rust-lang/rust/issues/101035 @@ -2339,6 +2576,22 @@ fn is_foo_a_and_bar_true() -> bool { } } ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "align_to_uninit_mut", + description: r##"# `align_to_uninit_mut` + + + +The tracking issue for this feature is: [#139062] + +[#139062]: https://github.com/rust-lang/rust/issues/139062 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -2348,6 +2601,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "alloc_error_handler", description: r##"# `alloc_error_handler` +Allows defining an `#[alloc_error_handler]`. + The tracking issue for this feature is: [#51540] [#51540]: https://github.com/rust-lang/rust/issues/51540 @@ -2362,6 +2617,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "alloc_error_hook", description: r##"# `alloc_error_hook` + + The tracking issue for this feature is: [#51245] [#51245]: https://github.com/rust-lang/rust/issues/51245 @@ -2376,6 +2633,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "alloc_internals", description: r##"# `alloc_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -2385,12 +2644,14 @@ fn is_foo_a_and_bar_true() -> bool { deny_since: None, }, Lint { - label: "alloc_layout_extra", - description: r##"# `alloc_layout_extra` + label: "alloc_slice_into_array", + description: r##"# `alloc_slice_into_array` -The tracking issue for this feature is: [#55724] -[#55724]: https://github.com/rust-lang/rust/issues/55724 + +The tracking issue for this feature is: [#148082] + +[#148082]: https://github.com/rust-lang/rust/issues/148082 ------------------------ "##, @@ -2428,6 +2689,20 @@ fn is_foo_a_and_bar_true() -> bool { detail of the `global_allocator` feature not intended for use outside the compiler. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "alloctests", + description: r##"# `alloctests` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -2438,6 +2713,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "allow_internal_unsafe", description: r##"# `allow_internal_unsafe` +Allows using `#[allow_internal_unsafe]`. This is an attribute on `macro_rules!` and can't use the attribute handling below (it has to be checked before expansion possibly makes macros disappear). + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -2450,6 +2727,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "allow_internal_unstable", description: r##"# `allow_internal_unstable` +Allows using `#[allow_internal_unstable]`. This is an attribute on `macro_rules!` and can't use the attribute handling below (it has to be checked before expansion possibly makes macros disappear). + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -2462,6 +2741,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "anonymous_lifetime_in_impl_trait", description: r##"# `anonymous_lifetime_in_impl_trait` +Allows using anonymous lifetimes in argument-position impl-trait. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -2471,12 +2752,14 @@ fn is_foo_a_and_bar_true() -> bool { deny_since: None, }, Lint { - label: "anonymous_pipe", - description: r##"# `anonymous_pipe` + label: "apx_target_feature", + description: r##"# `apx_target_feature` -The tracking issue for this feature is: [#127154] +The `apxf` target feature on x86 -[#127154]: https://github.com/rust-lang/rust/issues/127154 +The tracking issue for this feature is: [#139284] + +[#139284]: https://github.com/rust-lang/rust/issues/139284 ------------------------ "##, @@ -2493,6 +2776,153 @@ fn is_foo_a_and_bar_true() -> bool { [#44874]: https://github.com/rust-lang/rust/issues/44874 ------------------------ + +Allows any type implementing `core::ops::Receiver` to be used as the type +of `self` in a method belonging to `T`. + +For example, + +```rust +#![feature(arbitrary_self_types)] + +struct A; + +impl A { + fn f(self: SmartPtr) -> i32 { 1 } // note self type +} + +struct SmartPtr(T); + +impl core::ops::Receiver for SmartPtr { + type Target = T; +} + +fn main() { + let smart_ptr = SmartPtr(A); + assert_eq!(smart_ptr.f(), 1); +} +``` + +The `Receiver` trait has a blanket implementation for all `T: Deref`, so in fact +things like this work too: + +```rust +#![feature(arbitrary_self_types)] + +use std::rc::Rc; + +struct A; + +impl A { + fn f(self: Rc) -> i32 { 1 } // Rc implements Deref +} + +fn main() { + let smart_ptr = Rc::new(A); + assert_eq!(smart_ptr.f(), 1); +} +``` + +Interestingly, that works even without the `arbitrary_self_types` feature +- but that's because certain types are _effectively_ hard coded, including +`Rc`. ("Hard coding" isn't quite true; they use a lang-item called +`LegacyReceiver` to denote their special-ness in this way). With the +`arbitrary_self_types` feature, their special-ness goes away, and custom +smart pointers can achieve the same. + +## Changes to method lookup + +Method lookup previously used to work by stepping through the `Deref` +chain then using the resulting list of steps in two different ways: + +* To identify types that might contribute methods via their `impl` + blocks (inherent methods) or via traits +* To identify the types that the method receiver (`a` in the above + examples) can be converted to. + +With this feature, these lists are created by instead stepping through +the `Receiver` chain. However, a note is kept about whether the type +can be reached also via the `Deref` chain. + +The full chain (via `Receiver` hops) is used for the first purpose +(identifying relevant `impl` blocks and traits); whereas the shorter +list (reachable via `Deref`) is used for the second purpose. That's +because, to convert the method target (`a` in `a.b()`) to the self +type, Rust may need to be able to use `Deref::deref`. Type conversions, +then, can only proceed as far as the end of the `Deref` chain whereas +the longer `Receiver` chain can be used to explore more places where +useful methods might reside. + +## Types suitable for use as smart pointers + +This feature allows the creation of customised smart pointers - for example +your own equivalent to `Rc` or `Box` with whatever capabilities you like. +Those smart pointers can either implement `Deref` (if it's safe to +create a reference to the referent) or `Receiver` (if it isn't). + +Either way, smart pointer types should mostly _avoid having methods_. +Calling methods on a smart pointer leads to ambiguity about whether you're +aiming for a method on the pointer, or on the referent. + +Best practice is therefore to put smart pointer functionality into +associated functions instead - that's what's done in all the smart pointer +types within Rust's standard library which implement `Receiver`. + +If you choose to add any methods to your smart pointer type, your users +may run into errors from deshadowing, as described in the next section. + +## Avoiding shadowing + +With or without this feature, Rust emits an error if it finds two method +candidates, like this: + +```rust,compile_fail +use std::pin::Pin; +use std::pin::pin; + +struct A; + +impl A { + fn get_ref(self: Pin<&A>) {} +} + +fn main() { + let pinned_a: Pin<&A> = pin!(A).as_ref(); + let pinned_a: Pin<&A> = pinned_a.as_ref(); + pinned_a.get_ref(); // error[E0034]: multiple applicable items in scope +} +``` + +(this is why Rust's smart pointers are mostly carefully designed to avoid +having methods at all, and shouldn't add new methods in future.) + +With `arbitrary_self_types`, we take care to spot some other kinds of +conflict: + +```rust,compile_fail +#![feature(arbitrary_self_types)] + +use std::pin::Pin; +use std::pin::pin; + +struct A; + +impl A { + fn get_ref(self: &Pin<&A>) {} // note &Pin +} + +fn main() { + let pinned_a: Pin<&mut A> = pin!(A); + let pinned_a: Pin<&A> = pinned_a.as_ref(); + pinned_a.get_ref(); +} +``` + +This is to guard against the case where an inner (referent) type has a +method of a given name, taking the smart pointer by reference, and then +the smart pointer implementer adds a similar method taking self by value. +As noted in the previous section, the safe option is simply +not to add methods to smart pointers, and then these errors can't occur. "##, default_severity: Severity::Allow, warn_since: None, @@ -2504,7 +2934,73 @@ fn is_foo_a_and_bar_true() -> bool { The tracking issue for this feature is: [#44874] -[#44874]: https://github.com/rust-lang/rust/issues/44874 +[#38788]: https://github.com/rust-lang/rust/issues/44874 + +------------------------ + +This extends the [arbitrary self types] feature to allow methods to +receive `self` by pointer. For example: + +```rust +#![feature(arbitrary_self_types_pointers)] + +struct A; + +impl A { + fn m(self: *const Self) {} +} + +fn main() { + let a = A; + let a_ptr: *const A = &a as *const A; + a_ptr.m(); +} +``` + +In general this is not advised: it's thought to be better practice to wrap +raw pointers in a newtype wrapper which implements the `core::ops::Receiver` +trait, then you need "only" the `arbitrary_self_types` feature. For example: + +```rust +#![feature(arbitrary_self_types)] +#![allow(dead_code)] + +struct A; + +impl A { + fn m(self: Wrapper) {} // can extract the pointer and do + // what it needs +} + +struct Wrapper(*const T); + +impl core::ops::Receiver for Wrapper { + type Target = T; +} + +fn main() { + let a = A; + let a_ptr: *const A = &a as *const A; + let a_wrapper = Wrapper(a_ptr); + a_wrapper.m(); +} +``` + +[arbitrary self types]: arbitrary-self-types.md +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "arc_is_unique", + description: r##"# `arc_is_unique` + + + +The tracking issue for this feature is: [#138938] + +[#138938]: https://github.com/rust-lang/rust/issues/138938 ------------------------ "##, @@ -2516,23 +3012,11 @@ fn is_foo_a_and_bar_true() -> bool { label: "arm_target_feature", description: r##"# `arm_target_feature` -The tracking issue for this feature is: [#44839] +Target features on arm. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150246] ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "array_chunks", - description: r##"# `array_chunks` - -The tracking issue for this feature is: [#74985] - -[#74985]: https://github.com/rust-lang/rust/issues/74985 +[#150246]: https://github.com/rust-lang/rust/issues/150246 ------------------------ "##, @@ -2544,6 +3028,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "array_into_iter_constructors", description: r##"# `array_into_iter_constructors` + + The tracking issue for this feature is: [#91583] [#91583]: https://github.com/rust-lang/rust/issues/91583 @@ -2558,24 +3044,12 @@ fn is_foo_a_and_bar_true() -> bool { label: "array_ptr_get", description: r##"# `array_ptr_get` + + The tracking issue for this feature is: [#119834] [#119834]: https://github.com/rust-lang/rust/issues/119834 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "array_repeat", - description: r##"# `array_repeat` - -The tracking issue for this feature is: [#126695] - -[#126695]: https://github.com/rust-lang/rust/issues/126695 - ------------------------ "##, default_severity: Severity::Allow, @@ -2586,6 +3060,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "array_try_from_fn", description: r##"# `array_try_from_fn` + + The tracking issue for this feature is: [#89379] [#89379]: https://github.com/rust-lang/rust/issues/89379 @@ -2600,38 +3076,12 @@ fn is_foo_a_and_bar_true() -> bool { label: "array_try_map", description: r##"# `array_try_map` + + The tracking issue for this feature is: [#79711] [#79711]: https://github.com/rust-lang/rust/issues/79711 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "array_windows", - description: r##"# `array_windows` - -The tracking issue for this feature is: [#75027] - -[#75027]: https://github.com/rust-lang/rust/issues/75027 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "as_array_of_cells", - description: r##"# `as_array_of_cells` - -The tracking issue for this feature is: [#88248] - -[#88248]: https://github.com/rust-lang/rust/issues/88248 - ------------------------ "##, default_severity: Severity::Allow, @@ -2642,6 +3092,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "ascii_char", description: r##"# `ascii_char` + + The tracking issue for this feature is: [#110998] [#110998]: https://github.com/rust-lang/rust/issues/110998 @@ -2656,6 +3108,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "ascii_char_variants", description: r##"# `ascii_char_variants` + + The tracking issue for this feature is: [#110998] [#110998]: https://github.com/rust-lang/rust/issues/110998 @@ -2678,7 +3132,6 @@ fn is_foo_a_and_bar_true() -> bool { This feature tracks `asm!` and `global_asm!` support for the following architectures: - NVPTX -- PowerPC - Hexagon - MIPS32r2 and MIPS64r2 - wasm32 @@ -2701,12 +3154,6 @@ fn is_foo_a_and_bar_true() -> bool { | NVPTX | `reg64` | None\* | `l` | | Hexagon | `reg` | `r[0-28]` | `r` | | Hexagon | `preg` | `p[0-3]` | Only clobbers | -| PowerPC | `reg` | `r0`, `r[3-12]`, `r[14-28]` | `r` | -| PowerPC | `reg_nonzero` | `r[3-12]`, `r[14-28]` | `b` | -| PowerPC | `freg` | `f[0-31]` | `f` | -| PowerPC | `vreg` | `v[0-31]` | `v` | -| PowerPC | `cr` | `cr[0-7]`, `cr` | Only clobbers | -| PowerPC | `xer` | `xer` | Only clobbers | | wasm32 | `local` | None\* | `r` | | BPF | `reg` | `r[0-10]` | `r` | | BPF | `wreg` | `w[0-10]` | `w` | @@ -2742,13 +3189,6 @@ fn is_foo_a_and_bar_true() -> bool { | NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` | | Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` | | Hexagon | `preg` | N/A | Only clobbers | -| PowerPC | `reg` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) | -| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) | -| PowerPC | `freg` | None | `f32`, `f64` | -| PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` | -| PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` | -| PowerPC | `cr` | N/A | Only clobbers | -| PowerPC | `xer` | N/A | Only clobbers | | wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` | | BPF | `reg` | None | `i8` `i16` `i32` `i64` | | BPF | `wreg` | `alu32` | `i8` `i16` `i32` | @@ -2769,10 +3209,6 @@ fn is_foo_a_and_bar_true() -> bool { | Hexagon | `r29` | `sp` | | Hexagon | `r30` | `fr` | | Hexagon | `r31` | `lr` | -| PowerPC | `r1` | `sp` | -| PowerPC | `r31` | `fp` | -| PowerPC | `r[0-31]` | `[0-31]` | -| PowerPC | `f[0-31]` | `fr[0-31]`| | BPF | `r[0-10]` | `w[0-10]` | | AVR | `XH` | `r27` | | AVR | `XL` | `r26` | @@ -2811,18 +3247,14 @@ fn is_foo_a_and_bar_true() -> bool { | Architecture | Unsupported register | Reason | | ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | All | `sp`, `r14`/`o6` (SPARC) | The stack pointer must be restored to its original value at the end of an asm code block. | -| All | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output. | -| All | `r19` (Hexagon), `r29` (PowerPC), `r30` (PowerPC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. | +| All | `fr` (Hexagon) `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output. | +| All | `r19` (Hexagon) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. | | MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. | | MIPS | `$1` or `$at` | Reserved for assembler. | | MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. | | MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. | | MIPS | `$ra` | Return address cannot be used as inputs or outputs. | | Hexagon | `lr` | This is the link register which cannot be used as an input or output. | -| PowerPC | `r2`, `r13` | These are system reserved registers. | -| PowerPC | `lr` | The link register cannot be used as an input or output. | -| PowerPC | `ctr` | The counter register cannot be used as an input or output. | -| PowerPC | `vrsave` | The vrsave register cannot be used as an input or output. | | AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. | |MSP430 | `r0`, `r2`, `r3` | These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to. | | M68k | `a4`, `a5` | Used internally by LLVM for the base pointer and global base pointer. | @@ -2849,10 +3281,6 @@ fn is_foo_a_and_bar_true() -> bool { | NVPTX | `reg32` | None | `r0` | None | | NVPTX | `reg64` | None | `rd0` | None | | Hexagon | `reg` | None | `r0` | None | -| PowerPC | `reg` | None | `0` | None | -| PowerPC | `reg_nonzero` | None | `3` | None | -| PowerPC | `freg` | None | `0` | None | -| PowerPC | `vreg` | None | `0` | None | | SPARC | `reg` | None | `%o0` | None | | CSKY | `reg` | None | `r0` | None | | CSKY | `freg` | None | `f0` | None | @@ -2869,6 +3297,8 @@ fn is_foo_a_and_bar_true() -> bool { - SPARC - Integer condition codes (`icc` and `xcc`) - Floating-point condition codes (`fcc[0-3]`) +- CSKY + - Condition/carry bit (C) in `PSR`. "##, default_severity: Severity::Allow, warn_since: None, @@ -2890,16 +3320,14 @@ fn is_foo_a_and_bar_true() -> bool { | Architecture | Register class | Registers | LLVM constraint code | | ------------ | -------------- | --------- | -------------------- | -| s390x | `vreg` | `v[0-31]` | `v` | - -> **Notes**: -> - s390x `vreg` is clobber-only in stable. ## Register class supported types | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | ------------- | -| s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` | +| x86 | `xmm_reg` | `sse` | `i128` | +| x86 | `ymm_reg` | `avx` | `i128` | +| x86 | `zmm_reg` | `avx512f` | `i128` | ## Register aliases @@ -2915,46 +3343,6 @@ fn is_foo_a_and_bar_true() -> bool { | Architecture | Register class | Modifier | Example output | LLVM modifier | | ------------ | -------------- | -------- | -------------- | ------------- | -| s390x | `vreg` | None | `%v0` | None | -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "asm_goto", - description: r##"# `asm_goto` - -The tracking issue for this feature is: [#119364] - -[#119364]: https://github.com/rust-lang/rust/issues/119364 - ------------------------- - -This feature adds a `label ` operand type to `asm!`. - -Example: -```rust,ignore (partial-example, x86-only) - -unsafe { - asm!( - "jmp {}", - label { - println!("Jumped from asm!"); - } - ); -} -``` - -The block must have unit type or diverge. The block starts a new safety context, -so despite outer `unsafe`, you need extra unsafe to perform unsafe operations -within `label `. - -When `label ` is used together with `noreturn` option, it means that the -assembly will not fallthrough. It's allowed to jump to a label within the -assembly. In this case, the entire `asm!` expression will have an unit type as -opposed to diverging, if not all label blocks diverge. The `asm!` expression -still diverges if `noreturn` option is used and all label blocks diverge. "##, default_severity: Severity::Allow, warn_since: None, @@ -2969,6 +3357,26 @@ fn is_foo_a_and_bar_true() -> bool { [#119364]: https://github.com/rust-lang/rust/issues/119364 ------------------------ + +This feature allows label operands to be used together with output operands. + +Example: +```rust,ignore (partial-example, x86-only) + +unsafe { + let a: usize; + asm!( + "mov {}, 1" + "jmp {}", + out(reg) a, + label { + println!("Jumped from asm {}!", a); + } + ); +} +``` + +The output operands are assigned before the label blocks are executed. "##, default_severity: Severity::Allow, warn_since: None, @@ -2985,34 +3393,6 @@ fn is_foo_a_and_bar_true() -> bool { ------------------------ This feature adds a `may_unwind` option to `asm!` which allows an `asm` block to unwind stack and be part of the stack unwinding process. This option is only supported by the LLVM backend right now. -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "assert_matches", - description: r##"# `assert_matches` - -The tracking issue for this feature is: [#82775] - -[#82775]: https://github.com/rust-lang/rust/issues/82775 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "associated_const_equality", - description: r##"# `associated_const_equality` - -The tracking issue for this feature is: [#92827] - -[#92827]: https://github.com/rust-lang/rust/issues/92827 - ------------------------- "##, default_severity: Severity::Allow, warn_since: None, @@ -3022,24 +3402,12 @@ fn is_foo_a_and_bar_true() -> bool { label: "associated_type_defaults", description: r##"# `associated_type_defaults` +Allows associated type defaults. + The tracking issue for this feature is: [#29661] [#29661]: https://github.com/rust-lang/rust/issues/29661 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "async_closure", - description: r##"# `async_closure` - -The tracking issue for this feature is: [#62290] - -[#62290]: https://github.com/rust-lang/rust/issues/62290 - ------------------------ "##, default_severity: Severity::Allow, @@ -3050,10 +3418,28 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_drop", description: r##"# `async_drop` +Allows implementing `AsyncDrop`. + The tracking issue for this feature is: [#126482] [#126482]: https://github.com/rust-lang/rust/issues/126482 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "async_fn_in_dyn_trait", + description: r##"# `async_fn_in_dyn_trait` + +Allows async functions to be called from `dyn Trait`. + +The tracking issue for this feature is: [#133119] + +[#133119]: https://github.com/rust-lang/rust/issues/133119 + ------------------------ "##, default_severity: Severity::Allow, @@ -3064,6 +3450,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_fn_track_caller", description: r##"# `async_fn_track_caller` +Allows `#[track_caller]` on async functions. + The tracking issue for this feature is: [#110011] [#110011]: https://github.com/rust-lang/rust/issues/110011 @@ -3098,6 +3486,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_for_loop", description: r##"# `async_for_loop` +Allows `for await` loops. + The tracking issue for this feature is: [#118898] [#118898]: https://github.com/rust-lang/rust/issues/118898 @@ -3112,6 +3502,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_gen_internals", description: r##"# `async_gen_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -3124,6 +3516,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_iter_from_iter", description: r##"# `async_iter_from_iter` + + The tracking issue for this feature is: [#81798] [#81798]: https://github.com/rust-lang/rust/issues/81798 @@ -3138,6 +3532,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_iterator", description: r##"# `async_iterator` + + The tracking issue for this feature is: [#79024] [#79024]: https://github.com/rust-lang/rust/issues/79024 @@ -3152,6 +3548,8 @@ fn is_foo_a_and_bar_true() -> bool { label: "async_trait_bounds", description: r##"# `async_trait_bounds` +Allows `async` trait bound modifier. + The tracking issue for this feature is: [#62290] [#62290]: https://github.com/rust-lang/rust/issues/62290 @@ -3166,10 +3564,42 @@ fn is_foo_a_and_bar_true() -> bool { label: "atomic_from_mut", description: r##"# `atomic_from_mut` + + The tracking issue for this feature is: [#76314] [#76314]: https://github.com/rust-lang/rust/issues/76314 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "atomic_internals", + description: r##"# `atomic_internals` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "atomic_ptr_null", + description: r##"# `atomic_ptr_null` + + + +The tracking issue for this feature is: [#150733] + +[#150733]: https://github.com/rust-lang/rust/issues/150733 + ------------------------ "##, default_severity: Severity::Allow, @@ -3293,6 +3723,8 @@ trait matching, this cycle would be an error, but for an auto trait it label: "autodiff", description: r##"# `autodiff` + + The tracking issue for this feature is: [#124509] [#124509]: https://github.com/rust-lang/rust/issues/124509 @@ -3304,12 +3736,30 @@ trait matching, this cycle would be an error, but for an auto trait it deny_since: None, }, Lint { - label: "avx512_target_feature", - description: r##"# `avx512_target_feature` + label: "avr_target_feature", + description: r##"# `avr_target_feature` -The tracking issue for this feature is: [#44839] +Target features on avr. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#146889] + +[#146889]: https://github.com/rust-lang/rust/issues/146889 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "avx10_target_feature", + description: r##"# `avx10_target_feature` + +Allows using Intel AVX10 target features and intrinsics + +The tracking issue for this feature is: [#138843] + +[#138843]: https://github.com/rust-lang/rust/issues/138843 ------------------------ "##, @@ -3321,6 +3771,8 @@ trait matching, this cycle would be an error, but for an auto trait it label: "backtrace_frames", description: r##"# `backtrace_frames` + + The tracking issue for this feature is: [#79676] [#79676]: https://github.com/rust-lang/rust/issues/79676 @@ -3332,12 +3784,28 @@ trait matching, this cycle would be an error, but for an auto trait it deny_since: None, }, Lint { - label: "bigint_helper_methods", - description: r##"# `bigint_helper_methods` + label: "bikeshed_guaranteed_no_drop", + description: r##"# `bikeshed_guaranteed_no_drop` -The tracking issue for this feature is: [#85532] -[#85532]: https://github.com/rust-lang/rust/issues/85532 + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "binary_heap_as_mut_slice", + description: r##"# `binary_heap_as_mut_slice` + + + +The tracking issue for this feature is: [#154009] + +[#154009]: https://github.com/rust-lang/rust/issues/154009 ------------------------ "##, @@ -3349,10 +3817,28 @@ trait matching, this cycle would be an error, but for an auto trait it label: "binary_heap_drain_sorted", description: r##"# `binary_heap_drain_sorted` + + The tracking issue for this feature is: [#59278] [#59278]: https://github.com/rust-lang/rust/issues/59278 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "binary_heap_from_raw_vec", + description: r##"# `binary_heap_from_raw_vec` + + + +The tracking issue for this feature is: [#152500] + +[#152500]: https://github.com/rust-lang/rust/issues/152500 + ------------------------ "##, default_severity: Severity::Allow, @@ -3363,10 +3849,76 @@ trait matching, this cycle would be an error, but for an auto trait it label: "binary_heap_into_iter_sorted", description: r##"# `binary_heap_into_iter_sorted` + + The tracking issue for this feature is: [#59278] [#59278]: https://github.com/rust-lang/rust/issues/59278 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "binary_heap_peek_mut_refresh", + description: r##"# `binary_heap_peek_mut_refresh` + + + +The tracking issue for this feature is: [#138355] + +[#138355]: https://github.com/rust-lang/rust/issues/138355 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "binary_heap_pop_if", + description: r##"# `binary_heap_pop_if` + + + +The tracking issue for this feature is: [#151828] + +[#151828]: https://github.com/rust-lang/rust/issues/151828 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "bool_to_result", + description: r##"# `bool_to_result` + + + +The tracking issue for this feature is: [#142748] + +[#142748]: https://github.com/rust-lang/rust/issues/142748 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "borrowed_buf_init", + description: r##"# `borrowed_buf_init` + + + +The tracking issue for this feature is: [#78485] + +[#78485]: https://github.com/rust-lang/rust/issues/78485 + ------------------------ "##, default_severity: Severity::Allow, @@ -3377,10 +3929,28 @@ trait matching, this cycle would be an error, but for an auto trait it label: "bound_as_ref", description: r##"# `bound_as_ref` + + The tracking issue for this feature is: [#80996] [#80996]: https://github.com/rust-lang/rust/issues/80996 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "bound_copied", + description: r##"# `bound_copied` + + + +The tracking issue for this feature is: [#145966] + +[#145966]: https://github.com/rust-lang/rust/issues/145966 + ------------------------ "##, default_severity: Severity::Allow, @@ -3391,6 +3961,8 @@ trait matching, this cycle would be an error, but for an auto trait it label: "box_as_ptr", description: r##"# `box_as_ptr` + + The tracking issue for this feature is: [#129090] [#129090]: https://github.com/rust-lang/rust/issues/129090 @@ -3405,6 +3977,8 @@ trait matching, this cycle would be an error, but for an auto trait it label: "box_into_boxed_slice", description: r##"# `box_into_boxed_slice` + + The tracking issue for this feature is: [#71582] [#71582]: https://github.com/rust-lang/rust/issues/71582 @@ -3419,6 +3993,8 @@ trait matching, this cycle would be an error, but for an auto trait it label: "box_into_inner", description: r##"# `box_into_inner` + + The tracking issue for this feature is: [#80437] [#80437]: https://github.com/rust-lang/rust/issues/80437 @@ -3439,6 +4015,8 @@ trait matching, this cycle would be an error, but for an auto trait it ------------------------ +> **Note**: This feature will be superseded by [`deref_patterns`] in the future. + Box patterns let you match on `Box`s: @@ -3461,18 +4039,22 @@ fn main() { } } ``` + +[`deref_patterns`]: ./deref-patterns.md "##, default_severity: Severity::Allow, warn_since: None, deny_since: None, }, Lint { - label: "box_uninit_write", - description: r##"# `box_uninit_write` + label: "box_take", + description: r##"# `box_take` -The tracking issue for this feature is: [#129397] -[#129397]: https://github.com/rust-lang/rust/issues/129397 + +The tracking issue for this feature is: [#147212] + +[#147212]: https://github.com/rust-lang/rust/issues/147212 ------------------------ "##, @@ -3484,6 +4066,8 @@ fn main() { label: "box_vec_non_null", description: r##"# `box_vec_non_null` + + The tracking issue for this feature is: [#130364] [#130364]: https://github.com/rust-lang/rust/issues/130364 @@ -3498,9 +4082,11 @@ fn main() { label: "bpf_target_feature", description: r##"# `bpf_target_feature` -The tracking issue for this feature is: [#44839] +Target features on bpf. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150247] + +[#150247]: https://github.com/rust-lang/rust/issues/150247 ------------------------ "##, @@ -3512,10 +4098,42 @@ fn main() { label: "breakpoint", description: r##"# `breakpoint` + + The tracking issue for this feature is: [#133724] [#133724]: https://github.com/rust-lang/rust/issues/133724 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "bstr", + description: r##"# `bstr` + + + +The tracking issue for this feature is: [#134915] + +[#134915]: https://github.com/rust-lang/rust/issues/134915 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "bstr_internals", + description: r##"# `bstr_internals` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -3526,6 +4144,8 @@ fn main() { label: "btree_cursors", description: r##"# `btree_cursors` + + The tracking issue for this feature is: [#107540] [#107540]: https://github.com/rust-lang/rust/issues/107540 @@ -3537,26 +4157,14 @@ fn main() { deny_since: None, }, Lint { - label: "btree_entry_insert", - description: r##"# `btree_entry_insert` + label: "btree_merge", + description: r##"# `btree_merge` -The tracking issue for this feature is: [#65225] -[#65225]: https://github.com/rust-lang/rust/issues/65225 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "btree_extract_if", - description: r##"# `btree_extract_if` +The tracking issue for this feature is: [#152152] -The tracking issue for this feature is: [#70530] - -[#70530]: https://github.com/rust-lang/rust/issues/70530 +[#152152]: https://github.com/rust-lang/rust/issues/152152 ------------------------ "##, @@ -3568,6 +4176,8 @@ fn main() { label: "btree_set_entry", description: r##"# `btree_set_entry` + + The tracking issue for this feature is: [#133549] [#133549]: https://github.com/rust-lang/rust/issues/133549 @@ -3582,6 +4192,8 @@ fn main() { label: "btreemap_alloc", description: r##"# `btreemap_alloc` + + The tracking issue for this feature is: [#32838] [#32838]: https://github.com/rust-lang/rust/issues/32838 @@ -3596,6 +4208,8 @@ fn main() { label: "buf_read_has_data_left", description: r##"# `buf_read_has_data_left` + + The tracking issue for this feature is: [#86423] [#86423]: https://github.com/rust-lang/rust/issues/86423 @@ -3610,6 +4224,8 @@ fn main() { label: "bufreader_peek", description: r##"# `bufreader_peek` + + The tracking issue for this feature is: [#128405] [#128405]: https://github.com/rust-lang/rust/issues/128405 @@ -3624,6 +4240,8 @@ fn main() { label: "builtin_syntax", description: r##"# `builtin_syntax` +Allows builtin # foo() syntax + The tracking issue for this feature is: [#110680] [#110680]: https://github.com/rust-lang/rust/issues/110680 @@ -3638,24 +4256,12 @@ fn main() { label: "c_size_t", description: r##"# `c_size_t` + + The tracking issue for this feature is: [#88345] [#88345]: https://github.com/rust-lang/rust/issues/88345 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "c_str_module", - description: r##"# `c_str_module` - -The tracking issue for this feature is: [#112134] - -[#112134]: https://github.com/rust-lang/rust/issues/112134 - ------------------------ "##, default_severity: Severity::Allow, @@ -3694,33 +4300,16 @@ fn main() { deny_since: None, }, Lint { - label: "c_variadic", - description: r##"# `c_variadic` + label: "c_variadic_naked_functions", + description: r##"# `c_variadic_naked_functions` -The tracking issue for this feature is: [#44930] +Allows defining c-variadic naked functions with any extern ABI that is allowed on c-variadic foreign functions. -[#44930]: https://github.com/rust-lang/rust/issues/44930 +The tracking issue for this feature is: [#148767] + +[#148767]: https://github.com/rust-lang/rust/issues/148767 ------------------------ - -The `c_variadic` library feature exposes the `VaList` structure, -Rust's analogue of C's `va_list` type. - -## Examples - -```rust -#![feature(c_variadic)] - -use std::ffi::VaList; - -pub unsafe extern "C" fn vadd(n: usize, mut args: VaList) -> usize { - let mut sum = 0; - for _ in 0..n { - sum += args.arg::(); - } - sum -} -``` "##, default_severity: Severity::Allow, warn_since: None, @@ -3742,10 +4331,60 @@ fn main() { label: "can_vector", description: r##"# `can_vector` + + The tracking issue for this feature is: [#69941] [#69941]: https://github.com/rust-lang/rust/issues/69941 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "case_ignorable", + description: r##"# `case_ignorable` + + + +The tracking issue for this feature is: [#154848] + +[#154848]: https://github.com/rust-lang/rust/issues/154848 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cast_maybe_uninit", + description: r##"# `cast_maybe_uninit` + + + +The tracking issue for this feature is: [#145036] + +[#145036]: https://github.com/rust-lang/rust/issues/145036 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cell_get_cloned", + description: r##"# `cell_get_cloned` + + + +The tracking issue for this feature is: [#145329] + +[#145329]: https://github.com/rust-lang/rust/issues/145329 + ------------------------ "##, default_severity: Severity::Allow, @@ -3756,24 +4395,12 @@ fn main() { label: "cell_leak", description: r##"# `cell_leak` + + The tracking issue for this feature is: [#69099] [#69099]: https://github.com/rust-lang/rust/issues/69099 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "cell_update", - description: r##"# `cell_update` - -The tracking issue for this feature is: [#50186] - -[#50186]: https://github.com/rust-lang/rust/issues/50186 - ------------------------ "##, default_severity: Severity::Allow, @@ -3784,10 +4411,42 @@ fn main() { label: "cfg_accessible", description: r##"# `cfg_accessible` + + The tracking issue for this feature is: [#64797] [#64797]: https://github.com/rust-lang/rust/issues/64797 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cfg_contract_checks", + description: r##"# `cfg_contract_checks` + +Allows the use of `#[cfg(contract_checks)` to check if contract checks are enabled. + +The tracking issue for this feature is: [#128044] + +[#128044]: https://github.com/rust-lang/rust/issues/128044 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cfg_emscripten_wasm_eh", + description: r##"# `cfg_emscripten_wasm_eh` + +Allows access to the emscripten_wasm_eh config, used by panic_unwind and unwind + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -3798,24 +4457,12 @@ fn main() { label: "cfg_eval", description: r##"# `cfg_eval` + + The tracking issue for this feature is: [#82679] [#82679]: https://github.com/rust-lang/rust/issues/82679 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "cfg_match", - description: r##"# `cfg_match` - -The tracking issue for this feature is: [#115585] - -[#115585]: https://github.com/rust-lang/rust/issues/115585 - ------------------------ "##, default_severity: Severity::Allow, @@ -3826,6 +4473,8 @@ fn main() { label: "cfg_overflow_checks", description: r##"# `cfg_overflow_checks` +Allows the use of `#[cfg(overflow_checks)` to check if integer overflow behaviour. + The tracking issue for this feature is: [#111466] [#111466]: https://github.com/rust-lang/rust/issues/111466 @@ -3840,6 +4489,8 @@ fn main() { label: "cfg_relocation_model", description: r##"# `cfg_relocation_model` +Provides the relocation model information as cfg entry + The tracking issue for this feature is: [#114929] [#114929]: https://github.com/rust-lang/rust/issues/114929 @@ -3895,6 +4546,8 @@ fn b() { label: "cfg_sanitizer_cfi", description: r##"# `cfg_sanitizer_cfi` +Allows `cfg(sanitizer_cfi_generalize_pointers)` and `cfg(sanitizer_cfi_normalize_integers)`. + The tracking issue for this feature is: [#89653] [#89653]: https://github.com/rust-lang/rust/issues/89653 @@ -3909,6 +4562,8 @@ fn b() { label: "cfg_target_compact", description: r##"# `cfg_target_compact` +Allows `cfg(target(abi = "..."))`. + The tracking issue for this feature is: [#96901] [#96901]: https://github.com/rust-lang/rust/issues/96901 @@ -3923,6 +4578,8 @@ fn b() { label: "cfg_target_has_atomic", description: r##"# `cfg_target_has_atomic` +Allows `cfg(target_has_atomic_load_store = "...")`. + The tracking issue for this feature is: [#94039] [#94039]: https://github.com/rust-lang/rust/issues/94039 @@ -3937,10 +4594,26 @@ fn b() { label: "cfg_target_has_atomic_equal_alignment", description: r##"# `cfg_target_has_atomic_equal_alignment` +Allows `cfg(target_has_atomic_equal_alignment = "...")`. + The tracking issue for this feature is: [#93822] [#93822]: https://github.com/rust-lang/rust/issues/93822 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cfg_target_has_reliable_f16_f128", + description: r##"# `cfg_target_has_reliable_f16_f128` + +Allows checking whether or not the backend correctly supports unstable float types. + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -3951,6 +4624,8 @@ fn b() { label: "cfg_target_thread_local", description: r##"# `cfg_target_thread_local` +Allows `cfg(target_thread_local)`. + The tracking issue for this feature is: [#29594] [#29594]: https://github.com/rust-lang/rust/issues/29594 @@ -3965,6 +4640,8 @@ fn b() { label: "cfg_ub_checks", description: r##"# `cfg_ub_checks` +Allows the use of `#[cfg(ub_checks)` to check if UB checks are enabled. + The tracking issue for this feature is: [#123499] [#123499]: https://github.com/rust-lang/rust/issues/123499 @@ -4053,8 +4730,58 @@ fn b() { label: "char_internals", description: r##"# `char_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "char_max_len", + description: r##"# `char_max_len` + + + +The tracking issue for this feature is: [#121714] + +[#121714]: https://github.com/rust-lang/rust/issues/121714 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "clamp_magnitude", + description: r##"# `clamp_magnitude` + + + +The tracking issue for this feature is: [#148519] + +[#148519]: https://github.com/rust-lang/rust/issues/148519 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "clone_from_ref", + description: r##"# `clone_from_ref` + + + +The tracking issue for this feature is: [#149075] + +[#149075]: https://github.com/rust-lang/rust/issues/149075 + ------------------------ "##, default_severity: Severity::Allow, @@ -4065,6 +4792,8 @@ fn b() { label: "clone_to_uninit", description: r##"# `clone_to_uninit` + + The tracking issue for this feature is: [#126799] [#126799]: https://github.com/rust-lang/rust/issues/126799 @@ -4079,6 +4808,8 @@ fn b() { label: "closure_lifetime_binder", description: r##"# `closure_lifetime_binder` +Allows `for<...>` on closures and coroutines. + The tracking issue for this feature is: [#97362] [#97362]: https://github.com/rust-lang/rust/issues/97362 @@ -4112,6 +4843,8 @@ fn b() { label: "cmp_minmax", description: r##"# `cmp_minmax` + + The tracking issue for this feature is: [#115939] [#115939]: https://github.com/rust-lang/rust/issues/115939 @@ -4140,10 +4873,9 @@ fn b() { [support](https://developer.arm.com/documentation/ecm0359818/latest/) for the TrustZone-M feature. -One of the things provided, with this unstable feature, is the -`C-cmse-nonsecure-entry` ABI. This ABI marks a Secure function as an -entry function (see [section -5.4](https://developer.arm.com/documentation/ecm0359818/latest/) for details). +One of the things provided with this unstable feature is the "cmse-nonsecure-entry" ABI. +This ABI marks a Secure function as an entry function (see +[section 5.4](https://developer.arm.com/documentation/ecm0359818/latest/) for details). With this ABI, the compiler will do the following: * add a special symbol on the function which is the `__acle_se_` prefix and the standard function name @@ -4154,9 +4886,7 @@ fn b() { Because the stack can not be used to pass parameters, there will be compilation errors if: -* the total size of all parameters is too big (for example more than four 32 - bits integers) -* the entry function is not using a C ABI +* the total size of all parameters is too big (for example, more than four 32-bit integers) The special symbol `__acle_se_` will be used by the linker to generate a secure gateway veneer. @@ -4168,7 +4898,7 @@ fn b() { #![feature(cmse_nonsecure_entry)] #[no_mangle] -pub extern "C-cmse-nonsecure-entry" fn entry_function(input: u32) -> u32 { +pub extern "cmse-nonsecure-entry" fn entry_function(input: u32) -> u32 { input + 6 } ``` @@ -4205,6 +4935,20 @@ pub extern "C-cmse-nonsecure-entry" fn entry_function(input: u32) -> u32 { 3c: f7ff fffe bl 0 <_ZN4core9panicking5panic17h5c028258ca2fb3f5E> 40: defe udf #254 ; 0xfe ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "coerce_pointee_validated", + description: r##"# `coerce_pointee_validated` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -4214,10 +4958,28 @@ pub extern "C-cmse-nonsecure-entry" fn entry_function(input: u32) -> u32 { label: "coerce_unsized", description: r##"# `coerce_unsized` + + The tracking issue for this feature is: [#18598] [#18598]: https://github.com/rust-lang/rust/issues/18598 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "command_resolved_envs", + description: r##"# `command_resolved_envs` + + + +The tracking issue for this feature is: [#149070] + +[#149070]: https://github.com/rust-lang/rust/issues/149070 + ------------------------ "##, default_severity: Severity::Allow, @@ -4240,40 +5002,13 @@ pub extern "C-cmse-nonsecure-entry" fn entry_function(input: u32) -> u32 { label: "concat_bytes", description: r##"# `concat_bytes` + + The tracking issue for this feature is: [#87555] [#87555]: https://github.com/rust-lang/rust/issues/87555 ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "concat_idents", - description: r##"# `concat_idents` - -The tracking issue for this feature is: [#29599] - -[#29599]: https://github.com/rust-lang/rust/issues/29599 - ------------------------- - -The `concat_idents` feature adds a macro for concatenating multiple identifiers -into one identifier. - -## Examples - -```rust -#![feature(concat_idents)] - -fn main() { - fn foobar() -> u32 { 23 } - let f = concat_idents!(foo, bar); - assert_eq!(f(), 23); -} -``` "##, default_severity: Severity::Allow, warn_since: None, @@ -4283,6 +5018,8 @@ fn foobar() -> u32 { 23 } label: "const_alloc_error", description: r##"# `const_alloc_error` + + The tracking issue for this feature is: [#92523] [#92523]: https://github.com/rust-lang/rust/issues/92523 @@ -4294,40 +5031,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_alloc_layout", - description: r##"# `const_alloc_layout` + label: "const_array", + description: r##"# `const_array` -The tracking issue for this feature is: [#67521] -[#67521]: https://github.com/rust-lang/rust/issues/67521 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "const_array_as_mut_slice", - description: r##"# `const_array_as_mut_slice` +The tracking issue for this feature is: [#147606] -The tracking issue for this feature is: [#133333] - -[#133333]: https://github.com/rust-lang/rust/issues/133333 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "const_array_each_ref", - description: r##"# `const_array_each_ref` - -The tracking issue for this feature is: [#133289] - -[#133289]: https://github.com/rust-lang/rust/issues/133289 +[#147606]: https://github.com/rust-lang/rust/issues/147606 ------------------------ "##, @@ -4339,6 +5050,8 @@ fn foobar() -> u32 { 23 } label: "const_async_blocks", description: r##"# `const_async_blocks` +Allows `async {}` expressions in const contexts. + The tracking issue for this feature is: [#85368] [#85368]: https://github.com/rust-lang/rust/issues/85368 @@ -4350,10 +5063,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_black_box", - description: r##"# `const_black_box` + label: "const_block_items", + description: r##"# `const_block_items` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +Allows `const { ... }` as a shorthand for `const _: () = const { ... };` for module items. + +The tracking issue for this feature is: [#149226] + +[#149226]: https://github.com/rust-lang/rust/issues/149226 ------------------------ "##, @@ -4362,12 +5079,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_box", - description: r##"# `const_box` + label: "const_bool", + description: r##"# `const_bool` -The tracking issue for this feature is: [#92521] -[#92521]: https://github.com/rust-lang/rust/issues/92521 + +The tracking issue for this feature is: [#151531] + +[#151531]: https://github.com/rust-lang/rust/issues/151531 ------------------------ "##, @@ -4379,6 +5098,8 @@ fn foobar() -> u32 { 23 } label: "const_btree_len", description: r##"# `const_btree_len` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -4388,12 +5109,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_cell", - description: r##"# `const_cell` + label: "const_c_variadic", + description: r##"# `const_c_variadic` -The tracking issue for this feature is: [#131283] +Allows defining and calling c-variadic functions in const contexts. -[#131283]: https://github.com/rust-lang/rust/issues/131283 +The tracking issue for this feature is: [#151787] + +[#151787]: https://github.com/rust-lang/rust/issues/151787 ------------------------ "##, @@ -4402,12 +5125,46 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_char_classify", - description: r##"# `const_char_classify` + label: "const_carrying_mul_add", + description: r##"# `const_carrying_mul_add` -The tracking issue for this feature is: [#132241] -[#132241]: https://github.com/rust-lang/rust/issues/132241 + +The tracking issue for this feature is: [#85532] + +[#85532]: https://github.com/rust-lang/rust/issues/85532 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_cell_traits", + description: r##"# `const_cell_traits` + + + +The tracking issue for this feature is: [#147787] + +[#147787]: https://github.com/rust-lang/rust/issues/147787 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_clone", + description: r##"# `const_clone` + + + +The tracking issue for this feature is: [#142757] + +[#142757]: https://github.com/rust-lang/rust/issues/142757 ------------------------ "##, @@ -4419,6 +5176,8 @@ fn foobar() -> u32 { 23 } label: "const_closures", description: r##"# `const_closures` +Allows `const || {}` closures in const contexts. + The tracking issue for this feature is: [#106003] [#106003]: https://github.com/rust-lang/rust/issues/106003 @@ -4430,12 +5189,62 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_copy_from_slice", - description: r##"# `const_copy_from_slice` + label: "const_cmp", + description: r##"# `const_cmp` -The tracking issue for this feature is: [#131415] -[#131415]: https://github.com/rust-lang/rust/issues/131415 + +The tracking issue for this feature is: [#143800] + +[#143800]: https://github.com/rust-lang/rust/issues/143800 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_control_flow", + description: r##"# `const_control_flow` + + + +The tracking issue for this feature is: [#148739] + +[#148739]: https://github.com/rust-lang/rust/issues/148739 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_convert", + description: r##"# `const_convert` + + + +The tracking issue for this feature is: [#143773] + +[#143773]: https://github.com/rust-lang/rust/issues/143773 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_default", + description: r##"# `const_default` + + + +The tracking issue for this feature is: [#143894] + +[#143894]: https://github.com/rust-lang/rust/issues/143894 ------------------------ "##, @@ -4447,10 +5256,42 @@ fn foobar() -> u32 { 23 } label: "const_destruct", description: r##"# `const_destruct` +Allows using `[const] Destruct` bounds and calling drop impls in const contexts. + The tracking issue for this feature is: [#133214] [#133214]: https://github.com/rust-lang/rust/issues/133214 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_drop_guard", + description: r##"# `const_drop_guard` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_drop_in_place", + description: r##"# `const_drop_in_place` + + + +The tracking issue for this feature is: [#109342] + +[#109342]: https://github.com/rust-lang/rust/issues/109342 + ------------------------ "##, default_severity: Severity::Allow, @@ -4461,6 +5302,8 @@ fn foobar() -> u32 { 23 } label: "const_eval_select", description: r##"# `const_eval_select` + + The tracking issue for this feature is: [#124625] [#124625]: https://github.com/rust-lang/rust/issues/124625 @@ -4475,6 +5318,8 @@ fn foobar() -> u32 { 23 } label: "const_for", description: r##"# `const_for` +Allows `for _ in _` loops in const contexts. + The tracking issue for this feature is: [#87575] [#87575]: https://github.com/rust-lang/rust/issues/87575 @@ -4489,6 +5334,8 @@ fn foobar() -> u32 { 23 } label: "const_format_args", description: r##"# `const_format_args` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -4501,6 +5348,8 @@ fn foobar() -> u32 { 23 } label: "const_heap", description: r##"# `const_heap` + + The tracking issue for this feature is: [#79597] [#79597]: https://github.com/rust-lang/rust/issues/79597 @@ -4512,12 +5361,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_is_char_boundary", - description: r##"# `const_is_char_boundary` + label: "const_index", + description: r##"# `const_index` -The tracking issue for this feature is: [#131516] -[#131516]: https://github.com/rust-lang/rust/issues/131516 + +The tracking issue for this feature is: [#143775] + +[#143775]: https://github.com/rust-lang/rust/issues/143775 ------------------------ "##, @@ -4526,12 +5377,124 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_mut_cursor", - description: r##"# `const_mut_cursor` + label: "const_iter", + description: r##"# `const_iter` -The tracking issue for this feature is: [#130801] -[#130801]: https://github.com/rust-lang/rust/issues/130801 + +The tracking issue for this feature is: [#92476] + +[#92476]: https://github.com/rust-lang/rust/issues/92476 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_manually_drop_take", + description: r##"# `const_manually_drop_take` + + + +The tracking issue for this feature is: [#148773] + +[#148773]: https://github.com/rust-lang/rust/issues/148773 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_never_short_circuit", + description: r##"# `const_never_short_circuit` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_nonnull_with_exposed_provenance", + description: r##"# `const_nonnull_with_exposed_provenance` + + + +The tracking issue for this feature is: [#154215] + +[#154215]: https://github.com/rust-lang/rust/issues/154215 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_ops", + description: r##"# `const_ops` + + + +The tracking issue for this feature is: [#143802] + +[#143802]: https://github.com/rust-lang/rust/issues/143802 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_option_ops", + description: r##"# `const_option_ops` + + + +The tracking issue for this feature is: [#143956] + +[#143956]: https://github.com/rust-lang/rust/issues/143956 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_param_ty_trait", + description: r##"# `const_param_ty_trait` + + + +The tracking issue for this feature is: [#95174] + +[#95174]: https://github.com/rust-lang/rust/issues/95174 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_path_separators", + description: r##"# `const_path_separators` + + + +The tracking issue for this feature is: [#153106] + +[#153106]: https://github.com/rust-lang/rust/issues/153106 ------------------------ "##, @@ -4543,6 +5506,8 @@ fn foobar() -> u32 { 23 } label: "const_precise_live_drops", description: r##"# `const_precise_live_drops` +Be more precise when looking for live drops in a const context. + The tracking issue for this feature is: [#73255] [#73255]: https://github.com/rust-lang/rust/issues/73255 @@ -4554,12 +5519,12 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_ptr_sub_ptr", - description: r##"# `const_ptr_sub_ptr` + label: "const_range", + description: r##"# `const_range` -The tracking issue for this feature is: [#95892] -[#95892]: https://github.com/rust-lang/rust/issues/95892 + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -4571,6 +5536,8 @@ fn foobar() -> u32 { 23 } label: "const_range_bounds", description: r##"# `const_range_bounds` + + The tracking issue for this feature is: [#108082] [#108082]: https://github.com/rust-lang/rust/issues/108082 @@ -4585,6 +5552,8 @@ fn foobar() -> u32 { 23 } label: "const_raw_ptr_comparison", description: r##"# `const_raw_ptr_comparison` + + The tracking issue for this feature is: [#53020] [#53020]: https://github.com/rust-lang/rust/issues/53020 @@ -4596,12 +5565,62 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_slice_flatten", - description: r##"# `const_slice_flatten` + label: "const_ref_cell", + description: r##"# `const_ref_cell` -The tracking issue for this feature is: [#95629] -[#95629]: https://github.com/rust-lang/rust/issues/95629 + +The tracking issue for this feature is: [#137844] + +[#137844]: https://github.com/rust-lang/rust/issues/137844 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_result_trait_fn", + description: r##"# `const_result_trait_fn` + + + +The tracking issue for this feature is: [#144211] + +[#144211]: https://github.com/rust-lang/rust/issues/144211 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_result_unwrap_unchecked", + description: r##"# `const_result_unwrap_unchecked` + + + +The tracking issue for this feature is: [#148714] + +[#148714]: https://github.com/rust-lang/rust/issues/148714 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "const_select_unpredictable", + description: r##"# `const_select_unpredictable` + + + +The tracking issue for this feature is: [#145938] + +[#145938]: https://github.com/rust-lang/rust/issues/145938 ------------------------ "##, @@ -4613,6 +5632,8 @@ fn foobar() -> u32 { 23 } label: "const_slice_from_mut_ptr_range", description: r##"# `const_slice_from_mut_ptr_range` + + The tracking issue for this feature is: [#89792] [#89792]: https://github.com/rust-lang/rust/issues/89792 @@ -4627,6 +5648,8 @@ fn foobar() -> u32 { 23 } label: "const_slice_from_ptr_range", description: r##"# `const_slice_from_ptr_range` + + The tracking issue for this feature is: [#89792] [#89792]: https://github.com/rust-lang/rust/issues/89792 @@ -4638,12 +5661,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_sockaddr_setters", - description: r##"# `const_sockaddr_setters` + label: "const_slice_make_iter", + description: r##"# `const_slice_make_iter` -The tracking issue for this feature is: [#131714] -[#131714]: https://github.com/rust-lang/rust/issues/131714 + +The tracking issue for this feature is: [#137737] + +[#137737]: https://github.com/rust-lang/rust/issues/137737 ------------------------ "##, @@ -4652,12 +5677,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_str_from_utf8", - description: r##"# `const_str_from_utf8` + label: "const_split_off_first_last", + description: r##"# `const_split_off_first_last` -The tracking issue for this feature is: [#91006] -[#91006]: https://github.com/rust-lang/rust/issues/91006 + +The tracking issue for this feature is: [#138539] + +[#138539]: https://github.com/rust-lang/rust/issues/138539 ------------------------ "##, @@ -4666,40 +5693,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_str_split_at", - description: r##"# `const_str_split_at` + label: "const_swap_with_slice", + description: r##"# `const_swap_with_slice` -The tracking issue for this feature is: [#131518] -[#131518]: https://github.com/rust-lang/rust/issues/131518 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "const_swap", - description: r##"# `const_swap` +The tracking issue for this feature is: [#142204] -The tracking issue for this feature is: [#83163] - -[#83163]: https://github.com/rust-lang/rust/issues/83163 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "const_swap_nonoverlapping", - description: r##"# `const_swap_nonoverlapping` - -The tracking issue for this feature is: [#133668] - -[#133668]: https://github.com/rust-lang/rust/issues/133668 +[#142204]: https://github.com/rust-lang/rust/issues/142204 ------------------------ "##, @@ -4711,6 +5712,8 @@ fn foobar() -> u32 { 23 } label: "const_trait_impl", description: r##"# `const_trait_impl` +Allows `impl const Trait for T` syntax. + The tracking issue for this feature is: [#143874] [#143874]: https://github.com/rust-lang/rust/issues/143874 @@ -4725,6 +5728,8 @@ fn foobar() -> u32 { 23 } label: "const_try", description: r##"# `const_try` +Allows the `?` operator in const contexts. + The tracking issue for this feature is: [#74935] [#74935]: https://github.com/rust-lang/rust/issues/74935 @@ -4736,12 +5741,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_type_id", - description: r##"# `const_type_id` + label: "const_try_residual", + description: r##"# `const_try_residual` -The tracking issue for this feature is: [#77125] -[#77125]: https://github.com/rust-lang/rust/issues/77125 + +The tracking issue for this feature is: [#91285] + +[#91285]: https://github.com/rust-lang/rust/issues/91285 ------------------------ "##, @@ -4753,6 +5760,8 @@ fn foobar() -> u32 { 23 } label: "const_type_name", description: r##"# `const_type_name` + + The tracking issue for this feature is: [#63084] [#63084]: https://github.com/rust-lang/rust/issues/63084 @@ -4764,24 +5773,14 @@ fn foobar() -> u32 { 23 } deny_since: None, }, Lint { - label: "const_typed_swap", - description: r##"# `const_typed_swap` + label: "const_unsigned_bigint_helpers", + description: r##"# `const_unsigned_bigint_helpers` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "const_vec_string_slice", - description: r##"# `const_vec_string_slice` -The tracking issue for this feature is: [#129041] +The tracking issue for this feature is: [#152015] -[#129041]: https://github.com/rust-lang/rust/issues/129041 +[#152015]: https://github.com/rust-lang/rust/issues/152015 ------------------------ "##, @@ -4793,6 +5792,8 @@ fn foobar() -> u32 { 23 } label: "container_error_extra", description: r##"# `container_error_extra` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -4805,10 +5806,60 @@ fn foobar() -> u32 { 23 } label: "context_ext", description: r##"# `context_ext` + + The tracking issue for this feature is: [#123392] [#123392]: https://github.com/rust-lang/rust/issues/123392 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "contracts", + description: r##"# `contracts` + +Allows use of contracts attributes. + +The tracking issue for this feature is: [#128044] + +[#128044]: https://github.com/rust-lang/rust/issues/128044 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "contracts_internals", + description: r##"# `contracts_internals` + +Allows access to internal machinery used to implement contracts. + +The tracking issue for this feature is: [#128044] + +[#128044]: https://github.com/rust-lang/rust/issues/128044 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "control_flow_into_value", + description: r##"# `control_flow_into_value` + + + +The tracking issue for this feature is: [#137461] + +[#137461]: https://github.com/rust-lang/rust/issues/137461 + ------------------------ "##, default_severity: Severity::Allow, @@ -4819,10 +5870,42 @@ fn foobar() -> u32 { 23 } label: "convert_float_to_int", description: r##"# `convert_float_to_int` + + The tracking issue for this feature is: [#67057] [#67057]: https://github.com/rust-lang/rust/issues/67057 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "copied_into_inner", + description: r##"# `copied_into_inner` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "core_float_math", + description: r##"# `core_float_math` + + + +The tracking issue for this feature is: [#137578] + +[#137578]: https://github.com/rust-lang/rust/issues/137578 + ------------------------ "##, default_severity: Severity::Allow, @@ -4835,6 +5918,20 @@ fn foobar() -> u32 { 23 } This feature is internal to the Rust compiler and is not intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "core_intrinsics_fallbacks", + description: r##"# `core_intrinsics_fallbacks` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -4845,6 +5942,8 @@ fn foobar() -> u32 { 23 } label: "core_io_borrowed_buf", description: r##"# `core_io_borrowed_buf` + + The tracking issue for this feature is: [#117693] [#117693]: https://github.com/rust-lang/rust/issues/117693 @@ -4883,6 +5982,8 @@ fn foobar() -> u32 { 23 } label: "coroutine_clone", description: r##"# `coroutine_clone` +Allows coroutines to be cloned. + The tracking issue for this feature is: [#95360] [#95360]: https://github.com/rust-lang/rust/issues/95360 @@ -4897,6 +5998,8 @@ fn foobar() -> u32 { 23 } label: "coroutine_trait", description: r##"# `coroutine_trait` + + The tracking issue for this feature is: [#43122] [#43122]: https://github.com/rust-lang/rust/issues/43122 @@ -5202,6 +6305,8 @@ fn bar() { label: "cow_is_borrowed", description: r##"# `cow_is_borrowed` + + The tracking issue for this feature is: [#65143] [#65143]: https://github.com/rust-lang/rust/issues/65143 @@ -5216,9 +6321,11 @@ fn bar() { label: "csky_target_feature", description: r##"# `csky_target_feature` -The tracking issue for this feature is: [#44839] +Target features on csky. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150248] + +[#150248]: https://github.com/rust-lang/rust/issues/150248 ------------------------ "##, @@ -5230,10 +6337,28 @@ fn bar() { label: "cstr_bytes", description: r##"# `cstr_bytes` + + The tracking issue for this feature is: [#112115] [#112115]: https://github.com/rust-lang/rust/issues/112115 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "cstr_display", + description: r##"# `cstr_display` + + + +The tracking issue for this feature is: [#139984] + +[#139984]: https://github.com/rust-lang/rust/issues/139984 + ------------------------ "##, default_severity: Severity::Allow, @@ -5244,8 +6369,26 @@ fn bar() { label: "cstr_internals", description: r##"# `cstr_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "current_thread_id", + description: r##"# `current_thread_id` + + + +The tracking issue for this feature is: [#147194] + +[#147194]: https://github.com/rust-lang/rust/issues/147194 + ------------------------ "##, default_severity: Severity::Allow, @@ -5256,6 +6399,8 @@ fn bar() { label: "cursor_split", description: r##"# `cursor_split` + + The tracking issue for this feature is: [#86369] [#86369]: https://github.com/rust-lang/rust/issues/86369 @@ -5270,6 +6415,8 @@ fn bar() { label: "custom_inner_attributes", description: r##"# `custom_inner_attributes` +Allows non-builtin attributes in inner attribute position. + The tracking issue for this feature is: [#54726] [#54726]: https://github.com/rust-lang/rust/issues/54726 @@ -5284,6 +6431,8 @@ fn bar() { label: "custom_mir", description: r##"# `custom_mir` +Allows writing custom MIR + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -5326,6 +6475,22 @@ fn my_runner(tests: &[&i32]) { #[test_case] const WILL_FAIL: i32 = 4; ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "darwin_objc", + description: r##"# `darwin_objc` + + + +The tracking issue for this feature is: [#145496] + +[#145496]: https://github.com/rust-lang/rust/issues/145496 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -5335,6 +6500,8 @@ fn my_runner(tests: &[&i32]) { label: "deadline_api", description: r##"# `deadline_api` + + The tracking issue for this feature is: [#46316] [#46316]: https://github.com/rust-lang/rust/issues/46316 @@ -5349,6 +6516,8 @@ fn my_runner(tests: &[&i32]) { label: "debug_closure_helpers", description: r##"# `debug_closure_helpers` + + The tracking issue for this feature is: [#117729] [#117729]: https://github.com/rust-lang/rust/issues/117729 @@ -5375,6 +6544,8 @@ fn my_runner(tests: &[&i32]) { label: "decl_macro", description: r##"# `decl_macro` +Allows declarative macros 2.0 (`macro`). + The tracking issue for this feature is: [#39412] [#39412]: https://github.com/rust-lang/rust/issues/39412 @@ -5393,21 +6564,93 @@ fn my_runner(tests: &[&i32]) { [#132162]: https://github.com/rust-lang/rust/issues/132162 +The RFC for this feature is: [#3681] + +[#3681]: https://github.com/rust-lang/rfcs/blob/master/text/3681-default-field-values.md + ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, + +The `default_field_values` feature allows users to specify a const value for +individual fields in struct definitions, allowing those to be omitted from +initializers. + +## Examples + +```rust +#![feature(default_field_values)] + +#[derive(Default)] +struct Pet { + name: Option, // impl Default for Pet will use Default::default() for name + age: i128 = 42, // impl Default for Pet will use the literal 42 for age +} + +fn main() { + let a = Pet { name: Some(String::new()), .. }; // Pet { name: Some(""), age: 42 } + let b = Pet::default(); // Pet { name: None, age: 42 } + assert_eq!(a.age, b.age); + // The following would be a compilation error: `name` needs to be specified + // let _ = Pet { .. }; +} +``` + +## `#[derive(Default)]` + +When deriving Default, the provided values are then used. On enum variants, +the variant must still be marked with `#[default]` and have all its fields +with default values. + +```rust +#![feature(default_field_values)] + +#[derive(Default)] +enum A { + #[default] + B { + x: i32 = 0, + y: i32 = 0, }, - Lint { - label: "deprecated_safe", - description: r##"# `deprecated_safe` + C, +} +``` -The tracking issue for this feature is: [#94978] +## Enum variants -[#94978]: https://github.com/rust-lang/rust/issues/94978 +This feature also supports enum variants for both specifying default values +and `#[derive(Default)]`. ------------------------- +## Interaction with `#[non_exhaustive]` + +A struct or enum variant marked with `#[non_exhaustive]` is not allowed to +have default field values. + +## Lints + +When manually implementing the `Default` trait for a type that has default +field values, if any of these are overridden in the impl the +`default_overrides_default_fields` lint will trigger. This lint is in place +to avoid surprising diverging behavior between `S { .. }` and +`S::default()`, where using the same type in both ways could result in +different values. The appropriate way to write a manual `Default` +implementation is to use the functional update syntax: + +```rust +#![feature(default_field_values)] + +struct Pet { + name: String, + age: i128 = 42, // impl Default for Pet will use the literal 42 for age +} + +impl Default for Pet { + fn default() -> Pet { + Pet { + name: "no-name".to_string(), + .. + } + } +} +``` "##, default_severity: Severity::Allow, warn_since: None, @@ -5417,10 +6660,28 @@ fn my_runner(tests: &[&i32]) { label: "deprecated_suggestion", description: r##"# `deprecated_suggestion` +Allows having using `suggestion` in the `#[deprecated]` attribute. + The tracking issue for this feature is: [#94785] [#94785]: https://github.com/rust-lang/rust/issues/94785 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "deque_extend_front", + description: r##"# `deque_extend_front` + + + +The tracking issue for this feature is: [#146975] + +[#146975]: https://github.com/rust-lang/rust/issues/146975 + ------------------------ "##, default_severity: Severity::Allow, @@ -5436,6 +6697,101 @@ fn my_runner(tests: &[&i32]) { [#87121]: https://github.com/rust-lang/rust/issues/87121 ------------------------ + +> **Note**: This feature supersedes [`box_patterns`]. + +This feature permits pattern matching on [smart pointers in the standard library] through their +`Deref` target types, either implicitly or with explicit `deref!(_)` patterns (the syntax of which +is currently a placeholder). + +```rust +#![feature(deref_patterns)] + +let mut v = vec![Box::new(Some(0))]; + +// Implicit dereferences are inserted when a pattern can match against the +// result of repeatedly dereferencing but can't match against a smart +// pointer itself. This works alongside match ergonomics for references. +if let [Some(x)] = &mut v { + *x += 1; +} + +// Explicit `deref!(_)` patterns may instead be used when finer control is +// needed, e.g. to dereference only a single smart pointer, or to bind the +// the result of dereferencing to a variable. +if let deref!([deref!(opt_x @ Some(1))]) = &mut v { + opt_x.as_mut().map(|x| *x += 1); +} + +assert_eq!(v, [Box::new(Some(2))]); +``` + +Without this feature, it may be necessary to introduce temporaries to represent dereferenced places +when matching on nested structures: + +```rust +let mut v = vec![Box::new(Some(0))]; +if let [b] = &mut *v { + if let Some(x) = &mut **b { + *x += 1; + } +} +if let [b] = &mut *v { + if let opt_x @ Some(1) = &mut **b { + opt_x.as_mut().map(|x| *x += 1); + } +} +assert_eq!(v, [Box::new(Some(2))]); +``` + +Like [`box_patterns`], deref patterns may move out of boxes: + +```rust +# #![feature(deref_patterns)] +struct NoCopy; +let deref!(x) = Box::new(NoCopy); +drop::(x); +``` + +Additionally, `deref_patterns` implements changes to string and byte string literal patterns, +allowing then to be used in deref patterns: + +```rust +# #![feature(deref_patterns)] +match ("test".to_string(), Box::from("test"), b"test".to_vec()) { + ("test", "test", b"test") => {} + _ => panic!(), +} + +// This works through multiple layers of reference and smart pointer: +match (&Box::new(&"test".to_string()), &&&"test") { + ("test", "test") => {} + _ => panic!(), +} + +// `deref!("...")` syntax may also be used: +match "test".to_string() { + deref!("test") => {} + _ => panic!(), +} + +// Matching on slices and arrays using literals is possible elsewhere as well: +match *"test" { + "test" => {} + _ => panic!(), +} +match *b"test" { + b"test" => {} + _ => panic!(), +} +match *(b"test" as &[u8]) { + b"test" => {} + _ => panic!(), +} +``` + +[`box_patterns`]: ./box-patterns.md +[smart pointers in the standard library]: https://doc.rust-lang.org/std/ops/trait.DerefPure.html#implementors "##, default_severity: Severity::Allow, warn_since: None, @@ -5445,6 +6801,8 @@ fn my_runner(tests: &[&i32]) { label: "deref_pure_trait", description: r##"# `deref_pure_trait` + + The tracking issue for this feature is: [#87121] [#87121]: https://github.com/rust-lang/rust/issues/87121 @@ -5456,8 +6814,8 @@ fn my_runner(tests: &[&i32]) { deny_since: None, }, Lint { - label: "derive_clone_copy", - description: r##"# `derive_clone_copy` + label: "derive_clone_copy_internals", + description: r##"# `derive_clone_copy_internals` This feature is internal to the Rust compiler and is not intended for general use. @@ -5471,6 +6829,8 @@ fn my_runner(tests: &[&i32]) { label: "derive_coerce_pointee", description: r##"# `derive_coerce_pointee` + + The tracking issue for this feature is: [#123430] [#123430]: https://github.com/rust-lang/rust/issues/123430 @@ -5485,7 +6845,11 @@ fn my_runner(tests: &[&i32]) { label: "derive_const", description: r##"# `derive_const` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + + +The tracking issue for this feature is: [#118304] + +[#118304]: https://github.com/rust-lang/rust/issues/118304 ------------------------ "##, @@ -5494,11 +6858,75 @@ fn my_runner(tests: &[&i32]) { deny_since: None, }, Lint { - label: "derive_eq", - description: r##"# `derive_eq` + label: "derive_eq_internals", + description: r##"# `derive_eq_internals` This feature is internal to the Rust compiler and is not intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "derive_from", + description: r##"# `derive_from` + +Allows deriving the From trait on single-field structs. + +The tracking issue for this feature is: [#144889] + +[#144889]: https://github.com/rust-lang/rust/issues/144889 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "derive_macro_global_path", + description: r##"# `derive_macro_global_path` + + + +The tracking issue for this feature is: [#154645] + +[#154645]: https://github.com/rust-lang/rust/issues/154645 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "diagnostic_on_const", + description: r##"# `diagnostic_on_const` + +Allows giving non-const impls custom diagnostic messages if attempted to be used as const + +The tracking issue for this feature is: [#143874] + +[#143874]: https://github.com/rust-lang/rust/issues/143874 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "diagnostic_on_move", + description: r##"# `diagnostic_on_move` + +Allows giving on-move borrowck custom diagnostic messages for a type + +The tracking issue for this feature is: [#154181] + +[#154181]: https://github.com/rust-lang/rust/issues/154181 + ------------------------ "##, default_severity: Severity::Allow, @@ -5509,10 +6937,44 @@ fn my_runner(tests: &[&i32]) { label: "dir_entry_ext2", description: r##"# `dir_entry_ext2` + + The tracking issue for this feature is: [#85573] [#85573]: https://github.com/rust-lang/rust/issues/85573 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "dirfd", + description: r##"# `dirfd` + + + +The tracking issue for this feature is: [#120426] + +[#120426]: https://github.com/rust-lang/rust/issues/120426 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "dirhandle", + description: r##"# `dirhandle` + + + +The tracking issue for this feature is: [#120426] + +[#120426]: https://github.com/rust-lang/rust/issues/120426 + ------------------------ "##, default_severity: Severity::Allow, @@ -5523,8 +6985,26 @@ fn my_runner(tests: &[&i32]) { label: "discriminant_kind", description: r##"# `discriminant_kind` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "disjoint_bitor", + description: r##"# `disjoint_bitor` + + + +The tracking issue for this feature is: [#135758] + +[#135758]: https://github.com/rust-lang/rust/issues/135758 + ------------------------ "##, default_severity: Severity::Allow, @@ -5535,36 +7015,10 @@ fn my_runner(tests: &[&i32]) { label: "dispatch_from_dyn", description: r##"# `dispatch_from_dyn` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "do_not_recommend", - description: r##"# `do_not_recommend` - -The tracking issue for this feature is: [#51992] - -[#51992]: https://github.com/rust-lang/rust/issues/51992 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "doc_auto_cfg", - description: r##"# `doc_auto_cfg` - -The tracking issue for this feature is: [#43781] - -[#43781]: https://github.com/rust-lang/rust/issues/43781 - ------------------------ "##, default_severity: Severity::Allow, @@ -5619,20 +7073,6 @@ pub struct Icon { [#43781]: https://github.com/rust-lang/rust/issues/43781 [#43348]: https://github.com/rust-lang/rust/issues/43348 -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "doc_cfg_hide", - description: r##"# `doc_cfg_hide` - -The tracking issue for this feature is: [#43781] - -[#43781]: https://github.com/rust-lang/rust/issues/43781 - ------------------------- "##, default_severity: Severity::Allow, warn_since: None, @@ -5713,6 +7153,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "downcast_unchecked", description: r##"# `downcast_unchecked` + + The tracking issue for this feature is: [#90850] [#90850]: https://github.com/rust-lang/rust/issues/90850 @@ -5727,10 +7169,28 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "drain_keep_rest", description: r##"# `drain_keep_rest` + + The tracking issue for this feature is: [#101122] [#101122]: https://github.com/rust-lang/rust/issues/101122 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "drop_guard", + description: r##"# `drop_guard` + + + +The tracking issue for this feature is: [#144426] + +[#144426]: https://github.com/rust-lang/rust/issues/144426 + ------------------------ "##, default_severity: Severity::Allow, @@ -5741,6 +7201,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "dropck_eyepatch", description: r##"# `dropck_eyepatch` +Allows using the `may_dangle` attribute (RFC 1327). + The tracking issue for this feature is: [#34761] [#34761]: https://github.com/rust-lang/rust/issues/34761 @@ -5755,6 +7217,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "duration_constants", description: r##"# `duration_constants` + + The tracking issue for this feature is: [#57391] [#57391]: https://github.com/rust-lang/rust/issues/57391 @@ -5776,6 +7240,22 @@ pub fn my_fn() -> MyStruct { MyStruct } ------------------------ Add the methods `from_days` and `from_weeks` to `Duration`. +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "duration_integer_division", + description: r##"# `duration_integer_division` + + + +The tracking issue for this feature is: [#149573] + +[#149573]: https://github.com/rust-lang/rust/issues/149573 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -5785,6 +7265,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "duration_millis_float", description: r##"# `duration_millis_float` + + The tracking issue for this feature is: [#122451] [#122451]: https://github.com/rust-lang/rust/issues/122451 @@ -5799,38 +7281,12 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "duration_units", description: r##"# `duration_units` + + The tracking issue for this feature is: [#120301] [#120301]: https://github.com/rust-lang/rust/issues/120301 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "dyn_compatible_for_dispatch", - description: r##"# `dyn_compatible_for_dispatch` - -The tracking issue for this feature is: [#43561] - -[#43561]: https://github.com/rust-lang/rust/issues/43561 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "dyn_star", - description: r##"# `dyn_star` - -The tracking issue for this feature is: [#102425] - -[#102425]: https://github.com/rust-lang/rust/issues/102425 - ------------------------ "##, default_severity: Severity::Allow, @@ -5841,8 +7297,56 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "edition_panic", description: r##"# `edition_panic` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "effective_target_features", + description: r##"# `effective_target_features` + +Allows features to allow target_feature to better interact with traits. + +The tracking issue for this feature is: [#143352] + +[#143352]: https://github.com/rust-lang/rust/issues/143352 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "eii_internals", + description: r##"# `eii_internals` + +Implementation details of externally implementable items + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "ergonomic_clones", + description: r##"# `ergonomic_clones` + +Allows the .use postfix syntax `x.use` and use closures `use |x| { ... }` + +The tracking issue for this feature is: [#132290] + +[#132290]: https://github.com/rust-lang/rust/issues/132290 + ------------------------ "##, default_severity: Severity::Allow, @@ -5853,9 +7357,11 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "ermsb_target_feature", description: r##"# `ermsb_target_feature` -The tracking issue for this feature is: [#44839] +ermsb target feature on x86. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150249] + +[#150249]: https://github.com/rust-lang/rust/issues/150249 ------------------------ "##, @@ -5867,6 +7373,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "error_generic_member_access", description: r##"# `error_generic_member_access` + + The tracking issue for this feature is: [#99301] [#99301]: https://github.com/rust-lang/rust/issues/99301 @@ -5881,6 +7389,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "error_iter", description: r##"# `error_iter` + + The tracking issue for this feature is: [#58520] [#58520]: https://github.com/rust-lang/rust/issues/58520 @@ -5895,6 +7405,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "error_reporter", description: r##"# `error_reporter` + + The tracking issue for this feature is: [#90172] [#90172]: https://github.com/rust-lang/rust/issues/90172 @@ -5909,10 +7421,44 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "error_type_id", description: r##"# `error_type_id` + + The tracking issue for this feature is: [#60784] [#60784]: https://github.com/rust-lang/rust/issues/60784 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "exact_bitshifts", + description: r##"# `exact_bitshifts` + + + +The tracking issue for this feature is: [#144336] + +[#144336]: https://github.com/rust-lang/rust/issues/144336 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "exact_div", + description: r##"# `exact_div` + + + +The tracking issue for this feature is: [#139911] + +[#139911]: https://github.com/rust-lang/rust/issues/139911 + ------------------------ "##, default_severity: Severity::Allow, @@ -5923,6 +7469,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "exact_size_is_empty", description: r##"# `exact_size_is_empty` + + The tracking issue for this feature is: [#35428] [#35428]: https://github.com/rust-lang/rust/issues/35428 @@ -5937,6 +7485,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "exclusive_wrapper", description: r##"# `exclusive_wrapper` + + The tracking issue for this feature is: [#98407] [#98407]: https://github.com/rust-lang/rust/issues/98407 @@ -5951,6 +7501,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "exhaustive_patterns", description: r##"# `exhaustive_patterns` +Allows exhaustive pattern matching on types that contain uninhabited types. + The tracking issue for this feature is: [#51085] [#51085]: https://github.com/rust-lang/rust/issues/51085 @@ -5965,6 +7517,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "exit_status_error", description: r##"# `exit_status_error` + + The tracking issue for this feature is: [#84908] [#84908]: https://github.com/rust-lang/rust/issues/84908 @@ -5979,11 +7533,45 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "exitcode_exit_method", description: r##"# `exitcode_exit_method` + + The tracking issue for this feature is: [#97100] [#97100]: https://github.com/rust-lang/rust/issues/97100 ------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "explicit_extern_abis", + description: r##"# `explicit_extern_abis` + +The tracking issue for this feature is: [#134986] + +------ + +Disallow `extern` without an explicit ABI. We should write `extern "C"` +(or another ABI) instead of just `extern`. + +By making the ABI explicit, it becomes much clearer that "C" is just one of the +possible choices, rather than the "standard" way for external functions. +Removing the default makes it easier to add a new ABI on equal footing as "C". + +```rust,editionfuture,compile_fail +#![feature(explicit_extern_abis)] + +extern fn function1() {} // ERROR `extern` declarations without an explicit ABI + // are disallowed + +extern "C" fn function2() {} // compiles + +extern "aapcs" fn function3() {} // compiles +``` + +[#134986]: https://github.com/rust-lang/rust/issues/134986 "##, default_severity: Severity::Allow, warn_since: None, @@ -5993,10 +7581,28 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "explicit_tail_calls", description: r##"# `explicit_tail_calls` +Allows explicit tail calls via `become` expression. + The tracking issue for this feature is: [#112788] [#112788]: https://github.com/rust-lang/rust/issues/112788 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "export_stable", + description: r##"# `export_stable` + +Allows using `#[export_stable]` which indicates that an item is exportable. + +The tracking issue for this feature is: [#139939] + +[#139939]: https://github.com/rust-lang/rust/issues/139939 + ------------------------ "##, default_severity: Severity::Allow, @@ -6007,6 +7613,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "extend_one", description: r##"# `extend_one` + + The tracking issue for this feature is: [#72631] [#72631]: https://github.com/rust-lang/rust/issues/72631 @@ -6021,8 +7629,26 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "extend_one_unchecked", description: r##"# `extend_one_unchecked` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "extern_item_impls", + description: r##"# `extern_item_impls` + +Externally implementable items + +The tracking issue for this feature is: [#125418] + +[#125418]: https://github.com/rust-lang/rust/issues/125418 + ------------------------ "##, default_severity: Severity::Allow, @@ -6033,24 +7659,12 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "extern_types", description: r##"# `extern_types` +Allows defining `extern type`s. + The tracking issue for this feature is: [#43467] [#43467]: https://github.com/rust-lang/rust/issues/43467 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "extract_if", - description: r##"# `extract_if` - -The tracking issue for this feature is: [#43244] - -[#43244]: https://github.com/rust-lang/rust/issues/43244 - ------------------------ "##, default_severity: Severity::Allow, @@ -6067,7 +7681,7 @@ pub fn my_fn() -> MyStruct { MyStruct } --- -Enable the `f128` type for IEEE 128-bit floating numbers (quad precision). +Enable the `f128` type for IEEE 128-bit floating numbers (quad precision). "##, default_severity: Severity::Allow, warn_since: None, @@ -6083,7 +7697,7 @@ pub fn my_fn() -> MyStruct { MyStruct } --- -Enable the `f16` type for IEEE 16-bit floating numbers (half precision). +Enable the `f16` type for IEEE 16-bit floating numbers (half precision). "##, default_severity: Severity::Allow, warn_since: None, @@ -6095,18 +7709,6 @@ pub fn my_fn() -> MyStruct { MyStruct } This feature is internal to the Rust compiler and is not intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "fd_read", - description: r##"# `fd_read` - -This feature is internal to the Rust compiler and is not intended for general use. - ------------------------ "##, default_severity: Severity::Allow, @@ -6230,6 +7832,36 @@ pub fn my_fn() -> MyStruct { MyStruct } [ARM C/C++ compiler]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/Cacigdac.html [GCC]: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-pure-function-attribute [IBM ILE C/C++]: https://www.ibm.com/support/knowledgecenter/fr/ssw_ibm_i_71/rzarg/fn_attrib_pure.htm +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "field_projections", + description: r##"# `field_projections` + +Experimental field projections. + +The tracking issue for this feature is: [#145383] + +[#145383]: https://github.com/rust-lang/rust/issues/145383 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "field_representing_type_raw", + description: r##"# `field_representing_type_raw` + +Implementation details of field representing types. + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -6239,6 +7871,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "file_buffered", description: r##"# `file_buffered` + + The tracking issue for this feature is: [#130804] [#130804]: https://github.com/rust-lang/rust/issues/130804 @@ -6250,12 +7884,78 @@ pub fn my_fn() -> MyStruct { MyStruct } deny_since: None, }, Lint { - label: "file_lock", - description: r##"# `file_lock` + label: "final_associated_functions", + description: r##"# `final_associated_functions` -The tracking issue for this feature is: [#130994] +Allows marking trait functions as `final` to prevent overriding impls -[#130994]: https://github.com/rust-lang/rust/issues/130994 +The tracking issue for this feature is: [#131179] + +[#131179]: https://github.com/rust-lang/rust/issues/131179 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "float_algebraic", + description: r##"# `float_algebraic` + + + +The tracking issue for this feature is: [#136469] + +[#136469]: https://github.com/rust-lang/rust/issues/136469 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "float_bits_const", + description: r##"# `float_bits_const` + + + +The tracking issue for this feature is: [#151073] + +[#151073]: https://github.com/rust-lang/rust/issues/151073 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "float_erf", + description: r##"# `float_erf` + + + +The tracking issue for this feature is: [#136321] + +[#136321]: https://github.com/rust-lang/rust/issues/136321 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "float_exact_integer_constants", + description: r##"# `float_exact_integer_constants` + + + +The tracking issue for this feature is: [#152466] + +[#152466]: https://github.com/rust-lang/rust/issues/152466 ------------------------ "##, @@ -6267,6 +7967,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "float_gamma", description: r##"# `float_gamma` + + The tracking issue for this feature is: [#99842] [#99842]: https://github.com/rust-lang/rust/issues/99842 @@ -6281,24 +7983,12 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "float_minimum_maximum", description: r##"# `float_minimum_maximum` + + The tracking issue for this feature is: [#91079] [#91079]: https://github.com/rust-lang/rust/issues/91079 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "float_next_up_down", - description: r##"# `float_next_up_down` - -The tracking issue for this feature is: [#91399] - -[#91399]: https://github.com/rust-lang/rust/issues/91399 - ------------------------ "##, default_severity: Severity::Allow, @@ -6311,6 +8001,22 @@ pub fn my_fn() -> MyStruct { MyStruct } This feature is internal to the Rust compiler and is not intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "fmt_arguments_from_str", + description: r##"# `fmt_arguments_from_str` + + + +The tracking issue for this feature is: [#148905] + +[#148905]: https://github.com/rust-lang/rust/issues/148905 + ------------------------ "##, default_severity: Severity::Allow, @@ -6321,6 +8027,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "fmt_debug", description: r##"# `fmt_debug` +Controlling the behavior of fmt::Debug + The tracking issue for this feature is: [#129709] [#129709]: https://github.com/rust-lang/rust/issues/129709 @@ -6335,6 +8043,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "fmt_helpers_for_derive", description: r##"# `fmt_helpers_for_derive` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6359,6 +8069,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "fn_align", description: r##"# `fn_align` +Allows using `#[align(...)]` on function items + The tracking issue for this feature is: [#82232] [#82232]: https://github.com/rust-lang/rust/issues/82232 @@ -6373,6 +8085,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "fn_delegation", description: r##"# `fn_delegation` +Support delegating implementation of functions to other already implemented functions. + The tracking issue for this feature is: [#118212] [#118212]: https://github.com/rust-lang/rust/issues/118212 @@ -6387,6 +8101,8 @@ pub fn my_fn() -> MyStruct { MyStruct } label: "fn_ptr_trait", description: r##"# `fn_ptr_trait` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6441,6 +8157,8 @@ fn main() { label: "forget_unsized", description: r##"# `forget_unsized` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6453,6 +8171,8 @@ fn main() { label: "format_args_nl", description: r##"# `format_args_nl` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6465,6 +8185,8 @@ fn main() { label: "formatting_options", description: r##"# `formatting_options` + + The tracking issue for this feature is: [#118117] [#118117]: https://github.com/rust-lang/rust/issues/118117 @@ -6479,6 +8201,8 @@ fn main() { label: "freeze", description: r##"# `freeze` + + The tracking issue for this feature is: [#121675] [#121675]: https://github.com/rust-lang/rust/issues/121675 @@ -6493,10 +8217,60 @@ fn main() { label: "freeze_impls", description: r##"# `freeze_impls` +Allows impls for the Freeze trait. + The tracking issue for this feature is: [#121675] [#121675]: https://github.com/rust-lang/rust/issues/121675 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "frontmatter", + description: r##"# `frontmatter` + +The tracking issue for this feature is: [#136889] + +------ + +The `frontmatter` feature allows an extra metadata block at the top of files for consumption by +external tools. For example, it can be used by [`cargo-script`] files to specify dependencies. + +```rust +#!/usr/bin/env -S cargo -Zscript +--- +[dependencies] +libc = "0.2.172" +--- +#![feature(frontmatter)] +# mod libc { pub type c_int = i32; } + +fn main() { + let x: libc::c_int = 1i32; +} +``` + +[#136889]: https://github.com/rust-lang/rust/issues/136889 +[`cargo-script`]: https://rust-lang.github.io/rfcs/3502-cargo-script.html +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "fs_set_times", + description: r##"# `fs_set_times` + + + +The tracking issue for this feature is: [#147455] + +[#147455]: https://github.com/rust-lang/rust/issues/147455 + ------------------------ "##, default_severity: Severity::Allow, @@ -6507,10 +8281,28 @@ fn main() { label: "fundamental", description: r##"# `fundamental` +Allows using the `#[fundamental]` attribute. + The tracking issue for this feature is: [#29635] [#29635]: https://github.com/rust-lang/rust/issues/29635 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "funnel_shifts", + description: r##"# `funnel_shifts` + + + +The tracking issue for this feature is: [#145686] + +[#145686]: https://github.com/rust-lang/rust/issues/145686 + ------------------------ "##, default_severity: Severity::Allow, @@ -6521,6 +8313,8 @@ fn main() { label: "future_join", description: r##"# `future_join` + + The tracking issue for this feature is: [#91642] [#91642]: https://github.com/rust-lang/rust/issues/91642 @@ -6535,6 +8329,8 @@ fn main() { label: "gen_blocks", description: r##"# `gen_blocks` +Allows defining gen blocks and `gen fn`. + The tracking issue for this feature is: [#117078] [#117078]: https://github.com/rust-lang/rust/issues/117078 @@ -6549,23 +8345,9 @@ fn main() { label: "gen_future", description: r##"# `gen_future` -The tracking issue for this feature is: [#50547] -[#50547]: https://github.com/rust-lang/rust/issues/50547 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "generic_arg_infer", - description: r##"# `generic_arg_infer` - -The tracking issue for this feature is: [#85077] - -[#85077]: https://github.com/rust-lang/rust/issues/85077 +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -6577,6 +8359,8 @@ fn main() { label: "generic_assert", description: r##"# `generic_assert` +Outputs useful `assert!` messages + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6589,10 +8373,44 @@ fn main() { label: "generic_assert_internals", description: r##"# `generic_assert_internals` + + The tracking issue for this feature is: [#44838] [#44838]: https://github.com/rust-lang/rust/issues/44838 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "generic_atomic", + description: r##"# `generic_atomic` + + + +The tracking issue for this feature is: [#130539] + +[#130539]: https://github.com/rust-lang/rust/issues/130539 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "generic_const_args", + description: r##"# `generic_const_args` + +Allows using generics in more complex const expressions, based on definitional equality. + +The tracking issue for this feature is: [#151972] + +[#151972]: https://github.com/rust-lang/rust/issues/151972 + ------------------------ "##, default_severity: Severity::Allow, @@ -6603,6 +8421,8 @@ fn main() { label: "generic_const_exprs", description: r##"# `generic_const_exprs` +Allows non-trivial generic constants which have to have wfness manually propagated to callers + The tracking issue for this feature is: [#76560] [#76560]: https://github.com/rust-lang/rust/issues/76560 @@ -6617,6 +8437,8 @@ fn main() { label: "generic_const_items", description: r##"# `generic_const_items` +Allows generic parameters and where-clauses on free & associated const items. + The tracking issue for this feature is: [#113521] [#113521]: https://github.com/rust-lang/rust/issues/113521 @@ -6628,12 +8450,14 @@ fn main() { deny_since: None, }, Lint { - label: "get_many_mut", - description: r##"# `get_many_mut` + label: "generic_const_parameter_types", + description: r##"# `generic_const_parameter_types` -The tracking issue for this feature is: [#104642] +Allows the type of const generics to depend on generic parameters -[#104642]: https://github.com/rust-lang/rust/issues/104642 +The tracking issue for this feature is: [#137626] + +[#137626]: https://github.com/rust-lang/rust/issues/137626 ------------------------ "##, @@ -6642,8 +8466,26 @@ fn main() { deny_since: None, }, Lint { - label: "get_many_mut_helpers", - description: r##"# `get_many_mut_helpers` + label: "generic_pattern_types", + description: r##"# `generic_pattern_types` + +Allows any generic constants being used as pattern type range ends + +The tracking issue for this feature is: [#136574] + +[#136574]: https://github.com/rust-lang/rust/issues/136574 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "get_disjoint_mut_helpers", + description: r##"# `get_disjoint_mut_helpers` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. @@ -6657,10 +8499,28 @@ fn main() { label: "get_mut_unchecked", description: r##"# `get_mut_unchecked` + + The tracking issue for this feature is: [#63292] [#63292]: https://github.com/rust-lang/rust/issues/63292 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "gethostname", + description: r##"# `gethostname` + + + +The tracking issue for this feature is: [#135142] + +[#135142]: https://github.com/rust-lang/rust/issues/135142 + ------------------------ "##, default_severity: Severity::Allow, @@ -6671,10 +8531,26 @@ fn main() { label: "global_registration", description: r##"# `global_registration` +Allows registering static items globally, possibly across crates, to iterate over at runtime. + The tracking issue for this feature is: [#125119] [#125119]: https://github.com/rust-lang/rust/issues/125119 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "gpu_intrinsics", + description: r##"# `gpu_intrinsics` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -6685,6 +8561,8 @@ fn main() { label: "guard_patterns", description: r##"# `guard_patterns` +Allows using guards in patterns. + The tracking issue for this feature is: [#129967] [#129967]: https://github.com/rust-lang/rust/issues/129967 @@ -6732,12 +8610,12 @@ fn main() { deny_since: None, }, Lint { - label: "hash_extract_if", - description: r##"# `hash_extract_if` + label: "hash_map_internals", + description: r##"# `hash_map_internals` -The tracking issue for this feature is: [#59618] -[#59618]: https://github.com/rust-lang/rust/issues/59618 + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -6746,12 +8624,14 @@ fn main() { deny_since: None, }, Lint { - label: "hash_raw_entry", - description: r##"# `hash_raw_entry` + label: "hash_map_macro", + description: r##"# `hash_map_macro` -The tracking issue for this feature is: [#56167] -[#56167]: https://github.com/rust-lang/rust/issues/56167 + +The tracking issue for this feature is: [#144032] + +[#144032]: https://github.com/rust-lang/rust/issues/144032 ------------------------ "##, @@ -6763,6 +8643,8 @@ fn main() { label: "hash_set_entry", description: r##"# `hash_set_entry` + + The tracking issue for this feature is: [#60896] [#60896]: https://github.com/rust-lang/rust/issues/60896 @@ -6777,6 +8659,8 @@ fn main() { label: "hasher_prefixfree_extras", description: r##"# `hasher_prefixfree_extras` + + The tracking issue for this feature is: [#96762] [#96762]: https://github.com/rust-lang/rust/issues/96762 @@ -6791,6 +8675,8 @@ fn main() { label: "hashmap_internals", description: r##"# `hashmap_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -6803,9 +8689,11 @@ fn main() { label: "hexagon_target_feature", description: r##"# `hexagon_target_feature` -The tracking issue for this feature is: [#44839] +Target features on hexagon. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150250] + +[#150250]: https://github.com/rust-lang/rust/issues/150250 ------------------------ "##, @@ -6817,6 +8705,8 @@ fn main() { label: "hint_must_use", description: r##"# `hint_must_use` + + The tracking issue for this feature is: [#94745] [#94745]: https://github.com/rust-lang/rust/issues/94745 @@ -6828,12 +8718,30 @@ fn main() { deny_since: None, }, Lint { - label: "if_let_guard", - description: r##"# `if_let_guard` + label: "hint_prefetch", + description: r##"# `hint_prefetch` -The tracking issue for this feature is: [#51114] -[#51114]: https://github.com/rust-lang/rust/issues/51114 + +The tracking issue for this feature is: [#146941] + +[#146941]: https://github.com/rust-lang/rust/issues/146941 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "impl_restriction", + description: r##"# `impl_restriction` + +Allows `impl(crate) trait Foo` restrictions. + +The tracking issue for this feature is: [#105077] + +[#105077]: https://github.com/rust-lang/rust/issues/105077 ------------------------ "##, @@ -6845,10 +8753,28 @@ fn main() { label: "impl_trait_in_assoc_type", description: r##"# `impl_trait_in_assoc_type` +Allows `impl Trait` to be used inside associated types (RFC 2515). + The tracking issue for this feature is: [#63063] [#63063]: https://github.com/rust-lang/rust/issues/63063 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "impl_trait_in_bindings", + description: r##"# `impl_trait_in_bindings` + +Allows `impl Trait` in bindings (`let`). + +The tracking issue for this feature is: [#63065] + +[#63065]: https://github.com/rust-lang/rust/issues/63065 + ------------------------ "##, default_severity: Severity::Allow, @@ -6859,11 +8785,42 @@ fn main() { label: "impl_trait_in_fn_trait_return", description: r##"# `impl_trait_in_fn_trait_return` +Allows `impl Trait` as output type in `Fn` traits in return position of functions. + The tracking issue for this feature is: [#99697] [#99697]: https://github.com/rust-lang/rust/issues/99697 ------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "import_trait_associated_functions", + description: r##"# import_trait_associated_functions + +The tracking issue for this feature is: [#134691] + +[#134691]: https://github.com/rust-lang/rust/issues/134691 + +------------------------ + +This feature allows importing associated functions and constants from traits and then using them like regular items. + +```rust +#![feature(import_trait_associated_functions)] + +use std::ops::Add::add; + +fn main() { + let numbers = vec![1, 2, 3, 4, 5, 6]; + let sum = numbers.into_iter().reduce(add); // instead of `.reduce(Add:add)` + + assert_eq!(sum, Some(21)); +} +``` "##, default_severity: Severity::Allow, warn_since: None, @@ -6873,40 +8830,13 @@ fn main() { label: "inherent_associated_types", description: r##"# `inherent_associated_types` +Allows associated types in inherent impls. + The tracking issue for this feature is: [#8995] [#8995]: https://github.com/rust-lang/rust/issues/8995 ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "inline_const_pat", - description: r##"# `inline_const_pat` - -The tracking issue for this feature is: [#76001] - ------- - -This feature allows you to use inline constant expressions in pattern position: - -```rust -#![feature(inline_const_pat)] - -const fn one() -> i32 { 1 } - -let some_int = 3; -match some_int { - const { 1 + 2 } => println!("Matched 1 + 2"), - const { one() } => println!("Matched const fn returning 1"), - _ => println!("Didn't match anything :("), -} -``` - -[#76001]: https://github.com/rust-lang/rust/issues/76001 "##, default_severity: Severity::Allow, warn_since: None, @@ -6916,8 +8846,58 @@ const fn one() -> i32 { 1 } label: "inplace_iteration", description: r##"# `inplace_iteration` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "int_format_into", + description: r##"# `int_format_into` + + + +The tracking issue for this feature is: [#138215] + +[#138215]: https://github.com/rust-lang/rust/issues/138215 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "int_from_ascii", + description: r##"# `int_from_ascii` + + + +The tracking issue for this feature is: [#134821] + +[#134821]: https://github.com/rust-lang/rust/issues/134821 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "int_lowest_highest_one", + description: r##"# `int_lowest_highest_one` + + + +The tracking issue for this feature is: [#145203] + +[#145203]: https://github.com/rust-lang/rust/issues/145203 + ------------------------ "##, default_severity: Severity::Allow, @@ -6928,6 +8908,8 @@ const fn one() -> i32 { 1 } label: "int_roundings", description: r##"# `int_roundings` + + The tracking issue for this feature is: [#88581] [#88581]: https://github.com/rust-lang/rust/issues/88581 @@ -6942,6 +8924,8 @@ const fn one() -> i32 { 1 } label: "integer_atomics", description: r##"# `integer_atomics` + + The tracking issue for this feature is: [#99069] [#99069]: https://github.com/rust-lang/rust/issues/99069 @@ -6953,24 +8937,14 @@ const fn one() -> i32 { 1 } deny_since: None, }, Lint { - label: "integer_sign_cast", - description: r##"# `integer_sign_cast` + label: "integer_extend_truncate", + description: r##"# `integer_extend_truncate` -The tracking issue for this feature is: [#125882] -[#125882]: https://github.com/rust-lang/rust/issues/125882 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "internal_impls_macro", - description: r##"# `internal_impls_macro` +The tracking issue for this feature is: [#154330] -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +[#154330]: https://github.com/rust-lang/rust/issues/154330 ------------------------ "##, @@ -7068,9 +9042,9 @@ mod foo { Various intrinsics have native MIR operations that they correspond to. Instead of requiring backends to implement both the intrinsic and the MIR operation, the `lower_intrinsics` pass will convert the calls to the MIR operation. Backends do not need to know about these intrinsics -at all. These intrinsics only make sense without a body, and can either be declared as a "rust-intrinsic" -or as a `#[rustc_intrinsic]`. The body is never used, as calls to the intrinsic do not exist -anymore after MIR analyses. +at all. These intrinsics only make sense without a body, and can be declared as a `#[rustc_intrinsic]`. +The body is never used as the lowering pass implements support for all backends, so we never have to +use the fallback logic. ## Intrinsics without fallback logic @@ -7078,33 +9052,14 @@ mod foo { ### `#[rustc_intrinsic]` declarations -These are written like intrinsics with fallback bodies, but the body is irrelevant. -Use `loop {}` for the body or call the intrinsic recursively and add -`#[rustc_intrinsic_must_be_overridden]` to the function to ensure that backends don't -invoke the body. - -### Legacy extern ABI based intrinsics - -These are imported as if they were FFI functions, with the special -`rust-intrinsic` ABI. For example, if one was in a freestanding -context, but wished to be able to `transmute` between types, and -perform efficient pointer arithmetic, one would import those functions -via a declaration like - +These are written without a body: ```rust #![feature(intrinsics)] #![allow(internal_features)] -# fn main() {} -extern "rust-intrinsic" { - fn transmute(x: T) -> U; - - fn arith_offset(dst: *const T, offset: isize) -> *const T; -} +#[rustc_intrinsic] +pub fn abort() -> !; ``` - -As with any other FFI functions, these are by default always `unsafe` to call. -You can add `#[rustc_safe_intrinsic]` to the intrinsic to make it safe to call. "##, default_severity: Severity::Allow, warn_since: None, @@ -7114,6 +9069,8 @@ mod foo { label: "io_const_error", description: r##"# `io_const_error` + + The tracking issue for this feature is: [#133448] [#133448]: https://github.com/rust-lang/rust/issues/133448 @@ -7128,6 +9085,8 @@ mod foo { label: "io_const_error_internals", description: r##"# `io_const_error_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -7140,6 +9099,8 @@ mod foo { label: "io_error_inprogress", description: r##"# `io_error_inprogress` + + The tracking issue for this feature is: [#130840] [#130840]: https://github.com/rust-lang/rust/issues/130840 @@ -7154,6 +9115,8 @@ mod foo { label: "io_error_more", description: r##"# `io_error_more` + + The tracking issue for this feature is: [#86442] [#86442]: https://github.com/rust-lang/rust/issues/86442 @@ -7168,6 +9131,8 @@ mod foo { label: "io_error_uncategorized", description: r##"# `io_error_uncategorized` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -7180,6 +9145,8 @@ mod foo { label: "io_slice_as_bytes", description: r##"# `io_slice_as_bytes` + + The tracking issue for this feature is: [#132818] [#132818]: https://github.com/rust-lang/rust/issues/132818 @@ -7194,6 +9161,8 @@ mod foo { label: "ip", description: r##"# `ip` + + The tracking issue for this feature is: [#27709] [#27709]: https://github.com/rust-lang/rust/issues/27709 @@ -7205,12 +9174,28 @@ mod foo { deny_since: None, }, Lint { - label: "ip_from", - description: r##"# `ip_from` + label: "ip_as_octets", + description: r##"# `ip_as_octets` -The tracking issue for this feature is: [#131360] -[#131360]: https://github.com/rust-lang/rust/issues/131360 + +The tracking issue for this feature is: [#137259] + +[#137259]: https://github.com/rust-lang/rust/issues/137259 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "ip_multicast_reserved", + description: r##"# `ip_multicast_reserved` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -7222,6 +9207,8 @@ mod foo { label: "is_ascii_octdigit", description: r##"# `is_ascii_octdigit` + + The tracking issue for this feature is: [#101288] [#101288]: https://github.com/rust-lang/rust/issues/101288 @@ -7236,6 +9223,8 @@ mod foo { label: "is_loongarch_feature_detected", description: r##"# `is_loongarch_feature_detected` + + The tracking issue for this feature is: [#117425] [#117425]: https://github.com/rust-lang/rust/issues/117425 @@ -7250,10 +9239,28 @@ mod foo { label: "is_riscv_feature_detected", description: r##"# `is_riscv_feature_detected` + + The tracking issue for this feature is: [#111192] [#111192]: https://github.com/rust-lang/rust/issues/111192 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "isolate_most_least_significant_one", + description: r##"# `isolate_most_least_significant_one` + + + +The tracking issue for this feature is: [#136909] + +[#136909]: https://github.com/rust-lang/rust/issues/136909 + ------------------------ "##, default_severity: Severity::Allow, @@ -7264,6 +9271,8 @@ mod foo { label: "iter_advance_by", description: r##"# `iter_advance_by` + + The tracking issue for this feature is: [#77404] [#77404]: https://github.com/rust-lang/rust/issues/77404 @@ -7278,24 +9287,12 @@ mod foo { label: "iter_array_chunks", description: r##"# `iter_array_chunks` + + The tracking issue for this feature is: [#100450] [#100450]: https://github.com/rust-lang/rust/issues/100450 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "iter_chain", - description: r##"# `iter_chain` - -The tracking issue for this feature is: [#125964] - -[#125964]: https://github.com/rust-lang/rust/issues/125964 - ------------------------ "##, default_severity: Severity::Allow, @@ -7306,6 +9303,8 @@ mod foo { label: "iter_collect_into", description: r##"# `iter_collect_into` + + The tracking issue for this feature is: [#94780] [#94780]: https://github.com/rust-lang/rust/issues/94780 @@ -7320,6 +9319,8 @@ mod foo { label: "iter_from_coroutine", description: r##"# `iter_from_coroutine` + + The tracking issue for this feature is: [#43122] [#43122]: https://github.com/rust-lang/rust/issues/43122 @@ -7334,6 +9335,8 @@ mod foo { label: "iter_intersperse", description: r##"# `iter_intersperse` + + The tracking issue for this feature is: [#79524] [#79524]: https://github.com/rust-lang/rust/issues/79524 @@ -7348,10 +9351,28 @@ mod foo { label: "iter_is_partitioned", description: r##"# `iter_is_partitioned` + + The tracking issue for this feature is: [#62544] [#62544]: https://github.com/rust-lang/rust/issues/62544 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "iter_macro", + description: r##"# `iter_macro` + + + +The tracking issue for this feature is: [#142269] + +[#142269]: https://github.com/rust-lang/rust/issues/142269 + ------------------------ "##, default_severity: Severity::Allow, @@ -7362,6 +9383,8 @@ mod foo { label: "iter_map_windows", description: r##"# `iter_map_windows` + + The tracking issue for this feature is: [#87155] [#87155]: https://github.com/rust-lang/rust/issues/87155 @@ -7376,6 +9399,8 @@ mod foo { label: "iter_next_chunk", description: r##"# `iter_next_chunk` + + The tracking issue for this feature is: [#98326] [#98326]: https://github.com/rust-lang/rust/issues/98326 @@ -7390,6 +9415,8 @@ mod foo { label: "iter_order_by", description: r##"# `iter_order_by` + + The tracking issue for this feature is: [#64295] [#64295]: https://github.com/rust-lang/rust/issues/64295 @@ -7404,6 +9431,8 @@ mod foo { label: "iter_partition_in_place", description: r##"# `iter_partition_in_place` + + The tracking issue for this feature is: [#62543] [#62543]: https://github.com/rust-lang/rust/issues/62543 @@ -7418,6 +9447,8 @@ mod foo { label: "iterator_try_collect", description: r##"# `iterator_try_collect` + + The tracking issue for this feature is: [#94047] [#94047]: https://github.com/rust-lang/rust/issues/94047 @@ -7432,6 +9463,8 @@ mod foo { label: "iterator_try_reduce", description: r##"# `iterator_try_reduce` + + The tracking issue for this feature is: [#87053] [#87053]: https://github.com/rust-lang/rust/issues/87053 @@ -7446,6 +9479,8 @@ mod foo { label: "junction_point", description: r##"# `junction_point` + + The tracking issue for this feature is: [#121709] [#121709]: https://github.com/rust-lang/rust/issues/121709 @@ -7460,9 +9495,11 @@ mod foo { label: "lahfsahf_target_feature", description: r##"# `lahfsahf_target_feature` -The tracking issue for this feature is: [#44839] +lahfsahf target feature on x86. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150251] + +[#150251]: https://github.com/rust-lang/rust/issues/150251 ------------------------ "##, @@ -7520,14 +9557,15 @@ mod foo { allocations via `malloc` and `free`: ```rust,ignore (libc-is-finicky) -#![feature(lang_items, start, core_intrinsics, rustc_private, panic_unwind, rustc_attrs)] +#![feature(lang_items, core_intrinsics, rustc_private, panic_unwind, rustc_attrs)] #![allow(internal_features)] #![no_std] +#![no_main] extern crate libc; extern crate unwind; -use core::ffi::c_void; +use core::ffi::{c_int, c_void}; use core::intrinsics; use core::panic::PanicInfo; use core::ptr::NonNull; @@ -7565,8 +9603,8 @@ unsafe fn allocate(size: usize, _align: usize) -> *mut u8 { p } -#[start] -fn main(_argc: isize, _argv: *const *const u8) -> isize { +#[no_mangle] +extern "C" fn main(_argc: c_int, _argv: *const *const u8) -> c_int { let _x = Box::new(1); 0 @@ -7596,6 +9634,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "large_assignments", description: r##"# `large_assignments` +Allows setting the threshold for the `large_assignments` lint. + The tracking issue for this feature is: [#83518] [#83518]: https://github.com/rust-lang/rust/issues/83518 @@ -7610,6 +9650,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "layout_for_ptr", description: r##"# `layout_for_ptr` + + The tracking issue for this feature is: [#69835] [#69835]: https://github.com/rust-lang/rust/issues/69835 @@ -7624,24 +9666,12 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "lazy_cell_into_inner", description: r##"# `lazy_cell_into_inner` + + The tracking issue for this feature is: [#125623] [#125623]: https://github.com/rust-lang/rust/issues/125623 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "lazy_get", - description: r##"# `lazy_get` - -The tracking issue for this feature is: [#129333] - -[#129333]: https://github.com/rust-lang/rust/issues/129333 - ------------------------ "##, default_severity: Severity::Allow, @@ -7652,6 +9682,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "lazy_type_alias", description: r##"# `lazy_type_alias` +Allow to have type alias types for inter-crate use. + The tracking issue for this feature is: [#112792] [#112792]: https://github.com/rust-lang/rust/issues/112792 @@ -7666,22 +9698,10 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "legacy_receiver_trait", description: r##"# `legacy_receiver_trait` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "let_chains", - description: r##"# `let_chains` - -The tracking issue for this feature is: [#53667] - -[#53667]: https://github.com/rust-lang/rust/issues/53667 - ------------------------ "##, default_severity: Severity::Allow, @@ -7692,6 +9712,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "liballoc_internals", description: r##"# `liballoc_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -7713,10 +9735,14 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } deny_since: None, }, Lint { - label: "lifetime_capture_rules_2024", - description: r##"# `lifetime_capture_rules_2024` + label: "likely_unlikely", + description: r##"# `likely_unlikely` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + + +The tracking issue for this feature is: [#151619] + +[#151619]: https://github.com/rust-lang/rust/issues/151619 ------------------------ "##, @@ -7768,6 +9794,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "link_llvm_intrinsics", description: r##"# `link_llvm_intrinsics` +Allows using `#[link_name="llvm.*"]`. + The tracking issue for this feature is: [#29602] [#29602]: https://github.com/rust-lang/rust/issues/29602 @@ -7782,6 +9810,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "linkage", description: r##"# `linkage` +Allows using the `#[linkage = ".."]` attribute. + The tracking issue for this feature is: [#29603] [#29603]: https://github.com/rust-lang/rust/issues/29603 @@ -7796,6 +9826,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "linked_list_cursors", description: r##"# `linked_list_cursors` + + The tracking issue for this feature is: [#58533] [#58533]: https://github.com/rust-lang/rust/issues/58533 @@ -7810,6 +9842,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "linked_list_remove", description: r##"# `linked_list_remove` + + The tracking issue for this feature is: [#69210] [#69210]: https://github.com/rust-lang/rust/issues/69210 @@ -7824,6 +9858,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "linked_list_retain", description: r##"# `linked_list_retain` + + The tracking issue for this feature is: [#114135] [#114135]: https://github.com/rust-lang/rust/issues/114135 @@ -7838,10 +9874,28 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "linux_pidfd", description: r##"# `linux_pidfd` + + The tracking issue for this feature is: [#82971] [#82971]: https://github.com/rust-lang/rust/issues/82971 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "local_key_cell_update", + description: r##"# `local_key_cell_update` + + + +The tracking issue for this feature is: [#143989] + +[#143989]: https://github.com/rust-lang/rust/issues/143989 + ------------------------ "##, default_severity: Severity::Allow, @@ -7852,10 +9906,28 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "local_waker", description: r##"# `local_waker` + + The tracking issue for this feature is: [#118959] [#118959]: https://github.com/rust-lang/rust/issues/118959 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "lock_value_accessors", + description: r##"# `lock_value_accessors` + + + +The tracking issue for this feature is: [#133407] + +[#133407]: https://github.com/rust-lang/rust/issues/133407 + ------------------------ "##, default_severity: Severity::Allow, @@ -7866,6 +9938,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "log_syntax", description: r##"# `log_syntax` + + The tracking issue for this feature is: [#29598] [#29598]: https://github.com/rust-lang/rust/issues/29598 @@ -7880,9 +9954,134 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "loongarch_target_feature", description: r##"# `loongarch_target_feature` -The tracking issue for this feature is: [#44839] +Target features on loongarch. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150252] + +[#150252]: https://github.com/rust-lang/rust/issues/150252 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "loop_match", + description: r##"# `loop_match` + +The tracking issue for this feature is: [#132306] + +[#132306]: https://github.com/rust-lang/rust/issues/132306 + +------ + +The `#[loop_match]` and `#[const_continue]` attributes can be used to improve the code +generation of logic that fits this shape: + +```ignore (pseudo-rust) +loop { + state = 'blk: { + match state { + State::A => { + break 'blk State::B + } + State::B => { /* ... */ } + /* ... */ + } + } +} +``` + +Here the loop itself can be annotated with `#[loop_match]`, and any `break 'blk` with +`#[const_continue]` if the value is know at compile time: + +```ignore (pseudo-rust) +#[loop_match] +loop { + state = 'blk: { + match state { + State::A => { + #[const_continue] + break 'blk State::B + } + State::B => { /* ... */ } + /* ... */ + } + } +} +``` + +The observable behavior of this loop is exactly the same as without the extra attributes. +The difference is in the generated output: normally, when the state is `A`, control flow +moves from the `A` branch, back to the top of the loop, then to the `B` branch. With the +attributes, The `A` branch will immediately jump to the `B` branch. + +Removing the indirection can be beneficial for stack usage and branch prediction, and +enables other optimizations by clearly splitting out the control flow paths that your +program will actually use. +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "m68k_target_feature", + description: r##"# `m68k_target_feature` + +Target features on m68k. + +The tracking issue for this feature is: [#134328] + +[#134328]: https://github.com/rust-lang/rust/issues/134328 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "macro_attr", + description: r##"# `macro_attr` + +Allow `macro_rules!` attribute rules + +The tracking issue for this feature is: [#143547] + +[#143547]: https://github.com/rust-lang/rust/issues/143547 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "macro_derive", + description: r##"# `macro_derive` + +Allow `macro_rules!` derive rules + +The tracking issue for this feature is: [#143549] + +[#143549]: https://github.com/rust-lang/rust/issues/143549 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "macro_guard_matcher", + description: r##"# `macro_guard_matcher` + +Allow `$x:guard` matcher in macros + +The tracking issue for this feature is: [#153104] + +[#153104]: https://github.com/rust-lang/rust/issues/153104 ------------------------ "##, @@ -7896,9 +10095,12 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } The tracking issue for this feature is: [#83527] -[#83527]: https://github.com/rust-lang/rust/issues/83527 - ------------------------ + +> This feature is not to be confused with [`macro_metavar_expr_concat`]. + +[`macro_metavar_expr_concat`]: ./macro-metavar-expr-concat.md +[#83527]: https://github.com/rust-lang/rust/issues/83527 "##, default_severity: Severity::Allow, warn_since: None, @@ -7910,23 +10112,135 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } The tracking issue for this feature is: [#124225] +------------------------ + +In stable Rust, there is no way to create new identifiers by joining identifiers to literals or other identifiers without using procedural macros such as [`paste`]. + `#![feature(macro_metavar_expr_concat)]` introduces a way to do this, using the concat metavariable expression. + +> This feature uses the syntax from [`macro_metavar_expr`] but is otherwise +> independent. It replaces the since-removed unstable feature +> [`concat_idents`]. + +> This is an experimental feature; it and its syntax will require a RFC before stabilization. + + +### Overview + +`#![feature(macro_metavar_expr_concat)]` provides the `concat` metavariable expression for creating new identifiers: + +```rust +#![feature(macro_metavar_expr_concat)] + +macro_rules! create_some_structs { + ($name:ident) => { + pub struct ${ concat(First, $name) }; + pub struct ${ concat(Second, $name) }; + pub struct ${ concat(Third, $name) }; + } +} + +create_some_structs!(Thing); +``` + +This macro invocation expands to: + +```rust +pub struct FirstThing; +pub struct SecondThing; +pub struct ThirdThing; +``` + +### Syntax + +This feature builds upon the metavariable expression syntax `${ .. }` as specified in [RFC 3086] ([`macro_metavar_expr`]). + `concat` is available like `${ concat(items) }`, where `items` is a comma separated sequence of idents and/or literals. + +### Examples + +#### Create a function or method with a concatenated name + +```rust +#![feature(macro_metavar_expr_concat)] + +macro_rules! make_getter { + ($name:ident, $field: ident, $ret:ty) => { + impl $name { + pub fn ${ concat(get_, $field) }(&self) -> &$ret { + &self.$field + } + } + } +} + +pub struct Thing { + description: String, +} + +make_getter!(Thing, description, String); +``` + +This expands to: + +```rust +pub struct Thing { + description: String, +} + +impl Thing { + pub fn get_description(&self) -> &String { + &self.description + } +} +``` + +#### Create names for macro generated tests + +```rust +#![feature(macro_metavar_expr_concat)] + +macro_rules! test_math { + ($integer:ident) => { + #[test] + fn ${ concat(test_, $integer, _, addition) } () { + let a: $integer = 73; + let b: $integer = 42; + assert_eq!(a + b, 115) + } + + #[test] + fn ${ concat(test_, $integer, _, subtraction) } () { + let a: $integer = 73; + let b: $integer = 42; + assert_eq!(a - b, 31) + } + } +} + +test_math!(i32); +test_math!(u64); +test_math!(u128); +``` + +Running this returns the following output: + +```text +running 6 tests +test test_i32_subtraction ... ok +test test_i32_addition ... ok +test test_u128_addition ... ok +test test_u128_subtraction ... ok +test test_u64_addition ... ok +test test_u64_subtraction ... ok + +test result: ok. 6 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s +``` + +[`paste`]: https://crates.io/crates/paste +[RFC 3086]: https://rust-lang.github.io/rfcs/3086-macro-metavar-expr.html +[`macro_metavar_expr`]: ../language-features/macro-metavar-expr.md +[`concat_idents`]: https://github.com/rust-lang/rust/issues/29599 [#124225]: https://github.com/rust-lang/rust/issues/124225 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "map_many_mut", - description: r##"# `map_many_mut` - -The tracking issue for this feature is: [#97601] - -[#97601]: https://github.com/rust-lang/rust/issues/97601 - ------------------------- +[declarative macros]: https://doc.rust-lang.org/stable/reference/macros-by-example.html "##, default_severity: Severity::Allow, warn_since: None, @@ -7936,6 +10250,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "map_try_insert", description: r##"# `map_try_insert` + + The tracking issue for this feature is: [#82766] [#82766]: https://github.com/rust-lang/rust/issues/82766 @@ -7950,6 +10266,8 @@ fn panic_handler(_info: &PanicInfo) -> ! { intrinsics::abort() } label: "mapped_lock_guards", description: r##"# `mapped_lock_guards` + + The tracking issue for this feature is: [#117108] [#117108]: https://github.com/rust-lang/rust/issues/117108 @@ -7997,6 +10315,22 @@ fn cheap_clone(t: T) -> T { This is expected to replace the unstable `overlapping_marker_traits` feature, which applied to all empty traits (without needing an opt-in). +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "maybe_dangling", + description: r##"# `maybe_dangling` + + + +The tracking issue for this feature is: [#118166] + +[#118166]: https://github.com/rust-lang/rust/issues/118166 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -8006,6 +10340,8 @@ fn cheap_clone(t: T) -> T { label: "maybe_uninit_array_assume_init", description: r##"# `maybe_uninit_array_assume_init` + + The tracking issue for this feature is: [#96097] [#96097]: https://github.com/rust-lang/rust/issues/96097 @@ -8020,6 +10356,8 @@ fn cheap_clone(t: T) -> T { label: "maybe_uninit_as_bytes", description: r##"# `maybe_uninit_as_bytes` + + The tracking issue for this feature is: [#93092] [#93092]: https://github.com/rust-lang/rust/issues/93092 @@ -8034,38 +10372,12 @@ fn cheap_clone(t: T) -> T { label: "maybe_uninit_fill", description: r##"# `maybe_uninit_fill` + + The tracking issue for this feature is: [#117428] [#117428]: https://github.com/rust-lang/rust/issues/117428 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "maybe_uninit_slice", - description: r##"# `maybe_uninit_slice` - -The tracking issue for this feature is: [#63569] - -[#63569]: https://github.com/rust-lang/rust/issues/63569 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "maybe_uninit_uninit_array", - description: r##"# `maybe_uninit_uninit_array` - -The tracking issue for this feature is: [#96097] - -[#96097]: https://github.com/rust-lang/rust/issues/96097 - ------------------------ "##, default_severity: Severity::Allow, @@ -8076,6 +10388,8 @@ fn cheap_clone(t: T) -> T { label: "maybe_uninit_uninit_array_transpose", description: r##"# `maybe_uninit_uninit_array_transpose` + + The tracking issue for this feature is: [#96097] [#96097]: https://github.com/rust-lang/rust/issues/96097 @@ -8087,12 +10401,14 @@ fn cheap_clone(t: T) -> T { deny_since: None, }, Lint { - label: "maybe_uninit_write_slice", - description: r##"# `maybe_uninit_write_slice` + label: "mem_conjure_zst", + description: r##"# `mem_conjure_zst` -The tracking issue for this feature is: [#79995] -[#79995]: https://github.com/rust-lang/rust/issues/79995 + +The tracking issue for this feature is: [#95383] + +[#95383]: https://github.com/rust-lang/rust/issues/95383 ------------------------ "##, @@ -8104,10 +10420,44 @@ fn cheap_clone(t: T) -> T { label: "mem_copy_fn", description: r##"# `mem_copy_fn` + + The tracking issue for this feature is: [#98262] [#98262]: https://github.com/rust-lang/rust/issues/98262 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "mgca_type_const_syntax", + description: r##"# `mgca_type_const_syntax` + +Enable mgca `type const` syntax before expansion. + +The tracking issue for this feature is: [#132980] + +[#132980]: https://github.com/rust-lang/rust/issues/132980 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "min_adt_const_params", + description: r##"# `min_adt_const_params` + +Allows additional const parameter types, such as [u8; 10] or user defined types. User defined types must not have fields more private than the type itself. + +The tracking issue for this feature is: [#154042] + +[#154042]: https://github.com/rust-lang/rust/issues/154042 + ------------------------ "##, default_severity: Severity::Allow, @@ -8118,6 +10468,8 @@ fn cheap_clone(t: T) -> T { label: "min_generic_const_args", description: r##"# `min_generic_const_args` +Enables the generic const args MVP (only bare paths, not arbitrary computation). + The tracking issue for this feature is: [#132980] [#132980]: https://github.com/rust-lang/rust/issues/132980 @@ -8132,6 +10484,8 @@ fn cheap_clone(t: T) -> T { label: "min_specialization", description: r##"# `min_specialization` +A minimal, sound subset of specialization intended to be used by the standard library until the soundness issues with specialization are fixed. + The tracking issue for this feature is: [#31844] [#31844]: https://github.com/rust-lang/rust/issues/31844 @@ -8146,23 +10500,11 @@ fn cheap_clone(t: T) -> T { label: "mips_target_feature", description: r##"# `mips_target_feature` -The tracking issue for this feature is: [#44839] +Target features on mips. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150253] ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "mixed_integer_ops_unsigned_sub", - description: r##"# `mixed_integer_ops_unsigned_sub` - -The tracking issue for this feature is: [#126043] - -[#126043]: https://github.com/rust-lang/rust/issues/126043 +[#150253]: https://github.com/rust-lang/rust/issues/150253 ------------------------ "##, @@ -8174,9 +10516,11 @@ fn cheap_clone(t: T) -> T { label: "more_float_constants", description: r##"# `more_float_constants` -The tracking issue for this feature is: [#103883] -[#103883]: https://github.com/rust-lang/rust/issues/103883 + +The tracking issue for this feature is: [#146939] + +[#146939]: https://github.com/rust-lang/rust/issues/146939 ------------------------ "##, @@ -8188,6 +10532,8 @@ fn cheap_clone(t: T) -> T { label: "more_maybe_bounds", description: r##"# `more_maybe_bounds` +Allows using `?Trait` trait bounds in more contexts. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -8231,6 +10577,38 @@ impl A for Foo { type Assoc = StructStruct; } ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "motor_ext", + description: r##"# `motor_ext` + + + +The tracking issue for this feature is: [#147456] + +[#147456]: https://github.com/rust-lang/rust/issues/147456 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "movrs_target_feature", + description: r##"# `movrs_target_feature` + +The `movrs` target feature on x86. + +The tracking issue for this feature is: [#137976] + +[#137976]: https://github.com/rust-lang/rust/issues/137976 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -8240,10 +10618,28 @@ impl A for Foo { label: "mpmc_channel", description: r##"# `mpmc_channel` + + The tracking issue for this feature is: [#126840] [#126840]: https://github.com/rust-lang/rust/issues/126840 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "mpsc_is_disconnected", + description: r##"# `mpsc_is_disconnected` + + + +The tracking issue for this feature is: [#153668] + +[#153668]: https://github.com/rust-lang/rust/issues/153668 + ------------------------ "##, default_severity: Severity::Allow, @@ -8254,7 +10650,11 @@ impl A for Foo { label: "multiple_supertrait_upcastable", description: r##"# `multiple_supertrait_upcastable` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +Allows the `multiple_supertrait_upcastable` lint. + +The tracking issue for this feature is: [#150833] + +[#150833]: https://github.com/rust-lang/rust/issues/150833 ------------------------ "##, @@ -8266,6 +10666,8 @@ impl A for Foo { label: "must_not_suspend", description: r##"# `must_not_suspend` +Allows the `#[must_not_suspend]` attribute. + The tracking issue for this feature is: [#83310] [#83310]: https://github.com/rust-lang/rust/issues/83310 @@ -8280,6 +10682,8 @@ impl A for Foo { label: "mut_ref", description: r##"# `mut_ref` +Allows `mut ref` and `mut ref mut` identifier patterns. + The tracking issue for this feature is: [#123076] [#123076]: https://github.com/rust-lang/rust/issues/123076 @@ -8291,12 +10695,46 @@ impl A for Foo { deny_since: None, }, Lint { - label: "naked_functions", - description: r##"# `naked_functions` + label: "mutex_data_ptr", + description: r##"# `mutex_data_ptr` -The tracking issue for this feature is: [#90957] -[#90957]: https://github.com/rust-lang/rust/issues/90957 + +The tracking issue for this feature is: [#140368] + +[#140368]: https://github.com/rust-lang/rust/issues/140368 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "naked_functions_rustic_abi", + description: r##"# `naked_functions_rustic_abi` + +Allows using `#[naked]` on `extern "Rust"` functions. + +The tracking issue for this feature is: [#138997] + +[#138997]: https://github.com/rust-lang/rust/issues/138997 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "naked_functions_target_feature", + description: r##"# `naked_functions_target_feature` + +Allows using `#[target_feature(enable = "...")]` on `#[naked]` on functions. + +The tracking issue for this feature is: [#138568] + +[#138568]: https://github.com/rust-lang/rust/issues/138568 ------------------------ "##, @@ -8333,6 +10771,8 @@ impl A for Foo { label: "needs_panic_runtime", description: r##"# `needs_panic_runtime` +Allows declaring with `#![needs_panic_runtime]` that a panic runtime is needed. + The tracking issue for this feature is: [#32837] [#32837]: https://github.com/rust-lang/rust/issues/32837 @@ -8347,6 +10787,8 @@ impl A for Foo { label: "negative_bounds", description: r##"# `negative_bounds` +Allow negative trait bounds. This is an internal-only feature for testing the trait solver! + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -8423,6 +10865,8 @@ impl at all, but that is not an option for auto traits. A workaround label: "never_patterns", description: r##"# `never_patterns` +Allows the `!` pattern. + The tracking issue for this feature is: [#118155] [#118155]: https://github.com/rust-lang/rust/issues/118155 @@ -8437,6 +10881,8 @@ impl at all, but that is not an option for auto traits. A workaround label: "never_type", description: r##"# `never_type` +Allows the `!` type. Does not imply 'exhaustive_patterns' (below) any more. + The tracking issue for this feature is: [#35121] [#35121]: https://github.com/rust-lang/rust/issues/35121 @@ -8448,22 +10894,26 @@ impl at all, but that is not an option for auto traits. A workaround deny_since: None, }, Lint { - label: "never_type_fallback", - description: r##"# `never_type_fallback` + label: "new_range", + description: r##"# `new_range` -The tracking issue for this feature is: [#65992] +The tracking issue for this feature is: [#123741] -[#65992]: https://github.com/rust-lang/rust/issues/65992 +[#123741]: https://github.com/rust-lang/rust/issues/123741 ------------------------- +--- + +Switch the syntaxes `a..`, `a..b`, and `a..=b` to resolve the new range types. "##, default_severity: Severity::Allow, warn_since: None, deny_since: None, }, Lint { - label: "new_range_api", - description: r##"# `new_range_api` + label: "new_range_api_legacy", + description: r##"# `new_range_api_legacy` + + The tracking issue for this feature is: [#125687] @@ -8476,12 +10926,30 @@ impl at all, but that is not an option for auto traits. A workaround deny_since: None, }, Lint { - label: "new_zeroed_alloc", - description: r##"# `new_zeroed_alloc` + label: "new_range_remainder", + description: r##"# `new_range_remainder` -The tracking issue for this feature is: [#129396] -[#129396]: https://github.com/rust-lang/rust/issues/129396 + +The tracking issue for this feature is: [#154458] + +[#154458]: https://github.com/rust-lang/rust/issues/154458 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "next_index", + description: r##"# `next_index` + + + +The tracking issue for this feature is: [#130711] + +[#130711]: https://github.com/rust-lang/rust/issues/130711 ------------------------ "##, @@ -8493,47 +10961,13 @@ impl at all, but that is not an option for auto traits. A workaround label: "no_core", description: r##"# `no_core` +Allows `#![no_core]`. + The tracking issue for this feature is: [#29639] [#29639]: https://github.com/rust-lang/rust/issues/29639 ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "no_sanitize", - description: r##"# `no_sanitize` - -The tracking issue for this feature is: [#39699] - -[#39699]: https://github.com/rust-lang/rust/issues/39699 - ------------------------- - -The `no_sanitize` attribute can be used to selectively disable sanitizer -instrumentation in an annotated function. This might be useful to: avoid -instrumentation overhead in a performance critical function, or avoid -instrumenting code that contains constructs unsupported by given sanitizer. - -The precise effect of this annotation depends on particular sanitizer in use. -For example, with `no_sanitize(thread)`, the thread sanitizer will no longer -instrument non-atomic store / load operations, but it will instrument atomic -operations to avoid reporting false positives and provide meaning full stack -traces. - -## Examples - -``` rust -#![feature(no_sanitize)] - -#[no_sanitize(address)] -fn foo() { - // ... -} -``` "##, default_severity: Severity::Allow, warn_since: None, @@ -8543,6 +10977,8 @@ fn foo() { label: "non_exhaustive_omitted_patterns_lint", description: r##"# `non_exhaustive_omitted_patterns_lint` +Allows using the `non_exhaustive_omitted_patterns` lint. + The tracking issue for this feature is: [#89554] [#89554]: https://github.com/rust-lang/rust/issues/89554 @@ -8557,6 +10993,8 @@ fn foo() { label: "non_lifetime_binders", description: r##"# `non_lifetime_binders` +Allows `for` binders in where-clauses + The tracking issue for this feature is: [#108185] [#108185]: https://github.com/rust-lang/rust/issues/108185 @@ -8568,12 +11006,14 @@ fn foo() { deny_since: None, }, Lint { - label: "non_null_from_ref", - description: r##"# `non_null_from_ref` + label: "nonpoison_condvar", + description: r##"# `nonpoison_condvar` -The tracking issue for this feature is: [#130823] -[#130823]: https://github.com/rust-lang/rust/issues/130823 + +The tracking issue for this feature is: [#134645] + +[#134645]: https://github.com/rust-lang/rust/issues/134645 ------------------------ "##, @@ -8582,12 +11022,30 @@ fn foo() { deny_since: None, }, Lint { - label: "non_zero_count_ones", - description: r##"# `non_zero_count_ones` + label: "nonpoison_mutex", + description: r##"# `nonpoison_mutex` -The tracking issue for this feature is: [#120287] -[#120287]: https://github.com/rust-lang/rust/issues/120287 + +The tracking issue for this feature is: [#134645] + +[#134645]: https://github.com/rust-lang/rust/issues/134645 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "nonpoison_rwlock", + description: r##"# `nonpoison_rwlock` + + + +The tracking issue for this feature is: [#134645] + +[#134645]: https://github.com/rust-lang/rust/issues/134645 ------------------------ "##, @@ -8599,6 +11057,8 @@ fn foo() { label: "nonzero_bitwise", description: r##"# `nonzero_bitwise` + + The tracking issue for this feature is: [#128281] [#128281]: https://github.com/rust-lang/rust/issues/128281 @@ -8613,10 +11073,28 @@ fn foo() { label: "nonzero_from_mut", description: r##"# `nonzero_from_mut` + + The tracking issue for this feature is: [#106290] [#106290]: https://github.com/rust-lang/rust/issues/106290 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "nonzero_from_str_radix", + description: r##"# `nonzero_from_str_radix` + + + +The tracking issue for this feature is: [#152193] + +[#152193]: https://github.com/rust-lang/rust/issues/152193 + ------------------------ "##, default_severity: Severity::Allow, @@ -8627,6 +11105,8 @@ fn foo() { label: "nonzero_internals", description: r##"# `nonzero_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -8639,6 +11119,8 @@ fn foo() { label: "nonzero_ops", description: r##"# `nonzero_ops` + + The tracking issue for this feature is: [#84186] [#84186]: https://github.com/rust-lang/rust/issues/84186 @@ -8650,12 +11132,28 @@ fn foo() { deny_since: None, }, Lint { - label: "num_midpoint_signed", - description: r##"# `num_midpoint_signed` + label: "normalize_lexically", + description: r##"# `normalize_lexically` -The tracking issue for this feature is: [#110840] -[#110840]: https://github.com/rust-lang/rust/issues/110840 + +The tracking issue for this feature is: [#134694] + +[#134694]: https://github.com/rust-lang/rust/issues/134694 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "num_internals", + description: r##"# `num_internals` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -8667,6 +11165,52 @@ fn foo() { label: "numfmt", description: r##"# `numfmt` + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "nvptx_target_feature", + description: r##"# `nvptx_target_feature` + +Target feaures on nvptx. + +The tracking issue for this feature is: [#150254] + +[#150254]: https://github.com/rust-lang/rust/issues/150254 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "objc_class_variant", + description: r##"# `objc_class_variant` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "objc_selector_variant", + description: r##"# `objc_selector_variant` + + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -8684,6 +11228,28 @@ fn foo() { [#120141]: https://github.com/rust-lang/rust/issues/120141 ------------------------ + +When the `offset_of_enum` feature is enabled, the [`offset_of!`] macro may be used to obtain the +offsets of fields of `enum`s; to express this, `enum` variants may be traversed as if they were +fields. Variants themselves do not have an offset, so they cannot appear as the last path component. + +```rust +#![feature(offset_of_enum)] +use std::mem; + +#[repr(u8)] +enum Enum { + A(u8, u16), + B { one: u8, two: u16 }, +} + +assert_eq!(mem::offset_of!(Enum, A.0), 1); +assert_eq!(mem::offset_of!(Enum, B.two), 2); + +assert_eq!(mem::offset_of!(Option<&u8>, Some.0), 0); +``` + +[`offset_of!`]: ../../std/mem/macro.offset_of.html "##, default_severity: Severity::Allow, warn_since: None, @@ -8698,18 +11264,29 @@ fn foo() { [#126151]: https://github.com/rust-lang/rust/issues/126151 ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "omit_gdb_pretty_printer_section", - description: r##"# `omit_gdb_pretty_printer_section` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +When the `offset_of_slice` feature is enabled, the [`offset_of!`] macro may be used to determine +the offset of fields whose type is `[T]`, that is, a slice of dynamic size. ------------------------- +In general, fields whose type is dynamically sized do not have statically known offsets because +they do not have statically known alignments. However, `[T]` has the same alignment as `T`, so +it specifically may be allowed. + +```rust +#![feature(offset_of_slice)] + +#[repr(C)] +pub struct Struct { + head: u32, + tail: [u8], +} + +fn main() { + assert_eq!(std::mem::offset_of!(Struct, tail), 4); +} +``` + +[`offset_of!`]: ../../std/mem/macro.offset_of.html "##, default_severity: Severity::Allow, warn_since: None, @@ -8719,6 +11296,8 @@ fn foo() { label: "once_cell_get_mut", description: r##"# `once_cell_get_mut` + + The tracking issue for this feature is: [#121641] [#121641]: https://github.com/rust-lang/rust/issues/121641 @@ -8733,6 +11312,8 @@ fn foo() { label: "once_cell_try", description: r##"# `once_cell_try` + + The tracking issue for this feature is: [#109737] [#109737]: https://github.com/rust-lang/rust/issues/109737 @@ -8747,24 +11328,12 @@ fn foo() { label: "once_cell_try_insert", description: r##"# `once_cell_try_insert` + + The tracking issue for this feature is: [#116693] [#116693]: https://github.com/rust-lang/rust/issues/116693 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "once_wait", - description: r##"# `once_wait` - -The tracking issue for this feature is: [#127527] - -[#127527]: https://github.com/rust-lang/rust/issues/127527 - ------------------------ "##, default_severity: Severity::Allow, @@ -8775,10 +11344,28 @@ fn foo() { label: "one_sided_range", description: r##"# `one_sided_range` + + The tracking issue for this feature is: [#69780] [#69780]: https://github.com/rust-lang/rust/issues/69780 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "oneshot_channel", + description: r##"# `oneshot_channel` + + + +The tracking issue for this feature is: [#143674] + +[#143674]: https://github.com/rust-lang/rust/issues/143674 + ------------------------ "##, default_severity: Severity::Allow, @@ -8789,6 +11376,8 @@ fn foo() { label: "optimize_attribute", description: r##"# `optimize_attribute` +Allows using `#[optimize(X)]`. + The tracking issue for this feature is: [#54882] [#54882]: https://github.com/rust-lang/rust/issues/54882 @@ -8803,10 +11392,76 @@ fn foo() { label: "option_array_transpose", description: r##"# `option_array_transpose` + + The tracking issue for this feature is: [#130828] [#130828]: https://github.com/rust-lang/rust/issues/130828 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "option_get_or_try_insert_with", + description: r##"# `option_get_or_try_insert_with` + + + +The tracking issue for this feature is: [#143648] + +[#143648]: https://github.com/rust-lang/rust/issues/143648 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "option_into_flat_iter", + description: r##"# `option_into_flat_iter` + + + +The tracking issue for this feature is: [#148441] + +[#148441]: https://github.com/rust-lang/rust/issues/148441 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "option_reduce", + description: r##"# `option_reduce` + + + +The tracking issue for this feature is: [#144273] + +[#144273]: https://github.com/rust-lang/rust/issues/144273 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "option_reference_flattening", + description: r##"# `option_reference_flattening` + + + +The tracking issue for this feature is: [#149221] + +[#149221]: https://github.com/rust-lang/rust/issues/149221 + ------------------------ "##, default_severity: Severity::Allow, @@ -8817,24 +11472,12 @@ fn foo() { label: "option_zip", description: r##"# `option_zip` + + The tracking issue for this feature is: [#70086] [#70086]: https://github.com/rust-lang/rust/issues/70086 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "os_str_display", - description: r##"# `os_str_display` - -The tracking issue for this feature is: [#120048] - -[#120048]: https://github.com/rust-lang/rust/issues/120048 - ------------------------ "##, default_severity: Severity::Allow, @@ -8845,24 +11488,12 @@ fn foo() { label: "os_str_slice", description: r##"# `os_str_slice` + + The tracking issue for this feature is: [#118485] [#118485]: https://github.com/rust-lang/rust/issues/118485 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "os_string_pathbuf_leak", - description: r##"# `os_string_pathbuf_leak` - -The tracking issue for this feature is: [#125965] - -[#125965]: https://github.com/rust-lang/rust/issues/125965 - ------------------------ "##, default_severity: Severity::Allow, @@ -8873,6 +11504,8 @@ fn foo() { label: "os_string_truncate", description: r##"# `os_string_truncate` + + The tracking issue for this feature is: [#133262] [#133262]: https://github.com/rust-lang/rust/issues/133262 @@ -8887,6 +11520,8 @@ fn foo() { label: "panic_abort", description: r##"# `panic_abort` + + The tracking issue for this feature is: [#32837] [#32837]: https://github.com/rust-lang/rust/issues/32837 @@ -8901,6 +11536,8 @@ fn foo() { label: "panic_always_abort", description: r##"# `panic_always_abort` + + The tracking issue for this feature is: [#84438] [#84438]: https://github.com/rust-lang/rust/issues/84438 @@ -8915,6 +11552,8 @@ fn foo() { label: "panic_backtrace_config", description: r##"# `panic_backtrace_config` + + The tracking issue for this feature is: [#93346] [#93346]: https://github.com/rust-lang/rust/issues/93346 @@ -8929,6 +11568,8 @@ fn foo() { label: "panic_can_unwind", description: r##"# `panic_can_unwind` + + The tracking issue for this feature is: [#92988] [#92988]: https://github.com/rust-lang/rust/issues/92988 @@ -8943,22 +11584,10 @@ fn foo() { label: "panic_internals", description: r##"# `panic_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "panic_payload_as_str", - description: r##"# `panic_payload_as_str` - -The tracking issue for this feature is: [#125175] - -[#125175]: https://github.com/rust-lang/rust/issues/125175 - ------------------------ "##, default_severity: Severity::Allow, @@ -8969,6 +11598,8 @@ fn foo() { label: "panic_runtime", description: r##"# `panic_runtime` +Allows using the `#![panic_runtime]` attribute. + The tracking issue for this feature is: [#32837] [#32837]: https://github.com/rust-lang/rust/issues/32837 @@ -8983,6 +11614,8 @@ fn foo() { label: "panic_unwind", description: r##"# `panic_unwind` + + The tracking issue for this feature is: [#32837] [#32837]: https://github.com/rust-lang/rust/issues/32837 @@ -8997,10 +11630,26 @@ fn foo() { label: "panic_update_hook", description: r##"# `panic_update_hook` + + The tracking issue for this feature is: [#92649] [#92649]: https://github.com/rust-lang/rust/issues/92649 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "partial_ord_chaining_methods", + description: r##"# `partial_ord_chaining_methods` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -9011,6 +11660,8 @@ fn foo() { label: "patchable_function_entry", description: r##"# `patchable_function_entry` +Allows specifying nop padding on functions for dynamic patching. + The tracking issue for this feature is: [#123115] [#123115]: https://github.com/rust-lang/rust/issues/123115 @@ -9022,12 +11673,14 @@ fn foo() { deny_since: None, }, Lint { - label: "path_add_extension", - description: r##"# `path_add_extension` + label: "path_absolute_method", + description: r##"# `path_absolute_method` -The tracking issue for this feature is: [#127292] -[#127292]: https://github.com/rust-lang/rust/issues/127292 + +The tracking issue for this feature is: [#153328] + +[#153328]: https://github.com/rust-lang/rust/issues/153328 ------------------------ "##, @@ -9036,12 +11689,30 @@ fn foo() { deny_since: None, }, Lint { - label: "path_file_prefix", - description: r##"# `path_file_prefix` + label: "path_is_empty", + description: r##"# `path_is_empty` -The tracking issue for this feature is: [#86319] -[#86319]: https://github.com/rust-lang/rust/issues/86319 + +The tracking issue for this feature is: [#148494] + +[#148494]: https://github.com/rust-lang/rust/issues/148494 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "path_trailing_sep", + description: r##"# `path_trailing_sep` + + + +The tracking issue for this feature is: [#142503] + +[#142503]: https://github.com/rust-lang/rust/issues/142503 ------------------------ "##, @@ -9053,6 +11724,8 @@ fn foo() { label: "pattern", description: r##"# `pattern` + + The tracking issue for this feature is: [#27721] [#27721]: https://github.com/rust-lang/rust/issues/27721 @@ -9067,6 +11740,8 @@ fn foo() { label: "pattern_complexity_limit", description: r##"# `pattern_complexity_limit` +Set the maximum pattern complexity allowed (not limited by default). + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9079,6 +11754,24 @@ fn foo() { label: "pattern_type_macro", description: r##"# `pattern_type_macro` + + +The tracking issue for this feature is: [#123646] + +[#123646]: https://github.com/rust-lang/rust/issues/123646 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "pattern_type_range_trait", + description: r##"# `pattern_type_range_trait` + + + The tracking issue for this feature is: [#123646] [#123646]: https://github.com/rust-lang/rust/issues/123646 @@ -9093,6 +11786,8 @@ fn foo() { label: "pattern_types", description: r##"# `pattern_types` +Allows using pattern types. + The tracking issue for this feature is: [#123646] [#123646]: https://github.com/rust-lang/rust/issues/123646 @@ -9107,10 +11802,28 @@ fn foo() { label: "peer_credentials_unix_socket", description: r##"# `peer_credentials_unix_socket` + + The tracking issue for this feature is: [#42839] [#42839]: https://github.com/rust-lang/rust/issues/42839 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "phantom_variance_markers", + description: r##"# `phantom_variance_markers` + + + +The tracking issue for this feature is: [#135806] + +[#135806]: https://github.com/rust-lang/rust/issues/135806 + ------------------------ "##, default_severity: Severity::Allow, @@ -9121,9 +11834,25 @@ fn foo() { label: "pin_coerce_unsized_trait", description: r##"# `pin_coerce_unsized_trait` -The tracking issue for this feature is: [#123430] -[#123430]: https://github.com/rust-lang/rust/issues/123430 + +The tracking issue for this feature is: [#150112] + +[#150112]: https://github.com/rust-lang/rust/issues/150112 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "pin_derefmut_internals", + description: r##"# `pin_derefmut_internals` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -9135,6 +11864,8 @@ fn foo() { label: "pin_ergonomics", description: r##"# `pin_ergonomics` +Experimental features that make `Pin` more ergonomic. + The tracking issue for this feature is: [#130494] [#130494]: https://github.com/rust-lang/rust/issues/130494 @@ -9149,6 +11880,8 @@ fn foo() { label: "pointer_is_aligned_to", description: r##"# `pointer_is_aligned_to` + + The tracking issue for this feature is: [#96284] [#96284]: https://github.com/rust-lang/rust/issues/96284 @@ -9160,10 +11893,14 @@ fn foo() { deny_since: None, }, Lint { - label: "pointer_like_trait", - description: r##"# `pointer_like_trait` + label: "pointer_try_cast_aligned", + description: r##"# `pointer_try_cast_aligned` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + + +The tracking issue for this feature is: [#141221] + +[#141221]: https://github.com/rust-lang/rust/issues/141221 ------------------------ "##, @@ -9175,6 +11912,8 @@ fn foo() { label: "portable_simd", description: r##"# `portable_simd` + + The tracking issue for this feature is: [#86656] [#86656]: https://github.com/rust-lang/rust/issues/86656 @@ -9222,9 +11961,11 @@ fn get_foo() -> Foo { label: "powerpc_target_feature", description: r##"# `powerpc_target_feature` -The tracking issue for this feature is: [#44839] +Target features on powerpc. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150255] + +[#150255]: https://github.com/rust-lang/rust/issues/150255 ------------------------ "##, @@ -9233,26 +11974,12 @@ fn get_foo() -> Foo { deny_since: None, }, Lint { - label: "precise_capturing_in_traits", - description: r##"# `precise_capturing_in_traits` + label: "prelude_future", + description: r##"# `prelude_future` -The tracking issue for this feature is: [#130044] -[#130044]: https://github.com/rust-lang/rust/issues/130044 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "prelude_2024", - description: r##"# `prelude_2024` - -The tracking issue for this feature is: [#121042] - -[#121042]: https://github.com/rust-lang/rust/issues/121042 +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -9264,6 +11991,22 @@ fn get_foo() -> Foo { label: "prelude_import", description: r##"# `prelude_import` +Allows using `#[prelude_import]` on glob `use` items. + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "prelude_next", + description: r##"# `prelude_next` + + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9276,9 +12019,11 @@ fn get_foo() -> Foo { label: "prfchw_target_feature", description: r##"# `prfchw_target_feature` -The tracking issue for this feature is: [#44839] +The prfchw target feature on x86. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150256] + +[#150256]: https://github.com/rust-lang/rust/issues/150256 ------------------------ "##, @@ -9302,6 +12047,8 @@ fn get_foo() -> Foo { label: "proc_macro_def_site", description: r##"# `proc_macro_def_site` + + The tracking issue for this feature is: [#54724] [#54724]: https://github.com/rust-lang/rust/issues/54724 @@ -9316,6 +12063,8 @@ fn get_foo() -> Foo { label: "proc_macro_diagnostic", description: r##"# `proc_macro_diagnostic` + + The tracking issue for this feature is: [#54140] [#54140]: https://github.com/rust-lang/rust/issues/54140 @@ -9330,6 +12079,8 @@ fn get_foo() -> Foo { label: "proc_macro_expand", description: r##"# `proc_macro_expand` + + The tracking issue for this feature is: [#90765] [#90765]: https://github.com/rust-lang/rust/issues/90765 @@ -9344,6 +12095,8 @@ fn get_foo() -> Foo { label: "proc_macro_hygiene", description: r##"# `proc_macro_hygiene` +Allows macro attributes on expressions, statements and non-inline modules. + The tracking issue for this feature is: [#54727] [#54727]: https://github.com/rust-lang/rust/issues/54727 @@ -9358,6 +12111,8 @@ fn get_foo() -> Foo { label: "proc_macro_internals", description: r##"# `proc_macro_internals` + + The tracking issue for this feature is: [#27812] [#27812]: https://github.com/rust-lang/rust/issues/27812 @@ -9372,6 +12127,8 @@ fn get_foo() -> Foo { label: "proc_macro_quote", description: r##"# `proc_macro_quote` + + The tracking issue for this feature is: [#54722] [#54722]: https://github.com/rust-lang/rust/issues/54722 @@ -9386,6 +12143,8 @@ fn get_foo() -> Foo { label: "proc_macro_span", description: r##"# `proc_macro_span` + + The tracking issue for this feature is: [#54725] [#54725]: https://github.com/rust-lang/rust/issues/54725 @@ -9400,6 +12159,8 @@ fn get_foo() -> Foo { label: "proc_macro_totokens", description: r##"# `proc_macro_totokens` + + The tracking issue for this feature is: [#130977] [#130977]: https://github.com/rust-lang/rust/issues/130977 @@ -9414,10 +12175,60 @@ fn get_foo() -> Foo { label: "proc_macro_tracked_env", description: r##"# `proc_macro_tracked_env` + + The tracking issue for this feature is: [#99515] [#99515]: https://github.com/rust-lang/rust/issues/99515 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "proc_macro_tracked_path", + description: r##"# `proc_macro_tracked_path` + + + +The tracking issue for this feature is: [#99515] + +[#99515]: https://github.com/rust-lang/rust/issues/99515 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "proc_macro_value", + description: r##"# `proc_macro_value` + + + +The tracking issue for this feature is: [#136652] + +[#136652]: https://github.com/rust-lang/rust/issues/136652 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "process_chroot", + description: r##"# `process_chroot` + + + +The tracking issue for this feature is: [#141298] + +[#141298]: https://github.com/rust-lang/rust/issues/141298 + ------------------------ "##, default_severity: Severity::Allow, @@ -9428,6 +12239,8 @@ fn get_foo() -> Foo { label: "process_exitcode_internals", description: r##"# `process_exitcode_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9440,8 +12253,26 @@ fn get_foo() -> Foo { label: "process_internals", description: r##"# `process_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "process_setsid", + description: r##"# `process_setsid` + + + +The tracking issue for this feature is: [#105376] + +[#105376]: https://github.com/rust-lang/rust/issues/105376 + ------------------------ "##, default_severity: Severity::Allow, @@ -9466,6 +12297,22 @@ fn get_foo() -> Foo { This feature is internal to the Rust compiler and is not intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "profiling_marker_api", + description: r##"# `profiling_marker_api` + + + +The tracking issue for this feature is: [#148197] + +[#148197]: https://github.com/rust-lang/rust/issues/148197 + ------------------------ "##, default_severity: Severity::Allow, @@ -9476,24 +12323,12 @@ fn get_foo() -> Foo { label: "ptr_alignment_type", description: r##"# `ptr_alignment_type` + + The tracking issue for this feature is: [#102070] [#102070]: https://github.com/rust-lang/rust/issues/102070 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "ptr_as_ref_unchecked", - description: r##"# `ptr_as_ref_unchecked` - -The tracking issue for this feature is: [#122034] - -[#122034]: https://github.com/rust-lang/rust/issues/122034 - ------------------------ "##, default_severity: Severity::Allow, @@ -9504,10 +12339,44 @@ fn get_foo() -> Foo { label: "ptr_as_uninit", description: r##"# `ptr_as_uninit` + + The tracking issue for this feature is: [#75402] [#75402]: https://github.com/rust-lang/rust/issues/75402 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "ptr_cast_array", + description: r##"# `ptr_cast_array` + + + +The tracking issue for this feature is: [#144514] + +[#144514]: https://github.com/rust-lang/rust/issues/144514 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "ptr_cast_slice", + description: r##"# `ptr_cast_slice` + + + +The tracking issue for this feature is: [#149103] + +[#149103]: https://github.com/rust-lang/rust/issues/149103 + ------------------------ "##, default_severity: Severity::Allow, @@ -9518,6 +12387,8 @@ fn get_foo() -> Foo { label: "ptr_internals", description: r##"# `ptr_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9530,6 +12401,8 @@ fn get_foo() -> Foo { label: "ptr_mask", description: r##"# `ptr_mask` + + The tracking issue for this feature is: [#98290] [#98290]: https://github.com/rust-lang/rust/issues/98290 @@ -9544,24 +12417,12 @@ fn get_foo() -> Foo { label: "ptr_metadata", description: r##"# `ptr_metadata` + + The tracking issue for this feature is: [#81513] [#81513]: https://github.com/rust-lang/rust/issues/81513 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "ptr_sub_ptr", - description: r##"# `ptr_sub_ptr` - -The tracking issue for this feature is: [#95892] - -[#95892]: https://github.com/rust-lang/rust/issues/95892 - ------------------------ "##, default_severity: Severity::Allow, @@ -9572,6 +12433,8 @@ fn get_foo() -> Foo { label: "pub_crate_should_not_need_unstable_attr", description: r##"# `pub_crate_should_not_need_unstable_attr` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9584,10 +12447,60 @@ fn get_foo() -> Foo { label: "random", description: r##"# `random` + + The tracking issue for this feature is: [#130703] [#130703]: https://github.com/rust-lang/rust/issues/130703 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "range_bounds_is_empty", + description: r##"# `range_bounds_is_empty` + + + +The tracking issue for this feature is: [#137300] + +[#137300]: https://github.com/rust-lang/rust/issues/137300 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "range_into_bounds", + description: r##"# `range_into_bounds` + + + +The tracking issue for this feature is: [#136903] + +[#136903]: https://github.com/rust-lang/rust/issues/136903 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "raw_dylib_elf", + description: r##"# `raw_dylib_elf` + +Allows the use of raw-dylibs on ELF platforms + +The tracking issue for this feature is: [#135694] + +[#135694]: https://github.com/rust-lang/rust/issues/135694 + ------------------------ "##, default_severity: Severity::Allow, @@ -9598,6 +12511,8 @@ fn get_foo() -> Foo { label: "raw_os_error_ty", description: r##"# `raw_os_error_ty` + + The tracking issue for this feature is: [#107792] [#107792]: https://github.com/rust-lang/rust/issues/107792 @@ -9612,6 +12527,8 @@ fn get_foo() -> Foo { label: "raw_slice_split", description: r##"# `raw_slice_split` + + The tracking issue for this feature is: [#95595] [#95595]: https://github.com/rust-lang/rust/issues/95595 @@ -9626,8 +12543,26 @@ fn get_foo() -> Foo { label: "raw_vec_internals", description: r##"# `raw_vec_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "read_array", + description: r##"# `read_array` + + + +The tracking issue for this feature is: [#148848] + +[#148848]: https://github.com/rust-lang/rust/issues/148848 + ------------------------ "##, default_severity: Severity::Allow, @@ -9638,10 +12573,44 @@ fn get_foo() -> Foo { label: "read_buf", description: r##"# `read_buf` + + The tracking issue for this feature is: [#78485] [#78485]: https://github.com/rust-lang/rust/issues/78485 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "read_buf_at", + description: r##"# `read_buf_at` + + + +The tracking issue for this feature is: [#140771] + +[#140771]: https://github.com/rust-lang/rust/issues/140771 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "reborrow", + description: r##"# `reborrow` + + + +The tracking issue for this feature is: [#145612] + +[#145612]: https://github.com/rust-lang/rust/issues/145612 + ------------------------ "##, default_severity: Severity::Allow, @@ -9652,10 +12621,28 @@ fn get_foo() -> Foo { label: "reentrant_lock", description: r##"# `reentrant_lock` + + The tracking issue for this feature is: [#121440] [#121440]: https://github.com/rust-lang/rust/issues/121440 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "reentrant_lock_data_ptr", + description: r##"# `reentrant_lock_data_ptr` + + + +The tracking issue for this feature is: [#140368] + +[#140368]: https://github.com/rust-lang/rust/issues/140368 + ------------------------ "##, default_severity: Severity::Allow, @@ -9670,7 +12657,41 @@ fn get_foo() -> Foo { [#123076]: https://github.com/rust-lang/rust/issues/123076 ------------------------- +--- + +This feature is incomplete and not yet intended for general use. + +This implements experimental, Edition-dependent match ergonomics under consideration for inclusion +in Rust, allowing `&` patterns in more places. For example: + +```rust,edition2024 +#![feature(ref_pat_eat_one_layer_2024)] +#![allow(incomplete_features)] +# +# // Tests type equality in a way that avoids coercing `&&T` or `&mut T` to `&T`. +# trait Eq {} +# impl Eq for T {} +# fn has_type(_: impl Eq) {} + +// `&` can match against a `ref` binding mode instead of a reference type: +let (x, &y) = &(0, 1); +has_type::<&u8>(x); +has_type::(y); + +// `&` can match against `&mut` references: +let &z = &mut 2; +has_type::(z); +``` + +For specifics, see the corresponding typing rules for [Editions 2021 and earlier] and for +[Editions 2024 and later]. For more information on binding modes, see [The Rust Reference]. + +For alternative experimental match ergonomics, see the feature +[`ref_pat_eat_one_layer_2024_structural`](./ref-pat-eat-one-layer-2024-structural.md). + +[Editions 2021 and earlier]: https://nadrieril.github.io/typing-rust-patterns/?compare=false&opts1=AQEBAQIBAQABAAAAAQEBAAEBAAABAAA%3D&mode=rules&do_cmp=false +[Editions 2024 and later]: https://nadrieril.github.io/typing-rust-patterns/?compare=false&opts1=AQEBAAABAQABAgIAAQEBAAEBAAABAAA%3D&mode=rules&do_cmp=false +[The Rust Reference]: https://doc.rust-lang.org/reference/patterns.html#binding-modes "##, default_severity: Severity::Allow, warn_since: None, @@ -9684,6 +12705,55 @@ fn get_foo() -> Foo { [#123076]: https://github.com/rust-lang/rust/issues/123076 +--- + +This feature is incomplete and not yet intended for general use. + +This implements experimental, Edition-dependent match ergonomics under consideration for inclusion +in Rust, allowing `&` patterns in more places. For example: +```rust,edition2024 +#![feature(ref_pat_eat_one_layer_2024_structural)] +#![allow(incomplete_features)] +# +# // Tests type equality in a way that avoids coercing `&&T` or `&mut T` to `&T`. +# trait Eq {} +# impl Eq for T {} +# fn has_type(_: impl Eq) {} + +// `&` can match against a `ref` binding mode instead of a reference type: +let (x, &y) = &(0, 1); +has_type::<&u8>(x); +has_type::(y); + +// `&` can match against `&mut` references: +let &z = &mut 2; +has_type::(z); +``` + +For specifics, see the corresponding typing rules for [Editions 2021 and earlier] and for +[Editions 2024 and later]. For more information on binding modes, see [The Rust Reference]. + +For alternative experimental match ergonomics, see the feature +[`ref_pat_eat_one_layer_2024`](./ref-pat-eat-one-layer-2024.md). + +[Editions 2021 and earlier]: https://nadrieril.github.io/typing-rust-patterns/?compare=false&opts1=AQEBAQIBAQEBAAAAAAAAAAAAAAAAAAA%3D&mode=rules&do_cmp=false +[Editions 2024 and later]: https://nadrieril.github.io/typing-rust-patterns/?compare=false&opts1=AQEBAgEBAQEBAgIAAAAAAAAAAAAAAAA%3D&mode=rules&do_cmp=false +[The Rust Reference]: https://doc.rust-lang.org/reference/patterns.html#binding-modes +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "refcell_try_map", + description: r##"# `refcell_try_map` + + + +The tracking issue for this feature is: [#143801] + +[#143801]: https://github.com/rust-lang/rust/issues/143801 + ------------------------ "##, default_severity: Severity::Allow, @@ -9699,31 +12769,54 @@ fn get_foo() -> Foo { [#66079]: https://github.com/rust-lang/rust/issues/66079 ------------------------ -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "repr128", - description: r##"# `repr128` -The tracking issue for this feature is: [#56071] +The `register_tool` language feature informs the compiler that attributes in your code are meant to be used with tools other than the compiler itself. This can be useful if your code has semantic meaning without the external tool, but enables additional features when the tool is present. -[#56071]: https://github.com/rust-lang/rust/issues/56071 +`register_tool` also allows configuring lint levels for external tools. + +Tool attributes are only meant for ignorable attributes. If your code *changes* meaning when the attribute is present, it should not use a tool attribute (because it cannot be compiled with anything other than the external tool, and in a sense is a fork of the language). ------------------------ -The `repr128` feature adds support for `#[repr(u128)]` on `enum`s. +`#![register_tool(tool)]` is an attribute, and is only valid at the crate root. +Attributes using the registered tool are checked for valid syntax, and lint attributes are checked to be in a valid format. However, the compiler cannot validate the semantics of the attribute, nor can it tell whether the configured lint is present in the external tool. + +Semantically, `clippy::*`, `rustdoc::*`, and `rustfmt::*` lints and attributes all behave as if `#![register_tool(clippy, rustdoc, rustfmt)]` were injected into the crate root, except that the `rustdoc` namespace can only be used for lints, not for attributes. +When compiling with `-Z unstable-features`, `rustc::*` lints can also be used. Like `rustdoc`, the `rustc` namespace can only be used with lints, not attributes. + +The compiler will emit an error if it encounters a lint/attribute whose namespace isn't a registered tool. + +Tool namespaces cannot be nested; `register_tool(main_tool::subtool)` is an error. + +## Examples + +Tool attributes: ```rust -#![feature(repr128)] +#![feature(register_tool)] +#![register_tool(c2rust)] -#[repr(u128)] -enum Foo { - Bar(u64), +// Mark which C header file this module was generated from. +#[c2rust::header_src = "operations.h"] +pub mod operations_h { + use std::ffi::c_int; + + // Mark which source line this struct was generated from. + #[c2rust::src_loc = "11:0"] + pub struct Point { + pub x: c_int, + pub y: c_int, + } } ``` + +Tool lints: + +``` +#![feature(register_tool)] +#![register_tool(bevy)] +#![deny(bevy::duplicate_bevy_dependencies)] +``` "##, default_severity: Severity::Allow, warn_since: None, @@ -9733,6 +12826,8 @@ enum Foo { label: "repr_simd", description: r##"# `repr_simd` +Allows `repr(simd)` and importing the various simd intrinsics. + The tracking issue for this feature is: [#27731] [#27731]: https://github.com/rust-lang/rust/issues/27731 @@ -9747,6 +12842,8 @@ enum Foo { label: "restricted_std", description: r##"# `restricted_std` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -9756,12 +12853,14 @@ enum Foo { deny_since: None, }, Lint { - label: "result_flattening", - description: r##"# `result_flattening` + label: "result_option_map_or_default", + description: r##"# `result_option_map_or_default` -The tracking issue for this feature is: [#70142] -[#70142]: https://github.com/rust-lang/rust/issues/70142 + +The tracking issue for this feature is: [#138099] + +[#138099]: https://github.com/rust-lang/rust/issues/138099 ------------------------ "##, @@ -9773,6 +12872,8 @@ enum Foo { label: "return_type_notation", description: r##"# `return_type_notation` +Allows bounding the return type of AFIT/RPITIT. + The tracking issue for this feature is: [#109417] [#109417]: https://github.com/rust-lang/rust/issues/109417 @@ -9784,12 +12885,14 @@ enum Foo { deny_since: None, }, Lint { - label: "riscv_target_feature", - description: r##"# `riscv_target_feature` + label: "rev_into_inner", + description: r##"# `rev_into_inner` -The tracking issue for this feature is: [#44839] -[#44839]: https://github.com/rust-lang/rust/issues/44839 + +The tracking issue for this feature is: [#144277] + +[#144277]: https://github.com/rust-lang/rust/issues/144277 ------------------------ "##, @@ -9798,12 +12901,14 @@ enum Foo { deny_since: None, }, Lint { - label: "round_char_boundary", - description: r##"# `round_char_boundary` + label: "riscv_target_feature", + description: r##"# `riscv_target_feature` -The tracking issue for this feature is: [#93743] +Target features on riscv. -[#93743]: https://github.com/rust-lang/rust/issues/93743 +The tracking issue for this feature is: [#150257] + +[#150257]: https://github.com/rust-lang/rust/issues/150257 ------------------------ "##, @@ -9827,9 +12932,11 @@ enum Foo { label: "rtm_target_feature", description: r##"# `rtm_target_feature` -The tracking issue for this feature is: [#44839] +The rtm target feature on x86. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150258] + +[#150258]: https://github.com/rust-lang/rust/issues/150258 ------------------------ "##, @@ -9841,6 +12948,8 @@ enum Foo { label: "rust_cold_cc", description: r##"# `rust_cold_cc` +Allows `extern "rust-cold"`. + The tracking issue for this feature is: [#97544] [#97544]: https://github.com/rust-lang/rust/issues/97544 @@ -9852,12 +12961,14 @@ enum Foo { deny_since: None, }, Lint { - label: "rustc_allow_const_fn_unstable", - description: r##"# `rustc_allow_const_fn_unstable` + label: "rust_preserve_none_cc", + description: r##"# `rust_preserve_none_cc` -The tracking issue for this feature is: [#69399] +Allows `extern "rust-preserve-none"`. -[#69399]: https://github.com/rust-lang/rust/issues/69399 +The tracking issue for this feature is: [#151401] + +[#151401]: https://github.com/rust-lang/rust/issues/151401 ------------------------ "##, @@ -9920,18 +13031,6 @@ pub enum X { error: aborting due to 2 previous errors ``` -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "rustc_encodable_decodable", - description: r##"# `rustc_encodable_decodable` - -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. - ------------------------- "##, default_severity: Severity::Allow, warn_since: None, @@ -9947,9 +13046,42 @@ pub enum X { ------------------------ -This feature allows access to unstable internal compiler crates. +This feature allows access to unstable internal compiler crates such as `rustc_driver`. -Additionally it changes the linking behavior of crates which have this feature enabled. It will prevent linking to a dylib if there's a static variant of it already statically linked into another dylib dependency. This is required to successfully link to `rustc_driver`. +The presence of this feature changes the way the linkage format for dylibs is calculated in a way +that is necessary for linking against dylibs that statically link `std` (such as `rustc_driver`). +This makes this feature "viral" in linkage; its use in a given crate makes its use required in +dependent crates which link to it (including integration tests, which are built as separate crates). + +## Common linker failures related to missing LLVM libraries + +### When using `rustc-private` with Official Toolchains + +When using the `rustc_private` feature with official toolchains distributed via rustup, you'll need to install: + +1. The `rustc-dev` component (provides compiler libraries) +2. The `llvm-tools` component (provides LLVM libraries needed for linking) + +You can install these components using `rustup`: + +```text +rustup component add rustc-dev llvm-tools +``` + +Without the `llvm-tools` component, you may encounter linking errors like: + +```text +error: linking with `cc` failed: exit status: 1 + | + = note: rust-lld: error: unable to find library -lLLVM-{version} +``` + +### When using `rustc-private` with Custom Toolchains + +For custom-built toolchains or environments not using rustup, different configuration may be required: + +- Ensure LLVM libraries are available in your library search paths +- You might need to configure library paths explicitly depending on your LLVM installation "##, default_severity: Severity::Allow, warn_since: None, @@ -9959,6 +13091,8 @@ pub enum X { label: "rustdoc_internals", description: r##"# `rustdoc_internals` +Allows using internal rustdoc features like `doc(keyword)`. + The tracking issue for this feature is: [#90418] [#90418]: https://github.com/rust-lang/rust/issues/90418 @@ -9973,6 +13107,8 @@ pub enum X { label: "rustdoc_missing_doc_code_examples", description: r##"# `rustdoc_missing_doc_code_examples` +Allows using the `rustdoc::missing_doc_code_examples` lint + The tracking issue for this feature is: [#101730] [#101730]: https://github.com/rust-lang/rust/issues/101730 @@ -9984,12 +13120,14 @@ pub enum X { deny_since: None, }, Lint { - label: "rwlock_downgrade", - description: r##"# `rwlock_downgrade` + label: "rwlock_data_ptr", + description: r##"# `rwlock_data_ptr` -The tracking issue for this feature is: [#128203] -[#128203]: https://github.com/rust-lang/rust/issues/128203 + +The tracking issue for this feature is: [#140368] + +[#140368]: https://github.com/rust-lang/rust/issues/140368 ------------------------ "##, @@ -10001,11 +13139,93 @@ pub enum X { label: "s390x_target_feature", description: r##"# `s390x_target_feature` -The tracking issue for this feature is: [#44839] +Target features on s390x. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150259] + +[#150259]: https://github.com/rust-lang/rust/issues/150259 ------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "sanitize", + description: r##"# `sanitize` + +The tracking issue for this feature is: [#39699] + +[#39699]: https://github.com/rust-lang/rust/issues/39699 + +------------------------ + +The `sanitize` attribute can be used to selectively disable or enable sanitizer +instrumentation in an annotated function. This might be useful to: avoid +instrumentation overhead in a performance critical function, or avoid +instrumenting code that contains constructs unsupported by given sanitizer. + +The precise effect of this annotation depends on particular sanitizer in use. +For example, with `sanitize(thread = "off")`, the thread sanitizer will no +longer instrument non-atomic store / load operations, but it will instrument +atomic operations to avoid reporting false positives and provide meaning full +stack traces. + +This attribute was previously named `no_sanitize`. + +## Examples + +``` rust +#![feature(sanitize)] + +#[sanitize(address = "off")] +fn foo() { + // ... +} +``` + +It is also possible to disable sanitizers for entire modules and enable them +for single items or functions. + +```rust +#![feature(sanitize)] + +#[sanitize(address = "off")] +mod foo { + fn unsanitized() { + // ... + } + + #[sanitize(address = "on")] + fn sanitized() { + // ... + } +} +``` + +It's also applicable to impl blocks. + +```rust +#![feature(sanitize)] + +trait MyTrait { + fn foo(&self); + fn bar(&self); +} + +#[sanitize(address = "off")] +impl MyTrait for () { + fn foo(&self) { + // ... + } + + #[sanitize(address = "on")] + fn bar(&self) { + // ... + } +} +``` "##, default_severity: Severity::Allow, warn_since: None, @@ -10015,8 +13235,26 @@ pub enum X { label: "sealed", description: r##"# `sealed` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "seek_io_take_position", + description: r##"# `seek_io_take_position` + + + +The tracking issue for this feature is: [#97227] + +[#97227]: https://github.com/rust-lang/rust/issues/97227 + ------------------------ "##, default_severity: Severity::Allow, @@ -10027,10 +13265,28 @@ pub enum X { label: "seek_stream_len", description: r##"# `seek_stream_len` + + The tracking issue for this feature is: [#59359] [#59359]: https://github.com/rust-lang/rust/issues/59359 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "set_permissions_nofollow", + description: r##"# `set_permissions_nofollow` + + + +The tracking issue for this feature is: [#141607] + +[#141607]: https://github.com/rust-lang/rust/issues/141607 + ------------------------ "##, default_severity: Severity::Allow, @@ -10041,6 +13297,8 @@ pub enum X { label: "set_ptr_value", description: r##"# `set_ptr_value` + + The tracking issue for this feature is: [#75091] [#75091]: https://github.com/rust-lang/rust/issues/75091 @@ -10055,6 +13313,8 @@ pub enum X { label: "setgroups", description: r##"# `setgroups` + + The tracking issue for this feature is: [#90747] [#90747]: https://github.com/rust-lang/rust/issues/90747 @@ -10069,6 +13329,8 @@ pub enum X { label: "sgx_platform", description: r##"# `sgx_platform` + + The tracking issue for this feature is: [#56975] [#56975]: https://github.com/rust-lang/rust/issues/56975 @@ -10080,12 +13342,14 @@ pub enum X { deny_since: None, }, Lint { - label: "sha512_sm_x86", - description: r##"# `sha512_sm_x86` + label: "signed_bigint_helpers", + description: r##"# `signed_bigint_helpers` -The tracking issue for this feature is: [#126624] -[#126624]: https://github.com/rust-lang/rust/issues/126624 + +The tracking issue for this feature is: [#151989] + +[#151989]: https://github.com/rust-lang/rust/issues/151989 ------------------------ "##, @@ -10097,10 +13361,28 @@ pub enum X { label: "simd_ffi", description: r##"# `simd_ffi` +Allows the use of SIMD types in functions declared in `extern` blocks. + The tracking issue for this feature is: [#27731] [#27731]: https://github.com/rust-lang/rust/issues/27731 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "sized_hierarchy", + description: r##"# `sized_hierarchy` + +Introduces a hierarchy of `Sized` traits (RFC 3729). + +The tracking issue for this feature is: [#144404] + +[#144404]: https://github.com/rust-lang/rust/issues/144404 + ------------------------ "##, default_severity: Severity::Allow, @@ -10111,36 +13393,10 @@ pub enum X { label: "sized_type_properties", description: r##"# `sized_type_properties` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "slice_as_array", - description: r##"# `slice_as_array` - -The tracking issue for this feature is: [#133508] - -[#133508]: https://github.com/rust-lang/rust/issues/133508 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "slice_as_chunks", - description: r##"# `slice_as_chunks` - -The tracking issue for this feature is: [#74985] - -[#74985]: https://github.com/rust-lang/rust/issues/74985 - ------------------------ "##, default_severity: Severity::Allow, @@ -10151,6 +13407,8 @@ pub enum X { label: "slice_concat_ext", description: r##"# `slice_concat_ext` + + The tracking issue for this feature is: [#27747] [#27747]: https://github.com/rust-lang/rust/issues/27747 @@ -10165,6 +13423,8 @@ pub enum X { label: "slice_concat_trait", description: r##"# `slice_concat_trait` + + The tracking issue for this feature is: [#27747] [#27747]: https://github.com/rust-lang/rust/issues/27747 @@ -10179,6 +13439,8 @@ pub enum X { label: "slice_from_ptr_range", description: r##"# `slice_from_ptr_range` + + The tracking issue for this feature is: [#89792] [#89792]: https://github.com/rust-lang/rust/issues/89792 @@ -10193,6 +13455,8 @@ pub enum X { label: "slice_index_methods", description: r##"# `slice_index_methods` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -10205,6 +13469,8 @@ pub enum X { label: "slice_internals", description: r##"# `slice_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -10217,10 +13483,28 @@ pub enum X { label: "slice_iter_mut_as_mut_slice", description: r##"# `slice_iter_mut_as_mut_slice` + + The tracking issue for this feature is: [#93079] [#93079]: https://github.com/rust-lang/rust/issues/93079 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "slice_partial_sort_unstable", + description: r##"# `slice_partial_sort_unstable` + + + +The tracking issue for this feature is: [#149046] + +[#149046]: https://github.com/rust-lang/rust/issues/149046 + ------------------------ "##, default_severity: Severity::Allow, @@ -10231,6 +13515,8 @@ pub enum X { label: "slice_partition_dedup", description: r##"# `slice_partition_dedup` + + The tracking issue for this feature is: [#54279] [#54279]: https://github.com/rust-lang/rust/issues/54279 @@ -10245,6 +13531,8 @@ pub enum X { label: "slice_pattern", description: r##"# `slice_pattern` + + The tracking issue for this feature is: [#56345] [#56345]: https://github.com/rust-lang/rust/issues/56345 @@ -10259,6 +13547,8 @@ pub enum X { label: "slice_ptr_get", description: r##"# `slice_ptr_get` + + The tracking issue for this feature is: [#74265] [#74265]: https://github.com/rust-lang/rust/issues/74265 @@ -10273,10 +13563,28 @@ pub enum X { label: "slice_range", description: r##"# `slice_range` + + The tracking issue for this feature is: [#76393] [#76393]: https://github.com/rust-lang/rust/issues/76393 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "slice_shift", + description: r##"# `slice_shift` + + + +The tracking issue for this feature is: [#151772] + +[#151772]: https://github.com/rust-lang/rust/issues/151772 + ------------------------ "##, default_severity: Severity::Allow, @@ -10287,6 +13595,8 @@ pub enum X { label: "slice_split_once", description: r##"# `slice_split_once` + + The tracking issue for this feature is: [#112811] [#112811]: https://github.com/rust-lang/rust/issues/112811 @@ -10301,6 +13611,8 @@ pub enum X { label: "slice_swap_unchecked", description: r##"# `slice_swap_unchecked` + + The tracking issue for this feature is: [#88539] [#88539]: https://github.com/rust-lang/rust/issues/88539 @@ -10312,12 +13624,30 @@ pub enum X { deny_since: None, }, Lint { - label: "slice_take", - description: r##"# `slice_take` + label: "sliceindex_wrappers", + description: r##"# `sliceindex_wrappers` -The tracking issue for this feature is: [#62280] -[#62280]: https://github.com/rust-lang/rust/issues/62280 + +The tracking issue for this feature is: [#146179] + +[#146179]: https://github.com/rust-lang/rust/issues/146179 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "smart_pointer_try_map", + description: r##"# `smart_pointer_try_map` + + + +The tracking issue for this feature is: [#144419] + +[#144419]: https://github.com/rust-lang/rust/issues/144419 ------------------------ "##, @@ -10329,6 +13659,8 @@ pub enum X { label: "solid_ext", description: r##"# `solid_ext` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -10341,6 +13673,8 @@ pub enum X { label: "sort_floats", description: r##"# `sort_floats` + + The tracking issue for this feature is: [#93396] [#93396]: https://github.com/rust-lang/rust/issues/93396 @@ -10355,6 +13689,8 @@ pub enum X { label: "sparc_target_feature", description: r##"# `sparc_target_feature` +Target features on sparc. + The tracking issue for this feature is: [#132783] [#132783]: https://github.com/rust-lang/rust/issues/132783 @@ -10369,6 +13705,8 @@ pub enum X { label: "specialization", description: r##"# `specialization` +Allows specialization of implementations (RFC 1210). + The tracking issue for this feature is: [#31844] [#31844]: https://github.com/rust-lang/rust/issues/31844 @@ -10383,6 +13721,8 @@ pub enum X { label: "split_array", description: r##"# `split_array` + + The tracking issue for this feature is: [#90091] [#90091]: https://github.com/rust-lang/rust/issues/90091 @@ -10397,24 +13737,12 @@ pub enum X { label: "split_as_slice", description: r##"# `split_as_slice` + + The tracking issue for this feature is: [#96137] [#96137]: https://github.com/rust-lang/rust/issues/96137 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "sse4a_target_feature", - description: r##"# `sse4a_target_feature` - -The tracking issue for this feature is: [#44839] - -[#44839]: https://github.com/rust-lang/rust/issues/44839 - ------------------------ "##, default_severity: Severity::Allow, @@ -10425,6 +13753,8 @@ pub enum X { label: "staged_api", description: r##"# `staged_api` +Allows using the `#[stable]` and `#[unstable]` attributes. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -10434,66 +13764,16 @@ pub enum X { deny_since: None, }, Lint { - label: "start", - description: r##"# `start` + label: "static_align", + description: r##"# `static_align` -The tracking issue for this feature is: [#29633] +Allows using `#[rustc_align_static(...)]` on static items. -[#29633]: https://github.com/rust-lang/rust/issues/29633 +The tracking issue for this feature is: [#146177] + +[#146177]: https://github.com/rust-lang/rust/issues/146177 ------------------------ - -Allows you to mark a function as the entry point of the executable, which is -necessary in `#![no_std]` environments. - -The function marked `#[start]` is passed the command line parameters in the same -format as the C main function (aside from the integer types being used). -It has to be non-generic and have the following signature: - -```rust,ignore (only-for-syntax-highlight) -# let _: -fn(isize, *const *const u8) -> isize -# ; -``` - -This feature should not be confused with the `start` *lang item* which is -defined by the `std` crate and is written `#[lang = "start"]`. - -## Usage together with the `std` crate - -`#[start]` can be used in combination with the `std` crate, in which case the -normal `main` function (which would get called from the `std` crate) won't be -used as an entry point. -The initialization code in `std` will be skipped this way. - -Example: - -```rust -#![feature(start)] - -#[start] -fn start(_argc: isize, _argv: *const *const u8) -> isize { - 0 -} -``` - -Unwinding the stack past the `#[start]` function is currently considered -Undefined Behavior (for any unwinding implementation): - -```rust,ignore (UB) -#![feature(start)] - -#[start] -fn start(_argc: isize, _argv: *const *const u8) -> isize { - std::panic::catch_unwind(|| { - panic!(); // panic safely gets caught or safely aborts execution - }); - - panic!(); // UB! - - 0 -} -``` "##, default_severity: Severity::Allow, warn_since: None, @@ -10503,8 +13783,26 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "std_internals", description: r##"# `std_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdarch_aarch64_feature_detection", + description: r##"# `stdarch_aarch64_feature_detection` + + + +The tracking issue for this feature is: [#127764] + +[#127764]: https://github.com/rust-lang/rust/issues/127764 + ------------------------ "##, default_severity: Severity::Allow, @@ -10515,10 +13813,42 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "stdarch_arm_feature_detection", description: r##"# `stdarch_arm_feature_detection` + + The tracking issue for this feature is: [#111190] [#111190]: https://github.com/rust-lang/rust/issues/111190 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdarch_internal", + description: r##"# `stdarch_internal` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdarch_loongarch_feature_detection", + description: r##"# `stdarch_loongarch_feature_detection` + + + +The tracking issue for this feature is: [#117425] + +[#117425]: https://github.com/rust-lang/rust/issues/117425 + ------------------------ "##, default_severity: Severity::Allow, @@ -10529,6 +13859,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "stdarch_mips_feature_detection", description: r##"# `stdarch_mips_feature_detection` + + The tracking issue for this feature is: [#111188] [#111188]: https://github.com/rust-lang/rust/issues/111188 @@ -10543,10 +13875,44 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "stdarch_powerpc_feature_detection", description: r##"# `stdarch_powerpc_feature_detection` + + The tracking issue for this feature is: [#111191] [#111191]: https://github.com/rust-lang/rust/issues/111191 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdarch_riscv_feature_detection", + description: r##"# `stdarch_riscv_feature_detection` + + + +The tracking issue for this feature is: [#111192] + +[#111192]: https://github.com/rust-lang/rust/issues/111192 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdio_fd_consts", + description: r##"# `stdio_fd_consts` + + + +The tracking issue for this feature is: [#150836] + +[#150836]: https://github.com/rust-lang/rust/issues/150836 + ------------------------ "##, default_severity: Severity::Allow, @@ -10557,10 +13923,28 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "stdio_makes_pipe", description: r##"# `stdio_makes_pipe` + + The tracking issue for this feature is: [#98288] [#98288]: https://github.com/rust-lang/rust/issues/98288 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "stdio_swap", + description: r##"# `stdio_swap` + + + +The tracking issue for this feature is: [#150667] + +[#150667]: https://github.com/rust-lang/rust/issues/150667 + ------------------------ "##, default_severity: Severity::Allow, @@ -10571,6 +13955,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "step_trait", description: r##"# `step_trait` + + The tracking issue for this feature is: [#42168] [#42168]: https://github.com/rust-lang/rust/issues/42168 @@ -10585,6 +13971,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "stmt_expr_attributes", description: r##"# `stmt_expr_attributes` +Allows attributes on expressions and non-item statements. + The tracking issue for this feature is: [#15701] [#15701]: https://github.com/rust-lang/rust/issues/15701 @@ -10599,6 +13987,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_as_str", description: r##"# `str_as_str` + + The tracking issue for this feature is: [#130366] [#130366]: https://github.com/rust-lang/rust/issues/130366 @@ -10613,6 +14003,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_from_raw_parts", description: r##"# `str_from_raw_parts` + + The tracking issue for this feature is: [#119206] [#119206]: https://github.com/rust-lang/rust/issues/119206 @@ -10627,6 +14019,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_from_utf16_endian", description: r##"# `str_from_utf16_endian` + + The tracking issue for this feature is: [#116258] [#116258]: https://github.com/rust-lang/rust/issues/116258 @@ -10653,6 +14047,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_lines_remainder", description: r##"# `str_lines_remainder` + + The tracking issue for this feature is: [#77998] [#77998]: https://github.com/rust-lang/rust/issues/77998 @@ -10667,6 +14063,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_split_inclusive_remainder", description: r##"# `str_split_inclusive_remainder` + + The tracking issue for this feature is: [#77998] [#77998]: https://github.com/rust-lang/rust/issues/77998 @@ -10681,6 +14079,8 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_split_remainder", description: r##"# `str_split_remainder` + + The tracking issue for this feature is: [#77998] [#77998]: https://github.com/rust-lang/rust/issues/77998 @@ -10695,24 +14095,12 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { label: "str_split_whitespace_remainder", description: r##"# `str_split_whitespace_remainder` + + The tracking issue for this feature is: [#77998] [#77998]: https://github.com/rust-lang/rust/issues/77998 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "strict_provenance_atomic_ptr", - description: r##"# `strict_provenance_atomic_ptr` - -The tracking issue for this feature is: [#99108] - -[#99108]: https://github.com/rust-lang/rust/issues/99108 - ------------------------ "##, default_severity: Severity::Allow, @@ -10742,72 +14130,6 @@ fn main() { //~^ WARNING: strict provenance disallows casting integer `usize` to pointer `*const u8` } ``` -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "string_deref_patterns", - description: r##"# `string_deref_patterns` - -The tracking issue for this feature is: [#87121] - -[#87121]: https://github.com/rust-lang/rust/issues/87121 - ------------------------- - -This feature permits pattern matching `String` to `&str` through [its `Deref` implementation]. - -```rust -#![feature(string_deref_patterns)] - -pub enum Value { - String(String), - Number(u32), -} - -pub fn is_it_the_answer(value: Value) -> bool { - match value { - Value::String("42") => true, - Value::Number(42) => true, - _ => false, - } -} -``` - -Without this feature other constructs such as match guards have to be used. - -```rust -# pub enum Value { -# String(String), -# Number(u32), -# } -# -pub fn is_it_the_answer(value: Value) -> bool { - match value { - Value::String(s) if s == "42" => true, - Value::Number(42) => true, - _ => false, - } -} -``` - -[its `Deref` implementation]: https://doc.rust-lang.org/std/string/struct.String.html#impl-Deref-for-String -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "string_extend_from_within", - description: r##"# `string_extend_from_within` - -The tracking issue for this feature is: [#103806] - -[#103806]: https://github.com/rust-lang/rust/issues/103806 - ------------------------- "##, default_severity: Severity::Allow, warn_since: None, @@ -10817,10 +14139,28 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "string_from_utf8_lossy_owned", description: r##"# `string_from_utf8_lossy_owned` + + The tracking issue for this feature is: [#129436] [#129436]: https://github.com/rust-lang/rust/issues/129436 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "string_into_chars", + description: r##"# `string_into_chars` + + + +The tracking issue for this feature is: [#133125] + +[#133125]: https://github.com/rust-lang/rust/issues/133125 + ------------------------ "##, default_severity: Severity::Allow, @@ -10831,10 +14171,44 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "string_remove_matches", description: r##"# `string_remove_matches` + + The tracking issue for this feature is: [#72826] [#72826]: https://github.com/rust-lang/rust/issues/72826 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "string_replace_in_place", + description: r##"# `string_replace_in_place` + + + +The tracking issue for this feature is: [#147949] + +[#147949]: https://github.com/rust-lang/rust/issues/147949 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "strip_circumfix", + description: r##"# `strip_circumfix` + + + +The tracking issue for this feature is: [#147946] + +[#147946]: https://github.com/rust-lang/rust/issues/147946 + ------------------------ "##, default_severity: Severity::Allow, @@ -10845,6 +14219,8 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "structural_match", description: r##"# `structural_match` +Allows using `#[structural_match]` which indicates that a type is structurally matchable. FIXME: Subsumed by trait `StructuralPartialEq`, cannot move to removed until a library feature with the same name exists. + The tracking issue for this feature is: [#31434] [#31434]: https://github.com/rust-lang/rust/issues/31434 @@ -10859,10 +14235,76 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "substr_range", description: r##"# `substr_range` + + The tracking issue for this feature is: [#126769] [#126769]: https://github.com/rust-lang/rust/issues/126769 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "super_let", + description: r##"# `super_let` + +Allows `super let` statements. + +The tracking issue for this feature is: [#139076] + +[#139076]: https://github.com/rust-lang/rust/issues/139076 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "supertrait_item_shadowing", + description: r##"# `supertrait_item_shadowing` + +Allows subtrait items to shadow supertrait items. + +The tracking issue for this feature is: [#89151] + +[#89151]: https://github.com/rust-lang/rust/issues/89151 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "sync_nonpoison", + description: r##"# `sync_nonpoison` + + + +The tracking issue for this feature is: [#134645] + +[#134645]: https://github.com/rust-lang/rust/issues/134645 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "sync_poison_mod", + description: r##"# `sync_poison_mod` + + + +The tracking issue for this feature is: [#134646] + +[#134646]: https://github.com/rust-lang/rust/issues/134646 + ------------------------ "##, default_severity: Severity::Allow, @@ -10873,6 +14315,8 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "sync_unsafe_cell", description: r##"# `sync_unsafe_cell` + + The tracking issue for this feature is: [#95439] [#95439]: https://github.com/rust-lang/rust/issues/95439 @@ -10884,26 +14328,14 @@ pub fn is_it_the_answer(value: Value) -> bool { deny_since: None, }, Lint { - label: "target_feature_11", - description: r##"# `target_feature_11` + label: "target_feature_inline_always", + description: r##"# `target_feature_inline_always` -The tracking issue for this feature is: [#69098] +Allows the use of target_feature when a function is marked inline(always). -[#69098]: https://github.com/rust-lang/rust/issues/69098 +The tracking issue for this feature is: [#145574] ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "tbm_target_feature", - description: r##"# `tbm_target_feature` - -The tracking issue for this feature is: [#44839] - -[#44839]: https://github.com/rust-lang/rust/issues/44839 +[#145574]: https://github.com/rust-lang/rust/issues/145574 ------------------------ "##, @@ -10915,6 +14347,8 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "tcp_deferaccept", description: r##"# `tcp_deferaccept` + + The tracking issue for this feature is: [#119639] [#119639]: https://github.com/rust-lang/rust/issues/119639 @@ -10929,6 +14363,8 @@ pub fn is_it_the_answer(value: Value) -> bool { label: "tcp_linger", description: r##"# `tcp_linger` + + The tracking issue for this feature is: [#88494] [#88494]: https://github.com/rust-lang/rust/issues/88494 @@ -10940,12 +14376,14 @@ pub fn is_it_the_answer(value: Value) -> bool { deny_since: None, }, Lint { - label: "tcp_quickack", - description: r##"# `tcp_quickack` + label: "tcplistener_into_incoming", + description: r##"# `tcplistener_into_incoming` -The tracking issue for this feature is: [#96256] -[#96256]: https://github.com/rust-lang/rust/issues/96256 + +The tracking issue for this feature is: [#88373] + +[#88373]: https://github.com/rust-lang/rust/issues/88373 ------------------------ "##, @@ -10954,12 +14392,12 @@ pub fn is_it_the_answer(value: Value) -> bool { deny_since: None, }, Lint { - label: "tcplistener_into_incoming", - description: r##"# `tcplistener_into_incoming` + label: "temporary_niche_types", + description: r##"# `temporary_niche_types` -The tracking issue for this feature is: [#88373] -[#88373]: https://github.com/rust-lang/rust/issues/88373 + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ "##, @@ -11127,6 +14565,20 @@ fn bench_xor_1000_ints(b: &mut Bencher) { However, the optimizer can still modify a testcase in an undesirable manner even when using either of the above. +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "test_incomplete_feature", + description: r##"# `test_incomplete_feature` + +Perma-unstable, only used to test the `incomplete_features` lint. + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -11136,6 +14588,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "test_unstable_lint", description: r##"# `test_unstable_lint` +Added for testing unstable lints; perma-unstable. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11148,6 +14602,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thin_box", description: r##"# `thin_box` + + The tracking issue for this feature is: [#92791] [#92791]: https://github.com/rust-lang/rust/issues/92791 @@ -11162,6 +14618,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thread_id_value", description: r##"# `thread_id_value` + + The tracking issue for this feature is: [#67939] [#67939]: https://github.com/rust-lang/rust/issues/67939 @@ -11176,6 +14634,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thread_local", description: r##"# `thread_local` +Allows using `#[thread_local]` on `static` items. + The tracking issue for this feature is: [#29594] [#29594]: https://github.com/rust-lang/rust/issues/29594 @@ -11202,6 +14662,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thread_raw", description: r##"# `thread_raw` + + The tracking issue for this feature is: [#97523] [#97523]: https://github.com/rust-lang/rust/issues/97523 @@ -11216,6 +14678,8 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thread_sleep_until", description: r##"# `thread_sleep_until` + + The tracking issue for this feature is: [#113752] [#113752]: https://github.com/rust-lang/rust/issues/113752 @@ -11230,10 +14694,60 @@ fn bench_xor_1000_ints(b: &mut Bencher) { label: "thread_spawn_hook", description: r##"# `thread_spawn_hook` + + The tracking issue for this feature is: [#132951] [#132951]: https://github.com/rust-lang/rust/issues/132951 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "time_saturating_systemtime", + description: r##"# `time_saturating_systemtime` + + + +The tracking issue for this feature is: [#151199] + +[#151199]: https://github.com/rust-lang/rust/issues/151199 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "time_systemtime_limits", + description: r##"# `time_systemtime_limits` + + + +The tracking issue for this feature is: [#149067] + +[#149067]: https://github.com/rust-lang/rust/issues/149067 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "titlecase", + description: r##"# `titlecase` + + + +The tracking issue for this feature is: [#153892] + +[#153892]: https://github.com/rust-lang/rust/issues/153892 + ------------------------ "##, default_severity: Severity::Allow, @@ -11281,20 +14795,6 @@ fn main() { Finished dev [unoptimized + debuginfo] target(s) in 0.60 secs ``` -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "track_path", - description: r##"# `track_path` - -The tracking issue for this feature is: [#99515] - -[#99515]: https://github.com/rust-lang/rust/issues/99515 - ------------------------- "##, default_severity: Severity::Allow, warn_since: None, @@ -11336,39 +14836,6 @@ pub fn main() { println!("{:?}", b); } ``` -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "trait_upcasting", - description: r##"# `trait_upcasting` - -The tracking issue for this feature is: [#65991] - -[#65991]: https://github.com/rust-lang/rust/issues/65991 - ------------------------- - -The `trait_upcasting` feature adds support for trait upcasting coercion. This allows a -trait object of type `dyn Bar` to be cast to a trait object of type `dyn Foo` -so long as `Bar: Foo`. - -```rust,edition2018 -#![feature(trait_upcasting)] - -trait Foo {} - -trait Bar: Foo {} - -impl Foo for i32 {} - -impl Bar for T {} - -let bar: &dyn Bar = &123; -let foo: &dyn Foo = bar; -``` "##, default_severity: Severity::Allow, warn_since: None, @@ -11378,6 +14845,8 @@ impl Bar for T {} label: "transmutability", description: r##"# `transmutability` + + The tracking issue for this feature is: [#99571] [#99571]: https://github.com/rust-lang/rust/issues/99571 @@ -11392,6 +14861,8 @@ impl Bar for T {} label: "transmute_generic_consts", description: r##"# `transmute_generic_consts` +Allows for transmuting between arrays with sizes that contain generic consts. + The tracking issue for this feature is: [#109929] [#109929]: https://github.com/rust-lang/rust/issues/109929 @@ -11487,6 +14958,22 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. it is transparent). The Rust compiler is free to perform this optimization if possible, but is not required to, and different compiler versions may differ in their application of these optimizations. +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "trim_prefix_suffix", + description: r##"# `trim_prefix_suffix` + + + +The tracking issue for this feature is: [#142312] + +[#142312]: https://github.com/rust-lang/rust/issues/142312 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -11496,10 +14983,26 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trivial_bounds", description: r##"# `trivial_bounds` +Allows inconsistent bounds in where clauses. + The tracking issue for this feature is: [#48214] [#48214]: https://github.com/rust-lang/rust/issues/48214 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "trivial_clone", + description: r##"# `trivial_clone` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -11510,6 +15013,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trusted_fused", description: r##"# `trusted_fused` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11522,6 +15027,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trusted_len", description: r##"# `trusted_len` + + The tracking issue for this feature is: [#37572] [#37572]: https://github.com/rust-lang/rust/issues/37572 @@ -11536,6 +15043,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trusted_len_next_unchecked", description: r##"# `trusted_len_next_unchecked` + + The tracking issue for this feature is: [#37572] [#37572]: https://github.com/rust-lang/rust/issues/37572 @@ -11550,6 +15059,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trusted_random_access", description: r##"# `trusted_random_access` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11562,10 +15073,28 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "trusted_step", description: r##"# `trusted_step` + + The tracking issue for this feature is: [#85731] [#85731]: https://github.com/rust-lang/rust/issues/85731 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "try_as_dyn", + description: r##"# `try_as_dyn` + + + +The tracking issue for this feature is: [#144361] + +[#144361]: https://github.com/rust-lang/rust/issues/144361 + ------------------------ "##, default_severity: Severity::Allow, @@ -11604,6 +15133,22 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. }; assert!(result.is_err()); ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "try_blocks_heterogeneous", + description: r##"# `try_blocks_heterogeneous` + +Allows using `try bikeshed TargetType {...}` expressions. + +The tracking issue for this feature is: [#149488] + +[#149488]: https://github.com/rust-lang/rust/issues/149488 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -11613,6 +15158,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_find", description: r##"# `try_find` + + The tracking issue for this feature is: [#63178] [#63178]: https://github.com/rust-lang/rust/issues/63178 @@ -11627,6 +15174,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_reserve_kind", description: r##"# `try_reserve_kind` + + The tracking issue for this feature is: [#48043] [#48043]: https://github.com/rust-lang/rust/issues/48043 @@ -11641,6 +15190,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_trait_v2", description: r##"# `try_trait_v2` + + The tracking issue for this feature is: [#84277] [#84277]: https://github.com/rust-lang/rust/issues/84277 @@ -11655,6 +15206,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_trait_v2_residual", description: r##"# `try_trait_v2_residual` + + The tracking issue for this feature is: [#91285] [#91285]: https://github.com/rust-lang/rust/issues/91285 @@ -11669,6 +15222,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_trait_v2_yeet", description: r##"# `try_trait_v2_yeet` + + The tracking issue for this feature is: [#96374] [#96374]: https://github.com/rust-lang/rust/issues/96374 @@ -11683,6 +15238,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "try_with_capacity", description: r##"# `try_with_capacity` + + The tracking issue for this feature is: [#91913] [#91913]: https://github.com/rust-lang/rust/issues/91913 @@ -11697,6 +15254,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "tuple_trait", description: r##"# `tuple_trait` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11711,9 +15270,161 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. The tracking issue for this feature is: [#63063] -[#63063]: https://github.com/rust-lang/rust/issues/63063 - ------------------------ + +> This feature is not to be confused with [`trait_alias`] or [`impl_trait_in_assoc_type`]. + +### What is `impl Trait`? + +`impl Trait` in return position is useful for declaring types that are constrained by traits, but whose concrete type should be hidden: + +```rust +use std::fmt::Debug; + +fn new() -> impl Debug { + 42 +} + +fn main() { + let thing = new(); + // What actually is a `thing`? + // No idea but we know it implements `Debug`, so we can debug print it + println!("{thing:?}"); +} +``` + +See the [reference] for more information about `impl Trait` in return position. + +### `type_alias_impl_trait` + +However, we might want to use an `impl Trait` in multiple locations but actually use the same concrete type everywhere while keeping it hidden. +This can be useful in libraries where you want to hide implementation details. + +The `#[define_opaque]` attribute must be used to explicitly list opaque items constrained by the item it's on. + +```rust +#![feature(type_alias_impl_trait)] +# #![allow(unused_variables, dead_code)] +trait Trait {} + +struct MyType; + +impl Trait for MyType {} + +type Alias = impl Trait; + +#[define_opaque(Alias)] // To constrain the type alias to `MyType` +fn new() -> Alias { + MyType +} + +#[define_opaque(Alias)] // So we can name the concrete type inside this item +fn main() { + let thing: MyType = new(); +} + +// It can be a part of a struct too +struct HaveAlias { + stuff: String, + thing: Alias, +} +``` + +In this example, the concrete type referred to by `Alias` is guaranteed to be the same wherever `Alias` occurs. + +> Originally this feature included type aliases as an associated type of a trait. In [#110237] this was split off to [`impl_trait_in_assoc_type`]. + +### `type_alias_impl_trait` in argument position. + +Note that using `Alias` as an argument type is *not* the same as argument-position `impl Trait`, as `Alias` refers to a unique type, whereas the concrete type for argument-position `impl Trait` is chosen by the caller. + +```rust +# #![feature(type_alias_impl_trait)] +# #![allow(unused_variables)] +# pub mod x { +# pub trait Trait {} +# +# struct MyType; +# +# impl Trait for MyType {} +# +# pub type Alias = impl Trait; +# +# #[define_opaque(Alias)] +# pub fn new() -> Alias { +# MyType +# } +# } +# use x::*; +// this... +pub fn take_alias(x: Alias) { + // ... +} + +// ...is *not* the same as +pub fn take_impl(x: impl Trait) { + // ... +} +# fn main(){} +``` + +```rust,compile_fail,E0308 +# #![feature(type_alias_impl_trait)] +# #![allow(unused_variables)] +# pub mod x { +# pub trait Trait {} +# +# struct MyType; +# +# impl Trait for MyType {} +# +# pub type Alias = impl Trait; +# +# #[define_opaque(Alias)] +# pub fn new() -> Alias { +# MyType +# } +# } +# use x::*; +# pub fn take_alias(x: Alias) { +# // ... +# } +# +# pub fn take_impl(x: impl Trait) { +# // ... +# } +# +// a user's crate using the trait and type alias +struct UserType; +impl Trait for UserType {} + +# fn main(){ +let x = UserType; +take_alias(x); +// ERROR expected opaque type, found `UserType` +// this function *actually* takes a `MyType` as is constrained in `new` + +let x = UserType; +take_impl(x); +// OK + +let x = new(); +take_alias(x); +// OK + +let x = new(); +take_impl(x); +// OK +# } +``` + +Note that the user cannot use `#[define_opaque(Alias)]` to reify the opaque type because only the crate where the type alias is declared may do so. But if this happened in the same crate and the opaque type was reified, they'd get a familiar error: "expected `MyType`, got `UserType`". + +[#63063]: https://github.com/rust-lang/rust/issues/63063 +[#110237]: https://github.com/rust-lang/rust/pull/110237 +[reference]: https://doc.rust-lang.org/stable/reference/types/impl-trait.html#abstract-return-types +[`trait_alias`]: ./trait-alias.md +[`impl_trait_in_assoc_type`]: ./impl-trait-in-assoc-type.md "##, default_severity: Severity::Allow, warn_since: None, @@ -11723,6 +15434,8 @@ pub union GenericUnion { // Unions with non-`Copy` fields are unstable. label: "type_ascription", description: r##"# `type_ascription` + + The tracking issue for this feature is: [#23416] [#23416]: https://github.com/rust-lang/rust/issues/23416 @@ -11768,6 +15481,22 @@ struct Foo { }; } ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "type_info", + description: r##"# `type_info` + + + +The tracking issue for this feature is: [#146922] + +[#146922]: https://github.com/rust-lang/rust/issues/146922 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -11777,6 +15506,8 @@ struct Foo { label: "ub_checks", description: r##"# `ub_checks` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11789,6 +15520,8 @@ struct Foo { label: "uefi_std", description: r##"# `uefi_std` + + The tracking issue for this feature is: [#100499] [#100499]: https://github.com/rust-lang/rust/issues/100499 @@ -11800,12 +15533,46 @@ struct Foo { deny_since: None, }, Lint { - label: "unbounded_shifts", - description: r##"# `unbounded_shifts` + label: "uint_bit_width", + description: r##"# `uint_bit_width` -The tracking issue for this feature is: [#129375] -[#129375]: https://github.com/rust-lang/rust/issues/129375 + +The tracking issue for this feature is: [#142326] + +[#142326]: https://github.com/rust-lang/rust/issues/142326 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "uint_carryless_mul", + description: r##"# `uint_carryless_mul` + + + +The tracking issue for this feature is: [#152080] + +[#152080]: https://github.com/rust-lang/rust/issues/152080 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "uint_gather_scatter_bits", + description: r##"# `uint_gather_scatter_bits` + + + +The tracking issue for this feature is: [#149069] + +[#149069]: https://github.com/rust-lang/rust/issues/149069 ------------------------ "##, @@ -11849,6 +15616,8 @@ fn main() {} label: "unicode_internals", description: r##"# `unicode_internals` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -11861,6 +15630,8 @@ fn main() {} label: "unique_rc_arc", description: r##"# `unique_rc_arc` + + The tracking issue for this feature is: [#112566] [#112566]: https://github.com/rust-lang/rust/issues/112566 @@ -11875,10 +15646,44 @@ fn main() {} label: "unix_file_vectored_at", description: r##"# `unix_file_vectored_at` + + The tracking issue for this feature is: [#89517] [#89517]: https://github.com/rust-lang/rust/issues/89517 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unix_mkfifo", + description: r##"# `unix_mkfifo` + + + +The tracking issue for this feature is: [#139324] + +[#139324]: https://github.com/rust-lang/rust/issues/139324 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unix_send_signal", + description: r##"# `unix_send_signal` + + + +The tracking issue for this feature is: [#141975] + +[#141975]: https://github.com/rust-lang/rust/issues/141975 + ------------------------ "##, default_severity: Severity::Allow, @@ -11889,6 +15694,8 @@ fn main() {} label: "unix_set_mark", description: r##"# `unix_set_mark` + + The tracking issue for this feature is: [#96467] [#96467]: https://github.com/rust-lang/rust/issues/96467 @@ -11903,10 +15710,28 @@ fn main() {} label: "unix_socket_ancillary_data", description: r##"# `unix_socket_ancillary_data` + + The tracking issue for this feature is: [#76915] [#76915]: https://github.com/rust-lang/rust/issues/76915 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unix_socket_exclbind", + description: r##"# `unix_socket_exclbind` + + + +The tracking issue for this feature is: [#123481] + +[#123481]: https://github.com/rust-lang/rust/issues/123481 + ------------------------ "##, default_severity: Severity::Allow, @@ -11917,6 +15742,8 @@ fn main() {} label: "unix_socket_peek", description: r##"# `unix_socket_peek` + + The tracking issue for this feature is: [#76923] [#76923]: https://github.com/rust-lang/rust/issues/76923 @@ -11931,7 +15758,43 @@ fn main() {} label: "unqualified_local_imports", description: r##"# `unqualified_local_imports` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. +Helps with formatting for `group_imports = "StdExternalCrate"`. + +The tracking issue for this feature is: [#138299] + +[#138299]: https://github.com/rust-lang/rust/issues/138299 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unsafe_binders", + description: r##"# `unsafe_binders` + +Allows using `unsafe<'a> &'a T` unsafe binder types. + +The tracking issue for this feature is: [#130516] + +[#130516]: https://github.com/rust-lang/rust/issues/130516 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "unsafe_cell_access", + description: r##"# `unsafe_cell_access` + + + +The tracking issue for this feature is: [#136327] + +[#136327]: https://github.com/rust-lang/rust/issues/136327 ------------------------ "##, @@ -11943,6 +15806,8 @@ fn main() {} label: "unsafe_fields", description: r##"# `unsafe_fields` +Allows declaring fields `unsafe`. + The tracking issue for this feature is: [#132922] [#132922]: https://github.com/rust-lang/rust/issues/132922 @@ -11954,10 +15819,14 @@ fn main() {} deny_since: None, }, Lint { - label: "unsafe_pin_internals", - description: r##"# `unsafe_pin_internals` + label: "unsafe_pinned", + description: r##"# `unsafe_pinned` -This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + + +The tracking issue for this feature is: [#125735] + +[#125735]: https://github.com/rust-lang/rust/issues/125735 ------------------------ "##, @@ -11966,40 +15835,14 @@ fn main() {} deny_since: None, }, Lint { - label: "unsigned_is_multiple_of", - description: r##"# `unsigned_is_multiple_of` + label: "unsafe_unpin", + description: r##"# `unsafe_unpin` -The tracking issue for this feature is: [#128101] -[#128101]: https://github.com/rust-lang/rust/issues/128101 ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "unsigned_nonzero_div_ceil", - description: r##"# `unsigned_nonzero_div_ceil` +The tracking issue for this feature is: [#125735] -The tracking issue for this feature is: [#132968] - -[#132968]: https://github.com/rust-lang/rust/issues/132968 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "unsigned_signed_diff", - description: r##"# `unsigned_signed_diff` - -The tracking issue for this feature is: [#126041] - -[#126041]: https://github.com/rust-lang/rust/issues/126041 +[#125735]: https://github.com/rust-lang/rust/issues/125735 ------------------------ "##, @@ -12011,6 +15854,8 @@ fn main() {} label: "unsize", description: r##"# `unsize` + + The tracking issue for this feature is: [#18598] [#18598]: https://github.com/rust-lang/rust/issues/18598 @@ -12025,6 +15870,8 @@ fn main() {} label: "unsized_const_params", description: r##"# `unsized_const_params` +Allows const generic parameters to be defined with types that are not `Sized`, e.g. `fn foo() {`. + The tracking issue for this feature is: [#95174] [#95174]: https://github.com/rust-lang/rust/issues/95174 @@ -12039,193 +15886,13 @@ fn main() {} label: "unsized_fn_params", description: r##"# `unsized_fn_params` -The tracking issue for this feature is: [#48055] - -[#48055]: https://github.com/rust-lang/rust/issues/48055 - ------------------------- -"##, - default_severity: Severity::Allow, - warn_since: None, - deny_since: None, - }, - Lint { - label: "unsized_locals", - description: r##"# `unsized_locals` +Allows unsized fn parameters. The tracking issue for this feature is: [#48055] [#48055]: https://github.com/rust-lang/rust/issues/48055 ------------------------ - -This implements [RFC1909]. When turned on, you can have unsized arguments and locals: - -[RFC1909]: https://github.com/rust-lang/rfcs/blob/master/text/1909-unsized-rvalues.md - -```rust -#![allow(incomplete_features)] -#![feature(unsized_locals, unsized_fn_params)] - -use std::any::Any; - -fn main() { - let x: Box = Box::new(42); - let x: dyn Any = *x; - // ^ unsized local variable - // ^^ unsized temporary - foo(x); -} - -fn foo(_: dyn Any) {} -// ^^^^^^ unsized argument -``` - -The RFC still forbids the following unsized expressions: - -```rust,compile_fail -#![feature(unsized_locals)] - -use std::any::Any; - -struct MyStruct { - content: T, -} - -struct MyTupleStruct(T); - -fn answer() -> Box { - Box::new(42) -} - -fn main() { - // You CANNOT have unsized statics. - static X: dyn Any = *answer(); // ERROR - const Y: dyn Any = *answer(); // ERROR - - // You CANNOT have struct initialized unsized. - MyStruct { content: *answer() }; // ERROR - MyTupleStruct(*answer()); // ERROR - (42, *answer()); // ERROR - - // You CANNOT have unsized return types. - fn my_function() -> dyn Any { *answer() } // ERROR - - // You CAN have unsized local variables... - let mut x: dyn Any = *answer(); // OK - // ...but you CANNOT reassign to them. - x = *answer(); // ERROR - - // You CANNOT even initialize them separately. - let y: dyn Any; // OK - y = *answer(); // ERROR - - // Not mentioned in the RFC, but by-move captured variables are also Sized. - let x: dyn Any = *answer(); - (move || { // ERROR - let y = x; - })(); - - // You CAN create a closure with unsized arguments, - // but you CANNOT call it. - // This is an implementation detail and may be changed in the future. - let f = |x: dyn Any| {}; - f(*answer()); // ERROR -} -``` - -## By-value trait objects - -With this feature, you can have by-value `self` arguments without `Self: Sized` bounds. - -```rust -#![feature(unsized_fn_params)] - -trait Foo { - fn foo(self) {} -} - -impl Foo for T {} - -fn main() { - let slice: Box<[i32]> = Box::new([1, 2, 3]); - <[i32] as Foo>::foo(*slice); -} -``` - -And `Foo` will also be object-safe. - -```rust -#![feature(unsized_fn_params)] - -trait Foo { - fn foo(self) {} -} - -impl Foo for T {} - -fn main () { - let slice: Box = Box::new([1, 2, 3]); - // doesn't compile yet - ::foo(*slice); -} -``` - -One of the objectives of this feature is to allow `Box`. - -## Variable length arrays - -The RFC also describes an extension to the array literal syntax: `[e; dyn n]`. In the syntax, `n` isn't necessarily a constant expression. The array is dynamically allocated on the stack and has the type of `[T]`, instead of `[T; n]`. - -```rust,ignore (not-yet-implemented) -#![feature(unsized_locals)] - -fn mergesort(a: &mut [T]) { - let mut tmp = [T; dyn a.len()]; - // ... -} - -fn main() { - let mut a = [3, 1, 5, 6]; - mergesort(&mut a); - assert_eq!(a, [1, 3, 5, 6]); -} -``` - -VLAs are not implemented yet. The syntax isn't final, either. We may need an alternative syntax for Rust 2015 because, in Rust 2015, expressions like `[e; dyn(1)]` would be ambiguous. One possible alternative proposed in the RFC is `[e; n]`: if `n` captures one or more local variables, then it is considered as `[e; dyn n]`. - -## Advisory on stack usage - -It's advised not to casually use the `#![feature(unsized_locals)]` feature. Typical use-cases are: - -- When you need a by-value trait objects. -- When you really need a fast allocation of small temporary arrays. - -Another pitfall is repetitive allocation and temporaries. Currently the compiler simply extends the stack frame every time it encounters an unsized assignment. So for example, the code - -```rust -#![feature(unsized_locals)] - -fn main() { - let x: Box<[i32]> = Box::new([1, 2, 3, 4, 5]); - let _x = {{{{{{{{{{*x}}}}}}}}}}; -} -``` - -and the code - -```rust -#![feature(unsized_locals)] - -fn main() { - for _ in 0..10 { - let x: Box<[i32]> = Box::new([1, 2, 3, 4, 5]); - let _x = *x; - } -} -``` - -will unnecessarily extend the stack frame. "##, default_severity: Severity::Allow, warn_since: None, @@ -12235,6 +15902,8 @@ fn main() { label: "unwrap_infallible", description: r##"# `unwrap_infallible` + + The tracking issue for this feature is: [#61695] [#61695]: https://github.com/rust-lang/rust/issues/61695 @@ -12261,6 +15930,8 @@ fn main() { label: "used_with_arg", description: r##"# `used_with_arg` +Allows using the `#[used(linker)]` (or `#[used(compiler)]`) attribute. + The tracking issue for this feature is: [#93798] [#93798]: https://github.com/rust-lang/rust/issues/93798 @@ -12275,6 +15946,8 @@ fn main() { label: "utf16_extra", description: r##"# `utf16_extra` + + The tracking issue for this feature is: [#94919] [#94919]: https://github.com/rust-lang/rust/issues/94919 @@ -12289,10 +15962,28 @@ fn main() { label: "variant_count", description: r##"# `variant_count` + + The tracking issue for this feature is: [#73662] [#73662]: https://github.com/rust-lang/rust/issues/73662 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_deque_extract_if", + description: r##"# `vec_deque_extract_if` + + + +The tracking issue for this feature is: [#147750] + +[#147750]: https://github.com/rust-lang/rust/issues/147750 + ------------------------ "##, default_severity: Severity::Allow, @@ -12303,6 +15994,8 @@ fn main() { label: "vec_deque_iter_as_slices", description: r##"# `vec_deque_iter_as_slices` + + The tracking issue for this feature is: [#123947] [#123947]: https://github.com/rust-lang/rust/issues/123947 @@ -12314,12 +16007,14 @@ fn main() { deny_since: None, }, Lint { - label: "vec_into_raw_parts", - description: r##"# `vec_into_raw_parts` + label: "vec_deque_truncate_front", + description: r##"# `vec_deque_truncate_front` -The tracking issue for this feature is: [#65816] -[#65816]: https://github.com/rust-lang/rust/issues/65816 + +The tracking issue for this feature is: [#140667] + +[#140667]: https://github.com/rust-lang/rust/issues/140667 ------------------------ "##, @@ -12328,12 +16023,62 @@ fn main() { deny_since: None, }, Lint { - label: "vec_pop_if", - description: r##"# `vec_pop_if` + label: "vec_fallible_shrink", + description: r##"# `vec_fallible_shrink` -The tracking issue for this feature is: [#122741] -[#122741]: https://github.com/rust-lang/rust/issues/122741 + +The tracking issue for this feature is: [#152350] + +[#152350]: https://github.com/rust-lang/rust/issues/152350 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_from_fn", + description: r##"# `vec_from_fn` + + + +The tracking issue for this feature is: [#149698] + +[#149698]: https://github.com/rust-lang/rust/issues/149698 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_into_chunks", + description: r##"# `vec_into_chunks` + + + +The tracking issue for this feature is: [#142137] + +[#142137]: https://github.com/rust-lang/rust/issues/142137 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_peek_mut", + description: r##"# `vec_peek_mut` + + + +The tracking issue for this feature is: [#122742] + +[#122742]: https://github.com/rust-lang/rust/issues/122742 ------------------------ "##, @@ -12345,10 +16090,28 @@ fn main() { label: "vec_push_within_capacity", description: r##"# `vec_push_within_capacity` + + The tracking issue for this feature is: [#100486] [#100486]: https://github.com/rust-lang/rust/issues/100486 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_recycle", + description: r##"# `vec_recycle` + + + +The tracking issue for this feature is: [#148227] + +[#148227]: https://github.com/rust-lang/rust/issues/148227 + ------------------------ "##, default_severity: Severity::Allow, @@ -12359,10 +16122,60 @@ fn main() { label: "vec_split_at_spare", description: r##"# `vec_split_at_spare` + + The tracking issue for this feature is: [#81944] [#81944]: https://github.com/rust-lang/rust/issues/81944 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "vec_try_remove", + description: r##"# `vec_try_remove` + + + +The tracking issue for this feature is: [#146954] + +[#146954]: https://github.com/rust-lang/rust/issues/146954 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "waker_fn", + description: r##"# `waker_fn` + + + +The tracking issue for this feature is: [#149580] + +[#149580]: https://github.com/rust-lang/rust/issues/149580 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "waker_from_fn_ptr", + description: r##"# `waker_from_fn_ptr` + + + +The tracking issue for this feature is: [#148457] + +[#148457]: https://github.com/rust-lang/rust/issues/148457 + ------------------------ "##, default_severity: Severity::Allow, @@ -12373,6 +16186,8 @@ fn main() { label: "wasi_ext", description: r##"# `wasi_ext` + + The tracking issue for this feature is: [#71213] [#71213]: https://github.com/rust-lang/rust/issues/71213 @@ -12387,9 +16202,43 @@ fn main() { label: "wasm_target_feature", description: r##"# `wasm_target_feature` -The tracking issue for this feature is: [#44839] +Target features on wasm. -[#44839]: https://github.com/rust-lang/rust/issues/44839 +The tracking issue for this feature is: [#150260] + +[#150260]: https://github.com/rust-lang/rust/issues/150260 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "where_clause_attrs", + description: r##"# `where_clause_attrs` + +Allows use of attributes in `where` clauses. + +The tracking issue for this feature is: [#115590] + +[#115590]: https://github.com/rust-lang/rust/issues/115590 + +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "widening_mul", + description: r##"# `widening_mul` + + + +The tracking issue for this feature is: [#152016] + +[#152016]: https://github.com/rust-lang/rust/issues/152016 ------------------------ "##, @@ -12401,6 +16250,8 @@ fn main() { label: "windows_by_handle", description: r##"# `windows_by_handle` + + The tracking issue for this feature is: [#63010] [#63010]: https://github.com/rust-lang/rust/issues/63010 @@ -12427,10 +16278,28 @@ fn main() { label: "windows_change_time", description: r##"# `windows_change_time` + + The tracking issue for this feature is: [#121478] [#121478]: https://github.com/rust-lang/rust/issues/121478 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "windows_freeze_file_times", + description: r##"# `windows_freeze_file_times` + + + +The tracking issue for this feature is: [#149715] + +[#149715]: https://github.com/rust-lang/rust/issues/149715 + ------------------------ "##, default_severity: Severity::Allow, @@ -12465,6 +16334,8 @@ fn main() { label: "windows_process_exit_code_from", description: r##"# `windows_process_exit_code_from` + + The tracking issue for this feature is: [#111688] [#111688]: https://github.com/rust-lang/rust/issues/111688 @@ -12479,6 +16350,8 @@ fn main() { label: "windows_process_extensions_async_pipes", description: r##"# `windows_process_extensions_async_pipes` + + The tracking issue for this feature is: [#98289] [#98289]: https://github.com/rust-lang/rust/issues/98289 @@ -12493,10 +16366,28 @@ fn main() { label: "windows_process_extensions_force_quotes", description: r##"# `windows_process_extensions_force_quotes` + + The tracking issue for this feature is: [#82227] [#82227]: https://github.com/rust-lang/rust/issues/82227 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "windows_process_extensions_inherit_handles", + description: r##"# `windows_process_extensions_inherit_handles` + + + +The tracking issue for this feature is: [#146407] + +[#146407]: https://github.com/rust-lang/rust/issues/146407 + ------------------------ "##, default_severity: Severity::Allow, @@ -12507,6 +16398,8 @@ fn main() { label: "windows_process_extensions_main_thread_handle", description: r##"# `windows_process_extensions_main_thread_handle` + + The tracking issue for this feature is: [#96723] [#96723]: https://github.com/rust-lang/rust/issues/96723 @@ -12521,6 +16414,8 @@ fn main() { label: "windows_process_extensions_raw_attribute", description: r##"# `windows_process_extensions_raw_attribute` + + The tracking issue for this feature is: [#114854] [#114854]: https://github.com/rust-lang/rust/issues/114854 @@ -12535,10 +16430,28 @@ fn main() { label: "windows_process_extensions_show_window", description: r##"# `windows_process_extensions_show_window` + + The tracking issue for this feature is: [#127544] [#127544]: https://github.com/rust-lang/rust/issues/127544 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "windows_process_extensions_startupinfo", + description: r##"# `windows_process_extensions_startupinfo` + + + +The tracking issue for this feature is: [#141010] + +[#141010]: https://github.com/rust-lang/rust/issues/141010 + ------------------------ "##, default_severity: Severity::Allow, @@ -12551,6 +16464,22 @@ fn main() { This feature is internal to the Rust compiler and is not intended for general use. +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "windows_unix_domain_sockets", + description: r##"# `windows_unix_domain_sockets` + + + +The tracking issue for this feature is: [#150487] + +[#150487]: https://github.com/rust-lang/rust/issues/150487 + ------------------------ "##, default_severity: Severity::Allow, @@ -12561,6 +16490,8 @@ fn main() { label: "with_negative_coherence", description: r##"# `with_negative_coherence` +Use for stable + negative coherence and strict coherence depending on trait's rustc_strict_coherence value. + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -12573,6 +16504,8 @@ fn main() { label: "wrapping_int_impl", description: r##"# `wrapping_int_impl` + + The tracking issue for this feature is: [#32463] [#32463]: https://github.com/rust-lang/rust/issues/32463 @@ -12587,6 +16520,8 @@ fn main() { label: "wrapping_next_power_of_two", description: r##"# `wrapping_next_power_of_two` + + The tracking issue for this feature is: [#32463] [#32463]: https://github.com/rust-lang/rust/issues/32463 @@ -12601,10 +16536,26 @@ fn main() { label: "write_all_vectored", description: r##"# `write_all_vectored` + + The tracking issue for this feature is: [#70436] [#70436]: https://github.com/rust-lang/rust/issues/70436 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "wtf8_internals", + description: r##"# `wtf8_internals` + + + +This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. + ------------------------ "##, default_severity: Severity::Allow, @@ -12615,10 +16566,28 @@ fn main() { label: "x86_amx_intrinsics", description: r##"# `x86_amx_intrinsics` +Allows use of x86 `AMX` target-feature attributes and intrinsics + The tracking issue for this feature is: [#126622] [#126622]: https://github.com/rust-lang/rust/issues/126622 +------------------------ +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "x87_target_feature", + description: r##"# `x87_target_feature` + +The x87 target feature on x86. + +The tracking issue for this feature is: [#150261] + +[#150261]: https://github.com/rust-lang/rust/issues/150261 + ------------------------ "##, default_severity: Severity::Allow, @@ -12629,6 +16598,8 @@ fn main() { label: "xop_target_feature", description: r##"# `xop_target_feature` +Allows use of the `xop` target-feature + The tracking issue for this feature is: [#127208] [#127208]: https://github.com/rust-lang/rust/issues/127208 @@ -12643,6 +16614,8 @@ fn main() { label: "yeet_desugar_details", description: r##"# `yeet_desugar_details` + + This feature has no tracking issue, and is therefore likely internal to the compiler, not being intended for general use. ------------------------ @@ -12679,6 +16652,22 @@ fn bar() -> Option { } assert_eq!(bar(), None); ``` +"##, + default_severity: Severity::Allow, + warn_since: None, + deny_since: None, + }, + Lint { + label: "yield_expr", + description: r##"# `yield_expr` + + + +The tracking issue for this feature is: [#43122] + +[#43122]: https://github.com/rust-lang/rust/issues/43122 + +------------------------ "##, default_severity: Severity::Allow, warn_since: None, @@ -14967,7 +18956,7 @@ fn bar() -> Option { }, Lint { label: "clippy::manual_bits", - description: r##"Checks for usage of `size_of::() * 8` when + description: r##"Checks for usage of `std::mem::size_of::() * 8` when `T::BITS` is available."##, default_severity: Severity::Allow, warn_since: None, @@ -17309,7 +21298,7 @@ fn bar() -> Option { }, Lint { label: "clippy::size_of_ref", - description: r##"Checks for calls to `size_of_val()` where the argument is + description: r##"Checks for calls to `std::mem::size_of_val()` where the argument is a reference to a reference."##, default_severity: Severity::Allow, warn_since: None, diff --git a/src/tools/rust-analyzer/crates/ide-db/src/imports/import_assets.rs b/src/tools/rust-analyzer/crates/ide-db/src/imports/import_assets.rs index 1c485270272e..9018552afb4d 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/imports/import_assets.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/imports/import_assets.rs @@ -8,8 +8,10 @@ SemanticsScope, Trait, Type, }; use itertools::Itertools; +use parser::SyntaxKind; use rustc_hash::{FxHashMap, FxHashSet}; use smallvec::{SmallVec, smallvec}; +use stdx::never; use syntax::{ AstNode, SyntaxNode, ast::{self, HasName, make}, @@ -61,6 +63,105 @@ pub struct TraitImportCandidate<'db> { pub assoc_item_name: NameToImport, } +#[derive(Debug)] +struct PathDefinitionKinds { + modules: bool, + bang_macros: bool, + // FIXME: Distinguish between attr and derive macros. + attr_macros: bool, + value_namespace: bool, + type_namespace: bool, + /// Unions, record structs and record enum variants. Note that unions and structs + /// can also be enabled by `type_namespace` (either works). + records: bool, + /// Tuple structs and tuple enum variants. Both are also controlled by `value_namespace` + /// (either works). Structs are also covered by `type_namespace`. + tuple_structs: bool, + /// Structs, enum variants and consts. + structs_and_consts: bool, +} + +impl PathDefinitionKinds { + const ALL_DISABLED: Self = Self { + modules: false, + bang_macros: false, + attr_macros: false, + value_namespace: false, + type_namespace: false, + records: false, + tuple_structs: false, + structs_and_consts: false, + }; + const ALL_ENABLED: Self = Self { + modules: true, + bang_macros: true, + attr_macros: true, + value_namespace: true, + type_namespace: true, + records: true, + tuple_structs: true, + structs_and_consts: true, + }; + // While a path pattern only allows unit structs/enum variants, parentheses/braces may be written later. + const PATH_PAT_KINDS: PathDefinitionKinds = + Self { structs_and_consts: true, bang_macros: true, ..Self::ALL_DISABLED }; + + fn deduce_from_path(path: &ast::Path, exact: bool) -> Self { + let Some(parent) = path.syntax().parent() else { + return Self::ALL_ENABLED; + }; + let mut result = match parent.kind() { + // When there are following segments, it can be a type (with a method) or a module. + // Technically, a type can only have up to 2 segments following (an associated type + // then a method), but most paths are shorter than 3 segments anyway, and we'll also + // validate that the following segment resolve. + SyntaxKind::PATH => Self { modules: true, type_namespace: true, ..Self::ALL_DISABLED }, + SyntaxKind::MACRO_CALL => Self { bang_macros: true, ..Self::ALL_DISABLED }, + SyntaxKind::PATH_META | SyntaxKind::KEY_VALUE_META | SyntaxKind::TOKEN_TREE_META => { + Self { attr_macros: true, ..Self::ALL_DISABLED } + } + SyntaxKind::USE_TREE => { + if ast::UseTree::cast(parent).unwrap().use_tree_list().is_some() { + Self { modules: true, ..Self::ALL_DISABLED } + } else { + Self::ALL_ENABLED + } + } + SyntaxKind::VISIBILITY => Self { modules: true, ..Self::ALL_DISABLED }, + SyntaxKind::ASM_SYM => Self { value_namespace: true, ..Self::ALL_DISABLED }, + // `bang_macros = true` because you can still type the `!`. + // `type_namespace = true` because you can type `::method()`. + SyntaxKind::PATH_EXPR => Self { + value_namespace: true, + bang_macros: true, + type_namespace: true, + ..Self::ALL_DISABLED + }, + SyntaxKind::PATH_PAT => Self::PATH_PAT_KINDS, + SyntaxKind::TUPLE_STRUCT_PAT => { + Self { tuple_structs: true, bang_macros: true, ..Self::ALL_DISABLED } + } + SyntaxKind::RECORD_EXPR | SyntaxKind::RECORD_PAT => { + Self { records: true, bang_macros: true, ..Self::ALL_DISABLED } + } + SyntaxKind::PATH_TYPE => { + Self { type_namespace: true, bang_macros: true, ..Self::ALL_DISABLED } + } + SyntaxKind::ERROR => Self::ALL_ENABLED, + _ => { + never!("this match should cover all possible parents of paths\nparent={parent:#?}"); + Self::ALL_ENABLED + } + }; + if !exact { + // When the path is not required to be exact, there could be additional segments to be filled. + result.modules = true; + result.type_namespace = true; + } + result + } +} + /// Path import for a given name, qualified or not. #[derive(Debug)] pub struct PathImportCandidate { @@ -70,6 +171,8 @@ pub struct PathImportCandidate { pub name: NameToImport, /// Potentially more segments that should resolve in the candidate. pub after: Vec, + /// The kind of definitions that we can include. + definition_kinds: PathDefinitionKinds, } /// A name that will be used during item lookups. @@ -168,13 +271,14 @@ pub fn for_ident_pat(sema: &Semantics<'db, RootDatabase>, pat: &ast::IdentPat) - pub fn for_fuzzy_path( module_with_candidate: Module, + path: Option<&ast::Path>, qualifier: Option, fuzzy_name: String, sema: &Semantics<'db, RootDatabase>, candidate_node: SyntaxNode, ) -> Option { Some(Self { - import_candidate: ImportCandidate::for_fuzzy_path(qualifier, fuzzy_name, sema)?, + import_candidate: ImportCandidate::for_fuzzy_path(path, qualifier, fuzzy_name, sema)?, module_with_candidate, candidate_node, }) @@ -394,6 +498,9 @@ fn path_applicable_imports( // see also an ignored test under FIXME comment in the qualify_path.rs module AssocSearchMode::Exclude, ) + .filter(|(item, _)| { + filter_by_definition_kind(db, *item, &path_candidate.definition_kinds) + }) .filter_map(|(item, do_not_complete)| { if !scope_filter(item) { return None; @@ -442,6 +549,46 @@ fn path_applicable_imports( result } +fn filter_by_definition_kind( + db: &RootDatabase, + item: ItemInNs, + allowed: &PathDefinitionKinds, +) -> bool { + let item = item.into_module_def(); + let struct_per_kind = |struct_kind| { + allowed.structs_and_consts + || match struct_kind { + hir::StructKind::Record => allowed.records, + hir::StructKind::Tuple => allowed.value_namespace || allowed.tuple_structs, + hir::StructKind::Unit => allowed.value_namespace, + } + }; + match item { + ModuleDef::Module(_) => allowed.modules, + ModuleDef::Function(_) => allowed.value_namespace, + ModuleDef::Adt(hir::Adt::Struct(item)) => { + allowed.type_namespace || struct_per_kind(item.kind(db)) + } + ModuleDef::Adt(hir::Adt::Enum(_)) => allowed.type_namespace, + ModuleDef::Adt(hir::Adt::Union(_)) => { + allowed.type_namespace || allowed.records || allowed.structs_and_consts + } + ModuleDef::EnumVariant(item) => struct_per_kind(item.kind(db)), + ModuleDef::Const(_) => allowed.value_namespace || allowed.structs_and_consts, + ModuleDef::Static(_) => allowed.value_namespace, + ModuleDef::Trait(_) => allowed.type_namespace, + ModuleDef::TypeAlias(_) => allowed.type_namespace, + ModuleDef::BuiltinType(_) => allowed.type_namespace, + ModuleDef::Macro(item) => { + if item.is_fn_like(db) { + allowed.bang_macros + } else { + allowed.attr_macros + } + } + } +} + fn filter_candidates_by_after_path( db: &RootDatabase, scope: &SemanticsScope<'_>, @@ -835,6 +982,7 @@ fn for_regular_path(sema: &Semantics<'db, RootDatabase>, path: &ast::Path) -> Op .collect::>()?; path_import_candidate( sema, + Some(path), path.qualifier(), NameToImport::exact_case_sensitive(path.segment()?.name_ref()?.to_string()), after, @@ -853,25 +1001,31 @@ fn for_name(sema: &Semantics<'db, RootDatabase>, name: &ast::Name) -> Option, qualifier: Option, fuzzy_name: String, sema: &Semantics<'db, RootDatabase>, ) -> Option { // Assume a fuzzy match does not want the segments after. Because... I guess why not? - path_import_candidate(sema, qualifier, NameToImport::fuzzy(fuzzy_name), Vec::new()) + path_import_candidate(sema, path, qualifier, NameToImport::fuzzy(fuzzy_name), Vec::new()) } } fn path_import_candidate<'db>( sema: &Semantics<'db, RootDatabase>, + path: Option<&ast::Path>, qualifier: Option, name: NameToImport, after: Vec, ) -> Option> { + let definition_kinds = path.map_or(PathDefinitionKinds::ALL_ENABLED, |path| { + PathDefinitionKinds::deduce_from_path(path, matches!(name, NameToImport::Exact(..))) + }); Some(match qualifier { Some(qualifier) => match sema.resolve_path(&qualifier) { Some(PathResolution::Def(ModuleDef::BuiltinType(_))) | None => { @@ -880,7 +1034,12 @@ fn path_import_candidate<'db>( .segments() .map(|seg| seg.name_ref().map(|name| Name::new_root(&name.text()))) .collect::>>()?; - ImportCandidate::Path(PathImportCandidate { qualifier, name, after }) + ImportCandidate::Path(PathImportCandidate { + qualifier, + name, + after, + definition_kinds, + }) } else { return None; } @@ -904,7 +1063,12 @@ fn path_import_candidate<'db>( } Some(_) => return None, }, - None => ImportCandidate::Path(PathImportCandidate { qualifier: vec![], name, after }), + None => ImportCandidate::Path(PathImportCandidate { + qualifier: vec![], + name, + after, + definition_kinds, + }), }) } diff --git a/src/tools/rust-analyzer/crates/ide-db/src/imports/insert_use.rs b/src/tools/rust-analyzer/crates/ide-db/src/imports/insert_use.rs index da8525d1fb72..9318c3e13272 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/imports/insert_use.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/imports/insert_use.rs @@ -101,14 +101,12 @@ pub fn find_insert_use_container( { block = b.stmt_list(); } - if has_attrs - .attrs() - .any(|attr| attr.as_simple_call().is_some_and(|(ident, _)| ident == "cfg")) + if has_attrs.attrs().any(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))) { if let Some(b) = block.clone() { - let current_cfgs = has_attrs.attrs().filter(|attr| { - attr.as_simple_call().is_some_and(|(ident, _)| ident == "cfg") - }); + let current_cfgs = has_attrs + .attrs() + .filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))); let total_cfgs: Vec<_> = required_cfgs.iter().cloned().chain(current_cfgs).collect(); @@ -118,7 +116,7 @@ pub fn find_insert_use_container( if let Some(parent) = parent { can_merge = parent.children().filter_map(ast::Use::cast).any(|u| { let u_attrs = u.attrs().filter(|attr| { - attr.as_simple_call().is_some_and(|(ident, _)| ident == "cfg") + matches!(attr.meta(), Some(ast::Meta::CfgMeta(_))) }); crate::imports::merge_imports::eq_attrs( u_attrs, @@ -134,9 +132,11 @@ pub fn find_insert_use_container( }); } } - required_cfgs.extend(has_attrs.attrs().filter(|attr| { - attr.as_simple_call().is_some_and(|(ident, _)| ident == "cfg") - })); + required_cfgs.extend( + has_attrs + .attrs() + .filter(|attr| matches!(attr.meta(), Some(ast::Meta::CfgMeta(_)))), + ); } } } @@ -305,10 +305,8 @@ fn insert_use_with_alias_option_with_editor( if mb == Some(MergeBehavior::One) && use_tree.path().is_some() { use_tree.wrap_in_tree_list(); } - let use_item = make::use_(None, None, use_tree).clone_for_update(); - for attr in - scope.required_cfgs.iter().map(|attr| attr.syntax().clone_subtree().clone_for_update()) - { + let use_item = make::use_(None, None, use_tree); + for attr in scope.required_cfgs.iter().map(|attr| attr.syntax().clone()) { syntax_editor.insert(Position::first_child_of(use_item.syntax()), attr); } @@ -711,7 +709,11 @@ fn insert_use_with_editor_( Some(b) => { cov_mark::hit!(insert_empty_module); syntax_editor.insert(Position::after(&b), syntax_factory.whitespace("\n")); - syntax_editor.insert(Position::after(&b), use_item.syntax()); + syntax_editor.insert_with_whitespace( + Position::after(&b), + use_item.syntax(), + syntax_factory, + ); } None => { cov_mark::hit!(insert_empty_file); diff --git a/src/tools/rust-analyzer/crates/ide-db/src/imports/merge_imports.rs b/src/tools/rust-analyzer/crates/ide-db/src/imports/merge_imports.rs index 3301719f5ce2..76645464ddf5 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/imports/merge_imports.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/imports/merge_imports.rs @@ -256,16 +256,6 @@ pub fn try_normalize_import(use_item: &ast::Use, style: NormalizationStyle) -> O Some(use_item) } -/// Normalizes a use tree (see [`try_normalize_import`] doc). -pub fn try_normalize_use_tree( - use_tree: &ast::UseTree, - style: NormalizationStyle, -) -> Option { - let use_tree = use_tree.clone_subtree().clone_for_update(); - try_normalize_use_tree_mut(&use_tree, style)?; - Some(use_tree) -} - pub fn try_normalize_use_tree_mut( use_tree: &ast::UseTree, style: NormalizationStyle, diff --git a/src/tools/rust-analyzer/crates/ide-db/src/lib.rs b/src/tools/rust-analyzer/crates/ide-db/src/lib.rs index cde0705d8ac2..8d16826e191d 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/lib.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/lib.rs @@ -60,8 +60,8 @@ pub mod syntax_helpers { use std::{fmt, mem::ManuallyDrop}; use base_db::{ - CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Files, Nonce, RootQueryDb, - SourceDatabase, SourceRoot, SourceRootId, SourceRootInput, query_group, + CrateGraphBuilder, CratesMap, FileSourceRootInput, FileText, Files, Nonce, SourceDatabase, + SourceRoot, SourceRootId, SourceRootInput, query_group, set_all_crates_with_durability, }; use hir::{ FilePositionWrapper, FileRangeWrapper, @@ -197,7 +197,7 @@ pub fn new(lru_capacity: Option) -> RootDatabase { nonce: Nonce::new(), }; // This needs to be here otherwise `CrateGraphBuilder` will panic. - db.set_all_crates(Arc::new(Box::new([]))); + set_all_crates_with_durability(&mut db, std::iter::empty(), Durability::HIGH); CrateGraphBuilder::default().set_in_db(&mut db); db.set_proc_macros_with_durability(Default::default(), Durability::MEDIUM); _ = base_db::LibraryRoots::builder(Default::default()) @@ -253,7 +253,7 @@ pub fn update_lru_capacities(&mut self, _lru_capacities: &FxHashMap, u1 } #[query_group::query_group] -pub trait LineIndexDatabase: base_db::RootQueryDb { +pub trait LineIndexDatabase: base_db::SourceDatabase { #[salsa::invoke_interned(line_index)] fn line_index(&self, file_id: FileId) -> Arc; } diff --git a/src/tools/rust-analyzer/crates/ide-db/src/path_transform.rs b/src/tools/rust-analyzer/crates/ide-db/src/path_transform.rs index 508f841340b1..407276a2defc 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/path_transform.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/path_transform.rs @@ -197,7 +197,7 @@ fn build_ctx(&self) -> Ctx<'a> { && let Some(default) = &default.display_source_code(db, source_module.into(), false).ok() { - type_substs.insert(k, make::ty(default).clone_for_update()); + type_substs.insert(k, make::ty(default)); defaulted_params.push(Either::Left(k)); } } @@ -222,7 +222,7 @@ fn build_ctx(&self) -> Ctx<'a> { k.default(db, target_module.krate(db).to_display_target(db)) && let Some(default) = default.expr() { - const_substs.insert(k, default.syntax().clone_for_update()); + const_substs.insert(k, default.syntax().clone()); defaulted_params.push(Either::Right(k)); } } @@ -278,12 +278,10 @@ fn apply(&self, item: &SyntaxNode) -> SyntaxNode { // `transform_path` may update a node's parent and that would break the // tree traversal. Thus all paths in the tree are collected into a vec // so that such operation is safe. - let item = self.transform_path(item).clone_subtree(); - let mut editor = SyntaxEditor::new(item.clone()); + let (mut editor, item) = SyntaxEditor::new(self.transform_path(item)); preorder_rev(&item).filter_map(ast::Lifetime::cast).for_each(|lifetime| { if let Some(subst) = self.lifetime_substs.get(&lifetime.syntax().text().to_string()) { - editor - .replace(lifetime.syntax(), subst.clone_subtree().clone_for_update().syntax()); + editor.replace(lifetime.syntax(), subst.clone().syntax()); } }); @@ -331,18 +329,14 @@ fn find_child_paths_and_ident_pats( result } - let root_path = path.clone_subtree(); - + let (mut editor, root_path) = SyntaxEditor::new(path.clone()); let result = find_child_paths_and_ident_pats(&root_path); - let mut editor = SyntaxEditor::new(root_path.clone()); for sub_path in result { let new = self.transform_path(sub_path.syntax()); editor.replace(sub_path.syntax(), new); } - - let update_sub_item = editor.finish().new_root().clone().clone_subtree(); + let (mut editor, update_sub_item) = SyntaxEditor::new(editor.finish().new_root().clone()); let item = find_child_paths_and_ident_pats(&update_sub_item); - let mut editor = SyntaxEditor::new(update_sub_item); for sub_path in item { self.transform_path_or_ident_pat(&mut editor, &sub_path); } @@ -411,33 +405,27 @@ fn transform_path_(&self, editor: &mut SyntaxEditor, path: &ast::Path) -> Option let segment = make::path_segment_ty(subst.clone(), trait_ref); let qualified = make::path_from_segments(std::iter::once(segment), false); - editor.replace(path.syntax(), qualified.clone_for_update().syntax()); + editor.replace(path.syntax(), qualified.clone().syntax()); } else if let Some(path_ty) = ast::PathType::cast(parent) { let old = path_ty.syntax(); if old.parent().is_some() { - editor.replace(old, subst.clone_subtree().clone_for_update().syntax()); + editor.replace(old, subst.clone().syntax()); } else { - // Some `path_ty` has no parent, especially ones made for default value - // of type parameters. - // In this case, `ted` cannot replace `path_ty` with `subst` directly. - // So, just replace its children as long as the `subst` is the same type. - let new = subst.clone_subtree().clone_for_update(); - if !matches!(new, ast::Type::PathType(..)) { - return None; - } let start = path_ty.syntax().first_child().map(NodeOrToken::Node)?; let end = path_ty.syntax().last_child().map(NodeOrToken::Node)?; editor.replace_all( start..=end, - new.syntax().children().map(NodeOrToken::Node).collect::>(), + subst + .clone() + .syntax() + .children() + .map(NodeOrToken::Node) + .collect::>(), ); } } else { - editor.replace( - path.syntax(), - subst.clone_subtree().clone_for_update().syntax(), - ); + editor.replace(path.syntax(), subst.clone().syntax()); } } } @@ -459,18 +447,17 @@ fn transform_path_(&self, editor: &mut SyntaxEditor, path: &ast::Path) -> Option allow_unstable: true, }; let found_path = self.target_module.find_path(self.source_scope.db, def, cfg)?; - let res = mod_path_to_ast(&found_path, self.target_edition).clone_for_update(); - let mut res_editor = SyntaxEditor::new(res.syntax().clone_subtree()); + let res = mod_path_to_ast(&found_path, self.target_edition); + let (mut res_editor, res) = SyntaxEditor::with_ast_node(&res); if let Some(args) = path.segment().and_then(|it| it.generic_arg_list()) && let Some(segment) = res.segment() { if let Some(old) = segment.generic_arg_list() { - res_editor - .replace(old.syntax(), args.clone_subtree().syntax().clone_for_update()) + res_editor.replace(old.syntax(), args.syntax().clone()) } else { res_editor.insert( syntax_editor::Position::last_child_of(segment.syntax()), - args.clone_subtree().syntax().clone_for_update(), + args.syntax().clone(), ); } } @@ -479,7 +466,7 @@ fn transform_path_(&self, editor: &mut SyntaxEditor, path: &ast::Path) -> Option } hir::PathResolution::ConstParam(cp) => { if let Some(subst) = self.const_substs.get(&cp) { - editor.replace(path.syntax(), subst.clone_subtree().clone_for_update()); + editor.replace(path.syntax(), subst.clone()); } } hir::PathResolution::SelfType(imp) => { @@ -496,7 +483,7 @@ fn transform_path_(&self, editor: &mut SyntaxEditor, path: &ast::Path) -> Option true, ) .ok()?; - let ast_ty = make::ty(ty_str).clone_for_update(); + let ast_ty = make::ty(ty_str); if let Some(adt) = ty.as_adt() && let ast::Type::PathType(path_ty) = &ast_ty @@ -516,8 +503,10 @@ fn transform_path_(&self, editor: &mut SyntaxEditor, path: &ast::Path) -> Option if let Some(qual) = mod_path_to_ast(&found_path, self.target_edition).qualifier() { - let res = make::path_concat(qual, path_ty.path()?).clone_for_update(); - editor.replace(path.syntax(), res.syntax()); + editor.replace( + path.syntax(), + make::path_concat(qual, path_ty.path()?).syntax(), + ); return Some(()); } } @@ -593,8 +582,10 @@ fn transform_ident_pat( allow_unstable: true, }; let found_path = self.target_module.find_path(self.source_scope.db, def, cfg)?; - let res = mod_path_to_ast(&found_path, self.target_edition).clone_for_update(); - editor.replace(ident_pat.syntax(), res.syntax()); + editor.replace( + ident_pat.syntax(), + mod_path_to_ast(&found_path, self.target_edition).syntax(), + ); Some(()) } _ => None, diff --git a/src/tools/rust-analyzer/crates/ide-db/src/prime_caches.rs b/src/tools/rust-analyzer/crates/ide-db/src/prime_caches.rs index d264428212cb..12a48d65ac8c 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/prime_caches.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/prime_caches.rs @@ -4,15 +4,12 @@ //! various caches, it's not really advanced at the moment. use std::panic::AssertUnwindSafe; +use base_db::all_crates; use hir::{Symbol, import_map::ImportMap}; use rustc_hash::FxHashMap; use salsa::{Cancelled, Database}; -use crate::{ - FxIndexMap, RootDatabase, - base_db::{Crate, RootQueryDb}, - symbol_index::SymbolIndex, -}; +use crate::{FxIndexMap, RootDatabase, base_db::Crate, symbol_index::SymbolIndex}; /// We're indexing many crates. #[derive(Debug)] @@ -56,7 +53,7 @@ enum ParallelPrimeCacheWorkerProgress { // to compute the symbols/import map of an already computed def map in that time. let (reverse_deps, mut to_be_done_deps) = { - let all_crates = db.all_crates(); + let all_crates = all_crates(db); let to_be_done_deps = all_crates .iter() .map(|&krate| (krate, krate.data(db).dependencies.len() as u32)) @@ -200,7 +197,7 @@ enum ParallelPrimeCacheWorkerProgress { ) }; - let crate_def_maps_total = db.all_crates().len(); + let crate_def_maps_total = all_crates(db).len(); let mut crate_def_maps_done = 0; let (mut crate_import_maps_total, mut crate_import_maps_done) = (0usize, 0usize); let (mut module_symbols_total, mut module_symbols_done) = (0usize, 0usize); diff --git a/src/tools/rust-analyzer/crates/ide-db/src/ra_fixture.rs b/src/tools/rust-analyzer/crates/ide-db/src/ra_fixture.rs index c9a670b2d1c0..2f4d319ec821 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/ra_fixture.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/ra_fixture.rs @@ -52,6 +52,18 @@ fn from_ra_fixture( } } +#[derive(Debug, Clone, Copy)] +pub struct RaFixtureConfig<'a> { + pub minicore: MiniCore<'a>, + pub disable_ra_fixture: bool, +} + +impl<'a> RaFixtureConfig<'a> { + pub const fn default() -> Self { + Self { minicore: MiniCore::default(), disable_ra_fixture: false } + } +} + pub struct RaFixtureAnalysis { pub db: RootDatabase, tmp_file_ids: Vec<(FileId, usize)>, @@ -69,9 +81,14 @@ pub fn analyze_ra_fixture( sema: &Semantics<'_, RootDatabase>, literal: ast::String, expanded: &ast::String, - minicore: MiniCore<'_>, + config: &RaFixtureConfig<'_>, on_cursor: &mut dyn FnMut(TextRange), ) -> Option { + if config.disable_ra_fixture { + return None; + } + let minicore = config.minicore; + if !literal.is_raw() { return None; } diff --git a/src/tools/rust-analyzer/crates/ide-db/src/search.rs b/src/tools/rust-analyzer/crates/ide-db/src/search.rs index 25acb47f7b4c..69459a4b72da 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/search.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/search.rs @@ -7,7 +7,7 @@ use std::mem; use std::{cell::LazyCell, cmp::Reverse}; -use base_db::{RootQueryDb, SourceDatabase}; +use base_db::{SourceDatabase, all_crates}; use either::Either; use hir::{ Adt, AsAssocItem, DefWithBody, EditionedFileId, ExpressionStoreOwner, FileRange, @@ -161,7 +161,7 @@ fn new(entries: FxHashMap>) -> SearchScope { fn crate_graph(db: &RootDatabase) -> SearchScope { let mut entries = FxHashMap::default(); - let all_crates = db.all_crates(); + let all_crates = all_crates(db); for &krate in all_crates.iter() { let crate_data = krate.data(db); let source_root = db.file_source_root(crate_data.root_file_id).source_root_id(db); diff --git a/src/tools/rust-analyzer/crates/ide-db/src/source_change.rs b/src/tools/rust-analyzer/crates/ide-db/src/source_change.rs index 57072bb5ba36..4a83f707fcac 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/source_change.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/source_change.rs @@ -282,7 +282,7 @@ pub fn edit_file(&mut self, file_id: impl Into) { } pub fn make_editor(&self, node: &SyntaxNode) -> SyntaxEditor { - SyntaxEditor::new(node.ancestors().last().unwrap_or_else(|| node.clone())) + SyntaxEditor::new(node.ancestors().last().unwrap_or_else(|| node.clone())).0 } pub fn add_file_edits(&mut self, file_id: impl Into, edit: SyntaxEditor) { diff --git a/src/tools/rust-analyzer/crates/ide-db/src/symbol_index.rs b/src/tools/rust-analyzer/crates/ide-db/src/symbol_index.rs index 183f6b649537..2ad3a51c3d9a 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/symbol_index.rs +++ b/src/tools/rust-analyzer/crates/ide-db/src/symbol_index.rs @@ -27,7 +27,10 @@ ops::ControlFlow, }; -use base_db::{CrateOrigin, LangCrateOrigin, LibraryRoots, LocalRoots, RootQueryDb, SourceRootId}; +use base_db::{ + CrateOrigin, InternedSourceRootId, LangCrateOrigin, LibraryRoots, LocalRoots, SourceRootId, + source_root_crates, +}; use fst::{Automaton, Streamer, raw::IndexedValue}; use hir::{ Crate, Module, @@ -255,7 +258,7 @@ pub fn world_symbols(db: &RootDatabase, mut query: Query) -> Vec> let mut crates = Vec::new(); for &root in LocalRoots::get(db).roots(db).iter() { - crates.extend(db.source_root_crates(root).iter().copied()) + crates.extend(source_root_crates(db, root).iter().copied()) } crates .par_iter() @@ -322,7 +325,7 @@ fn resolve_path_to_modules( // If not anchored to crate, also search for modules matching first segment in local crates if !anchor_to_crate { for &root in LocalRoots::get(db).roots(db).iter() { - for &krate in db.source_root_crates(root).iter() { + for &krate in source_root_crates(db, root).iter() { let root_module = Crate::from(krate).root_module(db); for child in root_module.children(db) { if let Some(name) = child.name(db) @@ -369,11 +372,6 @@ pub fn library_symbols( db: &'db dyn HirDatabase, source_root_id: SourceRootId, ) -> &'db SymbolIndex<'db> { - // FIXME: - #[salsa::interned] - struct InternedSourceRootId { - id: SourceRootId, - } #[salsa::tracked(returns(ref))] fn library_symbols<'db>( db: &'db dyn HirDatabase, @@ -385,7 +383,7 @@ fn library_symbols<'db>( hir::attach_db(db, || { let mut symbol_collector = SymbolCollector::new(db, true); - db.source_root_crates(source_root_id.id(db)) + source_root_crates(db, source_root_id.id(db)) .iter() .flat_map(|&krate| Crate::from(krate).modules(db)) // we specifically avoid calling other SymbolsDatabase queries here, even though they do the same thing, diff --git a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_doc_alias.txt b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_doc_alias.txt index fc98ebb06921..17d002e8bf4c 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_doc_alias.txt +++ b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_doc_alias.txt @@ -2,7 +2,7 @@ ( Module { id: ModuleIdLt { - [salsa id]: Id(3400), + [salsa id]: Id(3000), }, }, [ @@ -12,7 +12,7 @@ Struct( Struct { id: StructId( - 3c01, + 3801, ), }, ), @@ -20,7 +20,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -49,7 +49,7 @@ Struct( Struct { id: StructId( - 3c00, + 3800, ), }, ), @@ -57,7 +57,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -86,7 +86,7 @@ Struct( Struct { id: StructId( - 3c00, + 3800, ), }, ), @@ -94,7 +94,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -123,7 +123,7 @@ Struct( Struct { id: StructId( - 3c00, + 3800, ), }, ), @@ -131,7 +131,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -160,7 +160,7 @@ Struct( Struct { id: StructId( - 3c00, + 3800, ), }, ), @@ -168,7 +168,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -197,7 +197,7 @@ Struct( Struct { id: StructId( - 3c01, + 3801, ), }, ), @@ -205,7 +205,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -234,7 +234,7 @@ Struct( Struct { id: StructId( - 3c00, + 3800, ), }, ), @@ -242,7 +242,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { diff --git a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbol_index_collection.txt b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbol_index_collection.txt index 02a023038a61..1b20a574bd1b 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbol_index_collection.txt +++ b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbol_index_collection.txt @@ -2,7 +2,7 @@ ( Module { id: ModuleIdLt { - [salsa id]: Id(3400), + [salsa id]: Id(3000), }, }, [ @@ -11,14 +11,14 @@ def: EnumVariant( EnumVariant { id: EnumVariantId( - 7c00, + 7800, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -48,14 +48,14 @@ def: TypeAlias( TypeAlias { id: TypeAliasId( - 7000, + 6c00, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -83,14 +83,14 @@ def: EnumVariant( EnumVariant { id: EnumVariantId( - 7c01, + 7801, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -120,14 +120,14 @@ def: Const( Const { id: ConstId( - 6800, + 6400, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -155,14 +155,14 @@ def: Const( Const { id: ConstId( - 6802, + 6402, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -191,7 +191,7 @@ Enum( Enum { id: EnumId( - 5400, + 5000, ), }, ), @@ -199,7 +199,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -228,7 +228,7 @@ Macro { id: Macro2Id( Macro2Id( - 5000, + 4c00, ), ), }, @@ -236,7 +236,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -265,7 +265,7 @@ Macro { id: Macro2Id( Macro2Id( - 5000, + 4c00, ), ), }, @@ -273,7 +273,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -301,14 +301,14 @@ def: Static( Static { id: StaticId( - 6c00, + 6800, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -337,7 +337,7 @@ Struct( Struct { id: StructId( - 4c01, + 4801, ), }, ), @@ -345,7 +345,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -374,7 +374,7 @@ Struct( Struct { id: StructId( - 4c00, + 4800, ), }, ), @@ -382,7 +382,7 @@ loc: DeclarationLocation { hir_file_id: MacroFile( MacroCallId( - Id(4400), + Id(4000), ), ), ptr: SyntaxNodePtr { @@ -411,7 +411,7 @@ Struct( Struct { id: StructId( - 4c05, + 4805, ), }, ), @@ -419,7 +419,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -450,7 +450,7 @@ Struct( Struct { id: StructId( - 4c06, + 4806, ), }, ), @@ -458,7 +458,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -489,7 +489,7 @@ Struct( Struct { id: StructId( - 4c07, + 4807, ), }, ), @@ -497,7 +497,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -526,7 +526,7 @@ Struct( Struct { id: StructId( - 4c02, + 4802, ), }, ), @@ -534,7 +534,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -562,14 +562,14 @@ def: Trait( Trait { id: TraitId( - 6000, + 5c00, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -598,7 +598,7 @@ Macro { id: Macro2Id( Macro2Id( - 5000, + 4c00, ), ), }, @@ -606,7 +606,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -635,7 +635,7 @@ Union( Union { id: UnionId( - 5800, + 5400, ), }, ), @@ -643,7 +643,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -671,14 +671,14 @@ def: Module( Module { id: ModuleIdLt { - [salsa id]: Id(3401), + [salsa id]: Id(3001), }, }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -706,14 +706,14 @@ def: Module( Module { id: ModuleIdLt { - [salsa id]: Id(3402), + [salsa id]: Id(3002), }, }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -742,7 +742,7 @@ Macro { id: MacroRulesId( MacroRulesId( - 4001, + 3c01, ), ), }, @@ -750,7 +750,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -778,14 +778,14 @@ def: Function( FunctionId( FunctionId( - 6402, + 6002, ), ), ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -815,14 +815,14 @@ def: Function( FunctionId( FunctionId( - 6401, + 6001, ), ), ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -853,7 +853,7 @@ Macro { id: MacroRulesId( MacroRulesId( - 4000, + 3c00, ), ), }, @@ -861,7 +861,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -889,14 +889,14 @@ def: Function( FunctionId( FunctionId( - 6400, + 6000, ), ), ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -925,7 +925,7 @@ Macro { id: MacroRulesId( MacroRulesId( - 4001, + 3c01, ), ), }, @@ -933,7 +933,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -961,14 +961,14 @@ def: Function( FunctionId( FunctionId( - 6403, + 6003, ), ), ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -998,7 +998,7 @@ ( Module { id: ModuleIdLt { - [salsa id]: Id(3401), + [salsa id]: Id(3001), }, }, [ @@ -1008,7 +1008,7 @@ Struct( Struct { id: StructId( - 4c03, + 4803, ), }, ), @@ -1016,7 +1016,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { @@ -1044,7 +1044,7 @@ ( Module { id: ModuleIdLt { - [salsa id]: Id(3402), + [salsa id]: Id(3002), }, }, [ @@ -1053,14 +1053,14 @@ def: Trait( Trait { id: TraitId( - 6000, + 5c00, ), }, ), loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { @@ -1089,7 +1089,7 @@ Macro { id: Macro2Id( Macro2Id( - 5000, + 4c00, ), ), }, @@ -1097,7 +1097,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { @@ -1126,7 +1126,7 @@ Struct( Struct { id: StructId( - 4c04, + 4804, ), }, ), @@ -1134,7 +1134,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { @@ -1163,7 +1163,7 @@ Macro { id: Macro2Id( Macro2Id( - 5000, + 4c00, ), ), }, @@ -1171,7 +1171,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { @@ -1200,7 +1200,7 @@ Struct( Struct { id: StructId( - 4c04, + 4804, ), }, ), @@ -1208,7 +1208,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { diff --git a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_exclude_imports.txt b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_exclude_imports.txt index aff1d56c56a3..f8ae687b784c 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_exclude_imports.txt +++ b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_exclude_imports.txt @@ -5,7 +5,7 @@ Struct( Struct { id: StructId( - 4000, + 3c00, ), }, ), @@ -13,7 +13,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { diff --git a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_with_imports.txt b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_with_imports.txt index bf5d81cfb149..2282815a6103 100644 --- a/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_with_imports.txt +++ b/src/tools/rust-analyzer/crates/ide-db/src/test_data/test_symbols_with_imports.txt @@ -5,7 +5,7 @@ Struct( Struct { id: StructId( - 4000, + 3c00, ), }, ), @@ -13,7 +13,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3001), + Id(2c01), ), ), ptr: SyntaxNodePtr { @@ -42,7 +42,7 @@ Struct( Struct { id: StructId( - 4000, + 3c00, ), }, ), @@ -50,7 +50,7 @@ loc: DeclarationLocation { hir_file_id: FileId( EditionedFileId( - Id(3000), + Id(2c00), ), ), ptr: SyntaxNodePtr { diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/inactive_code.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/inactive_code.rs index dfa9639f6eb9..be4fe763a054 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/inactive_code.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/inactive_code.rs @@ -40,7 +40,10 @@ pub(crate) fn inactive_code( #[cfg(test)] mod tests { - use crate::{DiagnosticsConfig, tests::check_diagnostics_with_config}; + use ide_db::RootDatabase; + use test_fixture::WithFixture; + + use crate::{DiagnosticCode, DiagnosticsConfig, tests::check_diagnostics_with_config}; #[track_caller] pub(crate) fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { @@ -206,10 +209,47 @@ fn cfg_true_false() { #[cfg(true)] fn active() {} - #[cfg(any(not(true)), false)] fn inactive2() {} -//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ weak: code is inactive due to #[cfg] directives: true is enabled + #[cfg(any(not(true), false))] fn inactive2() {} +//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ weak: code is inactive due to #[cfg] directives: true is enabled and false is disabled "#, ); } + + #[test] + fn inactive_crate() { + let db = RootDatabase::with_files( + r#" +#![cfg(false)] + +fn foo() {} + "#, + ); + let file_id = db.test_crate().root_file_id(&db); + let diagnostics = hir::attach_db(&db, || { + crate::full_diagnostics( + &db, + &DiagnosticsConfig::test_sample(), + &ide_db::assists::AssistResolveStrategy::All, + file_id.file_id(&db), + ) + }); + let [inactive_code] = &*diagnostics else { + panic!("expected one inactive_code diagnostic, found {diagnostics:#?}"); + }; + assert_eq!( + inactive_code.code, + DiagnosticCode::Ra("inactive-code", ide_db::Severity::WeakWarning) + ); + assert_eq!( + inactive_code.message, + "code is inactive due to #[cfg] directives: false is disabled", + ); + assert!(inactive_code.fixes.is_none()); + let full_file_range = file_id.parse(&db).syntax_node().text_range(); + assert_eq!( + inactive_code.range, + ide_db::FileRange { file_id: file_id.file_id(&db), range: full_file_range }, + ); + } } diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/missing_fields.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/missing_fields.rs index 050d5477f62c..85368cc09f91 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/missing_fields.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/missing_fields.rs @@ -1,6 +1,6 @@ use either::Either; use hir::{ - AssocItem, FindPathConfig, HirDisplay, InFile, Type, + AssocItem, FindPathConfig, HasVisibility, HirDisplay, InFile, Type, db::{ExpandDatabase, HirDatabase}, sym, }; @@ -35,7 +35,7 @@ // ``` pub(crate) fn missing_fields(ctx: &DiagnosticsContext<'_>, d: &hir::MissingFields) -> Diagnostic { let mut message = String::from("missing structure fields:\n"); - for field in &d.missed_fields { + for (field, _) in &d.missed_fields { format_to!(message, "- {}\n", field.display(ctx.sema.db, ctx.edition)); } @@ -57,7 +57,7 @@ fn fixes(ctx: &DiagnosticsContext<'_>, d: &hir::MissingFields) -> Option, d: &hir::MissingFields) -> Option, d: &hir::MissingFields) -> Option A { + let v = loop {}; + A {$0} +} + "#, + r#" +struct A { + v: f64, +} + +fn f() -> A { + let v = loop {}; + A { v } +} + "#, + ); + } + + #[test] + fn inaccessible_fields() { + check_no_fix( + r#" +mod foo { + pub struct Bar { baz: i32 } +} + +fn qux() { + foo::Bar {$0}; +} + "#, + ); + } } diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/trait_impl_redundant_assoc_item.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/trait_impl_redundant_assoc_item.rs index f4054610f2bd..6a380481d4c1 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/trait_impl_redundant_assoc_item.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/trait_impl_redundant_assoc_item.rs @@ -5,8 +5,10 @@ label::Label, source_change::SourceChangeBuilder, }; -use syntax::ToSmolStr; -use syntax::ast::edit::AstNodeEdit; +use syntax::{ + AstNode, ToSmolStr, + ast::{HasName, edit::AstNodeEdit}, +}; use crate::{Diagnostic, DiagnosticCode, DiagnosticsContext}; @@ -82,16 +84,18 @@ fn quickfix_for_redundant_assoc_item( let db = ctx.sema.db; let root = db.parse_or_expand(d.file_id); // don't modify trait def in outer crate - let current_crate = ctx.sema.scope(&d.impl_.syntax_node_ptr().to_node(&root))?.krate(); + let impl_def = d.impl_.to_node(&root); + let current_crate = ctx.sema.scope(impl_def.syntax())?.krate(); let trait_def_crate = d.trait_.module(db).krate(db); if trait_def_crate != current_crate { return None; } let trait_def = d.trait_.source(db)?.value; - let l_curly = trait_def.assoc_item_list()?.l_curly_token()?.text_range(); + let insert_after = find_insert_after(range, &impl_def, &trait_def)?; + let where_to_insert = - hir::InFile::new(d.file_id, l_curly).original_node_file_range_rooted_opt(db)?; + hir::InFile::new(d.file_id, insert_after).original_node_file_range_rooted_opt(db)?; if where_to_insert.file_id != file_id { return None; } @@ -112,6 +116,41 @@ fn quickfix_for_redundant_assoc_item( }]) } +fn find_insert_after( + redundant_range: TextRange, + impl_def: &syntax::ast::Impl, + trait_def: &syntax::ast::Trait, +) -> Option { + let impl_items_before_redundant = impl_def + .assoc_item_list()? + .assoc_items() + .take_while(|it| it.syntax().text_range().start() < redundant_range.start()) + .filter_map(|it| name_of(&it)) + .collect::>(); + + let after_item = trait_def + .assoc_item_list()? + .assoc_items() + .filter(|it| { + name_of(it).is_some_and(|name| { + impl_items_before_redundant.iter().any(|it| it.text() == name.text()) + }) + }) + .last() + .map(|it| it.syntax().text_range()); + + return after_item.or_else(|| Some(trait_def.assoc_item_list()?.l_curly_token()?.text_range())); + + fn name_of(it: &syntax::ast::AssocItem) -> Option { + match it { + syntax::ast::AssocItem::Const(it) => it.name(), + syntax::ast::AssocItem::Fn(it) => it.name(), + syntax::ast::AssocItem::TypeAlias(it) => it.name(), + syntax::ast::AssocItem::MacroCall(_) => None, + } + } +} + #[cfg(test)] mod tests { use crate::tests::{check_diagnostics, check_fix, check_no_fix}; @@ -274,6 +313,69 @@ impl Marker for Foo { ); } + #[test] + fn quickfix_order() { + check_fix( + r#" +trait Marker { + fn foo(); + fn baz(); +} +struct Foo; +impl Marker for Foo { + fn foo() {} + fn missing() {}$0 + fn baz() {} +} + "#, + r#" +trait Marker { + fn foo(); + fn missing(); + fn baz(); +} +struct Foo; +impl Marker for Foo { + fn foo() {} + fn missing() {} + fn baz() {} +} + "#, + ); + + check_fix( + r#" +trait Marker { + type Item; + fn bar(); + fn baz(); +} +struct Foo; +impl Marker for Foo { + type Item = Foo; + fn missing() {}$0 + fn bar() {} + fn baz() {} +} + "#, + r#" +trait Marker { + type Item; + fn missing(); + fn bar(); + fn baz(); +} +struct Foo; +impl Marker for Foo { + type Item = Foo; + fn missing() {} + fn bar() {} + fn baz() {} +} + "#, + ); + } + #[test] fn quickfix_dont_work() { check_no_fix( diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/type_mismatch.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/type_mismatch.rs index f443dc08f5fd..ff0e6a254b6a 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/type_mismatch.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/type_mismatch.rs @@ -20,7 +20,14 @@ // // This diagnostic is triggered when the type of an expression or pattern does not match // the expected type. -pub(crate) fn type_mismatch(ctx: &DiagnosticsContext<'_>, d: &hir::TypeMismatch<'_>) -> Diagnostic { +pub(crate) fn type_mismatch( + ctx: &DiagnosticsContext<'_>, + d: &hir::TypeMismatch<'_>, +) -> Option { + if d.expected.is_unknown() || d.actual.is_unknown() { + return None; + } + let display_range = adjusted_display_range(ctx, d.expr_or_pat, &|node| { let Either::Left(expr) = node else { return None }; let salient_token_range = match expr { @@ -39,21 +46,23 @@ pub(crate) fn type_mismatch(ctx: &DiagnosticsContext<'_>, d: &hir::TypeMismatch< cov_mark::hit!(type_mismatch_range_adjustment); Some(salient_token_range) }); - Diagnostic::new( - DiagnosticCode::RustcHardError("E0308"), - format!( - "expected {}, found {}", - d.expected - .display(ctx.sema.db, ctx.display_target) - .with_closure_style(ClosureStyle::ClosureWithId), - d.actual - .display(ctx.sema.db, ctx.display_target) - .with_closure_style(ClosureStyle::ClosureWithId), - ), - display_range, + Some( + Diagnostic::new( + DiagnosticCode::RustcHardError("E0308"), + format!( + "expected {}, found {}", + d.expected + .display(ctx.sema.db, ctx.display_target) + .with_closure_style(ClosureStyle::ClosureWithId), + d.actual + .display(ctx.sema.db, ctx.display_target) + .with_closure_style(ClosureStyle::ClosureWithId), + ), + display_range, + ) + .stable() + .with_fixes(fixes(ctx, d)), ) - .stable() - .with_fixes(fixes(ctx, d)) } fn fixes(ctx: &DiagnosticsContext<'_>, d: &hir::TypeMismatch<'_>) -> Option> { @@ -101,7 +110,8 @@ fn add_missing_ok_or_some( ) -> Option<()> { let root = ctx.sema.db.parse_or_expand(expr_ptr.file_id); let expr = expr_ptr.value.to_node(&root); - let expr_range = expr.syntax().text_range(); + let hir::FileRange { file_id, range: expr_range } = + ctx.sema.original_range_opt(expr.syntax())?; let scope = ctx.sema.scope(expr.syntax())?; let expected_adt = d.expected.as_adt()?; @@ -124,6 +134,8 @@ fn add_missing_ok_or_some( return None; } + let file_id = file_id.file_id(ctx.sema.db); + if d.actual.is_unit() { if let Expr::BlockExpr(block) = &expr { if block.tail_expr().is_none() { @@ -135,21 +147,18 @@ fn add_missing_ok_or_some( // Empty block let indent = block_indent + 1; builder.insert( - block.syntax().text_range().start() + TextSize::from(1), + expr_range.start() + TextSize::from(1), format!("\n{indent}{variant_name}(())\n{block_indent}"), ); } else { let indent = IndentLevel::from(1); builder.insert( - block.syntax().text_range().end() - TextSize::from(1), + expr_range.end() - TextSize::from(1), format!("{indent}{variant_name}(())\n{block_indent}"), ); } - let source_change = SourceChange::from_text_edit( - expr_ptr.file_id.original_file(ctx.sema.db).file_id(ctx.sema.db), - builder.finish(), - ); + let source_change = SourceChange::from_text_edit(file_id, builder.finish()); let name = format!("Insert {variant_name}(()) as the tail of this block"); acc.push(fix("insert_wrapped_unit", &name, source_change, expr_range)); } @@ -158,26 +167,31 @@ fn add_missing_ok_or_some( // Fix for forms like `fn foo() -> Result<(), String> { return; }` if ret_expr.expr().is_none() { let mut builder = TextEdit::builder(); - builder - .insert(ret_expr.syntax().text_range().end(), format!(" {variant_name}(())")); - let source_change = SourceChange::from_text_edit( - expr_ptr.file_id.original_file(ctx.sema.db).file_id(ctx.sema.db), - builder.finish(), - ); + builder.insert(expr_range.end(), format!(" {variant_name}(())")); + let source_change = SourceChange::from_text_edit(file_id, builder.finish()); let name = format!("Insert {variant_name}(()) as the return value"); acc.push(fix("insert_wrapped_unit", &name, source_change, expr_range)); } return Some(()); + } else if expr.is_block_like() + && expr.syntax().parent().and_then(ast::StmtList::cast).is_some() + { + // Fix for forms like `fn foo() -> Result<(), String> { for _ in 0..8 {} }` + let mut builder = TextEdit::builder(); + let indent = expr.indent_level(); + builder.insert(expr_range.end(), format!("\n{indent}{variant_name}(())")); + + let source_change = SourceChange::from_text_edit(file_id, builder.finish()); + let name = format!("Insert {variant_name}(()) as the tail of this block"); + acc.push(fix("insert_wrapped_unit", &name, source_change, expr_range)); + return Some(()); } } let mut builder = TextEdit::builder(); - builder.insert(expr.syntax().text_range().start(), format!("{variant_name}(")); - builder.insert(expr.syntax().text_range().end(), ")".to_owned()); - let source_change = SourceChange::from_text_edit( - expr_ptr.file_id.original_file(ctx.sema.db).file_id(ctx.sema.db), - builder.finish(), - ); + builder.insert(expr_range.start(), format!("{variant_name}(")); + builder.insert(expr_range.end(), ")".to_owned()); + let source_change = SourceChange::from_text_edit(file_id, builder.finish()); let name = format!("Wrap in {variant_name}"); acc.push(fix("wrap_in_constructor", &name, source_change, expr_range)); Some(()) @@ -192,6 +206,7 @@ fn remove_unnecessary_wrapper( let db = ctx.sema.db; let root = db.parse_or_expand(expr_ptr.file_id); let expr = expr_ptr.value.to_node(&root); + // FIXME: support inside MacroCall? let expr = ctx.sema.original_ast_node(expr)?; let Expr::CallExpr(call_expr) = expr else { @@ -278,6 +293,7 @@ fn remove_semicolon( return None; } let block = BlockExpr::cast(expr.syntax().clone())?; + // FIXME: support inside MacroCall? let expr_before_semi = block.statements().last().and_then(|s| ExprStmt::cast(s.syntax().clone()))?; let type_before_semi = ctx.sema.type_of_expr(&expr_before_semi.expr()?)?.original(); @@ -311,16 +327,13 @@ fn str_ref_to_owned( let root = ctx.sema.db.parse_or_expand(expr_ptr.file_id); let expr = expr_ptr.value.to_node(&root); - let expr_range = expr.syntax().text_range(); + let hir::FileRange { file_id, range } = ctx.sema.original_range_opt(expr.syntax())?; let to_owned = ".to_owned()".to_owned(); - let edit = TextEdit::insert(expr.syntax().text_range().end(), to_owned); - let source_change = SourceChange::from_text_edit( - expr_ptr.file_id.original_file(ctx.sema.db).file_id(ctx.sema.db), - edit, - ); - acc.push(fix("str_ref_to_owned", "Add .to_owned() here", source_change, expr_range)); + let edit = TextEdit::insert(range.end(), to_owned); + let source_change = SourceChange::from_text_edit(file_id.file_id(ctx.sema.db), edit); + acc.push(fix("str_ref_to_owned", "Add .to_owned() here", source_change, range)); Some(()) } @@ -566,6 +579,32 @@ fn div(x: i32, y: i32) -> Result { } Ok(x / y) } +"#, + ); + + check_fix( + r#" +//- minicore: option, result +macro_rules! identity { ($($t:tt)*) => ($($t)*) } +identity! { + fn div(x: i32, y: i32) -> Result { + if y == 0 { + return Err(()); + } + x / y$0 + } +} +"#, + r#" +macro_rules! identity { ($($t:tt)*) => ($($t)*) } +identity! { + fn div(x: i32, y: i32) -> Result { + if y == 0 { + return Err(()); + } + Ok(x / y) + } +} "#, ); } @@ -697,6 +736,21 @@ fn foo() -> Result<(), ()> {}$0 r#" fn foo() -> Result<(), ()> { Ok(()) +} + "#, + ); + + check_fix( + r#" +//- minicore: result +fn foo() -> Result<(), ()> { + for _ in 0..5 {}$0 +} + "#, + r#" +fn foo() -> Result<(), ()> { + for _ in 0..5 {} + Ok(()) } "#, ); @@ -1037,6 +1091,29 @@ fn test() -> String { fn test() -> String { "a".to_owned() +} + "#, + ); + + check_fix( + r#" +macro_rules! identity { ($($t:tt)*) => ($($t)*) } +struct String; + +identity! { + fn test() -> String { + "a"$0 + } +} + "#, + r#" +macro_rules! identity { ($($t:tt)*) => ($($t)*) } +struct String; + +identity! { + fn test() -> String { + "a".to_owned() + } } "#, ); @@ -1250,6 +1327,25 @@ enum E { V() } let E::V() = &S {}; // ^^^^^^ error: expected S, found E } +"#, + ); + } + + #[test] + fn test_ignore_unknown_mismatch() { + check_diagnostics( + r#" +pub trait Foo { + type Out; +} +impl Foo for [i32; 1] { + type Out = (); +} +pub fn foo(_: T) -> (T::Out,) { loop { } } + +fn main() { + let _x = foo(2); +} "#, ); } diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/unlinked_file.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/unlinked_file.rs index 1283a11700e1..d7a0a3b0f59d 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/unlinked_file.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/handlers/unlinked_file.rs @@ -4,7 +4,7 @@ use hir::crate_def_map; use hir::{InFile, ModuleSource}; -use ide_db::base_db::RootQueryDb; +use ide_db::base_db; use ide_db::text_edit::TextEdit; use ide_db::{ FileId, FileRange, LineIndexDatabase, base_db::SourceDatabase, source_change::SourceChange, @@ -101,8 +101,8 @@ fn fixes( }; // check crate roots, i.e. main.rs, lib.rs, ... - let relevant_crates = db.relevant_crates(file_id); - 'crates: for &krate in &*relevant_crates { + let relevant_crates = base_db::relevant_crates(db, file_id); + 'crates: for &krate in relevant_crates { // FIXME: This shouldnt need to access the crate def map directly let crate_def_map = crate_def_map(ctx.sema.db, krate); @@ -157,7 +157,7 @@ fn fixes( paths.into_iter().find_map(|path| source_root.file_for_path(&path)) })?; stack.pop(); - let relevant_crates = db.relevant_crates(parent_id); + let relevant_crates = base_db::relevant_crates(db, parent_id); 'crates: for &krate in relevant_crates.iter() { let crate_def_map = crate_def_map(ctx.sema.db, krate); let Some((_, module)) = crate_def_map.modules().find(|(_, module)| { diff --git a/src/tools/rust-analyzer/crates/ide-diagnostics/src/lib.rs b/src/tools/rust-analyzer/crates/ide-diagnostics/src/lib.rs index 0c6953419f7d..09c9f8eab0a0 100644 --- a/src/tools/rust-analyzer/crates/ide-diagnostics/src/lib.rs +++ b/src/tools/rust-analyzer/crates/ide-diagnostics/src/lib.rs @@ -96,7 +96,7 @@ mod handlers { use ide_db::{ FileId, FileRange, FxHashMap, FxHashSet, RootDatabase, Severity, SnippetCap, assists::{Assist, AssistId, AssistResolveStrategy, ExprFillDefaultMode}, - base_db::{ReleaseChannel, RootQueryDb as _}, + base_db::{ReleaseChannel, all_crates, toolchain_channel}, generated::lints::{CLIPPY_LINT_GROUPS, DEFAULT_LINT_GROUPS, DEFAULT_LINTS, Lint, LintGroup}, imports::insert_use::InsertUseConfig, label::Label, @@ -285,6 +285,12 @@ struct DiagnosticsContext<'a> { is_nightly: bool, } +impl<'a> DiagnosticsContext<'a> { + fn db(&self) -> &'a RootDatabase { + self.sema.db + } +} + /// Request parser level diagnostics for the given [`FileId`]. pub fn syntax_diagnostics( db: &RootDatabase, @@ -303,7 +309,8 @@ pub fn syntax_diagnostics( let (file_id, _) = editioned_file_id.unpack(db); // [#3434] Only take first 128 errors to prevent slowing down editor/ide, the number 128 is chosen arbitrarily. - db.parse_errors(editioned_file_id) + editioned_file_id + .parse_errors(db) .into_iter() .flatten() .take(128) @@ -353,14 +360,14 @@ pub fn semantic_diagnostics( let module = sema.file_to_module_def(file_id); let is_nightly = matches!( - module.and_then(|m| db.toolchain_channel(m.krate(db).into())), + module.and_then(|m| toolchain_channel(db, m.krate(db).into())), Some(ReleaseChannel::Nightly) | None ); let krate = match module { Some(module) => module.krate(db), None => { - match db.all_crates().last() { + match all_crates(db).last() { Some(last) => (*last).into(), // short-circuit, return an empty vec of diagnostics None => return vec![], @@ -375,7 +382,7 @@ pub fn semantic_diagnostics( // A bunch of parse errors in a file indicate some bigger structural parse changes in the // file, so we skip semantic diagnostics so we can show these faster. Some(m) => { - if db.parse_errors(editioned_file_id).is_none_or(|es| es.len() < 16) { + if editioned_file_id.parse_errors(db).is_none_or(|es| es.len() < 16) { m.diagnostics(db, &mut diags, config.style_lints); } } @@ -430,7 +437,10 @@ pub fn semantic_diagnostics( AnyDiagnostic::TraitImplRedundantAssocItems(d) => handlers::trait_impl_redundant_assoc_item::trait_impl_redundant_assoc_item(&ctx, &d), AnyDiagnostic::TraitImplOrphan(d) => handlers::trait_impl_orphan::trait_impl_orphan(&ctx, &d), AnyDiagnostic::TypedHole(d) => handlers::typed_hole::typed_hole(&ctx, &d), - AnyDiagnostic::TypeMismatch(d) => handlers::type_mismatch::type_mismatch(&ctx, &d), + AnyDiagnostic::TypeMismatch(d) => match handlers::type_mismatch::type_mismatch(&ctx, &d) { + Some(diag) => diag, + None => continue, + }, AnyDiagnostic::UndeclaredLabel(d) => handlers::undeclared_label::undeclared_label(&ctx, &d), AnyDiagnostic::UnimplementedBuiltinMacro(d) => handlers::unimplemented_builtin_macro::unimplemented_builtin_macro(&ctx, &d), AnyDiagnostic::UnreachableLabel(d) => handlers::unreachable_label::unreachable_label(&ctx, &d), diff --git a/src/tools/rust-analyzer/crates/ide-ssr/src/from_comment.rs b/src/tools/rust-analyzer/crates/ide-ssr/src/from_comment.rs index 181cc74a51d4..83b8c3dc81ea 100644 --- a/src/tools/rust-analyzer/crates/ide-ssr/src/from_comment.rs +++ b/src/tools/rust-analyzer/crates/ide-ssr/src/from_comment.rs @@ -1,7 +1,7 @@ //! This module allows building an SSR MatchFinder by parsing the SSR rule //! from a comment. -use ide_db::{EditionedFileId, FilePosition, FileRange, RootDatabase, base_db::RootQueryDb}; +use ide_db::{EditionedFileId, FilePosition, FileRange, RootDatabase}; use syntax::{ TextRange, ast::{self, AstNode, AstToken}, @@ -19,7 +19,7 @@ pub fn ssr_from_comment( let comment = { let file_id = EditionedFileId::current_edition(db, frange.file_id); - let file = db.parse(file_id); + let file = file_id.parse(db); file.tree().syntax().token_at_offset(frange.range.start()).find_map(ast::Comment::cast) }?; let comment_text_without_prefix = comment.text().strip_prefix(comment.prefix()).unwrap(); diff --git a/src/tools/rust-analyzer/crates/ide-ssr/src/matching.rs b/src/tools/rust-analyzer/crates/ide-ssr/src/matching.rs index 264f0660d7f2..ab5a0f70f5a6 100644 --- a/src/tools/rust-analyzer/crates/ide-ssr/src/matching.rs +++ b/src/tools/rust-analyzer/crates/ide-ssr/src/matching.rs @@ -7,7 +7,7 @@ resolving::{ResolvedPattern, ResolvedRule, UfcsCallInfo}, }; use hir::{FileRange, FindPathConfig, Semantics}; -use ide_db::{FxHashMap, base_db::RootQueryDb}; +use ide_db::{FxHashMap, base_db::all_crates}; use std::{cell::Cell, iter::Peekable}; use syntax::{ SmolStr, SyntaxElement, SyntaxElementChildren, SyntaxKind, SyntaxNode, SyntaxToken, @@ -621,7 +621,7 @@ fn check_expr_type( })? .original; let krate = self.sema.scope(expr.syntax()).map(|it| it.krate()).unwrap_or_else(|| { - hir::Crate::from(*self.sema.db.all_crates().last().expect("no crate graph present")) + hir::Crate::from(*all_crates(self.sema.db).last().expect("no crate graph present")) }); code_type diff --git a/src/tools/rust-analyzer/crates/ide/src/annotations.rs b/src/tools/rust-analyzer/crates/ide/src/annotations.rs index 6fb8dedea47c..21b2339c722c 100644 --- a/src/tools/rust-analyzer/crates/ide/src/annotations.rs +++ b/src/tools/rust-analyzer/crates/ide/src/annotations.rs @@ -1,7 +1,7 @@ use hir::{HasSource, InFile, InRealFile, Semantics}; use ide_db::{ - FileId, FilePosition, FileRange, FxIndexSet, MiniCore, RootDatabase, defs::Definition, - helpers::visit_file_defs, + FileId, FilePosition, FileRange, FxIndexSet, RootDatabase, defs::Definition, + helpers::visit_file_defs, ra_fixture::RaFixtureConfig, }; use itertools::Itertools; use syntax::{AstNode, TextRange, ast::HasName}; @@ -45,7 +45,7 @@ pub struct AnnotationConfig<'a> { pub annotate_enum_variant_references: bool, pub location: AnnotationLocation, pub filter_adjacent_derive_implementations: bool, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } pub enum AnnotationLocation { @@ -216,7 +216,7 @@ pub(crate) fn resolve_annotation( *data = find_all_refs( &Semantics::new(db), pos, - &FindAllRefsConfig { search_scope: None, minicore: config.minicore }, + &FindAllRefsConfig { search_scope: None, ra_fixture: config.ra_fixture }, ) .map(|result| { result @@ -244,7 +244,7 @@ fn should_skip_runnable(kind: &RunnableKind, binary_target: bool) -> bool { #[cfg(test)] mod tests { use expect_test::{Expect, expect}; - use ide_db::MiniCore; + use ide_db::ra_fixture::RaFixtureConfig; use crate::{Annotation, AnnotationConfig, fixture}; @@ -258,7 +258,7 @@ mod tests { annotate_method_references: true, annotate_enum_variant_references: true, location: AnnotationLocation::AboveName, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), filter_adjacent_derive_implementations: false, }; @@ -898,9 +898,6 @@ fn my_cool_test() {} test_id: Path( "tests::my_cool_test", ), - attr: TestAttr { - ignore: false, - }, }, cfg: None, update_test: UpdateTest { diff --git a/src/tools/rust-analyzer/crates/ide/src/call_hierarchy.rs b/src/tools/rust-analyzer/crates/ide/src/call_hierarchy.rs index aded911a8db1..402764f11202 100644 --- a/src/tools/rust-analyzer/crates/ide/src/call_hierarchy.rs +++ b/src/tools/rust-analyzer/crates/ide/src/call_hierarchy.rs @@ -4,9 +4,10 @@ use hir::Semantics; use ide_db::{ - FileRange, FxIndexMap, MiniCore, RootDatabase, + FileRange, FxIndexMap, RootDatabase, defs::{Definition, NameClass, NameRefClass}, helpers::pick_best_token, + ra_fixture::RaFixtureConfig, search::FileReference, }; use syntax::{AstNode, SyntaxKind::IDENT, ast}; @@ -25,7 +26,7 @@ pub struct CallItem { pub struct CallHierarchyConfig<'a> { /// Whether to exclude tests from the call hierarchy pub exclude_tests: bool, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } pub(crate) fn call_hierarchy( @@ -36,7 +37,7 @@ pub(crate) fn call_hierarchy( goto_definition::goto_definition( db, position, - &GotoDefinitionConfig { minicore: config.minicore }, + &GotoDefinitionConfig { ra_fixture: config.ra_fixture }, ) } @@ -174,7 +175,7 @@ fn into_items(self) -> Vec { #[cfg(test)] mod tests { use expect_test::{Expect, expect}; - use ide_db::{FilePosition, MiniCore}; + use ide_db::{FilePosition, ra_fixture::RaFixtureConfig}; use itertools::Itertools; use crate::fixture; @@ -197,7 +198,8 @@ fn debug_render(item: crate::CallItem) -> String { ) } - let config = crate::CallHierarchyConfig { exclude_tests, minicore: MiniCore::default() }; + let config = + crate::CallHierarchyConfig { exclude_tests, ra_fixture: RaFixtureConfig::default() }; let (analysis, pos) = fixture::position(ra_fixture); let mut navs = analysis.call_hierarchy(pos, &config).unwrap().unwrap().info; diff --git a/src/tools/rust-analyzer/crates/ide/src/doc_links.rs b/src/tools/rust-analyzer/crates/ide/src/doc_links.rs index 33bed9501a39..fd462d003d7d 100644 --- a/src/tools/rust-analyzer/crates/ide/src/doc_links.rs +++ b/src/tools/rust-analyzer/crates/ide/src/doc_links.rs @@ -17,7 +17,7 @@ }; use ide_db::{ RootDatabase, - base_db::{CrateOrigin, LangCrateOrigin, ReleaseChannel, RootQueryDb}, + base_db::{CrateOrigin, LangCrateOrigin, ReleaseChannel, toolchain_channel}, defs::{Definition, NameClass, NameRefClass}, documentation::{Documentation, HasDocs}, helpers::pick_best_token, @@ -552,7 +552,7 @@ fn get_doc_base_urls( .and_then(|it| Url::parse(&it).ok()); let krate = def.krate(db); let channel = krate - .and_then(|krate| db.toolchain_channel(krate.into())) + .and_then(|krate| toolchain_channel(db, krate.into())) .unwrap_or(ReleaseChannel::Nightly) .as_str(); diff --git a/src/tools/rust-analyzer/crates/ide/src/expand_macro.rs b/src/tools/rust-analyzer/crates/ide/src/expand_macro.rs index 44285d9315af..fb885c2ad11f 100644 --- a/src/tools/rust-analyzer/crates/ide/src/expand_macro.rs +++ b/src/tools/rust-analyzer/crates/ide/src/expand_macro.rs @@ -54,8 +54,9 @@ pub(crate) fn expand_macro(db: &RootDatabase, position: FilePosition) -> Option< let InFile { file_id, value: tokens } = hir::InMacroFile::new(macro_file, descended).upmap_once(db); let token = sema.parse_or_expand(file_id).covering_element(tokens[0]).into_token()?; - let attr = token.parent_ancestors().find_map(ast::Attr::cast)?; + let attr = token.parent_ancestors().find_map(ast::Meta::cast)?; let expansions = sema.expand_derive_macro(&attr)?; + let ast::Meta::TokenTreeMeta(attr) = attr else { return None }; let idx = attr .token_tree()? .token_trees_and_tokens() @@ -235,7 +236,7 @@ fn _format( file_id: FileId, expansion: &str, ) -> Option { - use ide_db::base_db::RootQueryDb; + use ide_db::base_db::relevant_crates; // hack until we get hygiene working (same character amount to preserve formatting as much as possible) const DOLLAR_CRATE_REPLACE: &str = "__r_a_"; @@ -250,7 +251,7 @@ fn _format( }; let expansion = format!("{prefix}{expansion}{suffix}"); - let &crate_id = db.relevant_crates(file_id).iter().next()?; + let &crate_id = relevant_crates(db, file_id).iter().next()?; let edition = crate_id.data(db).edition; #[allow(clippy::disallowed_methods)] diff --git a/src/tools/rust-analyzer/crates/ide/src/fetch_crates.rs b/src/tools/rust-analyzer/crates/ide/src/fetch_crates.rs index 956379e722d5..ad5af8bfe152 100644 --- a/src/tools/rust-analyzer/crates/ide/src/fetch_crates.rs +++ b/src/tools/rust-analyzer/crates/ide/src/fetch_crates.rs @@ -1,6 +1,6 @@ use ide_db::{ FileId, FxIndexSet, RootDatabase, - base_db::{CrateOrigin, RootQueryDb}, + base_db::{CrateOrigin, all_crates}, }; #[derive(Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] @@ -20,7 +20,7 @@ pub struct CrateInfo { // // ![Show Dependency Tree](https://user-images.githubusercontent.com/5748995/229394139-2625beab-f4c9-484b-84ed-ad5dee0b1e1a.png) pub(crate) fn fetch_crates(db: &RootDatabase) -> FxIndexSet { - db.all_crates() + all_crates(db) .iter() .copied() .map(|crate_id| (crate_id.data(db), crate_id.extra_data(db))) diff --git a/src/tools/rust-analyzer/crates/ide/src/folding_ranges.rs b/src/tools/rust-analyzer/crates/ide/src/folding_ranges.rs index 3969490e8dcf..375e42cc833e 100644 --- a/src/tools/rust-analyzer/crates/ide/src/folding_ranges.rs +++ b/src/tools/rust-analyzer/crates/ide/src/folding_ranges.rs @@ -1,10 +1,11 @@ use ide_db::{FxHashSet, syntax_helpers::node_ext::vis_eq}; use syntax::{ - Direction, NodeOrToken, SourceFile, - SyntaxKind::{self, *}, + Direction, NodeOrToken, SourceFile, SyntaxElement, + SyntaxKind::*, SyntaxNode, TextRange, TextSize, ast::{self, AstNode, AstToken}, match_ast, + syntax_editor::Element, }; use std::hash::Hash; @@ -31,19 +32,33 @@ pub enum FoldKind { TypeAliases, ExternCrates, // endregion: item runs + Stmt(ast::Stmt), + TailExpr(ast::Expr), } #[derive(Debug)] pub struct Fold { pub range: TextRange, pub kind: FoldKind, + pub collapsed_text: Option, +} + +impl Fold { + pub fn new(range: TextRange, kind: FoldKind) -> Self { + Self { range, kind, collapsed_text: None } + } + + pub fn with_text(mut self, text: Option) -> Self { + self.collapsed_text = text; + self + } } // Feature: Folding // // Defines folding regions for curly braced blocks, runs of consecutive use, mod, const or static // items, and `region` / `endregion` comment markers. -pub(crate) fn folding_ranges(file: &SourceFile) -> Vec { +pub(crate) fn folding_ranges(file: &SourceFile, add_collapsed_text: bool) -> Vec { let mut res = vec![]; let mut visited_comments = FxHashSet::default(); let mut visited_nodes = FxHashSet::default(); @@ -53,39 +68,41 @@ pub(crate) fn folding_ranges(file: &SourceFile) -> Vec { for element in file.syntax().descendants_with_tokens() { // Fold items that span multiple lines - if let Some(kind) = fold_kind(element.kind()) { + if let Some(kind) = fold_kind(element.clone()) { let is_multiline = match &element { NodeOrToken::Node(node) => node.text().contains_char('\n'), NodeOrToken::Token(token) => token.text().contains('\n'), }; + if is_multiline { - // for the func with multiline param list - if matches!(element.kind(), FN) - && let NodeOrToken::Node(node) = &element - && let Some(fn_node) = ast::Fn::cast(node.clone()) + if let NodeOrToken::Node(node) = &element + && let Some(fn_) = ast::Fn::cast(node.clone()) { - if !fn_node + if !fn_ .param_list() .map(|param_list| param_list.syntax().text().contains_char('\n')) - .unwrap_or(false) + .unwrap_or_default() { continue; } - if fn_node.body().is_some() { + if let Some(body) = fn_.body() { // Get the actual start of the function (excluding doc comments) - let fn_start = fn_node + let fn_start = fn_ .fn_token() .map(|token| token.text_range().start()) .unwrap_or(node.text_range().start()); - res.push(Fold { - range: TextRange::new(fn_start, node.text_range().end()), - kind: FoldKind::Function, - }); + res.push(Fold::new( + TextRange::new(fn_start, body.syntax().text_range().end()), + FoldKind::Function, + )); continue; } } - res.push(Fold { range: element.text_range(), kind }); + + let collapsed_text = if add_collapsed_text { collapsed_text(&kind) } else { None }; + let fold = Fold::new(element.text_range(), kind).with_text(collapsed_text); + res.push(fold); continue; } } @@ -102,15 +119,15 @@ pub(crate) fn folding_ranges(file: &SourceFile) -> Vec { region_starts.push(comment.syntax().text_range().start()); } else if text.starts_with(REGION_END) { if let Some(region) = region_starts.pop() { - res.push(Fold { - range: TextRange::new(region, comment.syntax().text_range().end()), - kind: FoldKind::Region, - }) + res.push(Fold::new( + TextRange::new(region, comment.syntax().text_range().end()), + FoldKind::Region, + )); } } else if let Some(range) = contiguous_range_for_comment(comment, &mut visited_comments) { - res.push(Fold { range, kind: FoldKind::Comment }) + res.push(Fold::new(range, FoldKind::Comment)); } } } @@ -123,37 +140,37 @@ pub(crate) fn folding_ranges(file: &SourceFile) -> Vec { module, &mut visited_nodes, ) { - res.push(Fold { range, kind: FoldKind::Modules }) + res.push(Fold::new(range, FoldKind::Modules)); } }, ast::Use(use_) => { if let Some(range) = contiguous_range_for_item_group(use_, &mut visited_nodes) { - res.push(Fold { range, kind: FoldKind::Imports }) + res.push(Fold::new(range, FoldKind::Imports)); } }, ast::Const(konst) => { if let Some(range) = contiguous_range_for_item_group(konst, &mut visited_nodes) { - res.push(Fold { range, kind: FoldKind::Consts }) + res.push(Fold::new(range, FoldKind::Consts)); } }, ast::Static(statik) => { if let Some(range) = contiguous_range_for_item_group(statik, &mut visited_nodes) { - res.push(Fold { range, kind: FoldKind::Statics }) + res.push(Fold::new(range, FoldKind::Statics)); } }, ast::TypeAlias(alias) => { if let Some(range) = contiguous_range_for_item_group(alias, &mut visited_nodes) { - res.push(Fold { range, kind: FoldKind::TypeAliases }) + res.push(Fold::new(range, FoldKind::TypeAliases)); } }, ast::ExternCrate(extern_crate) => { if let Some(range) = contiguous_range_for_item_group(extern_crate, &mut visited_nodes) { - res.push(Fold { range, kind: FoldKind::ExternCrates }) + res.push(Fold::new(range, FoldKind::ExternCrates)); } }, ast::MatchArm(match_arm) => { if let Some(range) = fold_range_for_multiline_match_arm(match_arm) { - res.push(Fold {range, kind: FoldKind::MatchArm}) + res.push(Fold::new(range, FoldKind::MatchArm)); } }, _ => (), @@ -166,8 +183,66 @@ pub(crate) fn folding_ranges(file: &SourceFile) -> Vec { res } -fn fold_kind(kind: SyntaxKind) -> Option { +fn collapsed_text(kind: &FoldKind) -> Option { match kind { + FoldKind::TailExpr(expr) => collapse_expr(expr.clone()), + FoldKind::Stmt(stmt) => { + match stmt { + ast::Stmt::ExprStmt(expr_stmt) => { + expr_stmt.expr().and_then(collapse_expr).map(|text| format!("{text};")) + } + ast::Stmt::LetStmt(let_stmt) => 'blk: { + if let_stmt.let_else().is_some() { + break 'blk None; + } + + let Some(expr) = let_stmt.initializer() else { + break 'blk None; + }; + + // If the `let` statement spans multiple lines, we do not collapse it. + // We use the `eq_token` to check whether the `let` statement is a single line, + // as the formatter may place the initializer on a new line for better readability. + // + // Example: + // ```rust + // let complex_pat = + // complex_expr; + // ``` + // + // In this case, we should generate the collapsed text. + let Some(eq_token) = let_stmt.eq_token() else { + break 'blk None; + }; + let eq_token_offset = + eq_token.text_range().end() - let_stmt.syntax().text_range().start(); + let text_until_eq_token = let_stmt.syntax().text().slice(..eq_token_offset); + if text_until_eq_token.contains_char('\n') { + break 'blk None; + } + + collapse_expr(expr).map(|text| format!("{text_until_eq_token} {text};")) + } + // handling `items` in external matches. + ast::Stmt::Item(_) => None, + } + } + _ => None, + } +} + +fn fold_kind(element: SyntaxElement) -> Option { + // handle tail_expr + if let Some(node) = element.as_node() + // tail_expr -> stmt_list -> block + && let Some(block) = node.parent().and_then(|it| it.parent()).and_then(ast::BlockExpr::cast) + && let Some(tail_expr) = block.tail_expr() + && tail_expr.syntax() == node + { + return Some(FoldKind::TailExpr(tail_expr)); + } + + match element.kind() { COMMENT => Some(FoldKind::Comment), ARG_LIST | PARAM_LIST | GENERIC_ARG_LIST | GENERIC_PARAM_LIST => Some(FoldKind::ArgList), ARRAY_EXPR => Some(FoldKind::Array), @@ -185,10 +260,73 @@ fn fold_kind(kind: SyntaxKind) -> Option { | MATCH_ARM_LIST | VARIANT_LIST | TOKEN_TREE => Some(FoldKind::Block), + EXPR_STMT | LET_STMT => Some(FoldKind::Stmt(ast::Stmt::cast(element.as_node()?.clone())?)), _ => None, } } +const COLLAPSE_EXPR_MAX_LEN: usize = 100; + +fn collapse_expr(expr: ast::Expr) -> Option { + let mut text = String::with_capacity(COLLAPSE_EXPR_MAX_LEN * 2); + + let mut preorder = expr.syntax().preorder_with_tokens(); + while let Some(element) = preorder.next() { + match element { + syntax::WalkEvent::Enter(NodeOrToken::Node(node)) => { + if let Some(arg_list) = ast::ArgList::cast(node.clone()) { + let content = if arg_list.args().next().is_some() { "(…)" } else { "()" }; + text.push_str(content); + preorder.skip_subtree(); + } else if let Some(expr) = ast::Expr::cast(node) { + match expr { + ast::Expr::AwaitExpr(_) + | ast::Expr::BecomeExpr(_) + | ast::Expr::BinExpr(_) + | ast::Expr::BreakExpr(_) + | ast::Expr::CallExpr(_) + | ast::Expr::CastExpr(_) + | ast::Expr::ContinueExpr(_) + | ast::Expr::FieldExpr(_) + | ast::Expr::IndexExpr(_) + | ast::Expr::LetExpr(_) + | ast::Expr::Literal(_) + | ast::Expr::MethodCallExpr(_) + | ast::Expr::OffsetOfExpr(_) + | ast::Expr::ParenExpr(_) + | ast::Expr::PathExpr(_) + | ast::Expr::PrefixExpr(_) + | ast::Expr::RangeExpr(_) + | ast::Expr::RefExpr(_) + | ast::Expr::ReturnExpr(_) + | ast::Expr::TryExpr(_) + | ast::Expr::UnderscoreExpr(_) + | ast::Expr::YeetExpr(_) + | ast::Expr::YieldExpr(_) => {} + + // Some other exprs (e.g. `while` loop) are too complex to have a collapsed text + _ => return None, + } + } + } + syntax::WalkEvent::Enter(NodeOrToken::Token(token)) => { + if !token.kind().is_trivia() { + text.push_str(token.text()); + } + } + syntax::WalkEvent::Leave(_) => {} + } + + if text.len() > COLLAPSE_EXPR_MAX_LEN { + return None; + } + } + + text.shrink_to_fit(); + + Some(text) +} + fn contiguous_range_for_item_group( first: N, visited: &mut FxHashSet, @@ -297,7 +435,7 @@ fn contiguous_range_for_comment( } fn fold_range_for_multiline_match_arm(match_arm: ast::MatchArm) -> Option { - if fold_kind(match_arm.expr()?.syntax().kind()).is_some() { + if fold_kind(match_arm.expr()?.syntax().syntax_element()).is_some() { None } else if match_arm.expr()?.syntax().text().contains_char('\n') { Some(match_arm.expr()?.syntax().text_range()) @@ -314,10 +452,33 @@ mod tests { #[track_caller] fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { + check_inner(ra_fixture, true); + } + + fn check_without_collapsed_text(#[rust_analyzer::rust_fixture] ra_fixture: &str) { + check_inner(ra_fixture, false); + } + + fn check_inner(ra_fixture: &str, enable_collapsed_text: bool) { let (ranges, text) = extract_tags(ra_fixture, "fold"); + let ranges: Vec<_> = ranges + .into_iter() + .map(|(range, text)| { + let (attr, collapsed_text) = match text { + Some(text) => match text.split_once(':') { + Some((attr, collapsed_text)) => { + (Some(attr.to_owned()), Some(collapsed_text.to_owned())) + } + None => (Some(text), None), + }, + None => (None, None), + }; + (range, attr, collapsed_text) + }) + .collect(); let parse = SourceFile::parse(&text, span::Edition::CURRENT); - let mut folds = folding_ranges(&parse.tree()); + let mut folds = folding_ranges(&parse.tree(), enable_collapsed_text); folds.sort_by_key(|fold| (fold.range.start(), fold.range.end())); assert_eq!( @@ -326,7 +487,7 @@ fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { "The amount of folds is different than the expected amount" ); - for (fold, (range, attr)) in folds.iter().zip(ranges.into_iter()) { + for (fold, (range, attr, collapsed_text)) in folds.iter().zip(ranges.into_iter()) { assert_eq!(fold.range.start(), range.start(), "mismatched start of folding ranges"); assert_eq!(fold.range.end(), range.end(), "mismatched end of folding ranges"); @@ -346,8 +507,15 @@ fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { FoldKind::MatchArm => "matcharm", FoldKind::Function => "function", FoldKind::ExternCrates => "externcrates", + FoldKind::Stmt(_) => "stmt", + FoldKind::TailExpr(_) => "tailexpr", }; assert_eq!(kind, &attr.unwrap()); + if enable_collapsed_text { + assert_eq!(fold.collapsed_text, collapsed_text); + } else { + assert_eq!(fold.collapsed_text, None); + } } } @@ -511,10 +679,10 @@ fn test_fold_match_arms() { check( r#" fn main() { - match 0 { + match 0 { 0 => 0, _ => 1, - } + } } "#, ); @@ -525,7 +693,7 @@ fn test_fold_multiline_non_block_match_arm() { check( r#" fn main() { - match foo { + match foo { block => { }, matcharm => some. @@ -544,7 +712,7 @@ fn main() { structS => StructS { a: 31, }, - } + } } "#, ) @@ -555,11 +723,11 @@ fn fold_big_calls() { check( r#" fn main() { - frobnicate( + frobnicate( 1, 2, 3, - ) + ) } "#, ) @@ -698,4 +866,51 @@ fn test_fold_doc_comments_with_multiline_paramlist_function() { "#, ); } + + #[test] + fn test_fold_tail_expr() { + check( + r#" +fn f() { + let x = 1; + + some_function() + .chain() + .method() +} +"#, + ) + } + + #[test] + fn test_fold_let_stmt_with_chained_methods() { + check( + r#" +fn main() { + let result = some_value + .method1() + .method2()? + .method3(); + + println!("{}", result); +} +"#, + ) + } + + #[test] + fn test_fold_let_stmt_with_chained_methods_without_collapsed_text() { + check_without_collapsed_text( + r#" +fn main() { + let result = some_value + .method1() + .method2()? + .method3(); + + println!("{}", result); +} +"#, + ) + } } diff --git a/src/tools/rust-analyzer/crates/ide/src/goto_declaration.rs b/src/tools/rust-analyzer/crates/ide/src/goto_declaration.rs index 375ce94bf644..d2b47a37c7b0 100644 --- a/src/tools/rust-analyzer/crates/ide/src/goto_declaration.rs +++ b/src/tools/rust-analyzer/crates/ide/src/goto_declaration.rs @@ -79,13 +79,13 @@ pub(crate) fn goto_declaration( #[cfg(test)] mod tests { - use ide_db::{FileRange, MiniCore}; + use ide_db::{FileRange, ra_fixture::RaFixtureConfig}; use itertools::Itertools; use crate::{GotoDefinitionConfig, fixture}; const TEST_CONFIG: GotoDefinitionConfig<'_> = - GotoDefinitionConfig { minicore: MiniCore::default() }; + GotoDefinitionConfig { ra_fixture: RaFixtureConfig::default() }; fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { let (analysis, position, expected) = fixture::annotations(ra_fixture); diff --git a/src/tools/rust-analyzer/crates/ide/src/goto_definition.rs b/src/tools/rust-analyzer/crates/ide/src/goto_definition.rs index 3890bcad7fc6..4cdf0eac7568 100644 --- a/src/tools/rust-analyzer/crates/ide/src/goto_definition.rs +++ b/src/tools/rust-analyzer/crates/ide/src/goto_definition.rs @@ -9,7 +9,7 @@ use hir::{ AsAssocItem, AssocItem, CallableKind, FileRange, HasCrate, InFile, ModuleDef, Semantics, sym, }; -use ide_db::{MiniCore, ra_fixture::UpmapFromRaFixture}; +use ide_db::ra_fixture::{RaFixtureConfig, UpmapFromRaFixture}; use ide_db::{ RootDatabase, SymbolKind, base_db::{AnchoredPath, SourceDatabase}, @@ -26,7 +26,7 @@ #[derive(Debug)] pub struct GotoDefinitionConfig<'a> { - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } // Feature: Go to Definition @@ -105,7 +105,7 @@ pub(crate) fn goto_definition( if let Some(token) = ast::String::cast(token.value.clone()) && let Some(original_token) = ast::String::cast(original_token.clone()) && let Some((analysis, fixture_analysis)) = - Analysis::from_ra_fixture(sema, original_token, &token, config.minicore) + Analysis::from_ra_fixture(sema, original_token, &token, &config.ra_fixture) && let Some((virtual_file_id, file_offset)) = fixture_analysis.map_offset_down(offset) { return hir::attach_db_allow_change(&analysis.db, || { @@ -605,11 +605,11 @@ fn expr_to_nav( #[cfg(test)] mod tests { use crate::{GotoDefinitionConfig, fixture}; - use ide_db::{FileRange, MiniCore}; + use ide_db::{FileRange, ra_fixture::RaFixtureConfig}; use itertools::Itertools; const TEST_CONFIG: GotoDefinitionConfig<'_> = - GotoDefinitionConfig { minicore: MiniCore::default() }; + GotoDefinitionConfig { ra_fixture: RaFixtureConfig::default() }; #[track_caller] fn check(#[rust_analyzer::rust_fixture] ra_fixture: &str) { diff --git a/src/tools/rust-analyzer/crates/ide/src/hover.rs b/src/tools/rust-analyzer/crates/ide/src/hover.rs index 958de8930d8a..df1fcecc991f 100644 --- a/src/tools/rust-analyzer/crates/ide/src/hover.rs +++ b/src/tools/rust-analyzer/crates/ide/src/hover.rs @@ -8,11 +8,11 @@ use either::Either; use hir::{DisplayTarget, GenericDef, GenericSubstitution, HasCrate, HasSource, Semantics}; use ide_db::{ - FileRange, FxIndexSet, MiniCore, Ranker, RootDatabase, + FileRange, FxIndexSet, Ranker, RootDatabase, defs::{Definition, IdentClass, NameRefClass, OperatorClass}, famous_defs::FamousDefs, helpers::pick_best_token, - ra_fixture::UpmapFromRaFixture, + ra_fixture::{RaFixtureConfig, UpmapFromRaFixture}, }; use itertools::{Itertools, multizip}; use macros::UpmapFromRaFixture; @@ -44,7 +44,7 @@ pub struct HoverConfig<'a> { pub max_enum_variants_count: Option, pub max_subst_ty_len: SubstTyLen, pub show_drop_glue: bool, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } #[derive(Clone, Debug, PartialEq, Eq)] @@ -221,7 +221,7 @@ fn hover_offset( if let Some(literal) = ast::String::cast(original_token.clone()) && let Some((analysis, fixture_analysis)) = - Analysis::from_ra_fixture(sema, literal.clone(), &literal, config.minicore) + Analysis::from_ra_fixture(sema, literal.clone(), &literal, &config.ra_fixture) { let (virtual_file_id, virtual_offset) = fixture_analysis.map_offset_down(offset)?; return analysis @@ -422,7 +422,7 @@ fn hover_ranged( Either::Left(ast::Expr::Literal(literal)) => { if let Some(literal) = ast::String::cast(literal.token()) && let Some((analysis, fixture_analysis)) = - Analysis::from_ra_fixture(sema, literal.clone(), &literal, config.minicore) + Analysis::from_ra_fixture(sema, literal.clone(), &literal, &config.ra_fixture) { let (virtual_file_id, virtual_range) = fixture_analysis.map_range_down(range)?; return analysis diff --git a/src/tools/rust-analyzer/crates/ide/src/hover/tests.rs b/src/tools/rust-analyzer/crates/ide/src/hover/tests.rs index 7fbbc576dd36..9c53b05539e2 100644 --- a/src/tools/rust-analyzer/crates/ide/src/hover/tests.rs +++ b/src/tools/rust-analyzer/crates/ide/src/hover/tests.rs @@ -1,5 +1,5 @@ use expect_test::{Expect, expect}; -use ide_db::{FileRange, MiniCore, base_db::SourceDatabase}; +use ide_db::{FileRange, base_db::SourceDatabase, ra_fixture::RaFixtureConfig}; use syntax::TextRange; use crate::{ @@ -25,7 +25,7 @@ max_enum_variants_count: Some(5), max_subst_ty_len: super::SubstTyLen::Unlimited, show_drop_glue: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; fn check_hover_no_result(#[rust_analyzer::rust_fixture] ra_fixture: &str) { @@ -3526,9 +3526,6 @@ fn foo_$0test() {} test_id: Path( "foo_test", ), - attr: TestAttr { - ignore: false, - }, }, cfg: None, update_test: UpdateTest { @@ -10707,9 +10704,6 @@ macro_rules! str { test_id: Path( "test", ), - attr: TestAttr { - ignore: false, - }, }, cfg: None, update_test: UpdateTest { @@ -10778,9 +10772,6 @@ macro_rules! expect { test_id: Path( "test", ), - attr: TestAttr { - ignore: false, - }, }, cfg: None, update_test: UpdateTest { @@ -11404,3 +11395,299 @@ pub fn do_something(&self) "#]], ); } + +#[test] +fn test_hover_doc_attr_macro_generated_method_stringify_self_ty() { + check( + r#" +#[rustc_builtin_macro] +macro_rules! concat {} + +#[rustc_builtin_macro] +macro_rules! stringify {} + +macro_rules! bar { + ($SelfT:ident) => { + struct $SelfT; + impl $SelfT { + #[doc = concat!("Do the foo for ", stringify!($SelfT))] + fn foo(&self) {} + } + } +} + +bar!(Bar); + +fn foo() { let bar = Bar; bar.fo$0o(); } +"#, + expect![[r#" + *foo* + + ```rust + ra_test_fixture::Bar + ``` + + ```rust + fn foo(&self) + ``` + + --- + + Do the foo for Bar + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_macro_argument_expr_issue_7688() { + check( + r#" +#[rustc_builtin_macro] +macro_rules! concat {} + +macro_rules! doc_comment { + ($x:expr, $($tt:tt)*) => { + #[doc = $x] + $($tt)* + }; +} + +doc_comment! { + concat!("Hello", " world"), + struct Ba$0r; +} +"#, + expect![[r#" + *Bar* + + ```rust + ra_test_fixture + ``` + + ```rust + struct Bar + ``` + + --- + + size = 0, align = 1, no Drop + + --- + + Hello world + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_concat_macro() { + check( + r#" +#[rustc_builtin_macro] +macro_rules! concat {} + +#[doc = concat!("Hello", " ", "World")] +struct Ba$0r; +"#, + expect![[r#" + *Bar* + + ```rust + ra_test_fixture + ``` + + ```rust + struct Bar + ``` + + --- + + size = 0, align = 1, no Drop + + --- + + Hello World + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_include_str_macro() { + check( + r#" +//- /main.rs +#[rustc_builtin_macro] +macro_rules! include_str {} + +#[doc = include_str!("docs.md")] +struct Ba$0r; + +//- /docs.md +Included docs from file. +Multiple lines of docs. +"#, + expect![[r#" + *Bar* + + ```rust + ra_test_fixture + ``` + + ```rust + struct Bar + ``` + + --- + + size = 0, align = 1, no Drop + + --- + + Included docs from file. + Multiple lines of docs. + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_user_macro_returning_string() { + check( + r#" +macro_rules! doc_str { + () => { "Documentation from macro" }; +} + +#[doc = doc_str!()] +struct Ba$0r; +"#, + expect![[r#" + *Bar* + + ```rust + ra_test_fixture + ``` + + ```rust + struct Bar + ``` + + --- + + size = 0, align = 1, no Drop + + --- + + Documentation from macro + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_mixed_literal_and_macro() { + check( + r#" +#[rustc_builtin_macro] +macro_rules! concat {} + +/// First line +#[doc = concat!("Second", " line")] +struct Ba$0r; +"#, + expect![[r#" + *Bar* + + ```rust + ra_test_fixture + ``` + + ```rust + struct Bar + ``` + + --- + + size = 0, align = 1, no Drop + + --- + + First line + Second line + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_field_with_macro() { + check( + r#" +#[rustc_builtin_macro] +macro_rules! concat {} + +struct Bar { + #[doc = concat!("field", " docs")] + ba$0z: i32, +} +"#, + expect![[r#" + *baz* + + ```rust + ra_test_fixture::Bar + ``` + + ```rust + baz: i32 + ``` + + --- + + size = 4, align = 4, offset = 0, no Drop + + --- + + field docs + "#]], + ); +} + +#[test] +fn test_hover_doc_attr_macro_on_outlined_mod() { + // Outer doc-macro on `mod foo;` resolves from inside the module's scope + // (matching rustc behavior), and combines with inner `//!` docs from the module file. + check( + r#" +//- /main.rs +mod mac { + macro_rules! doc_str { + () => { "expanded from macro" }; + } + pub(crate) use doc_str; +} + +/// plain outer doc +#[doc = super::mac::doc_str!()] +mod foo$0; + +//- /foo.rs +//! inner module docs +pub struct Bar; +"#, + expect![[r#" + *foo* + + ```rust + ra_test_fixture + ``` + + ```rust + mod foo + ``` + + --- + + plain outer doc + expanded from macro + inner module docs + "#]], + ); +} diff --git a/src/tools/rust-analyzer/crates/ide/src/inlay_hints.rs b/src/tools/rust-analyzer/crates/ide/src/inlay_hints.rs index a58dc6f03055..f51d7f520786 100644 --- a/src/tools/rust-analyzer/crates/ide/src/inlay_hints.rs +++ b/src/tools/rust-analyzer/crates/ide/src/inlay_hints.rs @@ -9,7 +9,8 @@ HirDisplay, HirDisplayError, HirWrite, InRealFile, ModuleDef, ModuleDefId, Semantics, sym, }; use ide_db::{ - FileRange, MiniCore, RootDatabase, famous_defs::FamousDefs, text_edit::TextEditBuilder, + FileRange, RootDatabase, famous_defs::FamousDefs, ra_fixture::RaFixtureConfig, + text_edit::TextEditBuilder, }; use ide_db::{FxHashSet, text_edit::TextEdit}; use itertools::Itertools; @@ -302,6 +303,7 @@ fn hints( pub struct InlayHintsConfig<'a> { pub render_colons: bool, pub type_hints: bool, + pub type_hints_placement: TypeHintsPlacement, pub sized_bound: bool, pub discriminant_hints: DiscriminantHints, pub parameter_hints: bool, @@ -328,7 +330,13 @@ pub struct InlayHintsConfig<'a> { pub max_length: Option, pub closing_brace_hints_min_lines: Option, pub fields_to_resolve: InlayFieldsToResolve, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, +} + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub enum TypeHintsPlacement { + Inline, + EndOfLine, } impl InlayHintsConfig<'_> { @@ -899,7 +907,7 @@ mod tests { use expect_test::Expect; use hir::ClosureStyle; - use ide_db::MiniCore; + use ide_db::ra_fixture::RaFixtureConfig; use itertools::Itertools; use test_utils::extract_annotations; @@ -907,12 +915,15 @@ mod tests { use crate::inlay_hints::{AdjustmentHints, AdjustmentHintsMode}; use crate::{LifetimeElisionHints, fixture, inlay_hints::InlayHintsConfig}; - use super::{ClosureReturnTypeHints, GenericParameterHints, InlayFieldsToResolve}; + use super::{ + ClosureReturnTypeHints, GenericParameterHints, InlayFieldsToResolve, TypeHintsPlacement, + }; pub(super) const DISABLED_CONFIG: InlayHintsConfig<'_> = InlayHintsConfig { discriminant_hints: DiscriminantHints::Never, render_colons: false, type_hints: false, + type_hints_placement: TypeHintsPlacement::Inline, parameter_hints: false, parameter_hints_for_missing_arguments: false, sized_bound: false, @@ -942,10 +953,11 @@ mod tests { implicit_drop_hints: false, implied_dyn_trait_hints: false, range_exclusive_hints: false, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; pub(super) const TEST_CONFIG: InlayHintsConfig<'_> = InlayHintsConfig { type_hints: true, + type_hints_placement: TypeHintsPlacement::Inline, parameter_hints: true, chaining_hints: true, closure_return_type_hints: ClosureReturnTypeHints::WithBlock, diff --git a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/bind_pat.rs b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/bind_pat.rs index caf7cc714d33..b901c6b67d3e 100644 --- a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/bind_pat.rs +++ b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/bind_pat.rs @@ -8,10 +8,12 @@ use itertools::Itertools; use syntax::{ + TextRange, ast::{self, AstNode, HasGenericArgs, HasName}, match_ast, }; +use super::TypeHintsPlacement; use crate::{ InlayHint, InlayHintPosition, InlayHintsConfig, InlayKind, inlay_hints::{closure_has_block_body, label_of_ty, ty_to_text_edit}, @@ -29,6 +31,7 @@ pub(super) fn hints( } let parent = pat.syntax().parent()?; + let mut enclosing_let_stmt = None; let type_ascriptable = match_ast! { match parent { ast::Param(it) => { @@ -41,6 +44,7 @@ pub(super) fn hints( Some(it.colon_token()) }, ast::LetStmt(it) => { + enclosing_let_stmt = Some(it.clone()); if config.hide_closure_initialization_hints && let Some(ast::Expr::ClosureExpr(closure)) = it.initializer() && closure_has_block_body(&closure) { @@ -101,16 +105,26 @@ pub(super) fn hints( Some(name) => name.syntax().text_range(), None => pat.syntax().text_range(), }; + let mut range = match type_ascriptable { + Some(Some(t)) => text_range.cover(t.text_range()), + _ => text_range, + }; + + let mut pad_left = !render_colons; + if matches!(config.type_hints_placement, TypeHintsPlacement::EndOfLine) + && let Some(let_stmt) = enclosing_let_stmt + { + let stmt_range = let_stmt.syntax().text_range(); + range = TextRange::new(range.start(), stmt_range.end()); + pad_left = true; + } acc.push(InlayHint { - range: match type_ascriptable { - Some(Some(t)) => text_range.cover(t.text_range()), - _ => text_range, - }, + range, kind: InlayKind::Type, label, text_edit, position: InlayHintPosition::After, - pad_left: !render_colons, + pad_left, pad_right: false, resolve_parent: Some(pat.syntax().text_range()), }); @@ -182,6 +196,7 @@ mod tests { use crate::{ClosureReturnTypeHints, fixture, inlay_hints::InlayHintsConfig}; + use super::TypeHintsPlacement; use crate::inlay_hints::tests::{ DISABLED_CONFIG, TEST_CONFIG, check, check_edit, check_expect, check_no_edit, check_with_config, @@ -204,6 +219,76 @@ fn main() { ); } + #[test] + fn type_hints_end_of_line_placement() { + let mut config = InlayHintsConfig { type_hints: true, ..DISABLED_CONFIG }; + config.type_hints_placement = TypeHintsPlacement::EndOfLine; + check_expect( + config, + r#" +fn main() { + let foo = 92_i32; +} + "#, + expect![[r#" + [ + ( + 20..33, + [ + "i32", + ], + ), + ] + "#]], + ); + } + + #[test] + fn type_hints_end_of_line_placement_chain_expr() { + let mut config = InlayHintsConfig { type_hints: true, ..DISABLED_CONFIG }; + config.type_hints_placement = TypeHintsPlacement::EndOfLine; + check_expect( + config, + r#" +fn main() { + struct Builder; + impl Builder { + fn iter(self) -> Builder { Builder } + fn map(self) -> Builder { Builder } + } + fn make() -> Builder { Builder } + + let foo = make() + .iter() + .map(); +} +"#, + expect![[r#" + [ + ( + 192..236, + [ + InlayHintLabelPart { + text: "Builder", + linked_location: Some( + Computed( + FileRangeWrapper { + file_id: FileId( + 0, + ), + range: 23..30, + }, + ), + ), + tooltip: "", + }, + ], + ), + ] + "#]], + ); + } + #[test] fn type_hints_bindings_after_at() { check_types( diff --git a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/chaining.rs b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/chaining.rs index cf3149c9461b..4b06f83971b2 100644 --- a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/chaining.rs +++ b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/chaining.rs @@ -2,13 +2,13 @@ use hir::DisplayTarget; use ide_db::famous_defs::FamousDefs; use syntax::{ - Direction, NodeOrToken, SyntaxKind, T, + Direction, NodeOrToken, SyntaxKind, T, TextRange, ast::{self, AstNode}, }; use crate::{InlayHint, InlayHintPosition, InlayHintsConfig, InlayKind}; -use super::label_of_ty; +use super::{TypeHintsPlacement, label_of_ty}; pub(super) fn hints( acc: &mut Vec, @@ -40,13 +40,14 @@ pub(super) fn hints( // Chaining can be defined as an expression whose next sibling tokens are newline and dot // Ignoring extra whitespace and comments - let next = tokens.next()?.kind(); - if next == SyntaxKind::WHITESPACE { - let mut next_next = tokens.next()?.kind(); - while next_next == SyntaxKind::WHITESPACE { - next_next = tokens.next()?.kind(); + let next_token = tokens.next()?; + if next_token.kind() == SyntaxKind::WHITESPACE { + let newline_token = next_token; + let mut next_next = tokens.next()?; + while next_next.kind() == SyntaxKind::WHITESPACE { + next_next = tokens.next()?; } - if next_next == T![.] { + if next_next.kind() == T![.] { let ty = sema.type_of_expr(desc_expr)?.original; if ty.is_unknown() { return None; @@ -58,8 +59,18 @@ pub(super) fn hints( return None; } let label = label_of_ty(famous_defs, config, &ty, display_target)?; + let range = { + let mut range = expr.syntax().text_range(); + if config.type_hints_placement == TypeHintsPlacement::EndOfLine { + range = TextRange::new( + range.start(), + newline_token.text_range().start().max(range.end()), + ); + } + range + }; acc.push(InlayHint { - range: expr.syntax().text_range(), + range, kind: InlayKind::Chaining, label, text_edit: None, @@ -79,7 +90,7 @@ mod tests { use ide_db::text_edit::{TextRange, TextSize}; use crate::{ - InlayHintsConfig, fixture, + InlayHintsConfig, TypeHintsPlacement, fixture, inlay_hints::{ LazyProperty, tests::{DISABLED_CONFIG, TEST_CONFIG, check_expect, check_with_config}, @@ -686,4 +697,80 @@ fn main() { "#]], ); } + + #[test] + fn chaining_hints_end_of_line_placement() { + check_expect( + InlayHintsConfig { + chaining_hints: true, + type_hints_placement: TypeHintsPlacement::EndOfLine, + ..DISABLED_CONFIG + }, + r#" +fn main() { + let baz = make() + .into_bar() + .into_baz(); +} + +struct Foo; +struct Bar; +struct Baz; + +impl Foo { + fn into_bar(self) -> Bar { Bar } +} + +impl Bar { + fn into_baz(self) -> Baz { Baz } +} + +fn make() -> Foo { + Foo +} +"#, + expect![[r#" + [ + ( + 26..52, + [ + InlayHintLabelPart { + text: "Bar", + linked_location: Some( + Computed( + FileRangeWrapper { + file_id: FileId( + 0, + ), + range: 96..99, + }, + ), + ), + tooltip: "", + }, + ], + ), + ( + 26..32, + [ + InlayHintLabelPart { + text: "Foo", + linked_location: Some( + Computed( + FileRangeWrapper { + file_id: FileId( + 0, + ), + range: 84..87, + }, + ), + ), + tooltip: "", + }, + ], + ), + ] + "#]], + ); + } } diff --git a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/param_name.rs b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/param_name.rs index 08588bbed090..8dddf9d37e4f 100644 --- a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/param_name.rs +++ b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/param_name.rs @@ -37,8 +37,9 @@ pub(super) fn hints( let hints = callable .params() .into_iter() - .zip(arg_list.args()) + .zip(arg_list.args_maybe_empty()) .filter_map(|(p, arg)| { + let arg = arg?; // Only annotate hints for expressions that exist in the original file let range = sema.original_range_opt(arg.syntax())?; if range.file_id != file_id { @@ -561,6 +562,19 @@ fn main() { ) } + #[test] + fn param_name_hints_show_after_empty_arg() { + check_params( + r#"pub fn test(a: i32, b: i32, c: i32) {} +fn main() { + test(, 2,); + //^ b + test(, , 3); + //^ c +}"#, + ) + } + #[test] fn function_call_parameter_hint() { check_params( diff --git a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/ra_fixture.rs b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/ra_fixture.rs index bee18416424c..701c8a8612e9 100644 --- a/src/tools/rust-analyzer/crates/ide/src/inlay_hints/ra_fixture.rs +++ b/src/tools/rust-analyzer/crates/ide/src/inlay_hints/ra_fixture.rs @@ -16,7 +16,7 @@ pub(super) fn hints( let file_id = file_id.file_id(sema.db); let literal = ast::String::cast(literal.token())?; let (analysis, fixture_analysis) = - Analysis::from_ra_fixture(sema, literal.clone(), &literal, config.minicore)?; + Analysis::from_ra_fixture(sema, literal.clone(), &literal, &config.ra_fixture)?; for virtual_file_id in fixture_analysis.files() { acc.extend( analysis diff --git a/src/tools/rust-analyzer/crates/ide/src/lib.rs b/src/tools/rust-analyzer/crates/ide/src/lib.rs index 81a771fec89e..270998cdf751 100644 --- a/src/tools/rust-analyzer/crates/ide/src/lib.rs +++ b/src/tools/rust-analyzer/crates/ide/src/lib.rs @@ -63,15 +63,16 @@ use cfg::CfgOptions; use fetch_crates::CrateInfo; use hir::{ChangeWithProcMacros, EditionedFileId, crate_def_map, sym}; +use ide_db::base_db::relevant_crates; +use ide_db::ra_fixture::RaFixtureAnalysis; use ide_db::{ FxHashMap, FxIndexSet, LineIndexDatabase, base_db::{ - CrateOrigin, CrateWorkspaceData, Env, FileSet, RootQueryDb, SourceDatabase, VfsPath, + CrateOrigin, CrateWorkspaceData, Env, FileSet, SourceDatabase, VfsPath, salsa::{Cancelled, Database}, }, prime_caches, symbol_index, }; -use ide_db::{MiniCore, ra_fixture::RaFixtureAnalysis}; use macros::UpmapFromRaFixture; use syntax::{AstNode, SourceFile, ast}; use triomphe::Arc; @@ -96,7 +97,7 @@ AdjustmentHints, AdjustmentHintsMode, ClosureReturnTypeHints, DiscriminantHints, GenericParameterHints, InlayFieldsToResolve, InlayHint, InlayHintLabel, InlayHintLabelPart, InlayHintPosition, InlayHintsConfig, InlayKind, InlayTooltip, LazyProperty, - LifetimeElisionHints, + LifetimeElisionHints, TypeHintsPlacement, }, join_lines::JoinLinesConfig, markup::Markup, @@ -135,6 +136,7 @@ label::Label, line_index::{LineCol, LineIndex}, prime_caches::ParallelPrimeCachesProgress, + ra_fixture::RaFixtureConfig, search::{ReferenceCategory, SearchScope}, source_change::{FileSystemEdit, SnippetEdit, SourceChange}, symbol_index::Query, @@ -289,9 +291,9 @@ pub(crate) fn from_ra_fixture( sema: &Semantics<'_, RootDatabase>, literal: ast::String, expanded: &ast::String, - minicore: MiniCore<'_>, + config: &RaFixtureConfig<'_>, ) -> Option<(Analysis, RaFixtureAnalysis)> { - Self::from_ra_fixture_with_on_cursor(sema, literal, expanded, minicore, &mut |_| {}) + Self::from_ra_fixture_with_on_cursor(sema, literal, expanded, config, &mut |_| {}) } /// Like [`Analysis::from_ra_fixture()`], but also calls `on_cursor` with the cursor position. @@ -299,11 +301,11 @@ pub(crate) fn from_ra_fixture_with_on_cursor( sema: &Semantics<'_, RootDatabase>, literal: ast::String, expanded: &ast::String, - minicore: MiniCore<'_>, + config: &RaFixtureConfig<'_>, on_cursor: &mut dyn FnMut(TextRange), ) -> Option<(Analysis, RaFixtureAnalysis)> { let analysis = - RaFixtureAnalysis::analyze_ra_fixture(sema, literal, expanded, minicore, on_cursor)?; + RaFixtureAnalysis::analyze_ra_fixture(sema, literal, expanded, config, on_cursor)?; Some((Analysis { db: analysis.db.clone() }, analysis)) } @@ -341,7 +343,7 @@ pub fn parse(&self, file_id: FileId) -> Cancellable { self.with_db(|db| { let editioned_file_id_wrapper = EditionedFileId::current_edition(&self.db, file_id); - db.parse(editioned_file_id_wrapper).tree() + editioned_file_id_wrapper.parse(db).tree() }) } @@ -369,7 +371,7 @@ pub fn extend_selection(&self, frange: FileRange) -> Cancellable { pub fn matching_brace(&self, position: FilePosition) -> Cancellable> { self.with_db(|db| { let file_id = EditionedFileId::current_edition(&self.db, position.file_id); - let parse = db.parse(file_id); + let parse = file_id.parse(db); let file = parse.tree(); matching_brace::matching_brace(&file, position.offset) }) @@ -412,7 +414,7 @@ pub fn discover_tests_in_file(&self, file_id: FileId) -> Cancellable Cancellable> { + pub fn view_crate_graph(&self, full: bool) -> Cancellable { self.with_db(|db| view_crate_graph::view_crate_graph(db, full)) } @@ -430,7 +432,7 @@ pub fn join_lines(&self, config: &JoinLinesConfig, frange: FileRange) -> Cancell self.with_db(|db| { let editioned_file_id_wrapper = EditionedFileId::current_edition(&self.db, frange.file_id); - let parse = db.parse(editioned_file_id_wrapper); + let parse = editioned_file_id_wrapper.parse(db); join_lines::join_lines(config, &parse.tree(), frange.range) }) } @@ -471,7 +473,7 @@ pub fn file_structure( // FIXME: Edition self.with_db(|db| { let editioned_file_id_wrapper = EditionedFileId::current_edition(&self.db, file_id); - let source_file = db.parse(editioned_file_id_wrapper).tree(); + let source_file = editioned_file_id_wrapper.parse(db).tree(); file_structure::file_structure(&source_file, config) }) } @@ -499,11 +501,14 @@ pub fn inlay_hints_resolve( } /// Returns the set of folding ranges. - pub fn folding_ranges(&self, file_id: FileId) -> Cancellable> { + pub fn folding_ranges(&self, file_id: FileId, collapsed_text: bool) -> Cancellable> { self.with_db(|db| { let editioned_file_id_wrapper = EditionedFileId::current_edition(&self.db, file_id); - folding_ranges::folding_ranges(&db.parse(editioned_file_id_wrapper).tree()) + folding_ranges::folding_ranges( + &editioned_file_id_wrapper.parse(db).tree(), + collapsed_text, + ) }) } @@ -654,7 +659,7 @@ pub fn transitive_rev_deps(&self, crate_id: Crate) -> Cancellable> { /// Returns crates that this file *might* belong to. pub fn relevant_crates_for(&self, file_id: FileId) -> Cancellable> { - self.with_db(|db| db.relevant_crates(file_id).iter().copied().collect()) + self.with_db(|db| relevant_crates(db, file_id).to_vec()) } /// Returns the edition of the given crate. diff --git a/src/tools/rust-analyzer/crates/ide/src/matching_brace.rs b/src/tools/rust-analyzer/crates/ide/src/matching_brace.rs index b2b91d6e3cf3..5079b0c4f917 100644 --- a/src/tools/rust-analyzer/crates/ide/src/matching_brace.rs +++ b/src/tools/rust-analyzer/crates/ide/src/matching_brace.rs @@ -17,25 +17,37 @@ pub(crate) fn matching_brace(file: &SourceFile, offset: TextSize) -> Option { const BRACES: &[SyntaxKind] = &[T!['{'], T!['}'], T!['['], T![']'], T!['('], T![')'], T![<], T![>], T![|], T![|]]; - let (brace_token, brace_idx) = file - .syntax() - .token_at_offset(offset) + let current = file.syntax().token_at_offset(offset); + if let Some((brace_token, brace_idx)) = current + .clone() .filter_map(|node| { let idx = BRACES.iter().position(|&brace| brace == node.kind())?; Some((node, idx)) }) - .last()?; - let parent = brace_token.parent()?; - if brace_token.kind() == T![|] && !ast::ParamList::can_cast(parent.kind()) { - cov_mark::hit!(pipes_not_braces); - return None; + .last() + { + let parent = brace_token.parent()?; + if brace_token.kind() == T![|] && !ast::ParamList::can_cast(parent.kind()) { + cov_mark::hit!(pipes_not_braces); + return None; + } + let matching_kind = BRACES[brace_idx ^ 1]; + let matching_node = parent + .children_with_tokens() + .filter_map(|it| it.into_token()) + .find(|node| node.kind() == matching_kind && node != &brace_token)?; + Some(matching_node.text_range().start()) + } else { + // when the offset is not at a brace, find first parent + current.last()?.parent_ancestors().find_map(|x| { + x.children_with_tokens() + .filter_map(|it| it.into_token()) + // with ending brace + .filter(|node| BRACES.contains(&node.kind())) + .last() + .map(|x| x.text_range().start()) + }) } - let matching_kind = BRACES[brace_idx ^ 1]; - let matching_node = parent - .children_with_tokens() - .filter_map(|it| it.into_token()) - .find(|node| node.kind() == matching_kind && node != &brace_token)?; - Some(matching_node.text_range().start()) } #[cfg(test)] @@ -64,6 +76,14 @@ fn do_check(before: &str, after: &str) { "fn func(x) { return (2 * (x + 3)$0) + 5;}", "fn func(x) { return $0(2 * (x + 3)) + 5;}", ); + do_check( + "fn func(x) { return (2 * (x $0+ 3)) + 5;}", + "fn func(x) { return (2 * (x + 3$0)) + 5;}", + ); + do_check( + "fn func(x) { re$0turn (2 * (x + 3)) + 5;}", + "fn func(x) { return (2 * (x + 3)) + 5;$0}", + ); { cov_mark::check!(pipes_not_braces); diff --git a/src/tools/rust-analyzer/crates/ide/src/navigation_target.rs b/src/tools/rust-analyzer/crates/ide/src/navigation_target.rs index 92020321f453..99f8634bcb05 100644 --- a/src/tools/rust-analyzer/crates/ide/src/navigation_target.rs +++ b/src/tools/rust-analyzer/crates/ide/src/navigation_target.rs @@ -11,7 +11,7 @@ }; use ide_db::{ FileId, FileRange, RootDatabase, SymbolKind, - base_db::{CrateOrigin, LangCrateOrigin, RootQueryDb}, + base_db::{CrateOrigin, LangCrateOrigin, all_crates}, defs::{Definition, find_std_module}, documentation::{Documentation, HasDocs}, famous_defs::FamousDefs, @@ -861,8 +861,7 @@ fn try_to_nav( sema: &Semantics<'_, RootDatabase>, ) -> Option> { let db = sema.db; - let krate = db - .all_crates() + let krate = all_crates(db) .iter() .copied() .find(|&krate| matches!(krate.data(db).origin, CrateOrigin::Lang(LangCrateOrigin::Std))) diff --git a/src/tools/rust-analyzer/crates/ide/src/parent_module.rs b/src/tools/rust-analyzer/crates/ide/src/parent_module.rs index 96d829d1260b..509ec2ab4051 100644 --- a/src/tools/rust-analyzer/crates/ide/src/parent_module.rs +++ b/src/tools/rust-analyzer/crates/ide/src/parent_module.rs @@ -1,7 +1,7 @@ use hir::{Semantics, crate_def_map}; use ide_db::{ FileId, FilePosition, RootDatabase, - base_db::{Crate, RootQueryDb}, + base_db::{Crate, relevant_crates}, }; use itertools::Itertools; use syntax::{ @@ -53,7 +53,7 @@ pub(crate) fn parent_module(db: &RootDatabase, position: FilePosition) -> Vec Vec { - db.relevant_crates(file_id) + relevant_crates(db, file_id) .iter() .copied() .filter(|&crate_id| { diff --git a/src/tools/rust-analyzer/crates/ide/src/references.rs b/src/tools/rust-analyzer/crates/ide/src/references.rs index 9392651c1794..0288099bbcc2 100644 --- a/src/tools/rust-analyzer/crates/ide/src/references.rs +++ b/src/tools/rust-analyzer/crates/ide/src/references.rs @@ -19,10 +19,10 @@ use hir::{PathResolution, Semantics}; use ide_db::{ - FileId, MiniCore, RootDatabase, + FileId, RootDatabase, defs::{Definition, NameClass, NameRefClass}, helpers::pick_best_token, - ra_fixture::UpmapFromRaFixture, + ra_fixture::{RaFixtureConfig, UpmapFromRaFixture}, search::{ReferenceCategory, SearchScope, UsageSearchResult}, }; use itertools::Itertools; @@ -90,7 +90,7 @@ pub struct Declaration { #[derive(Debug)] pub struct FindAllRefsConfig<'a> { pub search_scope: Option, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } /// Find all references to the item at the given position. @@ -179,7 +179,7 @@ pub(crate) fn find_all_refs( if let Some(token) = syntax.token_at_offset(position.offset).left_biased() && let Some(token) = ast::String::cast(token.clone()) && let Some((analysis, fixture_analysis)) = - Analysis::from_ra_fixture(sema, token.clone(), &token, config.minicore) + Analysis::from_ra_fixture(sema, token.clone(), &token, &config.ra_fixture) && let Some((virtual_file_id, file_offset)) = fixture_analysis.map_offset_down(position.offset) { @@ -462,7 +462,7 @@ fn handle_control_flow_keywords( mod tests { use expect_test::{Expect, expect}; use hir::EditionedFileId; - use ide_db::{FileId, MiniCore, RootDatabase}; + use ide_db::{FileId, RootDatabase, ra_fixture::RaFixtureConfig}; use stdx::format_to; use crate::{SearchScope, fixture, references::FindAllRefsConfig}; @@ -1567,7 +1567,7 @@ fn check_with_scope( let (analysis, pos) = fixture::position(ra_fixture); let config = FindAllRefsConfig { search_scope: search_scope.map(|it| it(&analysis.db)), - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; let refs = analysis.find_all_refs(pos, &config).unwrap().unwrap(); diff --git a/src/tools/rust-analyzer/crates/ide/src/runnables.rs b/src/tools/rust-analyzer/crates/ide/src/runnables.rs index a0a6a245592c..3b472390d2f4 100644 --- a/src/tools/rust-analyzer/crates/ide/src/runnables.rs +++ b/src/tools/rust-analyzer/crates/ide/src/runnables.rs @@ -3,12 +3,12 @@ use arrayvec::ArrayVec; use ast::HasName; use cfg::{CfgAtom, CfgExpr}; -use hir::{AsAssocItem, HasAttrs, HasCrate, HasSource, Semantics, Symbol, db::HirDatabase, sym}; +use hir::{AsAssocItem, HasAttrs, HasCrate, HasSource, Semantics, Symbol, sym}; use ide_assists::utils::{has_test_related_attribute, test_related_attribute_syn}; +use ide_db::base_db::all_crates; use ide_db::impl_empty_upmap_from_ra_fixture; use ide_db::{ FilePosition, FxHashMap, FxIndexMap, FxIndexSet, RootDatabase, SymbolKind, - base_db::RootQueryDb, defs::Definition, helpers::visit_file_defs, search::{FileReferenceNode, SearchScope}, @@ -55,7 +55,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { #[derive(Debug, Clone, Hash, PartialEq, Eq)] pub enum RunnableKind { TestMod { path: String }, - Test { test_id: TestId, attr: TestAttr }, + Test { test_id: TestId }, Bench { test_id: TestId }, DocTest { test_id: TestId }, Bin, @@ -334,8 +334,7 @@ pub(crate) fn runnable_fn( }; if def.is_test(sema.db) { - let attr = TestAttr::from_fn(sema.db, def); - RunnableKind::Test { test_id: test_id(), attr } + RunnableKind::Test { test_id: test_id() } } else if def.is_bench(sema.db) { RunnableKind::Bench { test_id: test_id() } } else { @@ -506,7 +505,7 @@ fn module_def_doctest(sema: &Semantics<'_, RootDatabase>, def: Definition) -> Op let krate = def.krate(db); let edition = krate.map(|it| it.edition(db)).unwrap_or(Edition::CURRENT); let display_target = krate - .unwrap_or_else(|| (*db.all_crates().last().expect("no crate graph present")).into()) + .unwrap_or_else(|| (*all_crates(db).last().expect("no crate graph present")).into()) .to_display_target(db); if !has_runnable_doc_test(db, &attrs) { return None; @@ -558,17 +557,6 @@ fn module_def_doctest(sema: &Semantics<'_, RootDatabase>, def: Definition) -> Op Some(res) } -#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)] -pub struct TestAttr { - pub ignore: bool, -} - -impl TestAttr { - fn from_fn(db: &dyn HirDatabase, fn_def: hir::Function) -> TestAttr { - TestAttr { ignore: fn_def.is_ignore(db) } - } -} - fn has_runnable_doc_test(db: &RootDatabase, attrs: &hir::AttrsWithOwner) -> bool { const RUSTDOC_FENCES: [&str; 2] = ["```", "~~~"]; const RUSTDOC_CODE_BLOCK_ATTRIBUTES_RUNNABLE: &[&str] = diff --git a/src/tools/rust-analyzer/crates/ide/src/signature_help.rs b/src/tools/rust-analyzer/crates/ide/src/signature_help.rs index 9eb01b12f2bd..cf796b27150e 100644 --- a/src/tools/rust-analyzer/crates/ide/src/signature_help.rs +++ b/src/tools/rust-analyzer/crates/ide/src/signature_help.rs @@ -1975,8 +1975,8 @@ trait Sub: Super + Super { fn f() -> impl Sub<$0 "#, expect![[r#" - trait Sub - ^^^^^^^^^^^ --------- + trait Sub + ^^^^^^^^^ ----------- "#]], ); } diff --git a/src/tools/rust-analyzer/crates/ide/src/static_index.rs b/src/tools/rust-analyzer/crates/ide/src/static_index.rs index aba6b64f977a..4b2c9ceef9ff 100644 --- a/src/tools/rust-analyzer/crates/ide/src/static_index.rs +++ b/src/tools/rust-analyzer/crates/ide/src/static_index.rs @@ -4,11 +4,12 @@ use arrayvec::ArrayVec; use hir::{Crate, Module, Semantics, db::HirDatabase}; use ide_db::{ - FileId, FileRange, FxHashMap, FxHashSet, MiniCore, RootDatabase, - base_db::{RootQueryDb, SourceDatabase, VfsPath}, + FileId, FileRange, FxHashMap, FxHashSet, RootDatabase, + base_db::{SourceDatabase, VfsPath}, defs::{Definition, IdentClass}, documentation::Documentation, famous_defs::FamousDefs, + ra_fixture::RaFixtureConfig, }; use syntax::{AstNode, SyntaxNode, SyntaxToken, TextRange}; @@ -16,7 +17,7 @@ use crate::{ Analysis, Fold, HoverConfig, HoverResult, InlayHint, InlayHintsConfig, TryToNav, hover::{SubstTyLen, hover_for_definition}, - inlay_hints::{AdjustmentHintsMode, InlayFieldsToResolve}, + inlay_hints::{AdjustmentHintsMode, InlayFieldsToResolve, TypeHintsPlacement}, moniker::{MonikerResult, SymbolInformationKind, def_to_kind, def_to_moniker}, parent_module::crates_for, }; @@ -123,16 +124,8 @@ fn documentation_for_definition( _ => None, }; - def.docs( - sema.db, - famous_defs.as_ref(), - def.krate(sema.db) - .unwrap_or_else(|| { - (*sema.db.all_crates().last().expect("no crate graph present")).into() - }) - .to_display_target(sema.db), - ) - .map(Documentation::into_owned) + def.docs(sema.db, famous_defs.as_ref(), def.krate(sema.db)?.to_display_target(sema.db)) + .map(Documentation::into_owned) } // FIXME: This is a weird function @@ -159,7 +152,7 @@ pub enum VendoredLibrariesConfig<'a> { impl StaticIndex<'_> { fn add_file(&mut self, file_id: FileId) { let current_crate = crates_for(self.db, file_id).pop().map(Into::into); - let folds = self.analysis.folding_ranges(file_id).unwrap(); + let folds = self.analysis.folding_ranges(file_id, true).unwrap(); let inlay_hints = self .analysis .inlay_hints( @@ -167,6 +160,7 @@ fn add_file(&mut self, file_id: FileId) { render_colons: true, discriminant_hints: crate::DiscriminantHints::Fieldless, type_hints: true, + type_hints_placement: TypeHintsPlacement::Inline, sized_bound: false, parameter_hints: true, parameter_hints_for_missing_arguments: false, @@ -196,7 +190,7 @@ fn add_file(&mut self, file_id: FileId) { closing_brace_hints_min_lines: Some(25), fields_to_resolve: InlayFieldsToResolve::empty(), range_exclusive_hints: false, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }, file_id, None, @@ -225,7 +219,7 @@ fn add_file(&mut self, file_id: FileId) { max_enum_variants_count: Some(5), max_subst_ty_len: SubstTyLen::Unlimited, show_drop_glue: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; let mut result = StaticIndexedFile { file_id, inlay_hints, folds, tokens: vec![] }; diff --git a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting.rs b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting.rs index 217b13b4ef95..9fd3f005ec70 100644 --- a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting.rs +++ b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting.rs @@ -17,7 +17,7 @@ use hir::{ DefWithBody, EditionedFileId, ExpressionStoreOwner, InFile, InRealFile, MacroKind, Semantics, }; -use ide_db::{FxHashMap, FxHashSet, MiniCore, Ranker, RootDatabase, SymbolKind}; +use ide_db::{FxHashMap, FxHashSet, Ranker, RootDatabase, SymbolKind, ra_fixture::RaFixtureConfig}; use syntax::{ AstNode, AstToken, NodeOrToken, SyntaxKind::*, @@ -65,7 +65,7 @@ pub struct HighlightConfig<'a> { pub macro_bang: bool, /// Whether to highlight unresolved things be their syntax pub syntactic_name_ref_highlighting: bool, - pub minicore: MiniCore<'a>, + pub ra_fixture: RaFixtureConfig<'a>, } // Feature: Semantic Syntax Highlighting diff --git a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/html.rs b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/html.rs index 74567e82139f..423c0c349cd2 100644 --- a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/html.rs +++ b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/html.rs @@ -1,7 +1,7 @@ //! Renders a bit of code as HTML. use hir::Semantics; -use ide_db::MiniCore; +use ide_db::ra_fixture::RaFixtureConfig; use oorandom::Rand32; use stdx::format_to; use syntax::AstNode; @@ -69,7 +69,7 @@ pub(crate) fn highlight_as_html(db: &RootDatabase, file_id: FileId, rainbow: boo inject_doc_comment: true, macro_bang: true, syntactic_name_ref_highlighting: false, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }, file_id, rainbow, diff --git a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/inject.rs b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/inject.rs index 74a8d93dfe82..6afe5681a9b5 100644 --- a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/inject.rs +++ b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/inject.rs @@ -27,7 +27,7 @@ pub(super) fn ra_fixture( sema, literal.clone(), expanded, - config.minicore, + &config.ra_fixture, &mut |range| { hl.add(HlRange { range, @@ -56,7 +56,7 @@ pub(super) fn ra_fixture( macro_bang: config.macro_bang, // What if there is a fixture inside a fixture? It's fixtures all the way down. // (In fact, we have a fixture inside a fixture in our test suite!) - minicore: config.minicore, + ra_fixture: config.ra_fixture, }, tmp_file_id, ) @@ -186,7 +186,7 @@ pub(super) fn doc_comment( specialize_operator: config.operator, inject_doc_comment: config.inject_doc_comment, macro_bang: config.macro_bang, - minicore: config.minicore, + ra_fixture: config.ra_fixture, }, tmp_file_id, None, diff --git a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/test_data/highlight_doctest.html b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/test_data/highlight_doctest.html index ce9ec7431a97..dcfe4dd41e76 100644 --- a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/test_data/highlight_doctest.html +++ b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/test_data/highlight_doctest.html @@ -166,12 +166,12 @@ pre { color: #DCDCCC; background: #3F3F3F; font-size: 22px; padd /// /// ``` /// loop {} -#[cfg_attr(not(feature = "false"), doc = "loop {}")] +#[cfg_attr(not(feature = "false"), doc = "loop {}")] #[doc = "loop {}"] /// ``` /// -#[cfg_attr(feature = "alloc", doc = "```rust")] -#[cfg_attr(not(feature = "alloc"), doc = "```ignore")] +#[cfg_attr(feature = "alloc", doc = "```rust")] +#[cfg_attr(not(feature = "alloc"), doc = "```ignore")] /// let _ = example(&alloc::vec![1, 2, 3]); /// ``` pub fn mix_and_match() {} diff --git a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/tests.rs b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/tests.rs index aecd1d3fdb56..e8d185b7b636 100644 --- a/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/tests.rs +++ b/src/tools/rust-analyzer/crates/ide/src/syntax_highlighting/tests.rs @@ -1,7 +1,7 @@ use std::time::Instant; use expect_test::{ExpectFile, expect_file}; -use ide_db::{MiniCore, SymbolKind}; +use ide_db::{SymbolKind, ra_fixture::RaFixtureConfig}; use span::Edition; use test_utils::{AssertLinear, bench, bench_fixture, skip_slow_tests}; @@ -17,7 +17,7 @@ inject_doc_comment: true, macro_bang: true, syntactic_name_ref_highlighting: false, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; #[test] diff --git a/src/tools/rust-analyzer/crates/ide/src/test_explorer.rs b/src/tools/rust-analyzer/crates/ide/src/test_explorer.rs index 4792566f5f5b..02040ef1388b 100644 --- a/src/tools/rust-analyzer/crates/ide/src/test_explorer.rs +++ b/src/tools/rust-analyzer/crates/ide/src/test_explorer.rs @@ -1,8 +1,8 @@ //! Discovers tests use hir::{Crate, Module, ModuleDef, Semantics}; -use ide_db::base_db; -use ide_db::{FileId, RootDatabase, base_db::RootQueryDb}; +use ide_db::base_db::{self, all_crates}; +use ide_db::{FileId, RootDatabase}; use syntax::TextRange; use crate::{NavigationTarget, Runnable, TryToNav, runnables::runnable_fn}; @@ -26,7 +26,7 @@ pub struct TestItem { } pub(crate) fn discover_test_roots(db: &RootDatabase) -> Vec { - db.all_crates() + all_crates(db) .iter() .copied() .filter(|&id| id.data(db).origin.is_local()) @@ -48,7 +48,7 @@ pub(crate) fn discover_test_roots(db: &RootDatabase) -> Vec { fn find_crate_by_id(db: &RootDatabase, crate_id: &str) -> Option { // here, we use display_name as the crate id. This is not super ideal, but it works since we // only show tests for the local crates. - db.all_crates().iter().copied().find(|&id| { + all_crates(db).iter().copied().find(|&id| { id.data(db).origin.is_local() && id.extra_data(db).display_name.as_ref().is_some_and(|x| x.to_string() == crate_id) }) diff --git a/src/tools/rust-analyzer/crates/ide/src/typing.rs b/src/tools/rust-analyzer/crates/ide/src/typing.rs index e8b0c92dcb20..a49a85fe7804 100644 --- a/src/tools/rust-analyzer/crates/ide/src/typing.rs +++ b/src/tools/rust-analyzer/crates/ide/src/typing.rs @@ -17,7 +17,7 @@ use either::Either; use hir::EditionedFileId; -use ide_db::{FilePosition, RootDatabase, base_db::RootQueryDb}; +use ide_db::{FilePosition, RootDatabase, base_db::relevant_crates}; use span::Edition; use std::iter; @@ -70,13 +70,12 @@ pub(crate) fn on_char_typed( if !TRIGGER_CHARS.contains(&char_typed) { return None; } - let edition = db - .relevant_crates(position.file_id) + let edition = relevant_crates(db, position.file_id) .first() .copied() .map_or(Edition::CURRENT, |krate| krate.data(db).edition); let editioned_file_id_wrapper = EditionedFileId::new(db, position.file_id, edition); - let file = &db.parse(editioned_file_id_wrapper); + let file = &editioned_file_id_wrapper.parse(db); let char_matches_position = file.tree().syntax().text().char_at(position.offset) == Some(char_typed); if !stdx::always!(char_matches_position) { @@ -1240,12 +1239,6 @@ mod m {} #[test] fn parenthesis_noop_in_item_position_with_macro() { type_char_noop('(', r#"$0println!();"#); - type_char_noop( - '(', - r#" -fn main() $0println!("hello"); -}"#, - ); } #[test] diff --git a/src/tools/rust-analyzer/crates/ide/src/typing/on_enter.rs b/src/tools/rust-analyzer/crates/ide/src/typing/on_enter.rs index fdc583a15cc7..7d04594a5bf8 100644 --- a/src/tools/rust-analyzer/crates/ide/src/typing/on_enter.rs +++ b/src/tools/rust-analyzer/crates/ide/src/typing/on_enter.rs @@ -1,13 +1,11 @@ -//! Handles the `Enter` key press. At the momently, this only continues -//! comments, but should handle indent some time in the future as well. +//! Handles the `Enter` key press, including comment continuation and +//! indentation in brace-delimited constructs. -use ide_db::base_db::RootQueryDb; use ide_db::{FilePosition, RootDatabase}; use syntax::{ AstNode, SmolStr, SourceFile, SyntaxKind::*, - SyntaxNode, SyntaxToken, TextRange, TextSize, TokenAtOffset, - algo::find_node_at_offset, + SyntaxToken, TextRange, TextSize, TokenAtOffset, ast::{self, AstToken, edit::IndentLevel}, }; @@ -20,7 +18,8 @@ // - Enter inside triple-slash comments automatically inserts `///` // - Enter in the middle or after a trailing space in `//` inserts `//` // - Enter inside `//!` doc comments automatically inserts `//!` -// - Enter after `{` indents contents and closing `}` of single-line block +// - Enter after `{` reformats single-line brace-delimited contents by +// moving the text between `{` and the matching `}` onto an indented line // // This action needs to be assigned to shortcut explicitly. // @@ -52,7 +51,7 @@ pub(crate) fn on_enter(db: &RootDatabase, position: FilePosition) -> Option { let editioned_file_id_wrapper = ide_db::base_db::EditionedFileId::current_edition(db, position.file_id); - let parse = db.parse(editioned_file_id_wrapper); + let parse = editioned_file_id_wrapper.parse(db); let file = parse.tree(); let token = file.syntax().token_at_offset(position.offset).left_biased()?; @@ -60,22 +59,11 @@ pub(crate) fn on_enter(db: &RootDatabase, position: FilePosition) -> Option Option { - let contents = block_contents(&block)?; - - if block.syntax().text().contains_char('\n') { +fn on_enter_in_braces(l_curly: SyntaxToken, position: FilePosition) -> Option { + if l_curly.text_range().end() != position.offset { return None; } - let indent = IndentLevel::from_node(block.syntax()); - let mut edit = TextEdit::insert(position.offset, format!("\n{}$0", indent + 1)); - edit.union(TextEdit::insert(contents.text_range().end(), format!("\n{indent}"))).ok()?; - Some(edit) + let (r_curly, content) = brace_contents_on_same_line(&l_curly)?; + let indent = IndentLevel::from_token(&l_curly); + Some(TextEdit::replace( + TextRange::new(position.offset, r_curly.text_range().start()), + format!("\n{}$0{}\n{indent}", indent + 1, content), + )) } -fn on_enter_in_use_tree_list(list: ast::UseTreeList, position: FilePosition) -> Option { - if list.syntax().text().contains_char('\n') { - return None; - } +fn brace_contents_on_same_line(l_curly: &SyntaxToken) -> Option<(SyntaxToken, String)> { + let mut depth = 0_u32; + let mut tokens = Vec::new(); + let mut token = l_curly.next_token()?; - let indent = IndentLevel::from_node(list.syntax()); - let mut edit = TextEdit::insert(position.offset, format!("\n{}$0", indent + 1)); - edit.union(TextEdit::insert(list.r_curly_token()?.text_range().start(), format!("\n{indent}"))) - .ok()?; - Some(edit) -} - -fn block_contents(block: &ast::BlockExpr) -> Option { - let mut node = block.tail_expr().map(|e| e.syntax().clone()); - - for stmt in block.statements() { - if node.is_some() { - // More than 1 node in the block + loop { + if token.kind() == WHITESPACE && token.text().contains('\n') { return None; } - node = Some(stmt.syntax().clone()); - } + match token.kind() { + L_CURLY => { + depth += 1; + tokens.push(token.clone()); + } + R_CURLY if depth == 0 => { + let first = tokens.iter().position(|it| it.kind() != WHITESPACE); + let last = tokens.iter().rposition(|it| it.kind() != WHITESPACE); + let content = match first.zip(last) { + Some((first, last)) => { + tokens[first..=last].iter().map(|it| it.text()).collect() + } + None => String::new(), + }; + return Some((token, content)); + } + R_CURLY => { + depth -= 1; + tokens.push(token.clone()); + } + _ => tokens.push(token.clone()), + } - node + token = token.next_token()?; + } } fn followed_by_comment(comment: &ast::Comment) -> bool { @@ -383,10 +381,58 @@ fn main() { } #[test] - fn indents_fn_body_block() { + fn indents_empty_brace_pairs() { cov_mark::check!(indent_block_contents); do_check( r#" +fn f() {$0} + "#, + r#" +fn f() { + $0 +} + "#, + ); + do_check( + r#" +fn f() { + let x = {$0}; +} + "#, + r#" +fn f() { + let x = { + $0 + }; +} + "#, + ); + do_check( + r#" +use crate::{$0}; + "#, + r#" +use crate::{ + $0 +}; + "#, + ); + do_check( + r#" +mod m {$0} + "#, + r#" +mod m { + $0 +} + "#, + ); + } + + #[test] + fn indents_fn_body_block() { + do_check( + r#" fn f() {$0()} "#, r#" @@ -478,29 +524,39 @@ fn f() { } #[test] - fn does_not_indent_empty_block() { - do_check_noop( + fn indents_block_with_multiple_statements() { + do_check( r#" -fn f() {$0} +fn f() {$0 a = b; ()} + "#, + r#" +fn f() { + $0a = b; () +} "#, ); - do_check_noop( + do_check( r#" -fn f() {{$0}} +fn f() {$0 a = b; a = b; } + "#, + r#" +fn f() { + $0a = b; a = b; +} "#, ); } #[test] - fn does_not_indent_block_with_too_much_content() { - do_check_noop( + fn trims_spaces_around_brace_contents() { + do_check( r#" -fn f() {$0 a = b; ()} +fn f() {$0 () } "#, - ); - do_check_noop( r#" -fn f() {$0 a = b; a = b; } +fn f() { + $0() +} "#, ); } @@ -570,6 +626,20 @@ fn indents_use_tree_list() { ); } + #[test] + fn indents_item_lists() { + do_check( + r#" +mod m {$0} + "#, + r#" +mod m { + $0 +} + "#, + ); + } + #[test] fn does_not_indent_use_tree_list_when_not_at_curly_brace() { do_check_noop( diff --git a/src/tools/rust-analyzer/crates/ide/src/view_crate_graph.rs b/src/tools/rust-analyzer/crates/ide/src/view_crate_graph.rs index 25deffe10eb8..ecfdd09b2448 100644 --- a/src/tools/rust-analyzer/crates/ide/src/view_crate_graph.rs +++ b/src/tools/rust-analyzer/crates/ide/src/view_crate_graph.rs @@ -1,10 +1,9 @@ use dot::{Id, LabelText}; +use ide_db::base_db::all_crates; use ide_db::base_db::salsa::plumbing::AsId; use ide_db::{ FxHashMap, RootDatabase, - base_db::{ - BuiltCrateData, BuiltDependency, Crate, ExtraCrateData, RootQueryDb, SourceDatabase, - }, + base_db::{BuiltCrateData, BuiltDependency, Crate, ExtraCrateData, SourceDatabase}, }; // Feature: View Crate Graph @@ -17,8 +16,8 @@ // | Editor | Action Name | // |---------|-------------| // | VS Code | **rust-analyzer: View Crate Graph** | -pub(crate) fn view_crate_graph(db: &RootDatabase, full: bool) -> Result { - let all_crates = db.all_crates(); +pub(crate) fn view_crate_graph(db: &RootDatabase, full: bool) -> String { + let all_crates = all_crates(db); let crates_to_render = all_crates .iter() .copied() @@ -37,7 +36,7 @@ pub(crate) fn view_crate_graph(db: &RootDatabase, full: bool) -> Result { diff --git a/src/tools/rust-analyzer/crates/load-cargo/src/lib.rs b/src/tools/rust-analyzer/crates/load-cargo/src/lib.rs index 8753eab43a8c..68bf78e037c0 100644 --- a/src/tools/rust-analyzer/crates/load-cargo/src/lib.rs +++ b/src/tools/rust-analyzer/crates/load-cargo/src/lib.rs @@ -283,6 +283,19 @@ pub fn new( } } + // Collect workspace roots not already covered by a local PackageRoot + // (e.g. virtual workspaces where no package lives at the workspace root). + // We need these to load workspace-root rust-analyzer.toml into a local source root. + let uncovered_ws_roots: Vec = workspaces + .iter() + .filter_map(|ws| { + let ws_root = ws.workspace_root().to_path_buf(); + let dominated = + roots.iter().any(|root| root.is_local && root.include.contains(&ws_root)); + (!dominated).then_some(ws_root) + }) + .collect(); + for root in roots.into_iter().filter(|it| !it.include.is_empty()) { let file_set_roots: Vec = root.include.iter().cloned().map(VfsPath::from).collect(); @@ -291,6 +304,7 @@ pub fn new( let mut dirs = vfs::loader::Directories::default(); dirs.extensions.push("rs".into()); dirs.extensions.push("toml".into()); + dirs.extensions.push("md".into()); dirs.include.extend(root.include); dirs.exclude.extend(root.exclude); for excl in global_excludes { @@ -335,6 +349,20 @@ pub fn new( } } + // For virtual workspaces, the workspace root has no local PackageRoot, so + // rust-analyzer.toml there would fall into a library source root and be + // ignored. Load it explicitly via Entry::Files and register the workspace + // root as a local file-set root so the file is classified as local. + for ws_root in &uncovered_ws_roots { + let ratoml_path = ws_root.join("rust-analyzer.toml"); + let file_set_roots = vec![VfsPath::from(ws_root.clone())]; + let entry = vfs::loader::Entry::Files(vec![ratoml_path]); + res.watch.push(res.load.len()); + res.load.push(entry); + local_filesets.push(fsc.len() as u64); + fsc.add_file_set(file_set_roots); + } + if let Some(user_config_path) = user_config_dir_path { let ratoml_path = { let mut p = user_config_path.to_path_buf(); @@ -738,7 +766,7 @@ fn resolve_sub_span( #[cfg(test)] mod tests { - use ide_db::base_db::RootQueryDb; + use ide_db::base_db::all_crates; use vfs::file_set::FileSetConfigBuilder; use super::*; @@ -766,7 +794,7 @@ fn test_loading_rust_analyzer() { let (db, _vfs, _proc_macro) = load_workspace(workspace, &cargo_config.extra_env, &load_cargo_config).unwrap(); - let n_crates = db.all_crates().len(); + let n_crates = all_crates(&db).len(); // RA has quite a few crates, but the exact count doesn't matter assert!(n_crates > 20); } diff --git a/src/tools/rust-analyzer/crates/parser/src/grammar.rs b/src/tools/rust-analyzer/crates/parser/src/grammar.rs index e481bbe9bc4a..1ff8a56b580f 100644 --- a/src/tools/rust-analyzer/crates/parser/src/grammar.rs +++ b/src/tools/rust-analyzer/crates/parser/src/grammar.rs @@ -303,6 +303,18 @@ fn opt_ret_type(p: &mut Parser<'_>) -> bool { } } +fn opt_no_arrow_ret_type(p: &mut Parser<'_>) -> bool { + if p.at_ts(PATH_NAME_REF_KINDS) { + let m = p.start(); + p.error("missing thin-arrow `->`"); + types::type_no_bounds(p); + m.complete(p, RET_TYPE); + true + } else { + false + } +} + fn name_r(p: &mut Parser<'_>, recovery: TokenSet) { if p.at(IDENT) { let m = p.start(); diff --git a/src/tools/rust-analyzer/crates/parser/src/grammar/attributes.rs b/src/tools/rust-analyzer/crates/parser/src/grammar/attributes.rs index c0cf43a87bf7..2eeaa25257db 100644 --- a/src/tools/rust-analyzer/crates/parser/src/grammar/attributes.rs +++ b/src/tools/rust-analyzer/crates/parser/src/grammar/attributes.rs @@ -40,6 +40,86 @@ fn attr(p: &mut Parser<'_>, inner: bool) { // #![unsafe] // #![unsafe =] +fn cfg_attr_meta(p: &mut Parser<'_>, m: Marker) { + // test cfg_attr + // #![cfg_attr(not(foo), unsafe(bar()), cfg_attr(all(true, foo = "bar"), baz = "baz"))] + p.eat_contextual_kw(T![cfg_attr]); + p.bump(T!['(']); + cfg_predicate(p); + p.expect(T![,]); + while !p.at(T![')']) && !p.at(EOF) { + meta(p); + if !p.eat(T![,]) { + break; + } + } + p.expect(T![')']); + m.complete(p, CFG_ATTR_META); +} + +const CFG_PREDICATE_FIRST_SET: TokenSet = TokenSet::new(&[T![true], T![false], T![ident]]); + +fn cfg_predicate(p: &mut Parser<'_>) { + let m = p.start(); + if p.eat(T![true]) || p.eat(T![false]) { + // test cfg_true_false_pred + // #![cfg(true)] + // #![cfg(false)] + m.complete(p, CFG_ATOM); + return; + } + p.expect(T![ident]); + if p.eat(T![=]) { + if p.at(T![ident]) { + // This is required for completion, that inserts an identifier, to work in cases like + // `#[cfg(key = $0)]`, and also makes sense on itself. + + // test_err key_ident_cfg_predicate + // #![cfg(key = value)] + p.err_and_bump("expected a string literal"); + } else { + // test cfg_key_value_pred + // #![cfg(key = "value")] + p.expect(T![string]); + } + m.complete(p, CFG_ATOM); + } else if p.at(T!['(']) { + // test cfg_composite_pred + // #![cfg(any(a, all(b = "c", d)))] + delimited( + p, + T!['('], + T![')'], + T![,], + || "expected a cfg predicate".to_owned(), + CFG_PREDICATE_FIRST_SET, + |p| { + if p.at_ts(CFG_PREDICATE_FIRST_SET) { + cfg_predicate(p); + true + } else { + false + } + }, + ); + m.complete(p, CFG_COMPOSITE); + } else { + m.complete(p, CFG_ATOM); + } +} + +fn cfg_meta(p: &mut Parser<'_>, m: Marker) { + // test cfg_meta + // #![cfg(foo)] + // #![cfg(foo = "bar",)] + p.eat_contextual_kw(T![cfg]); + p.bump(T!['(']); + cfg_predicate(p); + p.eat(T![,]); + p.expect(T![')']); + m.complete(p, CFG_META); +} + // test metas // #![simple_ident] // #![simple::path] @@ -62,11 +142,23 @@ fn attr(p: &mut Parser<'_>, inner: bool) { // #![unsafe(simple::path::tt[a b c])] // #![unsafe(simple::path::tt{a b c})] pub(super) fn meta(p: &mut Parser<'_>) { - let meta = p.start(); - let is_unsafe = p.eat(T![unsafe]); - if is_unsafe { + let m = p.start(); + if p.eat(T![unsafe]) { p.expect(T!['(']); + meta(p); + p.expect(T![')']); + m.complete(p, UNSAFE_META); + return; } + + if p.nth_at(1, T!['(']) { + if p.at_contextual_kw(T![cfg_attr]) { + return cfg_attr_meta(p, m); + } else if p.at_contextual_kw(T![cfg]) { + return cfg_meta(p, m); + } + } + paths::attr_path(p); match p.current() { @@ -75,13 +167,14 @@ pub(super) fn meta(p: &mut Parser<'_>) { if expressions::expr(p).is_none() { p.error("expected expression"); } + m.complete(p, KEY_VALUE_META); + } + T!['('] | T!['['] | T!['{'] => { + items::token_tree(p); + m.complete(p, TOKEN_TREE_META); + } + _ => { + m.complete(p, PATH_META); } - T!['('] | T!['['] | T!['{'] => items::token_tree(p), - _ => {} } - if is_unsafe { - p.expect(T![')']); - } - - meta.complete(p, META); } diff --git a/src/tools/rust-analyzer/crates/parser/src/grammar/items.rs b/src/tools/rust-analyzer/crates/parser/src/grammar/items.rs index c609f9383ee0..c0acdde2a724 100644 --- a/src/tools/rust-analyzer/crates/parser/src/grammar/items.rs +++ b/src/tools/rust-analyzer/crates/parser/src/grammar/items.rs @@ -422,7 +422,12 @@ fn fn_(p: &mut Parser<'_>, m: Marker) { // test function_ret_type // fn foo() {} // fn bar() -> () {} - opt_ret_type(p); + if !opt_ret_type(p) { + // test_err function_ret_type_missing_arrow + // fn foo() usize {} + // fn bar() super::Foo {} + opt_no_arrow_ret_type(p); + } // test_err fn_ret_recovery // fn foo() -> A>]) { let x = 1; } diff --git a/src/tools/rust-analyzer/crates/parser/src/grammar/types.rs b/src/tools/rust-analyzer/crates/parser/src/grammar/types.rs index c62356d5c956..667bb68c649c 100644 --- a/src/tools/rust-analyzer/crates/parser/src/grammar/types.rs +++ b/src/tools/rust-analyzer/crates/parser/src/grammar/types.rs @@ -59,6 +59,9 @@ fn type_with_bounds_cond(p: &mut Parser<'_>, allow_bounds: bool) { } _ if paths::is_path_start(p) => path_or_macro_type(p, allow_bounds), LIFETIME_IDENT if p.nth_at(1, T![+]) => bare_dyn_trait_type(p), + T!['{'] => { + p.err_recover("expected type, found `{`", TYPE_RECOVERY_SET); + } _ => { p.err_recover("expected type", TYPE_RECOVERY_SET); } diff --git a/src/tools/rust-analyzer/crates/parser/src/syntax_kind/generated.rs b/src/tools/rust-analyzer/crates/parser/src/syntax_kind/generated.rs index a2295e449550..9cd48f2aa4f3 100644 --- a/src/tools/rust-analyzer/crates/parser/src/syntax_kind/generated.rs +++ b/src/tools/rust-analyzer/crates/parser/src/syntax_kind/generated.rs @@ -116,6 +116,8 @@ pub enum SyntaxKind { AWAIT_KW, BIKESHED_KW, BUILTIN_KW, + CFG_ATTR_KW, + CFG_KW, CLOBBER_ABI_KW, DEFAULT_KW, DYN_KW, @@ -186,6 +188,10 @@ pub enum SyntaxKind { BREAK_EXPR, CALL_EXPR, CAST_EXPR, + CFG_ATOM, + CFG_ATTR_META, + CFG_COMPOSITE, + CFG_META, CLOSURE_EXPR, CONST, CONST_ARG, @@ -216,6 +222,7 @@ pub enum SyntaxKind { INDEX_EXPR, INFER_TYPE, ITEM_LIST, + KEY_VALUE_META, LABEL, LET_ELSE, LET_EXPR, @@ -238,7 +245,6 @@ pub enum SyntaxKind { MATCH_ARM_LIST, MATCH_EXPR, MATCH_GUARD, - META, METHOD_CALL_EXPR, MODULE, NAME, @@ -254,6 +260,7 @@ pub enum SyntaxKind { PAREN_TYPE, PATH, PATH_EXPR, + PATH_META, PATH_PAT, PATH_SEGMENT, PATH_TYPE, @@ -285,6 +292,7 @@ pub enum SyntaxKind { STMT_LIST, STRUCT, TOKEN_TREE, + TOKEN_TREE_META, TRAIT, TRY_BLOCK_MODIFIER, TRY_EXPR, @@ -302,6 +310,7 @@ pub enum SyntaxKind { TYPE_PARAM, UNDERSCORE_EXPR, UNION, + UNSAFE_META, USE, USE_BOUND_GENERIC_ARGS, USE_TREE, @@ -360,6 +369,10 @@ pub const fn text(self) -> &'static str { | BREAK_EXPR | CALL_EXPR | CAST_EXPR + | CFG_ATOM + | CFG_ATTR_META + | CFG_COMPOSITE + | CFG_META | CLOSURE_EXPR | CONST | CONST_ARG @@ -390,6 +403,7 @@ pub const fn text(self) -> &'static str { | INDEX_EXPR | INFER_TYPE | ITEM_LIST + | KEY_VALUE_META | LABEL | LET_ELSE | LET_EXPR @@ -412,7 +426,6 @@ pub const fn text(self) -> &'static str { | MATCH_ARM_LIST | MATCH_EXPR | MATCH_GUARD - | META | METHOD_CALL_EXPR | MODULE | NAME @@ -428,6 +441,7 @@ pub const fn text(self) -> &'static str { | PAREN_TYPE | PATH | PATH_EXPR + | PATH_META | PATH_PAT | PATH_SEGMENT | PATH_TYPE @@ -459,6 +473,7 @@ pub const fn text(self) -> &'static str { | STMT_LIST | STRUCT | TOKEN_TREE + | TOKEN_TREE_META | TRAIT | TRY_BLOCK_MODIFIER | TRY_EXPR @@ -476,6 +491,7 @@ pub const fn text(self) -> &'static str { | TYPE_PARAM | UNDERSCORE_EXPR | UNION + | UNSAFE_META | USE | USE_BOUND_GENERIC_ARGS | USE_TREE @@ -601,6 +617,8 @@ pub const fn text(self) -> &'static str { AUTO_KW => "auto", BIKESHED_KW => "bikeshed", BUILTIN_KW => "builtin", + CFG_KW => "cfg", + CFG_ATTR_KW => "cfg_attr", CLOBBER_ABI_KW => "clobber_abi", DEFAULT_KW => "default", DYN_KW => "dyn", @@ -704,6 +722,8 @@ pub fn is_contextual_keyword(self, edition: Edition) -> bool { AUTO_KW => true, BIKESHED_KW => true, BUILTIN_KW => true, + CFG_KW => true, + CFG_ATTR_KW => true, CLOBBER_ABI_KW => true, DEFAULT_KW => true, DYN_KW if edition < Edition::Edition2018 => true, @@ -795,6 +815,8 @@ pub fn is_keyword(self, edition: Edition) -> bool { AUTO_KW => true, BIKESHED_KW => true, BUILTIN_KW => true, + CFG_KW => true, + CFG_ATTR_KW => true, CLOBBER_ABI_KW => true, DEFAULT_KW => true, DYN_KW if edition < Edition::Edition2018 => true, @@ -949,6 +971,8 @@ pub fn from_contextual_keyword(ident: &str, edition: Edition) -> Option AUTO_KW, "bikeshed" => BIKESHED_KW, "builtin" => BUILTIN_KW, + "cfg" => CFG_KW, + "cfg_attr" => CFG_ATTR_KW, "clobber_abi" => CLOBBER_ABI_KW, "default" => DEFAULT_KW, "dyn" if edition < Edition::Edition2018 => DYN_KW, @@ -1121,6 +1145,8 @@ pub fn from_char(c: char) -> Option { [auto] => { $ crate :: SyntaxKind :: AUTO_KW }; [bikeshed] => { $ crate :: SyntaxKind :: BIKESHED_KW }; [builtin] => { $ crate :: SyntaxKind :: BUILTIN_KW }; + [cfg] => { $ crate :: SyntaxKind :: CFG_KW }; + [cfg_attr] => { $ crate :: SyntaxKind :: CFG_ATTR_KW }; [clobber_abi] => { $ crate :: SyntaxKind :: CLOBBER_ABI_KW }; [default] => { $ crate :: SyntaxKind :: DEFAULT_KW }; [dyn] => { $ crate :: SyntaxKind :: DYN_KW }; diff --git a/src/tools/rust-analyzer/crates/parser/test_data/generated/runner.rs b/src/tools/rust-analyzer/crates/parser/test_data/generated/runner.rs index 4c001104fe52..71978390df6a 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/generated/runner.rs +++ b/src/tools/rust-analyzer/crates/parser/test_data/generated/runner.rs @@ -87,6 +87,22 @@ fn break_ambiguity() { #[test] fn cast_expr() { run_and_expect_no_errors("test_data/parser/inline/ok/cast_expr.rs"); } #[test] + fn cfg_attr() { run_and_expect_no_errors("test_data/parser/inline/ok/cfg_attr.rs"); } + #[test] + fn cfg_composite_pred() { + run_and_expect_no_errors("test_data/parser/inline/ok/cfg_composite_pred.rs"); + } + #[test] + fn cfg_key_value_pred() { + run_and_expect_no_errors("test_data/parser/inline/ok/cfg_key_value_pred.rs"); + } + #[test] + fn cfg_meta() { run_and_expect_no_errors("test_data/parser/inline/ok/cfg_meta.rs"); } + #[test] + fn cfg_true_false_pred() { + run_and_expect_no_errors("test_data/parser/inline/ok/cfg_true_false_pred.rs"); + } + #[test] fn closure_binder() { run_and_expect_no_errors("test_data/parser/inline/ok/closure_binder.rs"); } @@ -793,6 +809,10 @@ fn fn_ret_recovery() { run_and_expect_errors("test_data/parser/inline/err/fn_ret_recovery.rs"); } #[test] + fn function_ret_type_missing_arrow() { + run_and_expect_errors("test_data/parser/inline/err/function_ret_type_missing_arrow.rs"); + } + #[test] fn gen_fn() { run_and_expect_errors_with_edition( "test_data/parser/inline/err/gen_fn.rs", @@ -822,6 +842,10 @@ fn invalid_question_for_type_trait_bound() { ); } #[test] + fn key_ident_cfg_predicate() { + run_and_expect_errors("test_data/parser/inline/err/key_ident_cfg_predicate.rs"); + } + #[test] fn let_else_right_curly_brace() { run_and_expect_errors("test_data/parser/inline/err/let_else_right_curly_brace.rs"); } diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0005_attribute_recover.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0005_attribute_recover.rast index 77b4d06321d5..cf45dcf522ad 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0005_attribute_recover.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0005_attribute_recover.rast @@ -3,7 +3,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -37,7 +37,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0025_nope.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0025_nope.rast index b6bc0088374f..23964ab9d9b3 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0025_nope.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0025_nope.rast @@ -194,7 +194,7 @@ SOURCE_FILE WHITESPACE "\n" R_CURLY "}" WHITESPACE "\n" -error 95: expected type +error 95: expected type, found `{` error 95: expected COMMA error 96: expected field error 98: expected field declaration diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0027_incomplete_where_for.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0027_incomplete_where_for.rast index 3768a55d5308..31db794d9f12 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0027_incomplete_where_for.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0027_incomplete_where_for.rast @@ -26,5 +26,5 @@ SOURCE_FILE L_CURLY "{" R_CURLY "}" WHITESPACE "\n" -error 26: expected type +error 26: expected type, found `{` error 26: expected colon diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0032_match_arms_inner_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0032_match_arms_inner_attrs.rast index b657e9834156..2334b730e4cc 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0032_match_arms_inner_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0032_match_arms_inner_attrs.rast @@ -136,15 +136,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " ATTR diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0033_match_arms_outer_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0033_match_arms_outer_attrs.rast index b5bc3d84df09..acacee234826 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0033_match_arms_outer_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/err/0033_match_arms_outer_attrs.rast @@ -48,15 +48,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " R_CURLY "}" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rast new file mode 100644 index 000000000000..c0bca6ed1c31 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rast @@ -0,0 +1,50 @@ +SOURCE_FILE + FN + FN_KW "fn" + WHITESPACE " " + NAME + IDENT "foo" + PARAM_LIST + L_PAREN "(" + R_PAREN ")" + WHITESPACE " " + RET_TYPE + PATH_TYPE + PATH + PATH_SEGMENT + NAME_REF + IDENT "usize" + WHITESPACE " " + BLOCK_EXPR + STMT_LIST + L_CURLY "{" + R_CURLY "}" + WHITESPACE "\n" + FN + FN_KW "fn" + WHITESPACE " " + NAME + IDENT "bar" + PARAM_LIST + L_PAREN "(" + R_PAREN ")" + WHITESPACE " " + RET_TYPE + PATH_TYPE + PATH + PATH + PATH_SEGMENT + NAME_REF + SUPER_KW "super" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "Foo" + WHITESPACE " " + BLOCK_EXPR + STMT_LIST + L_CURLY "{" + R_CURLY "}" + WHITESPACE "\n" +error 9: missing thin-arrow `->` +error 27: missing thin-arrow `->` diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rs new file mode 100644 index 000000000000..f48e539df50d --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/function_ret_type_missing_arrow.rs @@ -0,0 +1,2 @@ +fn foo() usize {} +fn bar() super::Foo {} diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rast new file mode 100644 index 000000000000..de5fc7d5bdc0 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rast @@ -0,0 +1,19 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + IDENT "key" + WHITESPACE " " + EQ "=" + WHITESPACE " " + ERROR + IDENT "value" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" +error 13: expected a string literal diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rs new file mode 100644 index 000000000000..9a981bf939cc --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/key_ident_cfg_predicate.rs @@ -0,0 +1 @@ +#![cfg(key = value)] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/meta_recovery.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/meta_recovery.rast index b5c16e0798cc..9e456c98554d 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/meta_recovery.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/err/meta_recovery.rast @@ -3,14 +3,14 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META R_BRACK "]" WHITESPACE "\n" ATTR POUND "#" BANG "!" L_BRACK "[" - META + KEY_VALUE_META PATH PATH_SEGMENT NAME_REF @@ -24,7 +24,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH PATH_SEGMENT @@ -37,7 +37,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + KEY_VALUE_META PATH PATH PATH_SEGMENT @@ -52,18 +52,20 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" + PATH_META R_BRACK "]" WHITESPACE "\n" ATTR POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" WHITESPACE " " - EQ "=" + KEY_VALUE_META + EQ "=" R_BRACK "]" WHITESPACE "\n" error 3: expected identifier, `self`, `super`, `crate`, or `Self` @@ -77,7 +79,7 @@ error 41: expected L_PAREN error 41: expected identifier, `self`, `super`, `crate`, or `Self` error 41: expected R_PAREN error 52: expected L_PAREN -error 52: expected identifier, `self`, `super`, `crate`, or `Self` +error 53: expected identifier, `self`, `super`, `crate`, or `Self` error 54: expected expression error 54: expected expression error 54: expected R_PAREN diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/arg_with_attr.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/arg_with_attr.rast index ae1074c3680c..672f2c2f7f99 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/arg_with_attr.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/arg_with_attr.rast @@ -24,7 +24,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/array_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/array_attrs.rast index 6eb8af331195..2812bbf71bcc 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/array_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/array_attrs.rast @@ -31,15 +31,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " INT_NUMBER "2" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/assoc_item_list_inner_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/assoc_item_list_inner_attrs.rast index 9cb3c8a5c3b4..7c6dbf65cfdc 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/assoc_item_list_inner_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/assoc_item_list_inner_attrs.rast @@ -15,7 +15,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/attr_on_expr_stmt.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/attr_on_expr_stmt.rast index 81b7f2b3cbbe..248e6d1360db 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/attr_on_expr_stmt.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/attr_on_expr_stmt.rast @@ -17,7 +17,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -39,7 +39,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -61,7 +61,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -71,7 +71,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -87,7 +87,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rast new file mode 100644 index 000000000000..9af94f447db8 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rast @@ -0,0 +1,63 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_ATTR_META + CFG_ATTR_KW "cfg_attr" + L_PAREN "(" + CFG_COMPOSITE + IDENT "not" + L_PAREN "(" + CFG_ATOM + IDENT "foo" + R_PAREN ")" + COMMA "," + WHITESPACE " " + UNSAFE_META + UNSAFE_KW "unsafe" + L_PAREN "(" + TOKEN_TREE_META + PATH + PATH_SEGMENT + NAME_REF + IDENT "bar" + TOKEN_TREE + L_PAREN "(" + R_PAREN ")" + R_PAREN ")" + COMMA "," + WHITESPACE " " + CFG_ATTR_META + CFG_ATTR_KW "cfg_attr" + L_PAREN "(" + CFG_COMPOSITE + IDENT "all" + L_PAREN "(" + CFG_ATOM + TRUE_KW "true" + COMMA "," + WHITESPACE " " + CFG_ATOM + IDENT "foo" + WHITESPACE " " + EQ "=" + WHITESPACE " " + STRING "\"bar\"" + R_PAREN ")" + COMMA "," + WHITESPACE " " + KEY_VALUE_META + PATH + PATH_SEGMENT + NAME_REF + IDENT "baz" + WHITESPACE " " + EQ "=" + WHITESPACE " " + LITERAL + STRING "\"baz\"" + R_PAREN ")" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rs new file mode 100644 index 000000000000..5fe2776144e3 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_attr.rs @@ -0,0 +1 @@ +#![cfg_attr(not(foo), unsafe(bar()), cfg_attr(all(true, foo = "bar"), baz = "baz"))] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rast new file mode 100644 index 000000000000..89d06d134fe2 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rast @@ -0,0 +1,33 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_COMPOSITE + IDENT "any" + L_PAREN "(" + CFG_ATOM + IDENT "a" + COMMA "," + WHITESPACE " " + CFG_COMPOSITE + IDENT "all" + L_PAREN "(" + CFG_ATOM + IDENT "b" + WHITESPACE " " + EQ "=" + WHITESPACE " " + STRING "\"c\"" + COMMA "," + WHITESPACE " " + CFG_ATOM + IDENT "d" + R_PAREN ")" + R_PAREN ")" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rs new file mode 100644 index 000000000000..7d830c128815 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_composite_pred.rs @@ -0,0 +1 @@ +#![cfg(any(a, all(b = "c", d)))] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rast new file mode 100644 index 000000000000..e48d39bf55db --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rast @@ -0,0 +1,17 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + IDENT "key" + WHITESPACE " " + EQ "=" + WHITESPACE " " + STRING "\"value\"" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rs new file mode 100644 index 000000000000..dc194ed86be2 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_key_value_pred.rs @@ -0,0 +1 @@ +#![cfg(key = "value")] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rast new file mode 100644 index 000000000000..f024cfd1aae4 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rast @@ -0,0 +1,30 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + IDENT "foo" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + IDENT "foo" + WHITESPACE " " + EQ "=" + WHITESPACE " " + STRING "\"bar\"" + COMMA "," + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rs new file mode 100644 index 000000000000..ef0030e75fde --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_meta.rs @@ -0,0 +1,2 @@ +#![cfg(foo)] +#![cfg(foo = "bar",)] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rast new file mode 100644 index 000000000000..e33595a93dcd --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rast @@ -0,0 +1,25 @@ +SOURCE_FILE + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + TRUE_KW "true" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM + FALSE_KW "false" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rs b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rs new file mode 100644 index 000000000000..473582164a22 --- /dev/null +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/cfg_true_false_pred.rs @@ -0,0 +1,2 @@ +#![cfg(true)] +#![cfg(false)] diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/generic_param_attribute.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/generic_param_attribute.rast index 28a216e87309..5567a53c56a2 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/generic_param_attribute.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/generic_param_attribute.rast @@ -10,7 +10,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -25,7 +25,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_inner_attribute.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_inner_attribute.rast index 6fd9f424676b..edb04387336a 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_inner_attribute.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_inner_attribute.rast @@ -26,7 +26,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -41,7 +41,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -56,7 +56,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_outer_attributes.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_outer_attributes.rast index 0f7580c1a339..321db782d133 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_outer_attributes.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/match_arms_outer_attributes.rast @@ -26,19 +26,16 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"some\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " WILDCARD_PAT @@ -55,19 +52,16 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"other\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " WILDCARD_PAT @@ -84,55 +78,46 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"many\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"attributes\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"before\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " WILDCARD_PAT diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/metas.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/metas.rast index b1ac60b530ef..6360552a6f06 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/metas.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/metas.rast @@ -3,7 +3,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -14,7 +14,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH PATH_SEGMENT @@ -30,7 +30,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + KEY_VALUE_META PATH PATH_SEGMENT NAME_REF @@ -46,7 +46,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + KEY_VALUE_META PATH PATH PATH @@ -72,7 +72,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -91,7 +91,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -110,7 +110,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -129,7 +129,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH PATH @@ -158,7 +158,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH PATH @@ -187,7 +187,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH PATH @@ -216,32 +216,14 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple_ident" - R_PAREN ")" - R_BRACK "]" - WHITESPACE "\n" - ATTR - POUND "#" - BANG "!" - L_BRACK "[" - META - UNSAFE_KW "unsafe" - L_PAREN "(" - PATH + PATH_META PATH PATH_SEGMENT NAME_REF - IDENT "simple" - COLON2 "::" - PATH_SEGMENT - NAME_REF - IDENT "path" + IDENT "simple_ident" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" @@ -249,29 +231,10 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple_ident_expr" - WHITESPACE " " - EQ "=" - WHITESPACE " " - LITERAL - STRING "\"\"" - R_PAREN ")" - R_BRACK "]" - WHITESPACE "\n" - ATTR - POUND "#" - BANG "!" - L_BRACK "[" - META - UNSAFE_KW "unsafe" - L_PAREN "(" - PATH + PATH_META PATH PATH PATH_SEGMENT @@ -281,15 +244,6 @@ SOURCE_FILE PATH_SEGMENT NAME_REF IDENT "path" - COLON2 "::" - PATH_SEGMENT - NAME_REF - IDENT "Expr" - WHITESPACE " " - EQ "=" - WHITESPACE " " - LITERAL - STRING "\"\"" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" @@ -297,21 +251,19 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple_ident_tt" - TOKEN_TREE - L_PAREN "(" - IDENT "a" + KEY_VALUE_META + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple_ident_expr" WHITESPACE " " - IDENT "b" + EQ "=" WHITESPACE " " - IDENT "c" - R_PAREN ")" + LITERAL + STRING "\"\"" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" @@ -319,75 +271,29 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple_ident_tt" - TOKEN_TREE - L_BRACK "[" - IDENT "a" - WHITESPACE " " - IDENT "b" - WHITESPACE " " - IDENT "c" - R_BRACK "]" - R_PAREN ")" - R_BRACK "]" - WHITESPACE "\n" - ATTR - POUND "#" - BANG "!" - L_BRACK "[" - META - UNSAFE_KW "unsafe" - L_PAREN "(" - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple_ident_tt" - TOKEN_TREE - L_CURLY "{" - IDENT "a" - WHITESPACE " " - IDENT "b" - WHITESPACE " " - IDENT "c" - R_CURLY "}" - R_PAREN ")" - R_BRACK "]" - WHITESPACE "\n" - ATTR - POUND "#" - BANG "!" - L_BRACK "[" - META - UNSAFE_KW "unsafe" - L_PAREN "(" - PATH + KEY_VALUE_META PATH PATH + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple" + COLON2 "::" PATH_SEGMENT NAME_REF - IDENT "simple" + IDENT "path" COLON2 "::" PATH_SEGMENT NAME_REF - IDENT "path" - COLON2 "::" - PATH_SEGMENT - NAME_REF - IDENT "tt" - TOKEN_TREE - L_PAREN "(" - IDENT "a" + IDENT "Expr" WHITESPACE " " - IDENT "b" + EQ "=" WHITESPACE " " - IDENT "c" - R_PAREN ")" + LITERAL + STRING "\"\"" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" @@ -395,31 +301,22 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH + TOKEN_TREE_META PATH - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple" - COLON2 "::" PATH_SEGMENT NAME_REF - IDENT "path" - COLON2 "::" - PATH_SEGMENT - NAME_REF - IDENT "tt" - TOKEN_TREE - L_BRACK "[" - IDENT "a" - WHITESPACE " " - IDENT "b" - WHITESPACE " " - IDENT "c" - R_BRACK "]" + IDENT "simple_ident_tt" + TOKEN_TREE + L_PAREN "(" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_PAREN ")" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" @@ -427,31 +324,144 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + UNSAFE_META UNSAFE_KW "unsafe" L_PAREN "(" - PATH + TOKEN_TREE_META PATH - PATH - PATH_SEGMENT - NAME_REF - IDENT "simple" - COLON2 "::" PATH_SEGMENT NAME_REF - IDENT "path" - COLON2 "::" - PATH_SEGMENT - NAME_REF - IDENT "tt" - TOKEN_TREE - L_CURLY "{" - IDENT "a" - WHITESPACE " " - IDENT "b" - WHITESPACE " " - IDENT "c" - R_CURLY "}" + IDENT "simple_ident_tt" + TOKEN_TREE + L_BRACK "[" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_BRACK "]" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + UNSAFE_META + UNSAFE_KW "unsafe" + L_PAREN "(" + TOKEN_TREE_META + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple_ident_tt" + TOKEN_TREE + L_CURLY "{" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_CURLY "}" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + UNSAFE_META + UNSAFE_KW "unsafe" + L_PAREN "(" + TOKEN_TREE_META + PATH + PATH + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "path" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "tt" + TOKEN_TREE + L_PAREN "(" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_PAREN ")" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + UNSAFE_META + UNSAFE_KW "unsafe" + L_PAREN "(" + TOKEN_TREE_META + PATH + PATH + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "path" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "tt" + TOKEN_TREE + L_BRACK "[" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_BRACK "]" + R_PAREN ")" + R_BRACK "]" + WHITESPACE "\n" + ATTR + POUND "#" + BANG "!" + L_BRACK "[" + UNSAFE_META + UNSAFE_KW "unsafe" + L_PAREN "(" + TOKEN_TREE_META + PATH + PATH + PATH + PATH_SEGMENT + NAME_REF + IDENT "simple" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "path" + COLON2 "::" + PATH_SEGMENT + NAME_REF + IDENT "tt" + TOKEN_TREE + L_CURLY "{" + IDENT "a" + WHITESPACE " " + IDENT "b" + WHITESPACE " " + IDENT "c" + R_CURLY "}" R_PAREN ")" R_BRACK "]" WHITESPACE "\n" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/param_outer_arg.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/param_outer_arg.rast index c63ea020a3f7..7495ba7b31a2 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/param_outer_arg.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/param_outer_arg.rast @@ -10,7 +10,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_field_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_field_attrs.rast index 639ee0eb7770..cfa2694fd1de 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_field_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_field_attrs.rast @@ -12,7 +12,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_literal_field_with_attr.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_literal_field_with_attr.rast index a1df70841e85..717dee8c9f39 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_literal_field_with_attr.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_literal_field_with_attr.rast @@ -25,15 +25,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field.rast index f3d2fde46698..7fba529be9e9 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field.rast @@ -88,18 +88,14 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_COMPOSITE IDENT "any" - TOKEN_TREE - L_PAREN "(" - R_PAREN ")" + L_PAREN "(" R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field_list.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field_list.rast index f69ae1d6445f..af5b82b889d3 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field_list.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/record_pat_field_list.rast @@ -146,18 +146,14 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_COMPOSITE IDENT "any" - TOKEN_TREE - L_PAREN "(" - R_PAREN ")" + L_PAREN "(" R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " DOT2 ".." diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/self_param_outer_attr.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/self_param_outer_attr.rast index db583f7d5266..3a163e5b8ee7 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/self_param_outer_attr.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/self_param_outer_attr.rast @@ -10,7 +10,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_attrs.rast index 39857b23c6e3..76954927d566 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_attrs.rast @@ -34,15 +34,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " INT_NUMBER "2" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_field_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_field_attrs.rast index 1699602f4fba..1f7100c46d4e 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_field_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/inline/ok/tuple_field_attrs.rast @@ -11,7 +11,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0006_inner_attributes.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0006_inner_attributes.rast index cb63ba80e77d..ddab028c0686 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0006_inner_attributes.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0006_inner_attributes.rast @@ -3,7 +3,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -14,7 +14,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -29,7 +29,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -44,7 +44,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -89,7 +89,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -104,7 +104,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -123,7 +123,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -138,7 +138,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -153,7 +153,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -175,7 +175,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0008_mod_item.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0008_mod_item.rast index adee67181b1a..cb6da8717ddd 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0008_mod_item.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0008_mod_item.rast @@ -48,7 +48,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0011_outer_attribute.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0011_outer_attribute.rast index dbb9bc54da8d..47a5cfce081a 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0011_outer_attribute.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0011_outer_attribute.rast @@ -3,21 +3,18 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "test" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n" ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -41,7 +38,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + KEY_VALUE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0017_attr_trailing_comma.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0017_attr_trailing_comma.rast index 7c914e2542eb..c5d054702fa4 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0017_attr_trailing_comma.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0017_attr_trailing_comma.rast @@ -3,7 +3,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0035_weird_exprs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0035_weird_exprs.rast index 318d492ab4a5..15ce6c70bea7 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0035_weird_exprs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0035_weird_exprs.rast @@ -11,7 +11,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -26,7 +26,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -41,7 +41,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -56,7 +56,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -71,7 +71,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + KEY_VALUE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0044_let_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0044_let_attrs.rast index f3c20337e43f..fcdc1a9895d8 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0044_let_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0044_let_attrs.rast @@ -18,19 +18,16 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "feature" WHITESPACE " " EQ "=" WHITESPACE " " STRING "\"backtrace\"" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE "\n " LET_KW "let" diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0045_block_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0045_block_attrs.rast index c22d99f1ae10..f26bb85df292 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0045_block_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0045_block_attrs.rast @@ -16,7 +16,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -38,7 +38,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -53,7 +53,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -77,7 +77,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -119,7 +119,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF @@ -211,7 +211,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0046_extern_inner_attributes.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0046_extern_inner_attributes.rast index 4eb51cfdf09e..3d33eb4ff73c 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0046_extern_inner_attributes.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0046_extern_inner_attributes.rast @@ -14,7 +14,7 @@ SOURCE_FILE POUND "#" BANG "!" L_BRACK "[" - META + TOKEN_TREE_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0051_parameter_attrs.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0051_parameter_attrs.rast index eafee90db427..24d4392282a0 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0051_parameter_attrs.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0051_parameter_attrs.rast @@ -10,7 +10,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -20,7 +20,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -55,7 +55,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -116,7 +116,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -158,7 +158,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -181,7 +181,7 @@ SOURCE_FILE POUND "#" WHITESPACE " " L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -228,7 +228,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -255,7 +255,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -282,7 +282,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -316,7 +316,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -352,7 +352,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -389,7 +389,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -422,7 +422,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -456,7 +456,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0053_outer_attribute_on_macro_rules.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0053_outer_attribute_on_macro_rules.rast index b94d43beb3c2..c300b7af5058 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0053_outer_attribute_on_macro_rules.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0053_outer_attribute_on_macro_rules.rast @@ -5,7 +5,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0062_macro_2.0.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0062_macro_2.0.rast index 1415a866b695..b92d78e5bd60 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0062_macro_2.0.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0062_macro_2.0.rast @@ -54,7 +54,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0063_variadic_fun.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0063_variadic_fun.rast index e36399123bcc..f1c6d2efeb9c 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0063_variadic_fun.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0063_variadic_fun.rast @@ -96,15 +96,12 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META - PATH - PATH_SEGMENT - NAME_REF - IDENT "cfg" - TOKEN_TREE - L_PAREN "(" + CFG_META + CFG_KW "cfg" + L_PAREN "(" + CFG_ATOM IDENT "never" - R_PAREN ")" + R_PAREN ")" R_BRACK "]" WHITESPACE " " SLICE_PAT diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0070_expr_attr_placement.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0070_expr_attr_placement.rast index 3d00b27ab8d3..5229b97eb2af 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0070_expr_attr_placement.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0070_expr_attr_placement.rast @@ -19,7 +19,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -39,7 +39,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0071_stmt_attr_placement.rast b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0071_stmt_attr_placement.rast index 1cafc775cdf7..c0685448f256 100644 --- a/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0071_stmt_attr_placement.rast +++ b/src/tools/rust-analyzer/crates/parser/test_data/parser/ok/0071_stmt_attr_placement.rast @@ -17,7 +17,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -31,7 +31,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF @@ -56,7 +56,7 @@ SOURCE_FILE ATTR POUND "#" L_BRACK "[" - META + PATH_META PATH PATH_SEGMENT NAME_REF diff --git a/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib/proc_macros.rs b/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib/proc_macros.rs index 4065dbd0b49b..cf00be0327cf 100644 --- a/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib/proc_macros.rs +++ b/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib/proc_macros.rs @@ -7,7 +7,7 @@ impl From for crate::PanicMessage { fn from(p: bridge::PanicMessage) -> Self { - Self { message: p.as_str().map(|s| s.to_owned()) } + Self { message: p.into_string() } } } diff --git a/src/tools/rust-analyzer/crates/profile/Cargo.toml b/src/tools/rust-analyzer/crates/profile/Cargo.toml index 4828419003a6..8377e94c8d60 100644 --- a/src/tools/rust-analyzer/crates/profile/Cargo.toml +++ b/src/tools/rust-analyzer/crates/profile/Cargo.toml @@ -16,8 +16,8 @@ doctest = false cfg-if = "1.0.1" jemalloc-ctl = { version = "0.5.4", package = "tikv-jemalloc-ctl", optional = true } -[target.'cfg(all(target_os = "linux", not(target_env = "ohos")))'.dependencies] -perf-event = "=0.4.7" +[target.'cfg(all(target_os = "linux", not(target_env = "ohos"), any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64")))'.dependencies] +perf-event = "=0.4.8" [target.'cfg(all(target_os = "linux", target_env = "gnu"))'.dependencies] libc.workspace = true diff --git a/src/tools/rust-analyzer/crates/profile/src/stop_watch.rs b/src/tools/rust-analyzer/crates/profile/src/stop_watch.rs index 00c37c01d25e..a1c1383ad539 100644 --- a/src/tools/rust-analyzer/crates/profile/src/stop_watch.rs +++ b/src/tools/rust-analyzer/crates/profile/src/stop_watch.rs @@ -11,7 +11,11 @@ pub struct StopWatch { time: Instant, - #[cfg(all(target_os = "linux", not(target_env = "ohos")))] + #[cfg(all( + target_os = "linux", + not(target_env = "ohos"), + any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64") + ))] counter: Option, memory: MemoryUsage, } @@ -24,7 +28,11 @@ pub struct StopWatchSpan { impl StopWatch { pub fn start() -> StopWatch { - #[cfg(all(target_os = "linux", not(target_env = "ohos")))] + #[cfg(all( + target_os = "linux", + not(target_env = "ohos"), + any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64") + ))] let counter = { // When debugging rust-analyzer using rr, the perf-related syscalls cause it to abort. // We allow disabling perf by setting the env var `RA_DISABLE_PERF`. @@ -51,7 +59,11 @@ pub fn start() -> StopWatch { let time = Instant::now(); StopWatch { time, - #[cfg(all(target_os = "linux", not(target_env = "ohos")))] + #[cfg(all( + target_os = "linux", + not(target_env = "ohos"), + any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64") + ))] counter, memory, } @@ -60,13 +72,19 @@ pub fn start() -> StopWatch { pub fn elapsed(&mut self) -> StopWatchSpan { let time = self.time.elapsed(); - #[cfg(all(target_os = "linux", not(target_env = "ohos")))] + #[cfg(all( + target_os = "linux", + not(target_env = "ohos"), + any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64") + ))] let instructions = self.counter.as_mut().and_then(|it| { it.read().map_err(|err| eprintln!("Failed to read perf counter: {err}")).ok() }); - #[cfg(all(target_os = "linux", target_env = "ohos"))] - let instructions = None; - #[cfg(not(target_os = "linux"))] + #[cfg(not(all( + target_os = "linux", + not(target_env = "ohos"), + any(target_arch = "x86", target_arch = "x86_64", target_arch = "aarch64") + )))] let instructions = None; let memory = MemoryUsage::now() - self.memory; diff --git a/src/tools/rust-analyzer/crates/project-model/src/cargo_workspace.rs b/src/tools/rust-analyzer/crates/project-model/src/cargo_workspace.rs index 792206b74f84..5d8273832bb2 100644 --- a/src/tools/rust-analyzer/crates/project-model/src/cargo_workspace.rs +++ b/src/tools/rust-analyzer/crates/project-model/src/cargo_workspace.rs @@ -131,6 +131,8 @@ pub struct CargoConfig { pub run_build_script_command: Option>, /// Extra args to pass to the cargo command. pub extra_args: Vec, + /// Extra args passed only to `cargo metadata`, not other cargo commands. + pub metadata_extra_args: Vec, /// Extra env vars to set when invoking the cargo command pub extra_env: FxHashMap>, pub invocation_strategy: InvocationStrategy, @@ -320,6 +322,8 @@ pub struct CargoMetadataConfig { pub targets: Vec, /// Extra args to pass to the cargo command. pub extra_args: Vec, + /// Extra args passed directly to `cargo metadata` without filtering. + pub metadata_extra_args: Vec, /// Extra env vars to set when invoking the cargo command pub extra_env: FxHashMap>, /// What kind of metadata are we fetching: workspace, rustc, or sysroot. @@ -679,6 +683,7 @@ pub(crate) fn new( other_options.push(arg.to_owned()); } } + other_options.extend(config.metadata_extra_args.iter().cloned()); let mut lockfile_copy = None; if cargo_toml.is_rust_manifest() { diff --git a/src/tools/rust-analyzer/crates/project-model/src/env.rs b/src/tools/rust-analyzer/crates/project-model/src/env.rs index 51c447945cf4..ab45917a5663 100644 --- a/src/tools/rust-analyzer/crates/project-model/src/env.rs +++ b/src/tools/rust-analyzer/crates/project-model/src/env.rs @@ -79,18 +79,31 @@ pub(crate) fn cargo_config_env( for (key, entry) in env_toml { let key = key.as_ref().as_ref(); let value = match entry.as_ref() { - DeValue::String(s) => String::from(s.clone()), + DeValue::String(s) => { + // Plain string entries have no `force` option, so they should not + // override existing environment variables (matching Cargo behavior). + if extra_env.get(key).is_some_and(Option::is_some) { + continue; + } + if let Ok(val) = std::env::var(key) { val } else { String::from(s.clone()) } + } DeValue::Table(entry) => { // Each entry MUST have a `value` key. let Some(map) = entry.get("value").and_then(|v| v.as_ref().as_str()) else { continue; }; - // If the entry already exists in the environment AND the `force` key is not set to - // true, then don't overwrite the value. - if extra_env.get(key).is_some_and(Option::is_some) - && !entry.get("force").and_then(|v| v.as_ref().as_bool()).unwrap_or(false) - { - continue; + let is_forced = + entry.get("force").and_then(|v| v.as_ref().as_bool()).unwrap_or(false); + // If the entry already exists in the environment AND the `force` key is not set + // to true, use the existing value instead of the config value. + if !is_forced { + if extra_env.get(key).is_some_and(Option::is_some) { + continue; + } + if let Ok(val) = std::env::var(key) { + env.insert(key, val); + continue; + } } if let Some(base) = entry.get("relative").and_then(|v| { @@ -124,38 +137,80 @@ fn parse_output_cargo_config_env_works() { .unwrap(); let config_path = cwd.join(".cargo").join("config.toml"); let raw = r#" -env.CARGO_WORKSPACE_DIR.relative = true -env.CARGO_WORKSPACE_DIR.value = "" -env.INVALID.relative = "invalidbool" -env.INVALID.value = "../relative" -env.RELATIVE.relative = true -env.RELATIVE.value = "../relative" -env.TEST.value = "test" -env.FORCED.value = "test" -env.FORCED.force = true -env.UNFORCED.value = "test" -env.UNFORCED.forced = false -env.OVERWRITTEN.value = "test" -env.NOT_AN_OBJECT = "value" +env.RA_TEST_WORKSPACE_DIR.relative = true +env.RA_TEST_WORKSPACE_DIR.value = "" +env.RA_TEST_INVALID.relative = "invalidbool" +env.RA_TEST_INVALID.value = "../relative" +env.RA_TEST_RELATIVE.relative = true +env.RA_TEST_RELATIVE.value = "../relative" +env.RA_TEST_UNSET.value = "test" +env.RA_TEST_FORCED.value = "test" +env.RA_TEST_FORCED.force = true +env.RA_TEST_UNFORCED.value = "test" +env.RA_TEST_UNFORCED.forced = false +env.RA_TEST_OVERWRITTEN.value = "test" +env.RA_TEST_NOT_AN_OBJECT = "value" "#; let raw = raw.lines().map(|l| format!("{l} # {config_path}")).join("\n"); let config = CargoConfigFile::from_string_for_test(raw); let extra_env = [ - ("FORCED", Some("ignored")), - ("UNFORCED", Some("newvalue")), - ("OVERWRITTEN", Some("newvalue")), - ("TEST", None), + ("RA_TEST_FORCED", Some("ignored")), + ("RA_TEST_UNFORCED", Some("newvalue")), + ("RA_TEST_OVERWRITTEN", Some("newvalue")), + ("RA_TEST_UNSET", None), ] .iter() .map(|(k, v)| (k.to_string(), v.map(ToString::to_string))) .collect(); let env = cargo_config_env(&Some(config), &extra_env); - assert_eq!(env.get("CARGO_WORKSPACE_DIR").as_deref(), Some(cwd.join("").as_str())); - assert_eq!(env.get("RELATIVE").as_deref(), Some(cwd.join("../relative").as_str())); - assert_eq!(env.get("INVALID").as_deref(), Some("../relative")); - assert_eq!(env.get("TEST").as_deref(), Some("test")); - assert_eq!(env.get("FORCED").as_deref(), Some("test")); - assert_eq!(env.get("UNFORCED").as_deref(), Some("newvalue")); - assert_eq!(env.get("OVERWRITTEN").as_deref(), Some("newvalue")); - assert_eq!(env.get("NOT_AN_OBJECT").as_deref(), Some("value")); + assert_eq!(env.get("RA_TEST_WORKSPACE_DIR").as_deref(), Some(cwd.join("").as_str())); + assert_eq!(env.get("RA_TEST_RELATIVE").as_deref(), Some(cwd.join("../relative").as_str())); + assert_eq!(env.get("RA_TEST_INVALID").as_deref(), Some("../relative")); + assert_eq!(env.get("RA_TEST_UNSET").as_deref(), Some("test")); + assert_eq!(env.get("RA_TEST_FORCED").as_deref(), Some("test")); + assert_eq!(env.get("RA_TEST_UNFORCED").as_deref(), Some("newvalue")); + assert_eq!(env.get("RA_TEST_OVERWRITTEN").as_deref(), Some("newvalue")); + assert_eq!(env.get("RA_TEST_NOT_AN_OBJECT").as_deref(), Some("value")); +} + +#[test] +fn cargo_config_env_respects_process_env() { + use itertools::Itertools; + + let cwd = paths::AbsPathBuf::try_from( + paths::Utf8PathBuf::try_from(std::env::current_dir().unwrap()).unwrap(), + ) + .unwrap(); + let config_path = cwd.join(".cargo").join("config.toml"); + + // SAFETY: this test is not run in parallel with other tests that depend on these env vars. + unsafe { + std::env::set_var("RA_TEST_PROCESS_ENV_STRING", "from_process"); + std::env::set_var("RA_TEST_PROCESS_ENV_TABLE", "from_process"); + std::env::set_var("RA_TEST_PROCESS_ENV_FORCED", "from_process"); + } + + let raw = r#" +env.RA_TEST_PROCESS_ENV_STRING = "from_config" +env.RA_TEST_PROCESS_ENV_TABLE.value = "from_config" +env.RA_TEST_PROCESS_ENV_FORCED.value = "from_config" +env.RA_TEST_PROCESS_ENV_FORCED.force = true +"#; + let raw = raw.lines().map(|l| format!("{l} # {config_path}")).join("\n"); + let config = CargoConfigFile::from_string_for_test(raw); + let extra_env = FxHashMap::default(); + let env = cargo_config_env(&Some(config), &extra_env); + + // Plain string form should use process env value, not config value + assert_eq!(env.get("RA_TEST_PROCESS_ENV_STRING").as_deref(), Some("from_process")); + // Table form without force should use process env value, not config value + assert_eq!(env.get("RA_TEST_PROCESS_ENV_TABLE").as_deref(), Some("from_process")); + // Table form with force=true should override process env + assert_eq!(env.get("RA_TEST_PROCESS_ENV_FORCED").as_deref(), Some("from_config")); + + unsafe { + std::env::remove_var("RA_TEST_PROCESS_ENV_STRING"); + std::env::remove_var("RA_TEST_PROCESS_ENV_TABLE"); + std::env::remove_var("RA_TEST_PROCESS_ENV_FORCED"); + } } diff --git a/src/tools/rust-analyzer/crates/project-model/src/workspace.rs b/src/tools/rust-analyzer/crates/project-model/src/workspace.rs index 581b5fa51446..29a19bc32e45 100644 --- a/src/tools/rust-analyzer/crates/project-model/src/workspace.rs +++ b/src/tools/rust-analyzer/crates/project-model/src/workspace.rs @@ -216,6 +216,7 @@ fn load_cargo( features, rustc_source, extra_args, + metadata_extra_args, extra_env, set_test, cfg_overrides, @@ -289,6 +290,7 @@ struct Root { features: features.clone(), targets: targets.clone(), extra_args: extra_args.clone(), + metadata_extra_args: metadata_extra_args.clone(), extra_env: extra_env.clone(), toolchain_version: toolchain.clone(), kind: "workspace", @@ -343,6 +345,7 @@ struct Root { features: crate::CargoFeatures::default(), targets: targets.clone(), extra_args: extra_args.clone(), + metadata_extra_args: metadata_extra_args.clone(), extra_env: extra_env.clone(), toolchain_version: toolchain.clone(), kind: "rustc-dev" @@ -575,6 +578,7 @@ pub fn load_detached_file( features: config.features.clone(), targets, extra_args: config.extra_args.clone(), + metadata_extra_args: config.metadata_extra_args.clone(), extra_env: config.extra_env.clone(), toolchain_version: toolchain.clone(), kind: "detached-file", @@ -1942,6 +1946,7 @@ fn sysroot_metadata_config( features: Default::default(), targets, extra_args: Default::default(), + metadata_extra_args: config.metadata_extra_args.clone(), extra_env: config.extra_env.clone(), toolchain_version, kind: "sysroot", diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/cli/analysis_stats.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/cli/analysis_stats.rs index 74828cba02ed..e56727d39d67 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/cli/analysis_stats.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/cli/analysis_stats.rs @@ -23,10 +23,10 @@ use hir_ty::InferenceResult; use ide::{ Analysis, AnalysisHost, AnnotationConfig, DiagnosticsConfig, Edition, InlayFieldsToResolve, - InlayHintsConfig, LineCol, RootDatabase, + InlayHintsConfig, LineCol, RaFixtureConfig, RootDatabase, }; use ide_db::{ - EditionedFileId, LineIndexDatabase, MiniCore, SnippetCap, + EditionedFileId, LineIndexDatabase, SnippetCap, base_db::{SourceDatabase, salsa::Database}, }; use itertools::Itertools; @@ -1367,6 +1367,7 @@ fn run_ide_things( &InlayHintsConfig { render_colons: false, type_hints: true, + type_hints_placement: ide::TypeHintsPlacement::Inline, sized_bound: false, discriminant_hints: ide::DiscriminantHints::Always, parameter_hints: true, @@ -1397,7 +1398,7 @@ fn run_ide_things( closing_brace_hints_min_lines: Some(20), fields_to_resolve: InlayFieldsToResolve::empty(), range_exclusive_hints: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }, analysis.editioned_file_id_to_vfs(file_id), None, @@ -1416,7 +1417,7 @@ fn run_ide_things( annotate_enum_variant_references: false, location: ide::AnnotationLocation::AboveName, filter_adjacent_derive_implementations: false, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; for &file_id in file_ids { let msg = format!("annotations: {}", vfs.file_path(file_id.file_id(db))); diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/config.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/config.rs index 2ccd85f0e34e..3a88a8fe8480 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/config.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/config.rs @@ -12,7 +12,8 @@ CompletionFieldsToResolve, DiagnosticsConfig, GenericParameterHints, GotoDefinitionConfig, GotoImplementationConfig, HighlightConfig, HighlightRelatedConfig, HoverConfig, HoverDocFormat, InlayFieldsToResolve, InlayHintsConfig, JoinLinesConfig, MemoryLayoutHoverConfig, - MemoryLayoutHoverRenderKind, RenameConfig, Snippet, SnippetScope, SourceRootId, + MemoryLayoutHoverRenderKind, RaFixtureConfig, RenameConfig, Snippet, SnippetScope, + SourceRootId, }; use ide_db::{ MiniCore, SnippetCap, @@ -313,6 +314,9 @@ pub enum MaxSubstitutionLength { /// Hide inlay type hints for constructors. inlayHints_typeHints_hideNamedConstructor: bool = false, + /// Where to render type hints relative to their binding pattern. + inlayHints_typeHints_location: TypeHintsLocation = TypeHintsLocation::Inline, + /// Enable the experimental support for interpreting tests. interpret_tests: bool = false, @@ -727,6 +731,11 @@ pub enum MaxSubstitutionLength { /// the `Problems Panel`. diagnostics_warningsAsInfo: Vec = vec![], + /// Disable support for `#[rust_analyzer::rust_fixture]` snippets. + /// + /// If you are not working on rust-analyzer itself, you should ignore this config. + disableFixtureSupport: bool = false, + /// Enforce the import granularity setting for all files. If set to false rust-analyzer will /// try to keep import styles consistent per file. imports_granularity_enforce: bool = false, @@ -822,6 +831,9 @@ pub enum MaxSubstitutionLength { /// /// Set this to `"all"` to pass `--all-features` to cargo. cargo_features: CargoFeaturesDef = CargoFeaturesDef::Selected(vec![]), + /// Extra arguments passed only to `cargo metadata`, not to other cargo invocations. + /// Useful for flags like `--config` that `cargo metadata` supports. + cargo_metadataExtraArgs: Vec = vec![], /// Whether to pass `--no-default-features` to cargo. cargo_noDefaultFeatures: bool = false, /// Whether to skip fetching dependencies. If set to "true", the analysis is performed @@ -948,18 +960,30 @@ pub enum MaxSubstitutionLength { /// Override the command used for bench runnables. /// The first element of the array should be the program to execute (for example, `cargo`). /// - /// Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically - /// replace the package name, target option (such as `--bin` or `--example`), the target name and - /// the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). + /// Use the placeholders: + /// - `${package}`: package name. + /// - `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. + /// - `${target}`: target name (empty for `--lib`). + /// - `${test_name}`: the test path filter, e.g. `module::bench_func`. + /// - `${exact}`: `--exact` for single benchmarks, empty for modules. + /// - `${include_ignored}`: always empty for benchmarks. + /// - `${executable_args}`: all of the above binary args bundled together + /// (includes `rust-analyzer.runnables.extraTestBinaryArgs`). runnables_bench_overrideCommand: Option> = None, /// Command to be executed instead of 'cargo' for runnables. runnables_command: Option = None, - /// Override the command used for bench runnables. + /// Override the command used for doc-test runnables. /// The first element of the array should be the program to execute (for example, `cargo`). /// - /// Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically - /// replace the package name, target option (such as `--bin` or `--example`), the target name and - /// the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). + /// Use the placeholders: + /// - `${package}`: package name. + /// - `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. + /// - `${target}`: target name (empty for `--lib`). + /// - `${test_name}`: the test path filter, e.g. `module::func`. + /// - `${exact}`: always empty for doc-tests. + /// - `${include_ignored}`: always empty for doc-tests. + /// - `${executable_args}`: all of the above binary args bundled together + /// (includes `rust-analyzer.runnables.extraTestBinaryArgs`). runnables_doctest_overrideCommand: Option> = None, /// Additional arguments to be passed to cargo for runnables such as /// tests or binaries. For example, it may be `--release`. @@ -977,9 +1001,15 @@ pub enum MaxSubstitutionLength { /// Override the command used for test runnables. /// The first element of the array should be the program to execute (for example, `cargo`). /// - /// Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically - /// replace the package name, target option (such as `--bin` or `--example`), the target name and - /// the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). + /// Available placeholders: + /// - `${package}`: package name. + /// - `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. + /// - `${target}`: target name (empty for `--lib`). + /// - `${test_name}`: the test path filter, e.g. `module::test_func`. + /// - `${exact}`: `--exact` for single tests, empty for modules. + /// - `${include_ignored}`: `--include-ignored` for single tests, empty otherwise. + /// - `${executable_args}`: all of the above binary args bundled together + /// (includes `rust-analyzer.runnables.extraTestBinaryArgs`). runnables_test_overrideCommand: Option> = None, /// Path to the Cargo.toml of the rust compiler workspace, for usage in rustc_private @@ -1061,6 +1091,7 @@ struct ClientInfo { version: Option, } +/// The configuration of this rust-analyzer instance. #[derive(Clone)] pub struct Config { /// Projects that have a Cargo.toml or a rust-project.json in a @@ -1070,11 +1101,16 @@ pub struct Config { /// Projects whose configuration was generated by a command /// configured in discoverConfig. discovered_projects_from_command: Vec, - /// The workspace roots as registered by the LSP client + /// The workspace roots as registered by the LSP client. workspace_roots: Vec, caps: ClientCapabilities, - /// The LSP root path, deprecated in favor of `workspace_roots` + + /// The root of the first project encountered. This is deprecated + /// because rust-analyzer might be handling multiple projects. + /// + /// Prefer `workspace_roots` and `workspace_root_for()`. root_path: AbsPathBuf, + snippets: Vec, client_info: Option, @@ -1504,6 +1540,8 @@ pub struct LensConfig { // annotations pub location: AnnotationLocation, pub filter_adjacent_derive_implementations: bool, + + disable_ra_fixture: bool, } #[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize, Deserialize)] @@ -1559,7 +1597,7 @@ pub fn into_annotation_config<'a>( annotate_method_references: self.method_refs, annotate_enum_variant_references: self.enum_variant_refs, location: self.location.into(), - minicore, + ra_fixture: RaFixtureConfig { minicore, disable_ra_fixture: self.disable_ra_fixture }, filter_adjacent_derive_implementations: self.filter_adjacent_derive_implementations, } } @@ -1776,9 +1814,23 @@ fn sort_objects_by_field(json: &mut serde_json::Value) { s } - pub fn root_path(&self) -> &AbsPathBuf { - // We should probably use `workspace_roots` here if set - &self.root_path + /// Find the workspace root that contains the given path, using the + /// longest prefix match. + pub fn workspace_root_for(&self, path: &AbsPath) -> &AbsPathBuf { + self.workspace_roots + .iter() + .filter(|root| path.starts_with(root.as_path())) + .max_by_key(|root| root.as_str().len()) + .unwrap_or(self.default_root_path()) + } + + /// Best-effort root path for the current project. + /// + /// Use `workspace_root_for` where possible, because + /// `default_root_path` may return the wrong path when a user has + /// multiple workspaces. + pub fn default_root_path(&self) -> &AbsPathBuf { + self.workspace_roots.first().unwrap_or(&self.root_path) } pub fn caps(&self) -> &ClientCapabilities { @@ -1816,8 +1868,15 @@ pub fn rename(&self, source_root: Option) -> RenameConfig { } } + pub fn ra_fixture<'a>(&self, minicore: MiniCore<'a>) -> RaFixtureConfig<'a> { + RaFixtureConfig { minicore, disable_ra_fixture: *self.disableFixtureSupport(None) } + } + pub fn call_hierarchy<'a>(&self, minicore: MiniCore<'a>) -> CallHierarchyConfig<'a> { - CallHierarchyConfig { exclude_tests: self.references_excludeTests().to_owned(), minicore } + CallHierarchyConfig { + exclude_tests: self.references_excludeTests().to_owned(), + ra_fixture: self.ra_fixture(minicore), + } } pub fn completion<'a>( @@ -1878,7 +1937,7 @@ pub fn completion<'a>( }) .collect(), exclude_traits: self.completion_excludeTraits(source_root), - minicore, + ra_fixture: self.ra_fixture(minicore), } } @@ -1987,12 +2046,12 @@ pub fn hover<'a>(&self, minicore: MiniCore<'a>) -> HoverConfig<'a> { None => ide::SubstTyLen::Unlimited, }, show_drop_glue: *self.hover_dropGlue_enable(), - minicore, + ra_fixture: self.ra_fixture(minicore), } } pub fn goto_definition<'a>(&self, minicore: MiniCore<'a>) -> GotoDefinitionConfig<'a> { - GotoDefinitionConfig { minicore } + GotoDefinitionConfig { ra_fixture: self.ra_fixture(minicore) } } pub fn inlay_hints<'a>(&self, minicore: MiniCore<'a>) -> InlayHintsConfig<'a> { @@ -2001,6 +2060,10 @@ pub fn inlay_hints<'a>(&self, minicore: MiniCore<'a>) -> InlayHintsConfig<'a> { InlayHintsConfig { render_colons: self.inlayHints_renderColons().to_owned(), type_hints: self.inlayHints_typeHints_enable().to_owned(), + type_hints_placement: match self.inlayHints_typeHints_location() { + TypeHintsLocation::Inline => ide::TypeHintsPlacement::Inline, + TypeHintsLocation::EndOfLine => ide::TypeHintsPlacement::EndOfLine, + }, sized_bound: self.inlayHints_implicitSizedBoundHints_enable().to_owned(), parameter_hints: self.inlayHints_parameterHints_enable().to_owned(), parameter_hints_for_missing_arguments: self @@ -2082,7 +2145,7 @@ pub fn inlay_hints<'a>(&self, minicore: MiniCore<'a>) -> InlayHintsConfig<'a> { implicit_drop_hints: self.inlayHints_implicitDrops_enable().to_owned(), implied_dyn_trait_hints: self.inlayHints_impliedDynTraitHints_enable().to_owned(), range_exclusive_hints: self.inlayHints_rangeExclusiveHints_enable().to_owned(), - minicore, + ra_fixture: self.ra_fixture(minicore), } } @@ -2135,7 +2198,7 @@ pub fn highlighting_config<'a>(&self, minicore: MiniCore<'a>) -> HighlightConfig .to_owned(), inject_doc_comment: self.semanticHighlighting_doc_comment_inject_enable().to_owned(), syntactic_name_ref_highlighting: false, - minicore, + ra_fixture: self.ra_fixture(minicore), } } @@ -2402,6 +2465,7 @@ pub fn cargo(&self, source_root: Option) -> CargoConfig { target_dir_config: self.target_dir_from_config(source_root), set_test: *self.cfg_setTest(source_root), no_deps: *self.cargo_noDeps(source_root), + metadata_extra_args: self.cargo_metadataExtraArgs(source_root).clone(), } } @@ -2621,6 +2685,7 @@ pub fn lens(&self) -> LensConfig { location: *self.lens_location(), filter_adjacent_derive_implementations: *self .gotoImplementations_filterAdjacentDerives(), + disable_ra_fixture: *self.disableFixtureSupport(None), } } @@ -2997,6 +3062,13 @@ enum ClosureStyle { Hide, } +#[derive(Serialize, Deserialize, Debug, Clone)] +#[serde(rename_all = "snake_case")] +enum TypeHintsLocation { + Inline, + EndOfLine, +} + #[derive(Serialize, Deserialize, Debug, Clone)] #[serde(rename_all = "snake_case")] enum ReborrowHintsDef { @@ -3908,6 +3980,14 @@ macro_rules! set { "`hide`: Shows `...` for every closure type", ], }, + "TypeHintsLocation" => set! { + "type": "string", + "enum": ["inline", "end_of_line"], + "enumDescriptions": [ + "Render type hints directly after the binding identifier.", + "Render type hints after the end of the containing `let` statement when possible.", + ], + }, "Option" => set! { "anyOf": [ { diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/flycheck.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/flycheck.rs index c41696bf3f6a..aad8bece9554 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/flycheck.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/flycheck.rs @@ -673,27 +673,31 @@ fn run(mut self, inbox: Receiver) { if self.diagnostics_received == DiagnosticsReceived::NotYet { tracing::trace!(flycheck_id = self.id, "clearing diagnostics"); // We finished without receiving any diagnostics. - // Clear everything for good measure - match &self.scope { - FlycheckScope::Workspace => { - self.send(FlycheckMessage::ClearDiagnostics { - id: self.id, - kind: ClearDiagnosticsKind::All(ClearScope::Workspace), - }); - } - FlycheckScope::Package { package, workspace_deps } => { - for pkg in - std::iter::once(package).chain(workspace_deps.iter().flatten()) - { - self.send(FlycheckMessage::ClearDiagnostics { - id: self.id, - kind: ClearDiagnosticsKind::All(ClearScope::Package( - pkg.clone(), - )), - }); - } - } - } + // + // `cargo check` generally outputs something, even if there are no + // warnings/errors, so we always know which package was checked. + // + // ```text + // $ cargo check --message-format=json 2>/dev/null + // {"reason":"compiler-artifact","package_id":"path+file:///Users/wilfred/tmp/scratch#0.1.0",...} + // ``` + // + // However, rustc only returns JSON if there are diagnostics present, so a + // build without warnings or errors has an empty output. + // + // ``` + // $ rustc --error-format=json bad.rs + // {"$message_type":"diagnostic","message":"mismatched types","...} + // + // $ rustc --error-format=json good.rs + // ``` + // + // So if we got zero diagnostics, it was almost certainly a check that + // wasn't specific to a package. + self.send(FlycheckMessage::ClearDiagnostics { + id: self.id, + kind: ClearDiagnosticsKind::All(ClearScope::Workspace), + }); } else if res.is_ok() { // We clear diagnostics for packages on // `[CargoCheckMessage::CompilerArtifact]` but there seem to be setups where diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/handlers/request.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/handlers/request.rs index ad07da77597d..c1806c82c724 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/handlers/request.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/handlers/request.rs @@ -332,7 +332,7 @@ pub(crate) fn handle_view_crate_graph( params: ViewCrateGraphParams, ) -> anyhow::Result { let _p = tracing::info_span!("handle_view_crate_graph").entered(); - let dot = snap.analysis.view_crate_graph(params.full)?.map_err(anyhow::Error::msg)?; + let dot = snap.analysis.view_crate_graph(params.full)?; Ok(dot) } @@ -1264,11 +1264,15 @@ pub(crate) fn handle_folding_range( params: FoldingRangeParams, ) -> anyhow::Result>> { let _p = tracing::info_span!("handle_folding_range").entered(); + let file_id = try_default!(from_proto::file_id(&snap, ¶ms.text_document.uri)?); - let folds = snap.analysis.folding_ranges(file_id)?; + let collapsed_text = snap.config.folding_range_collapsed_text(); + let folds = snap.analysis.folding_ranges(file_id, collapsed_text)?; + let text = snap.analysis.file_text(file_id)?; let line_index = snap.file_line_index(file_id)?; let line_folding_only = snap.config.line_folding_only(); + let res = folds .into_iter() .map(|it| to_proto::folding_range(&text, &line_index, line_folding_only, it)) @@ -1395,7 +1399,10 @@ pub(crate) fn handle_references( let Some(refs) = snap.analysis.find_all_refs( position, - &FindAllRefsConfig { search_scope: None, minicore: snap.minicore() }, + &FindAllRefsConfig { + search_scope: None, + ra_fixture: snap.config.ra_fixture(snap.minicore()), + }, )? else { return Ok(None); @@ -2202,7 +2209,10 @@ fn show_ref_command_link( .analysis .find_all_refs( *position, - &FindAllRefsConfig { search_scope: None, minicore: snap.minicore() }, + &FindAllRefsConfig { + search_scope: None, + ra_fixture: snap.config.ra_fixture(snap.minicore()), + }, ) .unwrap_or(None) { @@ -2432,8 +2442,7 @@ fn run_rustfmt( } RustfmtConfig::CustomCommand { command, args } => { let cmd = Utf8PathBuf::from(&command); - let target_spec = - crates.first().and_then(|&crate_id| snap.target_spec_for_file(file_id, crate_id)); + let target_spec = TargetSpec::for_file(snap, file_id).ok().flatten(); let extra_env = snap.config.extra_env(source_root_id); let mut cmd = match target_spec { Some(TargetSpec::Cargo(_)) => { @@ -2443,7 +2452,14 @@ fn run_rustfmt( let cmd_path = if command.contains(std::path::MAIN_SEPARATOR) || (cfg!(windows) && command.contains('/')) { - snap.config.root_path().join(cmd).into() + let project_root = Utf8PathBuf::from_path_buf(current_dir.clone()) + .ok() + .and_then(|p| AbsPathBuf::try_from(p).ok()); + let project_root = project_root + .as_ref() + .map(|dir| snap.config.workspace_root_for(dir)) + .unwrap_or(snap.config.default_root_path()); + project_root.join(cmd).into() } else { cmd }; diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/integrated_benchmarks.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/integrated_benchmarks.rs index 6a74b8a54deb..af449c473a85 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/integrated_benchmarks.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/integrated_benchmarks.rs @@ -13,10 +13,10 @@ use hir::ChangeWithProcMacros; use ide::{ AnalysisHost, CallableSnippets, CompletionConfig, CompletionFieldsToResolve, DiagnosticsConfig, - FilePosition, TextSize, + FilePosition, RaFixtureConfig, TextSize, }; use ide_db::{ - MiniCore, SnippetCap, + SnippetCap, imports::insert_use::{ImportGranularity, InsertUseConfig}, }; use project_model::CargoConfig; @@ -190,7 +190,7 @@ fn integrated_completion_benchmark() { exclude_traits: &[], enable_auto_await: true, enable_auto_iter: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; let position = FilePosition { file_id, offset: TextSize::try_from(completion_offset).unwrap() }; @@ -245,7 +245,7 @@ fn integrated_completion_benchmark() { exclude_traits: &[], enable_auto_await: true, enable_auto_iter: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; let position = FilePosition { file_id, offset: TextSize::try_from(completion_offset).unwrap() }; @@ -298,7 +298,7 @@ fn integrated_completion_benchmark() { exclude_traits: &[], enable_auto_await: true, enable_auto_iter: true, - minicore: MiniCore::default(), + ra_fixture: RaFixtureConfig::default(), }; let position = FilePosition { file_id, offset: TextSize::try_from(completion_offset).unwrap() }; diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/capabilities.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/capabilities.rs index d6a694be9121..3ad4cb70b419 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/capabilities.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/capabilities.rs @@ -335,6 +335,20 @@ pub fn line_folding_only(&self) -> bool { .unwrap_or_default() } + pub fn folding_range_collapsed_text(&self) -> bool { + (|| -> _ { + self.0 + .text_document + .as_ref()? + .folding_range + .as_ref()? + .folding_range + .as_ref()? + .collapsed_text + })() + .unwrap_or_default() + } + pub fn hierarchical_symbols(&self) -> bool { (|| -> _ { self.0 diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/to_proto.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/to_proto.rs index e5b983dcbf85..5fa95252e7cb 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/to_proto.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/lsp/to_proto.rs @@ -913,9 +913,9 @@ pub(crate) fn folding_range( text: &str, line_index: &LineIndex, line_folding_only: bool, - fold: Fold, + Fold { range: text_range, kind, collapsed_text }: Fold, ) -> lsp_types::FoldingRange { - let kind = match fold.kind { + let kind = match kind { FoldKind::Comment => Some(lsp_types::FoldingRangeKind::Comment), FoldKind::Imports => Some(lsp_types::FoldingRangeKind::Imports), FoldKind::Region => Some(lsp_types::FoldingRangeKind::Region), @@ -930,17 +930,19 @@ pub(crate) fn folding_range( | FoldKind::Array | FoldKind::ExternCrates | FoldKind::MatchArm - | FoldKind::Function => None, + | FoldKind::Function + | FoldKind::Stmt(_) + | FoldKind::TailExpr(_) => None, }; - let range = range(line_index, fold.range); + let range = range(line_index, text_range); if line_folding_only { // Clients with line_folding_only == true (such as VSCode) will fold the whole end line // even if it contains text not in the folding range. To prevent that we exclude // range.end.line from the folding region if there is more text after range.end // on the same line. - let has_more_text_on_end_line = text[TextRange::new(fold.range.end(), TextSize::of(text))] + let has_more_text_on_end_line = text[TextRange::new(text_range.end(), TextSize::of(text))] .chars() .take_while(|it| *it != '\n') .any(|it| !it.is_whitespace()); @@ -951,13 +953,20 @@ pub(crate) fn folding_range( range.end.line }; + let collapsed_text = collapsed_text.map(|collapsed_text| { + let range_start = text_range.start(); + let line_start = range_start - TextSize::from(range.start.character); + let text_before_range = &text[TextRange::new(line_start, range_start)]; + format!("{text_before_range}{collapsed_text}") + }); + lsp_types::FoldingRange { start_line: range.start.line, start_character: None, end_line, end_character: None, kind, - collapsed_text: None, + collapsed_text, } } else { lsp_types::FoldingRange { @@ -966,7 +975,7 @@ pub(crate) fn folding_range( end_line: range.end.line, end_character: Some(range.end.character), kind, - collapsed_text: None, + collapsed_text, } } } @@ -2037,8 +2046,8 @@ fn main() { }"#; let (analysis, file_id) = Analysis::from_single_file(text.to_owned()); - let folds = analysis.folding_ranges(file_id).unwrap(); - assert_eq!(folds.len(), 4); + let folds = analysis.folding_ranges(file_id, true).unwrap(); + assert_eq!(folds.len(), 5); let line_index = LineIndex { index: Arc::new(ide::LineIndex::new(text)), @@ -2048,7 +2057,7 @@ fn main() { let converted: Vec = folds.into_iter().map(|it| folding_range(text, &line_index, true, it)).collect(); - let expected_lines = [(0, 2), (4, 10), (5, 6), (7, 9)]; + let expected_lines = [(0, 2), (4, 10), (5, 9), (5, 6), (7, 9)]; assert_eq!(converted.len(), expected_lines.len()); for (folding_range, (start_line, end_line)) in converted.iter().zip(expected_lines.iter()) { assert_eq!(folding_range.start_line, *start_line); diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/main_loop.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/main_loop.rs index 7c494de6f73d..a8c3d062d041 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/main_loop.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/main_loop.rs @@ -830,12 +830,19 @@ fn handle_task(&mut self, prime_caches_progress: &mut Vec, let command = cfg.command.clone(); let discover = DiscoverCommand::new(self.discover_sender.clone(), command); + let discover_path = match &arg { + DiscoverProjectParam::Buildfile(it) => it, + DiscoverProjectParam::Path(it) => it, + }; + let current_dir = + self.config.workspace_root_for(discover_path.as_path()).clone(); + let arg = match arg { DiscoverProjectParam::Buildfile(it) => DiscoverArgument::Buildfile(it), DiscoverProjectParam::Path(it) => DiscoverArgument::Path(it), }; - match discover.spawn(arg, self.config.root_path().as_ref()) { + match discover.spawn(arg, current_dir.as_ref()) { Ok(handle) => { if self.discover_jobs_active == 0 { let title = &cfg.progress_label.clone(); @@ -953,7 +960,7 @@ fn handle_vfs_msg( if let Some(dir) = dir { message += &format!( ": {}", - match dir.strip_prefix(self.config.root_path()) { + match dir.strip_prefix(self.config.workspace_root_for(&dir)) { Some(relative_path) => relative_path.as_utf8_path(), None => dir.as_ref(), } diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/reload.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/reload.rs index 83f4a19b39fa..1832275eb38d 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/reload.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/reload.rs @@ -390,7 +390,7 @@ pub(crate) fn fetch_build_data(&mut self, cause: Cause) { info!(%cause, "will fetch build data"); let workspaces = Arc::clone(&self.workspaces); let config = self.config.cargo(None); - let root_path = self.config.root_path().clone(); + let root_path = self.config.default_root_path().clone(); self.task_pool.handle.spawn_with_sender(ThreadIntent::Worker, move |sender| { sender.send(Task::FetchBuildData(BuildDataProgress::Begin)).unwrap(); @@ -582,7 +582,8 @@ pub(crate) fn switch_workspaces(&mut self, cause: Cause) { [ (base.clone(), "**/*.rs"), (base.clone(), "**/Cargo.{lock,toml}"), - (base, "**/rust-analyzer.toml"), + (base.clone(), "**/rust-analyzer.toml"), + (base, "**/*.md"), ] }) }) @@ -607,6 +608,7 @@ pub(crate) fn switch_workspaces(&mut self, cause: Cause) { format!("{base}/**/*.rs"), format!("{base}/**/Cargo.{{toml,lock}}"), format!("{base}/**/rust-analyzer.toml"), + format!("{base}/**/*.md"), ] }) }) @@ -883,7 +885,7 @@ fn reload_flycheck(&mut self) { config, crate::flycheck::FlycheckConfigJson::default(), None, - self.config.root_path().clone(), + self.config.default_root_path().clone(), None, None, )] @@ -975,6 +977,7 @@ pub(crate) fn should_refresh_for_change( change_kind: ChangeKind, additional_paths: &[&str], ) -> bool { + // Note: build scripts are retriggered on file save, no refresh is necessary const IMPLICIT_TARGET_FILES: &[&str] = &["build.rs", "src/main.rs", "src/lib.rs"]; const IMPLICIT_TARGET_DIRS: &[&str] = &["src/bin", "examples", "tests", "benches"]; @@ -991,15 +994,20 @@ pub(crate) fn should_refresh_for_change( return true; } + // .cargo/config{.toml} + if matches!(file_name, "config.toml" | "config") + && path.parent().map(|parent| parent.as_str().ends_with(".cargo")).unwrap_or(false) + { + return true; + } + + // Everything below only matters when files are created or deleted if change_kind == ChangeKind::Modify { return false; } - // .cargo/config{.toml} if path.extension().unwrap_or_default() != "rs" { - let is_cargo_config = matches!(file_name, "config.toml" | "config") - && path.parent().map(|parent| parent.as_str().ends_with(".cargo")).unwrap_or(false); - return is_cargo_config; + return false; } if IMPLICIT_TARGET_FILES.iter().any(|it| path.as_str().ends_with(it)) { diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/src/target_spec.rs b/src/tools/rust-analyzer/crates/rust-analyzer/src/target_spec.rs index 8be061cacfa8..5bdc9d8ca315 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/src/target_spec.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/src/target_spec.rs @@ -230,6 +230,18 @@ pub(crate) fn override_command( }; let test_name = test_name.unwrap_or_default(); + let exact = match kind { + RunnableKind::Test { test_id } | RunnableKind::Bench { test_id } => match test_id { + TestId::Path(_) => "--exact", + TestId::Name(_) => "", + }, + _ => "", + }; + let include_ignored = match kind { + RunnableKind::Test { .. } => "--include-ignored", + _ => "", + }; + let target_arg = |kind| match kind { TargetKind::Bin => "--bin", TargetKind::Test => "--test", @@ -249,7 +261,9 @@ pub(crate) fn override_command( .replace("${package}", &spec.package) .replace("${target_arg}", target_arg(spec.target_kind)) .replace("${target}", target(spec.target_kind, &spec.target)) - .replace("${test_name}", &test_name), + .replace("${test_name}", &test_name) + .replace("${exact}", exact) + .replace("${include_ignored}", include_ignored), _ => arg, }; @@ -274,15 +288,13 @@ fn executable_args_for( let mut executable_args = Vec::new(); match kind { - RunnableKind::Test { test_id, attr } => { + RunnableKind::Test { test_id } => { executable_args.push(test_id.to_string()); if let TestId::Path(_) = test_id { executable_args.push("--exact".to_owned()); } executable_args.extend(extra_test_binary_args); - if attr.ignore { - executable_args.push("--ignored".to_owned()); - } + executable_args.push("--include-ignored".to_owned()); } RunnableKind::TestMod { path } => { executable_args.push(path.clone()); @@ -369,23 +381,13 @@ mod tests { SmolStr, ast::{self, AstNode}, }; - use syntax_bridge::{ - DocCommentDesugarMode, - dummy_test_span_utils::{DUMMY, DummyTestSpanMap}, - syntax_node_to_token_tree, - }; fn check(cfg: &str, expected_features: &[&str]) { let cfg_expr = { let source_file = ast::SourceFile::parse(cfg, Edition::CURRENT).ok().unwrap(); - let tt = source_file.syntax().descendants().find_map(ast::TokenTree::cast).unwrap(); - let tt = syntax_node_to_token_tree( - tt.syntax(), - &DummyTestSpanMap, - DUMMY, - DocCommentDesugarMode::Mbe, - ); - CfgExpr::parse(&tt) + let cfg_predicate = + source_file.syntax().descendants().find_map(ast::CfgPredicate::cast).unwrap(); + CfgExpr::parse_from_ast(cfg_predicate) }; let mut features = vec![]; diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/flycheck.rs b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/flycheck.rs index c1d53fb33ab6..c6f1f81139d2 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/flycheck.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/flycheck.rs @@ -110,3 +110,45 @@ fn main() {} diagnostics.diagnostics, ); } + +#[test] +fn test_flycheck_diagnostics_with_override_command_cleared_after_fix() { + if skip_slow_tests() { + return; + } + + // Start with a program that is lint clean. + let server = Project::with_fixture( + r#" +//- /Cargo.toml +[package] +name = "foo" +version = "0.0.0" + +//- /src/main.rs +fn main() {} +"#, + ) + .with_config(serde_json::json!({ + "checkOnSave": true, + "check": { + "overrideCommand": ["rustc", "--error-format=json", "$saved_file"] + } + })) + .server() + .wait_until_workspace_is_loaded(); + + // Introduce an unused variable. + server.write_file_and_save("src/main.rs", "fn main() {\n let x = 1;\n}\n".to_owned()); + + let diags = server.wait_for_diagnostics(); + assert!( + diags.diagnostics.iter().any(|d| d.message.contains("unused variable")), + "expected unused variable diagnostic, got: {:?}", + diags.diagnostics, + ); + + // Fix it and verify that diagnostics are cleared. + server.write_file_and_save("src/main.rs", "fn main() {\n let _x = 1;\n}\n".to_owned()); + server.wait_for_diagnostics_cleared(); +} diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/main.rs b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/main.rs index fcdc8bb7cdd0..3c57e36b4fe9 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/main.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/main.rs @@ -262,7 +262,7 @@ fn main() {} { "args": { "cargoArgs": ["test", "--package", "foo", "--test", "spam"], - "executableArgs": ["test_eggs", "--exact", "--nocapture"], + "executableArgs": ["test_eggs", "--exact", "--nocapture", "--include-ignored"], "overrideCargo": null, "cwd": server.path().join("foo"), "workspaceRoot": server.path().join("foo") diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/ratoml.rs b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/ratoml.rs index cac7efd84aaf..dd113babffeb 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/ratoml.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/ratoml.rs @@ -1008,3 +1008,45 @@ fn main() { InternalTestingFetchConfigResponse::CheckWorkspace(true), ); } + +#[test] +fn ratoml_virtual_workspace() { + if skip_slow_tests() { + return; + } + + let server = RatomlTest::new( + vec![ + r#" +//- /p1/Cargo.toml +[workspace] +members = ["member"] +"#, + r#" +//- /p1/rust-analyzer.toml +assist.emitMustUse = true +"#, + r#" +//- /p1/member/Cargo.toml +[package] +name = "member" +version = "0.1.0" +edition = "2021" +"#, + r#" +//- /p1/member/src/lib.rs +pub fn add(left: usize, right: usize) -> usize { + left + right +} +"#, + ], + vec!["p1"], + None, + ); + + server.query( + InternalTestingFetchConfigOption::AssistEmitMustUse, + 3, + InternalTestingFetchConfigResponse::AssistEmitMustUse(true), + ); +} diff --git a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/support.rs b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/support.rs index 7ee31f3d53ea..73904036730b 100644 --- a/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/support.rs +++ b/src/tools/rust-analyzer/crates/rust-analyzer/tests/slow-tests/support.rs @@ -173,7 +173,8 @@ pub(crate) fn server_with_lock(self, config_lock: bool) -> Server { chalk_filter: std::env::var("CHALK_DEBUG").ok(), profile_filter: std::env::var("RA_PROFILE").ok(), json_profile_filter: std::env::var("RA_PROFILE_JSON").ok(), - }; + } + .init(); }); let FixtureWithProjectMeta { diff --git a/src/tools/rust-analyzer/crates/syntax/Cargo.toml b/src/tools/rust-analyzer/crates/syntax/Cargo.toml index 8909fb423c4d..e65836ed8dcb 100644 --- a/src/tools/rust-analyzer/crates/syntax/Cargo.toml +++ b/src/tools/rust-analyzer/crates/syntax/Cargo.toml @@ -21,6 +21,7 @@ rustc-literal-escaper.workspace = true smol_str.workspace = true triomphe.workspace = true tracing.workspace = true +smallvec.workspace = true parser.workspace = true stdx.workspace = true diff --git a/src/tools/rust-analyzer/crates/syntax/rust.ungram b/src/tools/rust-analyzer/crates/syntax/rust.ungram index 3113fc74308b..324b2bbd58e1 100644 --- a/src/tools/rust-analyzer/crates/syntax/rust.ungram +++ b/src/tools/rust-analyzer/crates/syntax/rust.ungram @@ -126,9 +126,41 @@ MacroStmts = Attr = '#' '!'? '[' Meta ']' +CfgAttrMeta = + 'cfg_attr' '(' CfgPredicate ',' (Meta (',' Meta)* ','?) ')' + +CfgMeta = + 'cfg' '(' CfgPredicate ','? ')' + +CfgPredicate = + CfgAtom +| CfgComposite + +CfgAtom = + ('#ident' | 'true' | 'false') ('=' '@string')? + +CfgComposite = + keyword:'#ident' '(' (CfgPredicate (',' CfgPredicate)* ','?) ')' + Meta = - 'unsafe' '(' Path ('=' Expr | TokenTree)? ')' -| Path ('=' Expr | TokenTree)? + CfgAttrMeta +| CfgMeta +| UnsafeMeta +| PathMeta +| KeyValueMeta +| TokenTreeMeta + +UnsafeMeta = + 'unsafe' '(' Meta ')' + +PathMeta = + Path + +KeyValueMeta = + Path '=' Expr + +TokenTreeMeta = + Path TokenTree //*************************// // Items // diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast.rs b/src/tools/rust-analyzer/crates/syntax/src/ast.rs index 5d67fd449175..dc592a43727b 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast.rs @@ -25,9 +25,9 @@ expr_ext::{ArrayExprKind, BlockModifier, CallableExpr, ElseBranch, LiteralKind}, generated::{nodes::*, tokens::*}, node_ext::{ - AttrKind, FieldKind, Macro, NameLike, NameOrNameRef, PathSegmentKind, SelfParamKind, - SlicePatComponents, StructKind, TokenTreeChildren, TypeBoundKind, TypeOrConstParam, - VisibilityKind, + AttrKind, CfgAtomKey, FieldKind, Macro, NameLike, NameOrNameRef, PathSegmentKind, + SelfParamKind, SlicePatComponents, StructKind, TokenTreeChildren, TypeBoundKind, + TypeOrConstParam, VisibilityKind, }, operators::{ArithOp, BinaryOp, CmpOp, LogicOp, Ordering, RangeOp, UnaryOp}, token_ext::{ diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/edit.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/edit.rs index b706d7f722f4..23a0411eadbd 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/edit.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/edit.rs @@ -105,8 +105,7 @@ pub(super) fn increase_indent(self, node: &SyntaxNode) { } pub(super) fn clone_increase_indent(self, node: &SyntaxNode) -> SyntaxNode { - let node = node.clone_subtree(); - let mut editor = SyntaxEditor::new(node.clone()); + let (mut editor, node) = SyntaxEditor::new(node.clone()); let tokens = node .preorder_with_tokens() .filter_map(|event| match event { @@ -140,8 +139,7 @@ pub(super) fn decrease_indent(self, node: &SyntaxNode) { } pub(super) fn clone_decrease_indent(self, node: &SyntaxNode) -> SyntaxNode { - let node = node.clone_subtree(); - let mut editor = SyntaxEditor::new(node.clone()); + let (mut editor, node) = SyntaxEditor::new(node.clone()); let tokens = node .preorder_with_tokens() .filter_map(|event| match event { diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/generated/nodes.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/generated/nodes.rs index 7334de0fd96f..cd7f6a018ab2 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/generated/nodes.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/generated/nodes.rs @@ -377,6 +377,68 @@ pub fn ty(&self) -> Option { support::child(&self.syntax) } #[inline] pub fn as_token(&self) -> Option { support::token(&self.syntax, T![as]) } } +pub struct CfgAtom { + pub(crate) syntax: SyntaxNode, +} +impl CfgAtom { + #[inline] + pub fn eq_token(&self) -> Option { support::token(&self.syntax, T![=]) } + #[inline] + pub fn false_token(&self) -> Option { support::token(&self.syntax, T![false]) } + #[inline] + pub fn ident_token(&self) -> Option { support::token(&self.syntax, T![ident]) } + #[inline] + pub fn string_token(&self) -> Option { support::token(&self.syntax, T![string]) } + #[inline] + pub fn true_token(&self) -> Option { support::token(&self.syntax, T![true]) } +} +pub struct CfgAttrMeta { + pub(crate) syntax: SyntaxNode, +} +impl CfgAttrMeta { + #[inline] + pub fn cfg_predicate(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn metas(&self) -> AstChildren { support::children(&self.syntax) } + #[inline] + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + #[inline] + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } + #[inline] + pub fn comma_token(&self) -> Option { support::token(&self.syntax, T![,]) } + #[inline] + pub fn cfg_attr_token(&self) -> Option { + support::token(&self.syntax, T![cfg_attr]) + } +} +pub struct CfgComposite { + pub(crate) syntax: SyntaxNode, +} +impl CfgComposite { + #[inline] + pub fn cfg_predicates(&self) -> AstChildren { support::children(&self.syntax) } + #[inline] + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + #[inline] + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } + #[inline] + pub fn keyword(&self) -> Option { support::token(&self.syntax, T![ident]) } +} +pub struct CfgMeta { + pub(crate) syntax: SyntaxNode, +} +impl CfgMeta { + #[inline] + pub fn cfg_predicate(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + #[inline] + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } + #[inline] + pub fn comma_token(&self) -> Option { support::token(&self.syntax, T![,]) } + #[inline] + pub fn cfg_token(&self) -> Option { support::token(&self.syntax, T![cfg]) } +} pub struct ClosureExpr { pub(crate) syntax: SyntaxNode, } @@ -783,6 +845,17 @@ pub fn l_curly_token(&self) -> Option { support::token(&self.syntax #[inline] pub fn r_curly_token(&self) -> Option { support::token(&self.syntax, T!['}']) } } +pub struct KeyValueMeta { + pub(crate) syntax: SyntaxNode, +} +impl KeyValueMeta { + #[inline] + pub fn expr(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn path(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn eq_token(&self) -> Option { support::token(&self.syntax, T![=]) } +} pub struct Label { pub(crate) syntax: SyntaxNode, } @@ -1012,25 +1085,6 @@ impl MatchGuard { #[inline] pub fn if_token(&self) -> Option { support::token(&self.syntax, T![if]) } } -pub struct Meta { - pub(crate) syntax: SyntaxNode, -} -impl Meta { - #[inline] - pub fn expr(&self) -> Option { support::child(&self.syntax) } - #[inline] - pub fn path(&self) -> Option { support::child(&self.syntax) } - #[inline] - pub fn token_tree(&self) -> Option { support::child(&self.syntax) } - #[inline] - pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } - #[inline] - pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } - #[inline] - pub fn eq_token(&self) -> Option { support::token(&self.syntax, T![=]) } - #[inline] - pub fn unsafe_token(&self) -> Option { support::token(&self.syntax, T![unsafe]) } -} pub struct MethodCallExpr { pub(crate) syntax: SyntaxNode, } @@ -1225,6 +1279,13 @@ impl PathExpr { #[inline] pub fn path(&self) -> Option { support::child(&self.syntax) } } +pub struct PathMeta { + pub(crate) syntax: SyntaxNode, +} +impl PathMeta { + #[inline] + pub fn path(&self) -> Option { support::child(&self.syntax) } +} pub struct PathPat { pub(crate) syntax: SyntaxNode, } @@ -1607,6 +1668,15 @@ pub fn l_curly_token(&self) -> Option { support::token(&self.syntax #[inline] pub fn r_curly_token(&self) -> Option { support::token(&self.syntax, T!['}']) } } +pub struct TokenTreeMeta { + pub(crate) syntax: SyntaxNode, +} +impl TokenTreeMeta { + #[inline] + pub fn path(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn token_tree(&self) -> Option { support::child(&self.syntax) } +} pub struct Trait { pub(crate) syntax: SyntaxNode, } @@ -1834,6 +1904,19 @@ pub fn record_field_list(&self) -> Option { support::child(&sel #[inline] pub fn union_token(&self) -> Option { support::token(&self.syntax, T![union]) } } +pub struct UnsafeMeta { + pub(crate) syntax: SyntaxNode, +} +impl UnsafeMeta { + #[inline] + pub fn meta(&self) -> Option { support::child(&self.syntax) } + #[inline] + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + #[inline] + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } + #[inline] + pub fn unsafe_token(&self) -> Option { support::token(&self.syntax, T![unsafe]) } +} pub struct Use { pub(crate) syntax: SyntaxNode, } @@ -2024,6 +2107,12 @@ pub enum AssocItem { impl ast::HasAttrs for AssocItem {} impl ast::HasDocComments for AssocItem {} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub enum CfgPredicate { + CfgAtom(CfgAtom), + CfgComposite(CfgComposite), +} + #[derive(Debug, Clone, PartialEq, Eq, Hash)] pub enum Expr { ArrayExpr(ArrayExpr), @@ -2118,6 +2207,16 @@ pub enum Item { } impl ast::HasAttrs for Item {} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub enum Meta { + CfgAttrMeta(CfgAttrMeta), + CfgMeta(CfgMeta), + KeyValueMeta(KeyValueMeta), + PathMeta(PathMeta), + TokenTreeMeta(TokenTreeMeta), + UnsafeMeta(UnsafeMeta), +} + #[derive(Debug, Clone, PartialEq, Eq, Hash)] pub enum Pat { BoxPat(BoxPat), @@ -3133,6 +3232,134 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("CastExpr").field("syntax", &self.syntax).finish() } } +impl AstNode for CfgAtom { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + CFG_ATOM + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == CFG_ATOM } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for CfgAtom { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for CfgAtom {} +impl PartialEq for CfgAtom { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for CfgAtom { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for CfgAtom { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CfgAtom").field("syntax", &self.syntax).finish() + } +} +impl AstNode for CfgAttrMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + CFG_ATTR_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == CFG_ATTR_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for CfgAttrMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for CfgAttrMeta {} +impl PartialEq for CfgAttrMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for CfgAttrMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for CfgAttrMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CfgAttrMeta").field("syntax", &self.syntax).finish() + } +} +impl AstNode for CfgComposite { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + CFG_COMPOSITE + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == CFG_COMPOSITE } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for CfgComposite { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for CfgComposite {} +impl PartialEq for CfgComposite { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for CfgComposite { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for CfgComposite { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CfgComposite").field("syntax", &self.syntax).finish() + } +} +impl AstNode for CfgMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + CFG_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == CFG_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for CfgMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for CfgMeta {} +impl PartialEq for CfgMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for CfgMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for CfgMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CfgMeta").field("syntax", &self.syntax).finish() + } +} impl AstNode for ClosureExpr { #[inline] fn kind() -> SyntaxKind @@ -4093,6 +4320,38 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("ItemList").field("syntax", &self.syntax).finish() } } +impl AstNode for KeyValueMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + KEY_VALUE_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == KEY_VALUE_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for KeyValueMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for KeyValueMeta {} +impl PartialEq for KeyValueMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for KeyValueMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for KeyValueMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("KeyValueMeta").field("syntax", &self.syntax).finish() + } +} impl AstNode for Label { #[inline] fn kind() -> SyntaxKind @@ -4797,38 +5056,6 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("MatchGuard").field("syntax", &self.syntax).finish() } } -impl AstNode for Meta { - #[inline] - fn kind() -> SyntaxKind - where - Self: Sized, - { - META - } - #[inline] - fn can_cast(kind: SyntaxKind) -> bool { kind == META } - #[inline] - fn cast(syntax: SyntaxNode) -> Option { - if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } - } - #[inline] - fn syntax(&self) -> &SyntaxNode { &self.syntax } -} -impl hash::Hash for Meta { - fn hash(&self, state: &mut H) { self.syntax.hash(state); } -} -impl Eq for Meta {} -impl PartialEq for Meta { - fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } -} -impl Clone for Meta { - fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } -} -impl fmt::Debug for Meta { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_struct("Meta").field("syntax", &self.syntax).finish() - } -} impl AstNode for MethodCallExpr { #[inline] fn kind() -> SyntaxKind @@ -5309,6 +5536,38 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("PathExpr").field("syntax", &self.syntax).finish() } } +impl AstNode for PathMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + PATH_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == PATH_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for PathMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for PathMeta {} +impl PartialEq for PathMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for PathMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for PathMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("PathMeta").field("syntax", &self.syntax).finish() + } +} impl AstNode for PathPat { #[inline] fn kind() -> SyntaxKind @@ -6301,6 +6560,38 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("TokenTree").field("syntax", &self.syntax).finish() } } +impl AstNode for TokenTreeMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + TOKEN_TREE_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == TOKEN_TREE_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for TokenTreeMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for TokenTreeMeta {} +impl PartialEq for TokenTreeMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for TokenTreeMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for TokenTreeMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("TokenTreeMeta").field("syntax", &self.syntax).finish() + } +} impl AstNode for Trait { #[inline] fn kind() -> SyntaxKind @@ -6845,6 +7136,38 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { f.debug_struct("Union").field("syntax", &self.syntax).finish() } } +impl AstNode for UnsafeMeta { + #[inline] + fn kind() -> SyntaxKind + where + Self: Sized, + { + UNSAFE_META + } + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { kind == UNSAFE_META } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { Some(Self { syntax }) } else { None } + } + #[inline] + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl hash::Hash for UnsafeMeta { + fn hash(&self, state: &mut H) { self.syntax.hash(state); } +} +impl Eq for UnsafeMeta {} +impl PartialEq for UnsafeMeta { + fn eq(&self, other: &Self) -> bool { self.syntax == other.syntax } +} +impl Clone for UnsafeMeta { + fn clone(&self) -> Self { Self { syntax: self.syntax.clone() } } +} +impl fmt::Debug for UnsafeMeta { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("UnsafeMeta").field("syntax", &self.syntax).finish() + } +} impl AstNode for Use { #[inline] fn kind() -> SyntaxKind @@ -7413,6 +7736,34 @@ fn syntax(&self) -> &SyntaxNode { } } } +impl From for CfgPredicate { + #[inline] + fn from(node: CfgAtom) -> CfgPredicate { CfgPredicate::CfgAtom(node) } +} +impl From for CfgPredicate { + #[inline] + fn from(node: CfgComposite) -> CfgPredicate { CfgPredicate::CfgComposite(node) } +} +impl AstNode for CfgPredicate { + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { matches!(kind, CFG_ATOM | CFG_COMPOSITE) } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + let res = match syntax.kind() { + CFG_ATOM => CfgPredicate::CfgAtom(CfgAtom { syntax }), + CFG_COMPOSITE => CfgPredicate::CfgComposite(CfgComposite { syntax }), + _ => return None, + }; + Some(res) + } + #[inline] + fn syntax(&self) -> &SyntaxNode { + match self { + CfgPredicate::CfgAtom(it) => &it.syntax, + CfgPredicate::CfgComposite(it) => &it.syntax, + } + } +} impl From for Expr { #[inline] fn from(node: ArrayExpr) -> Expr { Expr::ArrayExpr(node) } @@ -7970,6 +8321,63 @@ fn syntax(&self) -> &SyntaxNode { } } } +impl From for Meta { + #[inline] + fn from(node: CfgAttrMeta) -> Meta { Meta::CfgAttrMeta(node) } +} +impl From for Meta { + #[inline] + fn from(node: CfgMeta) -> Meta { Meta::CfgMeta(node) } +} +impl From for Meta { + #[inline] + fn from(node: KeyValueMeta) -> Meta { Meta::KeyValueMeta(node) } +} +impl From for Meta { + #[inline] + fn from(node: PathMeta) -> Meta { Meta::PathMeta(node) } +} +impl From for Meta { + #[inline] + fn from(node: TokenTreeMeta) -> Meta { Meta::TokenTreeMeta(node) } +} +impl From for Meta { + #[inline] + fn from(node: UnsafeMeta) -> Meta { Meta::UnsafeMeta(node) } +} +impl AstNode for Meta { + #[inline] + fn can_cast(kind: SyntaxKind) -> bool { + matches!( + kind, + CFG_ATTR_META | CFG_META | KEY_VALUE_META | PATH_META | TOKEN_TREE_META | UNSAFE_META + ) + } + #[inline] + fn cast(syntax: SyntaxNode) -> Option { + let res = match syntax.kind() { + CFG_ATTR_META => Meta::CfgAttrMeta(CfgAttrMeta { syntax }), + CFG_META => Meta::CfgMeta(CfgMeta { syntax }), + KEY_VALUE_META => Meta::KeyValueMeta(KeyValueMeta { syntax }), + PATH_META => Meta::PathMeta(PathMeta { syntax }), + TOKEN_TREE_META => Meta::TokenTreeMeta(TokenTreeMeta { syntax }), + UNSAFE_META => Meta::UnsafeMeta(UnsafeMeta { syntax }), + _ => return None, + }; + Some(res) + } + #[inline] + fn syntax(&self) -> &SyntaxNode { + match self { + Meta::CfgAttrMeta(it) => &it.syntax, + Meta::CfgMeta(it) => &it.syntax, + Meta::KeyValueMeta(it) => &it.syntax, + Meta::PathMeta(it) => &it.syntax, + Meta::TokenTreeMeta(it) => &it.syntax, + Meta::UnsafeMeta(it) => &it.syntax, + } + } +} impl From for Pat { #[inline] fn from(node: BoxPat) -> Pat { Pat::BoxPat(node) } @@ -9334,6 +9742,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for CfgPredicate { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for Expr { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -9364,6 +9777,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for Meta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for Pat { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -9524,6 +9942,26 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for CfgAtom { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for CfgAttrMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for CfgComposite { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for CfgMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for ClosureExpr { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -9674,6 +10112,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for KeyValueMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for Label { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -9784,11 +10227,6 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } -impl std::fmt::Display for Meta { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - std::fmt::Display::fmt(self.syntax(), f) - } -} impl std::fmt::Display for MethodCallExpr { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -9864,6 +10302,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for PathMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for PathPat { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -10019,6 +10462,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for TokenTreeMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for Trait { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -10104,6 +10552,11 @@ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for UnsafeMeta { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for Use { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/make.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/make.rs index 00971569a2ef..ac02cc9e43fd 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/make.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/make.rs @@ -1322,6 +1322,18 @@ pub fn meta_path(path: ast::Path) -> ast::Meta { ast_from_text(&format!("#[{path}]")) } +pub fn cfg_attr_meta( + predicate: ast::CfgPredicate, + inner: impl IntoIterator, +) -> ast::CfgAttrMeta { + let inner = inner.into_iter().join(", "); + ast_from_text(&format!("#![cfg_attr({predicate}, {inner})]")) +} + +pub fn cfg_flag(flag: &str) -> ast::CfgPredicate { + ast_from_text(&format!("#![cfg({flag})]")) +} + pub fn token_tree( delimiter: SyntaxKind, tt: impl IntoIterator>, diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/node_ext.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/node_ext.rs index 63e4608d0f63..03118d01dc90 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/node_ext.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/node_ext.rs @@ -8,6 +8,7 @@ use itertools::Itertools; use parser::SyntaxKind; use rowan::{GreenNodeData, GreenTokenData}; +use smallvec::{SmallVec, smallvec}; use crate::{ NodeOrToken, SmolStr, SyntaxElement, SyntaxElementChildren, SyntaxToken, T, TokenText, @@ -77,6 +78,15 @@ fn first_token(green_ref: &GreenNodeData) -> &GreenTokenData { } } +fn into_comma(it: NodeOrToken) -> Option { + let token = match it { + NodeOrToken::Token(it) => it, + NodeOrToken::Node(node) if node.kind() == SyntaxKind::ERROR => node.first_token()?, + NodeOrToken::Node(_) => return None, + }; + (token.kind() == T![,]).then_some(token) +} + impl ast::Abi { pub fn abi_string(&self) -> Option { support::token(&self.syntax, SyntaxKind::STRING).and_then(ast::String::cast) @@ -192,36 +202,82 @@ pub fn is_outer(&self) -> bool { } } -impl ast::Attr { +impl ast::Meta { pub fn as_simple_atom(&self) -> Option { - let meta = self.meta()?; - if meta.eq_token().is_some() || meta.token_tree().is_some() { - return None; - } - self.simple_name() + Some(self.as_simple_path()?.as_single_name_ref()?.text().into()) } pub fn as_simple_call(&self) -> Option<(SmolStr, ast::TokenTree)> { - let tt = self.meta()?.token_tree()?; - Some((self.simple_name()?, tt)) + let ast::Meta::TokenTreeMeta(meta) = self else { return None }; + Some((meta.path()?.as_single_name_ref()?.text().into(), meta.token_tree()?)) } pub fn as_simple_path(&self) -> Option { - let meta = self.meta()?; - if meta.eq_token().is_some() || meta.token_tree().is_some() { - return None; - } - self.path() + let ast::Meta::PathMeta(meta) = self else { return None }; + meta.path() } pub fn simple_name(&self) -> Option { - let path = self.meta()?.path()?; - match (path.segment(), path.qualifier()) { - (Some(segment), None) => Some(segment.syntax().first_token()?.text().into()), - _ => None, + match self { + ast::Meta::CfgAttrMeta(_) => Some(SmolStr::new_static("cfg_attr")), + ast::Meta::CfgMeta(_) => Some(SmolStr::new_static("cfg")), + _ => { + let path = self.path()?; + match (path.segment(), path.qualifier()) { + (Some(segment), None) => Some(segment.syntax().first_token()?.text().into()), + _ => None, + } + } } } + pub fn path(&self) -> Option { + match self { + ast::Meta::CfgAttrMeta(_) | ast::Meta::CfgMeta(_) => None, + ast::Meta::KeyValueMeta(it) => it.path(), + ast::Meta::PathMeta(it) => it.path(), + ast::Meta::TokenTreeMeta(it) => it.path(), + ast::Meta::UnsafeMeta(it) => it.meta()?.path(), + } + } + + /// Includes `cfg_attr()` inner metas (without considering the predicate). + pub fn skip_cfg_attrs(self) -> SmallVec<[ast::Meta; 1]> { + match self { + ast::Meta::CfgAttrMeta(meta) => { + meta.metas().flat_map(|meta| meta.skip_cfg_attrs()).collect() + } + _ => smallvec![self], + } + } + + /// FIXME: Calling this is almost always incorrect, as `cfg_attr` can contains multiple `Meta`s. + pub fn parent_attr(&self) -> Option { + self.syntax().ancestors().find_map(ast::Attr::cast) + } +} + +impl ast::Attr { + pub fn as_simple_atom(&self) -> Option { + self.meta().and_then(|meta| meta.as_simple_atom()) + } + + pub fn as_simple_call(&self) -> Option<(SmolStr, ast::TokenTree)> { + self.meta().and_then(|meta| meta.as_simple_call()) + } + + pub fn as_simple_path(&self) -> Option { + self.meta().and_then(|meta| meta.as_simple_path()) + } + + pub fn simple_name(&self) -> Option { + self.meta().and_then(|meta| meta.simple_name()) + } + + pub fn path(&self) -> Option { + self.meta().and_then(|meta| meta.path()) + } + pub fn kind(&self) -> AttrKind { match self.excl_token() { Some(_) => AttrKind::Inner, @@ -229,16 +285,12 @@ pub fn kind(&self) -> AttrKind { } } - pub fn path(&self) -> Option { - self.meta()?.path() - } - - pub fn expr(&self) -> Option { - self.meta()?.expr() - } - - pub fn token_tree(&self) -> Option { - self.meta()?.token_tree() + /// Includes `cfg_attr()` inner metas (without considering the predicate). + pub fn skip_cfg_attrs(&self) -> SmallVec<[ast::Meta; 1]> { + match self.meta() { + Some(meta) => meta.skip_cfg_attrs(), + None => SmallVec::new(), + } } } @@ -1006,12 +1058,6 @@ pub fn parent_meta(&self) -> Option { } } -impl ast::Meta { - pub fn parent_attr(&self) -> Option { - self.syntax().parent().and_then(ast::Attr::cast) - } -} - impl ast::GenericArgList { pub fn lifetime_args(&self) -> impl Iterator { self.generic_args().filter_map(|arg| match arg { @@ -1037,6 +1083,21 @@ pub fn type_or_const_params(&self) -> impl Iterator impl Iterator> { + // (Expr? ','?)* + let mut after_arg = false; + self.syntax().children_with_tokens().filter_map(move |it| { + if into_comma(it.clone()).is_some() { + if std::mem::take(&mut after_arg) { None } else { Some(None) } + } else { + Some(ast::Expr::cast(it.into_node()?).inspect(|_| after_arg = true)) + } + }) + } +} + impl ast::ForExpr { pub fn iterable(&self) -> Option { // If the iterable is a BlockExpr, check if the body is missing. @@ -1140,6 +1201,25 @@ pub fn leading_pipe(&self) -> Option { } } +#[derive(Debug, Clone)] +pub enum CfgAtomKey { + True, + False, + Ident(SyntaxToken), +} + +impl ast::CfgAtom { + pub fn key(&self) -> Option { + if self.true_token().is_some() { + Some(CfgAtomKey::True) + } else if self.false_token().is_some() { + Some(CfgAtomKey::False) + } else { + self.ident_token().map(CfgAtomKey::Ident) + } + } +} + /// An iterator over the elements in an [`ast::TokenTree`]. /// /// Does not yield trivia or the delimiters. diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/syntax_factory/constructors.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/syntax_factory/constructors.rs index 44114a780295..c66f096e8342 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/syntax_factory/constructors.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/syntax_factory/constructors.rs @@ -1848,7 +1848,36 @@ pub fn meta_token_tree(&self, path: ast::Path, tt: ast::TokenTree) -> ast::Meta if let Some(mut mapping) = self.mappings() { let mut builder = SyntaxMappingBuilder::new(ast.syntax().clone()); builder.map_node(path.syntax().clone(), ast.path().unwrap().syntax().clone()); - builder.map_node(tt.syntax().clone(), ast.token_tree().unwrap().syntax().clone()); + let ast::Meta::TokenTreeMeta(meta) = &ast else { unreachable!() }; + builder.map_node(tt.syntax().clone(), meta.token_tree().unwrap().syntax().clone()); + builder.finish(&mut mapping); + } + + ast + } + + pub fn cfg_flag(&self, flag: &str) -> ast::CfgPredicate { + make::cfg_flag(flag).clone_for_update() + } + + pub fn cfg_attr_meta( + &self, + predicate: ast::CfgPredicate, + inner: impl IntoIterator, + ) -> ast::CfgAttrMeta { + let inner = Vec::from_iter(inner); + let ast = make::cfg_attr_meta(predicate.clone(), inner.iter().cloned()).clone_for_update(); + + if let Some(mut mapping) = self.mappings() { + let mut builder = SyntaxMappingBuilder::new(ast.syntax().clone()); + builder.map_node( + predicate.syntax().clone(), + ast.cfg_predicate().unwrap().syntax().clone(), + ); + builder.map_children( + inner.iter().map(|it| it.syntax().clone()), + ast.metas().map(|it| it.syntax().clone()), + ); builder.finish(&mut mapping); } @@ -1960,6 +1989,47 @@ pub fn impl_( ast } + pub fn trait_( + &self, + is_unsafe: bool, + ident: &str, + generic_param_list: Option, + where_clause: Option, + assoc_items: ast::AssocItemList, + ) -> ast::Trait { + let ast = make::trait_( + is_unsafe, + ident, + generic_param_list.clone(), + where_clause.clone(), + assoc_items.clone(), + ) + .clone_for_update(); + + if let Some(mut mapping) = self.mappings() { + let mut builder = SyntaxMappingBuilder::new(ast.syntax().clone()); + if let Some(generic_param_list) = generic_param_list { + builder.map_node( + generic_param_list.syntax().clone(), + ast.generic_param_list().unwrap().syntax().clone(), + ); + } + if let Some(where_clause) = where_clause { + builder.map_node( + where_clause.syntax().clone(), + ast.where_clause().unwrap().syntax().clone(), + ); + } + builder.map_node( + assoc_items.syntax().clone(), + ast.assoc_item_list().unwrap().syntax().clone(), + ); + builder.finish(&mut mapping); + } + + ast + } + pub fn ret_type(&self, ty: ast::Type) -> ast::RetType { let ast = make::ret_type(ty.clone()).clone_for_update(); @@ -2053,6 +2123,17 @@ pub fn ident_path(&self, ident: &str) -> ast::Path { self.path_unqualified(self.path_segment(self.name_ref(ident))) } + pub fn path_from_idents<'a>( + &self, + parts: impl IntoIterator, + ) -> Option { + make::ext::path_from_idents(parts).map(|path| path.clone_for_update()) + } + + pub fn token_tree_from_node(&self, node: &SyntaxNode) -> ast::TokenTree { + make::ext::token_tree_from_node(node).clone_for_update() + } + pub fn expr_unit(&self) -> ast::Expr { self.expr_tuple([]).into() } diff --git a/src/tools/rust-analyzer/crates/syntax/src/ast/traits.rs b/src/tools/rust-analyzer/crates/syntax/src/ast/traits.rs index 2f4109a2c976..6fe5abb84e22 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/ast/traits.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/ast/traits.rs @@ -73,9 +73,6 @@ pub trait HasAttrs: AstNode { fn attrs(&self) -> AstChildren { support::children(self.syntax()) } - fn has_atom_attr(&self, atom: &str) -> bool { - self.attrs().filter_map(|x| x.as_simple_atom()).any(|x| x == atom) - } /// This may return the same node as called with (with `SourceFile`). The caller has the responsibility /// to avoid duplicate attributes. diff --git a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor.rs b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor.rs index e6937e4d0f8a..8e4dc75d2219 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor.rs @@ -14,7 +14,10 @@ use rowan::TextRange; use rustc_hash::FxHashMap; -use crate::{SyntaxElement, SyntaxNode, SyntaxToken}; +use crate::{ + AstNode, SyntaxElement, SyntaxKind, SyntaxNode, SyntaxToken, T, + ast::{self, edit::IndentLevel, syntax_factory::SyntaxFactory}, +}; mod edit_algo; mod edits; @@ -32,9 +35,37 @@ pub struct SyntaxEditor { } impl SyntaxEditor { - /// Creates a syntax editor to start editing from `root` - pub fn new(root: SyntaxNode) -> Self { - Self { root, changes: vec![], mappings: SyntaxMapping::default(), annotations: vec![] } + /// Creates a syntax editor from `root`. + /// + /// The returned `root` is guaranteed to be a detached, immutable node. + /// If the provided node is not a root (i.e., has a parent) or is already + /// mutable, it is cloned into a fresh subtree to satisfy syntax editor + /// invariants. + pub fn new(root: SyntaxNode) -> (Self, SyntaxNode) { + let mut root = root; + + if root.parent().is_some() || root.is_mutable() { + root = root.clone_subtree() + }; + + let editor = Self { + root: root.clone(), + changes: Vec::new(), + mappings: SyntaxMapping::default(), + annotations: Vec::new(), + }; + + (editor, root) + } + + /// Typed-node variant of [`SyntaxEditor::new`]. + pub fn with_ast_node(root: &T) -> (Self, T) + where + T: AstNode, + { + let (editor, root) = Self::new(root.syntax().clone()); + + (editor, T::cast(root).unwrap()) } pub fn add_annotation(&mut self, element: impl Element, annotation: SyntaxAnnotation) { @@ -73,6 +104,34 @@ pub fn insert_all(&mut self, position: Position, elements: Vec) { self.changes.push(Change::InsertAll(position, elements)) } + pub fn insert_with_whitespace( + &mut self, + position: Position, + element: impl Element, + factory: &SyntaxFactory, + ) { + self.insert_all_with_whitespace(position, vec![element.syntax_element()], factory) + } + + pub fn insert_all_with_whitespace( + &mut self, + position: Position, + mut elements: Vec, + factory: &SyntaxFactory, + ) { + if let Some(first) = elements.first() + && let Some(ws) = ws_before(&position, first, factory) + { + elements.insert(0, ws.into()); + } + if let Some(last) = elements.last() + && let Some(ws) = ws_after(&position, last, factory) + { + elements.push(ws.into()); + } + self.insert_all(position, elements) + } + pub fn delete(&mut self, element: impl Element) { let element = element.syntax_element(); debug_assert!(is_ancestor_or_self_of_element(&element, &self.root)); @@ -384,6 +443,86 @@ fn syntax_element(self) -> SyntaxElement { } } +fn ws_before( + position: &Position, + new: &SyntaxElement, + factory: &SyntaxFactory, +) -> Option { + let prev = match &position.repr { + PositionRepr::FirstChild(_) => return None, + PositionRepr::After(it) => it, + }; + + if prev.kind() == T!['{'] + && new.kind() == SyntaxKind::USE + && let Some(item_list) = prev.parent().and_then(ast::ItemList::cast) + { + let mut indent = IndentLevel::from_element(&item_list.syntax().clone().into()); + indent.0 += 1; + return Some(factory.whitespace(&format!("\n{indent}"))); + } + + if prev.kind() == T!['{'] + && ast::Stmt::can_cast(new.kind()) + && let Some(stmt_list) = prev.parent().and_then(ast::StmtList::cast) + { + let mut indent = IndentLevel::from_element(&stmt_list.syntax().clone().into()); + indent.0 += 1; + return Some(factory.whitespace(&format!("\n{indent}"))); + } + + ws_between(prev, new, factory) +} + +fn ws_after( + position: &Position, + new: &SyntaxElement, + factory: &SyntaxFactory, +) -> Option { + let next = match &position.repr { + PositionRepr::FirstChild(parent) => parent.first_child_or_token()?, + PositionRepr::After(sibling) => sibling.next_sibling_or_token()?, + }; + ws_between(new, &next, factory) +} + +fn ws_between( + left: &SyntaxElement, + right: &SyntaxElement, + factory: &SyntaxFactory, +) -> Option { + if left.kind() == SyntaxKind::WHITESPACE || right.kind() == SyntaxKind::WHITESPACE { + return None; + } + if right.kind() == T![;] || right.kind() == T![,] { + return None; + } + if left.kind() == T![<] || right.kind() == T![>] { + return None; + } + if left.kind() == T![&] && right.kind() == SyntaxKind::LIFETIME { + return None; + } + if right.kind() == SyntaxKind::GENERIC_ARG_LIST { + return None; + } + if right.kind() == SyntaxKind::USE { + let mut indent = IndentLevel::from_element(left); + if left.kind() == SyntaxKind::USE { + indent.0 = IndentLevel::from_element(right).0.max(indent.0); + } + return Some(factory.whitespace(&format!("\n{indent}"))); + } + if left.kind() == SyntaxKind::ATTR { + let mut indent = IndentLevel::from_element(right); + if right.kind() == SyntaxKind::ATTR { + indent.0 = IndentLevel::from_element(left).0.max(indent.0); + } + return Some(factory.whitespace(&format!("\n{indent}"))); + } + Some(factory.whitespace(" ")) +} + fn is_ancestor_or_self(node: &SyntaxNode, ancestor: &SyntaxNode) -> bool { node == ancestor || node.ancestors().any(|it| &it == ancestor) } @@ -420,10 +559,11 @@ fn basic_usage() { .into(), ); + let (mut editor, root) = SyntaxEditor::with_ast_node(&root); + let to_wrap = root.syntax().descendants().find_map(ast::TupleExpr::cast).unwrap(); let to_replace = root.syntax().descendants().find_map(ast::BinExpr::cast).unwrap(); - let mut editor = SyntaxEditor::new(root.syntax().clone()); let make = SyntaxFactory::with_mappings(); let name = make::name("var_name"); @@ -478,9 +618,8 @@ fn test_insert_independent() { None, ); + let (mut editor, root) = SyntaxEditor::with_ast_node(&root); let second_let = root.syntax().descendants().find_map(ast::LetStmt::cast).unwrap(); - - let mut editor = SyntaxEditor::new(root.syntax().clone()); let make = SyntaxFactory::without_mappings(); editor.insert( @@ -530,11 +669,12 @@ fn test_insert_dependent() { ), ); + let (mut editor, root) = SyntaxEditor::with_ast_node(&root); + let inner_block = root.syntax().descendants().flat_map(ast::BlockExpr::cast).nth(1).unwrap(); let second_let = root.syntax().descendants().find_map(ast::LetStmt::cast).unwrap(); - let mut editor = SyntaxEditor::new(root.syntax().clone()); let make = SyntaxFactory::with_mappings(); let new_block_expr = make.block_expr([], Some(ast::Expr::BlockExpr(inner_block.clone()))); @@ -584,9 +724,9 @@ fn test_replace_root_with_dependent() { None, ); - let inner_block = root.clone(); + let (mut editor, root) = SyntaxEditor::with_ast_node(&root); - let mut editor = SyntaxEditor::new(root.syntax().clone()); + let inner_block = root; let make = SyntaxFactory::with_mappings(); let new_block_expr = make.block_expr([], Some(ast::Expr::BlockExpr(inner_block.clone()))); @@ -632,7 +772,7 @@ fn test_replace_token_in_parent() { false, ); - let mut editor = SyntaxEditor::new(parent_fn.syntax().clone()); + let (mut editor, parent_fn) = SyntaxEditor::with_ast_node(&parent_fn); if let Some(ret_ty) = parent_fn.ret_type() { editor.delete(ret_ty.syntax().clone()); @@ -659,7 +799,8 @@ fn test_more_times_replace_node_to_mutable_token() { let arg_list = make::arg_list([make::expr_literal("1").into(), make::expr_literal("2").into()]); - let mut editor = SyntaxEditor::new(arg_list.syntax().clone()); + let (mut editor, arg_list) = SyntaxEditor::with_ast_node(&arg_list); + let target_expr = make::token(parser::SyntaxKind::UNDERSCORE); for arg in arg_list.args() { @@ -677,7 +818,8 @@ fn test_more_times_replace_node_to_mutable() { let arg_list = make::arg_list([make::expr_literal("1").into(), make::expr_literal("2").into()]); - let mut editor = SyntaxEditor::new(arg_list.syntax().clone()); + let (mut editor, arg_list) = SyntaxEditor::with_ast_node(&arg_list); + let target_expr = make::expr_literal("3").clone_for_update(); for arg in arg_list.args() { @@ -695,7 +837,8 @@ fn test_more_times_insert_node_to_mutable() { let arg_list = make::arg_list([make::expr_literal("1").into(), make::expr_literal("2").into()]); - let mut editor = SyntaxEditor::new(arg_list.syntax().clone()); + let (mut editor, arg_list) = SyntaxEditor::with_ast_node(&arg_list); + let target_expr = make::ext::expr_unit().clone_for_update(); for arg in arg_list.args() { diff --git a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edit_algo.rs b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edit_algo.rs index e697d97061d9..78e7083f97e4 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edit_algo.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edit_algo.rs @@ -192,11 +192,8 @@ struct DependentChange { } }; } - Change::Replace(SyntaxElement::Node(target), Some(SyntaxElement::Node(new_target))) => { + Change::Replace(SyntaxElement::Node(target), Some(SyntaxElement::Node(_))) => { *target = tree_mutator.make_syntax_mut(target); - if new_target.ancestors().any(|node| node == tree_mutator.immutable) { - *new_target = new_target.clone_for_update(); - } } Change::Replace(target, _) | Change::ReplaceWithMany(target, _) => { *target = tree_mutator.make_element_mut(target); @@ -209,6 +206,56 @@ struct DependentChange { } } + match &mut changes[index as usize] { + Change::Insert(_, SyntaxElement::Node(node)) + | Change::Replace(_, Some(SyntaxElement::Node(node))) => { + if node.parent().is_some() { + *node = node.clone_subtree().clone_for_update(); + } else if !node.is_mutable() { + *node = node.clone_for_update(); + } + } + Change::Insert(_, SyntaxElement::Token(token)) + | Change::Replace(_, Some(SyntaxElement::Token(token))) => { + if let Some(parent) = token.parent() { + let idx = token.index(); + let new_parent = parent.clone_subtree().clone_for_update(); + *token = new_parent + .children_with_tokens() + .nth(idx) + .and_then(SyntaxElement::into_token) + .unwrap(); + } + } + Change::InsertAll(_, elements) + | Change::ReplaceWithMany(_, elements) + | Change::ReplaceAll(_, elements) => { + for element in elements { + match element { + SyntaxElement::Node(node) => { + if node.parent().is_some() { + *node = node.clone_subtree().clone_for_update(); + } else if !node.is_mutable() { + *node = node.clone_for_update(); + } + } + SyntaxElement::Token(token) => { + if let Some(parent) = token.parent() { + let idx = token.index(); + let new_parent = parent.clone_subtree().clone_for_update(); + *token = new_parent + .children_with_tokens() + .nth(idx) + .and_then(SyntaxElement::into_token) + .unwrap(); + } + } + } + } + } + _ => {} + } + match &mut changes[index as usize] { Change::Insert(_, element) | Change::Replace(_, Some(element)) => { deduplicate_node(element); diff --git a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edits.rs b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edits.rs index 44f0a8038eca..d741adb6e344 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edits.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/edits.rs @@ -229,6 +229,25 @@ pub fn add_items(&self, editor: &mut SyntaxEditor, items: Vec) { } } +impl ast::Impl { + pub fn get_or_create_assoc_item_list_with_editor( + &self, + editor: &mut SyntaxEditor, + make: &SyntaxFactory, + ) -> ast::AssocItemList { + if let Some(list) = self.assoc_item_list() { + list + } else { + let list = make.assoc_item_list_empty(); + editor.insert_all( + Position::last_child_of(self.syntax()), + vec![make.whitespace(" ").into(), list.syntax().clone().into()], + ); + list + } + } +} + impl ast::VariantList { pub fn add_variant(&self, editor: &mut SyntaxEditor, variant: &ast::Variant) { let make = SyntaxFactory::without_mappings(); @@ -473,8 +492,7 @@ enum Foo { } fn check_add_variant(before: &str, expected: &str, variant: ast::Variant) { - let enum_ = ast_from_text::(before); - let mut editor = SyntaxEditor::new(enum_.syntax().clone()); + let (mut editor, enum_) = SyntaxEditor::with_ast_node(&ast_from_text::(before)); if let Some(it) = enum_.variant_list() { it.add_variant(&mut editor, &variant) } diff --git a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/mapping.rs b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/mapping.rs index 6257bf4e572e..180c2e69fa3e 100644 --- a/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/mapping.rs +++ b/src/tools/rust-analyzer/crates/syntax/src/syntax_editor/mapping.rs @@ -161,7 +161,7 @@ pub fn upmap_node( // Try to follow the mapping tree, if it exists let input_mapping = self.upmap_node_single(input); let input_ancestor = - input.ancestors().find_map(|ancestor| self.upmap_node_single(&ancestor)); + input.ancestors().find(|ancestor| self.upmap_node_single(ancestor).is_some()); match (input_mapping, input_ancestor) { (Some(input_mapping), _) => { diff --git a/src/tools/rust-analyzer/crates/syntax/test_data/parser/validation/0031_block_inner_attrs.rast b/src/tools/rust-analyzer/crates/syntax/test_data/parser/validation/0031_block_inner_attrs.rast index 50057a02d809..5fdde93c603d 100644 --- a/src/tools/rust-analyzer/crates/syntax/test_data/parser/validation/0031_block_inner_attrs.rast +++ b/src/tools/rust-analyzer/crates/syntax/test_data/parser/validation/0031_block_inner_attrs.rast @@ -29,7 +29,7 @@ SOURCE_FILE@0..350 POUND@39..40 "#" BANG@40..41 "!" L_BRACK@41..42 "[" - META@42..82 + TOKEN_TREE_META@42..82 PATH@42..45 PATH_SEGMENT@42..45 NAME_REF@42..45 @@ -60,7 +60,7 @@ SOURCE_FILE@0..350 POUND@152..153 "#" BANG@153..154 "!" L_BRACK@154..155 "[" - META@155..170 + TOKEN_TREE_META@155..170 PATH@155..158 PATH_SEGMENT@155..158 NAME_REF@155..158 @@ -75,7 +75,7 @@ SOURCE_FILE@0..350 POUND@180..181 "#" BANG@181..182 "!" L_BRACK@182..183 "[" - META@183..211 + TOKEN_TREE_META@183..211 PATH@183..186 PATH_SEGMENT@183..186 NAME_REF@183..186 @@ -104,7 +104,7 @@ SOURCE_FILE@0..350 POUND@283..284 "#" BANG@284..285 "!" L_BRACK@285..286 "[" - META@286..301 + TOKEN_TREE_META@286..301 PATH@286..289 PATH_SEGMENT@286..289 NAME_REF@286..289 diff --git a/src/tools/rust-analyzer/crates/test-fixture/src/lib.rs b/src/tools/rust-analyzer/crates/test-fixture/src/lib.rs index e271c32c8626..f346535ca19c 100644 --- a/src/tools/rust-analyzer/crates/test-fixture/src/lib.rs +++ b/src/tools/rust-analyzer/crates/test-fixture/src/lib.rs @@ -11,7 +11,7 @@ use base_db::{ Crate, CrateDisplayName, CrateGraphBuilder, CrateName, CrateOrigin, CrateWorkspaceData, DependencyBuilder, Env, FileChange, FileSet, FxIndexMap, LangCrateOrigin, SourceDatabase, - SourceRoot, Version, VfsPath, + SourceRoot, Version, VfsPath, all_crates, }; use cfg::CfgOptions; use hir_expand::{ @@ -227,7 +227,7 @@ fn with_range_or_offset( } fn test_crate(&self) -> Crate { - self.all_crates().iter().copied().find(|&krate| !krate.data(self).origin.is_lang()).unwrap() + all_crates(self).iter().copied().find(|&krate| !krate.data(self).origin.is_lang()).unwrap() } } diff --git a/src/tools/rust-analyzer/crates/vfs-notify/src/lib.rs b/src/tools/rust-analyzer/crates/vfs-notify/src/lib.rs index 428b19c50b9d..6465a85d2d29 100644 --- a/src/tools/rust-analyzer/crates/vfs-notify/src/lib.rs +++ b/src/tools/rust-analyzer/crates/vfs-notify/src/lib.rs @@ -14,7 +14,7 @@ }; use crossbeam_channel::{Receiver, Sender, select, unbounded}; -use notify::{Config, EventKind, RecommendedWatcher, RecursiveMode, Watcher}; +use notify::{Config, EventKind, RecommendedWatcher, RecursiveMode, Watcher, event::AccessKind}; use paths::{AbsPath, AbsPathBuf, Utf8PathBuf}; use rayon::iter::{IndexedParallelIterator as _, IntoParallelIterator as _, ParallelIterator}; use rustc_hash::FxHashSet; @@ -63,6 +63,7 @@ struct NotifyActor { sender: loader::Sender, watched_file_entries: FxHashSet, watched_dir_entries: Vec, + seen_paths: FxHashSet, // Drop order is significant. watcher: Option<(RecommendedWatcher, Receiver)>, } @@ -79,6 +80,7 @@ fn new(sender: loader::Sender) -> NotifyActor { sender, watched_dir_entries: Vec::new(), watched_file_entries: FxHashSet::default(), + seen_paths: FxHashSet::default(), watcher: None, } } @@ -120,6 +122,7 @@ fn run(mut self, inbox: Receiver) { let n_total = config.load.len(); self.watched_dir_entries.clear(); self.watched_file_entries.clear(); + self.seen_paths.clear(); self.send(loader::Message::Progress { n_total, @@ -195,10 +198,12 @@ fn run(mut self, inbox: Receiver) { }, Event::NotifyEvent(event) => { if let Some(event) = log_notify_error(event) - && let EventKind::Create(_) | EventKind::Modify(_) | EventKind::Remove(_) = - event.kind + && let EventKind::Create(_) + | EventKind::Modify(_) + | EventKind::Remove(_) + | EventKind::Access(AccessKind::Open(_)) = event.kind { - let files = event + let abs_paths: Vec = event .paths .into_iter() .filter_map(|path| { @@ -207,6 +212,28 @@ fn run(mut self, inbox: Receiver) { .expect("path is absolute"), ) }) + .collect(); + + let mut saw_new_file = false; + for abs_path in &abs_paths { + if self.seen_paths.insert(abs_path.clone()) { + saw_new_file = true; + } + } + + // Only consider access events for files that we haven't seen + // before. + // + // This is important on FUSE filesystems, where we may not get a + // Create event. In other cases we're about to access the file, so + // we don't want an infinite loop where processing an Access event + // creates another Access event. + if matches!(event.kind, EventKind::Access(_)) && !saw_new_file { + continue; + } + + let files = abs_paths + .into_iter() .filter_map(|path| -> Option<(AbsPathBuf, Option>)> { // Ignore events for files/directories that we're not watching. if !(self.watched_file_entries.contains(&path) diff --git a/src/tools/rust-analyzer/crates/vfs/src/lib.rs b/src/tools/rust-analyzer/crates/vfs/src/lib.rs index 50e388d78002..d48b984407e6 100644 --- a/src/tools/rust-analyzer/crates/vfs/src/lib.rs +++ b/src/tools/rust-analyzer/crates/vfs/src/lib.rs @@ -157,7 +157,7 @@ pub enum Change { } /// Kind of [file change](ChangedFile). -#[derive(Eq, PartialEq, Debug)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] pub enum ChangeKind { /// The file was (re-)created Create, diff --git a/src/tools/rust-analyzer/docs/book/src/configuration_generated.md b/src/tools/rust-analyzer/docs/book/src/configuration_generated.md index 35fba5accdbb..da37fc158234 100644 --- a/src/tools/rust-analyzer/docs/book/src/configuration_generated.md +++ b/src/tools/rust-analyzer/docs/book/src/configuration_generated.md @@ -166,6 +166,14 @@ List of features to activate. Set this to `"all"` to pass `--all-features` to cargo. +## rust-analyzer.cargo.metadataExtraArgs {#cargo.metadataExtraArgs} + +Default: `[]` + +Extra arguments passed only to `cargo metadata`, not to other cargo invocations. +Useful for flags like `--config` that `cargo metadata` supports. + + ## rust-analyzer.cargo.noDefaultFeatures {#cargo.noDefaultFeatures} Default: `false` @@ -618,6 +626,15 @@ The warnings will be indicated by a blue squiggly underline in code and a blue i the `Problems Panel`. +## rust-analyzer.disableFixtureSupport {#disableFixtureSupport} + +Default: `false` + +Disable support for `#[rust_analyzer::rust_fixture]` snippets. + +If you are not working on rust-analyzer itself, you should ignore this config. + + ## rust-analyzer.document.symbol.search.excludeLocals {#document.symbol.search.excludeLocals} Default: `true` @@ -1147,6 +1164,13 @@ Default: `false` Hide inlay type hints for constructors. +## rust-analyzer.inlayHints.typeHints.location {#inlayHints.typeHints.location} + +Default: `"inline"` + +Where to render type hints relative to their binding pattern. + + ## rust-analyzer.interpret.tests {#interpret.tests} Default: `false` @@ -1380,9 +1404,15 @@ Default: `null` Override the command used for bench runnables. The first element of the array should be the program to execute (for example, `cargo`). -Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically -replace the package name, target option (such as `--bin` or `--example`), the target name and -the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). +Use the placeholders: +- `${package}`: package name. +- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. +- `${target}`: target name (empty for `--lib`). +- `${test_name}`: the test path filter, e.g. `module::bench_func`. +- `${exact}`: `--exact` for single benchmarks, empty for modules. +- `${include_ignored}`: always empty for benchmarks. +- `${executable_args}`: all of the above binary args bundled together + (includes `rust-analyzer.runnables.extraTestBinaryArgs`). ## rust-analyzer.runnables.command {#runnables.command} @@ -1396,12 +1426,18 @@ Command to be executed instead of 'cargo' for runnables. Default: `null` -Override the command used for bench runnables. +Override the command used for doc-test runnables. The first element of the array should be the program to execute (for example, `cargo`). -Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically -replace the package name, target option (such as `--bin` or `--example`), the target name and -the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). +Use the placeholders: +- `${package}`: package name. +- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. +- `${target}`: target name (empty for `--lib`). +- `${test_name}`: the test path filter, e.g. `module::func`. +- `${exact}`: always empty for doc-tests. +- `${include_ignored}`: always empty for doc-tests. +- `${executable_args}`: all of the above binary args bundled together + (includes `rust-analyzer.runnables.extraTestBinaryArgs`). ## rust-analyzer.runnables.extraArgs {#runnables.extraArgs} @@ -1444,9 +1480,15 @@ Default: `null` Override the command used for test runnables. The first element of the array should be the program to execute (for example, `cargo`). -Use the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically -replace the package name, target option (such as `--bin` or `--example`), the target name and -the arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`). +Available placeholders: +- `${package}`: package name. +- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc. +- `${target}`: target name (empty for `--lib`). +- `${test_name}`: the test path filter, e.g. `module::test_func`. +- `${exact}`: `--exact` for single tests, empty for modules. +- `${include_ignored}`: `--include-ignored` for single tests, empty otherwise. +- `${executable_args}`: all of the above binary args bundled together + (includes `rust-analyzer.runnables.extraTestBinaryArgs`). ## rust-analyzer.rustc.source {#rustc.source} diff --git a/src/tools/rust-analyzer/docs/book/src/contributing/lsp-extensions.md b/src/tools/rust-analyzer/docs/book/src/contributing/lsp-extensions.md index 5d21c37806dd..22c1784ac293 100644 --- a/src/tools/rust-analyzer/docs/book/src/contributing/lsp-extensions.md +++ b/src/tools/rust-analyzer/docs/book/src/contributing/lsp-extensions.md @@ -236,7 +236,7 @@ fn main() { ``` The primary goal of `onEnter` is to handle automatic indentation when opening a new line. -This is not yet implemented. +This is partially implemented for single-line brace-delimited contents, in addition to comment continuation. The secondary goal is to handle fixing up syntax, like continuing doc strings and comments, and escaping `\n` in string literals. As proper cursor positioning is raison d'être for `onEnter`, it uses `SnippetTextEdit`. diff --git a/src/tools/rust-analyzer/docs/book/src/other_editors.md b/src/tools/rust-analyzer/docs/book/src/other_editors.md index f7116fc19a6c..1cb2a44063b2 100644 --- a/src/tools/rust-analyzer/docs/book/src/other_editors.md +++ b/src/tools/rust-analyzer/docs/book/src/other_editors.md @@ -137,24 +137,22 @@ To use the LSP server in [ale](https://github.com/dense-analysis/ale): ### nvim-lsp -Neovim 0.5 has built-in language server support. For a quick start -configuration of rust-analyzer, use -[neovim/nvim-lspconfig](https://github.com/neovim/nvim-lspconfig#rust_analyzer). -Once `neovim/nvim-lspconfig` is installed, use -`lua require'lspconfig'.rust_analyzer.setup({})` in your `init.vim`. +Neovim 0.5+ added build-in support for language server with most of the heavy +lifting happening in "framework" plugins such as +[neovim/nvim-lspconfig](https://github.com/neovim/nvim-lspconfig). +Since v0.11+ Neovim has full featured LSP support. nvim-lspconfig is +still recommended to get the +[rust-analyzer config](https://github.com/neovim/nvim-lspconfig/blob/master/lsp/rust_analyzer.lua) +for free. -You can also pass LSP settings to the server: +1. Install [neovim/nvim-lspconfig](https://github.com/neovim/nvim-lspconfig) +2. Add `lua vim.lsp.enable('rust-analyzer')` to your `init.vim` +3. Customize your setup. ```lua lua << EOF -local lspconfig = require'lspconfig' - -local on_attach = function(client) - require'completion'.on_attach(client) -end - -lspconfig.rust_analyzer.setup({ - on_attach = on_attach, +-- You can pass LSP settings to the server: +vim.lsp.config("rust_analyzer", { settings = { ["rust-analyzer"] = { imports = { @@ -171,30 +169,35 @@ lspconfig.rust_analyzer.setup({ procMacro = { enable = true }, - } - } + }, + }, +}) + +-- You can enable different LSP features +vim.api.nvim_create_autocmd("LspAttach", { + callback = function(ev) + local client = assert(vim.lsp.get_client_by_id(ev.data.client_id)) + -- Inlay hints display inferred types, etc. + if client:supports_method("inlayHint/resolve") then + vim.lsp.inlay_hint.enable(true, { bufnr = ev.buf }) + end + -- Completion can be invoked via ctrl+x ctrl+o. It displays a list of + -- names inferred from the context (e.g. method names, variables, etc.) + if client:supports_method("textDocument/completion") then + vim.lsp.completion.enable(true, client.id, ev.buf, {}) + end + end, }) EOF ``` -If you're running Neovim 0.10 or later, you can enable inlay hints via `on_attach`: +Note that the hints are only visible after `rust-analyzer` has finished loading +**and** you have to edit the file to trigger a re-render. -```lua -lspconfig.rust_analyzer.setup({ - on_attach = function(client, bufnr) - vim.lsp.inlay_hint.enable(true, { bufnr = bufnr }) - end -}) -``` - -Note that the hints are only visible after `rust-analyzer` has finished loading **and** you have to -edit the file to trigger a re-render. - -See for more tips on -getting started. - -Check out for a batteries -included rust-analyzer setup for Neovim. +The instructions here use the 0.11+ API, if you're running an older version, you +can follow this guide or check +out for a batteries included +rust-analyzer setup for Neovim. ### vim-lsp diff --git a/src/tools/rust-analyzer/editors/code/package-lock.json b/src/tools/rust-analyzer/editors/code/package-lock.json index b51dc4d1320d..5755f0708f0f 100644 --- a/src/tools/rust-analyzer/editors/code/package-lock.json +++ b/src/tools/rust-analyzer/editors/code/package-lock.json @@ -17,8 +17,8 @@ "vscode-languageclient": "^9.0.1" }, "devDependencies": { - "@eslint/js": "^9.21.0", - "@stylistic/eslint-plugin": "^4.1.0", + "@eslint/js": "^10.0.1", + "@stylistic/eslint-plugin": "^5.10.0", "@stylistic/eslint-plugin-js": "^4.1.0", "@tsconfig/strictest": "^2.0.5", "@types/lodash": "^4.17.20", @@ -27,16 +27,16 @@ "@typescript-eslint/eslint-plugin": "^8.25.0", "@typescript-eslint/parser": "^8.25.0", "@vscode/test-electron": "^2.4.1", - "@vscode/vsce": "^3.6.0", + "@vscode/vsce": "^3.7.1", "esbuild": "^0.25.0", - "eslint": "^9.21.0", - "eslint-config-prettier": "^10.0.2", + "eslint": "^10.2.0", + "eslint-config-prettier": "^10.1.8", "eslint-define-config": "^2.1.0", - "ovsx": "0.10.1", - "prettier": "^3.5.2", + "ovsx": "0.10.10", + "prettier": "^3.8.1", "tslib": "^2.8.1", - "typescript": "^5.7.3", - "typescript-eslint": "^8.25.0" + "typescript": "^6.0.2", + "typescript-eslint": "^8.58.0" }, "engines": { "vscode": "^1.93.0" @@ -255,6 +255,40 @@ "node": ">=6.9.0" } }, + "node_modules/@emnapi/core": { + "version": "1.9.1", + "resolved": "https://registry.npmjs.org/@emnapi/core/-/core-1.9.1.tgz", + "integrity": "sha512-mukuNALVsoix/w1BJwFzwXBN/dHeejQtuVzcDsfOEsdpCumXb/E9j8w11h5S54tT1xhifGfbbSm/ICrObRb3KA==", + "dev": true, + "license": "MIT", + "optional": true, + "dependencies": { + "@emnapi/wasi-threads": "1.2.0", + "tslib": "^2.4.0" + } + }, + "node_modules/@emnapi/runtime": { + "version": "1.9.1", + "resolved": "https://registry.npmjs.org/@emnapi/runtime/-/runtime-1.9.1.tgz", + "integrity": "sha512-VYi5+ZVLhpgK4hQ0TAjiQiZ6ol0oe4mBx7mVv7IflsiEp0OWoVsp/+f9Vc1hOhE0TtkORVrI1GvzyreqpgWtkA==", + "dev": true, + "license": "MIT", + "optional": true, + "dependencies": { + "tslib": "^2.4.0" + } + }, + "node_modules/@emnapi/wasi-threads": { + "version": "1.2.0", + "resolved": "https://registry.npmjs.org/@emnapi/wasi-threads/-/wasi-threads-1.2.0.tgz", + "integrity": "sha512-N10dEJNSsUx41Z6pZsXU8FjPjpBEplgH24sfkmITrBED1/U2Esum9F3lfLrMjKHHjmi557zQn7kR9R+XWXu5Rg==", + "dev": true, + "license": "MIT", + "optional": true, + "dependencies": { + "tslib": "^2.4.0" + } + }, "node_modules/@esbuild/aix-ppc64": { "version": "0.25.0", "resolved": "https://registry.npmjs.org/@esbuild/aix-ppc64/-/aix-ppc64-0.25.0.tgz", @@ -681,9 +715,9 @@ } }, "node_modules/@eslint-community/eslint-utils": { - "version": "4.4.1", - "resolved": "https://registry.npmjs.org/@eslint-community/eslint-utils/-/eslint-utils-4.4.1.tgz", - "integrity": "sha512-s3O3waFUrMV8P/XaF/+ZTp1X9XBZW1a4B97ZnjQF2KYWaFD2A8KyFBsrsfSjEmjn3RGWAIuvlneuZm3CUK3jbA==", + "version": "4.9.1", + "resolved": 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"dev": true, - "license": "MIT", - "dependencies": { - "buffer-crc32": "~0.2.3", - "pend": "~1.2.0" - }, - "engines": { - "node": ">=12" - } - }, "node_modules/p-limit": { "version": "3.1.0", "resolved": "https://registry.npmjs.org/p-limit/-/p-limit-3.1.0.tgz", @@ -5297,19 +5709,6 @@ "dev": true, "license": "(MIT AND Zlib)" }, - "node_modules/parent-module": { - "version": "1.0.1", - "resolved": "https://registry.npmjs.org/parent-module/-/parent-module-1.0.1.tgz", - "integrity": "sha512-GQ2EWRpQV8/o+Aw8YqtfZZPfNRWZYkbidE9k5rpl/hC3vtHHBfGm2Ifi6qWV+coDGkrUKZAxE3Lot5kcsRlh+g==", - "dev": true, - "license": "MIT", - "dependencies": { - "callsites": "^3.0.0" - }, - "engines": { - "node": ">=6" - } - }, "node_modules/parse-json": { "version": "8.3.0", "resolved": "https://registry.npmjs.org/parse-json/-/parse-json-8.3.0.tgz", @@ -5524,9 +5923,9 @@ } }, "node_modules/prettier": { - "version": "3.5.2", - "resolved": "https://registry.npmjs.org/prettier/-/prettier-3.5.2.tgz", - "integrity": "sha512-lc6npv5PH7hVqozBR7lkBNOGXV9vMwROAPlumdBkX0wTbbzPu/U1hk5yL8p2pt4Xoc+2mkT8t/sow2YrV/M5qg==", + "version": "3.8.1", + "resolved": "https://registry.npmjs.org/prettier/-/prettier-3.8.1.tgz", + "integrity": "sha512-UOnG6LftzbdaHZcKoPFtOcCKztrQ57WkHDeRD9t/PTQtmT0NHSeWWepj6pS0z/N7+08BHFDQVUrfmfMRcZwbMg==", "dev": true, "license": "MIT", "bin": { @@ -5744,16 +6143,6 @@ "node": ">=0.10.0" } }, - "node_modules/resolve-from": { - "version": "4.0.0", - "resolved": "https://registry.npmjs.org/resolve-from/-/resolve-from-4.0.0.tgz", - "integrity": "sha512-pb/MYmXstAkysRFx8piNI1tGFNQIFA3vkE3Gq4EuA1dF6gHp/+vgZqsCGJapvy8N3Q+4o7FwvquPJcnZ7RYy4g==", - "dev": true, - "license": "MIT", - "engines": { - "node": ">=4" - } - }, "node_modules/restore-cursor": { "version": "4.0.0", "resolved": "https://registry.npmjs.org/restore-cursor/-/restore-cursor-4.0.0.tgz", @@ -5895,9 +6284,9 @@ } }, "node_modules/semver": { - "version": "7.7.1", - "resolved": "https://registry.npmjs.org/semver/-/semver-7.7.1.tgz", - "integrity": "sha512-hlq8tAfn0m/61p4BVRcPzIGr6LKiMwo4VM6dGi6pt4qcRkmNzTcWq6eCEjEh+qXjkMDvPlOFFSGwQjoEa6gyMA==", + "version": "7.7.4", + "resolved": "https://registry.npmjs.org/semver/-/semver-7.7.4.tgz", + "integrity": "sha512-vFKC2IEtQnVhpT78h1Yp8wzwrf8CM+MzKMHGJZfBtzhZNycRFnXsHk6E5TxIkkMsgNS7mdX3AGB7x2QM2di4lA==", "license": "ISC", "bin": { "semver": "bin/semver.js" @@ -6074,6 +6463,16 @@ "simple-concat": "^1.0.0" } }, + "node_modules/simple-invariant": { + "version": "2.0.1", + "resolved": "https://registry.npmjs.org/simple-invariant/-/simple-invariant-2.0.1.tgz", + "integrity": "sha512-1sbhsxqI+I2tqlmjbz99GXNmZtr6tKIyEgGGnJw/MKGblalqk/XoOYYFJlBzTKZCxx8kLaD3FD5s9BEEjx5Pyg==", + "dev": true, + "license": "MIT", + "engines": { + "node": ">=10" + } + }, "node_modules/slash": { "version": "5.1.0", "resolved": "https://registry.npmjs.org/slash/-/slash-5.1.0.tgz", @@ -6296,19 +6695,6 @@ "node": ">=8" } }, - "node_modules/strip-json-comments": { - "version": "3.1.1", - "resolved": "https://registry.npmjs.org/strip-json-comments/-/strip-json-comments-3.1.1.tgz", - "integrity": "sha512-6fPc+R4ihwqP6N/aIv2f1gMH8lOVtWQHoqC4yK6oSDVVocumAsfCqjkXnqiYMhmMwS/mEHLp7Vehlt3ql6lEig==", - "dev": true, - "license": "MIT", - "engines": { - "node": ">=8" - }, - "funding": { - "url": "https://github.com/sponsors/sindresorhus" - } - }, "node_modules/structured-source": { "version": "4.0.0", "resolved": "https://registry.npmjs.org/structured-source/-/structured-source-4.0.0.tgz", @@ -6562,6 +6948,23 @@ "url": "https://bevry.me/fund" } }, + "node_modules/tinyglobby": { + "version": "0.2.15", + "resolved": "https://registry.npmjs.org/tinyglobby/-/tinyglobby-0.2.15.tgz", + "integrity": "sha512-j2Zq4NyQYG5XMST4cbs02Ak8iJUdxRM0XI5QyxXuZOzKOINmWurp3smXu3y5wDcJrptwpSjgXHzIQxR0omXljQ==", + "dev": true, + "license": "MIT", + "dependencies": { + "fdir": "^6.5.0", + "picomatch": "^4.0.3" + }, + "engines": { + "node": ">=12.0.0" + }, + "funding": { + "url": "https://github.com/sponsors/SuperchupuDev" + } + }, "node_modules/tmp": { "version": "0.2.4", "resolved": "https://registry.npmjs.org/tmp/-/tmp-0.2.4.tgz", @@ -6586,9 +6989,9 @@ } }, "node_modules/ts-api-utils": { - "version": "2.0.1", - "resolved": "https://registry.npmjs.org/ts-api-utils/-/ts-api-utils-2.0.1.tgz", - "integrity": "sha512-dnlgjFSVetynI8nzgJ+qF62efpglpWRk8isUEWZGWlJYySCTD6aKvbUDu+zbPeDakk3bg5H4XpitHukgfL1m9w==", + "version": "2.5.0", + "resolved": "https://registry.npmjs.org/ts-api-utils/-/ts-api-utils-2.5.0.tgz", + "integrity": "sha512-OJ/ibxhPlqrMM0UiNHJ/0CKQkoKF243/AEmplt3qpRgkW8VG7IfOS41h7V8TjITqdByHzrjcS/2si+y4lIh8NA==", "dev": true, "license": "MIT", "engines": { @@ -6668,9 +7071,9 @@ } }, "node_modules/typescript": { - "version": "5.7.3", - "resolved": "https://registry.npmjs.org/typescript/-/typescript-5.7.3.tgz", - "integrity": "sha512-84MVSjMEHP+FQRPy3pX9sTVV/INIex71s9TL2Gm5FG/WG1SqXeKyZ0k7/blY/4FdOzI12CBy1vGc4og/eus0fw==", + "version": "6.0.2", + "resolved": "https://registry.npmjs.org/typescript/-/typescript-6.0.2.tgz", + "integrity": "sha512-bGdAIrZ0wiGDo5l8c++HWtbaNCWTS4UTv7RaTH/ThVIgjkveJt83m74bBHMJkuCbslY8ixgLBVZJIOiQlQTjfQ==", "dev": true, "license": "Apache-2.0", "bin": { @@ -6682,15 +7085,16 @@ } }, "node_modules/typescript-eslint": { - "version": "8.25.0", - "resolved": "https://registry.npmjs.org/typescript-eslint/-/typescript-eslint-8.25.0.tgz", - "integrity": "sha512-TxRdQQLH4g7JkoFlYG3caW5v1S6kEkz8rqt80iQJZUYPq1zD1Ra7HfQBJJ88ABRaMvHAXnwRvRB4V+6sQ9xN5Q==", + "version": "8.58.0", + "resolved": "https://registry.npmjs.org/typescript-eslint/-/typescript-eslint-8.58.0.tgz", + "integrity": "sha512-e2TQzKfaI85fO+F3QywtX+tCTsu/D3WW5LVU6nz8hTFKFZ8yBJ6mSYRpXqdR3mFjPWmO0eWsTa5f+UpAOe/FMA==", "dev": true, "license": "MIT", "dependencies": { - "@typescript-eslint/eslint-plugin": "8.25.0", - "@typescript-eslint/parser": "8.25.0", - "@typescript-eslint/utils": "8.25.0" + "@typescript-eslint/eslint-plugin": "8.58.0", + "@typescript-eslint/parser": "8.58.0", + "@typescript-eslint/typescript-estree": "8.58.0", + "@typescript-eslint/utils": "8.58.0" }, "engines": { "node": "^18.18.0 || ^20.9.0 || >=21.1.0" @@ -6700,8 +7104,8 @@ "url": "https://opencollective.com/typescript-eslint" }, "peerDependencies": { - "eslint": "^8.57.0 || ^9.0.0", - "typescript": ">=4.8.4 <5.8.0" + "eslint": "^8.57.0 || ^9.0.0 || ^10.0.0", + "typescript": ">=4.8.4 <6.1.0" } }, "node_modules/uc.micro": { @@ -7138,6 +7542,21 @@ "fd-slicer": "~1.1.0" } }, + "node_modules/yauzl-promise": { + "version": "4.0.0", + "resolved": "https://registry.npmjs.org/yauzl-promise/-/yauzl-promise-4.0.0.tgz", + "integrity": "sha512-/HCXpyHXJQQHvFq9noqrjfa/WpQC2XYs3vI7tBiAi4QiIU1knvYhZGaO1QPjwIVMdqflxbmwgMXtYeaRiAE0CA==", + "dev": true, + "license": "MIT", + "dependencies": { + "@node-rs/crc32": "^1.7.0", + "is-it-type": "^5.1.2", + "simple-invariant": "^2.0.1" + }, + "engines": { + "node": ">=16" + } + }, "node_modules/yazl": { "version": "2.5.1", "resolved": "https://registry.npmjs.org/yazl/-/yazl-2.5.1.tgz", diff --git a/src/tools/rust-analyzer/editors/code/package.json b/src/tools/rust-analyzer/editors/code/package.json index 1dd513c9de40..29cbc8bd4fda 100644 --- a/src/tools/rust-analyzer/editors/code/package.json +++ b/src/tools/rust-analyzer/editors/code/package.json @@ -31,6 +31,9 @@ "vscode": "^1.93.0" }, "enabledApiProposals": [], + "extensionKind": [ + "workspace" + ], "scripts": { "vscode:prepublish": "npm run build-base -- --minify", "package": "vsce package -o rust-analyzer.vsix", @@ -54,8 +57,8 @@ "vscode-languageclient": "^9.0.1" }, "devDependencies": { - "@eslint/js": "^9.21.0", - "@stylistic/eslint-plugin": "^4.1.0", + "@eslint/js": "^10.0.1", + "@stylistic/eslint-plugin": "^5.10.0", "@stylistic/eslint-plugin-js": "^4.1.0", "@tsconfig/strictest": "^2.0.5", "@types/lodash": "^4.17.20", @@ -64,16 +67,16 @@ "@typescript-eslint/eslint-plugin": "^8.25.0", "@typescript-eslint/parser": "^8.25.0", "@vscode/test-electron": "^2.4.1", - "@vscode/vsce": "^3.6.0", + "@vscode/vsce": "^3.7.1", "esbuild": "^0.25.0", - "eslint": "^9.21.0", - "eslint-config-prettier": "^10.0.2", + "eslint": "^10.2.0", + "eslint-config-prettier": "^10.1.8", "eslint-define-config": "^2.1.0", - "ovsx": "0.10.1", - "prettier": "^3.5.2", + "ovsx": "0.10.10", + "prettier": "^3.8.1", "tslib": "^2.8.1", - "typescript": "^5.7.3", - "typescript-eslint": "^8.25.0" + "typescript": "^6.0.2", + "typescript-eslint": "^8.58.0" }, "activationEvents": [ "workspaceContains:Cargo.toml", @@ -990,6 +993,19 @@ } } }, + { + "title": "Cargo", + "properties": { + "rust-analyzer.cargo.metadataExtraArgs": { + "markdownDescription": "Extra arguments passed only to `cargo metadata`, not to other cargo invocations.\nUseful for flags like `--config` that `cargo metadata` supports.", + "default": [], + "type": "array", + "items": { + "type": "string" + } + } + } + }, { "title": "Cargo", "properties": { @@ -1591,6 +1607,16 @@ } } }, + { + "title": "rust-analyzer", + "properties": { + "rust-analyzer.disableFixtureSupport": { + "markdownDescription": "Disable support for `#[rust_analyzer::rust_fixture]` snippets.\n\nIf you are not working on rust-analyzer itself, you should ignore this config.", + "default": false, + "type": "boolean" + } + } + }, { "title": "Document", "properties": { @@ -2501,6 +2527,24 @@ } } }, + { + "title": "Inlay Hints", + "properties": { + "rust-analyzer.inlayHints.typeHints.location": { + "markdownDescription": "Where to render type hints relative to their binding pattern.", + "default": "inline", + "type": "string", + "enum": [ + "inline", + "end_of_line" + ], + "enumDescriptions": [ + "Render type hints directly after the binding identifier.", + "Render type hints after the end of the containing `let` statement when possible." + ] + } + } + }, { "title": "Interpret", "properties": { @@ -2865,7 +2909,7 @@ "title": "Runnables", "properties": { "rust-analyzer.runnables.bench.overrideCommand": { - "markdownDescription": "Override the command used for bench runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nUse the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically\nreplace the package name, target option (such as `--bin` or `--example`), the target name and\nthe arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", + "markdownDescription": "Override the command used for bench runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nUse the placeholders:\n- `${package}`: package name.\n- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc.\n- `${target}`: target name (empty for `--lib`).\n- `${test_name}`: the test path filter, e.g. `module::bench_func`.\n- `${exact}`: `--exact` for single benchmarks, empty for modules.\n- `${include_ignored}`: always empty for benchmarks.\n- `${executable_args}`: all of the above binary args bundled together\n (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", "default": null, "type": [ "null", @@ -2894,7 +2938,7 @@ "title": "Runnables", "properties": { "rust-analyzer.runnables.doctest.overrideCommand": { - "markdownDescription": "Override the command used for bench runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nUse the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically\nreplace the package name, target option (such as `--bin` or `--example`), the target name and\nthe arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", + "markdownDescription": "Override the command used for doc-test runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nUse the placeholders:\n- `${package}`: package name.\n- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc.\n- `${target}`: target name (empty for `--lib`).\n- `${test_name}`: the test path filter, e.g. `module::func`.\n- `${exact}`: always empty for doc-tests.\n- `${include_ignored}`: always empty for doc-tests.\n- `${executable_args}`: all of the above binary args bundled together\n (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", "default": null, "type": [ "null", @@ -2948,7 +2992,7 @@ "title": "Runnables", "properties": { "rust-analyzer.runnables.test.overrideCommand": { - "markdownDescription": "Override the command used for test runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nUse the placeholders `${package}`, `${target_arg}`, `${target}`, `${executable_args}` to dynamically\nreplace the package name, target option (such as `--bin` or `--example`), the target name and\nthe arguments passed to test binary args (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", + "markdownDescription": "Override the command used for test runnables.\nThe first element of the array should be the program to execute (for example, `cargo`).\n\nAvailable placeholders:\n- `${package}`: package name.\n- `${target_arg}`: target option such as `--bin`, `--test`, `--lib`, etc.\n- `${target}`: target name (empty for `--lib`).\n- `${test_name}`: the test path filter, e.g. `module::test_func`.\n- `${exact}`: `--exact` for single tests, empty for modules.\n- `${include_ignored}`: `--include-ignored` for single tests, empty otherwise.\n- `${executable_args}`: all of the above binary args bundled together\n (includes `rust-analyzer.runnables.extraTestBinaryArgs`).", "default": null, "type": [ "null", diff --git a/src/tools/rust-analyzer/editors/code/src/client.ts b/src/tools/rust-analyzer/editors/code/src/client.ts index 5b358e3211fb..e265cff391d0 100644 --- a/src/tools/rust-analyzer/editors/code/src/client.ts +++ b/src/tools/rust-analyzer/editors/code/src/client.ts @@ -1,4 +1,4 @@ -import * as anser from "anser"; +import anser from "anser"; import * as lc from "vscode-languageclient/node"; import * as vscode from "vscode"; import * as ra from "../src/lsp_ext"; diff --git a/src/tools/rust-analyzer/editors/code/src/commands.ts b/src/tools/rust-analyzer/editors/code/src/commands.ts index c1b6f310301e..302f51dee44d 100644 --- a/src/tools/rust-analyzer/editors/code/src/commands.ts +++ b/src/tools/rust-analyzer/editors/code/src/commands.ts @@ -1194,9 +1194,8 @@ export function runSingle(ctx: CtxInit): Cmd { } export function copyRunCommandLine(ctx: CtxInit) { - let prevRunnable: RunnableQuickPick | undefined; return async () => { - const item = await selectRunnable(ctx, prevRunnable); + const item = await selectRunnable(ctx, undefined); if (!item || !isCargoRunnableArgs(item.runnable.args)) return; const args = createCargoArgs(item.runnable.args); const commandLine = ["cargo", ...args].join(" "); diff --git a/src/tools/rust-analyzer/editors/code/src/config.ts b/src/tools/rust-analyzer/editors/code/src/config.ts index 5dc2c419efa8..d65f011c754b 100644 --- a/src/tools/rust-analyzer/editors/code/src/config.ts +++ b/src/tools/rust-analyzer/editors/code/src/config.ts @@ -485,7 +485,7 @@ export function substituteVariablesInEnv(env: Env): Env { Object.entries(env).map(([key, value]) => { const deps = new Set(); if (value) { - let match = undefined; + let match; while ((match = depRe.exec(value))) { const depName = unwrapUndefinable(match.groups?.["depName"]); deps.add(depName); diff --git a/src/tools/rust-analyzer/editors/code/src/debug.ts b/src/tools/rust-analyzer/editors/code/src/debug.ts index 24f8d9087300..9bc3adad2f7e 100644 --- a/src/tools/rust-analyzer/editors/code/src/debug.ts +++ b/src/tools/rust-analyzer/editors/code/src/debug.ts @@ -48,7 +48,7 @@ export async function makeDebugConfig(ctx: Ctx, runnable: ra.Runnable): Promise< } export async function startDebugSession(ctx: Ctx, runnable: ra.Runnable): Promise { - let debugConfig: vscode.DebugConfiguration | undefined = undefined; + let debugConfig: vscode.DebugConfiguration | undefined; let message = ""; const wsLaunchSection = vscode.workspace.getConfiguration("launch"); diff --git a/src/tools/rust-analyzer/editors/code/src/dependencies_provider.ts b/src/tools/rust-analyzer/editors/code/src/dependencies_provider.ts index 203ef5cc85e4..3c04f2ef64e8 100644 --- a/src/tools/rust-analyzer/editors/code/src/dependencies_provider.ts +++ b/src/tools/rust-analyzer/editors/code/src/dependencies_provider.ts @@ -6,9 +6,9 @@ import * as ra from "./lsp_ext"; import type { FetchDependencyListResult } from "./lsp_ext"; import { unwrapUndefinable } from "./util"; -export class RustDependenciesProvider - implements vscode.TreeDataProvider -{ +export class RustDependenciesProvider implements vscode.TreeDataProvider< + Dependency | DependencyFile +> { dependenciesMap: { [id: string]: Dependency | DependencyFile }; ctx: CtxInit; diff --git a/src/tools/rust-analyzer/editors/code/src/diagnostics.ts b/src/tools/rust-analyzer/editors/code/src/diagnostics.ts index cd0e43b21203..32a41745edd8 100644 --- a/src/tools/rust-analyzer/editors/code/src/diagnostics.ts +++ b/src/tools/rust-analyzer/editors/code/src/diagnostics.ts @@ -1,4 +1,4 @@ -import * as anser from "anser"; +import anser from "anser"; import * as vscode from "vscode"; import { type ProviderResult, diff --git a/src/tools/rust-analyzer/editors/code/src/lsp_ext.ts b/src/tools/rust-analyzer/editors/code/src/lsp_ext.ts index 9712bd4b7b99..cf190ea3ce0d 100644 --- a/src/tools/rust-analyzer/editors/code/src/lsp_ext.ts +++ b/src/tools/rust-analyzer/editors/code/src/lsp_ext.ts @@ -300,14 +300,14 @@ export type SsrParams = { }; export type RecursiveMemoryLayoutNode = { - item_name: string; + itemName: string; typename: string; size: number; alignment: number; offset: number; - parent_idx: number; - children_start: number; - children_len: number; + parentIdx: number; + childrenStart: number; + childrenLen: number; }; export type RecursiveMemoryLayout = { nodes: RecursiveMemoryLayoutNode[]; diff --git a/src/tools/rust-analyzer/editors/code/src/snippets.ts b/src/tools/rust-analyzer/editors/code/src/snippets.ts index a469a9cd1f45..6d75428eaa3d 100644 --- a/src/tools/rust-analyzer/editors/code/src/snippets.ts +++ b/src/tools/rust-analyzer/editors/code/src/snippets.ts @@ -53,7 +53,7 @@ export async function applySnippetTextEdits(editor: vscode.TextEditor, edits: vs } function hasSnippet(snip: string): boolean { - const m = snip.match(/\$\d+|\{\d+:[^}]*\}/); + const m = snip.match(/\$\d+|\$\{\d+:[^}]*\}/); return m != null; } diff --git a/src/tools/rust-analyzer/editors/code/src/toolchain.ts b/src/tools/rust-analyzer/editors/code/src/toolchain.ts index 06f75a8f8d65..76946d151016 100644 --- a/src/tools/rust-analyzer/editors/code/src/toolchain.ts +++ b/src/tools/rust-analyzer/editors/code/src/toolchain.ts @@ -100,7 +100,7 @@ export class Cargo { ); } catch (err) { log.error(`Cargo invocation has failed: ${err}`); - throw new Error(`Cargo invocation has failed: ${err}`); + throw new Error(`Cargo invocation has failed: ${err}`, { cause: err }); } return spec.filter?.(artifacts) ?? artifacts; diff --git a/src/tools/rust-analyzer/editors/code/tsconfig.json b/src/tools/rust-analyzer/editors/code/tsconfig.json index a13afab17059..380acec59d85 100644 --- a/src/tools/rust-analyzer/editors/code/tsconfig.json +++ b/src/tools/rust-analyzer/editors/code/tsconfig.json @@ -1,7 +1,6 @@ { "extends": "@tsconfig/strictest/tsconfig.json", "compilerOptions": { - "esModuleInterop": false, "module": "NodeNext", "moduleResolution": "nodenext", "target": "ES2024", diff --git a/src/tools/rust-analyzer/rust-version b/src/tools/rust-analyzer/rust-version index 68f38716dbb0..38f153f78d02 100644 --- a/src/tools/rust-analyzer/rust-version +++ b/src/tools/rust-analyzer/rust-version @@ -1 +1 @@ -1174f784096deb8e4ba93f7e4b5ccb7bb4ba2c55 +4c4205163abcbd08948b3efab796c543ba1ea687 diff --git a/src/tools/rust-analyzer/xtask/src/codegen/grammar.rs b/src/tools/rust-analyzer/xtask/src/codegen/grammar.rs index 4e980bb3d986..257429c42661 100644 --- a/src/tools/rust-analyzer/xtask/src/codegen/grammar.rs +++ b/src/tools/rust-analyzer/xtask/src/codegen/grammar.rs @@ -780,7 +780,7 @@ fn is_many(&self) -> bool { } fn token_kind(&self) -> Option { match self { - Field::Token(token) => { + Field::Token { token, .. } => { let token: proc_macro2::TokenStream = token.parse().unwrap(); Some(quote! { T![#token] }) } @@ -789,8 +789,11 @@ fn token_kind(&self) -> Option { } fn method_name(&self) -> String { match self { - Field::Token(name) => { - let name = match name.as_str() { + Field::Token { name, token, .. } => { + if let Some(name) = name { + return name.clone(); + } + let name = match token.as_str() { ";" => "semicolon", "->" => "thin_arrow", "'{'" => "l_curly", @@ -820,7 +823,7 @@ fn method_name(&self) -> String { "," => "comma", "|" => "pipe", "~" => "tilde", - _ => name, + _ => token, }; format!("{name}_token",) } @@ -835,7 +838,7 @@ fn method_name(&self) -> String { } fn ty(&self) -> proc_macro2::Ident { match self { - Field::Token(_) => format_ident!("SyntaxToken"), + Field::Token { .. } => format_ident!("SyntaxToken"), Field::Node { ty, .. } => format_ident!("{}", ty), } } @@ -885,7 +888,7 @@ fn lower(grammar: &Grammar) -> AstSrc { res.nodes.iter_mut().for_each(|it| { it.traits.sort(); it.fields.sort_by_key(|it| match it { - Field::Token(name) => (true, name.clone()), + Field::Token { token, .. } => (true, token.clone()), Field::Node { name, .. } => (false, name.clone()), }); }); @@ -925,12 +928,11 @@ fn lower_rule(acc: &mut Vec, grammar: &Grammar, label: Option<&String>, r acc.push(field); } Rule::Token(token) => { - assert!(label.is_none()); - let mut name = clean_token_name(&grammar[*token].name); - if "[]{}()".contains(&name) { - name = format!("'{name}'"); + let mut token = clean_token_name(&grammar[*token].name); + if "[]{}()".contains(&token) { + token = format!("'{token}'"); } - let field = Field::Token(name); + let field = Field::Token { name: label.cloned(), token }; acc.push(field); } Rule::Rep(inner) => { @@ -1018,8 +1020,8 @@ fn lower_separated_list( } match nt { Either::Right(token) => { - let name = clean_token_name(&grammar[*token].name); - let field = Field::Token(name); + let token = clean_token_name(&grammar[*token].name); + let field = Field::Token { token, name: None }; acc.push(field); } Either::Left(node) => { diff --git a/src/tools/rust-analyzer/xtask/src/codegen/grammar/ast_src.rs b/src/tools/rust-analyzer/xtask/src/codegen/grammar/ast_src.rs index 564d9cc24efe..a0abdf09d3a5 100644 --- a/src/tools/rust-analyzer/xtask/src/codegen/grammar/ast_src.rs +++ b/src/tools/rust-analyzer/xtask/src/codegen/grammar/ast_src.rs @@ -111,8 +111,19 @@ fn to_tokens(&self, tokens: &mut proc_macro2::TokenStream) { ]; // keywords that are keywords only in specific parse contexts #[doc(alias = "WEAK_KEYWORDS")] -const CONTEXTUAL_KEYWORDS: &[&str] = - &["macro_rules", "union", "default", "raw", "dyn", "auto", "yeet", "safe", "bikeshed"]; +const CONTEXTUAL_KEYWORDS: &[&str] = &[ + "macro_rules", + "union", + "default", + "raw", + "dyn", + "auto", + "yeet", + "safe", + "bikeshed", + "cfg_attr", + "cfg", +]; // keywords we use for special macro expansions const CONTEXTUAL_BUILTIN_KEYWORDS: &[&str] = &[ "asm", @@ -261,7 +272,7 @@ pub(crate) struct AstNodeSrc { #[derive(Debug, Eq, PartialEq)] pub(crate) enum Field { - Token(String), + Token { name: Option, token: String }, Node { name: String, ty: String, cardinality: Cardinality }, } diff --git a/src/tools/rust-analyzer/xtask/src/codegen/lints.rs b/src/tools/rust-analyzer/xtask/src/codegen/lints.rs index 3b4c2e8da3c3..788ae8d6c1dd 100644 --- a/src/tools/rust-analyzer/xtask/src/codegen/lints.rs +++ b/src/tools/rust-analyzer/xtask/src/codegen/lints.rs @@ -83,7 +83,7 @@ pub struct LintGroup { let lints_json = project_root().join("./target/clippy_lints.json"); cmd!( sh, - "curl https://rust-lang.github.io/rust-clippy/stable/lints.json --output {lints_json}" + "curl -f https://raw.githubusercontent.com/rust-lang/rust-clippy/21fd71e3fe6eb063cfb619ecc37b1023f5283894/beta/lints.json --output {lints_json}" ) .run() .unwrap(); diff --git a/src/tools/tidy/src/deps.rs b/src/tools/tidy/src/deps.rs index b0730de77139..11569837fbfa 100644 --- a/src/tools/tidy/src/deps.rs +++ b/src/tools/tidy/src/deps.rs @@ -539,7 +539,8 @@ pub(crate) struct WorkspaceInfo<'a> { "shlex", "unwinding", "vex-sdk", - "wasi", + "wasip1", + "wasip2", "windows-link", "windows-sys", "windows-targets", @@ -881,10 +882,7 @@ fn check_runtime_no_duplicate_dependencies(metadata: &Metadata, check: &mut Runn continue; } - // Skip the `wasi` crate here which the standard library explicitly - // depends on two version of (one for the `wasm32-wasip1` target and - // another for the `wasm32-wasip2` target). - if pkg.name.to_string() != "wasi" && !seen_pkgs.insert(&*pkg.name) { + if !seen_pkgs.insert(&*pkg.name) { check.error(format!( "duplicate package `{}` is not allowed for the standard library", pkg.name diff --git a/src/tools/tidy/src/style.rs b/src/tools/tidy/src/style.rs index 77c15672e002..d144ffa22209 100644 --- a/src/tools/tidy/src/style.rs +++ b/src/tools/tidy/src/style.rs @@ -602,11 +602,34 @@ fn skip(path: &Path, is_dir: bool) -> bool { err(DOUBLE_SPACE_AFTER_DOT) } - if trimmed.contains("//") { + // Heuristics for matching unbalanced backticks by trying to find comments and + // comment blocks. Technically, this can have false negatives (or false positives), + // but as a heuristic this is fine. + let likely_comment = |trimmed: &str| { + // Line comments, doc comments + trimmed.contains("//") + // Also account for `#[cfg_attr(bootstrap, doc = "")]` cases. + || (trimmed.contains("cfg_attr") && trimmed.contains("doc")) + }; + + if likely_comment(trimmed) { let (start_line, mut backtick_count) = comment_block.unwrap_or((i + 1, 0)); let line_backticks = trimmed.chars().filter(|ch| *ch == '`').count(); - let comment_text = trimmed.split("//").nth(1).unwrap(); - // This check ensures that we don't lint for code that has `//` in a string literal + + // Try to split `//`-like comments or `#[cfg_attr(bootstrap), doc = ""]`-like + // doc attributes. Fuzzy, but probably good enough. + let comment_text = match trimmed.split("//").nth(1) { + Some(text) => text, + None => { + // Fallback to try look for RHS of doc attr bits. + let (_doc, rest) = + trimmed.split_once("doc").expect("failed to find `doc` attribute"); + rest + } + }; + + // If backticks on a given comment line is not balanced, add to backtick count. + // This is to account for wrapped backticks and code blocks. if line_backticks % 2 == 1 { backtick_count += comment_text.chars().filter(|ch| *ch == '`').count(); } diff --git a/src/tools/unicode-table-generator/src/main.rs b/src/tools/unicode-table-generator/src/main.rs index cdd137ff56a5..398b4c7b7ec5 100644 --- a/src/tools/unicode-table-generator/src/main.rs +++ b/src/tools/unicode-table-generator/src/main.rs @@ -91,11 +91,11 @@ "Alphabetic", "Lowercase", "Uppercase", - "Cased", "Case_Ignorable", "Grapheme_Extend", "White_Space", "N", + "Lt", ]; struct UnicodeData { diff --git a/src/version b/src/version index 9141007a5582..acbb747ac540 100644 --- a/src/version +++ b/src/version @@ -1 +1 @@ -1.96.0 +1.97.0 diff --git a/tests/assembly-llvm/aarch64-vld2-s16.rs b/tests/assembly-llvm/aarch64-vld2-s16.rs new file mode 100644 index 000000000000..137422f30019 --- /dev/null +++ b/tests/assembly-llvm/aarch64-vld2-s16.rs @@ -0,0 +1,46 @@ +//@ assembly-output: emit-asm +//@ compile-flags: -Copt-level=3 +//@ only-aarch64-unknown-linux-gnu +#![feature(repr_simd, portable_simd, core_intrinsics, f16, f128)] +#![crate_type = "lib"] +#![allow(non_camel_case_types)] + +// Test `vld_s16` can be implemented in a portable way (i.e. without using LLVM neon intrinsics). +// This relies on rust preserving the SIMD vector element type and using it to construct the +// LLVM type. Without this information, additional casts are needed that defeat the LLVM pattern +// matcher, see https://github.com/llvm/llvm-project/issues/181514. + +use std::mem::transmute; +use std::simd::Simd; + +#[unsafe(no_mangle)] +#[target_feature(enable = "neon")] +unsafe extern "C" fn vld2_s16_old(ptr: *const i16) -> std::arch::aarch64::int16x4x2_t { + // CHECK-LABEL: vld2_s16_old + // CHECK: .cfi_startproc + // CHECK-NEXT: ld2 { v0.4h, v1.4h }, [x0] + // CHECK-NEXT: ret + std::arch::aarch64::vld2_s16(ptr) +} + +#[unsafe(no_mangle)] +#[target_feature(enable = "neon")] +unsafe extern "C" fn vld2_s16_new(a: *const i16) -> std::arch::aarch64::int16x4x2_t { + // CHECK-LABEL: vld2_s16_new + // CHECK: .cfi_startproc + // CHECK-NEXT: ld2 { v0.4h, v1.4h }, [x0] + // CHECK-NEXT: ret + + type V = Simd; + type W = Simd; + + let w: W = std::ptr::read_unaligned(a as *const W); + + #[repr(simd)] + pub(crate) struct SimdShuffleIdx([u32; LEN]); + + let v0: V = std::intrinsics::simd::simd_shuffle(w, w, const { SimdShuffleIdx([0, 2, 4, 6]) }); + let v1: V = std::intrinsics::simd::simd_shuffle(w, w, const { SimdShuffleIdx([1, 3, 5, 7]) }); + + transmute((v0, v1)) +} diff --git a/tests/assembly-llvm/issue-141649.rs b/tests/assembly-llvm/issue-141649.rs new file mode 100644 index 000000000000..646ce41d5e57 --- /dev/null +++ b/tests/assembly-llvm/issue-141649.rs @@ -0,0 +1,81 @@ +//@ assembly-output: emit-asm +//@ compile-flags: -Copt-level=3 + +//@ revisions: aarch64 +//@ [aarch64] only-aarch64 + +//@ revisions: linux-x86_64 +//@ [linux-x86_64] compile-flags: --target x86_64-unknown-linux-gnu +//@ [linux-x86_64] only-x86_64-unknown-linux-gnu +//@ [linux-x86_64] needs-llvm-components: x86 + +//@ revisions: windows-x86_64-msvc +//@ [windows-x86_64-msvc] compile-flags: --target x86_64-pc-windows-msvc +//@ [windows-x86_64-msvc] needs-llvm-components: x86 +//@ [windows-x86_64-msvc] only-x86_64-pc-windows-msvc + +#![crate_type = "lib"] + +// Non-overlapping scopes should reuse of the same stack allocation. + +pub struct WithOffset { + pub data: T, + pub offset: usize, +} + +#[inline(never)] +pub fn peak_w(w: &WithOffset<&[u8; 16]>) { + std::hint::black_box(w); +} + +#[inline(never)] +pub fn use_w(w: WithOffset<&[u8; 16]>) { + std::hint::black_box(w); +} + +// CHECK-LABEL: scoped_two_small_structs +#[no_mangle] +pub fn scoped_two_small_structs(buf: [u8; 16]) { + { + let w = WithOffset { data: &buf, offset: 0 }; + + peak_w(&w); + use_w(w); + } + { + let w2 = WithOffset { data: &buf, offset: 1 }; + + peak_w(&w2); + use_w(w2); + } + // linux-x86_64: subq $16, %rsp + // windows-x86_64-msvc: subq $48, %rsp + // aarch64: sub sp, sp, #48 +} + +// CHECK-LABEL: scoped_three_small_structs +#[no_mangle] +pub fn scoped_three_small_structs(buf: [u8; 16]) { + { + let w = WithOffset { data: &buf, offset: 0 }; + + peak_w(&w); + use_w(w); + } + { + let w2 = WithOffset { data: &buf, offset: 1 }; + + peak_w(&w2); + use_w(w2); + } + { + let w3 = WithOffset { data: &buf, offset: 1 }; + + peak_w(&w3); + use_w(w3); + } + // Should be the same stack usage as the two struct version. + // linux-x86_64: subq $16, %rsp + // windows-x86_64-msvc: subq $48, %rsp + // aarch64: sub sp, sp, #48 +} diff --git a/tests/assembly-llvm/naked-functions/function-sections.rs b/tests/assembly-llvm/naked-functions/function-sections.rs new file mode 100644 index 000000000000..751812bd768b --- /dev/null +++ b/tests/assembly-llvm/naked-functions/function-sections.rs @@ -0,0 +1,97 @@ +//@ add-minicore +//@ assembly-output: emit-asm +// +//@ revisions: linux-x86-gnu-fs-true linux-x86-gnu-fs-false +//@[linux-x86-gnu-fs-true] compile-flags: --target x86_64-unknown-linux-gnu -Zfunction-sections=true +//@[linux-x86-gnu-fs-true] needs-llvm-components: x86 +//@[linux-x86-gnu-fs-false] compile-flags: --target x86_64-unknown-linux-gnu -Zfunction-sections=false +//@[linux-x86-gnu-fs-false] needs-llvm-components: x86 +// +//@ revisions: macos-aarch64-fs-true macos-aarch64-fs-false +//@[macos-aarch64-fs-true] compile-flags: --target aarch64-apple-darwin -Zfunction-sections=true +//@[macos-aarch64-fs-true] needs-llvm-components: aarch64 +//@[macos-aarch64-fs-false] compile-flags: --target aarch64-apple-darwin -Zfunction-sections=false +//@[macos-aarch64-fs-false] needs-llvm-components: aarch64 +// +//@ revisions: windows-x86-gnu-fs-true windows-x86-gnu-fs-false +//@[windows-x86-gnu-fs-true] compile-flags: --target x86_64-pc-windows-gnu -Zfunction-sections=true +//@[windows-x86-gnu-fs-true] needs-llvm-components: x86 +//@[windows-x86-gnu-fs-false] compile-flags: --target x86_64-pc-windows-gnu -Zfunction-sections=false +//@[windows-x86-gnu-fs-false] needs-llvm-components: x86 +// +//@ revisions: windows-x86-msvc-fs-true windows-x86-msvc-fs-false +//@[windows-x86-msvc-fs-true] compile-flags: --target x86_64-pc-windows-msvc -Zfunction-sections=true +//@[windows-x86-msvc-fs-true] needs-llvm-components: x86 +//@[windows-x86-msvc-fs-false] compile-flags: --target x86_64-pc-windows-msvc -Zfunction-sections=false +//@[windows-x86-msvc-fs-false] needs-llvm-components: x86 +// +//@ revisions: x86-uefi-fs-true x86-uefi-fs-false +//@[x86-uefi-fs-true] compile-flags: --target x86_64-unknown-uefi -Zfunction-sections=true +//@[x86-uefi-fs-true] needs-llvm-components: x86 +//@[x86-uefi-fs-false] compile-flags: --target x86_64-unknown-uefi -Zfunction-sections=false +//@[x86-uefi-fs-false] needs-llvm-components: x86 + +#![crate_type = "lib"] +#![feature(no_core)] +#![no_core] + +// Tests that naked and non-naked functions emit the same directives when (not) using +// -Zfunction-sections. This setting is ignored on macos, off by default on windows gnu, +// and on by default in the remaining revisions tested here. + +extern crate minicore; +use minicore::*; + +#[unsafe(naked)] +#[unsafe(no_mangle)] +extern "C" fn naked_ret() { + // linux-x86-gnu-fs-true: .section .text.naked_ret,"ax",@progbits + // linux-x86-gnu-fs-false: .text + // + // macos-aarch64-fs-true: .section __TEXT,__text,regular,pure_instructions + // macos-aarch64-fs-false: .section __TEXT,__text,regular,pure_instructions + // + // NOTE: the regular function below adds `unique,0` at the end, but we have no way of generating + // the unique ID to use there, so don't emit that part. + // + // windows-x86-gnu-fs-true: .section .text$naked_ret,"xr",one_only,naked_ret + // windows-x86-msvc-fs-true: .section .text,"xr",one_only,naked_ret + // x86-uefi-fs-true: .section .text,"xr",one_only,naked_ret + // + // windows-x86-gnu-fs-false: .text + // windows-x86-msvc-fs-false: .text + // x86-uefi-fs-false: .text + // + // CHECK-LABEL: naked_ret: + naked_asm!("ret") +} + +// Use a different section here so that `regular_ret` has to explicitly specify the section. +#[link_section = cfg_select!( + target_os = "macos" => "__FOO,bar", + _ => ".bar", +)] +#[unsafe(no_mangle)] +extern "C" fn omarker() -> i32 { + // CHECK-LABEL: omarker: + 32 +} + +#[unsafe(no_mangle)] +extern "C" fn regular_ret() { + // linux-x86-gnu-fs-true: .section .text.regular_ret,"ax",@progbits + // linux-x86-gnu-fs-false: .text + // + // macos-aarch64-fs-true: .section __TEXT,__text,regular,pure_instructions + // macos-aarch64-fs-false: .section __TEXT,__text,regular,pure_instructions + // + // windows-x86-gnu-fs-true: .section .text$regular_ret,"xr",one_only,regular_ret,unique,0 + // windows-x86-msvc-fs-true: .section .text,"xr",one_only,regular_ret,unique,0 + // x86-uefi-fs-true: .section .text,"xr",one_only,regular_ret,unique,0 + // + // windows-x86-gnu-fs-false: .text + // windows-x86-msvc-fs-false: .text + // x86-uefi-fs-false: .text + // + // CHECK-LABEL: regular_ret: +} diff --git a/tests/assembly-llvm/naked-functions/link-section-windows.rs b/tests/assembly-llvm/naked-functions/link-section-windows.rs index 5823498973a3..35782a7bf92c 100644 --- a/tests/assembly-llvm/naked-functions/link-section-windows.rs +++ b/tests/assembly-llvm/naked-functions/link-section-windows.rs @@ -1,4 +1,4 @@ -//@ revisions: windows-x86-gnu windows-x86-msvc +//@ revisions: windows-x86-gnu windows-x86-msvc x86-uefi //@ add-minicore //@ assembly-output: emit-asm // @@ -7,6 +7,9 @@ // //@[windows-x86-msvc] compile-flags: --target x86_64-pc-windows-msvc //@[windows-x86-msvc] needs-llvm-components: x86 +// +//@[x86-uefi] compile-flags: --target x86_64-unknown-uefi +//@[x86-uefi] needs-llvm-components: x86 #![crate_type = "lib"] #![feature(no_core)] diff --git a/tests/auxiliary/minicore.rs b/tests/auxiliary/minicore.rs index 5c6eb5483243..24da2c4a1c4e 100644 --- a/tests/auxiliary/minicore.rs +++ b/tests/auxiliary/minicore.rs @@ -22,6 +22,7 @@ auto_traits, freeze_impls, negative_impls, + pattern_types, rustc_attrs, decl_macro, f16, @@ -127,17 +128,42 @@ pub struct ManuallyDrop { impl Copy for ManuallyDrop {} #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] pub struct NonNull { - pointer: *const T, + pointer: pattern_type!(*const T is !null), } impl Copy for NonNull {} #[repr(transparent)] -#[rustc_layout_scalar_valid_range_start(1)] #[rustc_nonnull_optimization_guaranteed] -pub struct NonZero(T); +pub struct NonZero(T::NonZeroInner); + +pub trait ZeroablePrimitive { + type NonZeroInner; +} + +macro_rules! define_valid_range_type { + ($( + $name:ident($int:ident is $pat:pat); + )+) => {$( + #[repr(transparent)] + pub struct $name(pattern_type!($int is $pat)); + + impl ZeroablePrimitive for $int { + type NonZeroInner = $name; + } + )+}; +} + +define_valid_range_type! { + NonZeroU8Inner(u8 is 1..=0xFF); + NonZeroU16Inner(u16 is 1..=0xFFFF); + NonZeroU32Inner(u32 is 1..=0xFFFF_FFFF); + NonZeroU64Inner(u64 is 1..=0xFFFF_FFFF_FFFF_FFFF); + + NonZeroI8Inner(i8 is (-128..=-1 | 1..=0x7F)); + NonZeroI32Inner(i32 is (-0x8000_0000..=-1 | 1..=0x7FFF_FFFF)); +} pub struct Unique { pub pointer: NonNull, @@ -187,6 +213,12 @@ macro_rules! stringify { }; } +#[rustc_builtin_macro] +#[macro_export] +macro_rules! compile_error { + ($msg:expr $(,)?) => {{ /* compiler built-in */ }}; +} + #[lang = "add"] pub trait Add { type Output; @@ -225,6 +257,14 @@ fn neg(self) -> i8 { } } +impl Neg for i32 { + type Output = i32; + + fn neg(self) -> i32 { + loop {} + } +} + #[lang = "sync"] pub trait Sync {} impl_marker_trait!( @@ -314,6 +354,14 @@ pub enum c_void { __variant2, } +#[rustc_builtin_macro(pattern_type)] +#[macro_export] +macro_rules! pattern_type { + ($($arg:tt)*) => { + /* compiler built-in */ + }; +} + #[lang = "Ordering"] #[repr(i8)] pub enum Ordering { diff --git a/tests/codegen-llvm/enum/enum-array-index-spare-niche.rs b/tests/codegen-llvm/enum/enum-array-index-spare-niche.rs new file mode 100644 index 000000000000..e758996a29e0 --- /dev/null +++ b/tests/codegen-llvm/enum/enum-array-index-spare-niche.rs @@ -0,0 +1,28 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/113899. +//! When indexing into an array of an enum type with spare niches, the compiler +//! used to emit a superfluous branch checking whether the loaded value was +//! a niche value. Every element in the array is a valid variant, so this check +//! is unnecessary and should be optimised away. + +//@ compile-flags: -Copt-level=3 +#![crate_type = "lib"] + +#[derive(Clone, Copy)] +pub enum Outer { + A([u8; 8]), + B([u8; 8]), +} + +pub struct Error(u8); + +// CHECK-LABEL: @test +#[no_mangle] +pub fn test(x: usize) -> Result { + // There should be exactly one comparison: the bounds check on `x`. + // There must be no second comparison checking the discriminant + // against the niche value used by `Option` (from `get()`). + // CHECK: icmp ult + // CHECK-NOT: icmp + // CHECK: ret void + [Outer::A([10; 8]), Outer::B([20; 8])].get(x).copied().ok_or(Error(5)) +} diff --git a/tests/codegen-llvm/inject-autocast.rs b/tests/codegen-llvm/inject-autocast.rs new file mode 100644 index 000000000000..fec9d3f0b195 --- /dev/null +++ b/tests/codegen-llvm/inject-autocast.rs @@ -0,0 +1,93 @@ +//@ compile-flags: -C opt-level=0 -C target-feature=+kl,+avx512vp2intersect,+avx512vl,+avxneconvert +//@ only-x86_64 + +#![feature(link_llvm_intrinsics, abi_unadjusted, simd_ffi, portable_simd)] +#![crate_type = "lib"] + +use std::simd::{f32x4, i16x8, i64x2}; + +#[repr(C, packed)] +pub struct Bar(u32, i64x2, i64x2, i64x2, i64x2, i64x2, i64x2); +// CHECK: %Bar = type <{ i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> }> + +// CHECK-LABEL: @struct_autocast +#[no_mangle] +pub unsafe fn struct_autocast(key_metadata: u32, key: i64x2) -> Bar { + extern "unadjusted" { + #[link_name = "llvm.x86.encodekey128"] + fn foo(key_metadata: u32, key: i64x2) -> Bar; + } + + // CHECK: [[A:%[0-9]+]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 {{.*}}, <2 x i64> {{.*}}) + // CHECK: [[B:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 0 + // CHECK: [[C:%[0-9]+]] = insertvalue %Bar poison, i32 [[B]], 0 + // CHECK: [[D:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 1 + // CHECK: [[E:%[0-9]+]] = insertvalue %Bar [[C]], <2 x i64> [[D]], 1 + // CHECK: [[F:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 2 + // CHECK: [[G:%[0-9]+]] = insertvalue %Bar [[E]], <2 x i64> [[F]], 2 + // CHECK: [[H:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 3 + // CHECK: [[I:%[0-9]+]] = insertvalue %Bar [[G]], <2 x i64> [[H]], 3 + // CHECK: [[J:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 4 + // CHECK: [[K:%[0-9]+]] = insertvalue %Bar [[I]], <2 x i64> [[J]], 4 + // CHECK: [[L:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 5 + // CHECK: [[M:%[0-9]+]] = insertvalue %Bar [[K]], <2 x i64> [[L]], 5 + // CHECK: [[N:%[0-9]+]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[A]], 6 + // CHECK: insertvalue %Bar [[M]], <2 x i64> [[N]], 6 + foo(key_metadata, key) +} + +// CHECK-LABEL: @struct_with_i1_vector_autocast +#[no_mangle] +pub unsafe fn struct_with_i1_vector_autocast(a: i64x2, b: i64x2) -> (u8, u8) { + extern "unadjusted" { + #[link_name = "llvm.x86.avx512.vp2intersect.q.128"] + fn foo(a: i64x2, b: i64x2) -> (u8, u8); + } + + // CHECK: [[A:%[0-9]+]] = call { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}) + // CHECK: [[B:%[0-9]+]] = extractvalue { <2 x i1>, <2 x i1> } [[A]], 0 + // CHECK: [[C:%[0-9]+]] = shufflevector <2 x i1> [[B]], <2 x i1> zeroinitializer, <8 x i32> + // CHECK: [[D:%[0-9]+]] = bitcast <8 x i1> [[C]] to i8 + // CHECK: [[E:%[0-9]+]] = insertvalue { i8, i8 } poison, i8 [[D]], 0 + // CHECK: [[F:%[0-9]+]] = extractvalue { <2 x i1>, <2 x i1> } [[A]], 1 + // CHECK: [[G:%[0-9]+]] = shufflevector <2 x i1> [[F]], <2 x i1> zeroinitializer, <8 x i32> + // CHECK: [[H:%[0-9]+]] = bitcast <8 x i1> [[G]] to i8 + // CHECK: insertvalue { i8, i8 } [[E]], i8 [[H]], 1 + foo(a, b) +} + +// CHECK-LABEL: @i1_vector_autocast +#[no_mangle] +pub unsafe fn i1_vector_autocast(a: u8, b: u8) -> u8 { + extern "unadjusted" { + #[link_name = "llvm.x86.avx512.kadd.b"] + fn foo(a: u8, b: u8) -> u8; + } + + // CHECK: [[A:%[0-9]+]] = bitcast i8 {{.*}} to <8 x i1> + // CHECK: [[B:%[0-9]+]] = bitcast i8 {{.*}} to <8 x i1> + // CHECK: [[C:%[0-9]+]] = call <8 x i1> @llvm.x86.avx512.kadd.b(<8 x i1> [[A]], <8 x i1> [[B]]) + // CHECK: bitcast <8 x i1> [[C]] to i8 + foo(a, b) +} + +// CHECK-LABEL: @bf16_vector_autocast +#[no_mangle] +pub unsafe fn bf16_vector_autocast(a: f32x4) -> i16x8 { + extern "unadjusted" { + #[link_name = "llvm.x86.vcvtneps2bf16128"] + fn foo(a: f32x4) -> i16x8; + } + + // CHECK: [[A:%[0-9]+]] = call <8 x bfloat> @llvm.x86.vcvtneps2bf16128(<4 x float> {{.*}}) + // CHECK: bitcast <8 x bfloat> [[A]] to <8 x i16> + foo(a) +} + +// CHECK: declare { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32, <2 x i64>) + +// CHECK: declare { <2 x i1>, <2 x i1> } @llvm.x86.avx512.vp2intersect.q.128(<2 x i64>, <2 x i64>) + +// CHECK: declare <8 x i1> @llvm.x86.avx512.kadd.b(<8 x i1>, <8 x i1>) + +// CHECK: declare <8 x bfloat> @llvm.x86.vcvtneps2bf16128(<4 x float>) diff --git a/tests/codegen-llvm/issues/issue-123712-str-to-lower-autovectorization.rs b/tests/codegen-llvm/issues/issue-123712-str-to-lower-autovectorization.rs index 11ee10e8cc33..4bf7fa12760b 100644 --- a/tests/codegen-llvm/issues/issue-123712-str-to-lower-autovectorization.rs +++ b/tests/codegen-llvm/issues/issue-123712-str-to-lower-autovectorization.rs @@ -19,5 +19,6 @@ // CHECK-NEXT: [[C:%[0-9]]] = bitcast <16 x i1> [[B]] to i16 #[no_mangle] pub fn lower_while_ascii(s: &str) -> (alloc::string::String, &str) { - alloc::str::convert_while_ascii(s, u8::to_ascii_lowercase) + // SAFETY: `to_ascii_lowercase` preserves ASCII bytes. + unsafe { alloc::str::convert_while_ascii(s, u8::to_ascii_lowercase) } } diff --git a/tests/codegen-llvm/issues/issue-141649.rs b/tests/codegen-llvm/issues/issue-141649.rs new file mode 100644 index 000000000000..6377a9957857 --- /dev/null +++ b/tests/codegen-llvm/issues/issue-141649.rs @@ -0,0 +1,45 @@ +//@ compile-flags: -Copt-level=3 + +#![crate_type = "lib"] + +// Non-overlapping scopes should produce correct llvm.lifetimes, +// which allow reuse of the same stack allocation. + +pub struct WithOffset { + pub data: T, + pub offset: usize, +} + +#[inline(never)] +pub fn peak_w(w: &WithOffset<&[u8; 16]>) { + std::hint::black_box(w); +} + +#[inline(never)] +pub fn use_w(w: WithOffset<&[u8; 16]>) { + std::hint::black_box(w); +} + +// CHECK-LABEL: @scoped_small_structs +// CHECK-NEXT: start: +// CHECK-NEXT: [[B:%.*]] = alloca +// CHECK-NEXT: [[A:%.*]] = alloca +// CHECK: call void @llvm.lifetime.start.p0({{(i64 16, )?}}ptr {{.*}}[[A]]) +// CHECK: call void @llvm.lifetime.end.p0({{(i64 16, )?}}ptr {{.*}}[[A]]) +// CHECK: call void @llvm.lifetime.start.p0({{(i64 16, )?}}ptr {{.*}}[[B]]) +// CHECK: call void @llvm.lifetime.end.p0({{(i64 16, )?}}ptr {{.*}}[[B]]) +#[no_mangle] +pub fn scoped_small_structs(buf: [u8; 16]) { + { + let w = WithOffset { data: &buf, offset: 0 }; + + peak_w(&w); + use_w(w); + } + { + let w2 = WithOffset { data: &buf, offset: 1 }; + + peak_w(&w2); + use_w(w2); + } +} diff --git a/tests/codegen-llvm/llvm-writable.rs b/tests/codegen-llvm/llvm-writable.rs new file mode 100644 index 000000000000..ea245fc3a6e7 --- /dev/null +++ b/tests/codegen-llvm/llvm-writable.rs @@ -0,0 +1,30 @@ +//! The tests here test that the `-Zllvm-writable` flag and +//! the `#[rustc_no_writable]` attribute have the desired effect. +//@ compile-flags: -Copt-level=3 -C no-prepopulate-passes -Zllvm-writable +#![crate_type = "lib"] +#![feature(rustc_attrs, unsafe_pinned)] + +// CHECK: @mutable_borrow(ptr noalias noundef writable align 4 dereferenceable(4) %_1) +#[no_mangle] +pub fn mutable_borrow(_: &mut i32) {} + +// CHECK: @mutable_unsafe_borrow(ptr noalias noundef writable align 2 dereferenceable(2) %_1) +#[no_mangle] +pub fn mutable_unsafe_borrow(_: &mut std::cell::UnsafeCell) {} + +// CHECK: @option_borrow_mut(ptr noalias noundef writable align 4 dereferenceable_or_null(4) %_1) +#[no_mangle] +pub fn option_borrow_mut(_: Option<&mut i32>) {} + +// CHECK: @box_moved(ptr noalias noundef nonnull align 4 %0) +#[no_mangle] +pub fn box_moved(_: Box) {} + +// CHECK: @unsafe_pinned_borrow_mut(ptr noundef nonnull align 4 %_1) +#[no_mangle] +pub fn unsafe_pinned_borrow_mut(_: &mut std::pin::UnsafePinned) {} + +// CHECK: @mutable_borrow_no_writable(ptr noalias noundef align 4 dereferenceable(4) %_1) +#[no_mangle] +#[rustc_no_writable] +pub fn mutable_borrow_no_writable(_: &mut i32) {} diff --git a/tests/codegen-llvm/naked-fn/naked-functions.rs b/tests/codegen-llvm/naked-fn/naked-functions.rs index b5c84ede8f06..a782ab5310e3 100644 --- a/tests/codegen-llvm/naked-fn/naked-functions.rs +++ b/tests/codegen-llvm/naked-fn/naked-functions.rs @@ -1,12 +1,21 @@ +// ignore-tidy-linelength +// //@ add-minicore -//@ revisions: linux win_x86 win_i686 macos thumb +//@ revisions: linux linux_no_function_sections macos thumb +//@ revisions: win_x86_msvc win_x86_gnu win_i686_gnu win_x86_gnu_function_sections // //@[linux] compile-flags: --target x86_64-unknown-linux-gnu //@[linux] needs-llvm-components: x86 -//@[win_x86] compile-flags: --target x86_64-pc-windows-gnu -//@[win_x86] needs-llvm-components: x86 -//@[win_i686] compile-flags: --target i686-pc-windows-gnu -//@[win_i686] needs-llvm-components: x86 +//@[linux_no_function_sections] compile-flags: --target x86_64-unknown-linux-gnu -Zfunction-sections=false +//@[linux_no_function_sections] needs-llvm-components: x86 +//@[win_x86_gnu] compile-flags: --target x86_64-pc-windows-gnu +//@[win_x86_gnu] needs-llvm-components: x86 +//@[win_x86_gnu_function_sections] compile-flags: --target x86_64-pc-windows-gnu -Zfunction-sections +//@[win_x86_gnu_function_sections] needs-llvm-components: x86 +//@[win_x86_msvc] compile-flags: --target x86_64-pc-windows-msvc +//@[win_x86_msvc] needs-llvm-components: x86 +//@[win_i686_gnu] compile-flags: --target i686-pc-windows-gnu +//@[win_i686_gnu] needs-llvm-components: x86 //@[macos] compile-flags: --target aarch64-apple-darwin //@[macos] needs-llvm-components: aarch64 //@[thumb] compile-flags: --target thumbv7em-none-eabi @@ -19,15 +28,22 @@ extern crate minicore; use minicore::*; -// linux,win_x86,win_i686: .intel_syntax +// linux,win_x86_gnu,win_i686_gnu: .intel_syntax // // linux: .pushsection .text.naked_empty,\22ax\22, @progbits -// macos: .pushsection __TEXT,__text,regular,pure_instructions +// linux_no_function_sections: .text +// macos-NOT: .pushsection +// +// win_x86_msvc: .section .text,\22xr\22,one_only,naked_empty +// win_x86_gnu_function_sections: .section .text$naked_empty,\22xr\22,one_only,naked_empty +// win_x86_gnu-NOT: .section +// win_i686_gnu-NOT: .section +// // thumb: .pushsection .text.naked_empty,\22ax\22, %progbits // // linux, macos, thumb: .balign 4 // -// linux,thumb: .globl naked_empty +// linux,win_x86_gnu,thumb: .globl naked_empty // macos: .globl _naked_empty // // CHECK-NOT: .private_extern @@ -35,12 +51,12 @@ // // linux: .type naked_empty, @function // -// win_x86: .def naked_empty -// win_i686: .def _naked_empty +// win_x86_msvc,win_x86_gnu: .def naked_empty +// win_i686_gnu: .def _naked_empty // -// win_x86,win_i686: .scl 2 -// win_x86,win_i686: .type 32 -// win_x86,win_i686: .endef +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .scl 2 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .type 32 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .endef // // win_x86: .pushsection .text.naked_empty,\22xr\22 // win_i686: .pushsection .text._naked_empty,\22xr\22 @@ -56,10 +72,11 @@ // // CHECK-LABEL: naked_empty: // -// linux,macos,win_x86,win_x86: ret +// linux,macos,win_x86_msvc,win_x86_gnu,win_i686_gnu: ret // thumb: bx lr // -// linux,macos,thumb: .popsection +// linux,windows,win_x86_msvc,thumb: .popsection +// win_x86_gnu-NOT,win_i686_gnu-NOT: .popsection // // thumb: .thumb // @@ -78,15 +95,22 @@ pub extern "C" fn naked_empty() { } } -// linux,win_x86,win_i686: .intel_syntax +// linux,win_x86_gnu,win_i686_gnu,win_x86_msvc: .intel_syntax // // linux: .pushsection .text.naked_with_args_and_return,\22ax\22, @progbits -// macos: .pushsection __TEXT,__text,regular,pure_instructions +// linux_no_function_sections: .text +// macos-NOT: .pushsection +// +// win_x86_msvc: .section .text,\22xr\22,one_only,naked_with_args_and_return +// win_x86_gnu_function_sections: .section .text$naked_with_args_and_return,\22xr\22,one_only,naked_with_args_and_return +// win_x86_gnu-NOT: .section +// win_i686_gnu-NOT: .section +// // thumb: .pushsection .text.naked_with_args_and_return,\22ax\22, %progbits // // linux, macos, thumb: .balign 4 // -// linux,thumb: .globl naked_with_args_and_return +// linux,win_x86_gnu,win_x86_msvc,win_i686_gnu,thumb: .globl naked_with_args_and_return // macos: .globl _naked_with_args_and_return // // CHECK-NOT: .private_extern @@ -94,12 +118,12 @@ pub extern "C" fn naked_empty() { // // linux: .type naked_with_args_and_return, @function // -// win_x86: .def naked_with_args_and_return -// win_i686: .def _naked_with_args_and_return +// win_x86_msvc,win_x86_gnu: .def naked_with_args_and_return +// win_i686_gnu: .def _naked_with_args_and_return // -// win_x86,win_i686: .scl 2 -// win_x86,win_i686: .type 32 -// win_x86,win_i686: .endef +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .scl 2 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .type 32 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .endef // // win_x86: .pushsection .text.naked_with_args_and_return,\22xr\22 // win_i686: .pushsection .text._naked_with_args_and_return,\22xr\22 @@ -115,14 +139,15 @@ pub extern "C" fn naked_empty() { // // CHECK-LABEL: naked_with_args_and_return: // -// linux, win_x86,win_i686: lea rax, [rdi + rsi] +// linux,win_x86_msvc,win_x86_gnu,win_i686_gnu: lea rax, [rdi + rsi] // macos: add x0, x0, x1 // thumb: adds r0, r0, r1 // -// linux,macos,win_x86,win_i686: ret +// linux,macos,win_x86_msvc,win_x86_gnu,win_i686_gnu: ret // thumb: bx lr // -// linux,macos,thumb: .popsection +// linux,windows,win_x86_msvc,thumb: .popsection +// win_x86_gnu-NOT,win_i686_gnu-NOT: .popsection // // thumb: .thumb // @@ -144,9 +169,10 @@ pub extern "C" fn naked_with_args_and_return(a: isize, b: isize) -> isize { } } -// linux: .pushsection .text.some_different_name,\22ax\22, @progbits +// linux,linux_no_function_sections: .pushsection .text.some_different_name,\22ax\22, @progbits // macos: .pushsection .text.some_different_name,regular,pure_instructions -// win_x86,win_i686: .pushsection .text.some_different_name,\22xr\22 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .section .text.some_different_name,\22xr\22 +// win_x86_gnu_function_sections: .section .text.some_different_name,\22xr\22 // thumb: .pushsection .text.some_different_name,\22ax\22, %progbits // CHECK-LABEL: test_link_section: #[no_mangle] @@ -163,15 +189,15 @@ pub extern "C" fn test_link_section() { } } -// win_x86: .def fastcall_cc -// win_i686: .def @fastcall_cc@4 +// win_x86_msvc,win_x86_gnu: .def fastcall_cc +// win_i686_gnu: .def @fastcall_cc@4 // -// win_x86,win_i686: .scl 2 -// win_x86,win_i686: .type 32 -// win_x86,win_i686: .endef +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .scl 2 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .type 32 +// win_x86_msvc,win_x86_gnu,win_i686_gnu: .endef // -// win_x86-LABEL: fastcall_cc: -// win_i686-LABEL: @fastcall_cc@4: +// win_x86_msvc-LABEL,win_x86_gnu-LABEL: fastcall_cc: +// win_i686_gnu-LABEL: @fastcall_cc@4: #[cfg(target_os = "windows")] #[no_mangle] #[unsafe(naked)] diff --git a/tests/codegen-llvm/preserve-vec-element-types.rs b/tests/codegen-llvm/preserve-vec-element-types.rs new file mode 100644 index 000000000000..bfa45177a952 --- /dev/null +++ b/tests/codegen-llvm/preserve-vec-element-types.rs @@ -0,0 +1,98 @@ +// ignore-tidy-linelength +//@ compile-flags: -Copt-level=3 -Zmerge-functions=disabled --target=aarch64-unknown-linux-gnu +//@ needs-llvm-components: aarch64 +//@ add-minicore +#![feature(no_core, repr_simd, f16, f128)] +#![crate_type = "lib"] +#![no_std] +#![no_core] +#![allow(non_camel_case_types)] + +// Test that the SIMD vector element type is preserved. This is not required for correctness, but +// useful for optimization. It prevents additional bitcasts that make LLVM patterns fail. + +extern crate minicore; +use minicore::*; + +#[repr(simd)] +pub struct Simd([T; N]); + +#[repr(C)] +struct Pair(T, T); + +#[repr(C)] +struct Triple(T, T, T); + +#[repr(C)] +struct Quad(T, T, T, T); + +#[rustfmt::skip] +mod tests { + use super::*; + + // CHECK: define [2 x <8 x i8>] @pair_int8x8_t([2 x <8 x i8>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_int8x8_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <4 x i16>] @pair_int16x4_t([2 x <4 x i16>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_int16x4_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <2 x i32>] @pair_int32x2_t([2 x <2 x i32>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_int32x2_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <1 x i64>] @pair_int64x1_t([2 x <1 x i64>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_int64x1_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <4 x half>] @pair_float16x4_t([2 x <4 x half>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_float16x4_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <2 x float>] @pair_float32x2_t([2 x <2 x float>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_float32x2_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <1 x double>] @pair_float64x1_t([2 x <1 x double>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_float64x1_t(x: Pair>) -> Pair> { x } + + // CHECK: define [2 x <1 x ptr>] @pair_ptrx1_t([2 x <1 x ptr>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn pair_ptrx1_t(x: Pair>) -> Pair> { x } + + // When it fits in a 128-bit register, it's passed directly. + + // CHECK: define [4 x <4 x i8>] @quad_int8x4_t([4 x <4 x i8>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn quad_int8x4_t(x: Quad>) -> Quad> { x } + + // CHECK: define [4 x <2 x i16>] @quad_int16x2_t([4 x <2 x i16>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn quad_int16x2_t(x: Quad>) -> Quad> { x } + + // CHECK: define [4 x <1 x i32>] @quad_int32x1_t([4 x <1 x i32>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn quad_int32x1_t(x: Quad>) -> Quad> { x } + + // CHECK: define [4 x <2 x half>] @quad_float16x2_t([4 x <2 x half>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn quad_float16x2_t(x: Quad>) -> Quad> { x } + + // CHECK: define [4 x <1 x float>] @quad_float32x1_t([4 x <1 x float>] {{.*}} %0) + #[unsafe(no_mangle)] extern "C" fn quad_float32x1_t(x: Quad>) -> Quad> { x } + + // When it doesn't quite fit, padding is added which does erase the type. + + // CHECK: define [2 x i64] @triple_int8x4_t + #[unsafe(no_mangle)] extern "C" fn triple_int8x4_t(x: Triple>) -> Triple> { x } + + // Other configurations are not passed by-value but indirectly. + + // CHECK: define void @pair_int128x1_t + #[unsafe(no_mangle)] extern "C" fn pair_int128x1_t(x: Pair>) -> Pair> { x } + + // CHECK: define void @pair_float128x1_t + #[unsafe(no_mangle)] extern "C" fn pair_float128x1_t(x: Pair>) -> Pair> { x } + + // CHECK: define void @pair_int8x16_t + #[unsafe(no_mangle)] extern "C" fn pair_int8x16_t(x: Pair>) -> Pair> { x } + + // CHECK: define void @pair_int16x8_t + #[unsafe(no_mangle)] extern "C" fn pair_int16x8_t(x: Pair>) -> Pair> { x } + + // CHECK: define void @triple_int16x8_t + #[unsafe(no_mangle)] extern "C" fn triple_int16x8_t(x: Triple>) -> Triple> { x } + + // CHECK: define void @quad_int16x8_t + #[unsafe(no_mangle)] extern "C" fn quad_int16x8_t(x: Quad>) -> Quad> { x } +} diff --git a/tests/codegen-llvm/sanitizer/hwasan-vs-khwasan.rs b/tests/codegen-llvm/sanitizer/hwasan-vs-khwasan.rs index 93932d86582f..c34df8c3c5ac 100644 --- a/tests/codegen-llvm/sanitizer/hwasan-vs-khwasan.rs +++ b/tests/codegen-llvm/sanitizer/hwasan-vs-khwasan.rs @@ -18,6 +18,7 @@ // hwasan: @__hwasan_tls // hwasan: call void @llvm.hwasan.check.memaccess.shortgranules // hwasan: declare void @__hwasan_init() +// hwasan: attributes #0 {{.*"target-features"=".*\+tagged-globals.*"}} // The `__hwasan_tls` symbol is unconditionally declared by LLVM's `HWAddressSanitizer` pass. // However, in kernel mode KHWASAN does not actually use it (because shadow mapping is fixed @@ -33,6 +34,7 @@ // // khwasan-NOT: @__hwasan_init // khwasan: call void @llvm.hwasan.check.memaccess.shortgranules +// khwasan-NOT: attributes #0 {{.*"target-features"=".*\+tagged-globals.*"}} #[no_mangle] pub fn test(b: &mut u8) -> u8 { *b diff --git a/tests/crashes/123629.rs b/tests/crashes/123629.rs deleted file mode 100644 index 615323218067..000000000000 --- a/tests/crashes/123629.rs +++ /dev/null @@ -1,10 +0,0 @@ -//@ known-bug: #123629 -#![feature(generic_assert)] - -fn foo() -where - for ():, -{ -} - -fn main() {} diff --git a/tests/crashes/137187.rs b/tests/crashes/137187.rs index 554275441ff0..f63b459de9d0 100644 --- a/tests/crashes/137187.rs +++ b/tests/crashes/137187.rs @@ -1,13 +1,10 @@ //@ known-bug: #137187 -#![feature(const_trait_impl, const_ops)] - use std::ops::Add; + const trait A where - *const Self: const Add, + *const Self: Add, { fn b(c: *const Self) -> <*const Self as Add>::Output { c + c } } - -fn main() {} diff --git a/tests/crashes/139089.rs b/tests/crashes/139089.rs deleted file mode 100644 index 3326aa6ad984..000000000000 --- a/tests/crashes/139089.rs +++ /dev/null @@ -1,2 +0,0 @@ -//@ known-bug: #139089 -pub fn foo3(x: ＆Vec) { x.push(0); } diff --git a/tests/crashes/139570.rs b/tests/crashes/139570.rs deleted file mode 100644 index 9c001aaf848a..000000000000 --- a/tests/crashes/139570.rs +++ /dev/null @@ -1,4 +0,0 @@ -//@ known-bug: #139570 -fn main() { - |(1, 42), ()| yield; -} diff --git a/tests/debuginfo/basic-stepping.rs b/tests/debuginfo/basic-stepping.rs index 238ab12c186e..f81c5cf7d356 100644 --- a/tests/debuginfo/basic-stepping.rs +++ b/tests/debuginfo/basic-stepping.rs @@ -9,9 +9,20 @@ // Debugger tests need debuginfo //@ compile-flags: -g -// FIXME(#128945): SingleUseConsts shouldn't need to be disabled. -//@ revisions: default-mir-passes no-SingleUseConsts-mir-pass -//@ [no-SingleUseConsts-mir-pass] compile-flags: -Zmir-enable-passes=-SingleUseConsts +// Some optimization passes _improve_ compile times [1]. So we want to run some +// passes even with `-Copt-level=0`. That means that some of the lines below can +// be optimized away. To make regression testing more robust, we also want to +// run this test with such passes disabled. The solution is to use two +// revisions. One with default `-Copt-level=0` passes, and one "even less +// optimized", with enough optimization passes disabled to keep the maximum +// number of lines steppable. +// +// If `-Zmir-enable-passes=-...` ends up being annoying to maintain, we can try +// switching to `-Zmir-opt-level=0` instead. +// +// [1]: https://github.com/rust-lang/compiler-team/issues/319 +//@ revisions: opt-level-0 maximally-steppable +//@ [maximally-steppable] compile-flags: -Zmir-enable-passes=-SingleUseConsts // === GDB TESTS =================================================================================== @@ -20,12 +31,12 @@ //@ gdb-command: next //@ gdb-check: let d = c = 99; //@ gdb-command: next -//@ [no-SingleUseConsts-mir-pass] gdb-check: let e = "hi bob"; -//@ [no-SingleUseConsts-mir-pass] gdb-command: next -//@ [no-SingleUseConsts-mir-pass] gdb-check: let f = b"hi bob"; -//@ [no-SingleUseConsts-mir-pass] gdb-command: next -//@ [no-SingleUseConsts-mir-pass] gdb-check: let g = b'9'; -//@ [no-SingleUseConsts-mir-pass] gdb-command: next +//@ [maximally-steppable] gdb-check: let e = "hi bob"; +//@ [maximally-steppable] gdb-command: next +//@ [maximally-steppable] gdb-check: let f = b"hi bob"; +//@ [maximally-steppable] gdb-command: next +//@ [maximally-steppable] gdb-check: let g = b'9'; +//@ [maximally-steppable] gdb-command: next //@ gdb-check: let h = ["whatever"; 8]; //@ gdb-command: next //@ gdb-check: let i = [1,2,3,4]; @@ -61,15 +72,15 @@ //@ lldb-check: [...]let d = c = 99;[...] //@ lldb-command: next //@ lldb-command: frame select -//@ [no-SingleUseConsts-mir-pass] lldb-check: [...]let e = "hi bob";[...] -//@ [no-SingleUseConsts-mir-pass] lldb-command: next -//@ [no-SingleUseConsts-mir-pass] lldb-command: frame select -//@ [no-SingleUseConsts-mir-pass] lldb-check: [...]let f = b"hi bob";[...] -//@ [no-SingleUseConsts-mir-pass] lldb-command: next -//@ [no-SingleUseConsts-mir-pass] lldb-command: frame select -//@ [no-SingleUseConsts-mir-pass] lldb-check: [...]let g = b'9';[...] -//@ [no-SingleUseConsts-mir-pass] lldb-command: next -//@ [no-SingleUseConsts-mir-pass] lldb-command: frame select +//@ [maximally-steppable] lldb-check: [...]let e = "hi bob";[...] +//@ [maximally-steppable] lldb-command: next +//@ [maximally-steppable] lldb-command: frame select +//@ [maximally-steppable] lldb-check: [...]let f = b"hi bob";[...] +//@ [maximally-steppable] lldb-command: next +//@ [maximally-steppable] lldb-command: frame select +//@ [maximally-steppable] lldb-check: [...]let g = b'9';[...] +//@ [maximally-steppable] lldb-command: next +//@ [maximally-steppable] lldb-command: frame select //@ lldb-check: [...]let h = ["whatever"; 8];[...] //@ lldb-command: next //@ lldb-command: frame select @@ -107,12 +118,12 @@ //@ cdb-check: [...]: let mut c = 27; //@ cdb-command: p //@ cdb-check: [...]: let d = c = 99; -//@ [no-SingleUseConsts-mir-pass] cdb-command: p -//@ [no-SingleUseConsts-mir-pass] cdb-check: [...]: let e = "hi bob"; -//@ [no-SingleUseConsts-mir-pass] cdb-command: p -//@ [no-SingleUseConsts-mir-pass] cdb-check: [...]: let f = b"hi bob"; -//@ [no-SingleUseConsts-mir-pass] cdb-command: p -//@ [no-SingleUseConsts-mir-pass] cdb-check: [...]: let g = b'9'; +//@ [maximally-steppable] cdb-command: p +//@ [maximally-steppable] cdb-check: [...]: let e = "hi bob"; +//@ [maximally-steppable] cdb-command: p +//@ [maximally-steppable] cdb-check: [...]: let f = b"hi bob"; +//@ [maximally-steppable] cdb-command: p +//@ [maximally-steppable] cdb-check: [...]: let g = b'9'; //@ cdb-command: p //@ cdb-check: [...]: let h = ["whatever"; 8]; //@ cdb-command: p @@ -131,8 +142,8 @@ fn main () { let a = (); // #break let b : [i32; 0] = []; - // FIXME(#97083): Should we be able to break on initialization of zero-sized types? - // FIXME(#97083): Right now the first breakable line is: + // The above lines initialize zero-sized types. That does not emit machine + // code, so the first breakable line is: let mut c = 27; let d = c = 99; let e = "hi bob"; diff --git a/tests/debuginfo/macro-stepping.rs b/tests/debuginfo/macro-stepping.rs index 3f57eb9ad79b..c2f6183e3c7b 100644 --- a/tests/debuginfo/macro-stepping.rs +++ b/tests/debuginfo/macro-stepping.rs @@ -16,9 +16,9 @@ extern crate macro_stepping; // exports new_scope!() //@ compile-flags: -g -// FIXME(#128945): SingleUseConsts shouldn't need to be disabled. -//@ revisions: default-mir-passes no-SingleUseConsts-mir-pass -//@ [no-SingleUseConsts-mir-pass] compile-flags: -Zmir-enable-passes=-SingleUseConsts +// See explanation in `tests/debuginfo/basic-stepping.rs`. +//@ revisions: opt-level-0 maximally-steppable +//@ [maximally-steppable] compile-flags: -Zmir-enable-passes=-SingleUseConsts // === GDB TESTS =================================================================================== @@ -51,7 +51,7 @@ //@ gdb-check:[...]#inc-loc2[...] //@ gdb-command:next //@ gdb-command:frame -//@ [no-SingleUseConsts-mir-pass] gdb-check:[...]#inc-loc3[...] +//@ [maximally-steppable] gdb-check:[...]#inc-loc3[...] // === LLDB TESTS ================================================================================== diff --git a/tests/debuginfo/msvc-pretty-enums.rs b/tests/debuginfo/msvc-pretty-enums.rs index 1f55adcb5c00..de5dfef004a6 100644 --- a/tests/debuginfo/msvc-pretty-enums.rs +++ b/tests/debuginfo/msvc-pretty-enums.rs @@ -275,7 +275,6 @@ enum NicheLayoutWithFields3 { #[repr(transparent)] struct Wrapping128(u128); -// #[rustc_layout(debug)] enum Wrapping128Niche { X(Wrapping128), Y, diff --git a/tests/incremental/cache-lint-expectation.rs b/tests/incremental/cache-lint-expectation.rs new file mode 100644 index 000000000000..3c82225a95a2 --- /dev/null +++ b/tests/incremental/cache-lint-expectation.rs @@ -0,0 +1,8 @@ +// Regression test for #154878 +//@ revisions: cpass1 cpass2 + +pub fn main() { + let x = 42.0; + #[expect(invalid_nan_comparisons)] + let _b = x == f32::NAN; +} diff --git a/tests/incremental/const-generics/change-const-param-gat.rs b/tests/incremental/const-generics/change-const-param-gat.rs index 0aa628f4bd6b..7e9009e84b83 100644 --- a/tests/incremental/const-generics/change-const-param-gat.rs +++ b/tests/incremental/const-generics/change-const-param-gat.rs @@ -1,7 +1,6 @@ //@ revisions: rpass1 rpass2 rpass3 //@ compile-flags: -Zincremental-ignore-spans //@ ignore-backends: gcc -#![feature(generic_associated_types)] // This test unsures that with_opt_const_param returns the // def_id of the N param in the Foo::Assoc GAT. diff --git a/tests/incremental/delayed_span_bug.rs b/tests/incremental/delayed_span_bug.rs index 7b409db2e18e..ac14fc0f1b6d 100644 --- a/tests/incremental/delayed_span_bug.rs +++ b/tests/incremental/delayed_span_bug.rs @@ -1,5 +1,5 @@ //@ revisions: cfail1 cfail2 -//@ should-ice +//@ failure-status: 101 #![feature(rustc_attrs)] diff --git a/tests/incremental/hashes/delayed_lints.rs b/tests/incremental/hashes/delayed_lints.rs new file mode 100644 index 000000000000..eb65a455160e --- /dev/null +++ b/tests/incremental/hashes/delayed_lints.rs @@ -0,0 +1,27 @@ +// Some lints are emitted in `rustc_attr_parsing`, during ast lowering. +// Emitting these lints is delayed until after ast lowering. +// This test tests that the delayed hints are correctly hashed for incremental. + +//@ check-pass +//@ revisions: cfail1 cfail2 cfail3 +//@ compile-flags: -Z query-dep-graph -O -Zincremental-ignore-spans +//@ ignore-backends: gcc +#![feature(rustc_attrs)] + +// This attribute is here so the `has_delayed_lints` will be true on all revisions +#[doc(test = 1)] +//~^ WARN `#[doc(test(...)]` takes a list of attributes [invalid_doc_attributes] + +// Between revision 1 and 2, the only thing we change is that we add "test = 2" +// This will emit an extra delayed lint, but it will not change the HIR hash. +// We check that even tho the HIR hash didn't change, the extra lint is emitted +#[cfg_attr(cfail1, doc(hidden))] +#[cfg_attr(not(cfail1), doc(hidden, test = 2))] +//[cfail2,cfail3]~^ WARN `#[doc(test(...)]` takes a list of attributes [invalid_doc_attributes] + +// The HIR hash should not change between revisions, for this test to be representative +#[rustc_clean(cfg="cfail2")] +#[rustc_clean(cfg="cfail3")] +trait Test {} + +fn main() {} diff --git a/tests/incremental/krate_reassign_34991/main.rs b/tests/incremental/krate_reassign_34991/main.rs index 2aa77377f5da..1c237df827bd 100644 --- a/tests/incremental/krate_reassign_34991/main.rs +++ b/tests/incremental/krate_reassign_34991/main.rs @@ -8,13 +8,13 @@ extern crate a; #[cfg(rpass1)] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: a::X = 22; x as u32 } #[cfg(rpass2)] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { 22 } diff --git a/tests/incremental/rlib_cross_crate/b.rs b/tests/incremental/rlib_cross_crate/b.rs index c60e1c52f7ed..17f4a0d11500 100644 --- a/tests/incremental/rlib_cross_crate/b.rs +++ b/tests/incremental/rlib_cross_crate/b.rs @@ -15,14 +15,14 @@ #[rustc_clean(except="typeck_root,optimized_mir", cfg="rpass2")] #[rustc_clean(cfg="rpass3")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: a::X = 22; x as u32 } #[rustc_clean(cfg="rpass2")] #[rustc_clean(cfg="rpass3")] -pub fn use_Y() { +pub fn use_y() { let x: a::Y = 'c'; } diff --git a/tests/incremental/split_debuginfo_mode.rs b/tests/incremental/split_debuginfo_mode.rs index d994e24cd587..e3c1f03f5b76 100644 --- a/tests/incremental/split_debuginfo_mode.rs +++ b/tests/incremental/split_debuginfo_mode.rs @@ -5,6 +5,7 @@ // ignore-tidy-linelength //@ only-x86_64-unknown-linux-gnu //@ revisions:rpass1 rpass2 rpass3 rpass4 +//@ ignore-backends: gcc //@ [rpass1]compile-flags: -Zquery-dep-graph -Csplit-debuginfo=unpacked -Zsplit-dwarf-kind=single -Zsplit-dwarf-inlining=on //@ [rpass2]compile-flags: -Zquery-dep-graph -Csplit-debuginfo=packed -Zsplit-dwarf-kind=single -Zsplit-dwarf-inlining=on diff --git a/tests/incremental/static_cycle/b.rs b/tests/incremental/static_cycle/b.rs index c8243cb5328c..98d640ad8f8d 100644 --- a/tests/incremental/static_cycle/b.rs +++ b/tests/incremental/static_cycle/b.rs @@ -3,8 +3,8 @@ #![cfg_attr(rpass2, warn(dead_code))] -pub static mut BAA: *const i8 = unsafe { &BOO as *const _ as *const i8 }; +pub static mut BAA: *const i8 = unsafe { &raw const BOO as *const i8 }; -pub static mut BOO: *const i8 = unsafe { &BAA as *const _ as *const i8 }; +pub static mut BOO: *const i8 = unsafe { &raw const BAA as *const i8 }; fn main() {} diff --git a/tests/incremental/struct_add_field.rs b/tests/incremental/struct_add_field.rs index e39935c0231a..8deee224b77d 100644 --- a/tests/incremental/struct_add_field.rs +++ b/tests/incremental/struct_add_field.rs @@ -23,17 +23,17 @@ pub struct Y { } #[rustc_clean(except="fn_sig,typeck_root", cfg="rpass2")] -pub fn use_X(x: X) -> u32 { +pub fn use_x(x: X) -> u32 { x.x as u32 } #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_EmbedX(embed: EmbedX) -> u32 { +pub fn use_embed_x(embed: EmbedX) -> u32 { embed.x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/struct_change_field_name.rs b/tests/incremental/struct_change_field_name.rs index 76f42b68c5c8..70615a5b2a13 100644 --- a/tests/incremental/struct_change_field_name.rs +++ b/tests/incremental/struct_change_field_name.rs @@ -27,7 +27,7 @@ pub struct Y { } #[rustc_clean(except="typeck_root", cfg="cfail2")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: X = X { x: 22 }; //[cfail2]~^ ERROR struct `X` has no field named `x` x.x as u32 @@ -35,13 +35,13 @@ pub fn use_X() -> u32 { } #[rustc_clean(except="typeck_root", cfg="cfail2")] -pub fn use_EmbedX(embed: EmbedX) -> u32 { +pub fn use_embed_x(embed: EmbedX) -> u32 { embed.x.x as u32 //[cfail2]~^ ERROR no field `x` on type `X` } #[rustc_clean(cfg="cfail2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/struct_change_field_type.rs b/tests/incremental/struct_change_field_type.rs index 9414790303b3..a17550a412a5 100644 --- a/tests/incremental/struct_change_field_type.rs +++ b/tests/incremental/struct_change_field_type.rs @@ -26,19 +26,19 @@ pub struct Y { } #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: X = X { x: 22 }; x.x as u32 } #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_EmbedX(x: EmbedX) -> u32 { +pub fn use_embed_x(x: EmbedX) -> u32 { let x: X = X { x: 22 }; x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/struct_change_field_type_cross_crate/b.rs b/tests/incremental/struct_change_field_type_cross_crate/b.rs index ccd604717389..ecb2fae92639 100644 --- a/tests/incremental/struct_change_field_type_cross_crate/b.rs +++ b/tests/incremental/struct_change_field_type_cross_crate/b.rs @@ -10,18 +10,18 @@ use a::*; #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: X = X { x: 22 }; x.x as u32 } #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_EmbedX(embed: EmbedX) -> u32 { +pub fn use_embed_x(embed: EmbedX) -> u32 { embed.x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/struct_change_nothing.rs b/tests/incremental/struct_change_nothing.rs index fd8c4882e1b2..2c67192a9f53 100644 --- a/tests/incremental/struct_change_nothing.rs +++ b/tests/incremental/struct_change_nothing.rs @@ -26,19 +26,19 @@ pub struct Y { } #[rustc_clean(cfg="rpass2")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: X = X { x: 22 }; x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_EmbedX(x: EmbedX) -> u32 { +pub fn use_embed_x(x: EmbedX) -> u32 { let x: X = X { x: 22 }; x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/struct_remove_field.rs b/tests/incremental/struct_remove_field.rs index eeb0dff8f422..5804d90ed84d 100644 --- a/tests/incremental/struct_remove_field.rs +++ b/tests/incremental/struct_remove_field.rs @@ -27,17 +27,17 @@ pub struct Y { } #[rustc_clean(except="typeck_root,fn_sig", cfg="rpass2")] -pub fn use_X(x: X) -> u32 { +pub fn use_x(x: X) -> u32 { x.x as u32 } #[rustc_clean(except="typeck_root", cfg="rpass2")] -pub fn use_EmbedX(embed: EmbedX) -> u32 { +pub fn use_embed_x(embed: EmbedX) -> u32 { embed.x.x as u32 } #[rustc_clean(cfg="rpass2")] -pub fn use_Y() { +pub fn use_y() { let x: Y = Y { y: 'c' }; } diff --git a/tests/incremental/type_alias_cross_crate/b.rs b/tests/incremental/type_alias_cross_crate/b.rs index 095312c6cfe8..25e988b0a1ea 100644 --- a/tests/incremental/type_alias_cross_crate/b.rs +++ b/tests/incremental/type_alias_cross_crate/b.rs @@ -9,14 +9,14 @@ #[rustc_clean(except="typeck_root", cfg="rpass2")] #[rustc_clean(cfg="rpass3")] -pub fn use_X() -> u32 { +pub fn use_x() -> u32 { let x: a::X = 22; x as u32 } #[rustc_clean(cfg="rpass2")] #[rustc_clean(cfg="rpass3")] -pub fn use_Y() { +pub fn use_y() { let x: a::Y = 'c'; } diff --git a/tests/mir-opt/const_debuginfo.main.SingleUseConsts.diff b/tests/mir-opt/const_debuginfo.main.SingleUseConsts.diff index 9baf8439e59f..03e077b1528c 100644 --- a/tests/mir-opt/const_debuginfo.main.SingleUseConsts.diff +++ b/tests/mir-opt/const_debuginfo.main.SingleUseConsts.diff @@ -55,14 +55,14 @@ } bb0: { - nop; + StorageLive(_1); - _1 = const 1_u8; - nop; ++ nop; + StorageLive(_2); - _2 = const 2_u8; - nop; ++ nop; + StorageLive(_3); - _3 = const 3_u8; -+ nop; -+ nop; + nop; StorageLive(_4); StorageLive(_5); @@ -95,7 +95,7 @@ - _12 = const Point {{ x: 32_u32, y: 32_u32 }}; + nop; StorageLive(_13); - nop; + StorageLive(_14); - _14 = const 32_u32; + nop; StorageLive(_15); @@ -104,7 +104,7 @@ + nop; + nop; StorageDead(_15); - nop; + StorageDead(_14); _0 = const (); StorageDead(_13); StorageDead(_12); @@ -112,9 +112,9 @@ StorageDead(_10); StorageDead(_9); StorageDead(_4); - nop; - nop; - nop; + StorageDead(_3); + StorageDead(_2); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/aggregate.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/aggregate.main.GVN.panic-abort.diff index 0a59c59c2ed2..3371c19360f9 100644 --- a/tests/mir-opt/const_prop/aggregate.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/aggregate.main.GVN.panic-abort.diff @@ -13,8 +13,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); StorageLive(_3); _3 = (const 0_i32, const 1_u8, const 2_i32); @@ -36,8 +35,7 @@ StorageDead(_5); StorageDead(_4); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/aggregate.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/aggregate.main.GVN.panic-unwind.diff index 100369a2eee3..a0f9e7a11799 100644 --- a/tests/mir-opt/const_prop/aggregate.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/aggregate.main.GVN.panic-unwind.diff @@ -13,8 +13,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); StorageLive(_3); _3 = (const 0_i32, const 1_u8, const 2_i32); @@ -36,8 +35,7 @@ StorageDead(_5); StorageDead(_4); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-abort.diff index 8c535b567c32..d6551b8e3e74 100644 --- a/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-abort.diff @@ -18,8 +18,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 0_i32; StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-unwind.diff index 045f4d81db62..3dbd6ca6769c 100644 --- a/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/bad_op_div_by_zero.main.GVN.panic-unwind.diff @@ -18,8 +18,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 0_i32; StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-abort.diff index e5a8726b855c..eac751a231bd 100644 --- a/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-abort.diff @@ -18,8 +18,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 0_i32; StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-unwind.diff index 1110ff186dc6..72b13008f5c5 100644 --- a/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/bad_op_mod_by_zero.main.GVN.panic-unwind.diff @@ -18,8 +18,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 0_i32; StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/boolean_identities.test.GVN.diff b/tests/mir-opt/const_prop/boolean_identities.test.GVN.diff index 3fe70302b21c..2b389e815ce4 100644 --- a/tests/mir-opt/const_prop/boolean_identities.test.GVN.diff +++ b/tests/mir-opt/const_prop/boolean_identities.test.GVN.diff @@ -19,15 +19,13 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _2; - _3 = BitOr(move _4, const true); + _3 = const true; StorageDead(_4); -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _1; - _5 = BitAnd(move _6, const false); @@ -43,10 +41,8 @@ + _0 = const false; StorageDead(_8); StorageDead(_7); -- StorageDead(_5); -- StorageDead(_3); -+ nop; -+ nop; + StorageDead(_5); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-abort.diff index 7ca1b39d7711..405ef7f54d65 100644 --- a/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-abort.diff @@ -22,8 +22,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = foo() -> [return: bb1, unwind unreachable]; } @@ -44,8 +43,7 @@ StorageDead(_5); StorageDead(_4); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-unwind.diff index f63795138066..49782bb44c2a 100644 --- a/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/mutable_variable_unprop_assign.main.GVN.panic-unwind.diff @@ -22,8 +22,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = foo() -> [return: bb1, unwind continue]; } @@ -44,8 +43,7 @@ StorageDead(_5); StorageDead(_4); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-abort.diff index 657fa7a5fea1..c6991c0a3bb4 100644 --- a/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-abort.diff @@ -13,8 +13,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); StorageLive(_3); _3 = const main::FOO; @@ -33,8 +32,7 @@ StorageDead(_5); StorageDead(_4); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-unwind.diff index 8fef6591d41d..04a43e5973a8 100644 --- a/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/pointer_expose_provenance.main.GVN.panic-unwind.diff @@ -13,8 +13,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); StorageLive(_3); _3 = const main::FOO; @@ -33,8 +32,7 @@ StorageDead(_5); StorageDead(_4); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/read_immutable_static.main.GVN.diff b/tests/mir-opt/const_prop/read_immutable_static.main.GVN.diff index 8df262b351f1..1d8c05a4d6a9 100644 --- a/tests/mir-opt/const_prop/read_immutable_static.main.GVN.diff +++ b/tests/mir-opt/const_prop/read_immutable_static.main.GVN.diff @@ -14,10 +14,8 @@ bb0: { StorageLive(_1); -- StorageLive(_2); -- StorageLive(_3); -+ nop; -+ nop; + StorageLive(_2); + StorageLive(_3); _3 = const {ALLOC0: &u8}; - _2 = copy (*_3); + _2 = const 2_u8; @@ -29,11 +27,9 @@ + _4 = const 2_u8; + _1 = const 4_u8; StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); StorageDead(_5); -- StorageDead(_3); -+ nop; + StorageDead(_3); _0 = const (); StorageDead(_1); return; diff --git a/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-abort.diff index 3c73d34474c1..83093cc337cb 100644 --- a/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-abort.diff @@ -11,8 +11,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 1_u32; StorageLive(_2); StorageLive(_3); @@ -26,8 +25,7 @@ StorageDead(_3); StorageDead(_2); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-unwind.diff index 0a7fddee39b6..804763b4f399 100644 --- a/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/scalar_literal_propagation.main.GVN.panic-unwind.diff @@ -11,8 +11,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 1_u32; StorageLive(_2); StorageLive(_3); @@ -26,8 +25,7 @@ StorageDead(_3); StorageDead(_2); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.32bit.diff b/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.32bit.diff index bd24af602c88..6ebce526c983 100644 --- a/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.32bit.diff +++ b/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.32bit.diff @@ -13,8 +13,8 @@ StorageLive(_1); - _1 = const 1_usize as std::boxed::Box (Transmute); - _2 = copy ((_1.0: std::ptr::Unique).0: std::ptr::NonNull) as *const Never (Transmute); -+ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} }}, _marker: PhantomData:: }}, std::alloc::Global); -+ _2 = const std::ptr::NonNull:: {{ pointer: {0x1 as *const Never} }} as *const Never (Transmute); ++ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} is !null }}, _marker: PhantomData:: }}, std::alloc::Global); ++ _2 = const std::ptr::NonNull:: {{ pointer: {0x1 as *const Never} is !null }} as *const Never (Transmute); unreachable; } } diff --git a/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.64bit.diff b/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.64bit.diff index bd24af602c88..6ebce526c983 100644 --- a/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.64bit.diff +++ b/tests/mir-opt/const_prop/transmute.unreachable_box.GVN.64bit.diff @@ -13,8 +13,8 @@ StorageLive(_1); - _1 = const 1_usize as std::boxed::Box (Transmute); - _2 = copy ((_1.0: std::ptr::Unique).0: std::ptr::NonNull) as *const Never (Transmute); -+ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} }}, _marker: PhantomData:: }}, std::alloc::Global); -+ _2 = const std::ptr::NonNull:: {{ pointer: {0x1 as *const Never} }} as *const Never (Transmute); ++ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} is !null }}, _marker: PhantomData:: }}, std::alloc::Global); ++ _2 = const std::ptr::NonNull:: {{ pointer: {0x1 as *const Never} is !null }} as *const Never (Transmute); unreachable; } } diff --git a/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-abort.diff b/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-abort.diff index 01d86ce8717d..402482eb4e00 100644 --- a/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-abort.diff +++ b/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-abort.diff @@ -11,9 +11,8 @@ } bb0: { -- StorageLive(_1); + StorageLive(_1); - _1 = (const 1_u32, const 2_u32); -+ nop; + _1 = const (1_u32, 2_u32); StorageLive(_2); StorageLive(_3); @@ -27,8 +26,7 @@ StorageDead(_3); StorageDead(_2); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-unwind.diff b/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-unwind.diff index bd7d494212ce..2f1c5f1c0b0d 100644 --- a/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/const_prop/tuple_literal_propagation.main.GVN.panic-unwind.diff @@ -11,9 +11,8 @@ } bb0: { -- StorageLive(_1); + StorageLive(_1); - _1 = (const 1_u32, const 2_u32); -+ nop; + _1 = const (1_u32, 2_u32); StorageLive(_2); StorageLive(_3); @@ -27,8 +26,7 @@ StorageDead(_3); StorageDead(_2); _0 = const (); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/const_prop/union.main.GVN.diff b/tests/mir-opt/const_prop/union.main.GVN.diff index 4212a44d0a0d..4c3e0bb68fd4 100644 --- a/tests/mir-opt/const_prop/union.main.GVN.diff +++ b/tests/mir-opt/const_prop/union.main.GVN.diff @@ -17,13 +17,11 @@ bb0: { StorageLive(_1); -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = const 1_u32; - _1 = Un { us: move _2 }; -- StorageDead(_2); + _1 = const Un {{ us: 1_u32 }}; -+ nop; + StorageDead(_2); StorageLive(_3); StorageLive(_4); - _4 = copy (_1.0: u32); diff --git a/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-abort.diff index 8c5e6a9e827a..3d76cd65e038 100644 --- a/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-abort.diff @@ -43,12 +43,12 @@ } bb1: { -- StorageLive(_6); + StorageLive(_6); StorageLive(_7); _7 = copy (*_2); _6 = Not(move _7); StorageDead(_7); -- StorageLive(_8); + StorageLive(_8); StorageLive(_9); _9 = copy (*_2); _8 = Not(move _9); @@ -80,8 +80,8 @@ - StorageDead(_14); _0 = const (); StorageDead(_13); -- StorageDead(_8); -- StorageDead(_6); + StorageDead(_8); + StorageDead(_6); - StorageDead(_4); StorageDead(_2); StorageDead(_1); @@ -93,8 +93,8 @@ - StorageDead(_14); - _5 = const (); StorageDead(_13); -- StorageDead(_8); -- StorageDead(_6); + StorageDead(_8); + StorageDead(_6); goto -> bb1; } } diff --git a/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-unwind.diff index 8c5e6a9e827a..3d76cd65e038 100644 --- a/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/borrowed_local.borrow_in_loop.CopyProp.panic-unwind.diff @@ -43,12 +43,12 @@ } bb1: { -- StorageLive(_6); + StorageLive(_6); StorageLive(_7); _7 = copy (*_2); _6 = Not(move _7); StorageDead(_7); -- StorageLive(_8); + StorageLive(_8); StorageLive(_9); _9 = copy (*_2); _8 = Not(move _9); @@ -80,8 +80,8 @@ - StorageDead(_14); _0 = const (); StorageDead(_13); -- StorageDead(_8); -- StorageDead(_6); + StorageDead(_8); + StorageDead(_6); - StorageDead(_4); StorageDead(_2); StorageDead(_1); @@ -93,8 +93,8 @@ - StorageDead(_14); - _5 = const (); StorageDead(_13); -- StorageDead(_8); -- StorageDead(_6); + StorageDead(_8); + StorageDead(_6); goto -> bb1; } } diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.f.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.f.CopyProp.diff new file mode 100644 index 000000000000..3eebfdd6303a --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.f.CopyProp.diff @@ -0,0 +1,20 @@ +- // MIR for `f` before CopyProp ++ // MIR for `f` after CopyProp + + fn f(_1: &mut usize) -> () { + let mut _0: (); + let mut _2: usize; + let mut _3: usize; + + bb0: { + StorageLive(_2); + _2 = const 0_usize; +- _3 = copy _2; +- (*_1) = copy _3; ++ (*_1) = copy _2; + StorageDead(_2); + (*_1) = copy _2; + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.g.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.g.CopyProp.diff new file mode 100644 index 000000000000..d90cc6e8b41e --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.g.CopyProp.diff @@ -0,0 +1,23 @@ +- // MIR for `g` before CopyProp ++ // MIR for `g` after CopyProp + + fn g() -> usize { + let mut _0: usize; + let mut _1: usize; + let mut _2: usize; + let mut _3: usize; + + bb0: { +- StorageLive(_2); + StorageLive(_1); + _1 = const 0_usize; +- _2 = copy _1; +- _3 = copy _2; +- _0 = Add(copy _3, copy _3); ++ _0 = Add(copy _1, copy _1); + StorageDead(_1); +- StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.rs b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.rs new file mode 100644 index 000000000000..ec506c70327e --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_preserve_head.rs @@ -0,0 +1,57 @@ +//@ test-mir-pass: CopyProp +//@ compile-flags: -Zlint-mir=false + +#![feature(custom_mir, core_intrinsics)] +use std::intrinsics::mir::*; + +// EMIT_MIR copy_prop_storage_preserve_head.f.CopyProp.diff +// EMIT_MIR copy_prop_storage_preserve_head.g.CopyProp.diff + +#[custom_mir(dialect = "runtime", phase = "post-cleanup")] +pub fn f(_1: &mut usize) { + // CHECK-LABEL: fn f( + mir! { + let _2: usize; + let _3: usize; + // CHECK: bb0: { + { + // CHECK: StorageLive(_2); + // CHECK: (*_1) = copy _2; + // CHECK: StorageDead(_2); + StorageLive(_2); + _2 = 0; + _3 = _2; + (*_1) = _3; + StorageDead(_2); + (*_1) = _2; + Return() + } + } +} + +#[custom_mir(dialect = "runtime")] +pub fn g() -> usize { + // CHECK-LABEL: fn g( + mir! { + let _1: usize; + let _2: usize; + let _3: usize; + // CHECK: bb0: { + { + // CHECK: StorageLive(_1); + // CHECK: _0 = Add(copy _1, copy _1); + // CHECK: StorageDead(_1); + StorageLive(_2); + StorageLive(_1); + _1 = 0; + _2 = _1; + _3 = _2; + RET = _3 + _3; + // Even though the storage statements are in reverse order, + // we should be able to keep the ones for _1. + StorageDead(_1); + StorageDead(_2); + Return() + } + } +} diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.f.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.f.CopyProp.diff new file mode 100644 index 000000000000..109fa10cfde9 --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.f.CopyProp.diff @@ -0,0 +1,20 @@ +- // MIR for `f` before CopyProp ++ // MIR for `f` after CopyProp + + fn f(_1: (T, T)) -> T { + let mut _0: T; + let mut _2: T; + let mut _3: T; + let mut _4: &T; + + bb0: { + StorageLive(_2); + _2 = copy (_1.0: T); + _3 = copy _2; + _4 = &_3; + StorageDead(_2); + _0 = copy (*_4); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.rs b/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.rs new file mode 100644 index 000000000000..f7595e60078f --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_removed_when_local_borrowed.rs @@ -0,0 +1,36 @@ +//! Check that we remove the storage statements if one of the locals is borrowed, +//! and the head isn't borrowed. +//@ test-mir-pass: CopyProp + +#![feature(custom_mir, core_intrinsics, freeze)] + +use std::intrinsics::mir::*; +use std::marker::Freeze; + +// EMIT_MIR copy_prop_storage_removed_when_local_borrowed.f.CopyProp.diff + +#[custom_mir(dialect = "runtime")] +pub fn f(_1: (T, T)) -> T { + // CHECK-LABEL: fn f( + mir! { + let _2: T; + let _3: T; + let _4: &T; + // CHECK: bb0: { + { + // FIXME: Currently, copy propagation will not unify borrowed locals. + // If it does, the storage statements for `_2` should be remove + // so these checks will need to be updated. + // CHECK: StorageLive(_2); + // CHECK: _4 = &_3; + // CHECK: StorageDead(_2); + StorageLive(_2); + _2 = _1.0; + _3 = _2; + _4 = &_3; + StorageDead(_2); + RET = *_4; + Return() + } + } +} diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_twice.dead_twice.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_twice.dead_twice.CopyProp.diff new file mode 100644 index 000000000000..bf5766314a5c --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_twice.dead_twice.CopyProp.diff @@ -0,0 +1,28 @@ +- // MIR for `dead_twice` before CopyProp ++ // MIR for `dead_twice` after CopyProp + + fn dead_twice(_1: T) -> T { + let mut _0: T; + let mut _2: T; + let mut _3: T; + let mut _4: T; + + bb0: { +- StorageLive(_2); + _2 = opaque::(move _1) -> [return: bb1, unwind unreachable]; + } + + bb1: { +- _4 = move _2; +- StorageDead(_2); +- StorageLive(_2); +- _0 = opaque::(move _4) -> [return: bb2, unwind unreachable]; ++ _0 = opaque::(copy _2) -> [return: bb2, unwind unreachable]; + } + + bb2: { +- StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_twice.live_twice.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_twice.live_twice.CopyProp.diff new file mode 100644 index 000000000000..01b59b547eaa --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_twice.live_twice.CopyProp.diff @@ -0,0 +1,27 @@ +- // MIR for `live_twice` before CopyProp ++ // MIR for `live_twice` after CopyProp + + fn live_twice(_1: T) -> T { + let mut _0: T; + let mut _2: T; + let mut _3: T; + let mut _4: T; + + bb0: { +- StorageLive(_2); + _2 = opaque::(move _1) -> [return: bb1, unwind unreachable]; + } + + bb1: { +- _4 = move _2; +- StorageLive(_2); +- _0 = opaque::(copy _4) -> [return: bb2, unwind unreachable]; ++ _0 = opaque::(copy _2) -> [return: bb2, unwind unreachable]; + } + + bb2: { +- StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_twice.rs b/tests/mir-opt/copy-prop/copy_prop_storage_twice.rs new file mode 100644 index 000000000000..5d10285ce440 --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_twice.rs @@ -0,0 +1,70 @@ +//@ test-mir-pass: CopyProp +//@ compile-flags: -Zlint-mir=false + +#![feature(custom_mir, core_intrinsics)] + +// Check that we remove the storage statements if the head +// becomes uninitialized before it is used again. + +use std::intrinsics::mir::*; + +// EMIT_MIR copy_prop_storage_twice.dead_twice.CopyProp.diff +#[custom_mir(dialect = "runtime")] +pub fn dead_twice(_1: T) -> T { + // CHECK-LABEL: fn dead_twice( + mir! { + let _2: T; + let _3: T; + { + // CHECK-NOT: StorageLive(_2); + StorageLive(_2); + Call(_2 = opaque(Move(_1)), ReturnTo(bb1), UnwindUnreachable()) + } + bb1 = { + // CHECK-NOT: StorageDead(_2); + // CHECK-NOT: StorageLive(_2); + // CHECK: _0 = opaque::(copy _2) -> [return: bb2, unwind unreachable]; + let _3 = Move(_2); + StorageDead(_2); + StorageLive(_2); + Call(RET = opaque(Move(_3)), ReturnTo(bb2), UnwindUnreachable()) + } + bb2 = { + // CHECK-NOT: StorageDead(_2); + StorageDead(_2); + Return() + } + } +} + +// EMIT_MIR copy_prop_storage_twice.live_twice.CopyProp.diff +#[custom_mir(dialect = "runtime")] +pub fn live_twice(_1: T) -> T { + // CHECK-LABEL: fn live_twice( + mir! { + let _2: T; + let _3: T; + { + // CHECK-NOT: StorageLive(_2); + StorageLive(_2); + Call(_2 = opaque(Move(_1)), ReturnTo(bb1), UnwindUnreachable()) + } + bb1 = { + // CHECK-NOT: StorageLive(_2); + // CHECK: _0 = opaque::(copy _2) -> [return: bb2, unwind unreachable]; + let _3 = Move(_2); + StorageLive(_2); + Call(RET = opaque(_3), ReturnTo(bb2), UnwindUnreachable()) + } + bb2 = { + // CHECK-NOT: StorageDead(_2); + StorageDead(_2); + Return() + } + } +} + +#[inline(never)] +fn opaque(a: T) -> T { + a +} diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.f.CopyProp.diff b/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.f.CopyProp.diff new file mode 100644 index 000000000000..93c186846908 --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.f.CopyProp.diff @@ -0,0 +1,27 @@ +- // MIR for `f` before CopyProp ++ // MIR for `f` after CopyProp + + fn f(_1: &mut usize) -> () { + let mut _0: (); + let mut _2: usize; + let mut _3: usize; + + bb0: { + StorageLive(_2); + _2 = const 42_usize; +- _3 = copy _2; +- (*_1) = copy _3; ++ (*_1) = copy _2; + StorageDead(_2); + return; + } + + bb1: { + StorageLive(_2); +- (*_1) = copy _3; ++ (*_1) = copy _2; + StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.rs b/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.rs new file mode 100644 index 000000000000..2d28913ff847 --- /dev/null +++ b/tests/mir-opt/copy-prop/copy_prop_storage_unreachable.rs @@ -0,0 +1,37 @@ +//! Check that we do not remove the storage statements if the head +//! is uninitialized in an unreachable block. +//@ test-mir-pass: CopyProp + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +// EMIT_MIR copy_prop_storage_unreachable.f.CopyProp.diff + +#[custom_mir(dialect = "runtime", phase = "post-cleanup")] +pub fn f(_1: &mut usize) { + // CHECK-LABEL: fn f( + mir! { + let _2: usize; + let _3: usize; + { + // CHECK: StorageLive(_2); + // CHECK: (*_1) = copy _2; + // CHECK: StorageDead(_2); + StorageLive(_2); + _2 = 42; + _3 = _2; + (*_1) = _3; + StorageDead(_2); + Return() + } + bb1 = { + // Ensure that _2 is considered uninitialized by `MaybeUninitializedLocals`. + StorageLive(_2); + // Use of _3 (in an unreachable block) when definition of _2 is unavailable. + (*_1) = _3; + StorageDead(_2); + Return() + } + } +} diff --git a/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-abort.diff index d133091e6a43..f11685467fd7 100644 --- a/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-abort.diff @@ -26,7 +26,7 @@ } bb1: { -- StorageLive(_2); + StorageLive(_2); _2 = copy _1; - StorageLive(_3); - _3 = copy _2; @@ -46,7 +46,7 @@ StorageDead(_5); _0 = const (); - StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); StorageDead(_1); return; } diff --git a/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-unwind.diff index bd4ad737cec1..bf5d8d20b7a1 100644 --- a/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/cycle.main.CopyProp.panic-unwind.diff @@ -26,7 +26,7 @@ } bb1: { -- StorageLive(_2); + StorageLive(_2); _2 = copy _1; - StorageLive(_3); - _3 = copy _2; @@ -46,7 +46,7 @@ StorageDead(_5); _0 = const (); - StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); StorageDead(_1); return; } diff --git a/tests/mir-opt/copy-prop/cycle.rs b/tests/mir-opt/copy-prop/cycle.rs index 9f8312cc8fcd..9bd175f9c42d 100644 --- a/tests/mir-opt/copy-prop/cycle.rs +++ b/tests/mir-opt/copy-prop/cycle.rs @@ -11,7 +11,7 @@ fn main() { // CHECK: debug x => [[x:_.*]]; // CHECK: debug y => [[y:_.*]]; // CHECK: debug z => [[y]]; - // CHECK-NOT: StorageLive([[y]]); + // CHECK: StorageLive([[y]]); // CHECK: [[y]] = copy [[x]]; // CHECK-NOT: StorageLive(_3); // CHECK-NOT: _3 = copy [[y]]; @@ -19,6 +19,7 @@ fn main() { // CHECK-NOT: _4 = copy _3; // CHECK-NOT: _1 = move _4; // CHECK: [[x]] = copy [[y]]; + // CHECK: StorageDead([[y]]); let mut x = val(); let y = x; let z = y; diff --git a/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-abort.mir b/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-abort.mir index 4781fdfd902a..90bd2b8e07a8 100644 --- a/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-abort.mir +++ b/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-abort.mir @@ -11,6 +11,7 @@ fn f(_1: usize) -> usize { } bb0: { + StorageLive(_2); _2 = copy _1; _1 = const 5_usize; _1 = copy _2; @@ -21,6 +22,7 @@ fn f(_1: usize) -> usize { bb1: { StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-unwind.mir b/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-unwind.mir index f5fded45c13b..72b51f0b60a7 100644 --- a/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-unwind.mir +++ b/tests/mir-opt/copy-prop/dead_stores_79191.f.CopyProp.after.panic-unwind.mir @@ -11,6 +11,7 @@ fn f(_1: usize) -> usize { } bb0: { + StorageLive(_2); _2 = copy _1; _1 = const 5_usize; _1 = copy _2; @@ -21,6 +22,7 @@ fn f(_1: usize) -> usize { bb1: { StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-abort.diff index 689083dfc1d3..fb2aa9c055a6 100644 --- a/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-abort.diff @@ -86,7 +86,7 @@ } bb6: { -- StorageLive(_16); + StorageLive(_16); _16 = copy ((_11 as Some).0: usize); StorageLive(_17); - StorageLive(_18); @@ -116,7 +116,7 @@ StorageDead(_17); - StorageDead(_18); - _10 = const (); -- StorageDead(_16); + StorageDead(_16); StorageDead(_13); StorageDead(_11); - StorageDead(_10); diff --git a/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-unwind.diff index 7f768a9f834d..df3a7793bfdd 100644 --- a/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/issue_107511.main.CopyProp.panic-unwind.diff @@ -86,7 +86,7 @@ } bb6: { -- StorageLive(_16); + StorageLive(_16); _16 = copy ((_11 as Some).0: usize); StorageLive(_17); - StorageLive(_18); @@ -116,7 +116,7 @@ StorageDead(_17); - StorageDead(_18); - _10 = const (); -- StorageDead(_16); + StorageDead(_16); StorageDead(_13); StorageDead(_11); - StorageDead(_10); diff --git a/tests/mir-opt/copy-prop/issue_107511.rs b/tests/mir-opt/copy-prop/issue_107511.rs index d345d2db2b7d..b3dcc775b63d 100644 --- a/tests/mir-opt/copy-prop/issue_107511.rs +++ b/tests/mir-opt/copy-prop/issue_107511.rs @@ -5,8 +5,8 @@ fn main() { // CHECK-LABEL: fn main( // CHECK: debug i => [[i:_.*]]; - // CHECK-NOT: StorageLive([[i]]); - // CHECK-NOT: StorageDead([[i]]); + // CHECK: StorageLive([[i]]); + // CHECK: StorageDead([[i]]); let mut sum = 0; let a = [0, 10, 20, 30]; diff --git a/tests/mir-opt/copy-prop/issue_141649.f_head_borrowed.CopyProp.diff b/tests/mir-opt/copy-prop/issue_141649.f_head_borrowed.CopyProp.diff new file mode 100644 index 000000000000..f8c23f28ff1a --- /dev/null +++ b/tests/mir-opt/copy-prop/issue_141649.f_head_borrowed.CopyProp.diff @@ -0,0 +1,32 @@ +- // MIR for `f_head_borrowed` before CopyProp ++ // MIR for `f_head_borrowed` after CopyProp + + fn f_head_borrowed() -> () { + let mut _0: (); + let mut _1: S; + let mut _2: S; + let mut _3: S; + let mut _4: &S; + let mut _5: &S; + + bb0: { + StorageLive(_1); + _1 = S(const 1_u32, const 2_u32); +- StorageLive(_2); + _4 = &_1; +- _2 = copy _1; +- _3 = opaque::(move _1) -> [return: bb1, unwind unreachable]; ++ _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + } + + bb1: { +- StorageDead(_2); + StorageDead(_1); + _5 = opaque::<&S>(move _4) -> [return: bb2, unwind unreachable]; + } + + bb2: { + return; + } + } + diff --git a/tests/mir-opt/copy-prop/issue_141649.f_move.CopyProp.diff b/tests/mir-opt/copy-prop/issue_141649.f_move.CopyProp.diff new file mode 100644 index 000000000000..89af99210124 --- /dev/null +++ b/tests/mir-opt/copy-prop/issue_141649.f_move.CopyProp.diff @@ -0,0 +1,25 @@ +- // MIR for `f_move` before CopyProp ++ // MIR for `f_move` after CopyProp + + fn f_move() -> () { + let mut _0: (); + let mut _1: S; + let mut _2: S; + let mut _3: S; + + bb0: { + StorageLive(_1); + _1 = S(const 1_u32, const 2_u32); +- StorageLive(_2); +- _2 = copy _1; +- _3 = opaque::(move _1) -> [return: bb1, unwind unreachable]; ++ _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + } + + bb1: { +- StorageDead(_2); + StorageDead(_1); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/issue_141649.rs b/tests/mir-opt/copy-prop/issue_141649.rs new file mode 100644 index 000000000000..25884a9808db --- /dev/null +++ b/tests/mir-opt/copy-prop/issue_141649.rs @@ -0,0 +1,75 @@ +//! Check that we do not remove storage statements when the head is alive for all usages. +//@ test-mir-pass: CopyProp +// EMIT_MIR issue_141649.f_move.CopyProp.diff +// EMIT_MIR issue_141649.f_head_borrowed.CopyProp.diff + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +struct S(u32, u32); + +#[custom_mir(dialect = "runtime")] +pub fn f_move() { + // CHECK-LABEL: fn f_move( + mir! { + let _1: S; + let _2: S; + let _3: S; + { + // CHECK: StorageLive(_1); + // CHECK-NOT: StorageLive(_2); + // CHECK: _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + StorageLive(_1); + _1 = S(1, 2); + StorageLive(_2); + _2 = _1; + Call(_3 = opaque(Move(_1)), ReturnTo(bb1), UnwindUnreachable()) + } + bb1 = { + // CHECK-NOT: StorageDead(_2); + // CHECK: StorageDead(_1); + StorageDead(_2); + StorageDead(_1); + Return() + } + } +} + +#[custom_mir(dialect = "runtime")] +fn f_head_borrowed() { + // CHECK-LABEL: fn f_head_borrowed( + mir! { + let _1: S; + let _2: S; + let _3: S; + let _4: &S; + let _5: &S; + { + // CHECK: StorageLive(_1); + // CHECK-NOT: StorageLive(_2); + // CHECK: _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + StorageLive(_1); + _1 = S(1, 2); + StorageLive(_2); + _4 = &_1; + _2 = _1; + Call(_3 = opaque(Move(_1)), ReturnTo(bb1), UnwindUnreachable()) + } + bb1 = { + // CHECK-NOT: StorageDead(_2); + // CHECK: StorageDead(_1); + StorageDead(_2); + StorageDead(_1); + Call(_5 = opaque(Move(_4)), ReturnTo(bb2), UnwindUnreachable()) + } + bb2 = { + Return() + } + } +} + +#[inline(never)] +fn opaque(a: T) -> T { + a +} diff --git a/tests/mir-opt/copy-prop/issue_141649_debug.f_move.CopyProp.diff b/tests/mir-opt/copy-prop/issue_141649_debug.f_move.CopyProp.diff new file mode 100644 index 000000000000..5cb3753399d5 --- /dev/null +++ b/tests/mir-opt/copy-prop/issue_141649_debug.f_move.CopyProp.diff @@ -0,0 +1,25 @@ +- // MIR for `f_move` before CopyProp ++ // MIR for `f_move` after CopyProp + + fn f_move() -> () { + let mut _0: (); + let mut _1: S; + let mut _2: S; + let mut _3: S; + + bb0: { +- StorageLive(_1); + _1 = S(const 1_u32, const 2_u32); +- StorageLive(_2); +- _2 = copy _1; +- _3 = opaque::(move _1) -> [return: bb1, unwind unreachable]; ++ _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + } + + bb1: { +- StorageDead(_2); +- StorageDead(_1); + return; + } + } + diff --git a/tests/mir-opt/copy-prop/issue_141649_debug.rs b/tests/mir-opt/copy-prop/issue_141649_debug.rs new file mode 100644 index 000000000000..554228000b67 --- /dev/null +++ b/tests/mir-opt/copy-prop/issue_141649_debug.rs @@ -0,0 +1,42 @@ +//! In lower opt levels, we remove (more) storage statements using a simpler strategy. +//@ test-mir-pass: CopyProp +//@ compile-flags: -Copt-level=0 +// EMIT_MIR issue_141649_debug.f_move.CopyProp.diff + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +struct S(u32, u32); + +#[custom_mir(dialect = "runtime")] +pub fn f_move() { + // CHECK-LABEL: fn f_move( + mir! { + let _1: S; + let _2: S; + let _3: S; + { + // CHECK-NOT: StorageLive(_1); + // CHECK-NOT: StorageLive(_2); + // CHECK: _3 = opaque::(copy _1) -> [return: bb1, unwind unreachable]; + StorageLive(_1); + _1 = S(1, 2); + StorageLive(_2); + _2 = _1; + Call(_3 = opaque(Move(_1)), ReturnTo(bb1), UnwindUnreachable()) + } + bb1 = { + // CHECK-NOT: StorageDead(_2); + // CHECK-NOT: StorageDead(_1); + StorageDead(_2); + StorageDead(_1); + Return() + } + } +} + +#[inline(never)] +fn opaque(a: T) -> T { + a +} diff --git a/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-abort.diff index 676c5cee3438..ccd1e1caf003 100644 --- a/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-abort.diff @@ -22,7 +22,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &raw mut _1; StorageLive(_3); StorageLive(_4); @@ -44,7 +44,7 @@ _0 = const (); - StorageDead(_5); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-unwind.diff index ca2232ce54a1..6cfb4af1fcf2 100644 --- a/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/reborrow.demiraw.CopyProp.panic-unwind.diff @@ -22,7 +22,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &raw mut _1; StorageLive(_3); StorageLive(_4); @@ -44,7 +44,7 @@ _0 = const (); - StorageDead(_5); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-abort.diff index 1968696905fc..b5f6a6e22f29 100644 --- a/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-abort.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &raw mut _1; StorageLive(_3); _3 = &raw mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-unwind.diff index 9a3c9665bc8f..c28f7d037fd1 100644 --- a/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/reborrow.miraw.CopyProp.panic-unwind.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &raw mut _1; StorageLive(_3); _3 = &raw mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-abort.diff index 8ef61b5667dd..7ada873b82f8 100644 --- a/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-abort.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &mut _1; StorageLive(_3); _3 = &mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-unwind.diff index 2a7182af984d..23943f474661 100644 --- a/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/reborrow.remut.CopyProp.panic-unwind.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &mut _1; StorageLive(_3); _3 = &mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-abort.diff b/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-abort.diff index 8a2cdd8e5728..4fd9f5af8ee1 100644 --- a/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-abort.diff +++ b/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-abort.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &mut _1; StorageLive(_3); _3 = &raw mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-unwind.diff b/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-unwind.diff index 614d23cf6245..8a428ef12cdd 100644 --- a/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-unwind.diff +++ b/tests/mir-opt/copy-prop/reborrow.reraw.CopyProp.panic-unwind.diff @@ -21,7 +21,7 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); _2 = &mut _1; StorageLive(_3); _3 = &raw mut (*_2); @@ -40,7 +40,7 @@ _0 = const (); - StorageDead(_4); StorageDead(_3); -- StorageDead(_2); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-abort.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-abort.diff index 9ac720a8912c..1194609d31e3 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-abort.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-abort.diff @@ -34,14 +34,14 @@ StorageLive(_3); StorageLive(_4); StorageLive(_5); - _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; - _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; + _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; + _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; + _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); + _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; + _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind unreachable]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-unwind.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-unwind.diff index 4b77c9108eae..2e70718fb2e8 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-unwind.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.32bit.panic-unwind.diff @@ -34,14 +34,14 @@ StorageLive(_3); StorageLive(_4); StorageLive(_5); - _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; - _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; + _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; + _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; + _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); + _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; + _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind: bb2]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-abort.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-abort.diff index 8e9e15eb32d7..eba6e8193ec0 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-abort.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-abort.diff @@ -34,14 +34,14 @@ StorageLive(_3); StorageLive(_4); StorageLive(_5); - _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; - _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; + _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; + _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; + _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); + _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; + _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind unreachable]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-unwind.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-unwind.diff index 915a5bed4cb4..7c9ed108e269 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-unwind.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.DataflowConstProp.64bit.panic-unwind.diff @@ -34,14 +34,14 @@ StorageLive(_3); StorageLive(_4); StorageLive(_5); - _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; - _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; + _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; + _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; + _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); + _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; + _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind: bb2]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-abort.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-abort.diff index 273fe412f80e..b65fe0907b36 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-abort.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-abort.diff @@ -36,17 +36,17 @@ StorageLive(_5); - _5 = const <[bool; 0] as std::mem::SizedTypeProperties>::ALIGNMENT as std::ptr::NonNull<[bool; 0]> (Transmute); - _4 = std::ptr::Unique::<[bool; 0]> { pointer: move _5, _marker: const PhantomData::<[bool; 0]> }; -+ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; -+ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; ++ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; ++ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = move _4 as std::ptr::Unique<[bool]> (PointerCoercion(Unsize, Implicit)); -+ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; ++ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = Box::<[bool]>(copy _3, const std::alloc::Global); -+ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); ++ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = A { foo: move _2 }; -+ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; ++ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind unreachable]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-unwind.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-unwind.diff index 30beb0c9371b..14c5ea59de8f 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-unwind.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.32bit.panic-unwind.diff @@ -36,17 +36,17 @@ StorageLive(_5); - _5 = const <[bool; 0] as std::mem::SizedTypeProperties>::ALIGNMENT as std::ptr::NonNull<[bool; 0]> (Transmute); - _4 = std::ptr::Unique::<[bool; 0]> { pointer: move _5, _marker: const PhantomData::<[bool; 0]> }; -+ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; -+ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; ++ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; ++ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = move _4 as std::ptr::Unique<[bool]> (PointerCoercion(Unsize, Implicit)); -+ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; ++ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = Box::<[bool]>(copy _3, const std::alloc::Global); -+ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); ++ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = A { foo: move _2 }; -+ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; ++ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind: bb2]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-abort.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-abort.diff index b41d129c7359..937d9354e9cf 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-abort.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-abort.diff @@ -36,17 +36,17 @@ StorageLive(_5); - _5 = const <[bool; 0] as std::mem::SizedTypeProperties>::ALIGNMENT as std::ptr::NonNull<[bool; 0]> (Transmute); - _4 = std::ptr::Unique::<[bool; 0]> { pointer: move _5, _marker: const PhantomData::<[bool; 0]> }; -+ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; -+ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; ++ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; ++ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = move _4 as std::ptr::Unique<[bool]> (PointerCoercion(Unsize, Implicit)); -+ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; ++ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = Box::<[bool]>(copy _3, const std::alloc::Global); -+ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); ++ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = A { foo: move _2 }; -+ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; ++ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind unreachable]; diff --git a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-unwind.diff b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-unwind.diff index cd515b5b7cdb..207c583c0a80 100644 --- a/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-unwind.diff +++ b/tests/mir-opt/dataflow-const-prop/default_boxed_slice.main.GVN.64bit.panic-unwind.diff @@ -36,17 +36,17 @@ StorageLive(_5); - _5 = const <[bool; 0] as std::mem::SizedTypeProperties>::ALIGNMENT as std::ptr::NonNull<[bool; 0]> (Transmute); - _4 = std::ptr::Unique::<[bool; 0]> { pointer: move _5, _marker: const PhantomData::<[bool; 0]> }; -+ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}; -+ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} }}, _marker: PhantomData::<[bool; 0]> }}; ++ _5 = const NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}; ++ _4 = const std::ptr::Unique::<[bool; 0]> {{ pointer: NonNull::<[bool; 0]> {{ pointer: {0x1 as *const [bool; 0]} is !null }}, _marker: PhantomData::<[bool; 0]> }}; StorageDead(_5); - _3 = move _4 as std::ptr::Unique<[bool]> (PointerCoercion(Unsize, Implicit)); -+ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}; ++ _3 = const std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}; StorageDead(_4); - _2 = Box::<[bool]>(copy _3, const std::alloc::Global); -+ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); ++ _2 = const Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC1, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global); StorageDead(_3); - _1 = A { foo: move _2 }; -+ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: *const [bool] }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; ++ _1 = const A {{ foo: Box::<[bool]>(std::ptr::Unique::<[bool]> {{ pointer: NonNull::<[bool]> {{ pointer: Indirect { alloc_id: ALLOC2, offset: Size(0 bytes) }: (*const [bool]) is !null }}, _marker: PhantomData::<[bool]> }}, std::alloc::Global) }}; StorageDead(_2); _0 = const (); drop(_1) -> [return: bb1, unwind: bb2]; diff --git a/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.32bit.diff b/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.32bit.diff index 3bc5f8507590..0a21dea1335b 100644 --- a/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.32bit.diff +++ b/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.32bit.diff @@ -12,7 +12,7 @@ bb0: { StorageLive(_1); - _1 = const 1_usize as std::boxed::Box (Transmute); -+ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} }}, _marker: PhantomData:: }}, std::alloc::Global); ++ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} is !null }}, _marker: PhantomData:: }}, std::alloc::Global); _2 = copy ((_1.0: std::ptr::Unique).0: std::ptr::NonNull) as *const Never (Transmute); unreachable; } diff --git a/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.64bit.diff b/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.64bit.diff index 3bc5f8507590..0a21dea1335b 100644 --- a/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.64bit.diff +++ b/tests/mir-opt/dataflow-const-prop/transmute.unreachable_box.DataflowConstProp.64bit.diff @@ -12,7 +12,7 @@ bb0: { StorageLive(_1); - _1 = const 1_usize as std::boxed::Box (Transmute); -+ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} }}, _marker: PhantomData:: }}, std::alloc::Global); ++ _1 = const Box::(std::ptr::Unique:: {{ pointer: NonNull:: {{ pointer: {0x1 as *const Never} is !null }}, _marker: PhantomData:: }}, std::alloc::Global); _2 = copy ((_1.0: std::ptr::Unique).0: std::ptr::NonNull) as *const Never (Transmute); unreachable; } diff --git a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-abort.diff b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-abort.diff index b89141623cf8..ca53e87ec2c1 100644 --- a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-abort.diff +++ b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-abort.diff @@ -71,13 +71,11 @@ _2 = &_3; _1 = &(*_2); StorageDead(_2); -- StorageLive(_5); -+ nop; + StorageLive(_5); _10 = copy (*_1); _11 = copy ((_10.0: std::ptr::Unique<()>).0: std::ptr::NonNull<()>) as *const () (Transmute); _5 = &raw const (*_11); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _5; StorageLive(_14); @@ -98,10 +96,8 @@ StorageDead(_9); _0 = const (); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_5); -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_5); drop(_3) -> [return: bb1, unwind unreachable]; } + } diff --git a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-unwind.diff b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-unwind.diff index 9a354fc005ed..2d7c387d6b73 100644 --- a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-unwind.diff +++ b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.32bit.panic-unwind.diff @@ -51,13 +51,11 @@ _2 = &_3; _1 = &(*_2); StorageDead(_2); -- StorageLive(_5); -+ nop; + StorageLive(_5); _10 = copy (*_1); _11 = copy ((_10.0: std::ptr::Unique<()>).0: std::ptr::NonNull<()>) as *const () (Transmute); _5 = &raw const (*_11); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _5; StorageLive(_12); @@ -78,10 +76,8 @@ StorageDead(_9); _0 = const (); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_5); -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_5); drop(_3) -> [return: bb2, unwind: bb3]; } diff --git a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-abort.diff b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-abort.diff index 0219db325c8f..005f60e8a26f 100644 --- a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-abort.diff +++ b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-abort.diff @@ -71,13 +71,11 @@ _2 = &_3; _1 = &(*_2); StorageDead(_2); -- StorageLive(_5); -+ nop; + StorageLive(_5); _10 = copy (*_1); _11 = copy ((_10.0: std::ptr::Unique<()>).0: std::ptr::NonNull<()>) as *const () (Transmute); _5 = &raw const (*_11); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _5; StorageLive(_14); @@ -98,10 +96,8 @@ StorageDead(_9); _0 = const (); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_5); -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_5); drop(_3) -> [return: bb1, unwind unreachable]; } + } diff --git a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-unwind.diff b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-unwind.diff index 9a354fc005ed..2d7c387d6b73 100644 --- a/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-unwind.diff +++ b/tests/mir-opt/dont_reset_cast_kind_without_updating_operand.test.GVN.64bit.panic-unwind.diff @@ -51,13 +51,11 @@ _2 = &_3; _1 = &(*_2); StorageDead(_2); -- StorageLive(_5); -+ nop; + StorageLive(_5); _10 = copy (*_1); _11 = copy ((_10.0: std::ptr::Unique<()>).0: std::ptr::NonNull<()>) as *const () (Transmute); _5 = &raw const (*_11); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _5; StorageLive(_12); @@ -78,10 +76,8 @@ StorageDead(_9); _0 = const (); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_5); -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_5); drop(_3) -> [return: bb2, unwind: bb3]; } diff --git a/tests/mir-opt/elaborate_box_deref_in_debuginfo.pointee.ElaborateBoxDerefs.diff b/tests/mir-opt/elaborate_box_deref_in_debuginfo.pointee.ElaborateBoxDerefs.diff index 279c1a1990dc..6075d7895eeb 100644 --- a/tests/mir-opt/elaborate_box_deref_in_debuginfo.pointee.ElaborateBoxDerefs.diff +++ b/tests/mir-opt/elaborate_box_deref_in_debuginfo.pointee.ElaborateBoxDerefs.diff @@ -3,7 +3,7 @@ fn pointee(_1: Box) -> () { - debug foo => (*_1); -+ debug foo => (*(((_1.0: std::ptr::Unique).0: std::ptr::NonNull).0: *const i32)); ++ debug foo => (*((((_1.0: std::ptr::Unique).0: std::ptr::NonNull).0: (*const i32) is !null).0: *const i32)); let mut _0: (); bb0: { diff --git a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-abort.diff b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-abort.diff index 6dda5c4e3749..a070bebf5890 100644 --- a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-abort.diff +++ b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-abort.diff @@ -78,8 +78,7 @@ } bb4: { -- StorageLive(_8); -+ nop; + StorageLive(_8); _8 = copy ((_6 as Some).0: usize); StorageLive(_9); _9 = copy _1; @@ -108,8 +107,7 @@ StorageDead(_11); StorageDead(_10); StorageDead(_9); -- StorageDead(_8); -+ nop; + StorageDead(_8); goto -> bb8; } diff --git a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-unwind.diff b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-unwind.diff index 22b62171d4cb..e8b1878d5e81 100644 --- a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-unwind.diff +++ b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.32bit.panic-unwind.diff @@ -78,8 +78,7 @@ } bb4: { -- StorageLive(_8); -+ nop; + StorageLive(_8); _8 = copy ((_6 as Some).0: usize); StorageLive(_9); _9 = copy _1; @@ -108,8 +107,7 @@ StorageDead(_11); StorageDead(_10); StorageDead(_9); -- StorageDead(_8); -+ nop; + StorageDead(_8); goto -> bb8; } diff --git a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-abort.diff b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-abort.diff index cbbf5aa8bc59..e2267c5ed332 100644 --- a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-abort.diff +++ b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-abort.diff @@ -78,8 +78,7 @@ } bb4: { -- StorageLive(_8); -+ nop; + StorageLive(_8); _8 = copy ((_6 as Some).0: usize); StorageLive(_9); _9 = copy _1; @@ -108,8 +107,7 @@ StorageDead(_11); StorageDead(_10); StorageDead(_9); -- StorageDead(_8); -+ nop; + StorageDead(_8); goto -> bb8; } diff --git a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-unwind.diff b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-unwind.diff index e58545fa9fcc..88593a3001a8 100644 --- a/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-unwind.diff +++ b/tests/mir-opt/funky_arms.float_to_exponential_common.GVN.64bit.panic-unwind.diff @@ -78,8 +78,7 @@ } bb4: { -- StorageLive(_8); -+ nop; + StorageLive(_8); _8 = copy ((_6 as Some).0: usize); StorageLive(_9); _9 = copy _1; @@ -108,8 +107,7 @@ StorageDead(_11); StorageDead(_10); StorageDead(_9); -- StorageDead(_8); -+ nop; + StorageDead(_8); goto -> bb8; } diff --git a/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-abort.diff b/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-abort.diff index 5ae575f300af..9f8a839eee9a 100644 --- a/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-abort.diff @@ -91,8 +91,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; - _3 = MyId(move _4); @@ -113,8 +112,7 @@ bb1: { StorageDead(_6); StorageDead(_5); -- StorageLive(_8); -+ nop; + StorageLive(_8); StorageLive(_9); _9 = copy _1; StorageLive(_10); @@ -139,8 +137,7 @@ bb2: { StorageDead(_12); StorageDead(_11); -- StorageLive(_14); -+ nop; + StorageLive(_14); StorageLive(_15); _15 = copy _1; - _14 = Result::::Err(move _15); @@ -161,8 +158,7 @@ bb3: { StorageDead(_17); StorageDead(_16); -- StorageLive(_19); -+ nop; + StorageLive(_19); StorageLive(_20); _20 = copy _1; - _19 = Option::::Some(move _20); @@ -201,8 +197,7 @@ bb5: { StorageDead(_27); StorageDead(_26); -- StorageLive(_29); -+ nop; + StorageLive(_29); StorageLive(_30); _30 = copy _1; StorageLive(_31); @@ -248,8 +243,7 @@ bb7: { StorageDead(_39); StorageDead(_38); -- StorageLive(_41); -+ nop; + StorageLive(_41); StorageLive(_42); _42 = copy _1; - _41 = (move _42,); @@ -269,8 +263,7 @@ bb8: { StorageDead(_44); StorageDead(_43); -- StorageLive(_46); -+ nop; + StorageLive(_46); StorageLive(_47); _47 = copy _1; - _46 = [move _47]; @@ -290,8 +283,7 @@ bb9: { StorageDead(_49); StorageDead(_48); -- StorageLive(_51); -+ nop; + StorageLive(_51); StorageLive(_52); _52 = copy _2; StorageLive(_53); @@ -316,24 +308,16 @@ StorageDead(_55); StorageDead(_54); _0 = const (); -- StorageDead(_51); -- StorageDead(_46); -- StorageDead(_41); -+ nop; -+ nop; -+ nop; + StorageDead(_51); + StorageDead(_46); + StorageDead(_41); StorageDead(_35); -- StorageDead(_29); -+ nop; + StorageDead(_29); StorageDead(_24); -- StorageDead(_19); -- StorageDead(_14); -- StorageDead(_8); -- StorageDead(_3); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_19); + StorageDead(_14); + StorageDead(_8); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-unwind.diff b/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-unwind.diff index 3119a93fb891..f04f778349db 100644 --- a/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.aggregate_struct_then_transmute.GVN.panic-unwind.diff @@ -91,8 +91,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; - _3 = MyId(move _4); @@ -113,8 +112,7 @@ bb1: { StorageDead(_6); StorageDead(_5); -- StorageLive(_8); -+ nop; + StorageLive(_8); StorageLive(_9); _9 = copy _1; StorageLive(_10); @@ -139,8 +137,7 @@ bb2: { StorageDead(_12); StorageDead(_11); -- StorageLive(_14); -+ nop; + StorageLive(_14); StorageLive(_15); _15 = copy _1; - _14 = Result::::Err(move _15); @@ -161,8 +158,7 @@ bb3: { StorageDead(_17); StorageDead(_16); -- StorageLive(_19); -+ nop; + StorageLive(_19); StorageLive(_20); _20 = copy _1; - _19 = Option::::Some(move _20); @@ -201,8 +197,7 @@ bb5: { StorageDead(_27); StorageDead(_26); -- StorageLive(_29); -+ nop; + StorageLive(_29); StorageLive(_30); _30 = copy _1; StorageLive(_31); @@ -248,8 +243,7 @@ bb7: { StorageDead(_39); StorageDead(_38); -- StorageLive(_41); -+ nop; + StorageLive(_41); StorageLive(_42); _42 = copy _1; - _41 = (move _42,); @@ -269,8 +263,7 @@ bb8: { StorageDead(_44); StorageDead(_43); -- StorageLive(_46); -+ nop; + StorageLive(_46); StorageLive(_47); _47 = copy _1; - _46 = [move _47]; @@ -290,8 +283,7 @@ bb9: { StorageDead(_49); StorageDead(_48); -- StorageLive(_51); -+ nop; + StorageLive(_51); StorageLive(_52); _52 = copy _2; StorageLive(_53); @@ -316,24 +308,16 @@ StorageDead(_55); StorageDead(_54); _0 = const (); -- StorageDead(_51); -- StorageDead(_46); -- StorageDead(_41); -+ nop; -+ nop; -+ nop; + StorageDead(_51); + StorageDead(_46); + StorageDead(_41); StorageDead(_35); -- StorageDead(_29); -+ nop; + StorageDead(_29); StorageDead(_24); -- StorageDead(_19); -- StorageDead(_14); -- StorageDead(_8); -- StorageDead(_3); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_19); + StorageDead(_14); + StorageDead(_8); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.arithmetic.GVN.panic-abort.diff b/tests/mir-opt/gvn.arithmetic.GVN.panic-abort.diff index f980645b1d09..363c2f6ad37c 100644 --- a/tests/mir-opt/gvn.arithmetic.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.arithmetic.GVN.panic-abort.diff @@ -108,8 +108,7 @@ StorageDead(_6); StorageDead(_5); StorageLive(_8); -- StorageLive(_9); -+ nop; + StorageLive(_9); StorageLive(_10); _10 = copy _1; StorageLive(_11); @@ -123,8 +122,7 @@ } bb3: { -- StorageDead(_9); -+ nop; + StorageDead(_9); StorageDead(_8); StorageLive(_12); StorageLive(_13); diff --git a/tests/mir-opt/gvn.arithmetic.GVN.panic-unwind.diff b/tests/mir-opt/gvn.arithmetic.GVN.panic-unwind.diff index b8e4967fe8b1..f135532a3f20 100644 --- a/tests/mir-opt/gvn.arithmetic.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.arithmetic.GVN.panic-unwind.diff @@ -108,8 +108,7 @@ StorageDead(_6); StorageDead(_5); StorageLive(_8); -- StorageLive(_9); -+ nop; + StorageLive(_9); StorageLive(_10); _10 = copy _1; StorageLive(_11); @@ -123,8 +122,7 @@ } bb3: { -- StorageDead(_9); -+ nop; + StorageDead(_9); StorageDead(_8); StorageLive(_12); StorageLive(_13); diff --git a/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-abort.diff b/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-abort.diff index acf8bfc71bed..03db197c6a6c 100644 --- a/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-abort.diff @@ -70,8 +70,7 @@ StorageDead(_7); StorageDead(_6); StorageLive(_10); -- StorageLive(_11); -+ nop; + StorageLive(_11); StorageLive(_12); _12 = copy _1; StorageLive(_13); @@ -92,8 +91,7 @@ } bb6: { -- StorageDead(_11); -+ nop; + StorageDead(_11); StorageDead(_10); StorageLive(_15); StorageLive(_16); diff --git a/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-unwind.diff b/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-unwind.diff index f3f6b381a81c..61d4ec54a14d 100644 --- a/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.arithmetic_checked.GVN.panic-unwind.diff @@ -70,8 +70,7 @@ StorageDead(_7); StorageDead(_6); StorageLive(_10); -- StorageLive(_11); -+ nop; + StorageLive(_11); StorageLive(_12); _12 = copy _1; StorageLive(_13); @@ -92,8 +91,7 @@ } bb6: { -- StorageDead(_11); -+ nop; + StorageDead(_11); StorageDead(_10); StorageLive(_15); StorageLive(_16); diff --git a/tests/mir-opt/gvn.cast.GVN.panic-abort.diff b/tests/mir-opt/gvn.cast.GVN.panic-abort.diff index 1d523d22ca64..71566213f412 100644 --- a/tests/mir-opt/gvn.cast.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.cast.GVN.panic-abort.diff @@ -104,14 +104,11 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 1_i64; -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = const 1_u64; -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = const 1f64; StorageLive(_4); StorageLive(_5); @@ -552,12 +549,9 @@ StorageDead(_90); StorageDead(_89); _0 = const (); -- StorageDead(_3); -- StorageDead(_2); -- StorageDead(_1); -+ nop; -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_2); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.cast.GVN.panic-unwind.diff b/tests/mir-opt/gvn.cast.GVN.panic-unwind.diff index 3541c10da643..c0cd4882cd67 100644 --- a/tests/mir-opt/gvn.cast.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.cast.GVN.panic-unwind.diff @@ -104,14 +104,11 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 1_i64; -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = const 1_u64; -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = const 1f64; StorageLive(_4); StorageLive(_5); @@ -552,12 +549,9 @@ StorageDead(_90); StorageDead(_89); _0 = const (); -- StorageDead(_3); -- StorageDead(_2); -- StorageDead(_1); -+ nop; -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_2); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-abort.diff b/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-abort.diff index f66aed0f4415..7dc5180a0a5c 100644 --- a/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-abort.diff @@ -49,8 +49,7 @@ } bb0: { -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _1; - _5 = move _6 as *const u32 (PtrToPtr); @@ -78,10 +77,9 @@ StorageDead(_12); - _10 = move _11 as *const u32 (PtrToPtr); - StorageDead(_11); -- StorageLive(_13); + _10 = copy _11; + nop; -+ nop; + StorageLive(_13); StorageLive(_14); _14 = copy _4; - _13 = move _14 as *const u32 (PtrToPtr); @@ -122,12 +120,10 @@ StorageDead(_21); StorageDead(_18); StorageDead(_15); -- StorageDead(_13); -+ nop; + StorageDead(_13); StorageDead(_10); StorageDead(_7); -- StorageDead(_5); -+ nop; + StorageDead(_5); return; } } diff --git a/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-unwind.diff b/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-unwind.diff index f66aed0f4415..7dc5180a0a5c 100644 --- a/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.cast_pointer_eq.GVN.panic-unwind.diff @@ -49,8 +49,7 @@ } bb0: { -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _1; - _5 = move _6 as *const u32 (PtrToPtr); @@ -78,10 +77,9 @@ StorageDead(_12); - _10 = move _11 as *const u32 (PtrToPtr); - StorageDead(_11); -- StorageLive(_13); + _10 = copy _11; + nop; -+ nop; + StorageLive(_13); StorageLive(_14); _14 = copy _4; - _13 = move _14 as *const u32 (PtrToPtr); @@ -122,12 +120,10 @@ StorageDead(_21); StorageDead(_18); StorageDead(_15); -- StorageDead(_13); -+ nop; + StorageDead(_13); StorageDead(_10); StorageDead(_7); -- StorageDead(_5); -+ nop; + StorageDead(_5); return; } } diff --git a/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-abort.diff b/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-abort.diff index fd09310fabde..bb35b7ef57b2 100644 --- a/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-abort.diff @@ -22,22 +22,19 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = copy _1; - _2 = move _3 as *const [u8; 4] (PtrToPtr); + _2 = copy _1 as *const [u8; 4] (PtrToPtr); StorageDead(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); StorageLive(_5); _5 = copy _2; - _4 = move _5 as *const u8 (PtrToPtr); + _4 = copy _1 as *const u8 (PtrToPtr); StorageDead(_5); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _4; - _6 = move _7 as *const () (PtrToPtr); @@ -48,12 +45,9 @@ - _0 = *const [u8] from (move _8, const 4_usize); + _0 = *const [u8] from (copy _1, const 4_usize); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_4); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-unwind.diff b/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-unwind.diff index fd09310fabde..bb35b7ef57b2 100644 --- a/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.casts_before_aggregate_raw_ptr.GVN.panic-unwind.diff @@ -22,22 +22,19 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = copy _1; - _2 = move _3 as *const [u8; 4] (PtrToPtr); + _2 = copy _1 as *const [u8; 4] (PtrToPtr); StorageDead(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); StorageLive(_5); _5 = copy _2; - _4 = move _5 as *const u8 (PtrToPtr); + _4 = copy _1 as *const u8 (PtrToPtr); StorageDead(_5); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _4; - _6 = move _7 as *const () (PtrToPtr); @@ -48,12 +45,9 @@ - _0 = *const [u8] from (move _8, const 4_usize); + _0 = *const [u8] from (copy _1, const 4_usize); StorageDead(_8); -- StorageDead(_6); -- StorageDead(_4); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_6); + StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-abort.diff b/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-abort.diff index 183b4d2599f5..5ce130fbace8 100644 --- a/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-abort.diff @@ -25,9 +25,8 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); - _2 = const core::num::::MAX as usize (IntToInt); -+ nop; + _2 = const usize::MAX; StorageLive(_3); StorageLive(_4); @@ -96,8 +95,7 @@ bb7: { StorageDead(_14); StorageDead(_3); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-unwind.diff b/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-unwind.diff index 03e8aa3bd9b9..f81b8cbecb66 100644 --- a/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.constant_index_overflow.GVN.panic-unwind.diff @@ -25,9 +25,8 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); - _2 = const core::num::::MAX as usize (IntToInt); -+ nop; + _2 = const usize::MAX; StorageLive(_3); StorageLive(_4); @@ -96,8 +95,7 @@ bb7: { StorageDead(_14); StorageDead(_3); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-abort.diff b/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-abort.diff index 1b2e6c681b92..578b2ea40854 100644 --- a/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-abort.diff @@ -20,16 +20,14 @@ bb0: { StorageLive(_2); _2 = &(*_1); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy (*_2); StorageLive(_4); - _4 = copy (*_2); + _4 = copy _3; _0 = const (); StorageDead(_4); -- StorageDead(_3); -+ nop; + StorageDead(_3); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-unwind.diff b/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-unwind.diff index 1b2e6c681b92..578b2ea40854 100644 --- a/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.dereference_reborrow.GVN.panic-unwind.diff @@ -20,16 +20,14 @@ bb0: { StorageLive(_2); _2 = &(*_1); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy (*_2); StorageLive(_4); - _4 = copy (*_2); + _4 = copy _3; _0 = const (); StorageDead(_4); -- StorageDead(_3); -+ nop; + StorageDead(_3); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn.field_borrow.GVN.panic-abort.diff b/tests/mir-opt/gvn.field_borrow.GVN.panic-abort.diff index 5839ff581129..a0921a42d1b9 100644 --- a/tests/mir-opt/gvn.field_borrow.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.field_borrow.GVN.panic-abort.diff @@ -14,16 +14,14 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: &u8); StorageLive(_3); - _3 = copy ((*_1).0: &u8); + _3 = copy _2; _0 = const (); StorageDead(_3); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.field_borrow.GVN.panic-unwind.diff b/tests/mir-opt/gvn.field_borrow.GVN.panic-unwind.diff index 5839ff581129..a0921a42d1b9 100644 --- a/tests/mir-opt/gvn.field_borrow.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.field_borrow.GVN.panic-unwind.diff @@ -14,16 +14,14 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: &u8); StorageLive(_3); - _3 = copy ((*_1).0: &u8); + _3 = copy _2; _0 = const (); StorageDead(_3); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.field_borrow_2.GVN.panic-abort.diff b/tests/mir-opt/gvn.field_borrow_2.GVN.panic-abort.diff index 819211c41f90..3358e67e9346 100644 --- a/tests/mir-opt/gvn.field_borrow_2.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.field_borrow_2.GVN.panic-abort.diff @@ -32,16 +32,14 @@ _3 = copy ((*_2).0: &u8); StorageLive(_4); _4 = copy (*_1); -- StorageLive(_5); -+ nop; + StorageLive(_5); _5 = copy ((*_4).0: &u8); StorageLive(_6); - _6 = copy ((*_4).0: &u8); + _6 = copy _5; _0 = const (); StorageDead(_6); -- StorageDead(_5); -+ nop; + StorageDead(_5); StorageDead(_4); StorageDead(_3); StorageDead(_2); diff --git a/tests/mir-opt/gvn.field_borrow_2.GVN.panic-unwind.diff b/tests/mir-opt/gvn.field_borrow_2.GVN.panic-unwind.diff index 819211c41f90..3358e67e9346 100644 --- a/tests/mir-opt/gvn.field_borrow_2.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.field_borrow_2.GVN.panic-unwind.diff @@ -32,16 +32,14 @@ _3 = copy ((*_2).0: &u8); StorageLive(_4); _4 = copy (*_1); -- StorageLive(_5); -+ nop; + StorageLive(_5); _5 = copy ((*_4).0: &u8); StorageLive(_6); - _6 = copy ((*_4).0: &u8); + _6 = copy _5; _0 = const (); StorageDead(_6); -- StorageDead(_5); -+ nop; + StorageDead(_5); StorageDead(_4); StorageDead(_3); StorageDead(_2); diff --git a/tests/mir-opt/gvn.fn_pointers.GVN.panic-abort.diff b/tests/mir-opt/gvn.fn_pointers.GVN.panic-abort.diff index 96920af4dddc..fc0cfb284990 100644 --- a/tests/mir-opt/gvn.fn_pointers.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.fn_pointers.GVN.panic-abort.diff @@ -35,8 +35,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = identity:: as fn(u8) -> u8 (PointerCoercion(ReifyFnPointer(Safe), AsCast)); StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ bb1: { StorageDead(_3); StorageDead(_2); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = identity:: as fn(u8) -> u8 (PointerCoercion(ReifyFnPointer(Safe), AsCast)); StorageLive(_5); StorageLive(_6); @@ -61,12 +59,10 @@ bb2: { StorageDead(_6); StorageDead(_5); -- StorageLive(_7); + StorageLive(_7); - _7 = {closure@$DIR/gvn.rs:629:19: 629:21}; -- StorageLive(_8); -+ nop; + _7 = const ZeroSized: {closure@$DIR/gvn.rs:629:19: 629:21}; -+ nop; + StorageLive(_8); StorageLive(_9); - _9 = copy _7; - _8 = move _9 as fn() (PointerCoercion(ClosureFnPointer(Safe), AsCast)); @@ -83,8 +79,7 @@ bb3: { StorageDead(_11); StorageDead(_10); -- StorageLive(_12); -+ nop; + StorageLive(_12); StorageLive(_13); - _13 = copy _7; - _12 = move _13 as fn() (PointerCoercion(ClosureFnPointer(Safe), AsCast)); @@ -102,16 +97,11 @@ StorageDead(_15); StorageDead(_14); _0 = const (); -- StorageDead(_12); -- StorageDead(_8); -- StorageDead(_7); -- StorageDead(_4); -- StorageDead(_1); -+ nop; -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_12); + StorageDead(_8); + StorageDead(_7); + StorageDead(_4); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.fn_pointers.GVN.panic-unwind.diff b/tests/mir-opt/gvn.fn_pointers.GVN.panic-unwind.diff index d32a82322203..6916b6522793 100644 --- a/tests/mir-opt/gvn.fn_pointers.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.fn_pointers.GVN.panic-unwind.diff @@ -35,8 +35,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = identity:: as fn(u8) -> u8 (PointerCoercion(ReifyFnPointer(Safe), AsCast)); StorageLive(_2); StorageLive(_3); @@ -48,8 +47,7 @@ bb1: { StorageDead(_3); StorageDead(_2); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = identity:: as fn(u8) -> u8 (PointerCoercion(ReifyFnPointer(Safe), AsCast)); StorageLive(_5); StorageLive(_6); @@ -61,12 +59,10 @@ bb2: { StorageDead(_6); StorageDead(_5); -- StorageLive(_7); + StorageLive(_7); - _7 = {closure@$DIR/gvn.rs:629:19: 629:21}; -- StorageLive(_8); -+ nop; + _7 = const ZeroSized: {closure@$DIR/gvn.rs:629:19: 629:21}; -+ nop; + StorageLive(_8); StorageLive(_9); - _9 = copy _7; - _8 = move _9 as fn() (PointerCoercion(ClosureFnPointer(Safe), AsCast)); @@ -83,8 +79,7 @@ bb3: { StorageDead(_11); StorageDead(_10); -- StorageLive(_12); -+ nop; + StorageLive(_12); StorageLive(_13); - _13 = copy _7; - _12 = move _13 as fn() (PointerCoercion(ClosureFnPointer(Safe), AsCast)); @@ -102,16 +97,11 @@ StorageDead(_15); StorageDead(_14); _0 = const (); -- StorageDead(_12); -- StorageDead(_8); -- StorageDead(_7); -- StorageDead(_4); -- StorageDead(_1); -+ nop; -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_12); + StorageDead(_8); + StorageDead(_7); + StorageDead(_4); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-abort.diff b/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-abort.diff index 936fa3db82a7..7741d0907d2b 100644 --- a/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-abort.diff @@ -16,11 +16,9 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = &raw mut (*_1); -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _2; - _3 = move _4 as *const [i32] (PtrToPtr); @@ -31,10 +29,8 @@ - _0 = PtrMetadata(move _5); + _0 = PtrMetadata(copy _1); StorageDead(_5); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-unwind.diff b/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-unwind.diff index 936fa3db82a7..7741d0907d2b 100644 --- a/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.manual_slice_mut_len.GVN.panic-unwind.diff @@ -16,11 +16,9 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = &raw mut (*_1); -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _2; - _3 = move _4 as *const [i32] (PtrToPtr); @@ -31,10 +29,8 @@ - _0 = PtrMetadata(move _5); + _0 = PtrMetadata(copy _1); StorageDead(_5); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-abort.diff b/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-abort.diff index 3ed6c2b5308f..1825d68f1939 100644 --- a/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-abort.diff @@ -12,8 +12,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = copy _1; - _2 = *const [i32] from (move _3, const 1_usize); @@ -24,8 +23,7 @@ - _0 = PtrMetadata(move _4); + _0 = const 1_usize; StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-unwind.diff b/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-unwind.diff index 3ed6c2b5308f..1825d68f1939 100644 --- a/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.meta_of_ref_to_slice.GVN.panic-unwind.diff @@ -12,8 +12,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = copy _1; - _2 = *const [i32] from (move _3, const 1_usize); @@ -24,8 +23,7 @@ - _0 = PtrMetadata(move _4); + _0 = const 1_usize; StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.references.GVN.panic-abort.diff b/tests/mir-opt/gvn.references.GVN.panic-abort.diff index 62a487dee821..429c7df2f361 100644 --- a/tests/mir-opt/gvn.references.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.references.GVN.panic-abort.diff @@ -112,8 +112,7 @@ bb8: { StorageDead(_17); StorageDead(_16); -- StorageLive(_18); -+ nop; + StorageLive(_18); _18 = &mut _1; StorageLive(_19); StorageLive(_20); @@ -168,8 +167,7 @@ StorageDead(_28); _0 = const (); StorageDead(_19); -- StorageDead(_18); -+ nop; + StorageDead(_18); drop(_1) -> [return: bb13, unwind unreachable]; } diff --git a/tests/mir-opt/gvn.references.GVN.panic-unwind.diff b/tests/mir-opt/gvn.references.GVN.panic-unwind.diff index 6dd986907fcc..c2d67507c39d 100644 --- a/tests/mir-opt/gvn.references.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.references.GVN.panic-unwind.diff @@ -112,8 +112,7 @@ bb8: { StorageDead(_17); StorageDead(_16); -- StorageLive(_18); -+ nop; + StorageLive(_18); _18 = &mut _1; StorageLive(_19); StorageLive(_20); @@ -168,8 +167,7 @@ StorageDead(_28); _0 = const (); StorageDead(_19); -- StorageDead(_18); -+ nop; + StorageDead(_18); drop(_1) -> [return: bb13, unwind: bb15]; } diff --git a/tests/mir-opt/gvn.repeat.GVN.panic-abort.diff b/tests/mir-opt/gvn.repeat.GVN.panic-abort.diff index ef2eb1a66779..0b8b682ba52c 100644 --- a/tests/mir-opt/gvn.repeat.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.repeat.GVN.panic-abort.diff @@ -23,8 +23,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 5_i32; StorageLive(_2); StorageLive(_3); @@ -71,8 +70,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.repeat.GVN.panic-unwind.diff b/tests/mir-opt/gvn.repeat.GVN.panic-unwind.diff index ef2eb1a66779..0b8b682ba52c 100644 --- a/tests/mir-opt/gvn.repeat.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.repeat.GVN.panic-unwind.diff @@ -23,8 +23,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 5_i32; StorageLive(_2); StorageLive(_3); @@ -71,8 +70,7 @@ StorageDead(_3); _0 = const (); StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.slice_const_length.GVN.panic-abort.diff b/tests/mir-opt/gvn.slice_const_length.GVN.panic-abort.diff index 1a6204e4ac8a..412f908821ab 100644 --- a/tests/mir-opt/gvn.slice_const_length.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.slice_const_length.GVN.panic-abort.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = &(*_1); _2 = core::slice::::as_ptr(move _3) -> [return: bb1, unwind unreachable]; @@ -26,8 +25,7 @@ bb1: { StorageDead(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = const 123_usize; StorageLive(_5); _5 = copy _2; @@ -38,10 +36,8 @@ + _0 = *const [i32] from (copy _2, const 123_usize); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_2); -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.slice_const_length.GVN.panic-unwind.diff b/tests/mir-opt/gvn.slice_const_length.GVN.panic-unwind.diff index 62d57b0fe283..6f166971631c 100644 --- a/tests/mir-opt/gvn.slice_const_length.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.slice_const_length.GVN.panic-unwind.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); StorageLive(_3); _3 = &(*_1); _2 = core::slice::::as_ptr(move _3) -> [return: bb1, unwind continue]; @@ -26,8 +25,7 @@ bb1: { StorageDead(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = const 123_usize; StorageLive(_5); _5 = copy _2; @@ -38,10 +36,8 @@ + _0 = *const [i32] from (copy _2, const 123_usize); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_2); -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-abort.diff b/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-abort.diff index 4a2cc2518919..ab4971cc6c01 100644 --- a/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-abort.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -43,8 +42,7 @@ + _0 = (copy _1, move _8); StorageDead(_8); StorageDead(_6); -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-unwind.diff b/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-unwind.diff index 4a2cc2518919..ab4971cc6c01 100644 --- a/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.slice_from_raw_parts_as_ptr.GVN.panic-unwind.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -43,8 +42,7 @@ + _0 = (copy _1, move _8); StorageDead(_8); StorageDead(_6); -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.slices.GVN.panic-abort.diff b/tests/mir-opt/gvn.slices.GVN.panic-abort.diff index 247ddc73ec36..69c74d11d17e 100644 --- a/tests/mir-opt/gvn.slices.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.slices.GVN.panic-abort.diff @@ -82,8 +82,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const "my favourite slice"; StorageLive(_2); StorageLive(_3); @@ -113,9 +112,8 @@ StorageLive(_7); StorageLive(_8); - StorageLive(_9); -- StorageLive(_10); -+ nop; + nop; + StorageLive(_10); StorageLive(_11); _11 = &(*_1); _10 = core::str::::as_ptr(move _11) -> [return: bb3, unwind unreachable]; @@ -125,9 +123,8 @@ StorageDead(_11); _9 = &_10; - StorageLive(_12); -- StorageLive(_13); -+ nop; + nop; + StorageLive(_13); StorageLive(_14); - _14 = &(*_4); + _14 = &(*_1); @@ -168,14 +165,11 @@ StorageDead(_17); StorageDead(_16); StorageDead(_15); -- StorageDead(_13); -- StorageDead(_10); -+ nop; -+ nop; + StorageDead(_13); + StorageDead(_10); StorageDead(_8); StorageDead(_7); -- StorageLive(_29); -+ nop; + StorageLive(_29); StorageLive(_30); _30 = &(*_1); _29 = move _30 as &[u8] (Transmute); @@ -190,9 +184,8 @@ bb6: { StorageDead(_19); StorageDead(_18); -- StorageLive(_21); + StorageLive(_21); - _21 = core::panicking::AssertKind::Eq; -+ nop; + _21 = const core::panicking::AssertKind::Eq; StorageLive(_22); StorageLive(_23); @@ -221,9 +214,8 @@ StorageLive(_33); StorageLive(_34); - StorageLive(_35); -- StorageLive(_36); -+ nop; + nop; + StorageLive(_36); StorageLive(_37); _37 = &(*_1); _36 = core::str::::as_ptr(move _37) -> [return: bb8, unwind unreachable]; @@ -233,9 +225,8 @@ StorageDead(_37); _35 = &_36; - StorageLive(_38); -- StorageLive(_39); -+ nop; + nop; + StorageLive(_39); StorageLive(_40); _40 = &(*_29); _39 = core::slice::::as_ptr(move _40) -> [return: bb9, unwind unreachable]; @@ -275,27 +266,22 @@ StorageDead(_43); StorageDead(_42); StorageDead(_41); -- StorageDead(_39); -- StorageDead(_36); -+ nop; -+ nop; + StorageDead(_39); + StorageDead(_36); StorageDead(_34); StorageDead(_33); _0 = const (); -- StorageDead(_29); -+ nop; + StorageDead(_29); StorageDead(_4); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } bb11: { StorageDead(_45); StorageDead(_44); -- StorageLive(_47); + StorageLive(_47); - _47 = core::panicking::AssertKind::Eq; -+ nop; + _47 = const core::panicking::AssertKind::Eq; StorageLive(_48); StorageLive(_49); diff --git a/tests/mir-opt/gvn.slices.GVN.panic-unwind.diff b/tests/mir-opt/gvn.slices.GVN.panic-unwind.diff index f15c16f1ce0f..4a27c577303d 100644 --- a/tests/mir-opt/gvn.slices.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.slices.GVN.panic-unwind.diff @@ -82,8 +82,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const "my favourite slice"; StorageLive(_2); StorageLive(_3); @@ -113,9 +112,8 @@ StorageLive(_7); StorageLive(_8); - StorageLive(_9); -- StorageLive(_10); -+ nop; + nop; + StorageLive(_10); StorageLive(_11); _11 = &(*_1); _10 = core::str::::as_ptr(move _11) -> [return: bb3, unwind continue]; @@ -125,9 +123,8 @@ StorageDead(_11); _9 = &_10; - StorageLive(_12); -- StorageLive(_13); -+ nop; + nop; + StorageLive(_13); StorageLive(_14); - _14 = &(*_4); + _14 = &(*_1); @@ -168,14 +165,11 @@ StorageDead(_17); StorageDead(_16); StorageDead(_15); -- StorageDead(_13); -- StorageDead(_10); -+ nop; -+ nop; + StorageDead(_13); + StorageDead(_10); StorageDead(_8); StorageDead(_7); -- StorageLive(_29); -+ nop; + StorageLive(_29); StorageLive(_30); _30 = &(*_1); _29 = move _30 as &[u8] (Transmute); @@ -190,9 +184,8 @@ bb6: { StorageDead(_19); StorageDead(_18); -- StorageLive(_21); + StorageLive(_21); - _21 = core::panicking::AssertKind::Eq; -+ nop; + _21 = const core::panicking::AssertKind::Eq; StorageLive(_22); StorageLive(_23); @@ -221,9 +214,8 @@ StorageLive(_33); StorageLive(_34); - StorageLive(_35); -- StorageLive(_36); -+ nop; + nop; + StorageLive(_36); StorageLive(_37); _37 = &(*_1); _36 = core::str::::as_ptr(move _37) -> [return: bb8, unwind continue]; @@ -233,9 +225,8 @@ StorageDead(_37); _35 = &_36; - StorageLive(_38); -- StorageLive(_39); -+ nop; + nop; + StorageLive(_39); StorageLive(_40); _40 = &(*_29); _39 = core::slice::::as_ptr(move _40) -> [return: bb9, unwind continue]; @@ -275,27 +266,22 @@ StorageDead(_43); StorageDead(_42); StorageDead(_41); -- StorageDead(_39); -- StorageDead(_36); -+ nop; -+ nop; + StorageDead(_39); + StorageDead(_36); StorageDead(_34); StorageDead(_33); _0 = const (); -- StorageDead(_29); -+ nop; + StorageDead(_29); StorageDead(_4); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } bb11: { StorageDead(_45); StorageDead(_44); -- StorageLive(_47); + StorageLive(_47); - _47 = core::panicking::AssertKind::Eq; -+ nop; + _47 = const core::panicking::AssertKind::Eq; StorageLive(_48); StorageLive(_49); diff --git a/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-abort.diff b/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-abort.diff index 0bec425dd995..230a420d0c3d 100644 --- a/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-abort.diff @@ -34,8 +34,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; - _3 = move _4 as *mut u8 (Transmute); @@ -54,8 +53,7 @@ bb1: { StorageDead(_6); StorageDead(_5); -- StorageLive(_8); -+ nop; + StorageLive(_8); StorageLive(_9); StorageLive(_10); StorageLive(_11); @@ -82,8 +80,7 @@ bb2: { StorageDead(_14); StorageDead(_13); -- StorageLive(_16); -+ nop; + StorageLive(_16); StorageLive(_17); _17 = copy _2; - _16 = move _17 as *const [u8] (Transmute); @@ -103,12 +100,9 @@ StorageDead(_19); StorageDead(_18); _0 = const (); -- StorageDead(_16); -- StorageDead(_8); -- StorageDead(_3); -+ nop; -+ nop; -+ nop; + StorageDead(_16); + StorageDead(_8); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-unwind.diff b/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-unwind.diff index 14f2fe08a86a..a20b9cef59ae 100644 --- a/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.transmute_then_cast_pointer.GVN.panic-unwind.diff @@ -34,8 +34,7 @@ } bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; - _3 = move _4 as *mut u8 (Transmute); @@ -54,8 +53,7 @@ bb1: { StorageDead(_6); StorageDead(_5); -- StorageLive(_8); -+ nop; + StorageLive(_8); StorageLive(_9); StorageLive(_10); StorageLive(_11); @@ -82,8 +80,7 @@ bb2: { StorageDead(_14); StorageDead(_13); -- StorageLive(_16); -+ nop; + StorageLive(_16); StorageLive(_17); _17 = copy _2; - _16 = move _17 as *const [u8] (Transmute); @@ -103,12 +100,9 @@ StorageDead(_19); StorageDead(_18); _0 = const (); -- StorageDead(_16); -- StorageDead(_8); -- StorageDead(_3); -+ nop; -+ nop; -+ nop; + StorageDead(_16); + StorageDead(_8); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-abort.diff b/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-abort.diff index caed065536e3..160fb2c8d2bd 100644 --- a/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-abort.diff @@ -41,8 +41,7 @@ } bb0: { -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _1; - _5 = move _6 as char (Transmute); @@ -61,8 +60,7 @@ bb1: { StorageDead(_8); StorageDead(_7); -- StorageLive(_10); -+ nop; + StorageLive(_10); StorageLive(_11); _11 = copy _2; - _10 = move _11 as u32 (Transmute); @@ -81,8 +79,7 @@ bb2: { StorageDead(_13); StorageDead(_12); -- StorageLive(_15); -+ nop; + StorageLive(_15); StorageLive(_16); _16 = copy _3; - _15 = move _16 as ZeroOneTwo (Transmute); @@ -102,8 +99,7 @@ bb3: { StorageDead(_18); StorageDead(_17); -- StorageLive(_20); -+ nop; + StorageLive(_20); StorageLive(_21); _21 = copy _4; - _20 = move _21 as ZeroOneTwo (Transmute); @@ -124,14 +120,10 @@ StorageDead(_23); StorageDead(_22); _0 = const (); -- StorageDead(_20); -- StorageDead(_15); -- StorageDead(_10); -- StorageDead(_5); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_20); + StorageDead(_15); + StorageDead(_10); + StorageDead(_5); return; } } diff --git a/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-unwind.diff b/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-unwind.diff index 3b25dd362cd5..9f7e03e036a8 100644 --- a/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.transmute_then_transmute_again.GVN.panic-unwind.diff @@ -41,8 +41,7 @@ } bb0: { -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _1; - _5 = move _6 as char (Transmute); @@ -61,8 +60,7 @@ bb1: { StorageDead(_8); StorageDead(_7); -- StorageLive(_10); -+ nop; + StorageLive(_10); StorageLive(_11); _11 = copy _2; - _10 = move _11 as u32 (Transmute); @@ -81,8 +79,7 @@ bb2: { StorageDead(_13); StorageDead(_12); -- StorageLive(_15); -+ nop; + StorageLive(_15); StorageLive(_16); _16 = copy _3; - _15 = move _16 as ZeroOneTwo (Transmute); @@ -102,8 +99,7 @@ bb3: { StorageDead(_18); StorageDead(_17); -- StorageLive(_20); -+ nop; + StorageLive(_20); StorageLive(_21); _21 = copy _4; - _20 = move _21 as ZeroOneTwo (Transmute); @@ -124,14 +120,10 @@ StorageDead(_23); StorageDead(_22); _0 = const (); -- StorageDead(_20); -- StorageDead(_15); -- StorageDead(_10); -- StorageDead(_5); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_20); + StorageDead(_15); + StorageDead(_10); + StorageDead(_5); return; } } diff --git a/tests/mir-opt/gvn.unary.GVN.panic-abort.diff b/tests/mir-opt/gvn.unary.GVN.panic-abort.diff index d14aec6df5fa..2b23b0a32d55 100644 --- a/tests/mir-opt/gvn.unary.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.unary.GVN.panic-abort.diff @@ -51,8 +51,7 @@ bb1: { StorageDead(_3); StorageDead(_2); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _1; - _6 = Lt(move _7, const 13_i64); @@ -145,8 +144,7 @@ StorageDead(_23); StorageDead(_22); _0 = const (); -- StorageDead(_6); -+ nop; + StorageDead(_6); return; } } diff --git a/tests/mir-opt/gvn.unary.GVN.panic-unwind.diff b/tests/mir-opt/gvn.unary.GVN.panic-unwind.diff index 5978f1faa1f6..a2ca0dcb18db 100644 --- a/tests/mir-opt/gvn.unary.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.unary.GVN.panic-unwind.diff @@ -51,8 +51,7 @@ bb1: { StorageDead(_3); StorageDead(_2); -- StorageLive(_6); -+ nop; + StorageLive(_6); StorageLive(_7); _7 = copy _1; - _6 = Lt(move _7, const 13_i64); @@ -145,8 +144,7 @@ StorageDead(_23); StorageDead(_22); _0 = const (); -- StorageDead(_6); -+ nop; + StorageDead(_6); return; } } diff --git a/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-abort.diff b/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-abort.diff index bb938f3ba6a9..0d0c17c7c76a 100644 --- a/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-abort.diff @@ -39,16 +39,14 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = (const 1_usize, const 1_usize); - _1 = move _2 as *const [u8] (Transmute); + _2 = const (1_usize, 1_usize); + _1 = const Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [u8]; StorageDead(_2); -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); - _4 = (const 1_usize, const 2_usize); - _3 = move _4 as *const [u8] (Transmute); @@ -170,10 +168,8 @@ StorageDead(_26); StorageDead(_25); _0 = const (); -- StorageDead(_3); -- StorageDead(_1); -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-unwind.diff b/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-unwind.diff index 81432d687eb3..885ca25c3299 100644 --- a/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn.wide_ptr_integer.GVN.panic-unwind.diff @@ -39,16 +39,14 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = (const 1_usize, const 1_usize); - _1 = move _2 as *const [u8] (Transmute); + _2 = const (1_usize, 1_usize); + _1 = const Indirect { alloc_id: ALLOC0, offset: Size(0 bytes) }: *const [u8]; StorageDead(_2); -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); - _4 = (const 1_usize, const 2_usize); - _3 = move _4 as *const [u8] (Transmute); @@ -170,10 +168,8 @@ StorageDead(_26); StorageDead(_25); _0 = const (); -- StorageDead(_3); -- StorageDead(_1); -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn_clone.{impl#0}-clone.GVN.diff b/tests/mir-opt/gvn_clone.{impl#0}-clone.GVN.diff index 0f23415ec53b..9381c7c0af53 100644 --- a/tests/mir-opt/gvn_clone.{impl#0}-clone.GVN.diff +++ b/tests/mir-opt/gvn_clone.{impl#0}-clone.GVN.diff @@ -17,8 +17,7 @@ bb0: { StorageLive(_2); StorageLive(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = &((*_1).0: i32); _3 = copy _4; - _2 = copy (*_3); @@ -30,8 +29,7 @@ StorageDead(_3); StorageLive(_5); StorageLive(_6); -- StorageLive(_7); -+ nop; + StorageLive(_7); _7 = &((*_1).1: u64); _6 = copy _7; - _5 = copy (*_6); @@ -43,8 +41,7 @@ StorageDead(_6); StorageLive(_8); StorageLive(_9); -- StorageLive(_10); -+ nop; + StorageLive(_10); _10 = &((*_1).2: [i8; 3]); _9 = copy _10; - _8 = copy (*_9); @@ -55,15 +52,12 @@ bb3: { StorageDead(_9); - _0 = AllCopy { a: move _2, b: move _5, c: move _8 }; -- StorageDead(_10); + _0 = copy (*_1); -+ nop; + StorageDead(_10); StorageDead(_8); -- StorageDead(_7); -+ nop; + StorageDead(_7); StorageDead(_5); -- StorageDead(_4); -+ nop; + StorageDead(_4); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy.GVN.diff index f6345d5809f2..e88fc3e8553c 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy.GVN.diff @@ -21,14 +21,11 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).2: [i8; 3]); StorageLive(_5); _5 = copy _2; @@ -41,12 +38,9 @@ StorageDead(_7); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_2.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_2.GVN.diff index 2eeeff56cc77..46bf7be82127 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_2.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_2.GVN.diff @@ -24,16 +24,13 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _8 = copy (*_1); _2 = copy ((*_8).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _9 = copy (*_1); _3 = copy ((*_9).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _10 = copy (*_1); _4 = copy ((*_10).2: [i8; 3]); StorageLive(_5); @@ -47,12 +44,9 @@ StorageDead(_7); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_different_type.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_different_type.GVN.diff index 37652095fa44..5f22429b4a2a 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_different_type.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_different_type.GVN.diff @@ -21,14 +21,11 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).2: [i8; 3]); StorageLive(_5); _5 = copy _2; @@ -41,12 +38,9 @@ StorageDead(_7); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_has_changed.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_has_changed.GVN.diff index 8012c26499c9..7a90189c4c49 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_has_changed.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_has_changed.GVN.diff @@ -21,14 +21,11 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).2: [i8; 3]); ((*_1).0: i32) = const 1_i32; StorageLive(_5); @@ -42,12 +39,9 @@ StorageDead(_7); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_move.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_move.GVN.diff index 911b787a64bd..416ee4ce7eea 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_move.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_move.GVN.diff @@ -21,14 +21,11 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy (_1.0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy (_1.1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy (_1.2: [i8; 3]); StorageLive(_5); _5 = copy _2; @@ -41,12 +38,9 @@ StorageDead(_7); StorageDead(_6); StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_mut.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_mut.GVN.diff index 92c9db1b3d79..b0749749688f 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_mut.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_mut.GVN.diff @@ -27,14 +27,11 @@ bb0: { StorageLive(_2); _2 = &(*_1); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_2).0: i32); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_2).1: u64); -- StorageLive(_5); -+ nop; + StorageLive(_5); _5 = copy ((*_2).2: [i8; 3]); ((*_1).0: i32) = const 0_i32; StorageLive(_6); @@ -48,12 +45,9 @@ StorageDead(_8); StorageDead(_7); StorageDead(_6); -- StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -+ nop; -+ nop; -+ nop; + StorageDead(_5); + StorageDead(_4); + StorageDead(_3); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_ret_2.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_ret_2.GVN.diff index 5c6e2a6bc67d..fccbe492b479 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_ret_2.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_ret_2.GVN.diff @@ -26,17 +26,13 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).2: [i8; 3]); -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _2; StorageLive(_7); @@ -63,14 +59,10 @@ - _0 = (move _5, move _9); + _0 = (copy _5, copy _5); StorageDead(_9); -- StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_5); + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed.GVN.diff index dc65cccb7bd6..e3842c9064fe 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed.GVN.diff @@ -29,11 +29,9 @@ _3 = copy ((*_1).0: i32); _2 = move _3; StorageDead(_3); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).1: u64); -- StorageLive(_5); -+ nop; + StorageLive(_5); _5 = copy ((*_1).2: [i8; 3]); StorageLive(_6); _6 = copy _2; @@ -46,10 +44,8 @@ StorageDead(_8); StorageDead(_7); StorageDead(_6); -- StorageDead(_5); -- StorageDead(_4); -+ nop; -+ nop; + StorageDead(_5); + StorageDead(_4); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed_2.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed_2.GVN.diff index 08a4a078adcb..3769c3cfa2ee 100644 --- a/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed_2.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.all_copy_use_changed_2.GVN.diff @@ -24,11 +24,9 @@ bb0: { StorageLive(_2); _2 = copy ((*_1).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy ((*_1).2: [i8; 3]); ((*_1).0: i32) = const 1_i32; StorageLive(_5); @@ -46,10 +44,8 @@ StorageDead(_8); StorageDead(_7); StorageDead(_6); -- StorageDead(_4); -- StorageDead(_3); -+ nop; -+ nop; + StorageDead(_4); + StorageDead(_3); StorageDead(_2); return; } diff --git a/tests/mir-opt/gvn_copy_aggregate.deref_nonssa.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.deref_nonssa.GVN.diff index d9707e40c0bd..c4ae13999227 100644 --- a/tests/mir-opt/gvn_copy_aggregate.deref_nonssa.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.deref_nonssa.GVN.diff @@ -24,8 +24,7 @@ + _1 = const Single(0_u8); StorageLive(_2); _2 = &_1; -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_2).0: u8); StorageLive(_4); - _4 = Single(const 1_u8); @@ -38,8 +37,7 @@ - _0 = Single(move _5); + _0 = Single(copy _3); StorageDead(_5); -- StorageDead(_3); -+ nop; + StorageDead(_3); StorageDead(_2); StorageDead(_1); return; diff --git a/tests/mir-opt/gvn_copy_aggregate.deref_nonssa_2.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.deref_nonssa_2.GVN.diff index 0dea89020e85..c0e8622a5c43 100644 --- a/tests/mir-opt/gvn_copy_aggregate.deref_nonssa_2.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.deref_nonssa_2.GVN.diff @@ -41,10 +41,9 @@ StorageDead(_4); StorageLive(_5); - _5 = copy (_2.0: &Single); -- StorageLive(_6); -- _6 = copy ((*_5).0: u8); + _5 = copy _3; -+ nop; + StorageLive(_6); +- _6 = copy ((*_5).0: u8); + _6 = copy ((*_3).0: u8); StorageLive(_7); - _7 = Single(const 1_u8); @@ -57,8 +56,7 @@ - _0 = Single(move _8); + _0 = Single(copy _6); StorageDead(_8); -- StorageDead(_6); -+ nop; + StorageDead(_6); StorageDead(_5); StorageDead(_2); StorageDead(_1); diff --git a/tests/mir-opt/gvn_copy_aggregate.enum_different_variant.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.enum_different_variant.GVN.diff index 99318d395e21..a7063289e8ae 100644 --- a/tests/mir-opt/gvn_copy_aggregate.enum_different_variant.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.enum_different_variant.GVN.diff @@ -66,20 +66,16 @@ bb2: { StorageLive(_12); _12 = &(((*_1) as B).0: AllCopy); -- StorageLive(_13); + StorageLive(_13); - _13 = copy ((*_12).0: i32); -- StorageLive(_14); -- _14 = copy ((*_12).1: u64); -- StorageLive(_15); -- _15 = copy ((*_12).2: [i8; 3]); -- StorageLive(_16); -+ nop; + _13 = copy ((((*_1) as B).0: AllCopy).0: i32); -+ nop; + StorageLive(_14); +- _14 = copy ((*_12).1: u64); + _14 = copy ((((*_1) as B).0: AllCopy).1: u64); -+ nop; + StorageLive(_15); +- _15 = copy ((*_12).2: [i8; 3]); + _15 = copy ((((*_1) as B).0: AllCopy).2: [i8; 3]); -+ nop; + StorageLive(_16); StorageLive(_17); _17 = copy _13; StorageLive(_18); @@ -97,14 +93,10 @@ + _20 = copy _16; + _0 = Enum1::A(copy _16); StorageDead(_20); -- StorageDead(_16); -- StorageDead(_15); -- StorageDead(_14); -- StorageDead(_13); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_16); + StorageDead(_15); + StorageDead(_14); + StorageDead(_13); StorageDead(_12); goto -> bb4; } @@ -112,20 +104,16 @@ bb3: { StorageLive(_3); _3 = &(((*_1) as A).0: AllCopy); -- StorageLive(_4); + StorageLive(_4); - _4 = copy ((*_3).0: i32); -- StorageLive(_5); -- _5 = copy ((*_3).1: u64); -- StorageLive(_6); -- _6 = copy ((*_3).2: [i8; 3]); -- StorageLive(_7); -+ nop; + _4 = copy ((((*_1) as A).0: AllCopy).0: i32); -+ nop; + StorageLive(_5); +- _5 = copy ((*_3).1: u64); + _5 = copy ((((*_1) as A).0: AllCopy).1: u64); -+ nop; + StorageLive(_6); +- _6 = copy ((*_3).2: [i8; 3]); + _6 = copy ((((*_1) as A).0: AllCopy).2: [i8; 3]); -+ nop; + StorageLive(_7); StorageLive(_8); _8 = copy _4; StorageLive(_9); @@ -143,14 +131,10 @@ + _11 = copy _7; + _0 = Enum1::B(copy _7); StorageDead(_11); -- StorageDead(_7); -- StorageDead(_6); -- StorageDead(_5); -- StorageDead(_4); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_7); + StorageDead(_6); + StorageDead(_5); + StorageDead(_4); StorageDead(_3); goto -> bb4; } diff --git a/tests/mir-opt/gvn_copy_aggregate.enum_identical_variant.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.enum_identical_variant.GVN.diff index b740ba6411bd..22ebaa5ca193 100644 --- a/tests/mir-opt/gvn_copy_aggregate.enum_identical_variant.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.enum_identical_variant.GVN.diff @@ -66,20 +66,16 @@ bb2: { StorageLive(_12); _12 = &(((*_1) as B).0: AllCopy); -- StorageLive(_13); + StorageLive(_13); - _13 = copy ((*_12).0: i32); -- StorageLive(_14); -- _14 = copy ((*_12).1: u64); -- StorageLive(_15); -- _15 = copy ((*_12).2: [i8; 3]); -- StorageLive(_16); -+ nop; + _13 = copy ((((*_1) as B).0: AllCopy).0: i32); -+ nop; + StorageLive(_14); +- _14 = copy ((*_12).1: u64); + _14 = copy ((((*_1) as B).0: AllCopy).1: u64); -+ nop; + StorageLive(_15); +- _15 = copy ((*_12).2: [i8; 3]); + _15 = copy ((((*_1) as B).0: AllCopy).2: [i8; 3]); -+ nop; + StorageLive(_16); StorageLive(_17); _17 = copy _13; StorageLive(_18); @@ -97,14 +93,10 @@ + _20 = copy _16; + _0 = copy (*_1); StorageDead(_20); -- StorageDead(_16); -- StorageDead(_15); -- StorageDead(_14); -- StorageDead(_13); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_16); + StorageDead(_15); + StorageDead(_14); + StorageDead(_13); StorageDead(_12); goto -> bb4; } @@ -112,20 +104,16 @@ bb3: { StorageLive(_3); _3 = &(((*_1) as A).0: AllCopy); -- StorageLive(_4); + StorageLive(_4); - _4 = copy ((*_3).0: i32); -- StorageLive(_5); -- _5 = copy ((*_3).1: u64); -- StorageLive(_6); -- _6 = copy ((*_3).2: [i8; 3]); -- StorageLive(_7); -+ nop; + _4 = copy ((((*_1) as A).0: AllCopy).0: i32); -+ nop; + StorageLive(_5); +- _5 = copy ((*_3).1: u64); + _5 = copy ((((*_1) as A).0: AllCopy).1: u64); -+ nop; + StorageLive(_6); +- _6 = copy ((*_3).2: [i8; 3]); + _6 = copy ((((*_1) as A).0: AllCopy).2: [i8; 3]); -+ nop; + StorageLive(_7); StorageLive(_8); _8 = copy _4; StorageLive(_9); @@ -143,14 +131,10 @@ + _11 = copy _7; + _0 = copy (*_1); StorageDead(_11); -- StorageDead(_7); -- StorageDead(_6); -- StorageDead(_5); -- StorageDead(_4); -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_7); + StorageDead(_6); + StorageDead(_5); + StorageDead(_4); StorageDead(_3); goto -> bb4; } diff --git a/tests/mir-opt/gvn_copy_aggregate.nest_copy.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.nest_copy.GVN.diff index ee5906bab116..f8515be75b8d 100644 --- a/tests/mir-opt/gvn_copy_aggregate.nest_copy.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.nest_copy.GVN.diff @@ -31,17 +31,13 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy (((*_1).1: AllCopy).0: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy (((*_1).1: AllCopy).1: u64); -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = copy (((*_1).1: AllCopy).2: [i8; 3]); -- StorageLive(_5); -+ nop; + StorageLive(_5); StorageLive(_6); _6 = copy _2; StorageLive(_7); @@ -53,8 +49,7 @@ StorageDead(_8); StorageDead(_7); StorageDead(_6); -- StorageLive(_9); -+ nop; + StorageLive(_9); _9 = copy ((*_1).0: i32); StorageLive(_10); _10 = copy _9; @@ -65,16 +60,11 @@ + _0 = copy (*_1); StorageDead(_11); StorageDead(_10); -- StorageDead(_9); -- StorageDead(_5); -- StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; -+ nop; -+ nop; -+ nop; + StorageDead(_9); + StorageDead(_5); + StorageDead(_4); + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_aggregate.same_type_different_index.GVN.diff b/tests/mir-opt/gvn_copy_aggregate.same_type_different_index.GVN.diff index e3126b09a58e..9c214330e352 100644 --- a/tests/mir-opt/gvn_copy_aggregate.same_type_different_index.GVN.diff +++ b/tests/mir-opt/gvn_copy_aggregate.same_type_different_index.GVN.diff @@ -16,11 +16,9 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = copy ((*_1).1: i32); -- StorageLive(_3); -+ nop; + StorageLive(_3); _3 = copy ((*_1).0: i32); StorageLive(_4); _4 = copy _2; @@ -30,10 +28,8 @@ + _0 = SameType { a: copy _2, b: copy _3 }; StorageDead(_5); StorageDead(_4); -- StorageDead(_3); -- StorageDead(_2); -+ nop; -+ nop; + StorageDead(_3); + StorageDead(_2); return; } } diff --git a/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-abort.diff b/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-abort.diff index e2e55304921b..c107eec9ee65 100644 --- a/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-abort.diff +++ b/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-abort.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = const 0_usize; - _5 = Lt(copy _4, const 1_usize); - assert(move _5, "index out of bounds: the length is {} but the index is {}", const 1_usize, copy _4) -> [success: bb1, unwind unreachable]; @@ -50,8 +49,7 @@ StorageDead(_10); StorageDead(_9); StorageDead(_7); -- StorageDead(_4); -+ nop; + StorageDead(_4); return; } } diff --git a/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-unwind.diff b/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-unwind.diff index 60611146a0ee..498df5adc1ef 100644 --- a/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-unwind.diff +++ b/tests/mir-opt/gvn_copy_constant_projection.compare_constant_index.GVN.panic-unwind.diff @@ -17,8 +17,7 @@ } bb0: { -- StorageLive(_4); -+ nop; + StorageLive(_4); _4 = const 0_usize; - _5 = Lt(copy _4, const 1_usize); - assert(move _5, "index out of bounds: the length is {} but the index is {}", const 1_usize, copy _4) -> [success: bb1, unwind continue]; @@ -50,8 +49,7 @@ StorageDead(_10); StorageDead(_9); StorageDead(_7); -- StorageDead(_4); -+ nop; + StorageDead(_4); return; } } diff --git a/tests/mir-opt/gvn_loop.loop_deref_mut.GVN.diff b/tests/mir-opt/gvn_loop.loop_deref_mut.GVN.diff index 589cfd2a3cf1..4e491782c8cd 100644 --- a/tests/mir-opt/gvn_loop.loop_deref_mut.GVN.diff +++ b/tests/mir-opt/gvn_loop.loop_deref_mut.GVN.diff @@ -51,8 +51,7 @@ } bb3: { -- StorageLive(_7); -+ nop; + StorageLive(_7); _7 = copy (((*_3) as V0).0: i32); goto -> bb4; } @@ -73,8 +72,7 @@ _0 = move _11; StorageDead(_14); StorageDead(_11); -- StorageDead(_7); -+ nop; + StorageDead(_7); StorageDead(_5); return; } diff --git a/tests/mir-opt/gvn_on_unsafe_binder.propagate.GVN.diff b/tests/mir-opt/gvn_on_unsafe_binder.propagate.GVN.diff index e28d04f1d588..cef44cb99d66 100644 --- a/tests/mir-opt/gvn_on_unsafe_binder.propagate.GVN.diff +++ b/tests/mir-opt/gvn_on_unsafe_binder.propagate.GVN.diff @@ -14,8 +14,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); _1 = const 1_i32; StorageLive(_2); StorageLive(_3); @@ -27,8 +26,7 @@ - _0 = move _2; + _0 = const {transmute(0x00000001): unsafe<> i32}; StorageDead(_2); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/gvn_storage_issue_141649.f.GVN.diff b/tests/mir-opt/gvn_storage_issue_141649.f.GVN.diff new file mode 100644 index 000000000000..664839e79245 --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649.f.GVN.diff @@ -0,0 +1,20 @@ +- // MIR for `f` before GVN ++ // MIR for `f` after GVN + + fn f(_1: u32) -> () { + let mut _0: (); + let mut _2: S; + let mut _3: S; + + bb0: { + StorageLive(_2); + _2 = S(copy _1, const 2_u32); + StorageLive(_3); +- _3 = S(copy _1, const 2_u32); ++ _3 = copy _2; + StorageDead(_3); + StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_issue_141649.f_borrowed.GVN.diff b/tests/mir-opt/gvn_storage_issue_141649.f_borrowed.GVN.diff new file mode 100644 index 000000000000..4e9d355be608 --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649.f_borrowed.GVN.diff @@ -0,0 +1,25 @@ +- // MIR for `f_borrowed` before GVN ++ // MIR for `f_borrowed` after GVN + + fn f_borrowed(_1: u32) -> () { + let mut _0: (); + let mut _2: S; + let mut _3: S; + let mut _4: &S; + let mut _5: S; + + bb0: { +- StorageLive(_2); ++ nop; + _2 = S(copy _1, const 2_u32); +- _3 = S(copy _1, const 2_u32); ++ _3 = copy _2; + _4 = &_3; +- StorageDead(_2); +- _5 = copy (*_4); ++ nop; ++ _5 = copy _2; + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_issue_141649.f_dead.GVN.diff b/tests/mir-opt/gvn_storage_issue_141649.f_dead.GVN.diff new file mode 100644 index 000000000000..0a20c56d549e --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649.f_dead.GVN.diff @@ -0,0 +1,22 @@ +- // MIR for `f_dead` before GVN ++ // MIR for `f_dead` after GVN + + fn f_dead(_1: u32) -> () { + let mut _0: (); + let mut _2: S; + let mut _3: S; + + bb0: { +- StorageLive(_2); ++ nop; + _2 = S(copy _1, const 2_u32); +- StorageDead(_2); ++ nop; + StorageLive(_3); +- _3 = S(copy _1, const 2_u32); ++ _3 = copy _2; + StorageDead(_3); + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_issue_141649.rs b/tests/mir-opt/gvn_storage_issue_141649.rs new file mode 100644 index 000000000000..f87d9aa42616 --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649.rs @@ -0,0 +1,83 @@ +//! Check that we do not remove storage statements when possible. +//@ test-mir-pass: GVN +// EMIT_MIR gvn_storage_issue_141649.f.GVN.diff +// EMIT_MIR gvn_storage_issue_141649.f_borrowed.GVN.diff +// EMIT_MIR gvn_storage_issue_141649.f_dead.GVN.diff + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +struct S(u32, u32); + +#[custom_mir(dialect = "runtime")] +pub fn f(_1: u32) { + // CHECK-LABEL: fn f( + mir! { + let _2: S; + let _3: S; + { + // CHECK: StorageLive(_2); + // CHECK: StorageLive(_3); + // CHECK: _3 = copy _2; + // CHECK: StorageDead(_3); + // CHECK: StorageDead(_2); + StorageLive(_2); + _2 = S(_1, 2); + StorageLive(_3); + _3 = S(_1, 2); + StorageDead(_3); + StorageDead(_2); + Return() + } + } +} + +#[custom_mir(dialect = "runtime")] +pub fn f_borrowed(_1: u32) { + // CHECK-LABEL: fn f_borrowed( + mir! { + let _2: S; + let _3: S; + let _4: &S; + let _5: S; + { + // CHECK-NOT: StorageLive(_2); + // CHECK: _3 = copy _2; + // CHECK-NOT: StorageDead(_2); + // CHECK: _5 = copy _2; + StorageLive(_2); + _2 = S(_1, 2); + _3 = S(_1, 2); + _4 = &_3; + StorageDead(_2); + // Because `*_4` will be replaced with `_2`, + // we have to remove the storage statements of `_2`. + _5 = *_4; + Return() + } + } +} + +#[custom_mir(dialect = "runtime")] +pub fn f_dead(_1: u32) { + // CHECK-LABEL: fn f_dead( + mir! { + let _2: S; + let _3: S; + { + // CHECK-NOT: StorageLive(_2); + // CHECK: StorageLive(_3); + // CHECK: _3 = copy _2; + // CHECK: StorageDead(_3); + // CHECK-NOT: StorageDead(_2); + StorageLive(_2); + _2 = S(_1, 2); + StorageDead(_2); + StorageLive(_3); + _3 = S(_1, 2); + StorageDead(_3); + Return() + } + } +} diff --git a/tests/mir-opt/gvn_storage_issue_141649_debug.f.GVN.diff b/tests/mir-opt/gvn_storage_issue_141649_debug.f.GVN.diff new file mode 100644 index 000000000000..ee43324b2fe8 --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649_debug.f.GVN.diff @@ -0,0 +1,22 @@ +- // MIR for `f` before GVN ++ // MIR for `f` after GVN + + fn f(_1: u32) -> () { + let mut _0: (); + let mut _2: S; + let mut _3: S; + + bb0: { +- StorageLive(_2); ++ nop; + _2 = S(copy _1, const 2_u32); + StorageLive(_3); +- _3 = S(copy _1, const 2_u32); ++ _3 = copy _2; + StorageDead(_3); +- StorageDead(_2); ++ nop; + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_issue_141649_debug.rs b/tests/mir-opt/gvn_storage_issue_141649_debug.rs new file mode 100644 index 000000000000..2c397f58fe93 --- /dev/null +++ b/tests/mir-opt/gvn_storage_issue_141649_debug.rs @@ -0,0 +1,31 @@ +//! In lower opt levels, we remove any storage statements of reused locals. +//@ test-mir-pass: GVN +//@ compile-flags: -Copt-level=0 +// EMIT_MIR gvn_storage_issue_141649_debug.f.GVN.diff + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +struct S(u32, u32); + +#[custom_mir(dialect = "runtime")] +pub fn f(_1: u32) { + // CHECK-LABEL: fn f( + mir! { + let _2: S; + let _3: S; + { + // CHECK-NOT: StorageLive(_2); + // CHECK: _3 = copy _2; + // CHECK-NOT: StorageDead(_2); + StorageLive(_2); + _2 = S(_1, 2); + StorageLive(_3); + _3 = S(_1, 2); + StorageDead(_3); + StorageDead(_2); + Return() + } + } +} diff --git a/tests/mir-opt/gvn_storage_twice.repeat_local.GVN.diff b/tests/mir-opt/gvn_storage_twice.repeat_local.GVN.diff new file mode 100644 index 000000000000..1c399d42d6fc --- /dev/null +++ b/tests/mir-opt/gvn_storage_twice.repeat_local.GVN.diff @@ -0,0 +1,17 @@ +- // MIR for `repeat_local` before GVN ++ // MIR for `repeat_local` after GVN + + fn repeat_local(_1: usize, _2: usize, _3: i32) -> i32 { + let mut _0: i32; + let mut _4: [i32; 5]; + let mut _5: &i32; + + bb0: { + _4 = [copy _3; 5]; + _5 = &_4[_1]; +- _0 = copy (*_5); ++ _0 = copy _3; + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_twice.repeat_local_dead.GVN.diff b/tests/mir-opt/gvn_storage_twice.repeat_local_dead.GVN.diff new file mode 100644 index 000000000000..ee044aa5a0b1 --- /dev/null +++ b/tests/mir-opt/gvn_storage_twice.repeat_local_dead.GVN.diff @@ -0,0 +1,19 @@ +- // MIR for `repeat_local_dead` before GVN ++ // MIR for `repeat_local_dead` after GVN + + fn repeat_local_dead(_1: usize, _2: usize, _3: i32) -> i32 { + let mut _0: i32; + let mut _4: [i32; 5]; + let mut _5: &i32; + + bb0: { + _4 = [copy _3; 5]; + _5 = &_4[_1]; +- StorageDead(_3); +- _0 = copy (*_5); ++ nop; ++ _0 = copy _3; + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_twice.repeat_local_dead_live.GVN.diff b/tests/mir-opt/gvn_storage_twice.repeat_local_dead_live.GVN.diff new file mode 100644 index 000000000000..9448e91d33a3 --- /dev/null +++ b/tests/mir-opt/gvn_storage_twice.repeat_local_dead_live.GVN.diff @@ -0,0 +1,21 @@ +- // MIR for `repeat_local_dead_live` before GVN ++ // MIR for `repeat_local_dead_live` after GVN + + fn repeat_local_dead_live(_1: usize, _2: usize, _3: i32) -> i32 { + let mut _0: i32; + let mut _4: [i32; 5]; + let mut _5: &i32; + + bb0: { + _4 = [copy _3; 5]; + _5 = &_4[_1]; +- StorageDead(_3); +- StorageLive(_3); +- _0 = copy (*_5); ++ nop; ++ nop; ++ _0 = copy _3; + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_twice.rs b/tests/mir-opt/gvn_storage_twice.rs new file mode 100644 index 000000000000..ca040f7efd5d --- /dev/null +++ b/tests/mir-opt/gvn_storage_twice.rs @@ -0,0 +1,73 @@ +//@ test-mir-pass: GVN +//@ compile-flags: -Zlint-mir=false + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +// EMIT_MIR gvn_storage_twice.repeat_local.GVN.diff +// EMIT_MIR gvn_storage_twice.repeat_local_dead.GVN.diff +// EMIT_MIR gvn_storage_twice.repeat_local_dead_live.GVN.diff + +// Check that we remove the storage statements if the local +// doesn't have valid storage when it is used. +// +// Based on `gvn_repeat.rs::repeat_local`, were GVN should replace +// `let RET = *_5;` with `let RET = _3;`. + +#[custom_mir(dialect = "runtime")] +pub fn repeat_local(_1: usize, _2: usize, _3: i32) -> i32 { + // CHECK-LABEL: fn repeat_local( + mir! { + { + let _4 = [_3; 5]; + let _5 = &_4[_1]; + // CHECK: _0 = copy _3; + RET = *_5; + Return() + } + } +} + +// Since _3 is dead when we access _5, GVN should remove the storage statements. + +#[custom_mir(dialect = "runtime")] +pub fn repeat_local_dead(_1: usize, _2: usize, _3: i32) -> i32 { + // CHECK-LABEL: fn repeat_local_dead( + mir! { + { + let _4 = [_3; 5]; + let _5 = &_4[_1]; + // CHECK-NOT: StorageDead(_3); + StorageDead(_3); + // CHECK: _0 = copy _3; + RET = *_5; + Return() + } + } +} + +// Since _3 is uninit due to storage when we access _5, GVN should remove the storage statements. + +#[custom_mir(dialect = "runtime")] +pub fn repeat_local_dead_live(_1: usize, _2: usize, _3: i32) -> i32 { + // CHECK-LABEL: fn repeat_local_dead_live( + mir! { + { + let _4 = [_3; 5]; + let _5 = &_4[_1]; + // CHECK-NOT: StorageLive(_3); + // CHECK-NOT: StorageDead(_3); + StorageDead(_3); + StorageLive(_3); + // CHECK: _0 = copy _3; + RET = *_5; + Return() + } + } +} + +#[inline(never)] +fn opaque(a: T) -> T { + a +} diff --git a/tests/mir-opt/gvn_storage_unreachable.f.GVN.diff b/tests/mir-opt/gvn_storage_unreachable.f.GVN.diff new file mode 100644 index 000000000000..e29cbe0e2b00 --- /dev/null +++ b/tests/mir-opt/gvn_storage_unreachable.f.GVN.diff @@ -0,0 +1,28 @@ +- // MIR for `f` before GVN ++ // MIR for `f` after GVN + + fn f(_1: u32) -> () { + let mut _0: (); + let mut _2: S; + let mut _3: S; + let mut _4: S; + + bb0: { + StorageLive(_2); + _2 = S(copy _1, const 2_u32); + StorageLive(_3); +- _3 = S(copy _1, const 2_u32); ++ _3 = copy _2; + StorageDead(_3); + StorageDead(_2); + return; + } + + bb1: { + StorageLive(_2); + _4 = copy _2; + StorageDead(_2); + return; + } + } + diff --git a/tests/mir-opt/gvn_storage_unreachable.rs b/tests/mir-opt/gvn_storage_unreachable.rs new file mode 100644 index 000000000000..20e362d1a71d --- /dev/null +++ b/tests/mir-opt/gvn_storage_unreachable.rs @@ -0,0 +1,41 @@ +//! Check that we do not remove the storage statements if a reused local +//! is uninitialized in an unreachable block. +//@ test-mir-pass: GVN +// EMIT_MIR gvn_storage_unreachable.f.GVN.diff + +#![feature(custom_mir, core_intrinsics)] + +use std::intrinsics::mir::*; + +struct S(u32, u32); + +#[custom_mir(dialect = "runtime", phase = "post-cleanup")] +pub fn f(_1: u32) { + // CHECK-LABEL: fn f( + mir! { + let _2: S; + let _3: S; + let _4: S; + { + // CHECK: StorageLive(_2); + // CHECK: StorageLive(_3); + // CHECK: _3 = copy _2; + // CHECK: StorageDead(_3); + // CHECK: StorageDead(_2); + StorageLive(_2); + _2 = S(_1, 2); + StorageLive(_3); + _3 = S(_1, 2); + StorageDead(_3); + StorageDead(_2); + Return() + } + bb1 = { + StorageLive(_2); + // CHECK: _4 = copy _2; + _4 = _2; + StorageDead(_2); + Return() + } + } +} diff --git a/tests/mir-opt/if_condition_int.dont_remove_comparison.SimplifyComparisonIntegral.diff b/tests/mir-opt/if_condition_int.dont_remove_comparison.SimplifyComparisonIntegral.diff index f5f2e0317ead..ada818c6d476 100644 --- a/tests/mir-opt/if_condition_int.dont_remove_comparison.SimplifyComparisonIntegral.diff +++ b/tests/mir-opt/if_condition_int.dont_remove_comparison.SimplifyComparisonIntegral.diff @@ -15,7 +15,7 @@ } bb0: { - nop; + StorageLive(_2); StorageLive(_3); _3 = copy _1; _2 = Eq(copy _1, const 17_i8); @@ -47,7 +47,7 @@ } bb3: { - nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/inline/inline_diverging.h.Inline.panic-abort.diff b/tests/mir-opt/inline/inline_diverging.h.Inline.panic-abort.diff index f099d763c3d8..a116086a0ce1 100644 --- a/tests/mir-opt/inline/inline_diverging.h.Inline.panic-abort.diff +++ b/tests/mir-opt/inline/inline_diverging.h.Inline.panic-abort.diff @@ -35,7 +35,6 @@ + StorageLive(_2); + _2 = sleep; + StorageLive(_4); -+ StorageLive(_6); + StorageLive(_3); + _3 = &_2; + StorageLive(_7); diff --git a/tests/mir-opt/inline/inline_diverging.h.Inline.panic-unwind.diff b/tests/mir-opt/inline/inline_diverging.h.Inline.panic-unwind.diff index c33e0810739f..978de2884c08 100644 --- a/tests/mir-opt/inline/inline_diverging.h.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline/inline_diverging.h.Inline.panic-unwind.diff @@ -35,7 +35,6 @@ - _1 = call_twice:: ! {sleep}>(sleep) -> unwind continue; + StorageLive(_2); + _2 = sleep; -+ StorageLive(_6); + StorageLive(_4); + StorageLive(_3); + _3 = &_2; diff --git a/tests/mir-opt/remove_unneeded_drop_in_place.rs b/tests/mir-opt/inline/inline_empty_drop_glue.rs similarity index 55% rename from tests/mir-opt/remove_unneeded_drop_in_place.rs rename to tests/mir-opt/inline/inline_empty_drop_glue.rs index 470c6499d169..ad7dbb06da1e 100644 --- a/tests/mir-opt/remove_unneeded_drop_in_place.rs +++ b/tests/mir-opt/inline/inline_empty_drop_glue.rs @@ -1,12 +1,12 @@ -//@ test-mir-pass: RemoveUnneededDrops +//@ test-mir-pass: Inline //@ needs-unwind -//@ compile-flags: -Z mir-opt-level=1 +//@ compile-flags: -Zmir-opt-level=1 -// EMIT_MIR remove_unneeded_drop_in_place.slice_in_place.RemoveUnneededDrops.diff +// EMIT_MIR inline_empty_drop_glue.slice_in_place.Inline.diff unsafe fn slice_in_place(ptr: *mut [char]) { // CHECK-LABEL: fn slice_in_place(_1: *mut [char]) - // CHECK: bb0: { - // CHECK-NEXT: return; + // CHECK: bb0: { + // CHECK-NEXT: return; // CHECK-NEXT: } std::ptr::drop_in_place(ptr) } diff --git a/tests/mir-opt/remove_unneeded_drop_in_place.slice_in_place.RemoveUnneededDrops.diff b/tests/mir-opt/inline/inline_empty_drop_glue.slice_in_place.Inline.diff similarity index 69% rename from tests/mir-opt/remove_unneeded_drop_in_place.slice_in_place.RemoveUnneededDrops.diff rename to tests/mir-opt/inline/inline_empty_drop_glue.slice_in_place.Inline.diff index 4d70e7151c39..68136b0ad2a0 100644 --- a/tests/mir-opt/remove_unneeded_drop_in_place.slice_in_place.RemoveUnneededDrops.diff +++ b/tests/mir-opt/inline/inline_empty_drop_glue.slice_in_place.Inline.diff @@ -1,10 +1,12 @@ -- // MIR for `slice_in_place` before RemoveUnneededDrops -+ // MIR for `slice_in_place` after RemoveUnneededDrops +- // MIR for `slice_in_place` before Inline ++ // MIR for `slice_in_place` after Inline fn slice_in_place(_1: *mut [char]) -> () { debug ptr => _1; let mut _0: (); let mut _2: *mut [char]; ++ scope 1 (inlined drop_in_place::<[char]> - shim(None)) { ++ } bb0: { StorageLive(_2); diff --git a/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-abort.diff b/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-abort.diff index 440675826dd5..b5d0dc186293 100644 --- a/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-abort.diff +++ b/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-abort.diff @@ -197,8 +197,8 @@ + StorageLive(_40); + _40 = &raw mut _19; + _39 = copy _40 as *mut std::pin::helper::PinHelper<&mut std::future::Ready<()>> (PtrToPtr); -+ _37 = copy ((*_39).0: &mut std::future::Ready<()>); + StorageDead(_40); ++ _37 = copy ((*_39).0: &mut std::future::Ready<()>); + StorageLive(_42); + _42 = Option::<()>::None; + _35 = copy ((*_37).0: std::option::Option<()>); diff --git a/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-unwind.diff b/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-unwind.diff index f4efcc6c8c62..ffcb0014cec6 100644 --- a/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-unwind.diff +++ b/tests/mir-opt/inline_coroutine_body.run2-{closure#0}.Inline.panic-unwind.diff @@ -208,8 +208,8 @@ + StorageLive(_40); + _40 = &raw mut _19; + _39 = copy _40 as *mut std::pin::helper::PinHelper<&mut std::future::Ready<()>> (PtrToPtr); -+ _37 = copy ((*_39).0: &mut std::future::Ready<()>); + StorageDead(_40); ++ _37 = copy ((*_39).0: &mut std::future::Ready<()>); + StorageLive(_42); + _42 = Option::<()>::None; + _35 = copy ((*_37).0: std::option::Option<()>); diff --git a/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-abort.diff b/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-abort.diff index 614d9ad440d2..95f9b5997d4f 100644 --- a/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-abort.diff +++ b/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-abort.diff @@ -21,10 +21,12 @@ } bb0: { + StorageLive(_3); StorageLive(_4); _4 = [copy _1, copy _1, copy _1]; _3 = &_4; _2 = copy _3 as &[T] (PointerCoercion(Unsize, Implicit)); + StorageDead(_3); goto -> bb2; } diff --git a/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-unwind.diff b/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-unwind.diff index 57a88cf89841..87449b043fd5 100644 --- a/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-unwind.diff +++ b/tests/mir-opt/issue_76432.test.SimplifyComparisonIntegral.panic-unwind.diff @@ -21,10 +21,12 @@ } bb0: { + StorageLive(_3); StorageLive(_4); _4 = [copy _1, copy _1, copy _1]; _3 = &_4; _2 = copy _3 as &[T] (PointerCoercion(Unsize, Implicit)); + StorageDead(_3); goto -> bb2; } diff --git a/tests/mir-opt/issues/issue_75439.foo.MatchBranchSimplification.diff b/tests/mir-opt/issues/issue_75439.foo.MatchBranchSimplification.diff index d8eace98d556..febcb0944c71 100644 --- a/tests/mir-opt/issues/issue_75439.foo.MatchBranchSimplification.diff +++ b/tests/mir-opt/issues/issue_75439.foo.MatchBranchSimplification.diff @@ -29,11 +29,13 @@ } bb3: { + StorageLive(_3); _3 = copy _2[3 of 4]; StorageLive(_4); _4 = copy _3 as [u8; 4] (Transmute); _0 = Option::<[u8; 4]>::Some(move _4); StorageDead(_4); + StorageDead(_3); goto -> bb5; } diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff index a0aeb0a30f41..a59d76b05a99 100644 --- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff +++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff @@ -252,11 +252,9 @@ StorageDead(_30); StorageLive(_36); StorageLive(_38); - StorageLive(_39); - StorageLive(_42); - StorageLive(_43); _36 = copy _29 as &[u8] (Transmute); _38 = copy _28 as &[u8] (Transmute); + StorageLive(_39); _39 = PtrMetadata(copy _36); StorageLive(_40); StorageLive(_41); @@ -316,11 +314,9 @@ StorageDead(_50); StorageLive(_56); StorageLive(_58); - StorageLive(_59); - StorageLive(_62); - StorageLive(_63); _56 = copy _49 as &[u8] (Transmute); _58 = copy _48 as &[u8] (Transmute); + StorageLive(_59); _59 = PtrMetadata(copy _56); StorageLive(_60); StorageLive(_61); @@ -409,10 +405,12 @@ bb19: { StorageDead(_41); + StorageLive(_42); StorageLive(_44); _44 = &raw const (*_36); _42 = copy _44 as *const u8 (PtrToPtr); StorageDead(_44); + StorageLive(_43); StorageLive(_45); _45 = &raw const (*_38); _43 = copy _45 as *const u8 (PtrToPtr); @@ -430,8 +428,6 @@ bb21: { StorageDead(_40); - StorageDead(_43); - StorageDead(_42); StorageDead(_39); StorageDead(_38); StorageDead(_36); @@ -444,15 +440,19 @@ bb22: { _7 = Eq(move _46, const 0_i32); StorageDead(_46); + StorageDead(_43); + StorageDead(_42); goto -> bb21; } bb23: { StorageDead(_61); + StorageLive(_62); StorageLive(_64); _64 = &raw const (*_56); _62 = copy _64 as *const u8 (PtrToPtr); StorageDead(_64); + StorageLive(_63); StorageLive(_65); _65 = &raw const (*_58); _63 = copy _65 as *const u8 (PtrToPtr); @@ -470,8 +470,6 @@ bb25: { StorageDead(_60); - StorageDead(_63); - StorageDead(_62); StorageDead(_59); StorageDead(_58); StorageDead(_56); @@ -484,6 +482,8 @@ bb26: { _14 = Eq(move _66, const 0_i32); StorageDead(_66); + StorageDead(_63); + StorageDead(_62); goto -> bb25; + } + @@ -507,8 +507,6 @@ + + bb31: { + StorageDead(_60); -+ StorageDead(_63); -+ StorageDead(_62); + StorageDead(_59); + StorageDead(_58); + StorageDead(_56); @@ -520,8 +518,6 @@ + + bb32: { + StorageDead(_40); -+ StorageDead(_43); -+ StorageDead(_42); + StorageDead(_39); + StorageDead(_38); + StorageDead(_36); diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff index 71d91fed6307..b0811ab7f068 100644 --- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff +++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff @@ -252,11 +252,9 @@ StorageDead(_30); StorageLive(_36); StorageLive(_38); - StorageLive(_39); - StorageLive(_42); - StorageLive(_43); _36 = copy _29 as &[u8] (Transmute); _38 = copy _28 as &[u8] (Transmute); + StorageLive(_39); _39 = PtrMetadata(copy _36); StorageLive(_40); StorageLive(_41); @@ -316,11 +314,9 @@ StorageDead(_50); StorageLive(_56); StorageLive(_58); - StorageLive(_59); - StorageLive(_62); - StorageLive(_63); _56 = copy _49 as &[u8] (Transmute); _58 = copy _48 as &[u8] (Transmute); + StorageLive(_59); _59 = PtrMetadata(copy _56); StorageLive(_60); StorageLive(_61); @@ -426,10 +422,12 @@ bb23: { StorageDead(_41); + StorageLive(_42); StorageLive(_44); _44 = &raw const (*_36); _42 = copy _44 as *const u8 (PtrToPtr); StorageDead(_44); + StorageLive(_43); StorageLive(_45); _45 = &raw const (*_38); _43 = copy _45 as *const u8 (PtrToPtr); @@ -447,8 +445,6 @@ bb25: { StorageDead(_40); - StorageDead(_43); - StorageDead(_42); StorageDead(_39); StorageDead(_38); StorageDead(_36); @@ -461,15 +457,19 @@ bb26: { _7 = Eq(move _46, const 0_i32); StorageDead(_46); + StorageDead(_43); + StorageDead(_42); goto -> bb25; } bb27: { StorageDead(_61); + StorageLive(_62); StorageLive(_64); _64 = &raw const (*_56); _62 = copy _64 as *const u8 (PtrToPtr); StorageDead(_64); + StorageLive(_63); StorageLive(_65); _65 = &raw const (*_58); _63 = copy _65 as *const u8 (PtrToPtr); @@ -487,8 +487,6 @@ bb29: { StorageDead(_60); - StorageDead(_63); - StorageDead(_62); StorageDead(_59); StorageDead(_58); StorageDead(_56); @@ -501,6 +499,8 @@ bb30: { _14 = Eq(move _66, const 0_i32); StorageDead(_66); + StorageDead(_63); + StorageDead(_62); goto -> bb29; + } + @@ -524,8 +524,6 @@ + + bb35: { + StorageDead(_60); -+ StorageDead(_63); -+ StorageDead(_62); + StorageDead(_59); + StorageDead(_58); + StorageDead(_56); @@ -537,8 +535,6 @@ + + bb36: { + StorageDead(_40); -+ StorageDead(_43); -+ StorageDead(_42); + StorageDead(_39); + StorageDead(_38); + StorageDead(_36); diff --git a/tests/mir-opt/jump_threading.identity.JumpThreading.panic-abort.diff b/tests/mir-opt/jump_threading.identity.JumpThreading.panic-abort.diff index 9630f4001494..ec4a93c9a4e1 100644 --- a/tests/mir-opt/jump_threading.identity.JumpThreading.panic-abort.diff +++ b/tests/mir-opt/jump_threading.identity.JumpThreading.panic-abort.diff @@ -49,8 +49,6 @@ StorageLive(_4); _4 = copy _1; StorageLive(_10); - StorageLive(_11); - StorageLive(_12); _10 = discriminant(_4); switchInt(move _10) -> [0: bb7, 1: bb6, otherwise: bb1]; } @@ -76,18 +74,18 @@ StorageLive(_8); _8 = copy _6; StorageLive(_14); - StorageLive(_15); StorageLive(_17); _14 = discriminant(_8); _17 = Eq(copy _14, const 1_isize); assume(move _17); + StorageLive(_15); _15 = move ((_8 as Err).0: i32); StorageLive(_16); _16 = move _15; _0 = Result::::Err(move _16); StorageDead(_16); - StorageDead(_17); StorageDead(_15); + StorageDead(_17); StorageDead(_14); StorageDead(_8); StorageDead(_6); @@ -101,8 +99,6 @@ } bb5: { - StorageDead(_12); - StorageDead(_11); StorageDead(_10); StorageDead(_4); _5 = discriminant(_3); @@ -110,25 +106,27 @@ } bb6: { + StorageLive(_12); _12 = move ((_4 as Err).0: i32); StorageLive(_13); _13 = Result::::Err(copy _12); _3 = ControlFlow::, i32>::Break(move _13); StorageDead(_13); + StorageDead(_12); - goto -> bb5; + goto -> bb8; } bb7: { + StorageLive(_11); _11 = move ((_4 as Ok).0: i32); _3 = ControlFlow::, i32>::Continue(copy _11); + StorageDead(_11); - goto -> bb5; + goto -> bb9; + } + + bb8: { -+ StorageDead(_12); -+ StorageDead(_11); + StorageDead(_10); + StorageDead(_4); + _5 = discriminant(_3); @@ -136,8 +134,6 @@ + } + + bb9: { -+ StorageDead(_12); -+ StorageDead(_11); + StorageDead(_10); + StorageDead(_4); + _5 = discriminant(_3); diff --git a/tests/mir-opt/jump_threading.identity.JumpThreading.panic-unwind.diff b/tests/mir-opt/jump_threading.identity.JumpThreading.panic-unwind.diff index 9630f4001494..ec4a93c9a4e1 100644 --- a/tests/mir-opt/jump_threading.identity.JumpThreading.panic-unwind.diff +++ b/tests/mir-opt/jump_threading.identity.JumpThreading.panic-unwind.diff @@ -49,8 +49,6 @@ StorageLive(_4); _4 = copy _1; StorageLive(_10); - StorageLive(_11); - StorageLive(_12); _10 = discriminant(_4); switchInt(move _10) -> [0: bb7, 1: bb6, otherwise: bb1]; } @@ -76,18 +74,18 @@ StorageLive(_8); _8 = copy _6; StorageLive(_14); - StorageLive(_15); StorageLive(_17); _14 = discriminant(_8); _17 = Eq(copy _14, const 1_isize); assume(move _17); + StorageLive(_15); _15 = move ((_8 as Err).0: i32); StorageLive(_16); _16 = move _15; _0 = Result::::Err(move _16); StorageDead(_16); - StorageDead(_17); StorageDead(_15); + StorageDead(_17); StorageDead(_14); StorageDead(_8); StorageDead(_6); @@ -101,8 +99,6 @@ } bb5: { - StorageDead(_12); - StorageDead(_11); StorageDead(_10); StorageDead(_4); _5 = discriminant(_3); @@ -110,25 +106,27 @@ } bb6: { + StorageLive(_12); _12 = move ((_4 as Err).0: i32); StorageLive(_13); _13 = Result::::Err(copy _12); _3 = ControlFlow::, i32>::Break(move _13); StorageDead(_13); + StorageDead(_12); - goto -> bb5; + goto -> bb8; } bb7: { + StorageLive(_11); _11 = move ((_4 as Ok).0: i32); _3 = ControlFlow::, i32>::Continue(copy _11); + StorageDead(_11); - goto -> bb5; + goto -> bb9; + } + + bb8: { -+ StorageDead(_12); -+ StorageDead(_11); + StorageDead(_10); + StorageDead(_4); + _5 = discriminant(_3); @@ -136,8 +134,6 @@ + } + + bb9: { -+ StorageDead(_12); -+ StorageDead(_11); + StorageDead(_10); + StorageDead(_4); + _5 = discriminant(_3); diff --git a/tests/mir-opt/lower_array_len.array_bound.GVN.panic-abort.diff b/tests/mir-opt/lower_array_len.array_bound.GVN.panic-abort.diff index 98c5e868046b..c0500ca3bb83 100644 --- a/tests/mir-opt/lower_array_len.array_bound.GVN.panic-abort.diff +++ b/tests/mir-opt/lower_array_len.array_bound.GVN.panic-abort.diff @@ -14,8 +14,7 @@ let mut _9: bool; bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -63,8 +62,7 @@ } bb5: { -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/lower_array_len.array_bound.GVN.panic-unwind.diff b/tests/mir-opt/lower_array_len.array_bound.GVN.panic-unwind.diff index 72c731378699..9e6d01764ccd 100644 --- a/tests/mir-opt/lower_array_len.array_bound.GVN.panic-unwind.diff +++ b/tests/mir-opt/lower_array_len.array_bound.GVN.panic-unwind.diff @@ -14,8 +14,7 @@ let mut _9: bool; bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -63,8 +62,7 @@ } bb5: { -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-abort.diff b/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-abort.diff index 9ffaf44c02bd..b2d0efff8f30 100644 --- a/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-abort.diff +++ b/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-abort.diff @@ -16,8 +16,7 @@ let mut _11: bool; bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -77,8 +76,7 @@ } bb6: { -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-unwind.diff b/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-unwind.diff index 08008e463357..ab5209eca759 100644 --- a/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-unwind.diff +++ b/tests/mir-opt/lower_array_len.array_bound_mut.GVN.panic-unwind.diff @@ -16,8 +16,7 @@ let mut _11: bool; bb0: { -- StorageLive(_3); -+ nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; StorageLive(_5); @@ -77,8 +76,7 @@ } bb6: { -- StorageDead(_3); -+ nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-abort.mir index 3c475cd40309..426c114dfc2a 100644 --- a/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-abort.mir @@ -19,7 +19,7 @@ fn use_checked_sub(_1: u32, _2: u32) -> () { StorageLive(_5); StorageLive(_3); _3 = Lt(copy _1, copy _2); - switchInt(move _3) -> [0: bb1, otherwise: bb2]; + switchInt(move _3) -> [0: bb1, otherwise: bb3]; } bb1: { @@ -28,16 +28,22 @@ fn use_checked_sub(_1: u32, _2: u32) -> () { _5 = Option::::Some(move _4); StorageDead(_4); StorageDead(_3); + StorageLive(_6); _6 = copy ((_5 as Some).0: u32); - _7 = do_something(move _6) -> [return: bb3, unwind unreachable]; + _7 = do_something(move _6) -> [return: bb2, unwind unreachable]; } bb2: { - StorageDead(_3); - goto -> bb3; + StorageDead(_6); + goto -> bb4; } bb3: { + StorageDead(_3); + goto -> bb4; + } + + bb4: { StorageDead(_5); return; } diff --git a/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-unwind.mir index 3ef09764b1c5..f73c64a9b092 100644 --- a/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/checked_ops.use_checked_sub.PreCodegen.after.panic-unwind.mir @@ -19,7 +19,7 @@ fn use_checked_sub(_1: u32, _2: u32) -> () { StorageLive(_5); StorageLive(_3); _3 = Lt(copy _1, copy _2); - switchInt(move _3) -> [0: bb1, otherwise: bb2]; + switchInt(move _3) -> [0: bb1, otherwise: bb3]; } bb1: { @@ -28,16 +28,22 @@ fn use_checked_sub(_1: u32, _2: u32) -> () { _5 = Option::::Some(move _4); StorageDead(_4); StorageDead(_3); + StorageLive(_6); _6 = copy ((_5 as Some).0: u32); - _7 = do_something(move _6) -> [return: bb3, unwind continue]; + _7 = do_something(move _6) -> [return: bb2, unwind continue]; } bb2: { - StorageDead(_3); - goto -> bb3; + StorageDead(_6); + goto -> bb4; } bb3: { + StorageDead(_3); + goto -> bb4; + } + + bb4: { StorageDead(_5); return; } diff --git a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-abort.diff b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-abort.diff index 269af438e37e..f0b3a373d50a 100644 --- a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-abort.diff +++ b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-abort.diff @@ -15,8 +15,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _6 = copy (*_1); _2 = copy (*_6); _3 = unknown() -> [return: bb1, unwind unreachable]; @@ -32,8 +31,7 @@ + _0 = Eq(move _4, copy _2); StorageDead(_5); StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-unwind.diff b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-unwind.diff index 9ce17342a445..8676208dbf71 100644 --- a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-unwind.diff +++ b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.GVN.panic-unwind.diff @@ -15,8 +15,7 @@ } bb0: { -- StorageLive(_2); -+ nop; + StorageLive(_2); _6 = copy (*_1); _2 = copy (*_6); _3 = unknown() -> [return: bb1, unwind continue]; @@ -32,8 +31,7 @@ + _0 = Eq(move _4, copy _2); StorageDead(_5); StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-abort.mir index 23b1c3f3f43a..b3789dfab0cd 100644 --- a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-abort.mir @@ -13,6 +13,7 @@ fn src(_1: &&u8) -> bool { } bb0: { + StorageLive(_3); _2 = copy (*_1); _3 = copy (*_2); _4 = unknown() -> [return: bb1, unwind unreachable]; @@ -24,6 +25,7 @@ fn src(_1: &&u8) -> bool { _6 = copy (*_5); _0 = Eq(move _6, copy _3); StorageDead(_6); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-unwind.mir index 4c01e9464bf4..a3cf4806010a 100644 --- a/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/deref_nested_borrows.src.PreCodegen.after.panic-unwind.mir @@ -13,6 +13,7 @@ fn src(_1: &&u8) -> bool { } bb0: { + StorageLive(_3); _2 = copy (*_1); _3 = copy (*_2); _4 = unknown() -> [return: bb1, unwind continue]; @@ -24,6 +25,7 @@ fn src(_1: &&u8) -> bool { _6 = copy (*_5); _0 = Eq(move _6, copy _3); StorageDead(_6); + StorageDead(_3); return; } } diff --git a/tests/mir-opt/pre-codegen/derived_ord.demo_le.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/derived_ord.demo_le.PreCodegen.after.mir index 578aff4f7129..257b43050c3c 100644 --- a/tests/mir-opt/pre-codegen/derived_ord.demo_le.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/derived_ord.demo_le.PreCodegen.after.mir @@ -36,7 +36,6 @@ fn demo_le(_1: &MultiField, _2: &MultiField) -> bool { } bb0: { - StorageLive(_11); StorageLive(_6); StorageLive(_5); StorageLive(_7); @@ -69,13 +68,14 @@ fn demo_le(_1: &MultiField, _2: &MultiField) -> bool { bb2: { StorageDead(_7); StorageDead(_5); + StorageLive(_11); _11 = move ((_6 as Some).0: std::cmp::Ordering); StorageLive(_12); _12 = discriminant(_11); _0 = Le(move _12, const 0_i8); StorageDead(_12); - StorageDead(_6); StorageDead(_11); + StorageDead(_6); return; } } diff --git a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-abort.mir index 0cd241b4968e..7d45c16bb4dd 100644 --- a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-abort.mir @@ -67,12 +67,14 @@ fn drop_bytes(_1: *mut Box<[u8; 1024]>) -> () { bb0: { StorageLive(_3); + StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[u8; 1024]>).0: std::ptr::NonNull<[u8; 1024]>); _3 = copy _2 as std::ptr::NonNull (Transmute); _4 = alloc::alloc::__rust_dealloc(move _3, const 1024_usize, const std::mem::Alignment {{ _inner_repr_trick: mem::alignment::AlignmentEnum::_Align1Shl0 }}) -> [return: bb1, unwind unreachable]; } bb1: { + StorageDead(_2); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-unwind.mir index 0cd241b4968e..7d45c16bb4dd 100644 --- a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_bytes.PreCodegen.after.panic-unwind.mir @@ -67,12 +67,14 @@ fn drop_bytes(_1: *mut Box<[u8; 1024]>) -> () { bb0: { StorageLive(_3); + StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[u8; 1024]>).0: std::ptr::NonNull<[u8; 1024]>); _3 = copy _2 as std::ptr::NonNull (Transmute); _4 = alloc::alloc::__rust_dealloc(move _3, const 1024_usize, const std::mem::Alignment {{ _inner_repr_trick: mem::alignment::AlignmentEnum::_Align1Shl0 }}) -> [return: bb1, unwind unreachable]; } bb1: { + StorageDead(_2); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-abort.mir index 2b7c334394e0..4778b4ed7db7 100644 --- a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-abort.mir @@ -68,6 +68,7 @@ fn drop_generic(_1: *mut Box) -> () { bb0: { StorageLive(_4); + StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique).0: std::ptr::NonNull); _3 = const ::ALIGN as std::mem::Alignment (Transmute); switchInt(const ::SIZE) -> [0: bb3, otherwise: bb1]; @@ -83,6 +84,7 @@ fn drop_generic(_1: *mut Box) -> () { } bb3: { + StorageDead(_2); StorageDead(_4); return; } diff --git a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-unwind.mir index 2b7c334394e0..4778b4ed7db7 100644 --- a/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/drop_box_of_sized.drop_generic.PreCodegen.after.panic-unwind.mir @@ -68,6 +68,7 @@ fn drop_generic(_1: *mut Box) -> () { bb0: { StorageLive(_4); + StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique).0: std::ptr::NonNull); _3 = const ::ALIGN as std::mem::Alignment (Transmute); switchInt(const ::SIZE) -> [0: bb3, otherwise: bb1]; @@ -83,6 +84,7 @@ fn drop_generic(_1: *mut Box) -> () { } bb3: { + StorageDead(_2); StorageDead(_4); return; } diff --git a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-abort.mir b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-abort.mir index cb6a7743d578..1c5a9bca84d4 100644 --- a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-abort.mir @@ -72,6 +72,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb0: { StorageLive(_3); + StorageLive(_5); StorageLive(_8); StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[T]>).0: std::ptr::NonNull<[T]>); @@ -98,6 +99,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb3: { StorageDead(_2); StorageDead(_8); + StorageDead(_5); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-unwind.mir b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-unwind.mir index cb6a7743d578..1c5a9bca84d4 100644 --- a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.32bit.panic-unwind.mir @@ -72,6 +72,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb0: { StorageLive(_3); + StorageLive(_5); StorageLive(_8); StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[T]>).0: std::ptr::NonNull<[T]>); @@ -98,6 +99,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb3: { StorageDead(_2); StorageDead(_8); + StorageDead(_5); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-abort.mir b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-abort.mir index cb6a7743d578..1c5a9bca84d4 100644 --- a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-abort.mir @@ -72,6 +72,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb0: { StorageLive(_3); + StorageLive(_5); StorageLive(_8); StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[T]>).0: std::ptr::NonNull<[T]>); @@ -98,6 +99,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb3: { StorageDead(_2); StorageDead(_8); + StorageDead(_5); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-unwind.mir b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-unwind.mir index cb6a7743d578..1c5a9bca84d4 100644 --- a/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/drop_boxed_slice.generic_in_place.PreCodegen.after.64bit.panic-unwind.mir @@ -72,6 +72,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb0: { StorageLive(_3); + StorageLive(_5); StorageLive(_8); StorageLive(_2); _2 = copy (((*_1).0: std::ptr::Unique<[T]>).0: std::ptr::NonNull<[T]>); @@ -98,6 +99,7 @@ fn generic_in_place(_1: *mut Box<[T]>) -> () { bb3: { StorageDead(_2); StorageDead(_8); + StorageDead(_5); StorageDead(_3); return; } diff --git a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-abort.diff b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-abort.diff index babdc70ec0fd..a0526d279a86 100644 --- a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-abort.diff +++ b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-abort.diff @@ -41,8 +41,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = Option::::None; + _2 = const Option::::None; @@ -80,13 +79,13 @@ bb4: { StorageDead(_7); StorageLive(_10); - StorageLive(_14); _10 = discriminant(_6); switchInt(move _10) -> [0: bb6, 1: bb5, otherwise: bb1]; } bb5: { StorageLive(_13); + StorageLive(_14); _14 = &_11; _13 = copy _14 as &dyn std::fmt::Debug (PointerCoercion(Unsize, Implicit)); _12 = result::unwrap_failed(const "called `Result::unwrap()` on an `Err` value", move _13) -> unwind unreachable; @@ -94,7 +93,6 @@ bb6: { _5 = move ((_6 as Ok).0: std::ptr::NonNull<[u8]>); - StorageDead(_14); StorageDead(_10); StorageDead(_6); _4 = copy _5 as *mut [u8] (Transmute); @@ -102,8 +100,7 @@ _3 = copy _4 as *mut u8 (PtrToPtr); StorageDead(_4); StorageDead(_3); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-unwind.diff b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-unwind.diff index 2f535c61fc5a..3b5ecd3d2b16 100644 --- a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-unwind.diff +++ b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.32bit.panic-unwind.diff @@ -30,8 +30,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = Option::::None; + _2 = const Option::::None; @@ -49,8 +48,7 @@ _3 = copy _4 as *mut u8 (PtrToPtr); StorageDead(_4); StorageDead(_3); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } diff --git a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-abort.diff b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-abort.diff index 11d64d05c7d1..3a6b52b0f249 100644 --- a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-abort.diff +++ b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-abort.diff @@ -41,8 +41,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = Option::::None; + _2 = const Option::::None; @@ -80,13 +79,13 @@ bb4: { StorageDead(_7); StorageLive(_10); - StorageLive(_14); _10 = discriminant(_6); switchInt(move _10) -> [0: bb6, 1: bb5, otherwise: bb1]; } bb5: { StorageLive(_13); + StorageLive(_14); _14 = &_11; _13 = copy _14 as &dyn std::fmt::Debug (PointerCoercion(Unsize, Implicit)); _12 = result::unwrap_failed(const "called `Result::unwrap()` on an `Err` value", move _13) -> unwind unreachable; @@ -94,7 +93,6 @@ bb6: { _5 = move ((_6 as Ok).0: std::ptr::NonNull<[u8]>); - StorageDead(_14); StorageDead(_10); StorageDead(_6); _4 = copy _5 as *mut [u8] (Transmute); @@ -102,8 +100,7 @@ _3 = copy _4 as *mut u8 (PtrToPtr); StorageDead(_4); StorageDead(_3); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } } diff --git a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-unwind.diff b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-unwind.diff index f3f671b7735d..673c05d673fb 100644 --- a/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-unwind.diff +++ b/tests/mir-opt/pre-codegen/issue_117368_print_invalid_constant.main.GVN.64bit.panic-unwind.diff @@ -30,8 +30,7 @@ } bb0: { -- StorageLive(_1); -+ nop; + StorageLive(_1); StorageLive(_2); - _2 = Option::::None; + _2 = const Option::::None; @@ -49,8 +48,7 @@ _3 = copy _4 as *mut u8 (PtrToPtr); StorageDead(_4); StorageDead(_3); -- StorageDead(_1); -+ nop; + StorageDead(_1); return; } diff --git a/tests/mir-opt/pre-codegen/loops.filter_mapped.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/loops.filter_mapped.PreCodegen.after.mir index 8f30ad30fccd..6921827c599b 100644 --- a/tests/mir-opt/pre-codegen/loops.filter_mapped.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/loops.filter_mapped.PreCodegen.after.mir @@ -64,11 +64,13 @@ fn filter_mapped(_1: impl Iterator, _2: impl Fn(T) -> Option) -> () } bb6: { + StorageLive(_9); _9 = move ((_7 as Some).0: U); _10 = opaque::(move _9) -> [return: bb7, unwind: bb9]; } bb7: { + StorageDead(_9); StorageDead(_7); goto -> bb2; } diff --git a/tests/mir-opt/pre-codegen/loops.int_range.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/loops.int_range.PreCodegen.after.mir index beb7b936ccf7..49b373afdd38 100644 --- a/tests/mir-opt/pre-codegen/loops.int_range.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/loops.int_range.PreCodegen.after.mir @@ -79,18 +79,22 @@ fn int_range(_1: usize, _2: usize) -> () { } bb3: { + StorageLive(_7); _7 = copy (_3.0: usize); StorageLive(_8); _8 = AddUnchecked(copy _7, const 1_usize); (_3.0: usize) = move _8; StorageDead(_8); _9 = Option::::Some(copy _7); + StorageDead(_7); StorageDead(_6); + StorageLive(_10); _10 = copy ((_9 as Some).0: usize); _11 = opaque::(move _10) -> [return: bb4, unwind continue]; } bb4: { + StorageDead(_10); StorageDead(_9); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/loops.mapped.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/loops.mapped.PreCodegen.after.mir index 406c96fc32f4..c65b94a3e2a2 100644 --- a/tests/mir-opt/pre-codegen/loops.mapped.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/loops.mapped.PreCodegen.after.mir @@ -54,7 +54,6 @@ fn mapped(_1: impl Iterator, _2: impl Fn(T) -> U) -> () { bb2: { StorageLive(_12); // DBG: _15 = &_4; - StorageLive(_7); StorageLive(_6); StorageLive(_5); _5 = &mut (_4.0: impl Iterator); @@ -63,18 +62,17 @@ fn mapped(_1: impl Iterator, _2: impl Fn(T) -> U) -> () { bb3: { StorageDead(_5); + StorageLive(_7); _7 = &mut (_4.1: impl Fn(T) -> U); StorageLive(_8); - StorageLive(_9); _8 = discriminant(_6); switchInt(move _8) -> [0: bb4, 1: bb6, otherwise: bb9]; } bb4: { - StorageDead(_9); StorageDead(_8); - StorageDead(_6); StorageDead(_7); + StorageDead(_6); StorageDead(_12); drop(_4) -> [return: bb5, unwind continue]; } @@ -85,6 +83,7 @@ fn mapped(_1: impl Iterator, _2: impl Fn(T) -> U) -> () { } bb6: { + StorageLive(_9); _9 = move ((_6 as Some).0: T); StorageLive(_11); StorageLive(_10); @@ -98,13 +97,15 @@ fn mapped(_1: impl Iterator, _2: impl Fn(T) -> U) -> () { StorageDead(_11); StorageDead(_9); StorageDead(_8); - StorageDead(_6); StorageDead(_7); + StorageDead(_6); + StorageLive(_13); _13 = move ((_12 as Some).0: U); _14 = opaque::(move _13) -> [return: bb8, unwind: bb10]; } bb8: { + StorageDead(_13); StorageDead(_12); goto -> bb2; } diff --git a/tests/mir-opt/pre-codegen/loops.vec_move.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/loops.vec_move.PreCodegen.after.mir index 3aba69bf7fd5..5d22791eaa89 100644 --- a/tests/mir-opt/pre-codegen/loops.vec_move.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/loops.vec_move.PreCodegen.after.mir @@ -182,8 +182,6 @@ fn vec_move(_1: Vec) -> () { bb0: { StorageLive(_22); - StorageLive(_6); - StorageLive(_7); StorageLive(_11); StorageLive(_20); StorageLive(_5); @@ -198,10 +196,12 @@ fn vec_move(_1: Vec) -> () { // DBG: _29 = &((_3.0: std::mem::MaybeDangling>).0: std::vec::Vec); _4 = &raw const (((((_3.0: std::mem::MaybeDangling>).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).2: std::alloc::Global); StorageDead(_4); + StorageLive(_6); // DBG: _32 = &_3; // DBG: _31 = &(((_3.0: std::mem::MaybeDangling>).0: std::vec::Vec).0: alloc::raw_vec::RawVec); _5 = copy ((((((_3.0: std::mem::MaybeDangling>).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique).0: std::ptr::NonNull); _6 = copy _5 as std::ptr::NonNull (Transmute); + StorageLive(_7); _7 = copy _5 as *mut impl Sized (Transmute); switchInt(const ::IS_ZST) -> [0: bb1, otherwise: bb2]; } @@ -278,13 +278,13 @@ fn vec_move(_1: Vec) -> () { bb7: { _22 = std::vec::IntoIter:: { buf: copy _6, phantom: const ZeroSized: PhantomData, cap: move _20, alloc: const ManuallyDrop:: {{ value: MaybeDangling::(std::alloc::Global) }}, ptr: copy _6, end: copy _11 }; + StorageDead(_7); + StorageDead(_6); StorageDead(_3); StorageDead(_17); StorageDead(_5); StorageDead(_20); StorageDead(_11); - StorageDead(_7); - StorageDead(_6); StorageLive(_23); _23 = move _22; goto -> bb8; @@ -292,6 +292,7 @@ fn vec_move(_1: Vec) -> () { bb8: { StorageLive(_25); + StorageLive(_24); _24 = &mut _23; _25 = as Iterator>::next(move _24) -> [return: bb9, unwind: bb15]; } @@ -302,6 +303,7 @@ fn vec_move(_1: Vec) -> () { } bb10: { + StorageDead(_24); StorageDead(_25); drop(_23) -> [return: bb11, unwind continue]; } @@ -313,11 +315,14 @@ fn vec_move(_1: Vec) -> () { } bb12: { + StorageLive(_27); _27 = move ((_25 as Some).0: impl Sized); _28 = opaque::(move _27) -> [return: bb13, unwind: bb15]; } bb13: { + StorageDead(_27); + StorageDead(_24); StorageDead(_25); goto -> bb8; } diff --git a/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-abort.mir index 03a52b82b49b..d107a37da0fe 100644 --- a/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-abort.mir @@ -64,10 +64,13 @@ fn forward_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb4: { + StorageLive(_6); _6 = copy _1; _1 = AddUnchecked(copy _6, const 1_u32); _7 = Option::::Some(copy _6); + StorageDead(_6); StorageDead(_5); + StorageLive(_8); _8 = copy ((_7 as Some).0: u32); StorageLive(_9); _9 = &_3; @@ -79,6 +82,7 @@ fn forward_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb5: { StorageDead(_10); StorageDead(_9); + StorageDead(_8); StorageDead(_7); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir index 3b09f33e7333..207dde62f7d6 100644 --- a/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir @@ -64,10 +64,13 @@ fn forward_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb4: { + StorageLive(_6); _6 = copy _1; _1 = AddUnchecked(copy _6, const 1_u32); _7 = Option::::Some(copy _6); + StorageDead(_6); StorageDead(_5); + StorageLive(_8); _8 = copy ((_7 as Some).0: u32); StorageLive(_9); _9 = &_3; @@ -79,6 +82,7 @@ fn forward_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb5: { StorageDead(_10); StorageDead(_9); + StorageDead(_8); StorageDead(_7); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-abort.mir index 3f000dcafb03..63d9b1d1d003 100644 --- a/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-abort.mir @@ -36,6 +36,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb1: { StorageLive(_7); + StorageLive(_6); _6 = &mut _5; _7 = as iter::range::RangeInclusiveIteratorImpl>::spec_next(move _6) -> [return: bb2, unwind unreachable]; } @@ -46,6 +47,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb3: { + StorageDead(_6); StorageDead(_7); StorageDead(_5); drop(_3) -> [return: bb4, unwind unreachable]; @@ -56,6 +58,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb5: { + StorageLive(_9); _9 = copy ((_7 as Some).0: u32); StorageLive(_10); _10 = &_3; @@ -67,6 +70,8 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb6: { StorageDead(_11); StorageDead(_10); + StorageDead(_9); + StorageDead(_6); StorageDead(_7); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-unwind.mir index 235371736271..33c9b492c5f1 100644 --- a/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/range_iter.inclusive_loop.PreCodegen.after.panic-unwind.mir @@ -36,6 +36,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb1: { StorageLive(_7); + StorageLive(_6); _6 = &mut _5; _7 = as iter::range::RangeInclusiveIteratorImpl>::spec_next(move _6) -> [return: bb2, unwind: bb8]; } @@ -46,6 +47,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb3: { + StorageDead(_6); StorageDead(_7); StorageDead(_5); drop(_3) -> [return: bb4, unwind continue]; @@ -56,6 +58,7 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { } bb5: { + StorageLive(_9); _9 = copy ((_7 as Some).0: u32); StorageLive(_10); _10 = &_3; @@ -67,6 +70,8 @@ fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () { bb6: { StorageDead(_11); StorageDead(_10); + StorageDead(_9); + StorageDead(_6); StorageDead(_7); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-abort.mir index 1f82fc59ac2c..55caea9d8f96 100644 --- a/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-abort.mir @@ -43,12 +43,14 @@ fn range_iter_next(_1: &mut std::ops::Range) -> Option { } bb2: { + StorageLive(_5); _5 = copy ((*_1).0: u32); StorageLive(_6); _6 = AddUnchecked(copy _5, const 1_u32); ((*_1).0: u32) = move _6; StorageDead(_6); _0 = Option::::Some(copy _5); + StorageDead(_5); goto -> bb3; } diff --git a/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-unwind.mir index 1f82fc59ac2c..55caea9d8f96 100644 --- a/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/range_iter.range_iter_next.PreCodegen.after.panic-unwind.mir @@ -43,12 +43,14 @@ fn range_iter_next(_1: &mut std::ops::Range) -> Option { } bb2: { + StorageLive(_5); _5 = copy ((*_1).0: u32); StorageLive(_6); _6 = AddUnchecked(copy _5, const 1_u32); ((*_1).0: u32) = move _6; StorageDead(_6); _0 = Option::::Some(copy _5); + StorageDead(_5); goto -> bb3; } diff --git a/tests/mir-opt/pre-codegen/simple_option_map.ezmap.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/simple_option_map.ezmap.PreCodegen.after.mir index 7595ad88d9df..876fa96dfb6f 100644 --- a/tests/mir-opt/pre-codegen/simple_option_map.ezmap.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/simple_option_map.ezmap.PreCodegen.after.mir @@ -25,11 +25,13 @@ fn ezmap(_1: Option) -> Option { } bb2: { + StorageLive(_3); _3 = copy ((_1 as Some).0: i32); StorageLive(_4); _4 = Add(copy _3, const 1_i32); _0 = Option::::Some(move _4); StorageDead(_4); + StorageDead(_3); goto -> bb3; } diff --git a/tests/mir-opt/pre-codegen/simple_option_map.map_via_question_mark.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/simple_option_map.map_via_question_mark.PreCodegen.after.mir index ef7ccfa5bddf..ff0396b168f8 100644 --- a/tests/mir-opt/pre-codegen/simple_option_map.map_via_question_mark.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/simple_option_map.map_via_question_mark.PreCodegen.after.mir @@ -32,13 +32,11 @@ fn map_via_question_mark(_1: Option) -> Option { StorageLive(_9); StorageLive(_7); StorageLive(_2); - StorageLive(_6); _2 = discriminant(_1); switchInt(move _2) -> [0: bb1, 1: bb2, otherwise: bb4]; } bb1: { - StorageDead(_6); StorageDead(_2); StorageLive(_3); StorageLive(_5); @@ -54,6 +52,7 @@ fn map_via_question_mark(_1: Option) -> Option { } bb2: { + StorageLive(_6); _6 = copy ((_1 as Some).0: i32); _7 = ControlFlow::, i32>::Continue(copy _6); StorageDead(_6); diff --git a/tests/mir-opt/pre-codegen/slice_filter.variant_b-{closure#0}.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/slice_filter.variant_b-{closure#0}.PreCodegen.after.mir index f93f7264dec2..6a74719e04ad 100644 --- a/tests/mir-opt/pre-codegen/slice_filter.variant_b-{closure#0}.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/slice_filter.variant_b-{closure#0}.PreCodegen.after.mir @@ -21,12 +21,16 @@ fn variant_b::{closure#0}(_1: &mut {closure@$DIR/slice_filter.rs:11:25: 11:41}, } bb0: { + StorageLive(_4); _3 = copy (*_2); _4 = copy ((*_3).0: usize); + StorageLive(_6); _5 = copy (*_2); _6 = copy ((*_5).1: usize); + StorageLive(_8); _7 = copy (*_2); _8 = copy ((*_7).2: usize); + StorageLive(_10); _9 = copy (*_2); _10 = copy ((*_9).3: usize); StorageLive(_11); @@ -69,6 +73,10 @@ fn variant_b::{closure#0}(_1: &mut {closure@$DIR/slice_filter.rs:11:25: 11:41}, bb7: { StorageDead(_12); StorageDead(_11); + StorageDead(_10); + StorageDead(_8); + StorageDead(_6); + StorageDead(_4); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir index 8444157a1550..67194ea7225f 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-abort.mir @@ -31,12 +31,13 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); StorageLive(_11); StorageLive(_5); _5 = &raw mut (*_1); - StorageLive(_8); StorageLive(_6); _6 = PtrMetadata(copy _1); _7 = as SliceIndex<[T]>>::get_unchecked_mut::precondition_check(copy _3, copy _4, move _6) -> [return: bb1, unwind unreachable]; @@ -44,10 +45,11 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> bb1: { StorageDead(_6); + StorageLive(_8); _8 = SubUnchecked(copy _4, copy _3); StorageLive(_9); - StorageLive(_10); _9 = copy _5 as *mut u32 (PtrToPtr); + StorageLive(_10); _10 = Offset(copy _9, copy _3); _11 = *mut [u32] from (copy _10, copy _8); StorageDead(_10); @@ -56,6 +58,8 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> StorageDead(_5); _0 = &mut (*_11); StorageDead(_11); + StorageDead(_3); + StorageDead(_4); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir index 8444157a1550..67194ea7225f 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_get_unchecked_mut_range.PreCodegen.after.panic-unwind.mir @@ -31,12 +31,13 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); StorageLive(_11); StorageLive(_5); _5 = &raw mut (*_1); - StorageLive(_8); StorageLive(_6); _6 = PtrMetadata(copy _1); _7 = as SliceIndex<[T]>>::get_unchecked_mut::precondition_check(copy _3, copy _4, move _6) -> [return: bb1, unwind unreachable]; @@ -44,10 +45,11 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> bb1: { StorageDead(_6); + StorageLive(_8); _8 = SubUnchecked(copy _4, copy _3); StorageLive(_9); - StorageLive(_10); _9 = copy _5 as *mut u32 (PtrToPtr); + StorageLive(_10); _10 = Offset(copy _9, copy _3); _11 = *mut [u32] from (copy _10, copy _8); StorageDead(_10); @@ -56,6 +58,8 @@ fn slice_get_unchecked_mut_range(_1: &mut [u32], _2: std::ops::Range) -> StorageDead(_5); _0 = &mut (*_11); StorageDead(_11); + StorageDead(_3); + StorageDead(_4); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-abort.mir index 54be39b4293f..ed82be1bac33 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-abort.mir @@ -30,6 +30,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); StorageLive(_5); @@ -58,8 +60,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { StorageLive(_9); _9 = &raw const (*_1); StorageLive(_10); - StorageLive(_11); _10 = copy _9 as *const u32 (PtrToPtr); + StorageLive(_11); _11 = Offset(copy _10, copy _3); _12 = *const [u32] from (copy _11, copy _6); StorageDead(_11); @@ -68,6 +70,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { _0 = &(*_12); StorageDead(_12); StorageDead(_8); + StorageDead(_3); + StorageDead(_4); return; } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-unwind.mir index b258603a3d0d..cf2b8d664708 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_index_range.PreCodegen.after.panic-unwind.mir @@ -30,6 +30,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); StorageLive(_5); @@ -58,8 +60,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { StorageLive(_9); _9 = &raw const (*_1); StorageLive(_10); - StorageLive(_11); _10 = copy _9 as *const u32 (PtrToPtr); + StorageLive(_11); _11 = Offset(copy _10, copy _3); _12 = *const [u32] from (copy _11, copy _6); StorageDead(_11); @@ -68,6 +70,8 @@ fn slice_index_range(_1: &[u32], _2: std::ops::Range) -> &[u32] { _0 = &(*_12); StorageDead(_12); StorageDead(_8); + StorageDead(_3); + StorageDead(_4); return; } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-abort.mir b/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-abort.mir index 7e9d9d24d619..21bc3bcc07c4 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-abort.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-abort.mir @@ -29,9 +29,10 @@ fn slice_ptr_get_unchecked_range(_1: *const [u32], _2: std::ops::Range) - } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); - StorageLive(_7); StorageLive(_5); _5 = PtrMetadata(copy _1); _6 = as SliceIndex<[T]>>::get_unchecked::precondition_check(copy _3, copy _4, move _5) -> [return: bb1, unwind unreachable]; @@ -39,15 +40,18 @@ fn slice_ptr_get_unchecked_range(_1: *const [u32], _2: std::ops::Range) - bb1: { StorageDead(_5); + StorageLive(_7); _7 = SubUnchecked(copy _4, copy _3); StorageLive(_8); - StorageLive(_9); _8 = copy _1 as *const u32 (PtrToPtr); + StorageLive(_9); _9 = Offset(copy _8, copy _3); _0 = *const [u32] from (copy _9, copy _7); StorageDead(_9); StorageDead(_8); StorageDead(_7); + StorageDead(_3); + StorageDead(_4); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-unwind.mir index 7e9d9d24d619..21bc3bcc07c4 100644 --- a/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_index.slice_ptr_get_unchecked_range.PreCodegen.after.panic-unwind.mir @@ -29,9 +29,10 @@ fn slice_ptr_get_unchecked_range(_1: *const [u32], _2: std::ops::Range) - } bb0: { + StorageLive(_3); + StorageLive(_4); _3 = move (_2.0: usize); _4 = move (_2.1: usize); - StorageLive(_7); StorageLive(_5); _5 = PtrMetadata(copy _1); _6 = as SliceIndex<[T]>>::get_unchecked::precondition_check(copy _3, copy _4, move _5) -> [return: bb1, unwind unreachable]; @@ -39,15 +40,18 @@ fn slice_ptr_get_unchecked_range(_1: *const [u32], _2: std::ops::Range) - bb1: { StorageDead(_5); + StorageLive(_7); _7 = SubUnchecked(copy _4, copy _3); StorageLive(_8); - StorageLive(_9); _8 = copy _1 as *const u32 (PtrToPtr); + StorageLive(_9); _9 = Offset(copy _8, copy _3); _0 = *const [u32] from (copy _9, copy _7); StorageDead(_9); StorageDead(_8); StorageDead(_7); + StorageDead(_3); + StorageDead(_4); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_iter.enumerated_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.enumerated_loop.PreCodegen.after.panic-unwind.mir index 13ced6ec9b01..07522650e293 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.enumerated_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.enumerated_loop.PreCodegen.after.panic-unwind.mir @@ -64,10 +64,10 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { bb0: { StorageLive(_12); - StorageLive(_3); - StorageLive(_8); StorageLive(_11); + StorageLive(_3); _3 = PtrMetadata(copy _1); + StorageLive(_8); StorageLive(_5); StorageLive(_4); _4 = &raw const (*_1); @@ -102,9 +102,9 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { bb3: { _12 = std::slice::Iter::<'_, T> { ptr: copy _8, end_or_len: copy _11, _marker: const ZeroSized: PhantomData<&T> }; - StorageDead(_11); StorageDead(_8); StorageDead(_3); + StorageDead(_11); _13 = Enumerate::> { iter: copy _12, count: const 0_usize }; StorageDead(_12); StorageLive(_14); @@ -113,6 +113,8 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { } bb4: { + StorageLive(_16); + StorageLive(_15); _15 = &mut _14; _16 = > as Iterator>::next(move _15) -> [return: bb5, unwind: bb11]; } @@ -123,6 +125,8 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { } bb6: { + StorageDead(_15); + StorageDead(_16); StorageDead(_14); drop(_2) -> [return: bb7, unwind continue]; } @@ -132,7 +136,9 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { } bb8: { + StorageLive(_18); _18 = copy (((_16 as Some).0: (usize, &T)).0: usize); + StorageLive(_19); _19 = copy (((_16 as Some).0: (usize, &T)).1: &T); StorageLive(_20); _20 = &_2; @@ -144,6 +150,10 @@ fn enumerated_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { bb9: { StorageDead(_21); StorageDead(_20); + StorageDead(_19); + StorageDead(_18); + StorageDead(_15); + StorageDead(_16); goto -> bb4; } diff --git a/tests/mir-opt/pre-codegen/slice_iter.forward_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.forward_loop.PreCodegen.after.panic-unwind.mir index e8728eacf7f4..e06c093e3a5b 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.forward_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.forward_loop.PreCodegen.after.panic-unwind.mir @@ -142,20 +142,18 @@ fn forward_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb4: { StorageLive(_23); - StorageLive(_12); - StorageLive(_13); - StorageLive(_19); StorageLive(_20); - StorageLive(_14); - StorageLive(_22); StorageLive(_15); + StorageLive(_12); _12 = copy _8; + StorageLive(_13); _13 = copy _11; switchInt(const ::IS_ZST) -> [0: bb5, otherwise: bb8]; } bb5: { StorageLive(_17); + StorageLive(_14); _14 = copy _13 as std::ptr::NonNull (Transmute); _15 = copy _12 as *mut T (Transmute); StorageLive(_16); @@ -166,6 +164,7 @@ fn forward_loop(_1: &[T], _2: impl Fn(&T)) -> () { } bb6: { + StorageDead(_14); StorageDead(_17); StorageLive(_18); _18 = Offset(copy _15, const 1_usize); @@ -175,27 +174,27 @@ fn forward_loop(_1: &[T], _2: impl Fn(&T)) -> () { } bb7: { + StorageDead(_14); StorageDead(_17); goto -> bb10; } bb8: { + StorageLive(_19); _19 = copy _13 as usize (Transmute); switchInt(copy _19) -> [0: bb9, otherwise: bb12]; } bb9: { + StorageDead(_19); goto -> bb10; } bb10: { - StorageDead(_15); - StorageDead(_22); - StorageDead(_14); - StorageDead(_20); - StorageDead(_19); StorageDead(_13); StorageDead(_12); + StorageDead(_15); + StorageDead(_20); StorageDead(_23); drop(_2) -> [return: bb11, unwind continue]; } @@ -207,22 +206,23 @@ fn forward_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb12: { _20 = SubUnchecked(copy _19, const 1_usize); _11 = copy _20 as *const T (Transmute); + StorageDead(_19); goto -> bb13; } bb13: { + StorageLive(_22); StorageLive(_21); _21 = copy _12 as *const T (Transmute); _22 = &(*_21); StorageDead(_21); _23 = Option::<&T>::Some(copy _22); - StorageDead(_15); StorageDead(_22); - StorageDead(_14); - StorageDead(_20); - StorageDead(_19); StorageDead(_13); StorageDead(_12); + StorageDead(_15); + StorageDead(_20); + StorageLive(_24); _24 = copy ((_23 as Some).0: &T); StorageLive(_25); _25 = &_2; @@ -234,6 +234,7 @@ fn forward_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb14: { StorageDead(_26); StorageDead(_25); + StorageDead(_24); StorageDead(_23); goto -> bb4; } diff --git a/tests/mir-opt/pre-codegen/slice_iter.range_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.range_loop.PreCodegen.after.panic-unwind.mir index 8e573ef488fc..59aa46bd8cc3 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.range_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.range_loop.PreCodegen.after.panic-unwind.mir @@ -72,11 +72,15 @@ fn range_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { } bb4: { + StorageLive(_7); _7 = copy _4; _4 = AddUnchecked(copy _7, const 1_usize); _8 = Option::::Some(copy _7); + StorageDead(_7); StorageDead(_6); + StorageLive(_9); _9 = copy ((_8 as Some).0: usize); + StorageLive(_11); _10 = Lt(copy _9, copy _3); assert(move _10, "index out of bounds: the length is {} but the index is {}", copy _3, copy _9) -> [success: bb5, unwind: bb7]; } @@ -93,6 +97,8 @@ fn range_loop(_1: &[T], _2: impl Fn(usize, &T)) -> () { bb6: { StorageDead(_13); StorageDead(_12); + StorageDead(_11); + StorageDead(_9); StorageDead(_8); goto -> bb1; } diff --git a/tests/mir-opt/pre-codegen/slice_iter.reverse_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.reverse_loop.PreCodegen.after.panic-unwind.mir index bbb9b8e2dd50..84d3c68aba0d 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.reverse_loop.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.reverse_loop.PreCodegen.after.panic-unwind.mir @@ -132,10 +132,10 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb0: { StorageLive(_12); - StorageLive(_3); - StorageLive(_8); StorageLive(_11); + StorageLive(_3); _3 = PtrMetadata(copy _1); + StorageLive(_8); StorageLive(_5); StorageLive(_4); _4 = &raw const (*_1); @@ -170,9 +170,9 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb3: { _12 = std::slice::Iter::<'_, T> { ptr: copy _8, end_or_len: copy _11, _marker: const ZeroSized: PhantomData<&T> }; - StorageDead(_11); StorageDead(_8); StorageDead(_3); + StorageDead(_11); _13 = Rev::> { iter: copy _12 }; StorageDead(_12); StorageLive(_14); @@ -182,15 +182,12 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb4: { StorageLive(_35); - StorageLive(_22); - StorageLive(_21); - StorageLive(_16); - StorageLive(_34); StorageLive(_20); switchInt(const ::IS_ZST) -> [0: bb5, otherwise: bb6]; } bb5: { + StorageLive(_16); StorageLive(_15); _15 = copy ((_14.0: std::slice::Iter<'_, T>).1: *const T); _16 = copy _15 as std::ptr::NonNull (Transmute); @@ -205,13 +202,18 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { _20 = Eq(copy _18, copy _19); StorageDead(_19); StorageDead(_18); + StorageDead(_16); goto -> bb7; } bb6: { + StorageLive(_22); + StorageLive(_21); _21 = copy ((_14.0: std::slice::Iter<'_, T>).1: *const T); _22 = copy _21 as usize (Transmute); + StorageDead(_21); _20 = Eq(copy _22, const 0_usize); + StorageDead(_22); goto -> bb7; } @@ -220,6 +222,7 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { } bb8: { + StorageLive(_34); StorageLive(_28); StorageLive(_30); StorageLive(_24); @@ -279,11 +282,9 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { StorageDead(_33); StorageDead(_28); _35 = Option::<&T>::Some(copy _34); - StorageDead(_20); StorageDead(_34); - StorageDead(_16); - StorageDead(_21); - StorageDead(_22); + StorageDead(_20); + StorageLive(_36); _36 = copy ((_35 as Some).0: &T); StorageLive(_37); _37 = &_2; @@ -295,6 +296,7 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb14: { StorageDead(_38); StorageDead(_37); + StorageDead(_36); StorageDead(_35); goto -> bb4; } @@ -309,10 +311,6 @@ fn reverse_loop(_1: &[T], _2: impl Fn(&T)) -> () { bb17: { StorageDead(_20); - StorageDead(_34); - StorageDead(_16); - StorageDead(_21); - StorageDead(_22); StorageDead(_35); StorageDead(_14); drop(_2) -> [return: bb18, unwind continue]; diff --git a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_generic_is_empty.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_generic_is_empty.PreCodegen.after.panic-unwind.mir index 9b510380b10b..04f78fa3e7e3 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_generic_is_empty.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_generic_is_empty.PreCodegen.after.panic-unwind.mir @@ -30,13 +30,11 @@ fn slice_iter_generic_is_empty(_1: &std::slice::Iter<'_, T>) -> bool { } bb0: { - StorageLive(_8); - StorageLive(_7); - StorageLive(_3); switchInt(const ::IS_ZST) -> [0: bb1, otherwise: bb2]; } bb1: { + StorageLive(_3); StorageLive(_2); _2 = copy ((*_1).1: *const T); _3 = copy _2 as std::ptr::NonNull (Transmute); @@ -51,20 +49,22 @@ fn slice_iter_generic_is_empty(_1: &std::slice::Iter<'_, T>) -> bool { _0 = Eq(copy _5, copy _6); StorageDead(_6); StorageDead(_5); + StorageDead(_3); goto -> bb3; } bb2: { + StorageLive(_8); + StorageLive(_7); _7 = copy ((*_1).1: *const T); _8 = copy _7 as usize (Transmute); + StorageDead(_7); _0 = Eq(copy _8, const 0_usize); + StorageDead(_8); goto -> bb3; } bb3: { - StorageDead(_3); - StorageDead(_7); - StorageDead(_8); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_mut_next_back.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_mut_next_back.PreCodegen.after.panic-unwind.mir index 99f793ea6724..94471cbb157c 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_mut_next_back.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_mut_next_back.PreCodegen.after.panic-unwind.mir @@ -73,16 +73,13 @@ fn slice_iter_mut_next_back(_1: &mut std::slice::IterMut<'_, T>) -> Option<&mut } bb0: { - StorageLive(_9); - StorageLive(_8); - StorageLive(_3); StorageLive(_2); - StorageLive(_21); StorageLive(_7); switchInt(const ::IS_ZST) -> [0: bb1, otherwise: bb2]; } bb1: { + StorageLive(_3); _2 = copy ((*_1).1: *mut T); _3 = copy _2 as std::ptr::NonNull (Transmute); StorageLive(_5); @@ -95,13 +92,18 @@ fn slice_iter_mut_next_back(_1: &mut std::slice::IterMut<'_, T>) -> Option<&mut _7 = Eq(copy _5, copy _6); StorageDead(_6); StorageDead(_5); + StorageDead(_3); goto -> bb3; } bb2: { + StorageLive(_9); + StorageLive(_8); _8 = copy ((*_1).1: *mut T); _9 = copy _8 as usize (Transmute); + StorageDead(_8); _7 = Eq(copy _9, const 0_usize); + StorageDead(_9); goto -> bb3; } @@ -110,6 +112,7 @@ fn slice_iter_mut_next_back(_1: &mut std::slice::IterMut<'_, T>) -> Option<&mut } bb4: { + StorageLive(_21); StorageLive(_15); StorageLive(_17); StorageLive(_11); @@ -169,6 +172,7 @@ fn slice_iter_mut_next_back(_1: &mut std::slice::IterMut<'_, T>) -> Option<&mut StorageDead(_20); StorageDead(_15); _0 = Option::<&mut T>::Some(copy _21); + StorageDead(_21); goto -> bb11; } @@ -179,11 +183,7 @@ fn slice_iter_mut_next_back(_1: &mut std::slice::IterMut<'_, T>) -> Option<&mut bb11: { StorageDead(_7); - StorageDead(_21); StorageDead(_2); - StorageDead(_3); - StorageDead(_8); - StorageDead(_9); return; } } diff --git a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_next.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_next.PreCodegen.after.panic-unwind.mir index 5711b556203a..70e21435cc18 100644 --- a/tests/mir-opt/pre-codegen/slice_iter.slice_iter_next.PreCodegen.after.panic-unwind.mir +++ b/tests/mir-opt/pre-codegen/slice_iter.slice_iter_next.PreCodegen.after.panic-unwind.mir @@ -53,20 +53,18 @@ fn slice_iter_next(_1: &mut std::slice::Iter<'_, T>) -> Option<&T> { } bb0: { - StorageLive(_2); - StorageLive(_3); - StorageLive(_10); StorageLive(_11); - StorageLive(_4); - StorageLive(_13); StorageLive(_5); + StorageLive(_2); _2 = copy ((*_1).0: std::ptr::NonNull); + StorageLive(_3); _3 = copy ((*_1).1: *const T); switchInt(const ::IS_ZST) -> [0: bb1, otherwise: bb4]; } bb1: { StorageLive(_7); + StorageLive(_4); _4 = copy _3 as std::ptr::NonNull (Transmute); _5 = copy _2 as *mut T (Transmute); StorageLive(_6); @@ -77,6 +75,7 @@ fn slice_iter_next(_1: &mut std::slice::Iter<'_, T>) -> Option<&T> { } bb2: { + StorageDead(_4); StorageDead(_7); StorageLive(_9); StorageLive(_8); @@ -85,48 +84,57 @@ fn slice_iter_next(_1: &mut std::slice::Iter<'_, T>) -> Option<&T> { StorageDead(_8); ((*_1).0: std::ptr::NonNull) = move _9; StorageDead(_9); - goto -> bb7; - } - - bb3: { - _0 = const {transmute(0x0000000000000000): Option<&T>}; - StorageDead(_7); goto -> bb8; } + bb3: { + StorageDead(_4); + _0 = const {transmute(0x0000000000000000): Option<&T>}; + StorageDead(_7); + goto -> bb6; + } + bb4: { + StorageLive(_10); _10 = copy _3 as usize (Transmute); - switchInt(copy _10) -> [0: bb5, otherwise: bb6]; + switchInt(copy _10) -> [0: bb5, otherwise: bb7]; } bb5: { _0 = const {transmute(0x0000000000000000): Option<&T>}; - goto -> bb8; + StorageDead(_10); + goto -> bb6; } bb6: { - _11 = SubUnchecked(copy _10, const 1_usize); - ((*_1).1: *const T) = copy _11 as *const T (Transmute); - goto -> bb7; + StorageDead(_3); + StorageDead(_2); + goto -> bb9; } bb7: { + _11 = SubUnchecked(copy _10, const 1_usize); + ((*_1).1: *const T) = copy _11 as *const T (Transmute); + StorageDead(_10); + goto -> bb8; + } + + bb8: { + StorageLive(_13); StorageLive(_12); _12 = copy _2 as *const T (Transmute); _13 = &(*_12); StorageDead(_12); _0 = Option::<&T>::Some(copy _13); - goto -> bb8; - } - - bb8: { - StorageDead(_5); StorageDead(_13); - StorageDead(_4); - StorageDead(_11); - StorageDead(_10); StorageDead(_3); StorageDead(_2); + goto -> bb9; + } + + bb9: { + StorageDead(_5); + StorageDead(_11); return; } } diff --git a/tests/mir-opt/pre-codegen/transmutes.forget_at_home.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/transmutes.forget_at_home.PreCodegen.after.mir new file mode 100644 index 000000000000..5fc28fddedf8 --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.forget_at_home.PreCodegen.after.mir @@ -0,0 +1,20 @@ +// MIR for `forget_at_home` after PreCodegen + +fn forget_at_home(_1: String) -> () { + debug x => _1; + let mut _0: (); + scope 1 (inlined transmute_prefix::) { + scope 2 { + } + scope 3 { + scope 4 (inlined transmute_neo::, ()>) { + } + } + scope 5 (inlined transmute_neo::>) { + } + } + + bb0: { + return; + } +} diff --git a/tests/mir-opt/pre-codegen/transmutes.neo_to_cast.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/transmutes.neo_to_cast.PreCodegen.after.mir new file mode 100644 index 000000000000..6d6b1775d05b --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.neo_to_cast.PreCodegen.after.mir @@ -0,0 +1,13 @@ +// MIR for `neo_to_cast` after PreCodegen + +fn neo_to_cast(_1: f32) -> i32 { + debug x => _1; + let mut _0: i32; + scope 1 (inlined transmute_neo::) { + } + + bb0: { + _0 = copy _1 as i32 (Transmute); + return; + } +} diff --git a/tests/mir-opt/pre-codegen/transmutes.pad_for_alignment.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/transmutes.pad_for_alignment.PreCodegen.after.mir new file mode 100644 index 000000000000..100eebf0c244 --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.pad_for_alignment.PreCodegen.after.mir @@ -0,0 +1,29 @@ +// MIR for `pad_for_alignment` after PreCodegen + +fn pad_for_alignment(_1: u32) -> Align64 { + debug x => _1; + let mut _0: Align64; + scope 1 (inlined transmute_prefix::>) { + let _2: std::mem::ManuallyDrop; + let mut _3: std::mem::transmute_prefix::Transmute>; + scope 2 { + } + scope 3 { + scope 4 (inlined transmute_neo::>, Align64>) { + } + } + scope 5 (inlined transmute_neo::>) { + } + } + + bb0: { + StorageLive(_2); + _2 = copy _1 as std::mem::ManuallyDrop (Transmute); + StorageLive(_3); + _3 = transmute_prefix::Transmute::> { a: copy _2 }; + _0 = move _3 as Align64 (Transmute); + StorageDead(_3); + StorageDead(_2); + return; + } +} diff --git a/tests/mir-opt/pre-codegen/transmutes.prefix_of_array.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/transmutes.prefix_of_array.PreCodegen.after.mir new file mode 100644 index 000000000000..4050338e2418 --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.prefix_of_array.PreCodegen.after.mir @@ -0,0 +1,29 @@ +// MIR for `prefix_of_array` after PreCodegen + +fn prefix_of_array(_1: [u32; 4]) -> [u32; 2] { + debug x => _1; + let mut _0: [u32; 2]; + scope 1 (inlined transmute_prefix::<[u32; 4], [u32; 2]>) { + let _2: std::mem::transmute_prefix::Transmute<[u32; 4], [u32; 2]>; + let mut _3: std::mem::ManuallyDrop<[u32; 2]>; + scope 2 { + } + scope 3 { + scope 4 (inlined transmute_neo::, [u32; 2]>) { + } + } + scope 5 (inlined transmute_neo::<[u32; 4], ManuallyDrop<[u32; 4]>>) { + } + } + + bb0: { + StorageLive(_2); + _2 = copy _1 as std::mem::transmute_prefix::Transmute<[u32; 4], [u32; 2]> (Transmute); + StorageLive(_3); + _3 = move (_2.1: std::mem::ManuallyDrop<[u32; 2]>); + _0 = copy _3 as [u32; 2] (Transmute); + StorageDead(_3); + StorageDead(_2); + return; + } +} diff --git a/tests/mir-opt/pre-codegen/transmutes.prefix_to_cast.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/transmutes.prefix_to_cast.PreCodegen.after.mir new file mode 100644 index 000000000000..c0500fbae06f --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.prefix_to_cast.PreCodegen.after.mir @@ -0,0 +1,21 @@ +// MIR for `prefix_to_cast` after PreCodegen + +fn prefix_to_cast(_1: f32) -> i32 { + debug x => _1; + let mut _0: i32; + scope 1 (inlined transmute_prefix::) { + scope 2 { + } + scope 3 { + scope 4 (inlined transmute_neo::, i32>) { + } + } + scope 5 (inlined transmute_neo::>) { + } + } + + bb0: { + _0 = copy _1 as i32 (Transmute); + return; + } +} diff --git a/tests/mir-opt/pre-codegen/transmutes.rs b/tests/mir-opt/pre-codegen/transmutes.rs new file mode 100644 index 000000000000..4825e6079c2e --- /dev/null +++ b/tests/mir-opt/pre-codegen/transmutes.rs @@ -0,0 +1,50 @@ +//@ compile-flags: -O -Zmir-opt-level=2 + +#![crate_type = "lib"] +#![feature(transmute_neo)] +#![feature(transmute_prefix)] + +use std::mem::{transmute_neo, transmute_prefix}; + +// EMIT_MIR transmutes.neo_to_cast.PreCodegen.after.mir +pub fn neo_to_cast(x: f32) -> i32 { + // CHECK-LABEL: fn neo_to_cast + // CHECK: _0 = copy _1 as i32 (Transmute); + unsafe { transmute_neo(x) } +} + +// EMIT_MIR transmutes.prefix_to_cast.PreCodegen.after.mir +pub fn prefix_to_cast(x: f32) -> i32 { + // CHECK-LABEL: fn prefix_to_cast + // CHECK: _0 = copy _1 as i32 (Transmute); + unsafe { transmute_prefix(x) } +} + +// EMIT_MIR transmutes.prefix_of_array.PreCodegen.after.mir +pub fn prefix_of_array(x: [u32; 4]) -> [u32; 2] { + // CHECK-LABEL: fn prefix_of_array + // CHECK: _2 = copy _1 as {{.+}}::Transmute<[u32; 4], [u32; 2]> (Transmute); + // CHECK: _3 = move (_2.1: {{.+}}::ManuallyDrop<[u32; 2]>); + // CHECK: _0 = copy _3 as [u32; 2] (Transmute); + unsafe { transmute_prefix(x) } +} + +#[repr(C, align(64))] +struct Align64(T); + +// EMIT_MIR transmutes.pad_for_alignment.PreCodegen.after.mir +pub fn pad_for_alignment(x: u32) -> Align64 { + // CHECK-LABEL: fn pad_for_alignment + // CHECK: _2 = copy _1 as {{.+}}::ManuallyDrop (Transmute); + // CHECK: _3 = {{.+}}::Transmute::> { a: copy _2 }; + // CHECK: _0 = move _3 as Align64 (Transmute); + unsafe { transmute_prefix(x) } +} + +// EMIT_MIR transmutes.forget_at_home.PreCodegen.after.mir +pub fn forget_at_home(x: String) { + // CHECK-LABEL: fn forget_at_home + // CHECK: bb0: + // CHECK-NEXT: return; + unsafe { transmute_prefix(x) } +} diff --git a/tests/mir-opt/pre-codegen/try_identity.new.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/try_identity.new.PreCodegen.after.mir index baa01e28a941..6035f245c497 100644 --- a/tests/mir-opt/pre-codegen/try_identity.new.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/try_identity.new.PreCodegen.after.mir @@ -29,8 +29,10 @@ fn new(_1: Result) -> Result { } bb1: { + StorageLive(_3); _3 = move ((_1 as Ok).0: T); _4 = ControlFlow::::Continue(copy _3); + StorageDead(_3); _5 = move ((_4 as Continue).0: T); _0 = Result::::Ok(copy _5); StorageDead(_4); @@ -38,10 +40,14 @@ fn new(_1: Result) -> Result { } bb2: { + StorageLive(_6); _6 = move ((_1 as Err).0: E); _4 = ControlFlow::::Break(copy _6); + StorageDead(_6); + StorageLive(_7); _7 = move ((_4 as Break).0: E); _0 = Result::::Err(copy _7); + StorageDead(_7); StorageDead(_4); goto -> bb3; } diff --git a/tests/mir-opt/pre-codegen/try_identity.old.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/try_identity.old.PreCodegen.after.mir index 889e80d26e1c..aec51bfd8d74 100644 --- a/tests/mir-opt/pre-codegen/try_identity.old.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/try_identity.old.PreCodegen.after.mir @@ -19,14 +19,18 @@ fn old(_1: Result) -> Result { } bb1: { + StorageLive(_3); _3 = copy ((_1 as Ok).0: T); + StorageDead(_3); _0 = copy _1; goto -> bb3; } bb2: { + StorageLive(_4); _4 = copy ((_1 as Err).0: E); _0 = copy _1; + StorageDead(_4); goto -> bb3; } diff --git a/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.GVN.diff b/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.GVN.diff index 5b063e6762e0..78d58c6f60fa 100644 --- a/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.GVN.diff +++ b/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.GVN.diff @@ -40,9 +40,8 @@ } bb0: { -- StorageLive(_2); + StorageLive(_2); - StorageLive(_3); -+ nop; + nop; _3 = copy (*_1); - StorageLive(_8); @@ -97,8 +96,7 @@ StorageDead(_7); StorageDead(_6); StorageDead(_4); -- StorageDead(_2); -+ nop; + StorageDead(_2); return; } } diff --git a/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.PreCodegen.after.mir index c0f397866396..75543a53e286 100644 --- a/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/two_unwrap_unchecked.two_unwrap_unchecked.PreCodegen.after.mir @@ -35,12 +35,14 @@ fn two_unwrap_unchecked(_1: &Option) -> i32 { } bb0: { + StorageLive(_5); _2 = copy (*_1); _3 = discriminant(_2); _4 = Eq(copy _3, const 1_isize); assume(move _4); _5 = copy ((_2 as Some).0: i32); _0 = Add(copy _5, copy _5); + StorageDead(_5); return; } } diff --git a/tests/mir-opt/range/ssa_range.on_if.SsaRangePropagation.diff b/tests/mir-opt/range/ssa_range.on_if.SsaRangePropagation.diff index 2493e069edd4..d097ddf619f0 100644 --- a/tests/mir-opt/range/ssa_range.on_if.SsaRangePropagation.diff +++ b/tests/mir-opt/range/ssa_range.on_if.SsaRangePropagation.diff @@ -18,7 +18,7 @@ } bb0: { - nop; + StorageLive(_3); StorageLive(_4); _4 = copy _1; nop; @@ -56,7 +56,7 @@ } bb4: { - nop; + StorageDead(_3); return; } } diff --git a/tests/mir-opt/separate_const_switch.identity.JumpThreading.diff b/tests/mir-opt/separate_const_switch.identity.JumpThreading.diff index 10ad4ec75414..5bc79f76b370 100644 --- a/tests/mir-opt/separate_const_switch.identity.JumpThreading.diff +++ b/tests/mir-opt/separate_const_switch.identity.JumpThreading.diff @@ -41,8 +41,6 @@ bb0: { StorageLive(_2); StorageLive(_6); - StorageLive(_7); - StorageLive(_8); _6 = discriminant(_1); switchInt(move _6) -> [0: bb6, 1: bb5, otherwise: bb1]; } @@ -59,56 +57,58 @@ } bb3: { + StorageLive(_4); _4 = copy ((_2 as Break).0: std::result::Result); StorageLive(_10); StorageLive(_12); _10 = discriminant(_4); _12 = Eq(copy _10, const 1_isize); assume(move _12); + StorageLive(_11); _11 = copy ((_4 as Err).0: i32); _0 = Result::::Err(copy _11); + StorageDead(_11); StorageDead(_12); StorageDead(_10); + StorageDead(_4); StorageDead(_2); return; } bb4: { - StorageDead(_8); - StorageDead(_7); StorageDead(_6); _3 = discriminant(_2); switchInt(move _3) -> [0: bb2, 1: bb3, otherwise: bb1]; } bb5: { + StorageLive(_8); _8 = copy ((_1 as Err).0: i32); StorageLive(_9); _9 = Result::::Err(copy _8); _2 = ControlFlow::, i32>::Break(move _9); StorageDead(_9); + StorageDead(_8); - goto -> bb4; + goto -> bb7; } bb6: { + StorageLive(_7); _7 = copy ((_1 as Ok).0: i32); _2 = ControlFlow::, i32>::Continue(copy _7); + StorageDead(_7); - goto -> bb4; + goto -> bb8; + } + + bb7: { -+ StorageDead(_8); -+ StorageDead(_7); + StorageDead(_6); + _3 = discriminant(_2); + goto -> bb3; + } + + bb8: { -+ StorageDead(_8); -+ StorageDead(_7); + StorageDead(_6); + _3 = discriminant(_2); + goto -> bb2; diff --git a/tests/mir-opt/separate_const_switch.too_complex.JumpThreading.diff b/tests/mir-opt/separate_const_switch.too_complex.JumpThreading.diff index 794c28ab46da..ce76cf395abf 100644 --- a/tests/mir-opt/separate_const_switch.too_complex.JumpThreading.diff +++ b/tests/mir-opt/separate_const_switch.too_complex.JumpThreading.diff @@ -35,15 +35,19 @@ } bb2: { + StorageLive(_5); _5 = copy ((_1 as Err).0: usize); _2 = ControlFlow::::Break(copy _5); + StorageDead(_5); - goto -> bb4; + goto -> bb8; } bb3: { + StorageLive(_4); _4 = copy ((_1 as Ok).0: i32); _2 = ControlFlow::::Continue(copy _4); + StorageDead(_4); - goto -> bb4; + goto -> bb9; } @@ -62,8 +66,10 @@ } bb6: { + StorageLive(_7); _7 = copy ((_2 as Continue).0: i32); _0 = Option::::Some(copy _7); + StorageDead(_7); goto -> bb7; } diff --git a/tests/mir-opt/simplify_aggregate_to_copy_miscompile.foo.GVN.diff b/tests/mir-opt/simplify_aggregate_to_copy_miscompile.foo.GVN.diff index 54c11679f0c6..9d1c9079a246 100644 --- a/tests/mir-opt/simplify_aggregate_to_copy_miscompile.foo.GVN.diff +++ b/tests/mir-opt/simplify_aggregate_to_copy_miscompile.foo.GVN.diff @@ -30,8 +30,7 @@ } bb2: { -- StorageLive(_5); -+ nop; + StorageLive(_5); _5 = copy (((*_2) as Some).0: i32); StorageLive(_7); - _7 = Option::::None; @@ -44,8 +43,7 @@ - _0 = Option::::Some(move _8); + _0 = Option::::Some(copy _5); StorageDead(_8); -- StorageDead(_5); -+ nop; + StorageDead(_5); StorageDead(_2); return; } diff --git a/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-abort.diff b/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-abort.diff index dd21719adb65..98727b80ca12 100644 --- a/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-abort.diff +++ b/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-abort.diff @@ -34,7 +34,9 @@ } bb2: { + StorageLive(_6); _6 = copy (((_1.0: std::option::Option) as Some).0: u8); + StorageDead(_6); goto -> bb3; } diff --git a/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-unwind.diff b/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-unwind.diff index 6e50b615030f..12b0a7f4ba53 100644 --- a/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-unwind.diff +++ b/tests/mir-opt/simplify_locals_fixedpoint.foo.SimplifyLocals-final.panic-unwind.diff @@ -34,7 +34,9 @@ } bb2: { + StorageLive(_6); _6 = copy (((_1.0: std::option::Option) as Some).0: u8); + StorageDead(_6); goto -> bb3; } diff --git a/tests/mir-opt/simplify_match.main.GVN.panic-abort.diff b/tests/mir-opt/simplify_match.main.GVN.panic-abort.diff index 9e798cbcac0c..30c3b0bcfa1d 100644 --- a/tests/mir-opt/simplify_match.main.GVN.panic-abort.diff +++ b/tests/mir-opt/simplify_match.main.GVN.panic-abort.diff @@ -11,14 +11,12 @@ bb0: { StorageLive(_1); -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = const false; - _1 = copy _2; -- StorageDead(_2); -- switchInt(copy _1) -> [0: bb2, otherwise: bb1]; + _1 = const false; -+ nop; + StorageDead(_2); +- switchInt(copy _1) -> [0: bb2, otherwise: bb1]; + switchInt(const false) -> [0: bb2, otherwise: bb1]; } diff --git a/tests/mir-opt/simplify_match.main.GVN.panic-unwind.diff b/tests/mir-opt/simplify_match.main.GVN.panic-unwind.diff index e243ff45ab0b..7923d3210d83 100644 --- a/tests/mir-opt/simplify_match.main.GVN.panic-unwind.diff +++ b/tests/mir-opt/simplify_match.main.GVN.panic-unwind.diff @@ -11,14 +11,12 @@ bb0: { StorageLive(_1); -- StorageLive(_2); -+ nop; + StorageLive(_2); _2 = const false; - _1 = copy _2; -- StorageDead(_2); -- switchInt(copy _1) -> [0: bb2, otherwise: bb1]; + _1 = const false; -+ nop; + StorageDead(_2); +- switchInt(copy _1) -> [0: bb2, otherwise: bb1]; + switchInt(const false) -> [0: bb2, otherwise: bb1]; } diff --git a/tests/pretty/delegation-inherit-attributes.pp b/tests/pretty/delegation-inherit-attributes.pp index 2db27f3598cd..242e7161aa84 100644 --- a/tests/pretty/delegation-inherit-attributes.pp +++ b/tests/pretty/delegation-inherit-attributes.pp @@ -1,15 +1,14 @@ -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [incomplete_features]}])] -#![attr = Feature([fn_delegation#0])] -extern crate std; -#[attr = PreludeImport] -use std::prelude::rust_2021::*; //@ edition:2021 //@ aux-crate:to_reuse_functions=to-reuse-functions.rs //@ pretty-mode:hir //@ pretty-compare-only //@ pp-exact:delegation-inherit-attributes.pp +#![allow(incomplete_features)] +#![attr = Feature([fn_delegation#0])] +extern crate std; +#[attr = PreludeImport] +use std::prelude::rust_2021::*; extern crate to_reuse_functions; diff --git a/tests/pretty/delegation-inline-attribute.pp b/tests/pretty/delegation-inline-attribute.pp index 4828f2e6c80f..125ed1c29826 100644 --- a/tests/pretty/delegation-inline-attribute.pp +++ b/tests/pretty/delegation-inline-attribute.pp @@ -1,13 +1,12 @@ -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [incomplete_features]}])] -#![attr = Feature([fn_delegation#0])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; //@ pretty-compare-only //@ pretty-mode:hir //@ pp-exact:delegation-inline-attribute.pp +#![allow(incomplete_features)] +#![attr = Feature([fn_delegation#0])] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; mod to_reuse { fn foo(x: usize) -> usize { x } diff --git a/tests/pretty/hir-delegation.pp b/tests/pretty/hir-delegation.pp index 5337dd2e96df..28bb49458ce1 100644 --- a/tests/pretty/hir-delegation.pp +++ b/tests/pretty/hir-delegation.pp @@ -1,13 +1,12 @@ -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [incomplete_features]}])] -#![attr = Feature([fn_delegation#0])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; //@ pretty-compare-only //@ pretty-mode:hir //@ pp-exact:hir-delegation.pp +#![allow(incomplete_features)] +#![attr = Feature([fn_delegation#0])] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; fn b(e: C) { } diff --git a/tests/pretty/hir-lifetimes.pp b/tests/pretty/hir-lifetimes.pp index 07ac4ccfdd45..c35a40eed0c5 100644 --- a/tests/pretty/hir-lifetimes.pp +++ b/tests/pretty/hir-lifetimes.pp @@ -1,19 +1,13 @@ -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [unused_imports, unused_variables, unused_visibilities, -unused_assignments, dead_code, unused_mut, unreachable_code, -unreachable_patterns, unused_must_use, unused_unsafe, path_statements, -unused_attributes, unused_macros, unused_macro_rules, unused_allocation, -unused_doc_comments, unused_extern_crates, unused_features, unused_labels, -unused_parens, unused_braces, redundant_semicolons, map_unit_fn]}])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; //@ pretty-compare-only //@ pretty-mode:hir //@ pp-exact:hir-lifetimes.pp // This tests the pretty-printing of lifetimes in lots of ways. +#![allow(unused)] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; struct Foo<'a> { x: &'a u32, diff --git a/tests/pretty/pin-ergonomics-hir.pp b/tests/pretty/pin-ergonomics-hir.pp index 5b024bfff3b5..6c9dec2bfb1f 100644 --- a/tests/pretty/pin-ergonomics-hir.pp +++ b/tests/pretty/pin-ergonomics-hir.pp @@ -1,13 +1,12 @@ -#![attr = Feature([pin_ergonomics#0])] -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [dead_code, incomplete_features]}])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; //@ pretty-compare-only //@ pretty-mode:hir //@ pp-exact:pin-ergonomics-hir.pp +#![allow(dead_code, incomplete_features)] +#![attr = Feature([pin_ergonomics#0])] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; use std::pin::Pin; diff --git a/tests/run-make/c-link-to-rust-va-list-fn/checkrust.rs b/tests/run-make/c-link-to-rust-va-list-fn/checkrust.rs index c522ac46d918..109fbb1c6203 100644 --- a/tests/run-make/c-link-to-rust-va-list-fn/checkrust.rs +++ b/tests/run-make/c-link-to-rust-va-list-fn/checkrust.rs @@ -30,17 +30,17 @@ unsafe fn compare_c_str(ptr: *const c_char, val: &CStr) -> bool { continue_if!(ap.arg::() == '4' as c_int); continue_if!(ap.arg::() == ';' as c_int); continue_if!(ap.arg::() == 0x32); - continue_if!(ap.arg::() == 0x10000001); + continue_if!(ap.arg::() == 0x10000001); continue_if!(compare_c_str(ap.arg::<*const c_char>(), c"Valid!")); 0 } #[unsafe(no_mangle)] pub unsafe extern "C" fn check_list_2(mut ap: VaList) -> usize { - continue_if!(ap.arg::() == 3.14f64); + continue_if!(ap.arg::() == 3.14); continue_if!(ap.arg::() == 12); continue_if!(ap.arg::() == 'a' as c_int); - continue_if!(ap.arg::() == 6.28f64); + continue_if!(ap.arg::() == 6.28); continue_if!(compare_c_str(ap.arg::<*const c_char>(), c"Hello")); continue_if!(ap.arg::() == 42); continue_if!(compare_c_str(ap.arg::<*const c_char>(), c"World")); @@ -49,7 +49,7 @@ unsafe fn compare_c_str(ptr: *const c_char, val: &CStr) -> bool { #[unsafe(no_mangle)] pub unsafe extern "C" fn check_list_copy_0(mut ap: VaList) -> usize { - continue_if!(ap.arg::() == 6.28f64); + continue_if!(ap.arg::() == 6.28); continue_if!(ap.arg::() == 16); continue_if!(ap.arg::() == 'A' as c_int); continue_if!(compare_c_str(ap.arg::<*const c_char>(), c"Skip Me!")); @@ -66,7 +66,7 @@ unsafe fn compare_c_str(ptr: *const c_char, val: &CStr) -> bool { #[unsafe(no_mangle)] pub unsafe extern "C" fn check_varargs_1(_: c_int, mut ap: ...) -> usize { - continue_if!(ap.arg::() == 3.14f64); + continue_if!(ap.arg::() == 3.14); continue_if!(ap.arg::() == 12); continue_if!(ap.arg::() == 'A' as c_int); continue_if!(ap.arg::() == 1); @@ -156,7 +156,7 @@ extern "C" fn run_test_variadic() -> usize { #[unsafe(no_mangle)] extern "C" fn run_test_va_list_by_value() -> usize { - unsafe extern "C" fn helper(mut ap: ...) -> usize { + unsafe extern "C" fn helper(ap: ...) -> usize { unsafe { test_va_list_by_value(ap) } } diff --git a/tests/run-make/c-link-to-rust-va-list-fn/test.c b/tests/run-make/c-link-to-rust-va-list-fn/test.c index 2bb93c0b5d0e..b368302326c7 100644 --- a/tests/run-make/c-link-to-rust-va-list-fn/test.c +++ b/tests/run-make/c-link-to-rust-va-list-fn/test.c @@ -32,7 +32,7 @@ int test_rust(size_t (*fn)(va_list), ...) { int main(int argc, char* argv[]) { assert(test_rust(check_list_0, 0x01LL, 0x02, 0x03LL) == 0); - assert(test_rust(check_list_1, -1, 'A', '4', ';', 0x32, 0x10000001, "Valid!") == 0); + assert(test_rust(check_list_1, -1, 'A', '4', ';', 0x32, (int32_t)0x10000001, "Valid!") == 0); assert(test_rust(check_list_2, 3.14, 12l, 'a', 6.28, "Hello", 42, "World") == 0); diff --git a/tests/run-make/duplicate-profiler-builtins/rmake.rs b/tests/run-make/duplicate-profiler-builtins/rmake.rs index 2dc53d0ee59d..1566bc667076 100644 --- a/tests/run-make/duplicate-profiler-builtins/rmake.rs +++ b/tests/run-make/duplicate-profiler-builtins/rmake.rs @@ -2,6 +2,7 @@ // together without getting an error about duplicate profiler_builtins. //@ needs-profiler-runtime +//@ needs-dynamic-linking use run_make_support::{dynamic_lib_name, rustc}; diff --git a/tests/run-make/naked-dead-code-elimination/main.rs b/tests/run-make/naked-dead-code-elimination/main.rs new file mode 100644 index 000000000000..5df2691e5b44 --- /dev/null +++ b/tests/run-make/naked-dead-code-elimination/main.rs @@ -0,0 +1,48 @@ +#![feature(cfg_target_object_format)] +use std::arch::naked_asm; + +#[unsafe(naked)] +#[unsafe(no_mangle)] +extern "C" fn used() { + naked_asm!("ret") +} + +#[unsafe(no_mangle)] +extern "C" fn used_clothed() -> i32 { + 41 +} + +pub fn main() { + std::hint::black_box(used()); + std::hint::black_box(used_clothed()); +} + +#[unsafe(no_mangle)] +extern "C" fn unused_clothed() -> i32 { + 42 +} + +#[unsafe(naked)] +#[unsafe(no_mangle)] +extern "C" fn unused() { + naked_asm!("ret") +} + +#[unsafe(naked)] +#[unsafe(link_section = cfg_select!( + target_object_format = "mach-o" => "__TEXT,foobar", + _ => ".foobar", +))] +#[unsafe(no_mangle)] +extern "C" fn unused_link_section() { + naked_asm!("ret") +} + +#[unsafe(link_section = cfg_select!( + target_object_format = "mach-o" => "__TEXT,baz", + _ => ".baz", +))] +#[unsafe(no_mangle)] +extern "C" fn unused_link_section_clothed() -> i32 { + 43 +} diff --git a/tests/run-make/naked-dead-code-elimination/rmake.rs b/tests/run-make/naked-dead-code-elimination/rmake.rs new file mode 100644 index 000000000000..1be22de367c9 --- /dev/null +++ b/tests/run-make/naked-dead-code-elimination/rmake.rs @@ -0,0 +1,39 @@ +//@ ignore-cross-compile +//@ needs-asm-support + +use run_make_support::symbols::object_contains_any_symbol; +use run_make_support::{bin_name, rustc}; + +fn main() { + let bin = bin_name("main"); + + rustc().input("main.rs").opt().function_sections(false).run(); + + // Check that the naked symbol is eliminated when the "clothed" one is. + + assert_eq!( + object_contains_any_symbol(&bin, &["unused_clothed"]), + object_contains_any_symbol(&bin, &["unused"]) + ); + + assert_eq!( + object_contains_any_symbol(&bin, &["unused_link_section_clothed"]), + object_contains_any_symbol(&bin, &["unused_link_section"]) + ); + + // --- + + rustc().input("main.rs").opt().function_sections(true).run(); + + // Check that the naked symbol is eliminated when the "clothed" one is. + + assert_eq!( + object_contains_any_symbol(&bin, &["unused_clothed"]), + object_contains_any_symbol(&bin, &["unused"]) + ); + + assert_eq!( + object_contains_any_symbol(&bin, &["unused_link_section_clothed"]), + object_contains_any_symbol(&bin, &["unused_link_section"]) + ); +} diff --git a/tests/run-make/rustdoc-default-output/output-default.stdout b/tests/run-make/rustdoc-default-output/output-default.stdout index bc3a67a1ebcd..7202ed71a2a8 100644 --- a/tests/run-make/rustdoc-default-output/output-default.stdout +++ b/tests/run-make/rustdoc-default-output/output-default.stdout @@ -160,6 +160,9 @@ Options: rustdoc will emit a hard error. --remap-path-prefix FROM=TO Remap source names in compiler messages + --remap-path-scope [macro,diagnostics,debuginfo,coverage,object,all] + Defines which scopes of paths should be remapped by + `--remap-path-prefix` --show-type-layout Include the memory layout of types in the docs --no-capture Don't capture stdout and stderr of tests diff --git a/tests/run-make/rustdoc-dep-info/example.md b/tests/run-make/rustdoc-dep-info/example.md new file mode 100644 index 000000000000..b4970b4bc3cf --- /dev/null +++ b/tests/run-make/rustdoc-dep-info/example.md @@ -0,0 +1,3 @@ +% My Example + +First and only paragraph. diff --git a/tests/run-make/rustdoc-dep-info/index-page.md b/tests/run-make/rustdoc-dep-info/index-page.md new file mode 100644 index 000000000000..95fa11ed0b76 --- /dev/null +++ b/tests/run-make/rustdoc-dep-info/index-page.md @@ -0,0 +1,3 @@ +% Index page + +Index page diff --git a/tests/run-make/rustdoc-dep-info/rmake.rs b/tests/run-make/rustdoc-dep-info/rmake.rs index 11901c97fd6a..233225fde869 100644 --- a/tests/run-make/rustdoc-dep-info/rmake.rs +++ b/tests/run-make/rustdoc-dep-info/rmake.rs @@ -3,7 +3,7 @@ //@ needs-target-std -use run_make_support::assertion_helpers::assert_contains; +use run_make_support::assertion_helpers::{assert_contains, assert_not_contains}; use run_make_support::{path, rfs, rustdoc}; fn main() { @@ -19,6 +19,7 @@ fn main() { .arg("--markdown-after-content=after.md") .arg("--extend-css=extend.css") .arg("--theme=theme.css") + .arg("--index-page=index-page.md") .emit("dep-info") .run(); @@ -31,6 +32,7 @@ fn main() { assert_contains(&content, "before.html:"); assert_contains(&content, "extend.css:"); assert_contains(&content, "theme.css:"); + assert_contains(&content, "index-page.md:"); // Now we check that we can provide a file name to the `dep-info` argument. rustdoc().input("lib.rs").arg("-Zunstable-options").emit("dep-info=bla.d").run(); @@ -58,4 +60,40 @@ fn main() { assert!(!path("precedence1.d").exists()); assert!(!path("-").exists()); // `-` shouldn't be treated as a file path assert!(!result.stdout().is_empty()); // Something emitted to stdout + + // test --emit=dep-info combined with plain markdown input + rustdoc().input("example.md").arg("-Zunstable-options").emit("dep-info").run(); + let content = rfs::read_to_string("doc/example.d"); + assert_contains(&content, "example.md:"); + assert_not_contains(&content, "lib.rs:"); + assert_not_contains(&content, "foo.rs:"); + assert_not_contains(&content, "bar.rs:"); + assert_not_contains(&content, "doc.md:"); + assert_not_contains(&content, "after.md:"); + assert_not_contains(&content, "before.html:"); + assert_not_contains(&content, "extend.css:"); + assert_not_contains(&content, "theme.css:"); + + // combine --emit=dep-info=filename with plain markdown input + rustdoc() + .input("example.md") + .arg("-Zunstable-options") + .arg("--html-before-content=before.html") + .arg("--markdown-after-content=after.md") + .arg("--extend-css=extend.css") + .arg("--theme=theme.css") + .arg("--index-page=index-page.md") + .emit("dep-info=example.d") + .run(); + let content = rfs::read_to_string("example.d"); + assert_contains(&content, "example.md:"); + assert_not_contains(&content, "lib.rs:"); + assert_not_contains(&content, "foo.rs:"); + assert_not_contains(&content, "bar.rs:"); + assert_not_contains(&content, "doc.md:"); + assert_contains(&content, "after.md:"); + assert_contains(&content, "before.html:"); + assert_contains(&content, "extend.css:"); + assert_contains(&content, "theme.css:"); + assert_contains(&content, "index-page.md:"); } diff --git a/tests/run-make/simd-ffi/simd.rs b/tests/run-make/simd-ffi/simd.rs index 1cd961ff87e7..3f12dabdb65e 100644 --- a/tests/run-make/simd-ffi/simd.rs +++ b/tests/run-make/simd-ffi/simd.rs @@ -35,7 +35,7 @@ pub fn foo(x: f32x4) -> f32x4 { fn integer(a: i32x4, b: i32x4) -> i32x4; // vmaxq_s32 #[cfg(target_arch = "aarch64")] - #[link_name = "llvm.aarch64.neon.maxs.v4i32"] + #[link_name = "llvm.aarch64.neon.smax.v4i32"] fn integer(a: i32x4, b: i32x4) -> i32x4; // Use a generic LLVM intrinsic to do type checking on other platforms diff --git a/tests/rustdoc-gui/copy-path.goml b/tests/rustdoc-gui/copy-path.goml index e8766688f8d5..61e63d7822c7 100644 --- a/tests/rustdoc-gui/copy-path.goml +++ b/tests/rustdoc-gui/copy-path.goml @@ -18,3 +18,19 @@ assert-size: ("#copy-path.clicked", {"width": |width|, "height": |height|}) wait-for: "#copy-path:not(.clicked)" // We check that the size is still the same. assert-size: ("#copy-path:not(.clicked)", {"width": |width|, "height": |height|}) + +// Check the path for a module. +go-to: "file://" + |DOC_PATH| + "/test_docs/foreign_impl_order/index.html" +click: "#copy-path" +// We wait for the new text to appear. +wait-for: "#copy-path.clicked" +// We check that the clipboard value is the expected one. +assert-clipboard: "test_docs::foreign_impl_order" + +// Check the path for the crate. +go-to: "file://" + |DOC_PATH| + "/test_docs/index.html" +click: "#copy-path" +// We wait for the new text to appear. +wait-for: "#copy-path.clicked" +// We check that the clipboard value is the expected one. +assert-clipboard: "test_docs" diff --git a/tests/rustdoc-html/doc-cfg/all-targets.rs b/tests/rustdoc-html/doc-cfg/all-targets.rs index 4db41e1f8344..048d0d4c73d2 100644 --- a/tests/rustdoc-html/doc-cfg/all-targets.rs +++ b/tests/rustdoc-html/doc-cfg/all-targets.rs @@ -32,8 +32,8 @@ pub fn foo() {} //@ has all_targets/fn.bar.html \ // '//*[@id="main-content"]/*[@class="item-info"]/*[@class="stab portability"]' \ -// 'Available on AArch64 or AMG GPU or ARM or ARM64EC or AVR or BPF or C-SKY or \ -// Hexagon or LoongArch64 or LoongArch32 or Motorola 680x0 or MIPS or MIPS release \ +// 'Available on AArch64 or AMD GPU or ARM or ARM64EC or AVR or BPF or C-SKY or \ +// Hexagon or LoongArch32 or LoongArch64 or Motorola 680x0 or MIPS or MIPS release \ // 6 or MIPS-64 or MIPS-64 release 6 or MSP430 or NVidia GPU or PowerPC or \ // PowerPC64 or RISC-V RV32 or RISC-V RV64 or s390x or SPARC or SPARC-64 or SPIR-V \ // or WebAssembly or WebAssembly or x86 or x86-64 or Xtensa or \ diff --git a/tests/rustdoc-html/reexport/type-alias-reexport.rs b/tests/rustdoc-html/reexport/type-alias-reexport.rs new file mode 100644 index 000000000000..1bcdff88e22c --- /dev/null +++ b/tests/rustdoc-html/reexport/type-alias-reexport.rs @@ -0,0 +1,34 @@ +// Regression test for . +// This test ensures that auto-generated and explicit `doc(cfg)` attributes are correctly +// preserved for locally re-exported type aliases. + +//@ compile-flags: --cfg feature="foo" + +#![crate_name = "foo"] +#![feature(doc_cfg)] + +mod inner { + #[cfg(feature = "foo")] + pub type One = u32; + + #[doc(cfg(feature = "foo"))] + pub type Two = u32; +} + +//@ has 'foo/index.html' +// There should be two items in the type aliases table. +//@ count - '//*[@class="item-table"]/dt' 2 +// Both of them should have the portability badge in the module index. +//@ count - '//*[@class="item-table"]/dt/*[@class="stab portability"]' 2 + +//@ has 'foo/type.One.html' +// Check that the individual type page has the portability badge. +//@ count - '//*[@id="main-content"]/*[@class="item-info"]/*[@class="stab portability"]' 1 +//@ has - '//*[@id="main-content"]/*[@class="item-info"]/*[@class="stab portability"]' 'foo' + +//@ has 'foo/type.Two.html' +// Check the explicit doc(cfg) type page as well. +//@ count - '//*[@id="main-content"]/*[@class="item-info"]/*[@class="stab portability"]' 1 +//@ has - '//*[@id="main-content"]/*[@class="item-info"]/*[@class="stab portability"]' 'foo' + +pub use self::inner::{One, Two}; diff --git a/tests/rustdoc-html/unicode.rs b/tests/rustdoc-html/unicode.rs new file mode 100644 index 000000000000..a961f178ec3b --- /dev/null +++ b/tests/rustdoc-html/unicode.rs @@ -0,0 +1,10 @@ +#![crate_name = "unicode"] + +pub struct Foo; + +impl Foo { + //@ has unicode/struct.Foo.html //a/@href "#%C3%BA" + //@ !has unicode/struct.Foo.html //a/@href "#ú" + /// # ú + pub fn foo() {} +} diff --git a/tests/rustdoc-ui/doc-cfg-2.stderr b/tests/rustdoc-ui/doc-cfg-2.stderr index a842cbc40288..164e755de8ad 100644 --- a/tests/rustdoc-ui/doc-cfg-2.stderr +++ b/tests/rustdoc-ui/doc-cfg-2.stderr @@ -4,7 +4,7 @@ warning: unexpected `cfg` condition name: `foo` LL | #[doc(cfg(foo), cfg(bar))] | ^^^ | - = help: expected names are: `FALSE` and `test` and 31 more + = help: expected names are: `FALSE` and `test` and 32 more = help: to expect this configuration use `--check-cfg=cfg(foo)` = note: see for more information about checking conditional configuration = note: `#[warn(unexpected_cfgs)]` on by default diff --git a/tests/rustdoc-ui/doc-cfg.stderr b/tests/rustdoc-ui/doc-cfg.stderr index db525ca7a807..f3af95528b2d 100644 --- a/tests/rustdoc-ui/doc-cfg.stderr +++ b/tests/rustdoc-ui/doc-cfg.stderr @@ -4,7 +4,7 @@ error[E0805]: malformed `doc` attribute input LL | #[doc(cfg(), cfg(foo, bar))] | ^^^^^^^^^--^^^^^^^^^^^^^^^^^ | | - | expected a single argument here + | expected an argument here | help: if the function should be disabled, use `#[cfg(false)]` | @@ -36,7 +36,7 @@ error[E0805]: malformed `doc` attribute input LL | #[doc(cfg())] | ^^^^^^^^^--^^ | | - | expected a single argument here + | expected an argument here | help: if the function should be disabled, use `#[cfg(false)]` | diff --git a/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.fixed b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.fixed new file mode 100644 index 000000000000..75e2398e64c5 --- /dev/null +++ b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.fixed @@ -0,0 +1,17 @@ +//@ run-rustfix + +// There was a logic error in `redundant_explicit_links` that caused the lint +// to skip all remaining links once it skipped a link containing inline markups. +// This test asserts that the lint continues after skipping such links. + +#![deny(rustdoc::redundant_explicit_links)] + +/// [Option] +///~^ ERROR redundant explicit link target +/// +/// [**u8**](u8) +/// This link should not lint. +/// +/// [Result] +///~^ ERROR redundant explicit link target +pub fn func() {} diff --git a/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.rs b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.rs new file mode 100644 index 000000000000..0c39ad8f1801 --- /dev/null +++ b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.rs @@ -0,0 +1,17 @@ +//@ run-rustfix + +// There was a logic error in `redundant_explicit_links` that caused the lint +// to skip all remaining links once it skipped a link containing inline markups. +// This test asserts that the lint continues after skipping such links. + +#![deny(rustdoc::redundant_explicit_links)] + +/// [Option][Option] +///~^ ERROR redundant explicit link target +/// +/// [**u8**](u8) +/// This link should not lint. +/// +/// [Result][Result] +///~^ ERROR redundant explicit link target +pub fn func() {} diff --git a/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.stderr b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.stderr new file mode 100644 index 000000000000..61f4ee584da8 --- /dev/null +++ b/tests/rustdoc-ui/lints/redundant_explicit_links-some-skipped.stderr @@ -0,0 +1,39 @@ +error: redundant explicit link target + --> $DIR/redundant_explicit_links-some-skipped.rs:9:14 + | +LL | /// [Option][Option] + | ------ ^^^^^^ explicit target is redundant + | | + | because label contains path that resolves to same destination + | + = note: when a link's destination is not specified, + the label is used to resolve intra-doc links +note: the lint level is defined here + --> $DIR/redundant_explicit_links-some-skipped.rs:7:9 + | +LL | #![deny(rustdoc::redundant_explicit_links)] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +help: remove explicit link target + | +LL - /// [Option][Option] +LL + /// [Option] + | + +error: redundant explicit link target + --> $DIR/redundant_explicit_links-some-skipped.rs:15:14 + | +LL | /// [Result][Result] + | ------ ^^^^^^ explicit target is redundant + | | + | because label contains path that resolves to same destination + | + = note: when a link's destination is not specified, + the label is used to resolve intra-doc links +help: remove explicit link target + | +LL - /// [Result][Result] +LL + /// [Result] + | + +error: aborting due to 2 previous errors + diff --git a/tests/rustdoc-ui/lints/redundant_explicit_links-with-title.rs b/tests/rustdoc-ui/lints/redundant_explicit_links-with-title.rs new file mode 100644 index 000000000000..01b84563ce55 --- /dev/null +++ b/tests/rustdoc-ui/lints/redundant_explicit_links-with-title.rs @@ -0,0 +1,15 @@ +//@ check-pass + +#![deny(rustdoc::redundant_explicit_links)] + +/// [drop](drop "This function is not magic") +/// +/// This link should not lint, because it specifies a link title, and it is +/// not possible to remove the explicit link without also removing the title. +/// +/// [Vec][vec] +/// +/// [vec]: std::vec::Vec "A contiguous growable array type" +/// +/// This also applies to reference-style links. +pub fn func() {} diff --git a/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.rs b/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.rs deleted file mode 100644 index 6fe663518ad6..000000000000 --- a/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.rs +++ /dev/null @@ -1,12 +0,0 @@ -// compile-args: --crate-type lib - -// This file does not emit the rename warnings -// due to compilation aborting before we emit delayed lints - -#![deny(broken_intra_doc_links)] -//! [x] -//~^ ERROR unresolved link - -#![deny(rustdoc::non_autolinks)] -//! http://example.com -//~^ ERROR not a hyperlink diff --git a/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.stderr b/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.stderr deleted file mode 100644 index 484566587d9e..000000000000 --- a/tests/rustdoc-ui/lints/renamed-lint-still-applies-2.stderr +++ /dev/null @@ -1,32 +0,0 @@ -error: unresolved link to `x` - --> $DIR/renamed-lint-still-applies-2.rs:7:6 - | -LL | //! [x] - | ^ no item named `x` in scope - | - = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]` -note: the lint level is defined here - --> $DIR/renamed-lint-still-applies-2.rs:6:9 - | -LL | #![deny(broken_intra_doc_links)] - | ^^^^^^^^^^^^^^^^^^^^^^ - -error: this URL is not a hyperlink - --> $DIR/renamed-lint-still-applies-2.rs:11:5 - | -LL | //! http://example.com - | ^^^^^^^^^^^^^^^^^^ - | - = note: bare URLs are not automatically turned into clickable links -note: the lint level is defined here - --> $DIR/renamed-lint-still-applies-2.rs:10:9 - | -LL | #![deny(rustdoc::non_autolinks)] - | ^^^^^^^^^^^^^^^^^^^^^^ -help: use an automatic link instead - | -LL | //! - | + + - -error: aborting due to 2 previous errors - diff --git a/tests/rustdoc-ui/lints/renamed-lint-still-applies.rs b/tests/rustdoc-ui/lints/renamed-lint-still-applies.rs index 8dded5460f12..a4d3a4b49711 100644 --- a/tests/rustdoc-ui/lints/renamed-lint-still-applies.rs +++ b/tests/rustdoc-ui/lints/renamed-lint-still-applies.rs @@ -1,7 +1,10 @@ -//@ check-pass // compile-args: --crate-type lib #![deny(broken_intra_doc_links)] //~^ WARNING renamed to `rustdoc::broken_intra_doc_links` +//! [x] +//~^ ERROR unresolved link #![deny(rustdoc::non_autolinks)] //~^ WARNING renamed to `rustdoc::bare_urls` +//! http://example.com +//~^ ERROR not a hyperlink diff --git a/tests/rustdoc-ui/lints/renamed-lint-still-applies.stderr b/tests/rustdoc-ui/lints/renamed-lint-still-applies.stderr index b9dde5fbc7fe..88807dfb495d 100644 --- a/tests/rustdoc-ui/lints/renamed-lint-still-applies.stderr +++ b/tests/rustdoc-ui/lints/renamed-lint-still-applies.stderr @@ -1,5 +1,5 @@ warning: lint `broken_intra_doc_links` has been renamed to `rustdoc::broken_intra_doc_links` - --> $DIR/renamed-lint-still-applies.rs:3:9 + --> $DIR/renamed-lint-still-applies.rs:2:9 | LL | #![deny(broken_intra_doc_links)] | ^^^^^^^^^^^^^^^^^^^^^^ help: use the new name: `rustdoc::broken_intra_doc_links` @@ -7,10 +7,40 @@ LL | #![deny(broken_intra_doc_links)] = note: `#[warn(renamed_and_removed_lints)]` on by default warning: lint `rustdoc::non_autolinks` has been renamed to `rustdoc::bare_urls` - --> $DIR/renamed-lint-still-applies.rs:6:9 + --> $DIR/renamed-lint-still-applies.rs:7:9 | LL | #![deny(rustdoc::non_autolinks)] | ^^^^^^^^^^^^^^^^^^^^^^ help: use the new name: `rustdoc::bare_urls` -warning: 2 warnings emitted +error: unresolved link to `x` + --> $DIR/renamed-lint-still-applies.rs:4:6 + | +LL | //! [x] + | ^ no item named `x` in scope + | + = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]` +note: the lint level is defined here + --> $DIR/renamed-lint-still-applies.rs:2:9 + | +LL | #![deny(broken_intra_doc_links)] + | ^^^^^^^^^^^^^^^^^^^^^^ + +error: this URL is not a hyperlink + --> $DIR/renamed-lint-still-applies.rs:9:5 + | +LL | //! http://example.com + | ^^^^^^^^^^^^^^^^^^ + | + = note: bare URLs are not automatically turned into clickable links +note: the lint level is defined here + --> $DIR/renamed-lint-still-applies.rs:7:9 + | +LL | #![deny(rustdoc::non_autolinks)] + | ^^^^^^^^^^^^^^^^^^^^^^ +help: use an automatic link instead + | +LL | //! + | + + + +error: aborting due to 2 previous errors; 2 warnings emitted diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.rs b/tests/rustdoc-ui/remap-path-prefix-doctest.rs new file mode 100644 index 000000000000..34fff98d5caa --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.rs @@ -0,0 +1,22 @@ +// This test checks the output of remapping with `--remap-path-prefix` and +// `--remap-path-scope` with a doctest. + +//@ failure-status: 101 +//@ rustc-env:RUST_BACKTRACE=0 +//@ normalize-stdout: "finished in \d+\.\d+s" -> "finished in $$TIME" + +//@ revisions: with-diag-scope with-macro-scope with-object-scope with-doc-scope +//@ revisions: without-scope + +//@ compile-flags:--test --test-args --test-threads=1 +//@ compile-flags:-Z unstable-options --remap-path-prefix={{src-base}}=remapped_path + +//@[with-diag-scope] compile-flags: -Zunstable-options --remap-path-scope=diagnostics +//@[with-macro-scope] compile-flags: -Zunstable-options --remap-path-scope=macro +//@[with-object-scope] compile-flags: -Zunstable-options --remap-path-scope=debuginfo +//@[with-doc-scope] compile-flags: -Zunstable-options --remap-path-scope=documentation + +/// ``` +/// fn invalid( +/// ``` +pub struct SomeStruct; diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.with-diag-scope.stdout b/tests/rustdoc-ui/remap-path-prefix-doctest.with-diag-scope.stdout new file mode 100644 index 000000000000..22f4fe70c617 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.with-diag-scope.stdout @@ -0,0 +1,24 @@ + +running 1 test +test $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) ... FAILED + +failures: + +---- $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) stdout ---- +error: this file contains an unclosed delimiter + --> $DIR/remap-path-prefix-doctest.rs:20:12 + | +LL | fn invalid( + | -^ + | | + | unclosed delimiter + +error: aborting due to 1 previous error + +Couldn't compile the test. + +failures: + $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) + +test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in $TIME + diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.with-doc-scope.stdout b/tests/rustdoc-ui/remap-path-prefix-doctest.with-doc-scope.stdout new file mode 100644 index 000000000000..248f7734652f --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.with-doc-scope.stdout @@ -0,0 +1,24 @@ + +running 1 test +test remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) ... FAILED + +failures: + +---- remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) stdout ---- +error: this file contains an unclosed delimiter + --> remapped_path/remap-path-prefix-doctest.rs:20:12 + | +LL | fn invalid( + | -^ + | | + | unclosed delimiter + +error: aborting due to 1 previous error + +Couldn't compile the test. + +failures: + remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) + +test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in $TIME + diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.with-macro-scope.stdout b/tests/rustdoc-ui/remap-path-prefix-doctest.with-macro-scope.stdout new file mode 100644 index 000000000000..22f4fe70c617 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.with-macro-scope.stdout @@ -0,0 +1,24 @@ + +running 1 test +test $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) ... FAILED + +failures: + +---- $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) stdout ---- +error: this file contains an unclosed delimiter + --> $DIR/remap-path-prefix-doctest.rs:20:12 + | +LL | fn invalid( + | -^ + | | + | unclosed delimiter + +error: aborting due to 1 previous error + +Couldn't compile the test. + +failures: + $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) + +test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in $TIME + diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.with-object-scope.stdout b/tests/rustdoc-ui/remap-path-prefix-doctest.with-object-scope.stdout new file mode 100644 index 000000000000..22f4fe70c617 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.with-object-scope.stdout @@ -0,0 +1,24 @@ + +running 1 test +test $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) ... FAILED + +failures: + +---- $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) stdout ---- +error: this file contains an unclosed delimiter + --> $DIR/remap-path-prefix-doctest.rs:20:12 + | +LL | fn invalid( + | -^ + | | + | unclosed delimiter + +error: aborting due to 1 previous error + +Couldn't compile the test. + +failures: + $DIR/remap-path-prefix-doctest.rs - SomeStruct (line 19) + +test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in $TIME + diff --git a/tests/rustdoc-ui/remap-path-prefix-doctest.without-scope.stdout b/tests/rustdoc-ui/remap-path-prefix-doctest.without-scope.stdout new file mode 100644 index 000000000000..248f7734652f --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix-doctest.without-scope.stdout @@ -0,0 +1,24 @@ + +running 1 test +test remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) ... FAILED + +failures: + +---- remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) stdout ---- +error: this file contains an unclosed delimiter + --> remapped_path/remap-path-prefix-doctest.rs:20:12 + | +LL | fn invalid( + | -^ + | | + | unclosed delimiter + +error: aborting due to 1 previous error + +Couldn't compile the test. + +failures: + remapped_path/remap-path-prefix-doctest.rs - SomeStruct (line 19) + +test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in $TIME + diff --git a/tests/rustdoc-ui/remap-path-prefix-macro.rs b/tests/rustdoc-ui/remap-path-prefix-macro-138520.rs similarity index 100% rename from tests/rustdoc-ui/remap-path-prefix-macro.rs rename to tests/rustdoc-ui/remap-path-prefix-macro-138520.rs diff --git a/tests/rustdoc-ui/remap-path-prefix.rs b/tests/rustdoc-ui/remap-path-prefix.rs new file mode 100644 index 000000000000..e3efa9a69349 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.rs @@ -0,0 +1,28 @@ +// This test exercises `--remap-path-prefix` and `--remap-path-scope` with macros, +// like file!() and a diagnostic with compile_error!(). +// +// See the compiler test suite for a more advanced tests, we just want to +// make sure here that rustdoc passes the right scopes to the underline rustc APIs. + +//@ revisions: with-diag-scope with-macro-scope with-debuginfo-scope with-doc-scope +//@ revisions: without-scopes without-remap + +//@[with-diag-scope] compile-flags: -Zunstable-options --remap-path-prefix={{src-base}}=remapped +//@[with-macro-scope] compile-flags: -Zunstable-options --remap-path-prefix={{src-base}}=remapped +//@[with-debuginfo-scope] compile-flags: -Zunstable-options --remap-path-prefix={{src-base}}=remapped +//@[with-doc-scope] compile-flags: -Zunstable-options --remap-path-prefix={{src-base}}=remapped +//@[without-scopes] compile-flags: -Zunstable-options --remap-path-prefix={{src-base}}=remapped + +//@[with-diag-scope] compile-flags: -Zunstable-options --remap-path-scope=diagnostics +//@[with-macro-scope] compile-flags: -Zunstable-options --remap-path-scope=macro +//@[with-debuginfo-scope] compile-flags: -Zunstable-options --remap-path-scope=debuginfo +//@[with-doc-scope] compile-flags: -Zunstable-options --remap-path-scope=documentation + +compile_error!(concat!("file!() = ", file!())); +//[with-macro-scope]~^ ERROR file!() +//[with-debuginfo-scope]~^^ ERROR file!() +//[with-doc-scope]~^^^ ERROR file!() +//[without-remap]~^^^^ ERROR file!() + +//[with-diag-scope]~? ERROR file!() +//[without-scopes]~? ERROR file!() diff --git a/tests/rustdoc-ui/remap-path-prefix.with-debuginfo-scope.stderr b/tests/rustdoc-ui/remap-path-prefix.with-debuginfo-scope.stderr new file mode 100644 index 000000000000..ce506a9529c6 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.with-debuginfo-scope.stderr @@ -0,0 +1,8 @@ +error: file!() = $DIR/remap-path-prefix.rs + --> $DIR/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-prefix.with-diag-scope.stderr b/tests/rustdoc-ui/remap-path-prefix.with-diag-scope.stderr new file mode 100644 index 000000000000..a51ff5dce4a3 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.with-diag-scope.stderr @@ -0,0 +1,8 @@ +error: file!() = $DIR/remap-path-prefix.rs + --> remapped/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-prefix.with-doc-scope.stderr b/tests/rustdoc-ui/remap-path-prefix.with-doc-scope.stderr new file mode 100644 index 000000000000..ce506a9529c6 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.with-doc-scope.stderr @@ -0,0 +1,8 @@ +error: file!() = $DIR/remap-path-prefix.rs + --> $DIR/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-prefix.with-macro-scope.stderr b/tests/rustdoc-ui/remap-path-prefix.with-macro-scope.stderr new file mode 100644 index 000000000000..2ac0fb513a9c --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.with-macro-scope.stderr @@ -0,0 +1,8 @@ +error: file!() = remapped/remap-path-prefix.rs + --> $DIR/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-prefix.without-remap.stderr b/tests/rustdoc-ui/remap-path-prefix.without-remap.stderr new file mode 100644 index 000000000000..ce506a9529c6 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.without-remap.stderr @@ -0,0 +1,8 @@ +error: file!() = $DIR/remap-path-prefix.rs + --> $DIR/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-prefix.without-scopes.stderr b/tests/rustdoc-ui/remap-path-prefix.without-scopes.stderr new file mode 100644 index 000000000000..8564703e74dc --- /dev/null +++ b/tests/rustdoc-ui/remap-path-prefix.without-scopes.stderr @@ -0,0 +1,8 @@ +error: file!() = remapped/remap-path-prefix.rs + --> remapped/remap-path-prefix.rs:21:1 + | +LL | compile_error!(concat!("file!() = ", file!())); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/rustdoc-ui/remap-path-scope-invalid.foo.stderr b/tests/rustdoc-ui/remap-path-scope-invalid.foo.stderr new file mode 100644 index 000000000000..dc72089e0d57 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-scope-invalid.foo.stderr @@ -0,0 +1,2 @@ +error: argument for `--remap-path-scope` must be a comma separated list of scopes: `macro`, `diagnostics`, `documentation`, `debuginfo`, `coverage`, `object`, `all` + diff --git a/tests/rustdoc-ui/remap-path-scope-invalid.rs b/tests/rustdoc-ui/remap-path-scope-invalid.rs new file mode 100644 index 000000000000..7dde2739d409 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-scope-invalid.rs @@ -0,0 +1,10 @@ +// Error on invalid --remap-path-scope arguments + +//@ revisions: foo underscore +//@ compile-flags: -Zunstable-options +//@ [foo]compile-flags: --remap-path-scope=foo +//@ [underscore]compile-flags: --remap-path-scope=macro_object + +//~? RAW argument for `--remap-path-scope + +fn main() {} diff --git a/tests/rustdoc-ui/remap-path-scope-invalid.underscore.stderr b/tests/rustdoc-ui/remap-path-scope-invalid.underscore.stderr new file mode 100644 index 000000000000..dc72089e0d57 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-scope-invalid.underscore.stderr @@ -0,0 +1,2 @@ +error: argument for `--remap-path-scope` must be a comma separated list of scopes: `macro`, `diagnostics`, `documentation`, `debuginfo`, `coverage`, `object`, `all` + diff --git a/tests/rustdoc-ui/remap-path-scope-unstable.rs b/tests/rustdoc-ui/remap-path-scope-unstable.rs new file mode 100644 index 000000000000..34b8040c87c1 --- /dev/null +++ b/tests/rustdoc-ui/remap-path-scope-unstable.rs @@ -0,0 +1,7 @@ +// Regression test to make sure `--remap-path-scope` is unstable in rustdoc + +//@ compile-flags:--remap-path-scope macro + +//~? RAW the `-Z unstable-options` flag must also be passed to enable the flag `remap-path-scope` + +fn main() {} diff --git a/tests/rustdoc-ui/remap-path-scope-unstable.stderr b/tests/rustdoc-ui/remap-path-scope-unstable.stderr new file mode 100644 index 000000000000..04c51836206a --- /dev/null +++ b/tests/rustdoc-ui/remap-path-scope-unstable.stderr @@ -0,0 +1,2 @@ +error: the `-Z unstable-options` flag must also be passed to enable the flag `remap-path-scope` + diff --git a/tests/ui-fulldeps/internal-lints/must_match_exhaustively.rs b/tests/ui-fulldeps/internal-lints/must_match_exhaustively.rs new file mode 100644 index 000000000000..e3a77471a0fe --- /dev/null +++ b/tests/ui-fulldeps/internal-lints/must_match_exhaustively.rs @@ -0,0 +1,51 @@ +//@ compile-flags: -Z unstable-options +//@ ignore-stage1 + +#![feature(rustc_private)] +#![feature(rustc_attrs)] +#![deny(rustc::rustc_must_match_exhaustively)] + +#[rustc_must_match_exhaustively] +#[derive(Copy, Clone)] +enum Foo { + A { field: u32 }, + B, +} + +fn foo(f: Foo) { + match f { + Foo::A { .. } => {} + Foo::B => {} + } + + match f { + //~^ ERROR match is not exhaustive + Foo::A { .. } => {} + _ => {} + } + + match f { + //~^ ERROR match is not exhaustive + Foo::A { .. } => {} + a => {} + } + + match &f { + //~^ ERROR match is not exhaustive + Foo::A { .. } => {} + a => {} + } + + match f { + Foo::A { .. } => {} + a @ Foo::B => {} + } + + if let Foo::A { .. } = f {} + //~^ ERROR match is not exhaustive + + let Foo::A { .. } = f else { loop {} }; + //~^ ERROR match is not exhaustive +} + +fn main() {} diff --git a/tests/ui-fulldeps/internal-lints/must_match_exhaustively.stderr b/tests/ui-fulldeps/internal-lints/must_match_exhaustively.stderr new file mode 100644 index 000000000000..a6ef63c5aba8 --- /dev/null +++ b/tests/ui-fulldeps/internal-lints/must_match_exhaustively.stderr @@ -0,0 +1,87 @@ +error: match is not exhaustive + --> $DIR/must_match_exhaustively.rs:21:11 + | +LL | #[rustc_must_match_exhaustively] + | -------------------------------- required because of this attribute +... +LL | match f { + | ^ + | + = help: explicitly list all variants of the enum in a `match` +note: because of this wildcard pattern + --> $DIR/must_match_exhaustively.rs:24:9 + | +LL | _ => {} + | ^ +note: the lint level is defined here + --> $DIR/must_match_exhaustively.rs:6:9 + | +LL | #![deny(rustc::rustc_must_match_exhaustively)] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: match is not exhaustive + --> $DIR/must_match_exhaustively.rs:27:11 + | +LL | #[rustc_must_match_exhaustively] + | -------------------------------- required because of this attribute +... +LL | match f { + | ^ + | + = help: explicitly list all variants of the enum in a `match` +note: because of this variable binding + --> $DIR/must_match_exhaustively.rs:30:9 + | +LL | a => {} + | ^ + +error: match is not exhaustive + --> $DIR/must_match_exhaustively.rs:33:11 + | +LL | #[rustc_must_match_exhaustively] + | -------------------------------- required because of this attribute +... +LL | match &f { + | ^^ + | + = help: explicitly list all variants of the enum in a `match` +note: because of this variable binding + --> $DIR/must_match_exhaustively.rs:36:9 + | +LL | a => {} + | ^ + +error: match is not exhaustive + --> $DIR/must_match_exhaustively.rs:44:8 + | +LL | #[rustc_must_match_exhaustively] + | -------------------------------- required because of this attribute +... +LL | if let Foo::A { .. } = f {} + | ^^^^^^^^^^^^^^^^^^^^^ + | + = help: explicitly list all variants of the enum in a `match` +note: using `if let` only matches on one variant (try using `match`) + --> $DIR/must_match_exhaustively.rs:44:8 + | +LL | if let Foo::A { .. } = f {} + | ^^^^^^^^^^^^^^^^^^^^^ + +error: match is not exhaustive + --> $DIR/must_match_exhaustively.rs:47:5 + | +LL | #[rustc_must_match_exhaustively] + | -------------------------------- required because of this attribute +... +LL | let Foo::A { .. } = f else { loop {} }; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = help: explicitly list all variants of the enum in a `match` +note: using `let else` only matches on one variant (try using `match`) + --> $DIR/must_match_exhaustively.rs:47:9 + | +LL | let Foo::A { .. } = f else { loop {} }; + | ^^^^^^^^^^^^^ + +error: aborting due to 5 previous errors + diff --git a/tests/ui/README.md b/tests/ui/README.md index a9e7f022c2b6..9ef331698d2b 100644 --- a/tests/ui/README.md +++ b/tests/ui/README.md @@ -22,6 +22,12 @@ These tests exercise `#![feature(allocator_api)]` and the `#[global_allocator]` See [Allocator traits and `std::heap` #32838](https://github.com/rust-lang/rust/issues/32838). +## `tests/ui/allow-partial-mitigations` + +These tests exercise the support for mitigation coverage and the `allow-partial-mitigations` and `deny-partial-mitigations` options. + +See [RFC 3855](https://github.com/rust-lang/rfcs/pull/3855). + ## `tests/ui/annotate-moves` These tests exercise the `annotate-moves` feature. @@ -1352,7 +1358,7 @@ See [Strict Version Hash](https://rustc-dev-guide.rust-lang.org/backend/libs-and ## `tests/ui/symbol-names/`: Symbol mangling and related attributes -These tests revolve around `#[no_mangle]` attribute, as well as consistently mangled symbol names (checked with the `rustc_symbol_name` attribute), which is important to build reproducible binaries. +These tests revolve around `#[no_mangle]` attribute, as well as consistently mangled symbol names (checked with the `rustc_dump_symbol_name` attribute), which is important to build reproducible binaries. ## `tests/ui/sync/`: `Sync` trait diff --git a/tests/ui/allocator/allocator-args.stderr b/tests/ui/allocator/allocator-args.stderr index ad640767fee1..76e596e1740f 100644 --- a/tests/ui/allocator/allocator-args.stderr +++ b/tests/ui/allocator/allocator-args.stderr @@ -2,7 +2,13 @@ error: malformed `global_allocator` attribute input --> $DIR/allocator-args.rs:10:1 | LL | #[global_allocator(malloc)] - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: must be of the form: `#[global_allocator]` + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +help: must be of the form + | +LL - #[global_allocator(malloc)] +LL + #[global_allocator] + | error: aborting due to 1 previous error diff --git a/tests/ui/allocator/no-thread-local.rs b/tests/ui/allocator/no-thread-local.rs new file mode 100644 index 000000000000..4548b00816fd --- /dev/null +++ b/tests/ui/allocator/no-thread-local.rs @@ -0,0 +1,10 @@ +#![feature(thread_local)] + +use std::alloc::System; + +#[global_allocator] +#[thread_local] +static A: System = System; +//~^ ERROR: allocators cannot be `#[thread_local]` + +fn main() {} diff --git a/tests/ui/allocator/no-thread-local.stderr b/tests/ui/allocator/no-thread-local.stderr new file mode 100644 index 000000000000..b045dae09c8e --- /dev/null +++ b/tests/ui/allocator/no-thread-local.stderr @@ -0,0 +1,13 @@ +error: allocators cannot be `#[thread_local]` + --> $DIR/no-thread-local.rs:7:1 + | +LL | #[thread_local] + | --------------- + | | + | marked `#[thread_local]` here + | help: remove this attribute +LL | static A: System = System; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.control-flow-guard-future-allow-reset-by-mitigation.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.control-flow-guard-future-allow-reset-by-mitigation.stderr new file mode 100644 index 000000000000..1103e17a17f5 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.control-flow-guard-future-allow-reset-by-mitigation.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `core`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `alloc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `unwind/libc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.rs b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.rs new file mode 100644 index 000000000000..f4c5e56da53c --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.rs @@ -0,0 +1,42 @@ +// ignore-tidy-linelength +//@ revisions: stack-protector-future stack-protector-future-explicit-deny stack-protector-future-deny-reset-by-mitigation stack-protector-allow-then-deny stack-protector-but-allow-control-flow-guard control-flow-guard-future-allow-reset-by-mitigation stack-protector-future-allow-reset-by-mitigation stack-protector-future-deny-allow-reset-by-mitigation +//@ check-fail +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported +//@ edition:future + +// msvc has an extra unwind dependency of std, normalize it in the error messages +//@ normalize-stderr: "\b(unwind|libc)\b" -> "unwind/libc" + +// test that stack-protector is denied-partial in edition=future +//@ [stack-protector-future] compile-flags: -Z unstable-options -Z stack-protector=all + +// same, but with explicit deny +//@ [stack-protector-future-explicit-deny] compile-flags: -Z unstable-options -Z stack-protector=all -Z deny-partial-mitigations=stack-protector + +// same, but with explicit deny before the enable. The `-Z stack-protector=all` resets the mitigation status +// to default which is deny at edition=future. +// at edition=2024, this would be allowed, see ok-allow-partial-mitigations-current-edition scenario stack-protector-future-deny-reset-by-mitigation +//@ [stack-protector-future-deny-reset-by-mitigation] compile-flags: -Z unstable-options -Z deny-partial-mitigations=stack-protector -Z stack-protector=all + +// same, but with explicit allow followed by explicit deny +//@ [stack-protector-allow-then-deny] compile-flags: -Z unstable-options -Z stack-protector=all -Z allow-partial-mitigations=stack-protector -Z deny-partial-mitigations=stack-protector + +// check that allowing an unrelated mitigation (control-flow-guard) does not allow a different mitigation (stack-protector) +//@ [stack-protector-but-allow-control-flow-guard] compile-flags: -Z unstable-options -Z stack-protector=all -Z allow-partial-mitigations=control-flow-guard + +// check that `-C control-flow-guard` overrides the `-Z allow-partial-mitigations=control-flow-guard` (to the default, which is deny at edition=future) +//@ [control-flow-guard-future-allow-reset-by-mitigation] compile-flags: -Z unstable-options -Z allow-partial-mitigations=control-flow-guard -C control-flow-guard=on + +// check that `-Z stack-protector` overrides the `-Z allow-partial-mitigations=stack-protector` (to the default, which is deny at edition=future) +//@ [stack-protector-future-allow-reset-by-mitigation] compile-flags: -Z unstable-options -Z allow-partial-mitigations=stack-protector -Z stack-protector=all + +// check that this is the case even if there was a "deny" before the "allow" +//@ [stack-protector-future-deny-allow-reset-by-mitigation] compile-flags: -Z unstable-options -Z deny-partial-mitigations=stack-protector -Z allow-partial-mitigations=stack-protector -Z stack-protector=all + +fn main() {} +//~^ ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-allow-then-deny.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-allow-then-deny.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-allow-then-deny.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-but-allow-control-flow-guard.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-but-allow-control-flow-guard.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-but-allow-control-flow-guard.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-allow-reset-by-mitigation.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-allow-reset-by-mitigation.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-allow-reset-by-mitigation.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-allow-reset-by-mitigation.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-allow-reset-by-mitigation.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-allow-reset-by-mitigation.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-reset-by-mitigation.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-reset-by-mitigation.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-deny-reset-by-mitigation.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-explicit-deny.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-explicit-deny.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future-explicit-deny.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future.stderr new file mode 100644 index 000000000000..3fde64abb2f3 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-1-error.stack-protector-future.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-1-error.rs:37:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.both.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.both.stderr new file mode 100644 index 000000000000..acc9dd234c69 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.both.stderr @@ -0,0 +1,92 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `std`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: aborting due to 10 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-separately-disable-together.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-separately-disable-together.stderr new file mode 100644 index 000000000000..acc9dd234c69 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-separately-disable-together.stderr @@ -0,0 +1,92 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `std`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: aborting due to 10 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-together-disable-separately.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-together-disable-separately.stderr new file mode 100644 index 000000000000..acc9dd234c69 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.enable-together-disable-separately.stderr @@ -0,0 +1,92 @@ +error: your program uses the crate `std`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `std`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `core`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `core`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `alloc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `alloc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `unwind/libc`, that is not compiled with `stack-protector=all` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `stack-protector=all` enabled, or use `-Z allow-partial-mitigations=stack-protector` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=stack-protector` via `-Z deny-partial-mitigations=stack-protector` + +error: your program uses the crate `unwind/libc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-2-errors.rs:21:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: aborting due to 10 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.rs b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.rs new file mode 100644 index 000000000000..a1c7eba08ebe --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-2-errors.rs @@ -0,0 +1,31 @@ +// ignore-tidy-linelength +//@ revisions: both enable-separately-disable-together enable-together-disable-separately +//@ check-fail +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported +//@ edition:future + +// msvc has an extra unwind dependency of std, normalize it in the error messages +//@ normalize-stderr: "\b(unwind|libc)\b" -> "unwind/libc" + +// just use 2 partial mitigations, without any allow/deny flag. Should be denied at edition=future. +//@ [both] compile-flags: -Z unstable-options -C control-flow-guard=on -Z stack-protector=all + +// check that mitigations are denied if they are enabled separately and then disabled in a single command, +// to test the "foo,bar" syntax +//@ [enable-separately-disable-together] compile-flags: -Z unstable-options -C control-flow-guard=on -Z stack-protector=all -Z allow-partial-mitigations=stack-protector -Z allow-partial-mitigations=control-flow-guard -Z deny-partial-mitigations=control-flow-guard,stack-protector + +// same, but for allow +//@ [enable-together-disable-separately] compile-flags: -Z unstable-options -C control-flow-guard=on -Z stack-protector=all -Z allow-partial-mitigations=stack-protector,control-flow-guard -Z deny-partial-mitigations=control-flow-guard -Z deny-partial-mitigations=stack-protector + +fn main() {} +//~^ ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.rs b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.rs new file mode 100644 index 000000000000..c5fe5b0e1158 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.rs @@ -0,0 +1,12 @@ +// ignore-tidy-linelength +//@ check-fail +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported +//@ edition:future +//@ compile-flags: -Z unstable-options -Z deny-partial-mitigations=garbage + +// test that the list of mitigations in the error message is generated correctly + +//~? ERROR incorrect value `garbage` for unstable option `deny-partial-mitigations` - comma-separated list of mitigation kinds (available: + +fn main() {} diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.stderr new file mode 100644 index 000000000000..9af53a1689ae --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-bad-cli.stderr @@ -0,0 +1,2 @@ +error: incorrect value `garbage` for unstable option `deny-partial-mitigations` - comma-separated list of mitigation kinds (available: `stack-protector`, `control-flow-guard`) was expected + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.control-flow-2024-explicit-deny.stderr b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.control-flow-2024-explicit-deny.stderr new file mode 100644 index 000000000000..8f19f30d7656 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.control-flow-2024-explicit-deny.stderr @@ -0,0 +1,47 @@ +error: your program uses the crate `std`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-current-edition.rs:18:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `std` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `core`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-current-edition.rs:18:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `core` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `alloc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-current-edition.rs:18:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `alloc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `compiler_builtins`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-current-edition.rs:18:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `compiler_builtins` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: your program uses the crate `unwind/libc`, that is not compiled with `control-flow-guard` enabled + --> $DIR/err-allow-partial-mitigations-current-edition.rs:18:1 + | +LL | fn main() {} + | ^ + | + = note: recompile `unwind/libc` with `control-flow-guard` enabled, or use `-Z allow-partial-mitigations=control-flow-guard` to allow creating an artifact that has the mitigation partially enabled + = help: it is possible to disable `-Z allow-partial-mitigations=control-flow-guard` via `-Z deny-partial-mitigations=control-flow-guard` + +error: aborting due to 5 previous errors + diff --git a/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.rs b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.rs new file mode 100644 index 000000000000..fd3ff9492353 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/err-allow-partial-mitigations-current-edition.rs @@ -0,0 +1,23 @@ +// ignore-tidy-linelength +//@ revisions: control-flow-2024-explicit-deny +//@ check-fail +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported +//@ edition: 2024 + +// msvc has an extra unwind dependency of std, normalize it in the error messages +//@ normalize-stderr: "\b(unwind|libc)\b" -> "unwind/libc" + +// check that in edition 2024, it is still possible to explicitly +// disallow partial mitigations (in edition=future, they are +// disallowed by default) + +//@ [control-flow-2024-explicit-deny] compile-flags: -C control-flow-guard=on -Z deny-partial-mitigations=control-flow-guard + + +fn main() {} +//~^ ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with +//~| ERROR that is not compiled with diff --git a/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-current-edition.rs b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-current-edition.rs new file mode 100644 index 000000000000..dddad265aff4 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-current-edition.rs @@ -0,0 +1,25 @@ +// ignore-tidy-linelength +//@ revisions: control-flow-guard-2024-default control-flow-guard-2024-deny-reset-by-mitigation stack-protector-2024-deny-reset-by-mitigation stack-protector-2024-allow-deny-reset-by-mitigation +//@ check-pass +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported +//@ edition: 2024 + +// check that the `-C control-flow-guard=on` overrides the `-Z deny-partial-mitigations=control-flow-guard`, +// which in edition 2024 leads to partial mitigations being allowed. Test with both an explicit +// deny and without one. + +// just test control-flow-guard at edition 2024. allowed-partial due to backwards compatibility. +//@ [control-flow-guard-2024-default] compile-flags: -C control-flow-guard=on + +// test that -C control-flow-guard=on resets -Z deny-partial-mitigations=control-flow-guard +//@ [control-flow-guard-2024-deny-reset-by-mitigation] compile-flags: -Z deny-partial-mitigations=control-flow-guard -C control-flow-guard=on + +// same but for stack-protector, to match the stack-protector-future-deny-reset-by-mitigation test in +// err-allow-partial-mitigations-1-error (which has the same args but on edition=future). +//@ [stack-protector-2024-deny-reset-by-mitigation] compile-flags: -Z deny-partial-mitigations=stack-protector -Z stack-protector=all + +// check that this is the case even if there was an "allow" then a "deny" +//@ [stack-protector-2024-allow-deny-reset-by-mitigation] compile-flags: -Z unstable-options -Z allow-partial-mitigations=stack-protector -Z deny-partial-mitigations=stack-protector -Z stack-protector=all + +fn main() {} diff --git a/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-minicore.rs b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-minicore.rs new file mode 100644 index 000000000000..bc8aaa3cb2e6 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations-minicore.rs @@ -0,0 +1,18 @@ +// ignore-tidy-linelength +//@ check-pass +//@ add-minicore +//@ edition:future +//@ revisions: default deny +//@[default] compile-flags: -Z unstable-options -Z stack-protector=all +//@[deny] compile-flags: -Z deny-partial-mitigations=stack-protector -Z unstable-options -Z stack-protector=all + +// ^ enables stack-protector for both minicore and this crate + +#![crate_type = "lib"] +#![feature(no_core)] +#![no_std] +#![no_core] + +extern crate minicore; + +pub fn foo() {} diff --git a/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations.rs b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations.rs new file mode 100644 index 000000000000..f9f013e44cc6 --- /dev/null +++ b/tests/ui/allow-partial-mitigations/ok-allow-partial-mitigations.rs @@ -0,0 +1,18 @@ +// ignore-tidy-linelength +//@ revisions: stack-protector-explicit-allow stack-protector-and-control-flow-guard-explicit-allow stack-protector-deny-then-allow +//@ check-pass +//@ edition:future +//@ ignore-nvptx64 stack protector is not supported +//@ ignore-wasm32-unknown-unknown stack protector is not supported + +// requesting both stack-protector and control-flow-guard and then allow-partial-mitigations it +//@ [stack-protector-and-control-flow-guard-explicit-allow] compile-flags: -Z unstable-options -Z stack-protector=all -C control-flow-guard=on -Z allow-partial-mitigations=stack-protector,control-flow-guard + +// requesting stack-protector and then allow-partial-mitigations it +//@ [stack-protector-explicit-allow] compile-flags: -Z unstable-options -Z stack-protector=all -Z allow-partial-mitigations=stack-protector + +// testing that the later allow-partial-mitigations overrides the earlier deny-partial-mitigations +// see also the stack-protector-allow-then-deny test (in the error tests) for the other order +//@ [stack-protector-deny-then-allow] compile-flags: -Z unstable-options -Z stack-protector=all -Z deny-partial-mitigations=stack-protector -Z allow-partial-mitigations=stack-protector + +fn main() {} diff --git a/tests/ui/argument-suggestions/wrong-highlight-span-extra-arguments-147070.svg b/tests/ui/argument-suggestions/wrong-highlight-span-extra-arguments-147070.svg index af41631479cf..549acee7cee5 100644 --- a/tests/ui/argument-suggestions/wrong-highlight-span-extra-arguments-147070.svg +++ b/tests/ui/argument-suggestions/wrong-highlight-span-extra-arguments-147070.svg @@ -1,4 +1,4 @@ - + (&self) + fn foo(&self, _f: impl FnOnce(T, U) -> (U, T)) where T: Trait0, U: Trait0, @@ -39,7 +39,7 @@ impl Trait0 for u16 {} pub fn check() { let s = S(F, &123, &123, &123); - as Trait1>::foo::(&s); + as Trait1>::foo::(&s, |x, y| (y, x)); } } diff --git a/tests/ui/delegation/generics/mapping/inherent-impl-to-free-pass.rs b/tests/ui/delegation/generics/mapping/inherent-impl-to-free-pass.rs index 69e0523a0c99..1e08e155c5de 100644 --- a/tests/ui/delegation/generics/mapping/inherent-impl-to-free-pass.rs +++ b/tests/ui/delegation/generics/mapping/inherent-impl-to-free-pass.rs @@ -2,7 +2,6 @@ #![feature(fn_delegation)] #![allow(incomplete_features)] -#![allow(late_bound_lifetime_arguments)] //! This is one of the mapping tests, which tests mapping of delegee parent and child //! generic params, whose main goal is to create cases with @@ -12,10 +11,10 @@ // Testing lifetimes + types/consts OR types/consts OR none in delegation parent, // lifetimes + types/consts in child reuse, -// with(out) user-specified args +// with(out) user-specified args, with impl traits mod test_1 { mod to_reuse { - pub fn foo<'a: 'a, 'b: 'b, A, B, const N: usize>() {} + pub fn foo<'a: 'a, 'b: 'b, A, B, const N: usize>(_f: impl FnOnce(A, B) -> B) {} } #[allow(dead_code)] // Fields are used instead of phantom data for generics use @@ -40,14 +39,14 @@ impl X3 { pub fn check() { X1::<'static, 'static, i32, i32, 1> - ::foo::<'static, 'static, String, String, 123>(); - X1::<'static, 'static, i32, i32, 1>::bar(); + ::foo::<'static, 'static, String, String, 123>(|_, y| y); + X1::<'static, 'static, i32, i32, 1>::bar(|_, y| y); - X2::::foo::<'static, 'static, String, String, 123>(); - X2::::bar(); + X2::::foo::<'static, 'static, String, String, 123>(|_, y| y); + X2::::bar(|_, y| y); - X3::foo::<'static, 'static, String, String, 123>(); - X3::bar(); + X3::foo::<'static, 'static, String, String, 123>(|_, y| y); + X3::bar(|_, y| y); } } diff --git a/tests/ui/delegation/generics/mapping/inherent-impl-to-trait-pass.rs b/tests/ui/delegation/generics/mapping/inherent-impl-to-trait-pass.rs index 9e85a7c07c3a..bf4d1a7ca2cb 100644 --- a/tests/ui/delegation/generics/mapping/inherent-impl-to-trait-pass.rs +++ b/tests/ui/delegation/generics/mapping/inherent-impl-to-trait-pass.rs @@ -12,10 +12,10 @@ // Testing types in parent, none in child, // user-specified args in parent, checking predicates inheritance, -// with additional generic params in delegation parent +// with additional generic params in delegation parent, with impl traits mod test_1 { trait Trait { - fn foo(&self) {} + fn foo(&self, _f: impl FnOnce(T) -> String) {} } struct F; @@ -29,8 +29,8 @@ impl<'a, 'b, 'c, A, B> S<'a, 'b, 'c, A, B> { pub fn check() { let s = S(F, &123, &123, &123); - S::<'static, 'static, 'static, i32, i32>::foo(&s); - s.foo(); + S::<'static, 'static, 'static, i32, i32>::foo(&s, |t| t.to_string()); + s.foo(|t| t.to_string()); } } diff --git a/tests/ui/delegation/generics/mapping/trait-to-free-pass.rs b/tests/ui/delegation/generics/mapping/trait-to-free-pass.rs index 52e0a9c89394..12edc3b72fac 100644 --- a/tests/ui/delegation/generics/mapping/trait-to-free-pass.rs +++ b/tests/ui/delegation/generics/mapping/trait-to-free-pass.rs @@ -2,7 +2,6 @@ #![feature(fn_delegation)] #![allow(incomplete_features)] -#![allow(late_bound_lifetime_arguments)] //! This is one of the mapping tests, which tests mapping of delegee parent and child //! generic params, whose main goal is to create cases with @@ -11,9 +10,10 @@ //! added. At some tests user-specified args are specified in reuse statement. // Testing lifetimes + types/consts in child, lifetimes + types/consts in delegation parent, -// with(out) user-specified args +// with(out) user-specified args, with impl traits mod test_1 { - fn foo<'a: 'a, 'b: 'b, T: Clone + ToString, U: Clone, const N: usize>() {} + fn foo<'a: 'a, 'b: 'b, T: Clone + ToString, U: Clone, const N: usize>( + _f: impl FnOnce(T) -> (T, U)) {} trait Trait<'a, A, B, C, const N: usize> { reuse foo; @@ -22,8 +22,10 @@ trait Trait<'a, A, B, C, const N: usize> { impl Trait<'static, i32, i32, i32, 1> for u32 {} pub fn check() { - >::foo::<'static, 'static, i32, String, 1>(); - >::bar(); + > + ::foo::<'static, 'static, i32, String, 1>(|t| (t, "".to_string())); + >::bar(|t| (t, t.to_string())); + u32::bar(|t| (t, t.to_string())); } } diff --git a/tests/ui/delegation/generics/mapping/trait-to-trait-pass.rs b/tests/ui/delegation/generics/mapping/trait-to-trait-pass.rs index 0e96f045065a..bcc1369aa440 100644 --- a/tests/ui/delegation/generics/mapping/trait-to-trait-pass.rs +++ b/tests/ui/delegation/generics/mapping/trait-to-trait-pass.rs @@ -14,10 +14,10 @@ // lifetimes + types/consts in child, // in delegation parent with: // lifetimes + types OR none OR lifetimes OR types, -// with(out) user-specified args, with different target expr +// with(out) user-specified args, with different target expr, with impl traits mod test_1 { trait Trait<'b, 'c, 'a, T>: Sized { - fn foo<'d: 'd, U, const M: bool>(&self) {} + fn foo<'d: 'd, U, const M: bool>(&self, _f: impl FnOnce(T) -> U) {} } impl<'b, 'c, 'a, T> Trait<'b, 'c, 'a, T> for u8 {} @@ -83,26 +83,26 @@ impl Trait5 for u32 {} pub fn check<'a: 'a>() { > - ::bar1::<'static, String, true>(&123); - ::bar1::<'static, String, true>(&123); - >::bar1::<'static, String, true>(&123); - >::bar1::<'static, String, true>(&123); + ::bar1::<'static, String, true>(&123, |x| x.to_string()); + ::bar1::<'static, String, true>(&123, |x| x.to_string()); + >::bar1::<'static, String, true>(&123, |x| x.to_string()); + >::bar1::<'static, String, true>(&123, |x| x.to_string()); - >::bar2(&123); - ::bar2(&123); - >::bar2(&123); - >::bar2(&123); + >::bar2(&123, |x| x.to_string()); + ::bar2(&123, |x| x.to_string()); + >::bar2(&123, |x| x.to_string()); + >::bar2(&123, |x| x.to_string()); > - ::bar3::<'static, String, true>(&123); - ::bar3::<'static, String, true>(&123); - >::bar3::<'static, String, true>(&123); - >::bar3::<'static, String, true>(&123); + ::bar3::<'static, String, true>(&123, |x| x.to_string()); + ::bar3::<'static, String, true>(&123, |x| x.to_string()); + >::bar3::<'static, String, true>(&123, |x| x.to_string()); + >::bar3::<'static, String, true>(&123, |x| x.to_string()); - >::bar4(&123); - ::bar4(&123); - >::bar4(&123); - >::bar4(&123); + >::bar4(&123, |x| x.to_string()); + ::bar4(&123, |x| x.to_string()); + >::bar4(&123, |x| x.to_string()); + >::bar4(&123, |x| x.to_string()); } } diff --git a/tests/ui/delegation/generics/synth-params-ice-154780.rs b/tests/ui/delegation/generics/synth-params-ice-154780.rs new file mode 100644 index 000000000000..96af4ed86b4c --- /dev/null +++ b/tests/ui/delegation/generics/synth-params-ice-154780.rs @@ -0,0 +1,101 @@ +//@ run-pass + +#![feature(fn_delegation)] + +// Almost original ICE with recursive delegation. +mod test_1 { + pub fn check() { + fn foo(f: impl FnOnce() -> usize) -> usize { + f() + } + + reuse foo::<1, String, String> as bar; + + reuse bar as bar2; + + assert_eq!(bar(|| 123), 123); + assert_eq!(bar2(|| 123), 123); + } +} + +// Test recursive delegations through trait. +mod test_2 { + fn foo<'a, const B: bool, T, U>(_x: impl Trait<'a, T, B>, f: impl FnOnce() -> usize) -> usize { + f() + } + + trait Trait<'a, A, const B: bool> { + reuse foo; + reuse foo::<'a, false, (), ()> as bar; + } + + struct X; + impl<'a, A, const B: bool> Trait<'a, A, B> for X {} + + reuse ::foo as foo2; + reuse ::bar as bar2; + + pub fn check() { + assert_eq!(foo2::<'static, 'static, X, (), true, false, (), ()>(X, || 123), 123); + assert_eq!(bar2::<'static, X, (), true>(X, || 123), 123); + } +} + +// Testing impl Traits with SelfAndUserSpecified case. +mod test_3 { + trait Trait<'a, A, const B: bool> { + fn foo<'b, const B2: bool, T, U>(&self, f: impl FnOnce() -> usize) -> usize { + f() + } + } + + struct X; + impl<'a, A, const B: bool> Trait<'a, A, B> for X {} + + reuse Trait::foo; + reuse Trait::<'static, (), true>::foo:: as bar; + + pub fn check() { + assert_eq!(foo::<'static, X, (), true, false, (), ()>(&X, || 123), 123); + assert_eq!(bar::(&X, || 123), 123); + assert_eq!(bar(&X, || 123), 123); + } +} + +// FIXME(fn_delegation): rename Self generic param in recursive delegations +// mod test_4 { +// trait Trait<'a, A, const B: bool> { +// fn foo<'b, const B2: bool, T, U>(&self, f: impl FnOnce() -> usize) -> usize { +// f() +// } +// } + +// struct X; +// impl<'a, A, const B: bool> Trait<'a, A, B> for X {} + +// reuse Trait::foo; +// reuse Trait::<'static, (), true>::foo:: as bar; + +// trait Trait2 { +// reuse foo; +// reuse bar; +// } + +// reuse Trait2::foo as foo2; +// reuse Trait2::foo::<'static, X, (), true, false, (), ()> as foo3; +// reuse Trait2::bar as bar2; +// reuse Trait2::bar:: as bar3; + +// pub fn check() { +// assert_eq!(foo::<'static, X, (), true, false, (), ()>(&X, || 123), 123); +// assert_eq!(bar::(&X, || 123), 123); +// assert_eq!(bar(&X, || 123), 123); +// } +// } + +fn main() { + test_1::check(); + test_2::check(); + test_3::check(); + // test_4::check(); +} diff --git a/tests/ui/delegation/generics/unelided-lifetime-ice-154178.rs b/tests/ui/delegation/generics/unelided-lifetime-ice-154178.rs new file mode 100644 index 000000000000..3a53aad7132a --- /dev/null +++ b/tests/ui/delegation/generics/unelided-lifetime-ice-154178.rs @@ -0,0 +1,12 @@ +//@ compile-flags: -Z deduplicate-diagnostics=yes + +#![feature(fn_delegation)] + +fn foo<'b: 'b, const N: usize>() {} + +trait Trait { + reuse foo::<1>; + //~^ ERROR: function takes 1 lifetime argument but 0 lifetime arguments were supplied +} + +fn main() {} diff --git a/tests/ui/delegation/generics/unelided-lifetime-ice-154178.stderr b/tests/ui/delegation/generics/unelided-lifetime-ice-154178.stderr new file mode 100644 index 000000000000..3938e66d71c9 --- /dev/null +++ b/tests/ui/delegation/generics/unelided-lifetime-ice-154178.stderr @@ -0,0 +1,19 @@ +error[E0107]: function takes 1 lifetime argument but 0 lifetime arguments were supplied + --> $DIR/unelided-lifetime-ice-154178.rs:8:11 + | +LL | reuse foo::<1>; + | ^^^ expected 1 lifetime argument + | +note: function defined here, with 1 lifetime parameter: `'b` + --> $DIR/unelided-lifetime-ice-154178.rs:5:4 + | +LL | fn foo<'b: 'b, const N: usize>() {} + | ^^^ -- +help: add missing lifetime argument + | +LL | reuse foo::<'b, 1>; + | +++ + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0107`. diff --git a/tests/ui/delegation/glob-glob-conflict.rs b/tests/ui/delegation/glob-glob-conflict.rs index cb07a78b84fe..c1cd3f703e07 100644 --- a/tests/ui/delegation/glob-glob-conflict.rs +++ b/tests/ui/delegation/glob-glob-conflict.rs @@ -3,13 +3,10 @@ trait Trait1 { fn method(&self) -> u8; - //~^ ERROR: this function takes 1 argument but 0 arguments were supplied - //~| ERROR: mismatched types } trait Trait2 { fn method(&self) -> u8; - //~^ ERROR: this function takes 1 argument but 0 arguments were supplied - //~| ERROR: mismatched types + } trait Trait { fn method(&self) -> u8; @@ -28,10 +25,14 @@ fn method(&self) -> u8 { 2 } impl Trait for u8 { reuse Trait1::*; reuse Trait2::*; //~ ERROR duplicate definitions with name `method` + //~^ ERROR: this function takes 1 argument but 0 arguments were supplied + //~| ERROR: mismatched types } impl Trait for u16 { reuse Trait1::*; reuse Trait1::*; //~ ERROR duplicate definitions with name `method` + //~^ ERROR: this function takes 1 argument but 0 arguments were supplied + //~| ERROR: mismatched types } fn main() {} diff --git a/tests/ui/delegation/glob-glob-conflict.stderr b/tests/ui/delegation/glob-glob-conflict.stderr index 4259d71117b7..f55ee333630c 100644 --- a/tests/ui/delegation/glob-glob-conflict.stderr +++ b/tests/ui/delegation/glob-glob-conflict.stderr @@ -1,5 +1,5 @@ error[E0201]: duplicate definitions with name `method`: - --> $DIR/glob-glob-conflict.rs:30:5 + --> $DIR/glob-glob-conflict.rs:27:5 | LL | fn method(&self) -> u8; | ----------------------- item in trait @@ -10,7 +10,7 @@ LL | reuse Trait2::*; | ^^^^^^^^^^^^^^^^ duplicate definition error[E0201]: duplicate definitions with name `method`: - --> $DIR/glob-glob-conflict.rs:34:5 + --> $DIR/glob-glob-conflict.rs:33:5 | LL | fn method(&self) -> u8; | ----------------------- item in trait @@ -21,35 +21,35 @@ LL | reuse Trait1::*; | ^^^^^^^^^^^^^^^^ duplicate definition error[E0061]: this function takes 1 argument but 0 arguments were supplied - --> $DIR/glob-glob-conflict.rs:10:8 + --> $DIR/glob-glob-conflict.rs:27:19 | -LL | fn method(&self) -> u8; - | ^^^^^^ argument #1 of type `&_` is missing +LL | reuse Trait2::*; + | ^ argument #1 of type `&_` is missing | note: method defined here - --> $DIR/glob-glob-conflict.rs:10:8 + --> $DIR/glob-glob-conflict.rs:8:8 | LL | fn method(&self) -> u8; | ^^^^^^ ---- help: provide the argument | -LL | fn method(/* value */)(&self) -> u8; - | +++++++++++++ +LL | reuse Trait2::*(/* value */); + | +++++++++++++ error[E0308]: mismatched types - --> $DIR/glob-glob-conflict.rs:10:8 + --> $DIR/glob-glob-conflict.rs:27:19 | -LL | fn method(&self) -> u8; - | ^^^^^^- help: consider using a semicolon here: `;` - | | - | expected `()`, found `u8` - | expected `()` because of default return type +LL | reuse Trait2::*; + | ^- help: consider using a semicolon here: `;` + | | + | expected `()`, found `u8` + | expected `()` because of default return type error[E0061]: this function takes 1 argument but 0 arguments were supplied - --> $DIR/glob-glob-conflict.rs:5:8 + --> $DIR/glob-glob-conflict.rs:33:19 | -LL | fn method(&self) -> u8; - | ^^^^^^ argument #1 of type `&_` is missing +LL | reuse Trait1::*; + | ^ argument #1 of type `&_` is missing | note: method defined here --> $DIR/glob-glob-conflict.rs:5:8 @@ -58,17 +58,17 @@ LL | fn method(&self) -> u8; | ^^^^^^ ---- help: provide the argument | -LL | fn method(/* value */)(&self) -> u8; - | +++++++++++++ +LL | reuse Trait1::*(/* value */); + | +++++++++++++ error[E0308]: mismatched types - --> $DIR/glob-glob-conflict.rs:5:8 + --> $DIR/glob-glob-conflict.rs:33:19 | -LL | fn method(&self) -> u8; - | ^^^^^^- help: consider using a semicolon here: `;` - | | - | expected `()`, found `u8` - | expected `()` because of default return type +LL | reuse Trait1::*; + | ^- help: consider using a semicolon here: `;` + | | + | expected `()`, found `u8` + | expected `()` because of default return type error: aborting due to 6 previous errors diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155125.stderr b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155125.stderr new file mode 100644 index 000000000000..e8a32e340f3e --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155125.stderr @@ -0,0 +1,23 @@ +error[E0428]: the name `foo` is defined multiple times + --> $DIR/hir-crate-items-before-lowering-ices.rs:13:17 + | +LL | fn foo() {} + | -------- previous definition of the value `foo` here +LL | reuse foo; + | ^^^^^^^^^^ `foo` redefined here + | + = note: `foo` must be defined only once in the value namespace of this block + +error: complex const arguments must be placed inside of a `const` block + --> $DIR/hir-crate-items-before-lowering-ices.rs:11:13 + | +LL | / { +LL | | fn foo() {} +LL | | reuse foo; +LL | | 2 +LL | | }, + | |_____________^ + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0428`. diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155127.stderr b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155127.stderr new file mode 100644 index 000000000000..132e4e3034c4 --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155127.stderr @@ -0,0 +1,12 @@ +error: `#[deprecated]` attribute cannot be used on delegations + --> $DIR/hir-crate-items-before-lowering-ices.rs:27:9 + | +LL | #[deprecated] + | ^^^^^^^^^^^^^ + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements + = note: `#[deny(useless_deprecated)]` on by default + +error: aborting due to 1 previous error + diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155128.stderr b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155128.stderr new file mode 100644 index 000000000000..0a1b2c5a472c --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155128.stderr @@ -0,0 +1,24 @@ +error[E0061]: this function takes 0 arguments but 1 argument was supplied + --> $DIR/hir-crate-items-before-lowering-ices.rs:37:11 + | +LL | reuse a as b { + | ___________^______- +LL | | fn foo() {}; +LL | | foo +LL | | } + | |_____- unexpected argument of type `fn() {foo::<_>}` + | +note: function defined here + --> $DIR/hir-crate-items-before-lowering-ices.rs:35:8 + | +LL | fn a() {} + | ^ +help: remove the extra argument + | +LL - reuse a as b { +LL + reuse { + | + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0061`. diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155164.stderr b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155164.stderr new file mode 100644 index 000000000000..34d1a92ccd22 --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155164.stderr @@ -0,0 +1,13 @@ +error: complex const arguments must be placed inside of a `const` block + --> $DIR/hir-crate-items-before-lowering-ices.rs:47:13 + | +LL | / { +LL | | +LL | | struct W; +LL | | impl W { +... | +LL | | }, + | |_____________^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155202.stderr b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155202.stderr new file mode 100644 index 000000000000..28f045ca6944 --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.ice_155202.stderr @@ -0,0 +1,16 @@ +error[E0425]: cannot find value `async` in this scope + --> $DIR/hir-crate-items-before-lowering-ices.rs:66:13 + | +LL | async || {}; + | ^^^^^ not found in this scope + +error[E0308]: mismatched types + --> $DIR/hir-crate-items-before-lowering-ices.rs:66:22 + | +LL | async || {}; + | ^^ expected `bool`, found `()` + +error: aborting due to 2 previous errors + +Some errors have detailed explanations: E0308, E0425. +For more information about an error, try `rustc --explain E0308`. diff --git a/tests/ui/delegation/hir-crate-items-before-lowering-ices.rs b/tests/ui/delegation/hir-crate-items-before-lowering-ices.rs new file mode 100644 index 000000000000..6c16a1ae22d3 --- /dev/null +++ b/tests/ui/delegation/hir-crate-items-before-lowering-ices.rs @@ -0,0 +1,72 @@ +//@ revisions: ice_155125 ice_155127 ice_155128 ice_155164 ice_155202 + +#![feature(min_generic_const_args, fn_delegation)] +#![allow(incomplete_features)] + +#[cfg(ice_155125)] +mod ice_155125 { + struct S; + impl + S< + { //[ice_155125]~ ERROR: complex const arguments must be placed inside of a `const` block + fn foo() {} + reuse foo; //[ice_155125]~ ERROR: the name `foo` is defined multiple times + 2 + }, + > + { + } +} + +#[cfg(ice_155127)] +mod ice_155127 { + struct S; + + fn foo() {} + impl S { + #[deprecated] //[ice_155127]~ ERROR: `#[deprecated]` attribute cannot be used on delegations + //[ice_155127]~^ WARN: this was previously accepted by the compiler but is being phased out; + reuse foo; + } +} + +#[cfg(ice_155128)] +mod ice_155128 { + fn a() {} + + reuse a as b { //[ice_155128]~ ERROR: this function takes 0 arguments but 1 argument was supplied + fn foo() {}; + foo + } +} + +#[cfg(ice_155164)] +mod ice_155164 { + struct X { + inner: std::iter::Map< + { + //[ice_155164]~^ ERROR: complex const arguments must be placed inside of a `const` block + struct W; + impl W { + reuse Iterator::fold; + } + }, + F, + >, + } +} + +#[cfg(ice_155202)] +mod ice_155202 { + trait Trait { + fn bar(self); + } + impl Trait for () { + reuse Trait::bar { + async || {}; //[ice_155202]~ ERROR: mismatched types + //[ice_155202]~^ ERROR: cannot find value `async` in this scope + } + } +} + +fn main() {} diff --git a/tests/ui/delegation/impl-reuse-negative-traits.rs b/tests/ui/delegation/impl-reuse-negative-traits.rs index 7bcbc82f03db..8bc2b7270859 100644 --- a/tests/ui/delegation/impl-reuse-negative-traits.rs +++ b/tests/ui/delegation/impl-reuse-negative-traits.rs @@ -4,7 +4,6 @@ trait Trait { fn foo(&self); - //~^ ERROR negative impls cannot have any items [E0749] } struct S; @@ -15,5 +14,6 @@ fn foo(&self) {} struct F(S); reuse impl !Trait for F { &self.0 } +//~^ ERROR negative impls cannot have any items fn main() {} diff --git a/tests/ui/delegation/impl-reuse-negative-traits.stderr b/tests/ui/delegation/impl-reuse-negative-traits.stderr index 1be6ef715920..7510fdd89d7c 100644 --- a/tests/ui/delegation/impl-reuse-negative-traits.stderr +++ b/tests/ui/delegation/impl-reuse-negative-traits.stderr @@ -1,8 +1,8 @@ error[E0749]: negative impls cannot have any items - --> $DIR/impl-reuse-negative-traits.rs:6:8 + --> $DIR/impl-reuse-negative-traits.rs:16:1 | -LL | fn foo(&self); - | ^^^ +LL | reuse impl !Trait for F { &self.0 } + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 1 previous error diff --git a/tests/ui/delegation/impl-reuse-pass.rs b/tests/ui/delegation/impl-reuse-pass.rs index 90060b03f9ef..578e8c08e703 100644 --- a/tests/ui/delegation/impl-reuse-pass.rs +++ b/tests/ui/delegation/impl-reuse-pass.rs @@ -173,19 +173,6 @@ macro_rules! self_0_ref { ($self:ident) => { &$self.0 } } macro_rules! m { () => { M } } reuse impl Trait for m!() { self_0_ref!(self) } - struct S1(u8); - macro_rules! one_line_reuse { ($self:ident) => { reuse impl Trait for S1 { $self.0 } } } - one_line_reuse!(self); - - struct S2(u8); - macro_rules! one_line_reuse_expr { ($x:expr) => { reuse impl Trait for S2 { $x } } } - one_line_reuse_expr!(self.0); - - struct S3(u8); - macro_rules! s3 { () => { S3 } } - macro_rules! one_line_reuse_expr2 { ($x:expr) => { reuse impl Trait for s3!() { $x } } } - one_line_reuse_expr2!(self.0); - fn f() { let s = S(1); s.foo(); @@ -194,18 +181,6 @@ fn f() { let m = M(41); m.foo(); m.bar(); - - let s1 = S1(2); - s1.foo(); - s1.bar(); - - let s2 = S2(4); - s2.foo(); - s2.bar(); - - let s3 = S3(5); - s3.foo(); - s3.bar(); } } diff --git a/tests/ui/delegation/impl-reuse-self-hygiene.rs b/tests/ui/delegation/impl-reuse-self-hygiene.rs new file mode 100644 index 000000000000..b49e4419703a --- /dev/null +++ b/tests/ui/delegation/impl-reuse-self-hygiene.rs @@ -0,0 +1,28 @@ +#![allow(incomplete_features)] +#![feature(fn_delegation)] + +trait Trait { + fn foo(&self) -> u8 { 0 } + fn bar(&self) -> u8 { 1 } +} + +struct S1(u8); +macro_rules! one_line_reuse { ($self:ident) => { reuse impl Trait for S1 { $self.0 } } } +//~^ ERROR expected value, found module `self` +//~| ERROR expected value, found module `self` +one_line_reuse!(self); + +struct S2(u8); +macro_rules! one_line_reuse_expr { ($x:expr) => { reuse impl Trait for S2 { $x } } } +one_line_reuse_expr!(self.0); +//~^ ERROR expected value, found module `self` +//~| ERROR expected value, found module `self` + +struct S3(u8); +macro_rules! s3 { () => { S3 } } +macro_rules! one_line_reuse_expr2 { ($x:expr) => { reuse impl Trait for s3!() { $x } } } +one_line_reuse_expr2!(self.0); +//~^ ERROR expected value, found module `self` +//~| ERROR expected value, found module `self` + +fn main() {} diff --git a/tests/ui/delegation/impl-reuse-self-hygiene.stderr b/tests/ui/delegation/impl-reuse-self-hygiene.stderr new file mode 100644 index 000000000000..ae93829809e4 --- /dev/null +++ b/tests/ui/delegation/impl-reuse-self-hygiene.stderr @@ -0,0 +1,68 @@ +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:10:76 + | +LL | macro_rules! one_line_reuse { ($self:ident) => { reuse impl Trait for S1 { $self.0 } } } + | --------------------------^^^^^---- + | | | + | | `self` value is a keyword only available in methods with a `self` parameter + | `self` not allowed in an implementation +... +LL | one_line_reuse!(self); + | --------------------- in this macro invocation + | + = note: this error originates in the macro `one_line_reuse` (in Nightly builds, run with -Z macro-backtrace for more info) + +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:10:76 + | +LL | macro_rules! one_line_reuse { ($self:ident) => { reuse impl Trait for S1 { $self.0 } } } + | --------------------------^^^^^---- + | | | + | | `self` value is a keyword only available in methods with a `self` parameter + | `self` not allowed in an implementation +... +LL | one_line_reuse!(self); + | --------------------- in this macro invocation + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + = note: this error originates in the macro `one_line_reuse` (in Nightly builds, run with -Z macro-backtrace for more info) + +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:17:22 + | +LL | macro_rules! one_line_reuse_expr { ($x:expr) => { reuse impl Trait for S2 { $x } } } + | ------------------------------ `self` not allowed in an implementation +LL | one_line_reuse_expr!(self.0); + | ^^^^ `self` value is a keyword only available in methods with a `self` parameter + +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:17:22 + | +LL | macro_rules! one_line_reuse_expr { ($x:expr) => { reuse impl Trait for S2 { $x } } } + | ------------------------------ `self` not allowed in an implementation +LL | one_line_reuse_expr!(self.0); + | ^^^^ `self` value is a keyword only available in methods with a `self` parameter + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:24:23 + | +LL | macro_rules! one_line_reuse_expr2 { ($x:expr) => { reuse impl Trait for s3!() { $x } } } + | --------------------------------- `self` not allowed in an implementation +LL | one_line_reuse_expr2!(self.0); + | ^^^^ `self` value is a keyword only available in methods with a `self` parameter + +error[E0424]: expected value, found module `self` + --> $DIR/impl-reuse-self-hygiene.rs:24:23 + | +LL | macro_rules! one_line_reuse_expr2 { ($x:expr) => { reuse impl Trait for s3!() { $x } } } + | --------------------------------- `self` not allowed in an implementation +LL | one_line_reuse_expr2!(self.0); + | ^^^^ `self` value is a keyword only available in methods with a `self` parameter + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 6 previous errors + +For more information about this error, try `rustc --explain E0424`. diff --git a/tests/ui/issues/issue-4972.rs b/tests/ui/deref/box-pattern-trait-object-cannot-deref.rs similarity index 80% rename from tests/ui/issues/issue-4972.rs rename to tests/ui/deref/box-pattern-trait-object-cannot-deref.rs index 3f1c6f855007..a144fb360513 100644 --- a/tests/ui/issues/issue-4972.rs +++ b/tests/ui/deref/box-pattern-trait-object-cannot-deref.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/4972 + #![feature(box_patterns)] trait MyTrait { diff --git a/tests/ui/issues/issue-4972.stderr b/tests/ui/deref/box-pattern-trait-object-cannot-deref.stderr similarity index 85% rename from tests/ui/issues/issue-4972.stderr rename to tests/ui/deref/box-pattern-trait-object-cannot-deref.stderr index 8de3909ca305..451fbf4fbcd3 100644 --- a/tests/ui/issues/issue-4972.stderr +++ b/tests/ui/deref/box-pattern-trait-object-cannot-deref.stderr @@ -1,5 +1,5 @@ error[E0033]: type `Box<(dyn MyTrait + 'static)>` cannot be dereferenced - --> $DIR/issue-4972.rs:13:25 + --> $DIR/box-pattern-trait-object-cannot-deref.rs:15:25 | LL | TraitWrapper::A(box ref map) => map, | ^^^^^^^^^^^ type `Box<(dyn MyTrait + 'static)>` cannot be dereferenced diff --git a/tests/ui/issues/issue-27697.rs b/tests/ui/deref/deref-impl-for-dyn-trait.rs similarity index 81% rename from tests/ui/issues/issue-27697.rs rename to tests/ui/deref/deref-impl-for-dyn-trait.rs index 87ee190c01c4..4d15d05c45f5 100644 --- a/tests/ui/issues/issue-27697.rs +++ b/tests/ui/deref/deref-impl-for-dyn-trait.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/27697 + //@ check-pass use std::ops::Deref; diff --git a/tests/ui/issues/issue-16774.rs b/tests/ui/deref/deref-mut-closure-drop-order.rs similarity index 91% rename from tests/ui/issues/issue-16774.rs rename to tests/ui/deref/deref-mut-closure-drop-order.rs index bef7f0f975cf..b95ae68f1734 100644 --- a/tests/ui/issues/issue-16774.rs +++ b/tests/ui/deref/deref-mut-closure-drop-order.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/16774 + //@ run-pass #![feature(box_patterns)] diff --git a/tests/ui/issues/issue-26205.rs b/tests/ui/deref/deref-mut-method-through-box.rs similarity index 84% rename from tests/ui/issues/issue-26205.rs rename to tests/ui/deref/deref-mut-method-through-box.rs index de1846e3e017..984b6e55dbdc 100644 --- a/tests/ui/issues/issue-26205.rs +++ b/tests/ui/deref/deref-mut-method-through-box.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/26205 + //@ check-pass #![allow(dead_code)] use std::ops::{Deref, DerefMut}; diff --git a/tests/ui/issues/issue-22992-2.rs b/tests/ui/deref/deref-newtype-method-call.rs similarity index 73% rename from tests/ui/issues/issue-22992-2.rs rename to tests/ui/deref/deref-newtype-method-call.rs index c2edb4286585..9e773eb86692 100644 --- a/tests/ui/issues/issue-22992-2.rs +++ b/tests/ui/deref/deref-newtype-method-call.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/22992 + //@ run-pass struct A(B); struct B; diff --git a/tests/ui/issues/issue-24589.rs b/tests/ui/deref/deref-newtype-slice-coercion.rs similarity index 73% rename from tests/ui/issues/issue-24589.rs rename to tests/ui/deref/deref-newtype-slice-coercion.rs index e08e06a88b84..2947c9c36368 100644 --- a/tests/ui/issues/issue-24589.rs +++ b/tests/ui/deref/deref-newtype-slice-coercion.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/24589 + //@ run-pass pub struct _X([u8]); diff --git a/tests/ui/issues/issue-38381.rs b/tests/ui/deref/deref-target-in-fn-type.rs similarity index 62% rename from tests/ui/issues/issue-38381.rs rename to tests/ui/deref/deref-target-in-fn-type.rs index a51ee78eb76f..4a14d289ea30 100644 --- a/tests/ui/issues/issue-38381.rs +++ b/tests/ui/deref/deref-target-in-fn-type.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/38381 + //@ check-pass use std::ops::Deref; diff --git a/tests/ui/issues/issue-26186.rs b/tests/ui/deref/deref-to-dyn-fn-mut-callable.rs similarity index 95% rename from tests/ui/issues/issue-26186.rs rename to tests/ui/deref/deref-to-dyn-fn-mut-callable.rs index 225cfb4876aa..62a52fcd7cbf 100644 --- a/tests/ui/issues/issue-26186.rs +++ b/tests/ui/deref/deref-to-dyn-fn-mut-callable.rs @@ -1,3 +1,5 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/26186 + //@ check-pass use std::sync::Mutex; use std::cell::RefCell; diff --git a/tests/ui/deref/derefmut-closure-drop-order.rs b/tests/ui/deref/derefmut-closure-drop-order.rs new file mode 100644 index 000000000000..b95ae68f1734 --- /dev/null +++ b/tests/ui/deref/derefmut-closure-drop-order.rs @@ -0,0 +1,47 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/16774 + +//@ run-pass +#![feature(box_patterns)] + +use std::ops::{Deref, DerefMut}; + +struct X(Box); + +static mut DESTRUCTOR_RAN: bool = false; + +impl Drop for X { + fn drop(&mut self) { + unsafe { + assert!(!DESTRUCTOR_RAN); + DESTRUCTOR_RAN = true; + } + } +} + +impl Deref for X { + type Target = isize; + + fn deref(&self) -> &isize { + let &X(box ref x) = self; + x + } +} + +impl DerefMut for X { + fn deref_mut(&mut self) -> &mut isize { + let &mut X(box ref mut x) = self; + x + } +} + +fn main() { + { + let mut test = X(Box::new(5)); + { + let mut change = || { *test = 10 }; + change(); + } + assert_eq!(*test, 10); + } + assert!(unsafe { DESTRUCTOR_RAN }); +} diff --git a/tests/ui/derives/clone-vector-element-size.rs b/tests/ui/derives/clone-vector-element-size.rs new file mode 100644 index 000000000000..1f2965737245 --- /dev/null +++ b/tests/ui/derives/clone-vector-element-size.rs @@ -0,0 +1,17 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/104037. +//! LLVM used to hit an assertion "Vector elements must have same size" +//! when compiling derived Clone with MIR optimisation level of 3. + +//@ build-pass +//@ compile-flags: -Zmir-opt-level=3 -Copt-level=3 + +#[derive(Clone)] +pub struct Foo(Bar, u32); + +#[derive(Clone, Copy)] +pub struct Bar(u8, u8, u8); + +fn main() { + let foo: Vec = Vec::new(); + let _ = foo.clone(); +} diff --git a/tests/ui/diagnostic-flags/deduplicate-diagnostics.deduplicate.stderr b/tests/ui/diagnostic-flags/deduplicate-diagnostics.deduplicate.stderr index 327b1308d8fd..c0d568eb5384 100644 --- a/tests/ui/diagnostic-flags/deduplicate-diagnostics.deduplicate.stderr +++ b/tests/ui/diagnostic-flags/deduplicate-diagnostics.deduplicate.stderr @@ -1,30 +1,15 @@ +error[E0452]: malformed lint attribute input + --> $DIR/deduplicate-diagnostics.rs:10:8 + | +LL | #[deny("literal")] + | ^^^^^^^^^ bad attribute argument + error: cannot find derive macro `Unresolved` in this scope --> $DIR/deduplicate-diagnostics.rs:6:10 | LL | #[derive(Unresolved)] | ^^^^^^^^^^ -error[E0539]: malformed `deny` attribute input - --> $DIR/deduplicate-diagnostics.rs:10:1 - | -LL | #[deny("literal")] - | ^^^^^^^---------^^ - | | - | expected a valid identifier here - | - = note: for more information, visit -help: try changing it to one of the following valid forms of the attribute - | -LL - #[deny("literal")] -LL + #[deny(lint1)] - | -LL - #[deny("literal")] -LL + #[deny(lint1, lint2, ...)] - | -LL - #[deny("literal")] -LL + #[deny(lint1, lint2, lint3, reason = "...")] - | - error: aborting due to 2 previous errors -For more information about this error, try `rustc --explain E0539`. +For more information about this error, try `rustc --explain E0452`. diff --git a/tests/ui/diagnostic-flags/deduplicate-diagnostics.duplicate.stderr b/tests/ui/diagnostic-flags/deduplicate-diagnostics.duplicate.stderr index de9780ec2f57..74d7066293f3 100644 --- a/tests/ui/diagnostic-flags/deduplicate-diagnostics.duplicate.stderr +++ b/tests/ui/diagnostic-flags/deduplicate-diagnostics.duplicate.stderr @@ -1,3 +1,9 @@ +error[E0452]: malformed lint attribute input + --> $DIR/deduplicate-diagnostics.rs:10:8 + | +LL | #[deny("literal")] + | ^^^^^^^^^ bad attribute argument + error: cannot find derive macro `Unresolved` in this scope --> $DIR/deduplicate-diagnostics.rs:6:10 | @@ -12,27 +18,22 @@ LL | #[derive(Unresolved)] | = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` -error[E0539]: malformed `deny` attribute input - --> $DIR/deduplicate-diagnostics.rs:10:1 +error[E0452]: malformed lint attribute input + --> $DIR/deduplicate-diagnostics.rs:10:8 | LL | #[deny("literal")] - | ^^^^^^^---------^^ - | | - | expected a valid identifier here - | - = note: for more information, visit -help: try changing it to one of the following valid forms of the attribute - | -LL - #[deny("literal")] -LL + #[deny(lint1)] - | -LL - #[deny("literal")] -LL + #[deny(lint1, lint2, ...)] - | -LL - #[deny("literal")] -LL + #[deny(lint1, lint2, lint3, reason = "...")] + | ^^^^^^^^^ bad attribute argument | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` -error: aborting due to 3 previous errors +error[E0452]: malformed lint attribute input + --> $DIR/deduplicate-diagnostics.rs:10:8 + | +LL | #[deny("literal")] + | ^^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` -For more information about this error, try `rustc --explain E0539`. +error: aborting due to 5 previous errors + +For more information about this error, try `rustc --explain E0452`. diff --git a/tests/ui/diagnostic-flags/deduplicate-diagnostics.rs b/tests/ui/diagnostic-flags/deduplicate-diagnostics.rs index 387a1085d7ed..48705266e358 100644 --- a/tests/ui/diagnostic-flags/deduplicate-diagnostics.rs +++ b/tests/ui/diagnostic-flags/deduplicate-diagnostics.rs @@ -7,5 +7,7 @@ //[duplicate]~| ERROR cannot find derive macro `Unresolved` in this scope struct S; -#[deny("literal")] //~ ERROR malformed `deny` attribute input [E0539] +#[deny("literal")] //~ ERROR malformed lint attribute input + //[duplicate]~| ERROR malformed lint attribute input + //[duplicate]~| ERROR malformed lint attribute input fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_const/it_works_foreign.rs b/tests/ui/diagnostic_namespace/on_const/it_works_foreign.rs index 0888ee096ff4..3524ee6ad53c 100644 --- a/tests/ui/diagnostic_namespace/on_const/it_works_foreign.rs +++ b/tests/ui/diagnostic_namespace/on_const/it_works_foreign.rs @@ -8,9 +8,7 @@ const _: () = { let x = X; x == x; - //~^ ERROR: their message - //~| NOTE: their label - //~| NOTE: trait `PartialEq` is implemented but not `const` - //~| NOTE: their note - //~| NOTE: their other note + //~^ ERROR: cannot call non-const operator in constants + //~| NOTE: impl defined here, but it is not `const` + //~| NOTE: limited to constant functions }; diff --git a/tests/ui/diagnostic_namespace/on_const/it_works_foreign.stderr b/tests/ui/diagnostic_namespace/on_const/it_works_foreign.stderr index ad9b2364f21f..0d901a6458c8 100644 --- a/tests/ui/diagnostic_namespace/on_const/it_works_foreign.stderr +++ b/tests/ui/diagnostic_namespace/on_const/it_works_foreign.stderr @@ -1,17 +1,16 @@ -error[E0277]: their message +error[E0015]: cannot call non-const operator in constants --> $DIR/it_works_foreign.rs:10:5 | LL | x == x; - | ^^^^^^ their label + | ^^^^^^ | -note: trait `PartialEq` is implemented but not `const` +note: impl defined here, but it is not `const` --> $DIR/auxiliary/non_const_impl.rs:11:1 | LL | impl PartialEq for X { | ^^^^^^^^^^^^^^^^^^^^ - = note: their note - = note: their other note + = note: calls in constants are limited to constant functions, tuple structs and tuple variants error: aborting due to 1 previous error -For more information about this error, try `rustc --explain E0277`. +For more information about this error, try `rustc --explain E0015`. diff --git a/tests/ui/diagnostic_namespace/on_const/it_works_local.rs b/tests/ui/diagnostic_namespace/on_const/it_works_local.rs index 176fe8d01d35..143899001a75 100644 --- a/tests/ui/diagnostic_namespace/on_const/it_works_local.rs +++ b/tests/ui/diagnostic_namespace/on_const/it_works_local.rs @@ -10,6 +10,7 @@ note = "my other note" )] impl PartialEq for X { + //~^ NOTE: impl defined here, but it is not `const` fn eq(&self, _other: &X) -> bool { true } @@ -18,8 +19,6 @@ fn eq(&self, _other: &X) -> bool { const _: () = { let x = X; x == x; - //~^ ERROR: my message - //~| NOTE: my label - //~| NOTE: my note - //~| NOTE: my other note + //~^ ERROR: cannot call non-const operator in constants + //~| NOTE: limited to constant functions }; diff --git a/tests/ui/diagnostic_namespace/on_const/it_works_local.stderr b/tests/ui/diagnostic_namespace/on_const/it_works_local.stderr index 0db90fac1639..8c4abe0553a6 100644 --- a/tests/ui/diagnostic_namespace/on_const/it_works_local.stderr +++ b/tests/ui/diagnostic_namespace/on_const/it_works_local.stderr @@ -1,12 +1,16 @@ -error[E0277]: my message - --> $DIR/it_works_local.rs:20:5 +error[E0015]: cannot call non-const operator in constants + --> $DIR/it_works_local.rs:21:5 | LL | x == x; - | ^^^^^^ my label + | ^^^^^^ | - = note: my note - = note: my other note +note: impl defined here, but it is not `const` + --> $DIR/it_works_local.rs:12:1 + | +LL | impl PartialEq for X { + | ^^^^^^^^^^^^^^^^^^^^ + = note: calls in constants are limited to constant functions, tuple structs and tuple variants error: aborting due to 1 previous error -For more information about this error, try `rustc --explain E0277`. +For more information about this error, try `rustc --explain E0015`. diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.rs b/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.rs index 2050403210d5..2118adc57c45 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.rs +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.rs @@ -1,7 +1,7 @@ #![feature(diagnostic_on_move)] #[diagnostic::on_move = "foo"] -//~^WARN missing options for `on_move` attribute [malformed_diagnostic_attributes] +//~^WARN malformed `diagnostic::on_move` attribute [malformed_diagnostic_attributes] struct Foo; fn takes_foo(_: Foo) {} diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.stderr b/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.stderr index 39992b02e580..ba53ad3a9271 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.stderr +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_invalid_meta_item_syntax.stderr @@ -1,10 +1,10 @@ -warning: missing options for `on_move` attribute +warning: malformed `diagnostic::on_move` attribute --> $DIR/report_warning_on_invalid_meta_item_syntax.rs:3:1 | LL | #[diagnostic::on_move = "foo"] - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ invalid option found here | - = help: at least one of the `message`, `note` and `label` options are expected + = help: only `message`, `note` and `label` are allowed as options = note: `#[warn(malformed_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default error[E0382]: use of moved value: `foo` diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.rs b/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.rs index e5603fd24ec9..efe728d43195 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.rs +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.rs @@ -1,7 +1,7 @@ #![feature(diagnostic_on_move)] #[diagnostic::on_move] -//~^WARN missing options for `on_move` attribute [malformed_diagnostic_attributes] +//~^WARN missing options for `diagnostic::on_move` attribute [malformed_diagnostic_attributes] struct Foo; fn takes_foo(_: Foo) {} diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.stderr b/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.stderr index f4e6d69faecb..b885d72028c4 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.stderr +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_missing_options.stderr @@ -1,4 +1,4 @@ -warning: missing options for `on_move` attribute +warning: missing options for `diagnostic::on_move` attribute --> $DIR/report_warning_on_missing_options.rs:3:1 | LL | #[diagnostic::on_move] diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.rs b/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.rs index 651f6184cfac..3f25b4e264b7 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.rs +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.rs @@ -4,8 +4,8 @@ message = "Foo", label = "Bar", baz="Baz" - //~^WARN unknown or malformed `on_move` attribute - //~|HELP only `message`, `note` and `label` are allowed as options. Their values must be string literals + //~^WARN malformed `diagnostic::on_move` attribute + //~|HELP only `message`, `note` and `label` are allowed as options )] struct Foo; diff --git a/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.stderr b/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.stderr index a09b8a96d2d1..6af2e0850bab 100644 --- a/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.stderr +++ b/tests/ui/diagnostic_namespace/on_move/report_warning_on_unknown_options.stderr @@ -1,10 +1,10 @@ -warning: unknown or malformed `on_move` attribute +warning: malformed `diagnostic::on_move` attribute --> $DIR/report_warning_on_unknown_options.rs:6:5 | LL | baz="Baz" | ^^^^^^^^^ invalid option found here | - = help: only `message`, `note` and `label` are allowed as options. Their values must be string literals + = help: only `message`, `note` and `label` are allowed as options = note: `#[warn(malformed_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default error[E0382]: Foo diff --git a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.rs b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.rs index 09c2a05cd009..e3c38c7f55c9 100644 --- a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.rs +++ b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.rs @@ -4,19 +4,19 @@ //@ reference: attributes.diagnostic.on_unimplemented.invalid-formats #[diagnostic::on_unimplemented( on(Self = "&str"), - //~^WARN malformed `on_unimplemented` attribute + //~^WARN malformed `diagnostic::on_unimplemented` attribute message = "trait has `{Self}` and `{T}` as params", label = "trait has `{Self}` and `{T}` as params", note = "trait has `{Self}` and `{T}` as params", parent_label = "in this scope", - //~^WARN malformed `on_unimplemented` attribute + //~^WARN malformed `diagnostic::on_unimplemented` attribute append_const_msg - //~^WARN malformed `on_unimplemented` attribute + //~^WARN malformed `diagnostic::on_unimplemented` attribute )] trait Foo {} #[diagnostic::on_unimplemented = "Message"] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait Bar {} #[diagnostic::on_unimplemented(message = "Not allowed to apply it on a impl")] diff --git a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.stderr b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.stderr index 58d2bdbfc4d6..65d92e4592d0 100644 --- a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.stderr +++ b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_accept_options_of_the_internal_rustc_attribute.stderr @@ -119,7 +119,7 @@ LL | label = "{float}{_Self}{crate_local}{Trait}{ItemContext}{This}" | = help: expect either a generic argument name or `{Self}` as format argument -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_accept_options_of_the_internal_rustc_attribute.rs:6:5 | LL | on(Self = "&str"), @@ -128,7 +128,7 @@ LL | on(Self = "&str"), = help: only `message`, `note` and `label` are allowed as options = note: `#[warn(malformed_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_accept_options_of_the_internal_rustc_attribute.rs:11:5 | LL | parent_label = "in this scope", @@ -136,7 +136,7 @@ LL | parent_label = "in this scope", | = help: only `message`, `note` and `label` are allowed as options -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_accept_options_of_the_internal_rustc_attribute.rs:13:5 | LL | append_const_msg @@ -144,7 +144,7 @@ LL | append_const_msg | = help: only `message`, `note` and `label` are allowed as options -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_accept_options_of_the_internal_rustc_attribute.rs:18:1 | LL | #[diagnostic::on_unimplemented = "Message"] diff --git a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.rs b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.rs index c759acc12565..14763d21a2be 100644 --- a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.rs +++ b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.rs @@ -1,7 +1,7 @@ //@ reference: attributes.diagnostic.on_unimplemented.syntax //@ reference: attributes.diagnostic.on_unimplemented.unknown-keys #[diagnostic::on_unimplemented(unsupported = "foo")] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait Foo {} #[diagnostic::on_unimplemented(message = "Baz")] @@ -9,23 +9,23 @@ trait Foo {} struct Bar {} #[diagnostic::on_unimplemented(message = "Boom", unsupported = "Bar")] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait Baz {} #[diagnostic::on_unimplemented(message = "Boom", on(Self = "i32", message = "whatever"))] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait Boom {} #[diagnostic::on_unimplemented(message = "Boom", on(_Self = "i32", message = "whatever"))] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait _Self {} #[diagnostic::on_unimplemented = "boom"] -//~^WARN malformed `on_unimplemented` attribute +//~^WARN malformed `diagnostic::on_unimplemented` attribute trait Doom {} #[diagnostic::on_unimplemented] -//~^WARN missing options for `on_unimplemented` attribute +//~^WARN missing options for `diagnostic::on_unimplemented` attribute trait Whatever {} #[diagnostic::on_unimplemented(message = "{DoesNotExist}")] diff --git a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.stderr b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.stderr index 4361e3261a0c..14d3c0db1ec9 100644 --- a/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.stderr +++ b/tests/ui/diagnostic_namespace/on_unimplemented/do_not_fail_parsing_on_invalid_options_1.stderr @@ -15,7 +15,7 @@ LL | #[diagnostic::on_unimplemented(message = "{DoesNotExist}")] = help: expect either a generic argument name or `{Self}` as format argument = note: `#[warn(malformed_diagnostic_format_literals)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:3:32 | LL | #[diagnostic::on_unimplemented(unsupported = "foo")] @@ -24,7 +24,7 @@ LL | #[diagnostic::on_unimplemented(unsupported = "foo")] = help: only `message`, `note` and `label` are allowed as options = note: `#[warn(malformed_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:11:50 | LL | #[diagnostic::on_unimplemented(message = "Boom", unsupported = "Bar")] @@ -32,7 +32,7 @@ LL | #[diagnostic::on_unimplemented(message = "Boom", unsupported = "Bar")] | = help: only `message`, `note` and `label` are allowed as options -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:15:50 | LL | #[diagnostic::on_unimplemented(message = "Boom", on(Self = "i32", message = "whatever"))] @@ -40,7 +40,7 @@ LL | #[diagnostic::on_unimplemented(message = "Boom", on(Self = "i32", message = | = help: only `message`, `note` and `label` are allowed as options -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:19:50 | LL | #[diagnostic::on_unimplemented(message = "Boom", on(_Self = "i32", message = "whatever"))] @@ -48,7 +48,7 @@ LL | #[diagnostic::on_unimplemented(message = "Boom", on(_Self = "i32", message | = help: only `message`, `note` and `label` are allowed as options -warning: malformed `on_unimplemented` attribute +warning: malformed `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:23:1 | LL | #[diagnostic::on_unimplemented = "boom"] @@ -56,7 +56,7 @@ LL | #[diagnostic::on_unimplemented = "boom"] | = help: only `message`, `note` and `label` are allowed as options -warning: missing options for `on_unimplemented` attribute +warning: missing options for `diagnostic::on_unimplemented` attribute --> $DIR/do_not_fail_parsing_on_invalid_options_1.rs:27:1 | LL | #[diagnostic::on_unimplemented] diff --git a/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.rs b/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.rs new file mode 100644 index 000000000000..b8852e7dd216 --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.rs @@ -0,0 +1,52 @@ +//@ run-pass +#![allow(dead_code, unused_imports)] +#![feature(diagnostic_on_unknown)] + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +extern crate std as other_std; + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +const CONST: () = (); + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +static STATIC: () = (); + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +type Type = (); + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +enum Enum {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +impl Enum {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +extern "C" {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +fn fun() {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +struct Struct {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +trait Trait {} + +#[diagnostic::on_unknown(message = "foo")] +//~^WARN `#[diagnostic::on_unknown]` can only be applied to `use` statements +impl Trait for i32 {} + +#[diagnostic::on_unknown(message = "foo")] +use std::str::FromStr; + +fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.stderr b/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.stderr new file mode 100644 index 000000000000..33636e1fcfc3 --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/incorrect-locations.stderr @@ -0,0 +1,103 @@ +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:5:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | extern crate std as other_std; + | ----------------------------- not an import + | + = note: `#[warn(misplaced_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:9:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | const CONST: () = (); + | --------------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:13:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | static STATIC: () = (); + | ----------------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:17:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | type Type = (); + | --------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:21:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | enum Enum {} + | --------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:25:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | impl Enum {} + | --------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:29:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | extern "C" {} + | ------------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:33:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | fn fun() {} + | -------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:37:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | struct Struct {} + | ------------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:41:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | trait Trait {} + | ----------- not an import + +warning: `#[diagnostic::on_unknown]` can only be applied to `use` statements + --> $DIR/incorrect-locations.rs:45:1 + | +LL | #[diagnostic::on_unknown(message = "foo")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | +LL | impl Trait for i32 {} + | ------------------ not an import + +warning: 11 warnings emitted + diff --git a/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.rs b/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.rs new file mode 100644 index 000000000000..cdf0f1e89efc --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.rs @@ -0,0 +1,33 @@ +#![feature(diagnostic_on_unknown)] + +#[diagnostic::on_unknown(message = "foo {}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist; +//~^ ERROR: foo {} + +#[diagnostic::on_unknown(message = "foo {A}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist2; +//~^ ERROR: foo {} + +#[diagnostic::on_unknown(label = "foo {}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist3; +//~^ ERROR: unresolved import `std::does_not_exist3` + +#[diagnostic::on_unknown(label = "foo {A}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist4; +//~^ ERROR: unresolved import `std::does_not_exist4` + +#[diagnostic::on_unknown(note = "foo {}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist5; +//~^ ERROR: unresolved import `std::does_not_exist5` + +#[diagnostic::on_unknown(note = "foo {A}")] +//~^ WARN: format arguments are not allowed here +use std::does_not_exist6; +//~^ ERROR: unresolved import `std::does_not_exist6` + +fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.stderr b/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.stderr new file mode 100644 index 000000000000..2b942338ffb4 --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/incorrect_format_string.stderr @@ -0,0 +1,96 @@ +error[E0432]: foo {} + --> $DIR/incorrect_format_string.rs:5:5 + | +LL | use std::does_not_exist; + | ^^^^^^^^^^^^^^^^^^^ no `does_not_exist` in the root + | + = note: unresolved import `std::does_not_exist` + +error[E0432]: foo {} + --> $DIR/incorrect_format_string.rs:10:5 + | +LL | use std::does_not_exist2; + | ^^^^^^^^^^^^^^^^^^^^ no `does_not_exist2` in the root + | + = note: unresolved import `std::does_not_exist2` + +error[E0432]: unresolved import `std::does_not_exist3` + --> $DIR/incorrect_format_string.rs:15:5 + | +LL | use std::does_not_exist3; + | ^^^^^^^^^^^^^^^^^^^^ foo {} + +error[E0432]: unresolved import `std::does_not_exist4` + --> $DIR/incorrect_format_string.rs:20:5 + | +LL | use std::does_not_exist4; + | ^^^^^^^^^^^^^^^^^^^^ foo {} + +error[E0432]: unresolved import `std::does_not_exist5` + --> $DIR/incorrect_format_string.rs:25:5 + | +LL | use std::does_not_exist5; + | ^^^^^^^^^^^^^^^^^^^^ no `does_not_exist5` in the root + | + = note: foo {} + +error[E0432]: unresolved import `std::does_not_exist6` + --> $DIR/incorrect_format_string.rs:30:5 + | +LL | use std::does_not_exist6; + | ^^^^^^^^^^^^^^^^^^^^ no `does_not_exist6` in the root + | + = note: foo {} + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:3:42 + | +LL | #[diagnostic::on_unknown(message = "foo {}")] + | ^ + | + = help: consider removing this format argument + = note: `#[warn(malformed_diagnostic_format_literals)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:8:42 + | +LL | #[diagnostic::on_unknown(message = "foo {A}")] + | ^ + | + = help: consider removing this format argument + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:13:40 + | +LL | #[diagnostic::on_unknown(label = "foo {}")] + | ^ + | + = help: consider removing this format argument + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:18:40 + | +LL | #[diagnostic::on_unknown(label = "foo {A}")] + | ^ + | + = help: consider removing this format argument + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:23:39 + | +LL | #[diagnostic::on_unknown(note = "foo {}")] + | ^ + | + = help: consider removing this format argument + +warning: format arguments are not allowed here + --> $DIR/incorrect_format_string.rs:28:39 + | +LL | #[diagnostic::on_unknown(note = "foo {A}")] + | ^ + | + = help: consider removing this format argument + +error: aborting due to 6 previous errors; 6 warnings emitted + +For more information about this error, try `rustc --explain E0432`. diff --git a/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.rs b/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.rs new file mode 100644 index 000000000000..ee91eb7c7300 --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.rs @@ -0,0 +1,19 @@ +#![feature(diagnostic_on_unknown)] +#[diagnostic::on_unknown] +//~^WARN missing options for `diagnostic::on_unknown` attribute +use std::str::FromStr; + +#[diagnostic::on_unknown(foo = "bar", message = "foo")] +//~^WARN malformed `diagnostic::on_unknown` attribute +use std::str::Bytes; + +#[diagnostic::on_unknown(label = "foo", label = "bar")] +//~^WARN `label` is ignored due to previous definition of `label` +use std::str::Chars; + +#[diagnostic::on_unknown(message = "Foo", message = "Bar")] +//~^WARN `message` is ignored due to previous definition of `message` +use std::str::NotExisting; +//~^ERROR Foo + +fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.stderr b/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.stderr new file mode 100644 index 000000000000..a949ace4198d --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/malformed_attribute.stderr @@ -0,0 +1,44 @@ +error[E0432]: Foo + --> $DIR/malformed_attribute.rs:16:5 + | +LL | use std::str::NotExisting; + | ^^^^^^^^^^^^^^^^^^^^^ no `NotExisting` in `str` + | + = note: unresolved import `std::str::NotExisting` + +warning: missing options for `diagnostic::on_unknown` attribute + --> $DIR/malformed_attribute.rs:2:1 + | +LL | #[diagnostic::on_unknown] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = help: at least one of the `message`, `note` and `label` options are expected + = note: `#[warn(malformed_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default + +warning: malformed `diagnostic::on_unknown` attribute + --> $DIR/malformed_attribute.rs:6:26 + | +LL | #[diagnostic::on_unknown(foo = "bar", message = "foo")] + | ^^^^^^^^^^^ invalid option found here + | + = help: only `message`, `note` and `label` are allowed as options + +warning: `label` is ignored due to previous definition of `label` + --> $DIR/malformed_attribute.rs:10:41 + | +LL | #[diagnostic::on_unknown(label = "foo", label = "bar")] + | ------------- ^^^^^^^^^^^^^ `label` is later redundantly declared here + | | + | `label` is first declared here + +warning: `message` is ignored due to previous definition of `message` + --> $DIR/malformed_attribute.rs:14:43 + | +LL | #[diagnostic::on_unknown(message = "Foo", message = "Bar")] + | --------------- ^^^^^^^^^^^^^^^ `message` is later redundantly declared here + | | + | `message` is first declared here + +error: aborting due to 1 previous error; 4 warnings emitted + +For more information about this error, try `rustc --explain E0432`. diff --git a/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.rs b/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.rs new file mode 100644 index 000000000000..3ccf2fc5f6ca --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.rs @@ -0,0 +1,48 @@ +#![feature(diagnostic_on_unknown)] + +mod test1 { + #[diagnostic::on_unknown( + message = "custom message", + label = "custom label", + note = "custom note" + )] + use std::vec::{NonExisting, Vec, Whatever}; + //~^ ERROR: custom message +} + +mod test2 { + #[diagnostic::on_unknown( + message = "custom message", + label = "custom label", + note = "custom note" + )] + use std::{Whatever, vec::NonExisting, vec::Vec, *}; + //~^ ERROR: custom message +} + +mod test3 { + #[diagnostic::on_unknown( + message = "custom message", + label = "custom label", + note = "custom note" + )] + use std::{ + string::String, + vec::{NonExisting, Vec}, + //~^ ERROR: custom message + }; +} + +mod test4 { + #[diagnostic::on_unknown( + message = "custom message", + label = "custom label", + note = "custom note" + )] + use std::{ + string::String, + vec::{Vec, non_existing::*}, + //~^ ERROR: custom message + }; +} +fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.stderr b/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.stderr new file mode 100644 index 000000000000..fcce77f6aebb --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/multiple_errors.stderr @@ -0,0 +1,43 @@ +error[E0432]: custom message + --> $DIR/multiple_errors.rs:9:20 + | +LL | use std::vec::{NonExisting, Vec, Whatever}; + | ^^^^^^^^^^^ ^^^^^^^^ custom label + | | + | custom label + | + = note: unresolved imports `std::vec::NonExisting`, `std::vec::Whatever` + = note: custom note + +error[E0432]: custom message + --> $DIR/multiple_errors.rs:19:15 + | +LL | use std::{Whatever, vec::NonExisting, vec::Vec, *}; + | ^^^^^^^^ ^^^^^^^^^^^^^^^^ custom label + | | + | custom label + | + = note: unresolved imports `std::Whatever`, `std::vec::NonExisting` + = note: custom note + +error[E0432]: custom message + --> $DIR/multiple_errors.rs:31:15 + | +LL | vec::{NonExisting, Vec}, + | ^^^^^^^^^^^ custom label + | + = note: unresolved import `std::vec::NonExisting` + = note: custom note + +error[E0432]: custom message + --> $DIR/multiple_errors.rs:44:20 + | +LL | vec::{Vec, non_existing::*}, + | ^^^^^^^^^^^^ custom label + | + = note: unresolved import `std::vec::non_existing` + = note: custom note + +error: aborting due to 4 previous errors + +For more information about this error, try `rustc --explain E0432`. diff --git a/tests/ui/diagnostic_namespace/on_unknown/unknown_import.rs b/tests/ui/diagnostic_namespace/on_unknown/unknown_import.rs new file mode 100644 index 000000000000..f2b0f059bb0a --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/unknown_import.rs @@ -0,0 +1,17 @@ +#![feature(diagnostic_on_unknown)] +pub mod foo { + pub struct Bar; +} + +#[diagnostic::on_unknown( + message = "first message", + label = "first label", + note = "custom note", + note = "custom note 2" +)] +use foo::Foo; +//~^ERROR first message + +use foo::Bar; + +fn main() {} diff --git a/tests/ui/diagnostic_namespace/on_unknown/unknown_import.stderr b/tests/ui/diagnostic_namespace/on_unknown/unknown_import.stderr new file mode 100644 index 000000000000..a9867fd74bfb --- /dev/null +++ b/tests/ui/diagnostic_namespace/on_unknown/unknown_import.stderr @@ -0,0 +1,13 @@ +error[E0432]: first message + --> $DIR/unknown_import.rs:12:5 + | +LL | use foo::Foo; + | ^^^^^^^^ first label + | + = note: unresolved import `foo::Foo` + = note: custom note + = note: custom note 2 + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0432`. diff --git a/tests/ui/did_you_mean/issue-43871-enum-instead-of-variant.stderr b/tests/ui/did_you_mean/issue-43871-enum-instead-of-variant.stderr index 9dde5b3ebe30..6df485851e04 100644 --- a/tests/ui/did_you_mean/issue-43871-enum-instead-of-variant.stderr +++ b/tests/ui/did_you_mean/issue-43871-enum-instead-of-variant.stderr @@ -2,15 +2,20 @@ error[E0532]: expected tuple struct or tuple variant, found enum `Option` --> $DIR/issue-43871-enum-instead-of-variant.rs:21:12 | LL | if let Option(_) = x { - | ^^^^^^ help: try to match against one of the enum's variants: `std::option::Option::Some` + | ^^^^^^ | = help: you might have meant to match against the enum's non-tuple variant +help: try to match against one of the enum's variants + | +LL - if let Option(_) = x { +LL + if let std::option::Option::Some(_) = x { + | error[E0532]: expected tuple struct or tuple variant, found enum `Example` --> $DIR/issue-43871-enum-instead-of-variant.rs:27:12 | LL | if let Example(_) = y { - | ^^^^^^^ help: try to match against one of the enum's variants: `Example::Ex` + | ^^^^^^^ | = help: you might have meant to match against the enum's non-tuple variant note: the enum is defined here @@ -18,14 +23,23 @@ note: the enum is defined here | LL | enum Example { Ex(String), NotEx } | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +help: try to match against one of the enum's variants + | +LL | if let Example::Ex(_) = y { + | ++++ error[E0423]: expected function, tuple struct or tuple variant, found enum `Option` --> $DIR/issue-43871-enum-instead-of-variant.rs:19:13 | LL | let x = Option(1); - | ^^^^^^ help: try to construct one of the enum's variants: `std::option::Option::Some` + | ^^^^^^ | = help: you might have meant to construct the enum's non-tuple variant +help: try to construct one of the enum's variants + | +LL - let x = Option(1); +LL + let x = std::option::Option::Some(1); + | error[E0423]: expected function, tuple struct or tuple variant, found enum `Void` --> $DIR/issue-43871-enum-instead-of-variant.rs:31:13 diff --git a/tests/ui/eii/attribute_targets.stderr b/tests/ui/eii/attribute_targets.stderr index bf04c323c95c..8166609e1974 100644 --- a/tests/ui/eii/attribute_targets.stderr +++ b/tests/ui/eii/attribute_targets.stderr @@ -1,106 +1,106 @@ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:7:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:9:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:13:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:15:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:21:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:23:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:27:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:29:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:32:5 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:34:5 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:39:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:41:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:44:5 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:46:5 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:51:1 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:53:1 | LL | #[eii] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/attribute_targets.rs:56:5 | LL | #[foo] | ^^^^^^ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/attribute_targets.rs:58:5 | LL | #[eii] diff --git a/tests/ui/eii/default/call_default.rs b/tests/ui/eii/default/call_default.rs index b60a1dd0b215..8806c7fa7d8c 100644 --- a/tests/ui/eii/default/call_default.rs +++ b/tests/ui/eii/default/call_default.rs @@ -3,7 +3,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests EIIs with default implementations. // When there's no explicit declaration, the default should be called from the declaring crate. diff --git a/tests/ui/eii/default/call_default_panics.rs b/tests/ui/eii/default/call_default_panics.rs index 96b2742aa8e0..db664e0cbcb0 100644 --- a/tests/ui/eii/default/call_default_panics.rs +++ b/tests/ui/eii/default/call_default_panics.rs @@ -5,7 +5,7 @@ //@ needs-unwind //@ exec-env:RUST_BACKTRACE=1 //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // A small test to make sure that unwinding works properly. // diff --git a/tests/ui/eii/default/call_impl.rs b/tests/ui/eii/default/call_impl.rs index b88769757489..1a972774beae 100644 --- a/tests/ui/eii/default/call_impl.rs +++ b/tests/ui/eii/default/call_impl.rs @@ -4,7 +4,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests EIIs with default implementations. // When an explicit implementation is given in one dependency, and the declaration is in another, diff --git a/tests/ui/eii/default/local_crate.rs b/tests/ui/eii/default/local_crate.rs index d98c2fac4234..fd4fd459c52f 100644 --- a/tests/ui/eii/default/local_crate.rs +++ b/tests/ui/eii/default/local_crate.rs @@ -1,7 +1,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests EIIs with default implementations. // In the same crate, when there's no explicit declaration, the default should be called. diff --git a/tests/ui/eii/default/local_crate_explicit.rs b/tests/ui/eii/default/local_crate_explicit.rs index a4cc54fcd31f..200905b8753a 100644 --- a/tests/ui/eii/default/local_crate_explicit.rs +++ b/tests/ui/eii/default/local_crate_explicit.rs @@ -1,7 +1,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests EIIs with default implementations. // In the same crate, the explicit implementation should get priority. diff --git a/tests/ui/eii/duplicate/duplicate1.rs b/tests/ui/eii/duplicate/duplicate1.rs index 3269778aca0c..2128cac70eb3 100644 --- a/tests/ui/eii/duplicate/duplicate1.rs +++ b/tests/ui/eii/duplicate/duplicate1.rs @@ -2,7 +2,7 @@ //@ aux-build: impl1.rs //@ aux-build: impl2.rs //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // tests that EIIs error properly, even if the conflicting implementations live in another crate. #![feature(extern_item_impls)] diff --git a/tests/ui/eii/duplicate/duplicate2.rs b/tests/ui/eii/duplicate/duplicate2.rs index 4c883d28d74a..b0f1b1266e4c 100644 --- a/tests/ui/eii/duplicate/duplicate2.rs +++ b/tests/ui/eii/duplicate/duplicate2.rs @@ -3,7 +3,7 @@ //@ aux-build: impl2.rs //@ aux-build: impl3.rs //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests the error message when there are multiple implementations of an EII in many crates. #![feature(extern_item_impls)] diff --git a/tests/ui/eii/duplicate/duplicate3.rs b/tests/ui/eii/duplicate/duplicate3.rs index b04676074509..4b2b0fc111b5 100644 --- a/tests/ui/eii/duplicate/duplicate3.rs +++ b/tests/ui/eii/duplicate/duplicate3.rs @@ -4,7 +4,7 @@ //@ aux-build: impl3.rs //@ aux-build: impl4.rs //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests the error message when there are multiple implementations of an EII in many crates. #![feature(extern_item_impls)] diff --git a/tests/ui/eii/duplicate/multiple_impls.rs b/tests/ui/eii/duplicate/multiple_impls.rs index c02c783223ac..5ce2a27e1695 100644 --- a/tests/ui/eii/duplicate/multiple_impls.rs +++ b/tests/ui/eii/duplicate/multiple_impls.rs @@ -1,7 +1,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests whether one function could implement two EIIs. #![feature(extern_item_impls)] diff --git a/tests/ui/eii/eii-declaration-not-fn-issue-152337.rs b/tests/ui/eii/eii-declaration-not-fn-issue-152337.rs new file mode 100644 index 000000000000..0d71f4854d34 --- /dev/null +++ b/tests/ui/eii/eii-declaration-not-fn-issue-152337.rs @@ -0,0 +1,12 @@ +// Regression test for ICE "unexpected sort of node in fn_sig()" (issue #152337). +// When the same name is used for a const and an #[eii] function, the declaration +// was incorrectly resolved to the const, causing fn_sig() to be called on a non-function. +#![feature(extern_item_impls)] + +const A: () = (); +#[eii] +fn A() {} //~ ERROR the name `A` is defined multiple times +//~^ ERROR expected function or static, found constant +//~| ERROR expected function or static, found constant + +fn main() {} diff --git a/tests/ui/eii/eii-declaration-not-fn-issue-152337.stderr b/tests/ui/eii/eii-declaration-not-fn-issue-152337.stderr new file mode 100644 index 000000000000..34998f33cc92 --- /dev/null +++ b/tests/ui/eii/eii-declaration-not-fn-issue-152337.stderr @@ -0,0 +1,27 @@ +error[E0428]: the name `A` is defined multiple times + --> $DIR/eii-declaration-not-fn-issue-152337.rs:8:1 + | +LL | const A: () = (); + | ----------------- previous definition of the value `A` here +LL | #[eii] +LL | fn A() {} + | ^^^^^^ `A` redefined here + | + = note: `A` must be defined only once in the value namespace of this module + +error[E0423]: expected function or static, found constant `self::A` + --> $DIR/eii-declaration-not-fn-issue-152337.rs:8:4 + | +LL | fn A() {} + | ^ not a function or static + +error[E0423]: expected function or static, found constant `A` + --> $DIR/eii-declaration-not-fn-issue-152337.rs:8:4 + | +LL | fn A() {} + | ^ not a function or static + +error: aborting due to 3 previous errors + +Some errors have detailed explanations: E0423, E0428. +For more information about an error, try `rustc --explain E0423`. diff --git a/tests/ui/eii/eii_impl_with_contract.rs b/tests/ui/eii/eii_impl_with_contract.rs new file mode 100644 index 000000000000..43d34c294a79 --- /dev/null +++ b/tests/ui/eii/eii_impl_with_contract.rs @@ -0,0 +1,20 @@ +//@ run-pass +//@ ignore-backends: gcc +//@ ignore-windows + +#![feature(extern_item_impls)] +#![feature(contracts)] +#![allow(incomplete_features)] + +#[eii(hello)] +fn hello(x: u64); + +#[hello] +#[core::contracts::requires(x > 0)] +fn hello_impl(x: u64) { + println!("{x:?}") +} + +fn main() { + hello(42); +} diff --git a/tests/ui/eii/error_statement_position.stderr b/tests/ui/eii/error_statement_position.stderr index f14e6c33e64f..c6af18044db8 100644 --- a/tests/ui/eii/error_statement_position.stderr +++ b/tests/ui/eii/error_statement_position.stderr @@ -1,4 +1,4 @@ -error: `#[eii]` is only valid on functions +error: `#[eii]` is only valid on functions and statics --> $DIR/error_statement_position.rs:8:5 | LL | #[eii] diff --git a/tests/ui/eii/errors.rs b/tests/ui/eii/errors.rs index 5fcf33336b40..bc6c17f463a7 100644 --- a/tests/ui/eii/errors.rs +++ b/tests/ui/eii/errors.rs @@ -25,11 +25,9 @@ fn hello() { safe fn bar(x: u64) -> u64; } -#[foo] //~ ERROR `#[foo]` is only valid on functions -static X: u64 = 4; -#[foo] //~ ERROR `#[foo]` is only valid on functions +#[foo] //~ ERROR `#[foo]` is only valid on functions and statics const Y: u64 = 4; -#[foo] //~ ERROR `#[foo]` is only valid on functions +#[foo] //~ ERROR `#[foo]` is only valid on functions and statics macro bar() {} #[foo()] diff --git a/tests/ui/eii/errors.stderr b/tests/ui/eii/errors.stderr index c7eb96a9c219..553ae622cb36 100644 --- a/tests/ui/eii/errors.stderr +++ b/tests/ui/eii/errors.stderr @@ -52,47 +52,41 @@ error: `#[eii_declaration(...)]` expects a list of one or two elements LL | #[eii_declaration = "unsafe"] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/errors.rs:28:1 | LL | #[foo] | ^^^^^^ -error: `#[foo]` is only valid on functions +error: `#[foo]` is only valid on functions and statics --> $DIR/errors.rs:30:1 | LL | #[foo] | ^^^^^^ -error: `#[foo]` is only valid on functions - --> $DIR/errors.rs:32:1 - | -LL | #[foo] - | ^^^^^^ - error: `#[foo]` expected no arguments or a single argument: `#[foo(default)]` - --> $DIR/errors.rs:35:1 + --> $DIR/errors.rs:33:1 | LL | #[foo()] | ^^^^^^^^ error: `#[foo]` expected no arguments or a single argument: `#[foo(default)]` - --> $DIR/errors.rs:37:1 + --> $DIR/errors.rs:35:1 | LL | #[foo(default, bar)] | ^^^^^^^^^^^^^^^^^^^^ error: `#[foo]` expected no arguments or a single argument: `#[foo(default)]` - --> $DIR/errors.rs:39:1 + --> $DIR/errors.rs:37:1 | LL | #[foo("default")] | ^^^^^^^^^^^^^^^^^ error: `#[foo]` expected no arguments or a single argument: `#[foo(default)]` - --> $DIR/errors.rs:41:1 + --> $DIR/errors.rs:39:1 | LL | #[foo = "default"] | ^^^^^^^^^^^^^^^^^^ -error: aborting due to 15 previous errors +error: aborting due to 14 previous errors diff --git a/tests/ui/eii/ice_contract_attr_on_eii_generated_item.rs b/tests/ui/eii/ice_contract_attr_on_eii_generated_item.rs new file mode 100644 index 000000000000..fce142f6dc08 --- /dev/null +++ b/tests/ui/eii/ice_contract_attr_on_eii_generated_item.rs @@ -0,0 +1,11 @@ +//@ compile-flags: --crate-type rlib + +#![feature(extern_item_impls)] +#![feature(contracts)] +#![allow(incomplete_features)] + +#[eii] +#[core::contracts::ensures] +//~^ ERROR contract annotations is only supported in functions with bodies +//~| ERROR contract annotations can only be used on functions +fn implementation(); diff --git a/tests/ui/eii/ice_contract_attr_on_eii_generated_item.stderr b/tests/ui/eii/ice_contract_attr_on_eii_generated_item.stderr new file mode 100644 index 000000000000..3335346e55ee --- /dev/null +++ b/tests/ui/eii/ice_contract_attr_on_eii_generated_item.stderr @@ -0,0 +1,14 @@ +error: contract annotations is only supported in functions with bodies + --> $DIR/ice_contract_attr_on_eii_generated_item.rs:8:1 + | +LL | #[core::contracts::ensures] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: contract annotations can only be used on functions + --> $DIR/ice_contract_attr_on_eii_generated_item.rs:8:1 + | +LL | #[core::contracts::ensures] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 2 previous errors + diff --git a/tests/ui/eii/linking/codegen_cross_crate.rs b/tests/ui/eii/linking/codegen_cross_crate.rs index 2958a0f10521..192aac592070 100644 --- a/tests/ui/eii/linking/codegen_cross_crate.rs +++ b/tests/ui/eii/linking/codegen_cross_crate.rs @@ -3,7 +3,7 @@ //@ aux-build: codegen_cross_crate_other_crate.rs //@ compile-flags: -O //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests whether calling EIIs works with the declaration in another crate. diff --git a/tests/ui/eii/linking/codegen_single_crate.rs b/tests/ui/eii/linking/codegen_single_crate.rs index 8e85c354bba1..d0e9c015da41 100644 --- a/tests/ui/eii/linking/codegen_single_crate.rs +++ b/tests/ui/eii/linking/codegen_single_crate.rs @@ -1,7 +1,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows // Tests whether calling EIIs works with the declaration in the same crate. #![feature(extern_item_impls)] diff --git a/tests/ui/eii/linking/same-symbol.rs b/tests/ui/eii/linking/same-symbol.rs index baf36ff4f5a0..afba9b775026 100644 --- a/tests/ui/eii/linking/same-symbol.rs +++ b/tests/ui/eii/linking/same-symbol.rs @@ -1,7 +1,7 @@ //@ run-pass //@ check-run-results //@ ignore-backends: gcc -// FIXME: linking on windows (speciifcally mingw) not yet supported, see tracking issue #125418 +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 //@ ignore-windows #![feature(extern_item_impls)] diff --git a/tests/ui/eii/shadow_builtin.rs b/tests/ui/eii/shadow_builtin.rs new file mode 100644 index 000000000000..5f619b79d01a --- /dev/null +++ b/tests/ui/eii/shadow_builtin.rs @@ -0,0 +1,17 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether calling EIIs works with the declaration in the same crate. +#![feature(extern_item_impls)] + +#[eii(inline)] +//~^ ERROR `#[inline]` required, but not found +fn test(x: u64); + +#[inline] +//~^ ERROR `inline` is ambiguous +fn test_impl(x: u64) { + println!("{x:?}") +} + +fn main() { } diff --git a/tests/ui/eii/shadow_builtin.stderr b/tests/ui/eii/shadow_builtin.stderr new file mode 100644 index 000000000000..d48e66a18af2 --- /dev/null +++ b/tests/ui/eii/shadow_builtin.stderr @@ -0,0 +1,26 @@ +error[E0659]: `inline` is ambiguous + --> $DIR/shadow_builtin.rs:11:3 + | +LL | #[inline] + | ^^^^^^ ambiguous name + | + = note: ambiguous because of a name conflict with a builtin attribute + = note: `inline` could refer to a built-in attribute +note: `inline` could also refer to the attribute macro defined here + --> $DIR/shadow_builtin.rs:7:1 + | +LL | #[eii(inline)] + | ^^^^^^^^^^^^^^ + = help: use `crate::inline` to refer to this attribute macro unambiguously + +error: `#[inline]` required, but not found + --> $DIR/shadow_builtin.rs:7:7 + | +LL | #[eii(inline)] + | ^^^^^^ expected because `#[inline]` was declared here in crate `shadow_builtin` + | + = help: expected at least one implementation in crate `shadow_builtin` or any of its dependencies + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0659`. diff --git a/tests/ui/eii/static/argument_required.rs b/tests/ui/eii/static/argument_required.rs new file mode 100644 index 000000000000..114b8a35de5c --- /dev/null +++ b/tests/ui/eii/static/argument_required.rs @@ -0,0 +1,11 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii] +//~^ ERROR `#[eii]` requires the name as an explicit argument when used on a static +static HELLO: u64; + +fn main() { } diff --git a/tests/ui/eii/static/argument_required.stderr b/tests/ui/eii/static/argument_required.stderr new file mode 100644 index 000000000000..9e5ee398f77d --- /dev/null +++ b/tests/ui/eii/static/argument_required.stderr @@ -0,0 +1,8 @@ +error: `#[eii]` requires the name as an explicit argument when used on a static + --> $DIR/argument_required.rs:7:1 + | +LL | #[eii] + | ^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/auxiliary/cross_crate_decl.rs b/tests/ui/eii/static/auxiliary/cross_crate_decl.rs new file mode 100644 index 000000000000..06b7daca2207 --- /dev/null +++ b/tests/ui/eii/static/auxiliary/cross_crate_decl.rs @@ -0,0 +1,6 @@ +//@ no-prefer-dynamic +#![crate_type = "rlib"] +#![feature(extern_item_impls)] + +#[eii(eii1)] +pub static DECL1: u64; diff --git a/tests/ui/eii/static/auxiliary/cross_crate_def.rs b/tests/ui/eii/static/auxiliary/cross_crate_def.rs new file mode 100644 index 000000000000..70933440a62b --- /dev/null +++ b/tests/ui/eii/static/auxiliary/cross_crate_def.rs @@ -0,0 +1,9 @@ +//@ no-prefer-dynamic +#![crate_type = "rlib"] +#![feature(extern_item_impls)] + +#[eii(eii1)] +pub static DECL1: u64; + +#[eii1] +pub static EII1_IMPL: u64 = 5; diff --git a/tests/ui/eii/static/cross_crate_decl.rs b/tests/ui/eii/static/cross_crate_decl.rs new file mode 100644 index 000000000000..63e3511198e1 --- /dev/null +++ b/tests/ui/eii/static/cross_crate_decl.rs @@ -0,0 +1,21 @@ +//@ run-pass +//@ check-run-results +//@ aux-build: cross_crate_decl.rs +//@ compile-flags: -O +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether calling EIIs works with the declaration in another crate. + +extern crate cross_crate_decl as codegen; + +#[codegen::eii1] +static EII1_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{}", EII1_IMPL); + // through the alias + println!("{}", codegen::DECL1); +} diff --git a/tests/ui/eii/static/cross_crate_decl.run.stdout b/tests/ui/eii/static/cross_crate_decl.run.stdout new file mode 100644 index 000000000000..fd3c81a4d763 --- /dev/null +++ b/tests/ui/eii/static/cross_crate_decl.run.stdout @@ -0,0 +1,2 @@ +5 +5 diff --git a/tests/ui/eii/static/cross_crate_def.rs b/tests/ui/eii/static/cross_crate_def.rs new file mode 100644 index 000000000000..a0b6afbfd760 --- /dev/null +++ b/tests/ui/eii/static/cross_crate_def.rs @@ -0,0 +1,18 @@ +//@ run-pass +//@ check-run-results +//@ aux-build: cross_crate_def.rs +//@ compile-flags: -O +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether calling EIIs works with the declaration and definition in another crate. + +extern crate cross_crate_def as codegen; + +// what you would write: +fn main() { + // directly + println!("{}", codegen::EII1_IMPL); + // through the alias + println!("{}", codegen::DECL1); +} diff --git a/tests/ui/eii/static/cross_crate_def.run.stdout b/tests/ui/eii/static/cross_crate_def.run.stdout new file mode 100644 index 000000000000..fd3c81a4d763 --- /dev/null +++ b/tests/ui/eii/static/cross_crate_def.run.stdout @@ -0,0 +1,2 @@ +5 +5 diff --git a/tests/ui/eii/static/duplicate.rs b/tests/ui/eii/static/duplicate.rs new file mode 100644 index 000000000000..12b2e56c07e4 --- /dev/null +++ b/tests/ui/eii/static/duplicate.rs @@ -0,0 +1,25 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +static HELLO_IMPL1: u64 = 5; +//~^ ERROR multiple implementations of `#[hello]` + +#[hello] +static HELLO_IMPL2: u64 = 6; + +// what you would write: +fn main() { + // directly + println!("{HELLO_IMPL1}"); + println!("{HELLO_IMPL2}"); + + // through the alias + println!("{HELLO}"); +} diff --git a/tests/ui/eii/static/duplicate.stderr b/tests/ui/eii/static/duplicate.stderr new file mode 100644 index 000000000000..270664c8c74c --- /dev/null +++ b/tests/ui/eii/static/duplicate.stderr @@ -0,0 +1,13 @@ +error: multiple implementations of `#[hello]` + --> $DIR/duplicate.rs:11:1 + | +LL | static HELLO_IMPL1: u64 = 5; + | ^^^^^^^^^^^^^^^^^^^^^^^ first implemented here in crate `duplicate` +... +LL | static HELLO_IMPL2: u64 = 6; + | ----------------------- also implemented here in crate `duplicate` + | + = help: an "externally implementable item" can only have a single implementation in the final artifact. When multiple implementations are found, also in different crates, they conflict + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mismatch_fn_static.rs b/tests/ui/eii/static/mismatch_fn_static.rs new file mode 100644 index 000000000000..298fdca18d96 --- /dev/null +++ b/tests/ui/eii/static/mismatch_fn_static.rs @@ -0,0 +1,14 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +fn hello() -> u64; + +#[hello] +//~^ ERROR `#[hello]` must be used on a function +static HELLO_IMPL: u64 = 5; + +fn main() { } diff --git a/tests/ui/eii/static/mismatch_fn_static.stderr b/tests/ui/eii/static/mismatch_fn_static.stderr new file mode 100644 index 000000000000..e8fa5f85b1f1 --- /dev/null +++ b/tests/ui/eii/static/mismatch_fn_static.stderr @@ -0,0 +1,8 @@ +error: `#[hello]` must be used on a function + --> $DIR/mismatch_fn_static.rs:10:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mismatch_mut.rs b/tests/ui/eii/static/mismatch_mut.rs new file mode 100644 index 000000000000..87c2c4128aa5 --- /dev/null +++ b/tests/ui/eii/static/mismatch_mut.rs @@ -0,0 +1,22 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +//~^ ERROR `#[eii]` cannot be used on mutable statics +static mut HELLO: u64; + +#[hello] +//~^ ERROR mutability does not match with the definition of`#[hello]` +static HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{HELLO_IMPL}"); + + // through the alias + println!("{}", unsafe { HELLO }); +} diff --git a/tests/ui/eii/static/mismatch_mut.stderr b/tests/ui/eii/static/mismatch_mut.stderr new file mode 100644 index 000000000000..537ac0de3c3a --- /dev/null +++ b/tests/ui/eii/static/mismatch_mut.stderr @@ -0,0 +1,14 @@ +error: `#[eii]` cannot be used on mutable statics + --> $DIR/mismatch_mut.rs:7:1 + | +LL | #[eii(hello)] + | ^^^^^^^^^^^^^ + +error: mutability does not match with the definition of`#[hello]` + --> $DIR/mismatch_mut.rs:11:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 2 previous errors + diff --git a/tests/ui/eii/static/mismatch_mut2.rs b/tests/ui/eii/static/mismatch_mut2.rs new file mode 100644 index 000000000000..ab525e418ade --- /dev/null +++ b/tests/ui/eii/static/mismatch_mut2.rs @@ -0,0 +1,21 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +//~^ ERROR mutability does not match with the definition of`#[hello]` +static mut HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{}", unsafe { HELLO_IMPL }); + + // through the alias + println!("{HELLO}"); +} diff --git a/tests/ui/eii/static/mismatch_mut2.stderr b/tests/ui/eii/static/mismatch_mut2.stderr new file mode 100644 index 000000000000..6ac3df57697d --- /dev/null +++ b/tests/ui/eii/static/mismatch_mut2.stderr @@ -0,0 +1,8 @@ +error: mutability does not match with the definition of`#[hello]` + --> $DIR/mismatch_mut2.rs:10:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mismatch_safety.rs b/tests/ui/eii/static/mismatch_safety.rs new file mode 100644 index 000000000000..f30326b0755c --- /dev/null +++ b/tests/ui/eii/static/mismatch_safety.rs @@ -0,0 +1,21 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +unsafe static HELLO: u64; + +#[hello] +//~^ ERROR safety does not match with the definition of`#[hello]` +static HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{HELLO_IMPL}"); + + // through the alias + println!("{}", unsafe { HELLO }); +} diff --git a/tests/ui/eii/static/mismatch_safety.stderr b/tests/ui/eii/static/mismatch_safety.stderr new file mode 100644 index 000000000000..d4fa85778ae1 --- /dev/null +++ b/tests/ui/eii/static/mismatch_safety.stderr @@ -0,0 +1,8 @@ +error: safety does not match with the definition of`#[hello]` + --> $DIR/mismatch_safety.rs:10:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mismatch_safety2.rs b/tests/ui/eii/static/mismatch_safety2.rs new file mode 100644 index 000000000000..dea45c26292d --- /dev/null +++ b/tests/ui/eii/static/mismatch_safety2.rs @@ -0,0 +1,21 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +unsafe static HELLO_IMPL: u64 = 5; +//~^ ERROR static items cannot be declared with `unsafe` safety qualifier outside of `extern` block + +// what you would write: +fn main() { + // directly + println!("{HELLO_IMPL}"); + + // through the alias + println!("{}", unsafe { HELLO }); +} diff --git a/tests/ui/eii/static/mismatch_safety2.stderr b/tests/ui/eii/static/mismatch_safety2.stderr new file mode 100644 index 000000000000..6957a6202b61 --- /dev/null +++ b/tests/ui/eii/static/mismatch_safety2.stderr @@ -0,0 +1,8 @@ +error: static items cannot be declared with `unsafe` safety qualifier outside of `extern` block + --> $DIR/mismatch_safety2.rs:11:1 + | +LL | unsafe static HELLO_IMPL: u64 = 5; + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mismatch_static_fn.rs b/tests/ui/eii/static/mismatch_static_fn.rs new file mode 100644 index 000000000000..cd9a8109dc33 --- /dev/null +++ b/tests/ui/eii/static/mismatch_static_fn.rs @@ -0,0 +1,16 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +//~^ ERROR `#[hello]` must be used on a static +fn hello_impl() -> u64 { + 5 +} + +fn main() { } diff --git a/tests/ui/eii/static/mismatch_static_fn.stderr b/tests/ui/eii/static/mismatch_static_fn.stderr new file mode 100644 index 000000000000..639e3cfa3beb --- /dev/null +++ b/tests/ui/eii/static/mismatch_static_fn.stderr @@ -0,0 +1,8 @@ +error: `#[hello]` must be used on a static + --> $DIR/mismatch_static_fn.rs:10:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/multiple_decls.rs b/tests/ui/eii/static/multiple_decls.rs new file mode 100644 index 000000000000..791e2725087f --- /dev/null +++ b/tests/ui/eii/static/multiple_decls.rs @@ -0,0 +1,12 @@ +#![feature(extern_item_impls)] + +const A: () = (); +#[eii(A)] +static A: u64; +//~^ ERROR the name `A` is defined multiple times +//~| ERROR expected function or static, found constant `A` + +#[A] +static A_IMPL: u64 = 5; + +fn main() {} diff --git a/tests/ui/eii/static/multiple_decls.stderr b/tests/ui/eii/static/multiple_decls.stderr new file mode 100644 index 000000000000..fcc5d93c5f99 --- /dev/null +++ b/tests/ui/eii/static/multiple_decls.stderr @@ -0,0 +1,21 @@ +error[E0428]: the name `A` is defined multiple times + --> $DIR/multiple_decls.rs:5:1 + | +LL | const A: () = (); + | ----------------- previous definition of the value `A` here +LL | #[eii(A)] +LL | static A: u64; + | ^^^^^^^^^^^^^^ `A` redefined here + | + = note: `A` must be defined only once in the value namespace of this module + +error[E0423]: expected function or static, found constant `A` + --> $DIR/multiple_decls.rs:5:8 + | +LL | static A: u64; + | ^ not a function or static + +error: aborting due to 2 previous errors + +Some errors have detailed explanations: E0423, E0428. +For more information about an error, try `rustc --explain E0423`. diff --git a/tests/ui/eii/static/multiple_impls.rs b/tests/ui/eii/static/multiple_impls.rs new file mode 100644 index 000000000000..8ad7d87040a3 --- /dev/null +++ b/tests/ui/eii/static/multiple_impls.rs @@ -0,0 +1,20 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether one function could implement two EIIs. +#![feature(extern_item_impls)] + +#[eii(a)] +static A: u64; + +#[eii(b)] +static B: u64; + +#[a] +#[b] +//~^ ERROR static cannot implement multiple EIIs +static IMPL: u64 = 5; + +fn main() { + println!("{A} {B} {IMPL}") +} diff --git a/tests/ui/eii/static/multiple_impls.run.stdout b/tests/ui/eii/static/multiple_impls.run.stdout new file mode 100644 index 000000000000..58945c2b4829 --- /dev/null +++ b/tests/ui/eii/static/multiple_impls.run.stdout @@ -0,0 +1 @@ +5 5 5 diff --git a/tests/ui/eii/static/multiple_impls.stderr b/tests/ui/eii/static/multiple_impls.stderr new file mode 100644 index 000000000000..b31331f2483f --- /dev/null +++ b/tests/ui/eii/static/multiple_impls.stderr @@ -0,0 +1,10 @@ +error: static cannot implement multiple EIIs + --> $DIR/multiple_impls.rs:14:1 + | +LL | #[b] + | ^^^^ + | + = note: this is not allowed because multiple externally implementable statics that alias may be unintuitive + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/mut.rs b/tests/ui/eii/static/mut.rs new file mode 100644 index 000000000000..803ffc229799 --- /dev/null +++ b/tests/ui/eii/static/mut.rs @@ -0,0 +1,21 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +//~^ ERROR `#[eii]` cannot be used on mutable statics +static mut HELLO: u64; + +#[hello] +static mut HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{}", unsafe { HELLO_IMPL }); + + // through the alias + println!("{}", unsafe { HELLO }); +} diff --git a/tests/ui/eii/static/mut.run.stdout b/tests/ui/eii/static/mut.run.stdout new file mode 100644 index 000000000000..fd3c81a4d763 --- /dev/null +++ b/tests/ui/eii/static/mut.run.stdout @@ -0,0 +1,2 @@ +5 +5 diff --git a/tests/ui/eii/static/mut.stderr b/tests/ui/eii/static/mut.stderr new file mode 100644 index 000000000000..cd3a0ca23c7f --- /dev/null +++ b/tests/ui/eii/static/mut.stderr @@ -0,0 +1,8 @@ +error: `#[eii]` cannot be used on mutable statics + --> $DIR/mut.rs:7:1 + | +LL | #[eii(hello)] + | ^^^^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/eii/static/same_address.rs b/tests/ui/eii/static/same_address.rs new file mode 100644 index 000000000000..81de19406dc4 --- /dev/null +++ b/tests/ui/eii/static/same_address.rs @@ -0,0 +1,21 @@ +//@ run-pass +//@ check-run-results +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs and their declarations share the same address +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +static HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + assert_eq!( + &HELLO as *const u64 as usize, + &HELLO_IMPL as *const u64 as usize, + ) +} diff --git a/tests/ui/eii/static/simple.rs b/tests/ui/eii/static/simple.rs new file mode 100644 index 000000000000..661ab9b9835f --- /dev/null +++ b/tests/ui/eii/static/simple.rs @@ -0,0 +1,22 @@ +//@ run-pass +//@ check-run-results +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests whether EIIs work on statics +#![feature(extern_item_impls)] + +#[eii(hello)] +static HELLO: u64; + +#[hello] +static HELLO_IMPL: u64 = 5; + +// what you would write: +fn main() { + // directly + println!("{HELLO_IMPL}"); + + // through the alias + println!("{HELLO}"); +} diff --git a/tests/ui/eii/static/simple.run.stdout b/tests/ui/eii/static/simple.run.stdout new file mode 100644 index 000000000000..fd3c81a4d763 --- /dev/null +++ b/tests/ui/eii/static/simple.run.stdout @@ -0,0 +1,2 @@ +5 +5 diff --git a/tests/ui/eii/static/subtype.rs b/tests/ui/eii/static/subtype.rs new file mode 100644 index 000000000000..d98e94fa9032 --- /dev/null +++ b/tests/ui/eii/static/subtype.rs @@ -0,0 +1,18 @@ +//@ check-pass +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests that mismatching types of the declaration and definition are rejected +#![feature(extern_item_impls)] + +use std::ptr; + +#[eii(hello)] +static HELLO: for<'a> fn(&'a u8) -> &'a u8; + +#[hello] +static HELLO_IMPL: for<'a> fn(&'a u8) -> &'static u8 = |_| todo!(); + +fn main() { + +} diff --git a/tests/ui/eii/static/subtype_wrong.rs b/tests/ui/eii/static/subtype_wrong.rs new file mode 100644 index 000000000000..964a3d767b19 --- /dev/null +++ b/tests/ui/eii/static/subtype_wrong.rs @@ -0,0 +1,17 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests that mismatching types of the declaration and definition are rejected +#![feature(extern_item_impls)] + +use std::ptr; + +#[eii(hello)] +static HELLO: for<'a> fn(&'a u8) -> &'static u8; + +#[hello] +static HELLO_IMPL: for<'a> fn(&'a u8) -> &'a u8 = |_| todo!(); +//~^ ERROR mismatched types + +fn main() { +} diff --git a/tests/ui/eii/static/subtype_wrong.stderr b/tests/ui/eii/static/subtype_wrong.stderr new file mode 100644 index 000000000000..a20074947c15 --- /dev/null +++ b/tests/ui/eii/static/subtype_wrong.stderr @@ -0,0 +1,12 @@ +error[E0308]: mismatched types + --> $DIR/subtype_wrong.rs:13:1 + | +LL | static HELLO_IMPL: for<'a> fn(&'a u8) -> &'a u8 = |_| todo!(); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ one type is more general than the other + | + = note: expected fn pointer `for<'a> fn(&'a _) -> &'static _` + found fn pointer `for<'a> fn(&'a _) -> &'a _` + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0308`. diff --git a/tests/ui/eii/static/wrong_ty.rs b/tests/ui/eii/static/wrong_ty.rs new file mode 100644 index 000000000000..beee0a5a0857 --- /dev/null +++ b/tests/ui/eii/static/wrong_ty.rs @@ -0,0 +1,18 @@ +//@ ignore-backends: gcc +// FIXME: linking on windows (specifically mingw) not yet supported, see tracking issue #125418 +//@ ignore-windows +// Tests that mismatching types of the declaration and definition are rejected +#![feature(extern_item_impls)] + +use std::ptr; + +#[eii(hello)] +static HELLO: u64; + +#[hello] +static HELLO_IMPL: bool = true; +//~^ ERROR static `HELLO_IMPL` has a type that is incompatible with the declaration of `#[hello]` [E0806] + +fn main() { + +} diff --git a/tests/ui/eii/static/wrong_ty.stderr b/tests/ui/eii/static/wrong_ty.stderr new file mode 100644 index 000000000000..509551352774 --- /dev/null +++ b/tests/ui/eii/static/wrong_ty.stderr @@ -0,0 +1,15 @@ +error[E0806]: static `HELLO_IMPL` has a type that is incompatible with the declaration of `#[hello]` + --> $DIR/wrong_ty.rs:13:1 + | +LL | static HELLO_IMPL: bool = true; + | ^^^^^^^^^^^^^^^^^^^^^^^ + | +note: expected this because of this attribute + --> $DIR/wrong_ty.rs:12:1 + | +LL | #[hello] + | ^^^^^^^^ + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0806`. diff --git a/tests/ui/enum-discriminant/generic-self-in-discr-ice.rs b/tests/ui/enum-discriminant/generic-self-in-discr-ice.rs new file mode 100644 index 000000000000..2d60380efffa --- /dev/null +++ b/tests/ui/enum-discriminant/generic-self-in-discr-ice.rs @@ -0,0 +1,12 @@ +#![feature(sized_hierarchy)] + +use std::marker::PointeeSized; + +#[repr(usize)] +enum What { + X = size_of::<*mut Self>(), + //~^ ERROR generic `Self` types are not permitted in enum discriminant values + Y(*mut T), +} + +fn main() {} diff --git a/tests/ui/enum-discriminant/generic-self-in-discr-ice.stderr b/tests/ui/enum-discriminant/generic-self-in-discr-ice.stderr new file mode 100644 index 000000000000..d827897c8e3e --- /dev/null +++ b/tests/ui/enum-discriminant/generic-self-in-discr-ice.stderr @@ -0,0 +1,8 @@ +error: generic `Self` types are not permitted in enum discriminant values + --> $DIR/generic-self-in-discr-ice.rs:7:24 + | +LL | X = size_of::<*mut Self>(), + | ^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.rs b/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.rs new file mode 100644 index 000000000000..de02bb95e5a0 --- /dev/null +++ b/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.rs @@ -0,0 +1,17 @@ +//@ check-fail +// Test that `Self` is rejected even when nested inside an inline const +// or closure within an enum discriminant. Regression test for issue #154281. +#![feature(sized_hierarchy)] + +use std::marker::PointeeSized; + +#[repr(usize)] +enum What { + X = const { { let _: *mut Self; 1_usize } }, + //~^ ERROR generic `Self` types are not permitted in enum discriminant values + Y = { let _f = || { let _: *mut Self; }; 1_usize }, + //~^ ERROR generic `Self` types are not permitted in enum discriminant values + Z(*mut T), +} + +fn main() {} diff --git a/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.stderr b/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.stderr new file mode 100644 index 000000000000..cc5db2eb266d --- /dev/null +++ b/tests/ui/enum-discriminant/generic-self-in-discr-inline-const.stderr @@ -0,0 +1,14 @@ +error: generic `Self` types are not permitted in enum discriminant values + --> $DIR/generic-self-in-discr-inline-const.rs:10:31 + | +LL | X = const { { let _: *mut Self; 1_usize } }, + | ^^^^ + +error: generic `Self` types are not permitted in enum discriminant values + --> $DIR/generic-self-in-discr-inline-const.rs:12:37 + | +LL | Y = { let _f = || { let _: *mut Self; }; 1_usize }, + | ^^^^ + +error: aborting due to 2 previous errors + diff --git a/tests/ui/enum-discriminant/wrapping_niche.rs b/tests/ui/enum-discriminant/wrapping_niche.rs index 8097414be687..d16645bb2082 100644 --- a/tests/ui/enum-discriminant/wrapping_niche.rs +++ b/tests/ui/enum-discriminant/wrapping_niche.rs @@ -4,7 +4,7 @@ #![feature(rustc_attrs)] #[repr(u16)] -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] enum UnsignedAroundZero { //~^ ERROR: layout_of A = 65535, @@ -13,7 +13,7 @@ enum UnsignedAroundZero { } #[repr(i16)] -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] enum SignedAroundZero { //~^ ERROR: layout_of A = -1, diff --git a/tests/ui/enum/enum-variant-type-2.stderr b/tests/ui/enum/enum-variant-type-2.stderr index a69e38b2df8b..21c9be1184ae 100644 --- a/tests/ui/enum/enum-variant-type-2.stderr +++ b/tests/ui/enum/enum-variant-type-2.stderr @@ -2,10 +2,13 @@ error[E0573]: expected type, found variant `Foo::Bar` --> $DIR/enum-variant-type-2.rs:8:11 | LL | fn foo(x: Foo::Bar) {} - | ^^^^^^^^ - | | - | not a type - | help: try using the variant's enum: `Foo` + | ^^^^^^^^ not a type + | +help: try using the variant's enum + | +LL - fn foo(x: Foo::Bar) {} +LL + fn foo(x: Foo) {} + | error: aborting due to 1 previous error diff --git a/tests/ui/error-codes/E0452.rs b/tests/ui/error-codes/E0452.rs new file mode 100644 index 000000000000..4e5a6c930146 --- /dev/null +++ b/tests/ui/error-codes/E0452.rs @@ -0,0 +1,8 @@ +#![allow(foo = "")] //~ ERROR E0452 + //~| ERROR E0452 + //~| ERROR E0452 + //~| ERROR E0452 + //~| ERROR E0452 + //~| ERROR E0452 +fn main() { +} diff --git a/tests/ui/error-codes/E0452.stderr b/tests/ui/error-codes/E0452.stderr new file mode 100644 index 000000000000..c20429e363dd --- /dev/null +++ b/tests/ui/error-codes/E0452.stderr @@ -0,0 +1,49 @@ +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0452]: malformed lint attribute input + --> $DIR/E0452.rs:1:10 + | +LL | #![allow(foo = "")] + | ^^^^^^^^ bad attribute argument + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 6 previous errors + +For more information about this error, try `rustc --explain E0452`. diff --git a/tests/ui/error-codes/E0540.stderr b/tests/ui/error-codes/E0540.stderr index ae23dce5c50a..53f696807a68 100644 --- a/tests/ui/error-codes/E0540.stderr +++ b/tests/ui/error-codes/E0540.stderr @@ -4,7 +4,7 @@ error[E0805]: malformed `inline` attribute input LL | #[inline()] | ^^^^^^^^--^ | | - | expected a single argument here + | expected an argument here | = note: for more information, visit help: try changing it to one of the following valid forms of the attribute diff --git a/tests/ui/errors/unknown-target-suggestion.rs b/tests/ui/errors/unknown-target-suggestion.rs new file mode 100644 index 000000000000..0c371aed921a --- /dev/null +++ b/tests/ui/errors/unknown-target-suggestion.rs @@ -0,0 +1,11 @@ +// Checks that an unknown --target also suggests a similar known target. +// See https://github.com/rust-lang/rust/issues/155085 + +// ignore-tidy-target-specific-tests +//@ compile-flags: --target x86_64-linux-gnu + +fn main() {} + +//~? ERROR error loading target specification: could not find specification for target "x86_64-linux-gnu" +//~? HELP run `rustc --print target-list` for a list of built-in targets +//~? HELP did you mean `x86_64-unknown-linux-gnu` diff --git a/tests/ui/errors/unknown-target-suggestion.stderr b/tests/ui/errors/unknown-target-suggestion.stderr new file mode 100644 index 000000000000..09d482724152 --- /dev/null +++ b/tests/ui/errors/unknown-target-suggestion.stderr @@ -0,0 +1,5 @@ +error: error loading target specification: could not find specification for target "x86_64-linux-gnu" + | + = help: run `rustc --print target-list` for a list of built-in targets + = help: did you mean `x86_64-unknown-linux-gnu`? + diff --git a/tests/ui/errors/wrong-target-spec.stderr b/tests/ui/errors/wrong-target-spec.stderr index 98b03ae00cb3..cab485312bfd 100644 --- a/tests/ui/errors/wrong-target-spec.stderr +++ b/tests/ui/errors/wrong-target-spec.stderr @@ -1,4 +1,5 @@ error: error loading target specification: could not find specification for target "x86_64_unknown-linux-musl" | = help: run `rustc --print target-list` for a list of built-in targets + = help: did you mean `x86_64-unknown-linux-musl`? diff --git a/tests/ui/explicit-tail-calls/support/bystack.rs b/tests/ui/explicit-tail-calls/support/bystack.rs index ad1e0827f9f0..0f10fe3d172e 100644 --- a/tests/ui/explicit-tail-calls/support/bystack.rs +++ b/tests/ui/explicit-tail-calls/support/bystack.rs @@ -36,9 +36,11 @@ //@ revisions: loongarch32 //@[loongarch32] compile-flags: --target loongarch32-unknown-none //@[loongarch32] needs-llvm-components: loongarch +//@[loongarch32] ignore-llvm-version: 23 //@ revisions: loongarch64 //@[loongarch64] compile-flags: --target loongarch64-unknown-linux-gnu //@[loongarch64] needs-llvm-components: loongarch +//@[loongarch64] ignore-llvm-version: 23 //@ revisions: bpf //@[bpf] compile-flags: --target bpfeb-unknown-none //@[bpf] needs-llvm-components: bpf diff --git a/tests/ui/explicit-tail-calls/support/byval.rs b/tests/ui/explicit-tail-calls/support/byval.rs index 965c63c8688a..be11741fd016 100644 --- a/tests/ui/explicit-tail-calls/support/byval.rs +++ b/tests/ui/explicit-tail-calls/support/byval.rs @@ -36,9 +36,11 @@ //@ revisions: loongarch32 //@[loongarch32] compile-flags: --target loongarch32-unknown-none //@[loongarch32] needs-llvm-components: loongarch +//@[loongarch32] ignore-llvm-version: 23 //@ revisions: loongarch64 //@[loongarch64] compile-flags: --target loongarch64-unknown-linux-gnu //@[loongarch64] needs-llvm-components: loongarch +//@[loongarch64] ignore-llvm-version: 23 //@ revisions: bpf //@[bpf] compile-flags: --target bpfeb-unknown-none //@[bpf] needs-llvm-components: bpf diff --git a/tests/ui/extern/issue-47725.stderr b/tests/ui/extern/issue-47725.stderr index 27da18df37cd..023f4265c80f 100644 --- a/tests/ui/extern/issue-47725.stderr +++ b/tests/ui/extern/issue-47725.stderr @@ -2,9 +2,13 @@ error[E0539]: malformed `link_name` attribute input --> $DIR/issue-47725.rs:19:1 | LL | #[link_name] - | ^^^^^^^^^^^^ help: must be of the form: `#[link_name = "name"]` + | ^^^^^^^^^^^^ | = note: for more information, visit +help: must be of the form + | +LL | #[link_name = "name"] + | ++++++++ warning: `#[link_name]` attribute cannot be used on structs --> $DIR/issue-47725.rs:3:1 diff --git a/tests/ui/feature-gates/feature-gate-adt_const_params.stderr b/tests/ui/feature-gates/feature-gate-adt_const_params.stderr index 7ea91a8f4c2b..607e7869c789 100644 --- a/tests/ui/feature-gates/feature-gate-adt_const_params.stderr +++ b/tests/ui/feature-gates/feature-gate-adt_const_params.stderr @@ -5,9 +5,9 @@ LL | struct Foo; | ^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | error: aborting due to 1 previous error diff --git a/tests/ui/feature-gates/feature-gate-cfg_target_object_format.rs b/tests/ui/feature-gates/feature-gate-cfg_target_object_format.rs new file mode 100644 index 000000000000..6cb16a4d036c --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-cfg_target_object_format.rs @@ -0,0 +1,6 @@ +#[allow(unused)] +#[cfg(target_object_format = "elf")] +//~^ ERROR `cfg(target_object_format)` is experimental +const X: () = (); + +fn main() {} diff --git a/tests/ui/feature-gates/feature-gate-cfg_target_object_format.stderr b/tests/ui/feature-gates/feature-gate-cfg_target_object_format.stderr new file mode 100644 index 000000000000..bd65d9c175cd --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-cfg_target_object_format.stderr @@ -0,0 +1,13 @@ +error[E0658]: `cfg(target_object_format)` is experimental and subject to change + --> $DIR/feature-gate-cfg_target_object_format.rs:2:7 + | +LL | #[cfg(target_object_format = "elf")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: see issue #152586 for more information + = help: add `#![feature(cfg_target_object_format)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0658`. diff --git a/tests/ui/issues/issue-32782.rs b/tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.rs similarity index 80% rename from tests/ui/issues/issue-32782.rs rename to tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.rs index 1e99a25cec3a..c81d2e538c7f 100644 --- a/tests/ui/issues/issue-32782.rs +++ b/tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.rs @@ -1,3 +1,4 @@ +//! Regression test for macro_rules! bar ( () => () ); diff --git a/tests/ui/issues/issue-32782.stderr b/tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.stderr similarity index 89% rename from tests/ui/issues/issue-32782.stderr rename to tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.stderr index 2a1183ab978d..cc3dda7c1f09 100644 --- a/tests/ui/issues/issue-32782.stderr +++ b/tests/ui/feature-gates/feature-gate-check-nested-macro-invocation.stderr @@ -1,5 +1,5 @@ error[E0658]: allow_internal_unstable side-steps feature gating and stability checks - --> $DIR/issue-32782.rs:7:9 + --> $DIR/feature-gate-check-nested-macro-invocation.rs:8:9 | LL | #[allow_internal_unstable()] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -12,7 +12,7 @@ LL | foo!(); = note: this error originates in the macro `foo` (in Nightly builds, run with -Z macro-backtrace for more info) error: `#[allow_internal_unstable]` attribute cannot be used on macro calls - --> $DIR/issue-32782.rs:7:9 + --> $DIR/feature-gate-check-nested-macro-invocation.rs:8:9 | LL | #[allow_internal_unstable()] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-const.rs b/tests/ui/feature-gates/feature-gate-diagnostic-on-const.rs index 890e4aa5a601..398fa30e7404 100644 --- a/tests/ui/feature-gates/feature-gate-diagnostic-on-const.rs +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-const.rs @@ -10,7 +10,7 @@ const fn foo() { Foo == Foo; - //~^ ERROR: the trait bound `Foo: [const] PartialEq` is not satisfied + //~^ ERROR: cannot call non-const operator in constant functions } fn main() {} diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-const.stderr b/tests/ui/feature-gates/feature-gate-diagnostic-on-const.stderr index 4e2a573f72d7..04c901f4f938 100644 --- a/tests/ui/feature-gates/feature-gate-diagnostic-on-const.stderr +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-const.stderr @@ -1,15 +1,16 @@ -error[E0277]: the trait bound `Foo: [const] PartialEq` is not satisfied +error[E0015]: cannot call non-const operator in constant functions --> $DIR/feature-gate-diagnostic-on-const.rs:12:5 | LL | Foo == Foo; | ^^^^^^^^^^ | -note: trait `PartialEq` is implemented but not `const` +note: impl defined here, but it is not `const` --> $DIR/auxiliary/diagnostic-on-const.rs:4:1 | LL | impl PartialEq for Foo { | ^^^^^^^^^^^^^^^^^^^^^^ + = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants error: aborting due to 1 previous error -For more information about this error, try `rustc --explain E0277`. +For more information about this error, try `rustc --explain E0015`. diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-move.rs b/tests/ui/feature-gates/feature-gate-diagnostic-on-move.rs index a1f3b1fbbc86..a55a6260d651 100644 --- a/tests/ui/feature-gates/feature-gate-diagnostic-on-move.rs +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-move.rs @@ -2,9 +2,8 @@ //! gate, but the fact that not adding the feature gate will cause the //! diagnostic to not emit the custom diagnostic message //! -#[diagnostic::on_move( - message = "Foo" -)] +#[diagnostic::on_move(message = "Foo")] +//~^ WARN unknown diagnostic attribute #[derive(Debug)] struct Foo; diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-move.stderr b/tests/ui/feature-gates/feature-gate-diagnostic-on-move.stderr index 9ba6f272cf92..593120edd170 100644 --- a/tests/ui/feature-gates/feature-gate-diagnostic-on-move.stderr +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-move.stderr @@ -1,5 +1,14 @@ +warning: unknown diagnostic attribute + --> $DIR/feature-gate-diagnostic-on-move.rs:5:15 + | +LL | #[diagnostic::on_move(message = "Foo")] + | ^^^^^^^ + | + = help: add `#![feature(diagnostic_on_move)]` to the crate attributes to enable + = note: `#[warn(unknown_diagnostic_attributes)]` (part of `#[warn(unknown_or_malformed_diagnostic_attributes)]`) on by default + error[E0382]: use of moved value: `foo` - --> $DIR/feature-gate-diagnostic-on-move.rs:16:15 + --> $DIR/feature-gate-diagnostic-on-move.rs:15:15 | LL | let foo = Foo; | --- move occurs because `foo` has type `Foo`, which does not implement the `Copy` trait @@ -9,14 +18,14 @@ LL | let bar = foo; | ^^^ value used here after move | note: consider changing this parameter type in function `takes_foo` to borrow instead if owning the value isn't necessary - --> $DIR/feature-gate-diagnostic-on-move.rs:11:17 + --> $DIR/feature-gate-diagnostic-on-move.rs:10:17 | LL | fn takes_foo(_: Foo) {} | --------- ^^^ this parameter takes ownership of the value | | | in this function note: if `Foo` implemented `Clone`, you could clone the value - --> $DIR/feature-gate-diagnostic-on-move.rs:9:1 + --> $DIR/feature-gate-diagnostic-on-move.rs:8:1 | LL | struct Foo; | ^^^^^^^^^^ consider implementing `Clone` for this type @@ -24,6 +33,6 @@ LL | struct Foo; LL | takes_foo(foo); | --- you could clone this value -error: aborting due to 1 previous error +error: aborting due to 1 previous error; 1 warning emitted For more information about this error, try `rustc --explain E0382`. diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.rs b/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.rs new file mode 100644 index 000000000000..11cc0d50e0c9 --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.rs @@ -0,0 +1,8 @@ +#![deny(warnings)] + +#[diagnostic::on_unknown(message = "Tada")] +//~^ ERROR: unknown diagnostic attribute +use std::vec::NotExisting; +//~^ ERROR: unresolved import `std::vec::NotExisting` + +fn main() {} diff --git a/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.stderr b/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.stderr new file mode 100644 index 000000000000..d9c8071339b7 --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-diagnostic-on-unknown.stderr @@ -0,0 +1,23 @@ +error[E0432]: unresolved import `std::vec::NotExisting` + --> $DIR/feature-gate-diagnostic-on-unknown.rs:5:5 + | +LL | use std::vec::NotExisting; + | ^^^^^^^^^^^^^^^^^^^^^ no `NotExisting` in `vec` + +error: unknown diagnostic attribute + --> $DIR/feature-gate-diagnostic-on-unknown.rs:3:15 + | +LL | #[diagnostic::on_unknown(message = "Tada")] + | ^^^^^^^^^^ + | + = help: add `#![feature(diagnostic_on_unknown)]` to the crate attributes to enable +note: the lint level is defined here + --> $DIR/feature-gate-diagnostic-on-unknown.rs:1:9 + | +LL | #![deny(warnings)] + | ^^^^^^^^ + = note: `#[deny(unknown_diagnostic_attributes)]` implied by `#[deny(warnings)]` + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0432`. diff --git a/tests/ui/feature-gates/feature-gate-f16.e2015.stderr b/tests/ui/feature-gates/feature-gate-f16.e2015.stderr index 5d1ca8f6d047..b53f12af48fc 100644 --- a/tests/ui/feature-gates/feature-gate-f16.e2015.stderr +++ b/tests/ui/feature-gates/feature-gate-f16.e2015.stderr @@ -19,7 +19,7 @@ LL | let a: f16 = 100.0; = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date error[E0658]: the type `f16` is unstable - --> $DIR/feature-gate-f16.rs:16:11 + --> $DIR/feature-gate-f16.rs:19:11 | LL | fn foo(a: f16) {} | ^^^ @@ -29,7 +29,7 @@ LL | fn foo(a: f16) {} = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date error[E0658]: the type `f16` is unstable - --> $DIR/feature-gate-f16.rs:19:8 + --> $DIR/feature-gate-f16.rs:22:8 | LL | a: f16, | ^^^ @@ -58,6 +58,27 @@ LL | let c = 0f16; = help: add `#![feature(f16)]` to the crate attributes to enable = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date -error: aborting due to 6 previous errors +error[E0658]: the type `f16` is unstable + --> $DIR/feature-gate-f16.rs:13:18 + | +LL | let d: f32 = 1.0f16.into(); + | ^^^^^^ + | + = note: see issue #116909 for more information + = help: add `#![feature(f16)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + +error[E0658]: use of unstable library feature `f32_from_f16` + --> $DIR/feature-gate-f16.rs:13:25 + | +LL | let d: f32 = 1.0f16.into(); + | ^^^^ + | + = help: add `#![feature(f32_from_f16)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + = note: required for `f32` to implement `From` + = note: required for `f16` to implement `Into` + +error: aborting due to 8 previous errors For more information about this error, try `rustc --explain E0658`. diff --git a/tests/ui/feature-gates/feature-gate-f16.e2018.stderr b/tests/ui/feature-gates/feature-gate-f16.e2018.stderr index 5d1ca8f6d047..b53f12af48fc 100644 --- a/tests/ui/feature-gates/feature-gate-f16.e2018.stderr +++ b/tests/ui/feature-gates/feature-gate-f16.e2018.stderr @@ -19,7 +19,7 @@ LL | let a: f16 = 100.0; = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date error[E0658]: the type `f16` is unstable - --> $DIR/feature-gate-f16.rs:16:11 + --> $DIR/feature-gate-f16.rs:19:11 | LL | fn foo(a: f16) {} | ^^^ @@ -29,7 +29,7 @@ LL | fn foo(a: f16) {} = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date error[E0658]: the type `f16` is unstable - --> $DIR/feature-gate-f16.rs:19:8 + --> $DIR/feature-gate-f16.rs:22:8 | LL | a: f16, | ^^^ @@ -58,6 +58,27 @@ LL | let c = 0f16; = help: add `#![feature(f16)]` to the crate attributes to enable = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date -error: aborting due to 6 previous errors +error[E0658]: the type `f16` is unstable + --> $DIR/feature-gate-f16.rs:13:18 + | +LL | let d: f32 = 1.0f16.into(); + | ^^^^^^ + | + = note: see issue #116909 for more information + = help: add `#![feature(f16)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + +error[E0658]: use of unstable library feature `f32_from_f16` + --> $DIR/feature-gate-f16.rs:13:25 + | +LL | let d: f32 = 1.0f16.into(); + | ^^^^ + | + = help: add `#![feature(f32_from_f16)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + = note: required for `f32` to implement `From` + = note: required for `f16` to implement `Into` + +error: aborting due to 8 previous errors For more information about this error, try `rustc --explain E0658`. diff --git a/tests/ui/feature-gates/feature-gate-f16.rs b/tests/ui/feature-gates/feature-gate-f16.rs index f748c603efe9..6babc6c5c03c 100644 --- a/tests/ui/feature-gates/feature-gate-f16.rs +++ b/tests/ui/feature-gates/feature-gate-f16.rs @@ -10,6 +10,9 @@ pub fn main() { let a: f16 = 100.0; //~ ERROR the type `f16` is unstable let b = 0.0f16; //~ ERROR the type `f16` is unstable let c = 0f16; //~ ERROR the type `f16` is unstable + let d: f32 = 1.0f16.into(); + //~^ ERROR the type `f16` is unstable + //~| ERROR use of unstable library feature `f32_from_f16` foo(1.23); } diff --git a/tests/ui/feature-gates/feature-gate-f32_from_f16.rs b/tests/ui/feature-gates/feature-gate-f32_from_f16.rs new file mode 100644 index 000000000000..5a7381b85b0f --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-f32_from_f16.rs @@ -0,0 +1,7 @@ +#![feature(f16)] +#![allow(unused)] + +pub fn main() { + let _: f32 = 1.0f16.into(); + //~^ ERROR use of unstable library feature `f32_from_f16` +} diff --git a/tests/ui/feature-gates/feature-gate-f32_from_f16.stderr b/tests/ui/feature-gates/feature-gate-f32_from_f16.stderr new file mode 100644 index 000000000000..ce3e8ffb3b0d --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-f32_from_f16.stderr @@ -0,0 +1,14 @@ +error[E0658]: use of unstable library feature `f32_from_f16` + --> $DIR/feature-gate-f32_from_f16.rs:5:25 + | +LL | let _: f32 = 1.0f16.into(); + | ^^^^ + | + = help: add `#![feature(f32_from_f16)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + = note: required for `f32` to implement `From` + = note: required for `f16` to implement `Into` + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0658`. diff --git a/tests/ui/feature-gates/feature-gate-fma4_target_feature.rs b/tests/ui/feature-gates/feature-gate-fma4_target_feature.rs new file mode 100644 index 000000000000..afab2f947751 --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-fma4_target_feature.rs @@ -0,0 +1,6 @@ +//@ only-x86_64 +#[target_feature(enable = "fma4")] +//~^ ERROR: currently unstable +unsafe fn foo() {} + +fn main() {} diff --git a/tests/ui/feature-gates/feature-gate-fma4_target_feature.stderr b/tests/ui/feature-gates/feature-gate-fma4_target_feature.stderr new file mode 100644 index 000000000000..b28bb0713fb1 --- /dev/null +++ b/tests/ui/feature-gates/feature-gate-fma4_target_feature.stderr @@ -0,0 +1,13 @@ +error[E0658]: the target feature `fma4` is currently unstable + --> $DIR/feature-gate-fma4_target_feature.rs:2:18 + | +LL | #[target_feature(enable = "fma4")] + | ^^^^^^^^^^^^^^^ + | + = note: see issue #155233 for more information + = help: add `#![feature(fma4_target_feature)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0658`. diff --git a/tests/ui/feature-gates/feature-gate-fn_align.stderr b/tests/ui/feature-gates/feature-gate-fn_align.stderr index 6196f4f298fd..249791511741 100644 --- a/tests/ui/feature-gates/feature-gate-fn_align.stderr +++ b/tests/ui/feature-gates/feature-gate-fn_align.stderr @@ -22,10 +22,12 @@ error[E0539]: malformed `rustc_align` attribute input --> $DIR/feature-gate-fn_align.rs:12:5 | LL | #[rustc_align] - | ^^^^^^^^^^^^^^ - | | - | expected this to be a list - | help: must be of the form: `#[rustc_align()]` + | ^^^^^^^^^^^^^^ expected this to be a list + | +help: must be of the form + | +LL | #[rustc_align()] + | ++++++++++++++++++++++ error: aborting due to 3 previous errors diff --git a/tests/ui/feature-gates/feature-gate-generic-const-parameter-types.normal.stderr b/tests/ui/feature-gates/feature-gate-generic-const-parameter-types.normal.stderr index 1377f845d164..48b3c43c30a0 100644 --- a/tests/ui/feature-gates/feature-gate-generic-const-parameter-types.normal.stderr +++ b/tests/ui/feature-gates/feature-gate-generic-const-parameter-types.normal.stderr @@ -11,9 +11,9 @@ LL | struct MyADT; | ^^^^^^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | error: aborting due to 2 previous errors diff --git a/tests/ui/feature-gates/feature-gate-offset-of-enum.stderr b/tests/ui/feature-gates/feature-gate-offset-of-enum.stderr index 55f1a83cb37c..0ba8afa12c63 100644 --- a/tests/ui/feature-gates/feature-gate-offset-of-enum.stderr +++ b/tests/ui/feature-gates/feature-gate-offset-of-enum.stderr @@ -2,10 +2,13 @@ error[E0573]: expected type, found variant `Alpha::One` --> $DIR/feature-gate-offset-of-enum.rs:10:16 | LL | offset_of!(Alpha::One, 0); - | ^^^^^^^^^^ - | | - | not a type - | help: try using the variant's enum: `Alpha` + | ^^^^^^^^^^ not a type + | +help: try using the variant's enum + | +LL - offset_of!(Alpha::One, 0); +LL + offset_of!(Alpha, 0); + | error[E0658]: using enums in offset_of is experimental --> $DIR/feature-gate-offset-of-enum.rs:11:23 diff --git a/tests/ui/feature-gates/feature-gate-unsized-const-params.rs b/tests/ui/feature-gates/feature-gate-unsized-const-params.rs index d088d382377c..c38aa3ea4f75 100644 --- a/tests/ui/feature-gates/feature-gate-unsized-const-params.rs +++ b/tests/ui/feature-gates/feature-gate-unsized-const-params.rs @@ -1,6 +1,6 @@ struct Foo; //~^ ERROR: `[u8]` is forbidden as the type of a const generic parameter -//~| HELP: add `#![feature(adt_const_params)]` to the crate +//~| HELP: add `#![feature(min_adt_const_params)]` to the crate //~| HELP: add `#![feature(unsized_const_params)]` to the crate fn main() {} diff --git a/tests/ui/feature-gates/feature-gate-unsized-const-params.stderr b/tests/ui/feature-gates/feature-gate-unsized-const-params.stderr index 85ca2f59cb63..90906058dfe6 100644 --- a/tests/ui/feature-gates/feature-gate-unsized-const-params.stderr +++ b/tests/ui/feature-gates/feature-gate-unsized-const-params.stderr @@ -5,9 +5,9 @@ LL | struct Foo; | ^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | help: add `#![feature(unsized_const_params)]` to the crate attributes to enable references to implement the `ConstParamTy` trait | diff --git a/tests/ui/feature-gates/gated-bad-feature.stderr b/tests/ui/feature-gates/gated-bad-feature.stderr index afcc6b6f11c4..d5cce2267cec 100644 --- a/tests/ui/feature-gates/gated-bad-feature.stderr +++ b/tests/ui/feature-gates/gated-bad-feature.stderr @@ -11,36 +11,53 @@ error[E0565]: malformed `feature` attribute input | LL | #![feature(foo_bar_baz, foo(bar), foo = "baz", foo)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^-----^^^^^^^^^^^^^^^^^^^^ - | | | - | | didn't expect any arguments here - | help: must be of the form: `#![feature(feature1, feature2, ...)]` + | | + | didn't expect any arguments here + | +help: must be of the form + | +LL - #![feature(foo_bar_baz, foo(bar), foo = "baz", foo)] +LL + #![feature(feature1, feature2, ...)] + | error[E0565]: malformed `feature` attribute input --> $DIR/gated-bad-feature.rs:1:1 | LL | #![feature(foo_bar_baz, foo(bar), foo = "baz", foo)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^-------^^^^^^^ - | | | - | | didn't expect any arguments here - | help: must be of the form: `#![feature(feature1, feature2, ...)]` + | | + | didn't expect any arguments here + | +help: must be of the form + | +LL - #![feature(foo_bar_baz, foo(bar), foo = "baz", foo)] +LL + #![feature(feature1, feature2, ...)] + | error[E0539]: malformed `feature` attribute input --> $DIR/gated-bad-feature.rs:6:1 | LL | #![feature] - | ^^^^^^^^^^^ - | | - | expected this to be a list - | help: must be of the form: `#![feature(feature1, feature2, ...)]` + | ^^^^^^^^^^^ expected this to be a list + | +help: must be of the form + | +LL | #![feature(feature1, feature2, ...)] + | +++++++++++++++++++++++++ error[E0539]: malformed `feature` attribute input --> $DIR/gated-bad-feature.rs:7:1 | LL | #![feature = "foo"] | ^^^^^^^^^^^-------^ - | | | - | | expected this to be a list - | help: must be of the form: `#![feature(feature1, feature2, ...)]` + | | + | expected this to be a list + | +help: must be of the form + | +LL - #![feature = "foo"] +LL + #![feature(feature1, feature2, ...)] + | error[E0635]: unknown feature `foo_bar_baz` --> $DIR/gated-bad-feature.rs:1:12 diff --git a/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr b/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr index 0bfda62ef844..724d623e79ee 100644 --- a/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr +++ b/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr @@ -12,96 +12,11 @@ warning: `#[macro_escape]` is a deprecated synonym for `#[macro_use]` LL | #[macro_escape] | ^^^^^^^^^^^^^^^ -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:685:1 - | -LL | #[link(name = "x")] - | ^^^^^^^^^^^^^^^^^^^ -... -LL | / mod link { -LL | | -LL | | -LL | | mod inner { #![link(name = "x")] } -... | -LL | | } - | |_- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! -note: the lint level is defined here - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:36:9 - | -LL | #![warn(unused_attributes, unknown_lints)] - | ^^^^^^^^^^^^^^^^^ - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:70:1 - | -LL | #![link(name = "x")] - | ^^^^^^^^^^^^^^^^^^^^ not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: the feature `rust1` has been stable since 1.0.0 and no longer requires an attribute to enable - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:98:12 - | -LL | #![feature(rust1)] - | ^^^^^ - | - = note: `#[warn(stable_features)]` on by default - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:691:17 - | -LL | mod inner { #![link(name = "x")] } - | ------------^^^^^^^^^^^^^^^^^^^^-- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:696:5 - | -LL | #[link(name = "x")] fn f() { } - | ^^^^^^^^^^^^^^^^^^^ ---------- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:701:5 - | -LL | #[link(name = "x")] struct S; - | ^^^^^^^^^^^^^^^^^^^ --------- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:706:5 - | -LL | #[link(name = "x")] type T = S; - | ^^^^^^^^^^^^^^^^^^^ ----------- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:711:5 - | -LL | #[link(name = "x")] impl S { } - | ^^^^^^^^^^^^^^^^^^^ ---------- not an `extern` block - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - -warning: attribute should be applied to an `extern` block with non-Rust ABI - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:716:5 - | -LL | #[link(name = "x")] extern "Rust" {} - | ^^^^^^^^^^^^^^^^^^^ - | - = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - warning: unknown lint: `x5400` - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:109:8 + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:42:9 | -LL | #[warn(x5400)] - | ^^^^^ +LL | #![warn(x5400)] + | ^^^^^ | note: the lint level is defined here --> $DIR/issue-43106-gating-of-builtin-attrs.rs:36:28 @@ -109,6 +24,30 @@ note: the lint level is defined here LL | #![warn(unused_attributes, unknown_lints)] | ^^^^^^^^^^^^^ +warning: unknown lint: `x5300` + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:43:10 + | +LL | #![allow(x5300)] + | ^^^^^ + +warning: unknown lint: `x5200` + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:44:11 + | +LL | #![forbid(x5200)] + | ^^^^^ + +warning: unknown lint: `x5100` + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:45:9 + | +LL | #![deny(x5100)] + | ^^^^^ + +warning: unknown lint: `x5400` + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:109:8 + | +LL | #[warn(x5400)] + | ^^^^^ + warning: unknown lint: `x5400` --> $DIR/issue-43106-gating-of-builtin-attrs.rs:112:25 | @@ -247,6 +186,91 @@ warning: unknown lint: `x5100` LL | #[deny(x5100)] impl S { } | ^^^^^ +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:685:1 + | +LL | #[link(name = "x")] + | ^^^^^^^^^^^^^^^^^^^ +... +LL | / mod link { +LL | | +LL | | +LL | | mod inner { #![link(name = "x")] } +... | +LL | | } + | |_- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! +note: the lint level is defined here + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:36:9 + | +LL | #![warn(unused_attributes, unknown_lints)] + | ^^^^^^^^^^^^^^^^^ + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:70:1 + | +LL | #![link(name = "x")] + | ^^^^^^^^^^^^^^^^^^^^ not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: the feature `rust1` has been stable since 1.0.0 and no longer requires an attribute to enable + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:98:12 + | +LL | #![feature(rust1)] + | ^^^^^ + | + = note: `#[warn(stable_features)]` on by default + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:691:17 + | +LL | mod inner { #![link(name = "x")] } + | ------------^^^^^^^^^^^^^^^^^^^^-- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:696:5 + | +LL | #[link(name = "x")] fn f() { } + | ^^^^^^^^^^^^^^^^^^^ ---------- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:701:5 + | +LL | #[link(name = "x")] struct S; + | ^^^^^^^^^^^^^^^^^^^ --------- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:706:5 + | +LL | #[link(name = "x")] type T = S; + | ^^^^^^^^^^^^^^^^^^^ ----------- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:711:5 + | +LL | #[link(name = "x")] impl S { } + | ^^^^^^^^^^^^^^^^^^^ ---------- not an `extern` block + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + +warning: attribute should be applied to an `extern` block with non-Rust ABI + --> $DIR/issue-43106-gating-of-builtin-attrs.rs:716:5 + | +LL | #[link(name = "x")] extern "Rust" {} + | ^^^^^^^^^^^^^^^^^^^ + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + warning: `#[macro_use]` attribute cannot be used on functions --> $DIR/issue-43106-gating-of-builtin-attrs.rs:189:5 | @@ -1498,30 +1522,6 @@ note: this attribute does not have an `!`, which means it is applied to this imp LL | #[type_length_limit="0100"] impl S { } | ^^^^^^^^^^ -warning: unknown lint: `x5400` - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:42:9 - | -LL | #![warn(x5400)] - | ^^^^^ - -warning: unknown lint: `x5300` - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:43:10 - | -LL | #![allow(x5300)] - | ^^^^^ - -warning: unknown lint: `x5200` - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:44:11 - | -LL | #![forbid(x5200)] - | ^^^^^ - -warning: unknown lint: `x5100` - --> $DIR/issue-43106-gating-of-builtin-attrs.rs:45:9 - | -LL | #![deny(x5100)] - | ^^^^^ - warning: `#[should_panic]` attribute cannot be used on crates --> $DIR/issue-43106-gating-of-builtin-attrs.rs:49:1 | diff --git a/tests/ui/float/f16-into-f32.rs b/tests/ui/float/f16-into-f32.rs new file mode 100644 index 000000000000..ad428edec727 --- /dev/null +++ b/tests/ui/float/f16-into-f32.rs @@ -0,0 +1,17 @@ +//@ build-pass +#![feature(f16, f32_from_f16)] +#![allow(unused)] + +// Check that float conversions work, specifically a {float} literal that normally would fall back +// to an f64 but due to the Into bound here falls back to f32. Also test that the lint is emitted in +// the correct location, and can be `expect`ed or `allow`ed. +fn convert(x: impl Into) -> f32 { + x.into() +} + +pub fn main() { + let _ = convert(1.0f32); + let _ = convert(1.0f16); + #[expect(float_literal_f32_fallback)] + let _ = convert(1.0); +} diff --git a/tests/ui/float/f32-into-f32.next-solver.fixed b/tests/ui/float/f32-into-f32.next-solver.fixed new file mode 100644 index 000000000000..a8d56f4428b9 --- /dev/null +++ b/tests/ui/float/f32-into-f32.next-solver.fixed @@ -0,0 +1,23 @@ +//@ revisions: old-solver next-solver +//@[next-solver] compile-flags: -Znext-solver +//@ run-pass +//@ run-rustfix + +fn foo(_: impl Into) {} + +fn main() { + foo(1.0_f32); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(-(2.5_f32)); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(1e5_f32); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(4f32); // no warning + let x = -4.0_f32; + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(x); +} diff --git a/tests/ui/float/f32-into-f32.next-solver.stderr b/tests/ui/float/f32-into-f32.next-solver.stderr new file mode 100644 index 000000000000..fc88f9d2c7f3 --- /dev/null +++ b/tests/ui/float/f32-into-f32.next-solver.stderr @@ -0,0 +1,39 @@ +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:9:9 + | +LL | foo(1.0); + | ^^^ help: explicitly specify the type as `f32`: `1.0_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + = note: `#[warn(float_literal_f32_fallback)]` (part of `#[warn(future_incompatible)]`) on by default + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:12:11 + | +LL | foo(-(2.5)); + | ^^^ help: explicitly specify the type as `f32`: `2.5_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:15:9 + | +LL | foo(1e5); + | ^^^ help: explicitly specify the type as `f32`: `1e5_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:19:14 + | +LL | let x = -4.0; + | ^^^ help: explicitly specify the type as `f32`: `4.0_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: 4 warnings emitted + diff --git a/tests/ui/float/f32-into-f32.old-solver.fixed b/tests/ui/float/f32-into-f32.old-solver.fixed new file mode 100644 index 000000000000..a8d56f4428b9 --- /dev/null +++ b/tests/ui/float/f32-into-f32.old-solver.fixed @@ -0,0 +1,23 @@ +//@ revisions: old-solver next-solver +//@[next-solver] compile-flags: -Znext-solver +//@ run-pass +//@ run-rustfix + +fn foo(_: impl Into) {} + +fn main() { + foo(1.0_f32); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(-(2.5_f32)); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(1e5_f32); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(4f32); // no warning + let x = -4.0_f32; + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(x); +} diff --git a/tests/ui/float/f32-into-f32.old-solver.stderr b/tests/ui/float/f32-into-f32.old-solver.stderr new file mode 100644 index 000000000000..fc88f9d2c7f3 --- /dev/null +++ b/tests/ui/float/f32-into-f32.old-solver.stderr @@ -0,0 +1,39 @@ +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:9:9 + | +LL | foo(1.0); + | ^^^ help: explicitly specify the type as `f32`: `1.0_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + = note: `#[warn(float_literal_f32_fallback)]` (part of `#[warn(future_incompatible)]`) on by default + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:12:11 + | +LL | foo(-(2.5)); + | ^^^ help: explicitly specify the type as `f32`: `2.5_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:15:9 + | +LL | foo(1e5); + | ^^^ help: explicitly specify the type as `f32`: `1e5_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: falling back to `f32` as the trait bound `f32: From` is not satisfied + --> $DIR/f32-into-f32.rs:19:14 + | +LL | let x = -4.0; + | ^^^ help: explicitly specify the type as `f32`: `4.0_f32` + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #154024 + +warning: 4 warnings emitted + diff --git a/tests/ui/float/f32-into-f32.rs b/tests/ui/float/f32-into-f32.rs new file mode 100644 index 000000000000..b55023453b7e --- /dev/null +++ b/tests/ui/float/f32-into-f32.rs @@ -0,0 +1,23 @@ +//@ revisions: old-solver next-solver +//@[next-solver] compile-flags: -Znext-solver +//@ run-pass +//@ run-rustfix + +fn foo(_: impl Into) {} + +fn main() { + foo(1.0); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(-(2.5)); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(1e5); + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(4f32); // no warning + let x = -4.0; + //~^ WARN falling back to `f32` + //~| WARN this was previously accepted + foo(x); +} diff --git a/tests/ui/float/trait-f16-or-f32.rs b/tests/ui/float/trait-f16-or-f32.rs new file mode 100644 index 000000000000..72f0a4fbde47 --- /dev/null +++ b/tests/ui/float/trait-f16-or-f32.rs @@ -0,0 +1,13 @@ +//@ check-fail + +#![feature(f16)] + +trait Trait {} +impl Trait for f16 {} +impl Trait for f32 {} + +fn foo(_: impl Trait) {} + +fn main() { + foo(1.0); //~ ERROR the trait bound `f64: Trait` is not satisfied +} diff --git a/tests/ui/float/trait-f16-or-f32.stderr b/tests/ui/float/trait-f16-or-f32.stderr new file mode 100644 index 000000000000..0117d787bc61 --- /dev/null +++ b/tests/ui/float/trait-f16-or-f32.stderr @@ -0,0 +1,24 @@ +error[E0277]: the trait bound `f64: Trait` is not satisfied + --> $DIR/trait-f16-or-f32.rs:12:9 + | +LL | foo(1.0); + | --- ^^^ the trait `Trait` is not implemented for `f64` + | | + | required by a bound introduced by this call + | +help: the following other types implement trait `Trait` + --> $DIR/trait-f16-or-f32.rs:6:1 + | +LL | impl Trait for f16 {} + | ^^^^^^^^^^^^^^^^^^ `f16` +LL | impl Trait for f32 {} + | ^^^^^^^^^^^^^^^^^^ `f32` +note: required by a bound in `foo` + --> $DIR/trait-f16-or-f32.rs:9:16 + | +LL | fn foo(_: impl Trait) {} + | ^^^^^ required by this bound in `foo` + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0277`. diff --git a/tests/ui/issues/issue-45425.rs b/tests/ui/higher-ranked/binop-lhs-hrtb-subtyping.rs similarity index 69% rename from tests/ui/issues/issue-45425.rs rename to tests/ui/higher-ranked/binop-lhs-hrtb-subtyping.rs index fad8284caf5b..9408bc120e1c 100644 --- a/tests/ui/issues/issue-45425.rs +++ b/tests/ui/higher-ranked/binop-lhs-hrtb-subtyping.rs @@ -1,3 +1,4 @@ +//! Regression test for //@ check-pass #![allow(dead_code)] use std::ops::Add; diff --git a/tests/ui/impl-restriction/auxiliary/external-impl-restriction.rs b/tests/ui/impl-restriction/auxiliary/external-impl-restriction.rs new file mode 100644 index 000000000000..785aeedf56d5 --- /dev/null +++ b/tests/ui/impl-restriction/auxiliary/external-impl-restriction.rs @@ -0,0 +1,8 @@ +#![feature(impl_restriction)] +#![expect(incomplete_features)] + +pub impl(crate) trait TopLevel {} + +pub mod inner { + pub impl(self) trait Inner {} +} diff --git a/tests/ui/impl-restriction/impl-restriction-check.e2015.stderr b/tests/ui/impl-restriction/impl-restriction-check.e2015.stderr new file mode 100644 index 000000000000..402464f8a545 --- /dev/null +++ b/tests/ui/impl-restriction/impl-restriction-check.e2015.stderr @@ -0,0 +1,98 @@ +error: trait cannot be implemented outside `external` + --> $DIR/impl-restriction-check.rs:12:1 + | +LL | impl external::TopLevel for LocalType {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/auxiliary/external-impl-restriction.rs:4:5 + | +LL | pub impl(crate) trait TopLevel {} + | ^^^^^^^^^^^ + +error: trait cannot be implemented outside `external` + --> $DIR/impl-restriction-check.rs:13:1 + | +LL | impl external::inner::Inner for LocalType {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/auxiliary/external-impl-restriction.rs:7:9 + | +LL | pub impl(self) trait Inner {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `foo::bar` + --> $DIR/impl-restriction-check.rs:30:5 + | +LL | impl bar::Foo for i8 {} + | ^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:17:20 + | +LL | pub(crate) impl(self) trait Foo {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `foo::bar` + --> $DIR/impl-restriction-check.rs:39:1 + | +LL | impl foo::bar::Foo for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:17:20 + | +LL | pub(crate) impl(self) trait Foo {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `foo` + --> $DIR/impl-restriction-check.rs:41:1 + | +LL | impl foo::bar::Bar for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:18:20 + | +LL | pub(crate) impl(super) trait Bar {} + | ^^^^^^^^^^^ + +error: trait cannot be implemented outside `foo::bar` + --> $DIR/impl-restriction-check.rs:34:5 + | +LL | impl bar::Qux for i8 {} + | ^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:20:20 + | +LL | pub(crate) impl(in crate::foo::bar) trait Qux {} + | ^^^^^^^^^^^^^^^^^^^^^^^^ + +error: trait cannot be implemented outside `foo::bar` + --> $DIR/impl-restriction-check.rs:44:1 + | +LL | impl foo::bar::Qux for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:20:20 + | +LL | pub(crate) impl(in crate::foo::bar) trait Qux {} + | ^^^^^^^^^^^^^^^^^^^^^^^^ + +error: trait cannot be implemented outside `foo` + --> $DIR/impl-restriction-check.rs:46:1 + | +LL | impl foo::bar::FooBar for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:21:20 + | +LL | pub(crate) impl(in crate::foo) trait FooBar {} + | ^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 8 previous errors + diff --git a/tests/ui/impl-restriction/impl-restriction-check.e2018.stderr b/tests/ui/impl-restriction/impl-restriction-check.e2018.stderr new file mode 100644 index 000000000000..8bd256cc9cae --- /dev/null +++ b/tests/ui/impl-restriction/impl-restriction-check.e2018.stderr @@ -0,0 +1,98 @@ +error: trait cannot be implemented outside `external` + --> $DIR/impl-restriction-check.rs:12:1 + | +LL | impl external::TopLevel for LocalType {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/auxiliary/external-impl-restriction.rs:4:5 + | +LL | pub impl(crate) trait TopLevel {} + | ^^^^^^^^^^^ + +error: trait cannot be implemented outside `external` + --> $DIR/impl-restriction-check.rs:13:1 + | +LL | impl external::inner::Inner for LocalType {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/auxiliary/external-impl-restriction.rs:7:9 + | +LL | pub impl(self) trait Inner {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo::bar` + --> $DIR/impl-restriction-check.rs:30:5 + | +LL | impl bar::Foo for i8 {} + | ^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:17:20 + | +LL | pub(crate) impl(self) trait Foo {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo::bar` + --> $DIR/impl-restriction-check.rs:39:1 + | +LL | impl foo::bar::Foo for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:17:20 + | +LL | pub(crate) impl(self) trait Foo {} + | ^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo` + --> $DIR/impl-restriction-check.rs:41:1 + | +LL | impl foo::bar::Bar for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:18:20 + | +LL | pub(crate) impl(super) trait Bar {} + | ^^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo::bar` + --> $DIR/impl-restriction-check.rs:34:5 + | +LL | impl bar::Qux for i8 {} + | ^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:20:20 + | +LL | pub(crate) impl(in crate::foo::bar) trait Qux {} + | ^^^^^^^^^^^^^^^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo::bar` + --> $DIR/impl-restriction-check.rs:44:1 + | +LL | impl foo::bar::Qux for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:20:20 + | +LL | pub(crate) impl(in crate::foo::bar) trait Qux {} + | ^^^^^^^^^^^^^^^^^^^^^^^^ + +error: trait cannot be implemented outside `crate::foo` + --> $DIR/impl-restriction-check.rs:46:1 + | +LL | impl foo::bar::FooBar for u8 {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | +note: trait restricted here + --> $DIR/impl-restriction-check.rs:21:20 + | +LL | pub(crate) impl(in crate::foo) trait FooBar {} + | ^^^^^^^^^^^^^^^^^^^ + +error: aborting due to 8 previous errors + diff --git a/tests/ui/impl-restriction/impl-restriction-check.rs b/tests/ui/impl-restriction/impl-restriction-check.rs new file mode 100644 index 000000000000..cf5e699dfce9 --- /dev/null +++ b/tests/ui/impl-restriction/impl-restriction-check.rs @@ -0,0 +1,49 @@ +//@ aux-build: external-impl-restriction.rs +//@ revisions: e2015 e2018 +//@ [e2015] edition: 2015 +//@ [e2018] edition: 2018.. +#![feature(impl_restriction)] +#![expect(incomplete_features)] + +extern crate external_impl_restriction as external; + +struct LocalType; // needed to avoid orphan rule errors + +impl external::TopLevel for LocalType {} //~ ERROR trait cannot be implemented outside `external` +impl external::inner::Inner for LocalType {} //~ ERROR trait cannot be implemented outside `external` + +pub mod foo { + pub mod bar { + pub(crate) impl(self) trait Foo {} + pub(crate) impl(super) trait Bar {} + pub impl(crate) trait Baz {} + pub(crate) impl(in crate::foo::bar) trait Qux {} + pub(crate) impl(in crate::foo) trait FooBar {} + + impl Foo for i16 {} // OK + impl Bar for i16 {} // OK + impl Baz for i16 {} // OK + impl Qux for i16 {} // OK + impl FooBar for i16 {} // OK + } + + impl bar::Foo for i8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo::bar` + //[e2018]~^ ERROR trait cannot be implemented outside `crate::foo::bar` + impl bar::Bar for i8 {} // OK + impl bar::Baz for i8 {} // OK + impl bar::Qux for i8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo::bar` + //[e2018]~^ ERROR trait cannot be implemented outside `crate::foo::bar` + impl bar::FooBar for i8 {} // OK +} + +impl foo::bar::Foo for u8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo::bar` +//[e2018]~^ ERROR trait cannot be implemented outside `crate::foo::bar` +impl foo::bar::Bar for u8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo` +//[e2018]~^ ERROR trait cannot be implemented outside `crate::foo` +impl foo::bar::Baz for u8 {} // OK +impl foo::bar::Qux for u8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo::bar` +//[e2018]~^ ERROR trait cannot be implemented outside `crate::foo::bar` +impl foo::bar::FooBar for u8 {} //[e2015]~ ERROR trait cannot be implemented outside `foo` +//[e2018]~^ ERROR trait cannot be implemented outside `crate::foo` + +fn main() {} diff --git a/tests/ui/impl-restriction/restriction_resolution_errors.rs b/tests/ui/impl-restriction/restriction_resolution_errors.rs index b36f2cf9bdfb..01173c111ae7 100644 --- a/tests/ui/impl-restriction/restriction_resolution_errors.rs +++ b/tests/ui/impl-restriction/restriction_resolution_errors.rs @@ -1,6 +1,9 @@ +//@ aux-build: external-impl-restriction.rs #![feature(impl_restriction)] #![expect(incomplete_features)] +extern crate external_impl_restriction as external; + pub mod a { pub enum E {} pub mod d {} @@ -53,6 +56,8 @@ pub mod h {} pub impl(super) trait T17 {} //~ ERROR too many leading `super` keywords [E0433] +pub impl(in external) trait T18 {} //~ ERROR trait implementation can only be restricted to ancestor modules + // Check if we can resolve paths referring to modules declared later. pub impl(in crate::j) trait L4 {} //~ ERROR trait implementation can only be restricted to ancestor modules diff --git a/tests/ui/impl-restriction/restriction_resolution_errors.stderr b/tests/ui/impl-restriction/restriction_resolution_errors.stderr index 540803285c1b..48bfab2bc1eb 100644 --- a/tests/ui/impl-restriction/restriction_resolution_errors.stderr +++ b/tests/ui/impl-restriction/restriction_resolution_errors.stderr @@ -1,71 +1,77 @@ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:14:21 + --> $DIR/restriction_resolution_errors.rs:17:21 | LL | pub impl(in ::std) trait T2 {} | ^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:16:21 + --> $DIR/restriction_resolution_errors.rs:19:21 | LL | pub impl(in self::c) trait T3 {} | ^^^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:18:21 + --> $DIR/restriction_resolution_errors.rs:21:21 | LL | pub impl(in super::d) trait T4 {} | ^^^^^^^^ error[E0433]: too many leading `super` keywords - --> $DIR/restriction_resolution_errors.rs:24:35 + --> $DIR/restriction_resolution_errors.rs:27:35 | LL | pub impl(in super::super::super) trait T7 {} | ^^^^^ there are too many leading `super` keywords error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:34:21 + --> $DIR/restriction_resolution_errors.rs:37:21 | LL | pub impl(in self::f) trait L1 {} | ^^^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:38:21 + --> $DIR/restriction_resolution_errors.rs:41:21 | LL | pub impl(in super::h) trait L3 {} | ^^^^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:47:13 + --> $DIR/restriction_resolution_errors.rs:50:13 | LL | pub impl(in crate::a) trait T13 {} | ^^^^^^^^ error[E0433]: too many leading `super` keywords - --> $DIR/restriction_resolution_errors.rs:54:10 + --> $DIR/restriction_resolution_errors.rs:57:10 | LL | pub impl(super) trait T17 {} | ^^^^^ there are too many leading `super` keywords error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:57:13 + --> $DIR/restriction_resolution_errors.rs:59:13 + | +LL | pub impl(in external) trait T18 {} + | ^^^^^^^^ + +error: trait implementation can only be restricted to ancestor modules + --> $DIR/restriction_resolution_errors.rs:62:13 | LL | pub impl(in crate::j) trait L4 {} | ^^^^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:73:21 + --> $DIR/restriction_resolution_errors.rs:78:21 | LL | pub impl(in crate::m2) trait U2 {} | ^^^^^^^^^ error: trait implementation can only be restricted to ancestor modules - --> $DIR/restriction_resolution_errors.rs:75:21 + --> $DIR/restriction_resolution_errors.rs:80:21 | LL | pub impl(in m6::m5) trait U4 {} | ^^^^^^ error[E0433]: cannot find module or crate `a` in this scope - --> $DIR/restriction_resolution_errors.rs:12:21 + --> $DIR/restriction_resolution_errors.rs:15:21 | LL | pub impl(in a::b) trait T1 {} | ^ use of unresolved module or unlinked crate `a` @@ -81,25 +87,25 @@ LL + use a; | error[E0433]: cannot find module `c` in the crate root - --> $DIR/restriction_resolution_errors.rs:20:28 + --> $DIR/restriction_resolution_errors.rs:23:28 | LL | pub impl(in crate::c) trait T5 {} | ^ not found in the crate root error[E0577]: expected module, found enum `super::E` - --> $DIR/restriction_resolution_errors.rs:22:21 + --> $DIR/restriction_resolution_errors.rs:25:21 | LL | pub impl(in super::E) trait T6 {} | ^^^^^^^^ not a module error[E0577]: expected module, found enum `super::G` - --> $DIR/restriction_resolution_errors.rs:36:21 + --> $DIR/restriction_resolution_errors.rs:39:21 | LL | pub impl(in super::G) trait L2 {} | ^^^^^^^^ not a module error[E0577]: expected module, found enum `crate::a::E` - --> $DIR/restriction_resolution_errors.rs:49:13 + --> $DIR/restriction_resolution_errors.rs:52:13 | LL | pub mod b { | --------- similarly named module `b` defined here @@ -114,7 +120,7 @@ LL + pub impl(in crate::a::b) trait T14 {} | error[E0577]: expected module, found enum `crate::I` - --> $DIR/restriction_resolution_errors.rs:59:13 + --> $DIR/restriction_resolution_errors.rs:64:13 | LL | pub mod a { | --------- similarly named module `a` defined here @@ -129,12 +135,12 @@ LL + pub impl(in crate::a) trait L5 {} | error[E0577]: expected module, found enum `m7` - --> $DIR/restriction_resolution_errors.rs:76:21 + --> $DIR/restriction_resolution_errors.rs:81:21 | LL | pub impl(in m7) trait U5 {} | ^^ not a module -error: aborting due to 18 previous errors +error: aborting due to 19 previous errors Some errors have detailed explanations: E0433, E0577. For more information about an error, try `rustc --explain E0433`. diff --git a/tests/ui/impl-trait/diagnostics/highlight-difference-between-expected-trait-and-found-trait.svg b/tests/ui/impl-trait/diagnostics/highlight-difference-between-expected-trait-and-found-trait.svg index caf840ca60a1..6e68356c4813 100644 --- a/tests/ui/impl-trait/diagnostics/highlight-difference-between-expected-trait-and-found-trait.svg +++ b/tests/ui/impl-trait/diagnostics/highlight-difference-between-expected-trait-and-found-trait.svg @@ -1,4 +1,4 @@ - +

` (where P is one of the previous types except `Self`) -error: aborting due to 2 previous errors +error: aborting due to 3 previous errors -Some errors have detailed explanations: E0277, E0801. -For more information about an error, try `rustc --explain E0277`. +Some errors have detailed explanations: E0015, E0493, E0801. +For more information about an error, try `rustc --explain E0015`. diff --git a/tests/ui/self/arbitrary-self-types-dyn-receiver.rs b/tests/ui/self/arbitrary-self-types-dyn-receiver.rs new file mode 100644 index 000000000000..fe128301d497 --- /dev/null +++ b/tests/ui/self/arbitrary-self-types-dyn-receiver.rs @@ -0,0 +1,21 @@ +//@ run-pass +#![feature(arbitrary_self_types)] + +use std::ops::Receiver; + +trait Trait { + fn foo(self: &dyn Receiver); +} + +struct Thing; +impl Trait for Thing { + fn foo(self: &dyn Receiver) { + println!("huh???"); + } +} + +fn main() { + let x = Box::new(Thing); + let y: &dyn Receiver = &x; + y.foo(); +} diff --git a/tests/ui/span/E0805.stderr b/tests/ui/span/E0805.stderr index 0247e8d8ec9b..17f719a6efb1 100644 --- a/tests/ui/span/E0805.stderr +++ b/tests/ui/span/E0805.stderr @@ -3,11 +3,15 @@ error[E0805]: malformed `cfg` macro input | LL | if cfg!(not()) { } | ^^^^^^^^--^ - | | | - | | expected a single argument here - | help: must be of the form: `cfg!(predicate)` + | | + | expected an argument here | = note: for more information, visit +help: must be of the form + | +LL - if cfg!(not()) { } +LL + if cfg!(predicate) { } + | error: aborting due to 1 previous error diff --git a/tests/ui/span/mutability-suggestion-fullwidth-ampersand.rs b/tests/ui/span/mutability-suggestion-fullwidth-ampersand.rs new file mode 100644 index 000000000000..a9bdd381307e --- /dev/null +++ b/tests/ui/span/mutability-suggestion-fullwidth-ampersand.rs @@ -0,0 +1,9 @@ +// Regression test for https://github.com/rust-lang/rust/issues/139089 + +fn foo(x: ＆Vec) { + //~^ ERROR unknown start of token + x.push(0); + //~^ ERROR cannot borrow `*x` as mutable +} + +fn main() {} diff --git a/tests/ui/span/mutability-suggestion-fullwidth-ampersand.stderr b/tests/ui/span/mutability-suggestion-fullwidth-ampersand.stderr new file mode 100644 index 000000000000..e6712f5da9a8 --- /dev/null +++ b/tests/ui/span/mutability-suggestion-fullwidth-ampersand.stderr @@ -0,0 +1,27 @@ +error: unknown start of token: \u{ff06} + --> $DIR/mutability-suggestion-fullwidth-ampersand.rs:3:11 + | +LL | fn foo(x: ＆Vec) { + | ^^ + | +help: Unicode character '＆' (Fullwidth Ampersand) looks like '&' (Ampersand), but it is not + | +LL - fn foo(x: ＆Vec) { +LL + fn foo(x: &Vec) { + | + +error[E0596]: cannot borrow `*x` as mutable, as it is behind a `&` reference + --> $DIR/mutability-suggestion-fullwidth-ampersand.rs:5:5 + | +LL | x.push(0); + | ^ `x` is a `&` reference, so it cannot be borrowed as mutable + | +help: consider changing this to be a mutable reference + | +LL - fn foo(x: ＆Vec) { +LL + fn foo(x: &mut Vec) { + | + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0596`. diff --git a/tests/ui/span/span-extend-prev-while-multibyte.rs b/tests/ui/span/span-extend-prev-while-multibyte.rs new file mode 100644 index 000000000000..292699d6aa3e --- /dev/null +++ b/tests/ui/span/span-extend-prev-while-multibyte.rs @@ -0,0 +1,10 @@ +//@ build-pass +// Regression test for https://github.com/rust-lang/rust/issues/155037 +#![feature(associated_type_defaults)] + +trait Trait { + type 否 where = (); + //~^ WARNING where clause not allowed here +} + +fn main() {} diff --git a/tests/ui/span/span-extend-prev-while-multibyte.stderr b/tests/ui/span/span-extend-prev-while-multibyte.stderr new file mode 100644 index 000000000000..20232baa992b --- /dev/null +++ b/tests/ui/span/span-extend-prev-while-multibyte.stderr @@ -0,0 +1,16 @@ +warning: where clause not allowed here + --> $DIR/span-extend-prev-while-multibyte.rs:6:12 + | +LL | type 否 where = (); + | ^^^^^ + | + = note: see issue #89122 for more information + = note: `#[warn(deprecated_where_clause_location)]` on by default +help: move it to the end of the type declaration + | +LL - type 否 where = (); +LL + type 否 = () where; + | + +warning: 1 warning emitted + diff --git a/tests/ui/specialization/min_specialization/next-solver-region-resolution.rs b/tests/ui/specialization/min_specialization/next-solver-region-resolution.rs new file mode 100644 index 000000000000..d4b74802c2df --- /dev/null +++ b/tests/ui/specialization/min_specialization/next-solver-region-resolution.rs @@ -0,0 +1,26 @@ +//@ compile-flags: -Znext-solver=globally +// Regression test for https://github.com/rust-lang/rust/issues/151327 + +#![feature(min_specialization)] + +trait Foo { + type Item; +} + +trait Baz {} + +impl<'a, T> Foo for &'a T //~ ERROR not all trait items implemented, missing: `Item` +//~| ERROR the trait bound `&'a T: Foo` is not satisfied +where + Self::Item: 'a, //~ ERROR the trait bound `&'a T: Foo` is not satisfied +{ +} + +impl<'a, T> Foo for &T //~ ERROR not all trait items implemented, missing: `Item` +//~| ERROR cannot normalize `<&_ as Foo>::Item: '_` +where + Self::Item: Baz, +{ +} + +fn main() {} diff --git a/tests/ui/specialization/min_specialization/next-solver-region-resolution.stderr b/tests/ui/specialization/min_specialization/next-solver-region-resolution.stderr new file mode 100644 index 000000000000..df0e8fefaa84 --- /dev/null +++ b/tests/ui/specialization/min_specialization/next-solver-region-resolution.stderr @@ -0,0 +1,69 @@ +error[E0046]: not all trait items implemented, missing: `Item` + --> $DIR/next-solver-region-resolution.rs:12:1 + | +LL | type Item; + | --------- `Item` from trait +... +LL | / impl<'a, T> Foo for &'a T +LL | | +LL | | where +LL | | Self::Item: 'a, + | |___________________^ missing `Item` in implementation + +error[E0277]: the trait bound `&'a T: Foo` is not satisfied + --> $DIR/next-solver-region-resolution.rs:12:21 + | +LL | impl<'a, T> Foo for &'a T + | ^^^^^ the trait `Foo` is not implemented for `&'a T` + | +help: the trait `Foo` is not implemented for `&'a _` + but it is implemented for `&_` + --> $DIR/next-solver-region-resolution.rs:12:1 + | +LL | / impl<'a, T> Foo for &'a T +LL | | +LL | | where +LL | | Self::Item: 'a, + | |___________________^ + +error[E0277]: the trait bound `&'a T: Foo` is not satisfied + --> $DIR/next-solver-region-resolution.rs:15:17 + | +LL | Self::Item: 'a, + | ^^ the trait `Foo` is not implemented for `&'a T` + | +help: the trait `Foo` is not implemented for `&'a _` + but it is implemented for `&_` + --> $DIR/next-solver-region-resolution.rs:12:1 + | +LL | / impl<'a, T> Foo for &'a T +LL | | +LL | | where +LL | | Self::Item: 'a, + | |___________________^ + +error[E0046]: not all trait items implemented, missing: `Item` + --> $DIR/next-solver-region-resolution.rs:19:1 + | +LL | type Item; + | --------- `Item` from trait +... +LL | / impl<'a, T> Foo for &T +LL | | +LL | | where +LL | | Self::Item: Baz, + | |____________________^ missing `Item` in implementation + +error: cannot normalize `<&_ as Foo>::Item: '_` + --> $DIR/next-solver-region-resolution.rs:19:1 + | +LL | / impl<'a, T> Foo for &T +LL | | +LL | | where +LL | | Self::Item: Baz, + | |____________________^ + +error: aborting due to 5 previous errors + +Some errors have detailed explanations: E0046, E0277. +For more information about an error, try `rustc --explain E0046`. diff --git a/tests/ui/stability-attribute/stability-attribute-sanity-2.stderr b/tests/ui/stability-attribute/stability-attribute-sanity-2.stderr index 7beb9fd979ce..e798b6d6f6a0 100644 --- a/tests/ui/stability-attribute/stability-attribute-sanity-2.stderr +++ b/tests/ui/stability-attribute/stability-attribute-sanity-2.stderr @@ -3,18 +3,28 @@ error[E0538]: malformed `stable` attribute input | LL | #[stable(feature = "a", feature = "b", since = "1.0.0")] | ^^^^^^^^^^^^^^^^^^^^^^^^-------^^^^^^^^^^^^^^^^^^^^^^^^^ - | | | - | | found `feature` used as a key more than once - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | found `feature` used as a key more than once + | +help: must be of the form + | +LL - #[stable(feature = "a", feature = "b", since = "1.0.0")] +LL + #[stable(feature = "name", since = "version")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity-2.rs:10:1 | LL | #[stable(feature = "a", sinse = "1.0.0")] | ^^^^^^^^^^^^^^^^^^^^^^^^---------------^^ - | | | - | | valid arguments are `feature` or `since` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | valid arguments are `feature` or `since` + | +help: must be of the form + | +LL - #[stable(feature = "a", sinse = "1.0.0")] +LL + #[stable(feature = "name", since = "version")] + | error[E0545]: `issue` must be a non-zero numeric string or "none" --> $DIR/stability-attribute-sanity-2.rs:13:27 diff --git a/tests/ui/stability-attribute/stability-attribute-sanity-4.stderr b/tests/ui/stability-attribute/stability-attribute-sanity-4.stderr index 9b3f540198ce..9e82a4daa50e 100644 --- a/tests/ui/stability-attribute/stability-attribute-sanity-4.stderr +++ b/tests/ui/stability-attribute/stability-attribute-sanity-4.stderr @@ -2,37 +2,51 @@ error[E0539]: malformed `unstable` attribute input --> $DIR/stability-attribute-sanity-4.rs:8:5 | LL | #[unstable] - | ^^^^^^^^^^^ - | | - | expected this to be a list - | help: must be of the form: `#[unstable(feature = "name", reason = "...", issue = "N")]` + | ^^^^^^^^^^^ expected this to be a list + | +help: must be of the form + | +LL | #[unstable(feature = "name", reason = "...", issue = "N")] + | +++++++++++++++++++++++++++++++++++++++++++++++ error[E0539]: malformed `unstable` attribute input --> $DIR/stability-attribute-sanity-4.rs:11:5 | LL | #[unstable = "b"] | ^^^^^^^^^^^-----^ - | | | - | | expected this to be a list - | help: must be of the form: `#[unstable(feature = "name", reason = "...", issue = "N")]` + | | + | expected this to be a list + | +help: must be of the form + | +LL - #[unstable = "b"] +LL + #[unstable(feature = "name", reason = "...", issue = "N")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity-4.rs:14:5 | LL | #[stable] - | ^^^^^^^^^ - | | - | expected this to be a list - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | ^^^^^^^^^ expected this to be a list + | +help: must be of the form + | +LL | #[stable(feature = "name", since = "version")] + | +++++++++++++++++++++++++++++++++++++ error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity-4.rs:17:5 | LL | #[stable = "a"] | ^^^^^^^^^-----^ - | | | - | | expected this to be a list - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | expected this to be a list + | +help: must be of the form + | +LL - #[stable = "a"] +LL + #[stable(feature = "name", since = "version")] + | error[E0542]: missing 'since' --> $DIR/stability-attribute-sanity-4.rs:21:5 diff --git a/tests/ui/stability-attribute/stability-attribute-sanity.stderr b/tests/ui/stability-attribute/stability-attribute-sanity.stderr index 05c34484b9f8..55b318c51ab9 100644 --- a/tests/ui/stability-attribute/stability-attribute-sanity.stderr +++ b/tests/ui/stability-attribute/stability-attribute-sanity.stderr @@ -3,45 +3,70 @@ error[E0539]: malformed `stable` attribute input | LL | #[stable(feature = "a", since = "4.4.4", reason)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^------^^ - | | | - | | valid arguments are `feature` or `since` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | valid arguments are `feature` or `since` + | +help: must be of the form + | +LL - #[stable(feature = "a", since = "4.4.4", reason)] +LL + #[stable(feature = "name", since = "version")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity.rs:11:5 | LL | #[stable(feature = "a", since)] | ^^^^^^^^^^^^^^^^^^^^^^^^-----^^ - | | | - | | expected this to be of the form `since = "..."` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | expected this to be of the form `since = "..."` + | +help: must be of the form + | +LL - #[stable(feature = "a", since)] +LL + #[stable(feature = "name", since = "version")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity.rs:14:5 | LL | #[stable(feature, since = "3.3.3")] | ^^^^^^^^^-------^^^^^^^^^^^^^^^^^^^ - | | | - | | expected this to be of the form `feature = "..."` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | expected this to be of the form `feature = "..."` + | +help: must be of the form + | +LL - #[stable(feature, since = "3.3.3")] +LL + #[stable(feature = "name", since = "version")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity.rs:17:5 | LL | #[stable(feature = "a", since(b))] | ^^^^^^^^^^^^^^^^^^^^^^^^--------^^ - | | | - | | expected this to be of the form `since = "..."` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | expected this to be of the form `since = "..."` + | +help: must be of the form + | +LL - #[stable(feature = "a", since(b))] +LL + #[stable(feature = "name", since = "version")] + | error[E0539]: malformed `stable` attribute input --> $DIR/stability-attribute-sanity.rs:20:5 | LL | #[stable(feature(b), since = "3.3.3")] | ^^^^^^^^^----------^^^^^^^^^^^^^^^^^^^ - | | | - | | expected this to be of the form `feature = "..."` - | help: must be of the form: `#[stable(feature = "name", since = "version")]` + | | + | expected this to be of the form `feature = "..."` + | +help: must be of the form + | +LL - #[stable(feature(b), since = "3.3.3")] +LL + #[stable(feature = "name", since = "version")] + | error[E0546]: missing 'feature' --> $DIR/stability-attribute-sanity.rs:25:5 diff --git a/tests/ui/statics/static-ref-deref-non-const-trait.rs b/tests/ui/statics/static-ref-deref-non-const-trait.rs index 6d7b375ecb10..50952a859508 100644 --- a/tests/ui/statics/static-ref-deref-non-const-trait.rs +++ b/tests/ui/statics/static-ref-deref-non-const-trait.rs @@ -4,7 +4,7 @@ struct B; static S: &'static B = &A; -//~^ ERROR the trait bound `A: const Deref` is not satisfied +//~^ ERROR cannot perform non-const deref coercion use std::ops::Deref; diff --git a/tests/ui/statics/static-ref-deref-non-const-trait.stderr b/tests/ui/statics/static-ref-deref-non-const-trait.stderr index 88ddffecc928..a1fdca1f284e 100644 --- a/tests/ui/statics/static-ref-deref-non-const-trait.stderr +++ b/tests/ui/statics/static-ref-deref-non-const-trait.stderr @@ -1,14 +1,23 @@ -error[E0277]: the trait bound `A: const Deref` is not satisfied +error[E0015]: cannot perform non-const deref coercion on `A` in statics --> $DIR/static-ref-deref-non-const-trait.rs:6:24 | LL | static S: &'static B = &A; | ^^ | -help: make the `impl` of trait `Deref` `const` + = note: attempting to deref into `B` +note: deref defined here + --> $DIR/static-ref-deref-non-const-trait.rs:12:5 | -LL | impl const Deref for A { - | +++++ +LL | type Target = B; + | ^^^^^^^^^^^ +note: impl defined here, but it is not `const` + --> $DIR/static-ref-deref-non-const-trait.rs:11:1 + | +LL | impl Deref for A { + | ^^^^^^^^^^^^^^^^ + = note: calls in statics are limited to constant functions, tuple structs and tuple variants + = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)` error: aborting due to 1 previous error -For more information about this error, try `rustc --explain E0277`. +For more information about this error, try `rustc --explain E0015`. diff --git a/tests/ui/std/open-options-ext-compat.rs b/tests/ui/std/open-options-ext-compat.rs new file mode 100644 index 000000000000..783b1e0961cb --- /dev/null +++ b/tests/ui/std/open-options-ext-compat.rs @@ -0,0 +1,20 @@ +//@ only-windows +//@ check-pass + +// Regression test for https://github.com/rust-lang/rust/issues/153486 +// Ensures that `OpenOptionsExt` remains implementable by downstream crates +// without requiring changes when new methods are added to the standard library. + +use std::os::windows::fs::OpenOptionsExt; + +struct MockOptions; + +impl OpenOptionsExt for MockOptions { + fn access_mode(&mut self, _: u32) -> &mut Self { self } + fn share_mode(&mut self, _: u32) -> &mut Self { self } + fn custom_flags(&mut self, _: u32) -> &mut Self { self } + fn attributes(&mut self, _: u32) -> &mut Self { self } + fn security_qos_flags(&mut self, _: u32) -> &mut Self { self } +} + +fn main() {} diff --git a/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.rs b/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.rs new file mode 100644 index 000000000000..77bd286697eb --- /dev/null +++ b/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.rs @@ -0,0 +1,12 @@ +// Regression test for #154826. + +use std::rc::Rc; + +struct NonCopy; + +fn main() { + let b: NonCopy; + (b,) = *Rc::new((NonCopy,)); + //~^ ERROR cannot move out of an `Rc` + //~| HELP destructuring assignment cannot borrow from this expression; consider using a `let` binding instead +} diff --git a/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.stderr b/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.stderr new file mode 100644 index 000000000000..8022e7384f3e --- /dev/null +++ b/tests/ui/suggestions/borrow-from-overloaded-deref-assign-issue-154826.stderr @@ -0,0 +1,25 @@ +error[E0507]: cannot move out of an `Rc` + --> $DIR/borrow-from-overloaded-deref-assign-issue-154826.rs:9:12 + | +LL | (b,) = *Rc::new((NonCopy,)); + | - ^^^^^^^^^^^^^^^^^^^^ + | | + | data moved here because the place has type `NonCopy`, which does not implement the `Copy` trait + | +help: destructuring assignment cannot borrow from this expression; consider using a `let` binding instead + --> $DIR/borrow-from-overloaded-deref-assign-issue-154826.rs:9:12 + | +LL | (b,) = *Rc::new((NonCopy,)); + | ^^^^^^^^^^^^^^^^^^^^ +note: if `NonCopy` implemented `Clone`, you could clone the value + --> $DIR/borrow-from-overloaded-deref-assign-issue-154826.rs:5:1 + | +LL | struct NonCopy; + | ^^^^^^^^^^^^^^ consider implementing `Clone` for this type +... +LL | (b,) = *Rc::new((NonCopy,)); + | - you could clone this value + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0507`. diff --git a/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.rs b/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.rs new file mode 100644 index 000000000000..2d5df0ca214c --- /dev/null +++ b/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.rs @@ -0,0 +1,12 @@ +// Regression test for #154826. + +use std::sync::LazyLock; + +static V: LazyLock<(Vec,)> = LazyLock::new(|| (vec![],)); + +fn main() { + let (v,) = *V; + //~^ ERROR cannot move out of dereference of `LazyLock<(Vec,)>` + //~| HELP consider borrowing here + let _: &Vec<_> = &v; +} diff --git a/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.stderr b/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.stderr new file mode 100644 index 000000000000..2ae3cf143fc5 --- /dev/null +++ b/tests/ui/suggestions/borrow-from-overloaded-deref-issue-154826.stderr @@ -0,0 +1,16 @@ +error[E0507]: cannot move out of dereference of `LazyLock<(Vec,)>` + --> $DIR/borrow-from-overloaded-deref-issue-154826.rs:8:16 + | +LL | let (v,) = *V; + | - ^^ + | | + | data moved here because `v` has type `Vec`, which does not implement the `Copy` trait + | +help: consider borrowing here + | +LL | let (v,) = &*V; + | + + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0507`. diff --git a/tests/ui/suggestions/cow-into-owned-suggestion.rs b/tests/ui/suggestions/cow-into-owned-suggestion.rs new file mode 100644 index 000000000000..8d1019431df0 --- /dev/null +++ b/tests/ui/suggestions/cow-into-owned-suggestion.rs @@ -0,0 +1,23 @@ +//! Regression test for: https://github.com/rust-lang/rust/issues/144792 + +fn main() { + let _ = || { + let os_string = std::ffi::OsString::from("test"); + os_string.to_string_lossy().to_owned() + //~^ ERROR: cannot return value referencing local variable `os_string` [E0515] + }; + + let _ = || { + let s = "hello".to_owned(); + let cow = std::borrow::Cow::from(&s); + cow.to_owned() + //~^ ERROR: cannot return value referencing local variable `s` [E0515] + }; + + let _ = || { + let bytes = b"hello".to_owned(); + let cow = std::borrow::Cow::from(&bytes[..]); + cow.to_owned() + //~^ ERROR: cannot return value referencing local variable `bytes` [E0515] + }; +} diff --git a/tests/ui/suggestions/cow-into-owned-suggestion.stderr b/tests/ui/suggestions/cow-into-owned-suggestion.stderr new file mode 100644 index 000000000000..8d30af958913 --- /dev/null +++ b/tests/ui/suggestions/cow-into-owned-suggestion.stderr @@ -0,0 +1,43 @@ +error[E0515]: cannot return value referencing local variable `os_string` + --> $DIR/cow-into-owned-suggestion.rs:6:9 + | +LL | os_string.to_string_lossy().to_owned() + | ---------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | | + | returns a value referencing data owned by the current function + | `os_string` is borrowed here + | +help: try using `.into_owned()` if you meant to convert a `Cow<'_, T>` to an owned `T` + | +LL | os_string.to_string_lossy().into_owned() + | ++ + +error[E0515]: cannot return value referencing local variable `s` + --> $DIR/cow-into-owned-suggestion.rs:13:9 + | +LL | let cow = std::borrow::Cow::from(&s); + | -- `s` is borrowed here +LL | cow.to_owned() + | ^^^^^^^^^^^^^^ returns a value referencing data owned by the current function + | +help: try using `.into_owned()` if you meant to convert a `Cow<'_, T>` to an owned `T` + | +LL | cow.into_owned() + | ++ + +error[E0515]: cannot return value referencing local variable `bytes` + --> $DIR/cow-into-owned-suggestion.rs:20:9 + | +LL | let cow = std::borrow::Cow::from(&bytes[..]); + | ----- `bytes` is borrowed here +LL | cow.to_owned() + | ^^^^^^^^^^^^^^ returns a value referencing data owned by the current function + | +help: try using `.into_owned()` if you meant to convert a `Cow<'_, T>` to an owned `T` + | +LL | cow.into_owned() + | ++ + +error: aborting due to 3 previous errors + +For more information about this error, try `rustc --explain E0515`. diff --git a/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.rs b/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.rs index cec66214978b..85609b073316 100644 --- a/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.rs +++ b/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.rs @@ -1,7 +1,9 @@ //@ aux-build:hidden-child.rs -// FIXME(compiler-errors): This currently suggests the wrong thing. -// UI test exists to track the problem. +// Regression test for #153477. +// When a re-export is #[doc(hidden)], diagnostics should prefer +// the canonical path (e.g. `Some`) over the hidden re-export path +// (e.g. `hidden_child::__private::Some`). extern crate hidden_child; diff --git a/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.stderr b/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.stderr index 00d001f6bee2..c0abb4f4ee26 100644 --- a/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.stderr +++ b/tests/ui/suggestions/dont-suggest-doc-hidden-variant-for-enum/hidden-child.stderr @@ -1,5 +1,5 @@ error[E0308]: mismatched types - --> $DIR/hidden-child.rs:9:26 + --> $DIR/hidden-child.rs:11:26 | LL | let x: Option = 1i32; | ----------- ^^^^ expected `Option`, found `i32` @@ -8,10 +8,10 @@ LL | let x: Option = 1i32; | = note: expected enum `Option` found type `i32` -help: try wrapping the expression in `hidden_child::__private::Some` +help: try wrapping the expression in `Some` | -LL | let x: Option = hidden_child::__private::Some(1i32); - | ++++++++++++++++++++++++++++++ + +LL | let x: Option = Some(1i32); + | +++++ + error: aborting due to 1 previous error diff --git a/tests/ui/suggestions/issue-102892.stderr b/tests/ui/suggestions/issue-102892.stderr index 38f19b332188..ed7a88c6422e 100644 --- a/tests/ui/suggestions/issue-102892.stderr +++ b/tests/ui/suggestions/issue-102892.stderr @@ -61,12 +61,12 @@ LL | let (a, b) = **arc; // suggests putting `&**arc` here; with that, fixed | | ...and here | data moved here | +help: destructuring assignment cannot borrow from this expression; consider using a `let` binding instead + --> $DIR/issue-102892.rs:11:18 + | +LL | let (a, b) = **arc; // suggests putting `&**arc` here; with that, fixed! + | ^^^^^ = note: move occurs because these variables have types that don't implement the `Copy` trait -help: consider removing the dereference here - | -LL - let (a, b) = **arc; // suggests putting `&**arc` here; with that, fixed! -LL + let (a, b) = *arc; // suggests putting `&**arc` here; with that, fixed! - | error: aborting due to 4 previous errors diff --git a/tests/ui/suggestions/suggest-mut-method-for-loop-closure.stderr b/tests/ui/suggestions/suggest-mut-method-for-loop-closure.stderr index 5c0bbe24ec92..8a1e57e11ddc 100644 --- a/tests/ui/suggestions/suggest-mut-method-for-loop-closure.stderr +++ b/tests/ui/suggestions/suggest-mut-method-for-loop-closure.stderr @@ -2,13 +2,15 @@ error[E0594]: cannot assign to `t.v`, which is behind a `&` reference --> $DIR/suggest-mut-method-for-loop-closure.rs:15:13 | LL | for mut t in buzz.values() { - | ------------- - | | | - | | help: use mutable method: `values_mut()` - | this iterator yields `&` references + | ------------- this iterator yields `&` references ... LL | t.v += 1; | ^^^^^^^^ `t` is a `&` reference, so it cannot be written to + | +help: use mutable method + | +LL | for mut t in buzz.values_mut() { + | ++++ error: aborting due to 1 previous error diff --git a/tests/ui/suggestions/suggest-mut-method-for-loop-hashmap.stderr b/tests/ui/suggestions/suggest-mut-method-for-loop-hashmap.stderr index 8e4412806387..a8f596ac8c9a 100644 --- a/tests/ui/suggestions/suggest-mut-method-for-loop-hashmap.stderr +++ b/tests/ui/suggestions/suggest-mut-method-for-loop-hashmap.stderr @@ -2,13 +2,15 @@ error[E0594]: cannot assign to `v.v`, which is behind a `&` reference --> $DIR/suggest-mut-method-for-loop-hashmap.rs:17:9 | LL | for (_k, v) in map.iter() { - | ---------- - | | | - | | help: use mutable method: `iter_mut()` - | this iterator yields `&` references + | ---------- this iterator yields `&` references ... LL | v.v += 1; | ^^^^^^^^ `v` is a `&` reference, so it cannot be written to + | +help: use mutable method + | +LL | for (_k, v) in map.iter_mut() { + | ++++ error: aborting due to 1 previous error diff --git a/tests/ui/suggestions/suggest-mut-method-for-loop.stderr b/tests/ui/suggestions/suggest-mut-method-for-loop.stderr index 26764ebc4a45..7fc224636d36 100644 --- a/tests/ui/suggestions/suggest-mut-method-for-loop.stderr +++ b/tests/ui/suggestions/suggest-mut-method-for-loop.stderr @@ -2,13 +2,15 @@ error[E0594]: cannot assign to `t.v`, which is behind a `&` reference --> $DIR/suggest-mut-method-for-loop.rs:14:9 | LL | for mut t in buzz.values() { - | ------------- - | | | - | | help: use mutable method: `values_mut()` - | this iterator yields `&` references + | ------------- this iterator yields `&` references ... LL | t.v += 1; | ^^^^^^^^ `t` is a `&` reference, so it cannot be written to + | +help: use mutable method + | +LL | for mut t in buzz.values_mut() { + | ++++ error: aborting due to 1 previous error diff --git a/tests/ui/symbol-names/basic.legacy.stderr b/tests/ui/symbol-names/basic.legacy.stderr index a028f4331725..8309b8f957a7 100644 --- a/tests/ui/symbol-names/basic.legacy.stderr +++ b/tests/ui/symbol-names/basic.legacy.stderr @@ -1,26 +1,26 @@ -error: symbol-name(_ZN5basic4main17h1dddcfd03744167fE) +error: symbol-name(_ZN5basic4main17h947b7a9ed2b2bf56E) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ -error: demangling(basic::main::h1dddcfd03744167f) +error: demangling(basic::main::h947b7a9ed2b2bf56) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(basic::main) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(main) --> $DIR/basic.rs:15:1 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 4 previous errors diff --git a/tests/ui/symbol-names/basic.rs b/tests/ui/symbol-names/basic.rs index 839dda2b3a3b..d4c23f988384 100644 --- a/tests/ui/symbol-names/basic.rs +++ b/tests/ui/symbol-names/basic.rs @@ -5,14 +5,14 @@ #![feature(rustc_attrs)] -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN5basic4main //[legacy]~| ERROR demangling(basic::main //[legacy]~| ERROR demangling-alt(basic::main) //[v0]~^^^^ ERROR symbol-name(_RNv //[v0]~| ERROR demangling(basic[ //[v0]~| ERROR demangling-alt(basic::main) -#[rustc_def_path] +#[rustc_dump_def_path] //[legacy]~^ ERROR def-path(main) //[v0]~^^ ERROR def-path(main) fn main() { diff --git a/tests/ui/symbol-names/basic.v0.stderr b/tests/ui/symbol-names/basic.v0.stderr index 17c6d0ce704c..6a9da17eebe0 100644 --- a/tests/ui/symbol-names/basic.v0.stderr +++ b/tests/ui/symbol-names/basic.v0.stderr @@ -1,26 +1,26 @@ error: symbol-name(_RNvCsCRATE_HASH_5basic4main) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(basic[a90d658f4748b9d1]::main) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(basic::main) --> $DIR/basic.rs:8:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(main) --> $DIR/basic.rs:15:1 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 4 previous errors diff --git a/tests/ui/symbol-names/const-generics-demangling.legacy.stderr b/tests/ui/symbol-names/const-generics-demangling.legacy.stderr index bebbb7aac981..a2331da13c41 100644 --- a/tests/ui/symbol-names/const-generics-demangling.legacy.stderr +++ b/tests/ui/symbol-names/const-generics-demangling.legacy.stderr @@ -1,74 +1,74 @@ error: symbol-name(_ZN1c21Unsigned$LT$11_u8$GT$1f17h[HASH]E) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(c::Unsigned<11_u8>::f::h[HASH]) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(c::Unsigned<11_u8>::f) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1c22Signed$LT$.152_i16$GT$1f17h[HASH]E) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(c::Signed<.152_i16>::f::h[HASH]) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(c::Signed<.152_i16>::f) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1c13Bool$LT$_$GT$1f17h[HASH]E) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(c::Bool<_>::f::h[HASH]) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(c::Bool<_>::f) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1c13Char$LT$_$GT$1f17h[HASH]E) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(c::Char<_>::f::h[HASH]) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(c::Char<_>::f) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 12 previous errors diff --git a/tests/ui/symbol-names/const-generics-demangling.rs b/tests/ui/symbol-names/const-generics-demangling.rs index 9c078d4192a9..e32ab180fab2 100644 --- a/tests/ui/symbol-names/const-generics-demangling.rs +++ b/tests/ui/symbol-names/const-generics-demangling.rs @@ -10,7 +10,7 @@ pub struct Unsigned; impl Unsigned<11> { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name(_RNvMCs //[v0]~| ERROR demangling(>::f) @@ -23,7 +23,7 @@ fn f() {} pub struct Signed; impl Signed<-152> { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name(_RNvMs_Cs //[v0]~| ERROR demangling(>::f) @@ -36,7 +36,7 @@ fn f() {} pub struct Bool; impl Bool { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name(_RNvMs0_Cs //[v0]~| ERROR demangling(>::f) @@ -49,7 +49,7 @@ fn f() {} pub struct Char; impl Char<'∂'> { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name(_RNvMs1_Cs //[v0]~| ERROR demangling(>::f) diff --git a/tests/ui/symbol-names/const-generics-demangling.v0.stderr b/tests/ui/symbol-names/const-generics-demangling.v0.stderr index 7238a849332a..25fe5873389e 100644 --- a/tests/ui/symbol-names/const-generics-demangling.v0.stderr +++ b/tests/ui/symbol-names/const-generics-demangling.v0.stderr @@ -1,74 +1,74 @@ error: symbol-name(_RNvMCsCRATE_HASH_1cINtB_8UnsignedKhb_E1f) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>::f) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>::f) --> $DIR/const-generics-demangling.rs:13:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvMs_CsCRATE_HASH_1cINtB_6SignedKsn98_E1f) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>::f) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>::f) --> $DIR/const-generics-demangling.rs:26:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvMs0_CsCRATE_HASH_1cINtB_4BoolKb1_E1f) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>::f) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>::f) --> $DIR/const-generics-demangling.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvMs1_CsCRATE_HASH_1cINtB_4CharKc2202_E1f) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>::f) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>::f) --> $DIR/const-generics-demangling.rs:52:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 12 previous errors diff --git a/tests/ui/symbol-names/const-generics-str-demangling.rs b/tests/ui/symbol-names/const-generics-str-demangling.rs index 94c3b4c44488..90a79fd5bf7d 100644 --- a/tests/ui/symbol-names/const-generics-str-demangling.rs +++ b/tests/ui/symbol-names/const-generics-str-demangling.rs @@ -6,37 +6,37 @@ pub struct Str; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) impl Str<"abc"> {} -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) impl Str<"'"> {} -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) impl Str<"\t\n"> {} -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) impl Str<"∂ü"> {} -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) impl Str<"საჭმელად_გემრიელი_სადილი"> {} -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) diff --git a/tests/ui/symbol-names/const-generics-str-demangling.stderr b/tests/ui/symbol-names/const-generics-str-demangling.stderr index 06d3cdda2f83..09c3f7ca743f 100644 --- a/tests/ui/symbol-names/const-generics-str-demangling.stderr +++ b/tests/ui/symbol-names/const-generics-str-demangling.stderr @@ -1,110 +1,110 @@ error: symbol-name(_RMCsCRATE_HASH_1cINtB_3StrKRe616263_E) --> $DIR/const-generics-str-demangling.rs:9:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:9:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:9:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs_CsCRATE_HASH_1cINtB_3StrKRe27_E) --> $DIR/const-generics-str-demangling.rs:15:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:15:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:15:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs0_CsCRATE_HASH_1cINtB_3StrKRe090a_E) --> $DIR/const-generics-str-demangling.rs:21:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:21:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:21:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs1_CsCRATE_HASH_1cINtB_3StrKRee28882c3bc_E) --> $DIR/const-generics-str-demangling.rs:27:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:27:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:27:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs2_CsCRATE_HASH_1cINtB_3StrKRee183a1e18390e183ade1839be18394e1839ae18390e183935fe18392e18394e1839be183a0e18398e18394e1839ae183985fe183a1e18390e18393e18398e1839ae18398_E) --> $DIR/const-generics-str-demangling.rs:33:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:33:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:33:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs3_CsCRATE_HASH_1cINtB_3StrKRef09f908af09fa688f09fa686f09f90ae20c2a720f09f90b6f09f9192e29895f09f94a520c2a720f09fa7a1f09f929bf09f929af09f9299f09f929c_E) --> $DIR/const-generics-str-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-str-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-str-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 18 previous errors diff --git a/tests/ui/symbol-names/const-generics-structural-demangling.rs b/tests/ui/symbol-names/const-generics-structural-demangling.rs index 0b4af61f9910..a9a11d0ea8a4 100644 --- a/tests/ui/symbol-names/const-generics-structural-demangling.rs +++ b/tests/ui/symbol-names/const-generics-structural-demangling.rs @@ -10,7 +10,7 @@ pub struct RefByte; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) @@ -20,7 +20,7 @@ impl RefByte<{ &123 }> {} // but that is currently not allowed in const generics. pub struct RefZst; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) @@ -28,7 +28,7 @@ impl RefZst<{ &[] }> {} pub struct Array3Bytes; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) @@ -36,7 +36,7 @@ impl Array3Bytes<{ [1, 2, 3] }> {} pub struct TupleByteBool; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) @@ -52,7 +52,7 @@ pub enum MyOption { // HACK(eddyb) the full mangling is only in `.stderr` because we can normalize // the `core` disambiguator hash away there, but not here. -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(::None}>>) @@ -60,7 +60,7 @@ impl OptionUsize<{ MyOption::None }> {} // HACK(eddyb) the full mangling is only in `.stderr` because we can normalize // the `core` disambiguator hash away there, but not here. -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(::Some(0)}>>) @@ -74,7 +74,7 @@ pub struct Foo { } pub struct Foo_; -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) @@ -90,7 +90,7 @@ pub struct Bar { } pub struct Bar_; - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //~^ ERROR symbol-name //~| ERROR demangling //~| ERROR demangling-alt(>) diff --git a/tests/ui/symbol-names/const-generics-structural-demangling.stderr b/tests/ui/symbol-names/const-generics-structural-demangling.stderr index 270c126e3f55..3ec255b3e235 100644 --- a/tests/ui/symbol-names/const-generics-structural-demangling.stderr +++ b/tests/ui/symbol-names/const-generics-structural-demangling.stderr @@ -1,134 +1,134 @@ error: symbol-name(_RMCsCRATE_HASH_1cINtB_7RefByteKRh7b_E) --> $DIR/const-generics-structural-demangling.rs:13:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:13:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:13:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs_CsCRATE_HASH_1cINtB_6RefZstKRAEE) --> $DIR/const-generics-structural-demangling.rs:23:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:23:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:23:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs0_CsCRATE_HASH_1cINtB_11Array3BytesKAh1_h2_h3_EE) --> $DIR/const-generics-structural-demangling.rs:31:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:31:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:31:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs1_CsCRATE_HASH_1cINtB_13TupleByteBoolKTh1_b0_EE) --> $DIR/const-generics-structural-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:39:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs2_CsCRATE_HASH_1cINtB_11OptionUsizeKVNtINtB_8MyOptionjE4NoneUE) --> $DIR/const-generics-structural-demangling.rs:55:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(::None}>>) --> $DIR/const-generics-structural-demangling.rs:55:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(::None}>>) --> $DIR/const-generics-structural-demangling.rs:55:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs3_CsCRATE_HASH_1cINtB_11OptionUsizeKVNtINtB_8MyOptionjE4SomeTj0_EE) --> $DIR/const-generics-structural-demangling.rs:63:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(::Some(0usize)}>>) --> $DIR/const-generics-structural-demangling.rs:63:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(::Some(0)}>>) --> $DIR/const-generics-structural-demangling.rs:63:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs4_CsCRATE_HASH_1cINtB_4Foo_KVNtB_3FooS1sRe616263_2chc78_5sliceRAh1_h2_h3_EEE) --> $DIR/const-generics-structural-demangling.rs:77:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:77:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:77:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsd_CsCRATE_HASH_1cINtB_4Bar_KVNtB_3BarS1xh7b_s_1xt1000_EE) --> $DIR/const-generics-structural-demangling.rs:93:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ ... LL | duplicate_field_name_test!(x); | ----------------------------- in this macro invocation @@ -138,8 +138,8 @@ LL | duplicate_field_name_test!(x); error: demangling(>) --> $DIR/const-generics-structural-demangling.rs:93:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ ... LL | duplicate_field_name_test!(x); | ----------------------------- in this macro invocation @@ -149,8 +149,8 @@ LL | duplicate_field_name_test!(x); error: demangling-alt(>) --> $DIR/const-generics-structural-demangling.rs:93:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ ... LL | duplicate_field_name_test!(x); | ----------------------------- in this macro invocation diff --git a/tests/ui/symbol-names/const-in-global-asm.rs b/tests/ui/symbol-names/const-in-global-asm.rs index 16aa15d9a299..52c345f09bb7 100644 --- a/tests/ui/symbol-names/const-in-global-asm.rs +++ b/tests/ui/symbol-names/const-in-global-asm.rs @@ -7,8 +7,8 @@ // Test that a symbol in a `global_asm` namespace doesn't cause an ICE during v0 symbol mangling // due to a lack of missing namespace character for `global_asm`. // -// FIXME: Can't use `#[rustc_symbol_name]` on the `foo` call to check its symbol, so just checking -// the test compiles. +// FIXME: Can't use `#[rustc_dump_symbol_name]` on the `foo` call to check its symbol, +// so just checking the test compiles. fn foo() {} diff --git a/tests/ui/symbol-names/foreign-types.rs b/tests/ui/symbol-names/foreign-types.rs index b863e8c17594..b7851a06ed06 100644 --- a/tests/ui/symbol-names/foreign-types.rs +++ b/tests/ui/symbol-names/foreign-types.rs @@ -13,7 +13,7 @@ struct Check(T); -#[rustc_symbol_name] +#[rustc_dump_symbol_name] //~^ ERROR symbol-name(_RMCs //~| ERROR demangling(>) diff --git a/tests/ui/symbol-names/foreign-types.stderr b/tests/ui/symbol-names/foreign-types.stderr index 4640ceae8116..b0af84801795 100644 --- a/tests/ui/symbol-names/foreign-types.stderr +++ b/tests/ui/symbol-names/foreign-types.stderr @@ -1,20 +1,20 @@ error: symbol-name(_RMCsCRATE_HASH_13foreign_typesINtB_5CheckNtB_11ForeignTypeE) --> $DIR/foreign-types.rs:16:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/foreign-types.rs:16:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/foreign-types.rs:16:1 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 3 previous errors diff --git a/tests/ui/symbol-names/impl1.legacy.stderr b/tests/ui/symbol-names/impl1.legacy.stderr index 3d438df92b85..87a2837e0192 100644 --- a/tests/ui/symbol-names/impl1.legacy.stderr +++ b/tests/ui/symbol-names/impl1.legacy.stderr @@ -1,74 +1,74 @@ error: symbol-name(_ZN5impl13foo3Foo3bar17) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(impl1::foo::Foo::bar::) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(impl1::foo::Foo::bar) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(foo::Foo::bar) --> $DIR/impl1.rs:21:9 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN5impl13bar33_$LT$impl$u20$impl1..foo..Foo$GT$3baz17) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(impl1::bar::::baz::) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(impl1::bar::::baz) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(bar::::baz) --> $DIR/impl1.rs:39:9 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN209_$LT$$u5b$$RF$dyn$u20$impl1..Foo$u2b$Assoc$u20$$u3d$$u20$extern$u20$$u22$C$u22$$u20$fn$LP$$RF$u8$C$$u20$...$RP$$u2b$impl1..AutoTrait$u3b$$u20$3$u5d$$u20$as$u20$impl1..main..$u7b$$u7b$closure$u7d$$u7d$..Bar$GT$6method17) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(<[&dyn impl1::Foo+Assoc = extern "C" fn(&u8, ::.)+impl1::AutoTrait; 3] as impl1::main::{{closure}}::Bar>::method::) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(<[&dyn impl1::Foo+Assoc = extern "C" fn(&u8, ::.)+impl1::AutoTrait; 3] as impl1::main::{{closure}}::Bar>::method) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(<[&dyn Foo extern "C" fn(&'a u8, ...)> + AutoTrait; 3] as main::{closure#1}::Bar>::method) --> $DIR/impl1.rs:69:13 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 12 previous errors diff --git a/tests/ui/symbol-names/impl1.rs b/tests/ui/symbol-names/impl1.rs index 0fdf56454799..5902df54b486 100644 --- a/tests/ui/symbol-names/impl1.rs +++ b/tests/ui/symbol-names/impl1.rs @@ -11,14 +11,14 @@ mod foo { pub struct Foo { x: u32 } impl Foo { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN5impl13foo3Foo3bar //[legacy]~| ERROR demangling(impl1::foo::Foo::bar //[legacy]~| ERROR demangling-alt(impl1::foo::Foo::bar) //[v0]~^^^^ ERROR symbol-name(_RNvMNtCs //[v0]~| ERROR demangling(::bar) - #[rustc_def_path] + #[rustc_dump_def_path] //[legacy]~^ ERROR def-path(foo::Foo::bar) //[v0]~^^ ERROR def-path(foo::Foo::bar) fn bar() { } @@ -29,14 +29,14 @@ mod bar { use crate::foo::Foo; impl Foo { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN5impl13bar33_$LT$impl$u20$impl1..foo..Foo$GT$3baz //[legacy]~| ERROR demangling(impl1::bar::::baz //[legacy]~| ERROR demangling-alt(impl1::bar::::baz) //[v0]~^^^^ ERROR symbol-name(_RNvMNtCs //[v0]~| ERROR demangling(::baz) - #[rustc_def_path] + #[rustc_dump_def_path] //[legacy]~^ ERROR def-path(bar::::baz) //[v0]~^^ ERROR def-path(bar::::baz) fn baz() { } @@ -59,14 +59,14 @@ fn method(&self) {} // Test type mangling, by putting them in an `impl` header. impl Bar for [&'_ (dyn Foo + AutoTrait); 3] { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN209_$LT$$u5b$$RF$dyn$u20$impl1..Foo$u2b$Assoc$u20$$u3d$$u20$extern$u20$$u22$C$u22$$u20$fn$LP$$RF$u8$C$$u20$...$RP$$u2b$impl1..AutoTrait$u3b$$u20$3$u5d$$u20$as$u20$impl1..main..$u7b$$u7b$closure$u7d$$u7d$..Bar$GT$6method //[legacy]~| ERROR demangling(<[&dyn impl1::Foo+Assoc = extern "C" fn(&u8, ::.)+impl1::AutoTrait; 3] as impl1::main::{{closure}}::Bar>::method //[legacy]~| ERROR demangling-alt(<[&dyn impl1::Foo+Assoc = extern "C" fn(&u8, ::.)+impl1::AutoTrait; 3] as impl1::main::{{closure}}::Bar>::method) //[v0]~^^^^ ERROR symbol-name(_RNvXNCNvCs //[v0]~| ERROR demangling(<[&dyn //[v0]~| ERROR demangling-alt(<[&dyn impl1::Foo extern "C" fn(&'a u8, ...)> + impl1::AutoTrait; 3] as impl1::main::{closure#1}::Bar>::method) - #[rustc_def_path] + #[rustc_dump_def_path] //[legacy]~^ ERROR def-path(<[&dyn Foo extern "C" fn(&'a u8, ...)> + AutoTrait; 3] as main::{closure#1}::Bar>::method) //[v0]~^^ ERROR def-path(<[&dyn Foo extern "C" fn(&'a u8, ...)> + AutoTrait; 3] as main::{closure#1}::Bar>::method) fn method(&self) {} diff --git a/tests/ui/symbol-names/impl1.v0.stderr b/tests/ui/symbol-names/impl1.v0.stderr index a7cc5fc8ed21..77319825b177 100644 --- a/tests/ui/symbol-names/impl1.v0.stderr +++ b/tests/ui/symbol-names/impl1.v0.stderr @@ -1,74 +1,74 @@ error: symbol-name(_RNvMNtCsCRATE_HASH_5impl13fooNtB_3Foo3bar) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(::bar) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(::bar) --> $DIR/impl1.rs:14:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(foo::Foo::bar) --> $DIR/impl1.rs:21:9 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvMNtCsCRATE_HASH_5impl13barNtNtB_3foo3Foo3baz) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(::baz) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(::baz) --> $DIR/impl1.rs:32:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(bar::::baz) --> $DIR/impl1.rs:39:9 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvXNCNvCsCRATE_HASH_5impl14mains_0ARDNtB_3Foop5AssocFG_KCRL0_hvEuNtB_9AutoTraitEL_j3_NtB_3Bar6method) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(<[&dyn impl1[d5591eb39db23cbb]::Foo extern "C" fn(&'a u8, ...)> + impl1[d5591eb39db23cbb]::AutoTrait; 3usize] as impl1[d5591eb39db23cbb]::main::{closure#1}::Bar>::method) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(<[&dyn impl1::Foo extern "C" fn(&'a u8, ...)> + impl1::AutoTrait; 3] as impl1::main::{closure#1}::Bar>::method) --> $DIR/impl1.rs:62:13 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: def-path(<[&dyn Foo extern "C" fn(&'a u8, ...)> + AutoTrait; 3] as main::{closure#1}::Bar>::method) --> $DIR/impl1.rs:69:13 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 12 previous errors diff --git a/tests/ui/symbol-names/impl2.rs b/tests/ui/symbol-names/impl2.rs index 8d103fab43ba..05e212cf5d12 100644 --- a/tests/ui/symbol-names/impl2.rs +++ b/tests/ui/symbol-names/impl2.rs @@ -8,7 +8,7 @@ trait Foo { } impl Foo for [u8; 1 + 2] { - #[rustc_def_path] //~ ERROR def-path(<[u8; 1 + 2] as Foo>::baz) + #[rustc_dump_def_path] //~ ERROR def-path(<[u8; 1 + 2] as Foo>::baz) fn baz() {} } diff --git a/tests/ui/symbol-names/impl2.stderr b/tests/ui/symbol-names/impl2.stderr index 36f080b60836..69bdc4abb0b5 100644 --- a/tests/ui/symbol-names/impl2.stderr +++ b/tests/ui/symbol-names/impl2.stderr @@ -1,8 +1,8 @@ error: def-path(<[u8; 1 + 2] as Foo>::baz) --> $DIR/impl2.rs:11:5 | -LL | #[rustc_def_path] - | ^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_def_path] + | ^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 1 previous error diff --git a/tests/ui/symbol-names/issue-60925.legacy.stderr b/tests/ui/symbol-names/issue-60925.legacy.stderr index 14cbd877d9f8..359bafdff469 100644 --- a/tests/ui/symbol-names/issue-60925.legacy.stderr +++ b/tests/ui/symbol-names/issue-60925.legacy.stderr @@ -1,20 +1,20 @@ -error: symbol-name(_ZN11issue_609253foo37Foo$LT$issue_60925..llv$u6d$..Foo$GT$3foo17h4b3099ec5dc5d306E) +error: symbol-name(_ZN11issue_609253foo37Foo$LT$issue_60925..llv$u6d$..Foo$GT$3foo17hba5ac046b858f549E) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ -error: demangling(issue_60925::foo::Foo::foo::h4b3099ec5dc5d306) +error: demangling(issue_60925::foo::Foo::foo::hba5ac046b858f549) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(issue_60925::foo::Foo::foo) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 3 previous errors diff --git a/tests/ui/symbol-names/issue-60925.rs b/tests/ui/symbol-names/issue-60925.rs index 24969fc66419..76552d88880e 100644 --- a/tests/ui/symbol-names/issue-60925.rs +++ b/tests/ui/symbol-names/issue-60925.rs @@ -18,7 +18,7 @@ mod foo { pub(crate) struct Foo(T); impl Foo { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN11issue_609253foo37Foo$LT$issue_60925..llv$u6d$..Foo$GT$3foo //[legacy]~| ERROR demangling(issue_60925::foo::Foo::foo //[legacy]~| ERROR demangling-alt(issue_60925::foo::Foo::foo) diff --git a/tests/ui/symbol-names/issue-60925.v0.stderr b/tests/ui/symbol-names/issue-60925.v0.stderr index 77449becc84d..587ee1090ade 100644 --- a/tests/ui/symbol-names/issue-60925.v0.stderr +++ b/tests/ui/symbol-names/issue-60925.v0.stderr @@ -1,20 +1,20 @@ error: symbol-name(_RNvMNtCsCRATE_HASH_11issue_609253fooINtB_3FooNtNtB_4llvm3FooE3foo) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>::foo) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>::foo) --> $DIR/issue-60925.rs:21:9 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 3 previous errors diff --git a/tests/ui/symbol-names/issue-75326.legacy.stderr b/tests/ui/symbol-names/issue-75326.legacy.stderr index aadc0cf43a21..c4b248427c7e 100644 --- a/tests/ui/symbol-names/issue-75326.legacy.stderr +++ b/tests/ui/symbol-names/issue-75326.legacy.stderr @@ -1,20 +1,20 @@ error: symbol-name(_ZN72_$LT$issue_75326..Foo$LT$I$C$E$GT$$u20$as$u20$issue_75326..Iterator2$GT$4next17SYMBOL_HASH) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling( as issue_75326::Iterator2>::next::SYMBOL_HASH) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt( as issue_75326::Iterator2>::next) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 3 previous errors diff --git a/tests/ui/symbol-names/issue-75326.rs b/tests/ui/symbol-names/issue-75326.rs index c60b872b0a23..7810483f5f39 100644 --- a/tests/ui/symbol-names/issue-75326.rs +++ b/tests/ui/symbol-names/issue-75326.rs @@ -38,7 +38,7 @@ impl Iterator2 for Foo { type Item = T; - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy]~^ ERROR symbol-name(_ZN72_$LT$issue_75326..Foo$LT$I$C$E$GT$$u20$as$u20$issue_75326..Iterator2$GT$4next //[legacy]~| ERROR demangling( as issue_75326::Iterator2>::next //[legacy]~| ERROR demangling-alt( as issue_75326::Iterator2>::next) diff --git a/tests/ui/symbol-names/issue-75326.v0.stderr b/tests/ui/symbol-names/issue-75326.v0.stderr index fb742f5e4490..d07a85730a2b 100644 --- a/tests/ui/symbol-names/issue-75326.v0.stderr +++ b/tests/ui/symbol-names/issue-75326.v0.stderr @@ -1,20 +1,20 @@ error: symbol-name(_RNvXINICsCRATE_HASH_11issue_75326s_0pppEINtB_3FooppENtB_9Iterator24nextB_) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling( as issue_75326[189ebc60e18860d7]::Iterator2>::next) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt( as issue_75326::Iterator2>::next) --> $DIR/issue-75326.rs:41:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 3 previous errors diff --git a/tests/ui/symbol-names/trait-objects.rs b/tests/ui/symbol-names/trait-objects.rs index da48190285da..9f9178c6b074 100644 --- a/tests/ui/symbol-names/trait-objects.rs +++ b/tests/ui/symbol-names/trait-objects.rs @@ -12,7 +12,7 @@ fn method(&self) {} } impl Bar for &dyn FnMut(&u8) { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name //[v0]~| ERROR demangling //[v0]~| ERROR demangling-alt @@ -24,7 +24,7 @@ fn method(&self) {} } impl Foo for &(dyn FnMut(&u8) + for<'b> Send) { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name //[v0]~| ERROR demangling //[v0]~| ERROR demangling-alt @@ -36,7 +36,7 @@ fn method(&self) {} } impl Baz for &(dyn for<'b> Send + FnMut(&u8)) { - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[v0]~^ ERROR symbol-name //[v0]~| ERROR demangling //[v0]~| ERROR demangling-alt diff --git a/tests/ui/symbol-names/trait-objects.v0.stderr b/tests/ui/symbol-names/trait-objects.v0.stderr index 84f2bce66be1..b0cd9c9e7e3f 100644 --- a/tests/ui/symbol-names/trait-objects.v0.stderr +++ b/tests/ui/symbol-names/trait-objects.v0.stderr @@ -1,56 +1,56 @@ error: symbol-name(_RNvXCsCRATE_HASH_13trait_objectsRDG_INtNtNtCsCRATE_HASH_4core3ops8function5FnMutTRL0_hEEp6OutputuEL_NtB_3Bar6method) --> $DIR/trait-objects.rs:15:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(<&dyn for<'a> core[HASH]::ops::function::FnMut<(&'a u8,), Output = ()> as trait_objects[3c073c57f94bedc2]::Bar>::method) --> $DIR/trait-objects.rs:15:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(<&dyn for<'a> core::ops::function::FnMut<(&'a u8,), Output = ()> as trait_objects::Bar>::method) --> $DIR/trait-objects.rs:15:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvXs_CsCRATE_HASH_13trait_objectsRDG_INtNtNtCsCRATE_HASH_4core3ops8function5FnMutTRL0_hEEp6OutputuNtNtB_6marker4SendEL_NtB_3Foo6method) --> $DIR/trait-objects.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(<&dyn for<'a> core[HASH]::ops::function::FnMut<(&'a u8,), Output = ()> + core[HASH]::marker::Send as trait_objects[3c073c57f94bedc2]::Foo>::method) --> $DIR/trait-objects.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(<&dyn for<'a> core::ops::function::FnMut<(&'a u8,), Output = ()> + core::marker::Send as trait_objects::Foo>::method) --> $DIR/trait-objects.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RNvXs0_CsCRATE_HASH_13trait_objectsRDG_INtNtNtCsCRATE_HASH_4core3ops8function5FnMutTRL0_hEEp6OutputuNtNtB_6marker4SendEL_NtB_3Baz6method) --> $DIR/trait-objects.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(<&dyn for<'a> core[HASH]::ops::function::FnMut<(&'a u8,), Output = ()> + core[HASH]::marker::Send as trait_objects[3c073c57f94bedc2]::Baz>::method) --> $DIR/trait-objects.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(<&dyn for<'a> core::ops::function::FnMut<(&'a u8,), Output = ()> + core::marker::Send as trait_objects::Baz>::method) --> $DIR/trait-objects.rs:39:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 9 previous errors diff --git a/tests/ui/symbol-names/types.legacy.stderr b/tests/ui/symbol-names/types.legacy.stderr index c368b3186098..53f0c1e57666 100644 --- a/tests/ui/symbol-names/types.legacy.stderr +++ b/tests/ui/symbol-names/types.legacy.stderr @@ -1,524 +1,524 @@ error: symbol-name(_ZN1a1b16Type$LT$bool$GT$17h[HASH]E) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b16Type$LT$char$GT$17h[HASH]E) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b14Type$LT$i8$GT$17h[HASH]E) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i16$GT$17h[HASH]E) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i32$GT$17h[HASH]E) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i64$GT$17h[HASH]E) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b14Type$LT$u8$GT$17h[HASH]E) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u16$GT$17h[HASH]E) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u32$GT$17h[HASH]E) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u64$GT$17h[HASH]E) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f16$GT$17h[HASH]E) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f32$GT$17h[HASH]E) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f64$GT$17h[HASH]E) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b16Type$LT$f128$GT$17h[HASH]E) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$str$GT$17h[HASH]E) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b17Type$LT$$u21$$GT$17h[HASH]E) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b20Type$LT$$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<()>::h[HASH]) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<()>) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b25Type$LT$$LP$u8$C$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,)>::h[HASH]) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,)>) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b28Type$LT$$LP$u8$C$u16$RP$$GT$17h[HASH]E) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,u16)>::h[HASH]) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,u16)>) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b34Type$LT$$LP$u8$C$u16$C$u32$RP$$GT$17h[HASH]E) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,u16,u32)>::h[HASH]) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,u16,u32)>) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b28Type$LT$$BP$const$u20$u8$GT$17h[HASH]E) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<*const u8>::h[HASH]) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<*const u8>) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b26Type$LT$$BP$mut$u20$u8$GT$17h[HASH]E) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<*mut u8>::h[HASH]) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<*mut u8>) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b19Type$LT$$RF$str$GT$17h[HASH]E) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<&str>::h[HASH]) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<&str>) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b27Type$LT$$RF$mut$u20$str$GT$17h[HASH]E) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<&mut str>::h[HASH]) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<&mut str>) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[u8; 0]>::h[HASH]) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[u8; 0]>) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b22Type$LT$fn$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b60Type$LT$unsafe$u20$extern$u20$$u22$C$u22$$u20$fn$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b34Type$LT$$u5b$T$u3b$$u20$N$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[T; N]>::h[HASH]) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[T; N]>) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[u8; 0]>::h[HASH]) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[u8; 0]>) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 87 previous errors diff --git a/tests/ui/symbol-names/types.rs b/tests/ui/symbol-names/types.rs index a4bbbaa02f27..9dc7cad33cb0 100644 --- a/tests/ui/symbol-names/types.rs +++ b/tests/ui/symbol-names/types.rs @@ -15,7 +15,7 @@ pub fn b() { struct Type(T); - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b16Type$LT$bool$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -24,7 +24,7 @@ pub fn b() { //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b16Type$LT$char$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -33,7 +33,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b14Type$LT$i8$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -42,7 +42,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$i16$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -51,7 +51,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$i32$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -60,7 +60,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$i64$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -69,7 +69,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b14Type$LT$u8$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -78,7 +78,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$u16$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -87,7 +87,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$u32$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -96,7 +96,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$u64$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -105,7 +105,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$f16$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -114,7 +114,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$f32$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -123,7 +123,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$f64$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -132,7 +132,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b16Type$LT$f128$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -141,7 +141,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b15Type$LT$str$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -150,7 +150,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b17Type$LT$$u21$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -159,7 +159,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b20Type$LT$$LP$$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<()>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<()>) @@ -168,7 +168,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type<()> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b25Type$LT$$LP$u8$C$$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<(u8,)>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<(u8,)>) @@ -177,7 +177,7 @@ impl Type<()> {} //[v0]~| ERROR demangling-alt(>) impl Type<(u8,)> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b28Type$LT$$LP$u8$C$u16$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<(u8,u16)>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<(u8,u16)>) @@ -186,7 +186,7 @@ impl Type<(u8,)> {} //[v0]~| ERROR demangling-alt(>) impl Type<(u8, u16)> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b34Type$LT$$LP$u8$C$u16$C$u32$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<(u8,u16,u32)>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<(u8,u16,u32)>) @@ -195,7 +195,7 @@ impl Type<(u8, u16)> {} //[v0]~| ERROR demangling-alt(>) impl Type<(u8, u16, u32)> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b28Type$LT$$BP$const$u20$u8$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<*const u8>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<*const u8>) @@ -204,7 +204,7 @@ impl Type<(u8, u16, u32)> {} //[v0]~| ERROR demangling-alt(>) impl Type<*const u8> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b26Type$LT$$BP$mut$u20$u8$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<*mut u8>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<*mut u8>) @@ -213,7 +213,7 @@ impl Type<*const u8> {} //[v0]~| ERROR demangling-alt(>) impl Type<*mut u8> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b19Type$LT$$RF$str$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<&str>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<&str>) @@ -222,7 +222,7 @@ impl Type<*mut u8> {} //[v0]~| ERROR demangling-alt(>) impl Type<&str> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b27Type$LT$$RF$mut$u20$str$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<&mut str>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<&mut str>) @@ -231,7 +231,7 @@ impl Type<&str> {} //[v0]~| ERROR demangling-alt(>) impl Type<&mut str> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<[u8; 0]>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<[u8; 0]>) @@ -240,7 +240,7 @@ impl Type<&mut str> {} //[v0]~| ERROR demangling-alt(>) impl Type<[u8; 0]> {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b22Type$LT$fn$LP$$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -249,7 +249,7 @@ impl Type<&mut str> {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b60Type$LT$unsafe$u20$extern$u20$$u22$C$u22$$u20$fn$LP$$RP$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type) @@ -258,7 +258,7 @@ impl Type {} //[v0]~| ERROR demangling-alt(>) impl Type {} - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b34Type$LT$$u5b$T$u3b$$u20$N$u5d$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<[T; N]>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<[T; N]>) @@ -269,7 +269,7 @@ impl Type {} const ZERO: usize = 0; - #[rustc_symbol_name] + #[rustc_dump_symbol_name] //[legacy,verbose-legacy]~^ ERROR symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$ //[legacy,verbose-legacy]~| ERROR demangling(a::b::Type<[u8; 0]>:: //[legacy,verbose-legacy]~| ERROR demangling-alt(a::b::Type<[u8; 0]>) diff --git a/tests/ui/symbol-names/types.v0.stderr b/tests/ui/symbol-names/types.v0.stderr index 90012a2dcf72..36e0306c18b4 100644 --- a/tests/ui/symbol-names/types.v0.stderr +++ b/tests/ui/symbol-names/types.v0.stderr @@ -1,524 +1,524 @@ error: symbol-name(_RMNvCsCRATE_HASH_1a1bINtB_4TypebE) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs_NvCsCRATE_HASH_1a1bINtB_4TypecE) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs0_NvCsCRATE_HASH_1a1bINtB_4TypeaE) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs1_NvCsCRATE_HASH_1a1bINtB_4TypesE) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs2_NvCsCRATE_HASH_1a1bINtB_4TypelE) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs3_NvCsCRATE_HASH_1a1bINtB_4TypexE) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs4_NvCsCRATE_HASH_1a1bINtB_4TypehE) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs5_NvCsCRATE_HASH_1a1bINtB_4TypetE) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs6_NvCsCRATE_HASH_1a1bINtB_4TypemE) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs7_NvCsCRATE_HASH_1a1bINtB_4TypeyE) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs8_NvCsCRATE_HASH_1a1bINtB_4TypeC3f16E) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMs9_NvCsCRATE_HASH_1a1bINtB_4TypefE) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsa_NvCsCRATE_HASH_1a1bINtB_4TypedE) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsb_NvCsCRATE_HASH_1a1bINtB_4TypeC4f128E) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsc_NvCsCRATE_HASH_1a1bINtB_4TypeeE) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsd_NvCsCRATE_HASH_1a1bINtB_4TypezE) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMse_NvCsCRATE_HASH_1a1bINtB_4TypeuE) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsf_NvCsCRATE_HASH_1a1bINtB_4TypeThEE) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsg_NvCsCRATE_HASH_1a1bINtB_4TypeThtEE) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsh_NvCsCRATE_HASH_1a1bINtB_4TypeThtmEE) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsi_NvCsCRATE_HASH_1a1bINtB_4TypePhE) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsj_NvCsCRATE_HASH_1a1bINtB_4TypeOhE) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsk_NvCsCRATE_HASH_1a1bINtB_4TypeReE) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsl_NvCsCRATE_HASH_1a1bINtB_4TypeQeE) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsm_NvCsCRATE_HASH_1a1bINtB_4TypeAhj0_E) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsn_NvCsCRATE_HASH_1a1bINtB_4TypeFEuE) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMso_NvCsCRATE_HASH_1a1bINtB_4TypeFUKCEuE) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsp_NvCsCRATE_HASH_1a1bINtB_4TypeAppEB_) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_RMsq_NvCsCRATE_HASH_1a1bINtB_4TypeAhj0_E) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(>) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(>) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 87 previous errors diff --git a/tests/ui/symbol-names/types.verbose-legacy.stderr b/tests/ui/symbol-names/types.verbose-legacy.stderr index c368b3186098..53f0c1e57666 100644 --- a/tests/ui/symbol-names/types.verbose-legacy.stderr +++ b/tests/ui/symbol-names/types.verbose-legacy.stderr @@ -1,524 +1,524 @@ error: symbol-name(_ZN1a1b16Type$LT$bool$GT$17h[HASH]E) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:18:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b16Type$LT$char$GT$17h[HASH]E) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:27:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b14Type$LT$i8$GT$17h[HASH]E) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:36:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i16$GT$17h[HASH]E) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:45:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i32$GT$17h[HASH]E) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:54:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$i64$GT$17h[HASH]E) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:63:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b14Type$LT$u8$GT$17h[HASH]E) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:72:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u16$GT$17h[HASH]E) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:81:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u32$GT$17h[HASH]E) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:90:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$u64$GT$17h[HASH]E) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:99:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f16$GT$17h[HASH]E) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:108:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f32$GT$17h[HASH]E) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:117:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$f64$GT$17h[HASH]E) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:126:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b16Type$LT$f128$GT$17h[HASH]E) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:135:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b15Type$LT$str$GT$17h[HASH]E) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:144:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b17Type$LT$$u21$$GT$17h[HASH]E) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:153:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b20Type$LT$$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<()>::h[HASH]) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<()>) --> $DIR/types.rs:162:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b25Type$LT$$LP$u8$C$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,)>::h[HASH]) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,)>) --> $DIR/types.rs:171:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b28Type$LT$$LP$u8$C$u16$RP$$GT$17h[HASH]E) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,u16)>::h[HASH]) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,u16)>) --> $DIR/types.rs:180:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b34Type$LT$$LP$u8$C$u16$C$u32$RP$$GT$17h[HASH]E) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<(u8,u16,u32)>::h[HASH]) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<(u8,u16,u32)>) --> $DIR/types.rs:189:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b28Type$LT$$BP$const$u20$u8$GT$17h[HASH]E) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<*const u8>::h[HASH]) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<*const u8>) --> $DIR/types.rs:198:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b26Type$LT$$BP$mut$u20$u8$GT$17h[HASH]E) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<*mut u8>::h[HASH]) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<*mut u8>) --> $DIR/types.rs:207:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b19Type$LT$$RF$str$GT$17h[HASH]E) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<&str>::h[HASH]) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<&str>) --> $DIR/types.rs:216:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b27Type$LT$$RF$mut$u20$str$GT$17h[HASH]E) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<&mut str>::h[HASH]) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<&mut str>) --> $DIR/types.rs:225:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[u8; 0]>::h[HASH]) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[u8; 0]>) --> $DIR/types.rs:234:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b22Type$LT$fn$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:243:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b60Type$LT$unsafe$u20$extern$u20$$u22$C$u22$$u20$fn$LP$$RP$$GT$17h[HASH]E) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type::h[HASH]) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type) --> $DIR/types.rs:252:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b34Type$LT$$u5b$T$u3b$$u20$N$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[T; N]>::h[HASH]) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[T; N]>) --> $DIR/types.rs:261:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: symbol-name(_ZN1a1b35Type$LT$$u5b$u8$u3b$$u20$0$u5d$$GT$17h[HASH]E) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling(a::b::Type<[u8; 0]>::h[HASH]) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: demangling-alt(a::b::Type<[u8; 0]>) --> $DIR/types.rs:272:5 | -LL | #[rustc_symbol_name] - | ^^^^^^^^^^^^^^^^^^^^ +LL | #[rustc_dump_symbol_name] + | ^^^^^^^^^^^^^^^^^^^^^^^^^ error: aborting due to 87 previous errors diff --git a/tests/ui/target-feature/feature-hierarchy.hexagon-hvxv66.stderr b/tests/ui/target-feature/feature-hierarchy.hexagon-hvxv66.stderr new file mode 100644 index 000000000000..99a6aa67e7fe --- /dev/null +++ b/tests/ui/target-feature/feature-hierarchy.hexagon-hvxv66.stderr @@ -0,0 +1,6 @@ +warning: unstable feature specified for `-Ctarget-feature`: `hvxv66` + | + = note: this feature is not stably supported; its behavior can change in the future + +warning: 1 warning emitted + diff --git a/tests/ui/target-feature/feature-hierarchy.hexagon-v60.stderr b/tests/ui/target-feature/feature-hierarchy.hexagon-v60.stderr new file mode 100644 index 000000000000..611bf370bdfa --- /dev/null +++ b/tests/ui/target-feature/feature-hierarchy.hexagon-v60.stderr @@ -0,0 +1,6 @@ +warning: unstable feature specified for `-Ctarget-feature`: `v60` + | + = note: this feature is not stably supported; its behavior can change in the future + +warning: 1 warning emitted + diff --git a/tests/ui/target-feature/feature-hierarchy.hexagon-v68.stderr b/tests/ui/target-feature/feature-hierarchy.hexagon-v68.stderr new file mode 100644 index 000000000000..67343fa798b8 --- /dev/null +++ b/tests/ui/target-feature/feature-hierarchy.hexagon-v68.stderr @@ -0,0 +1,6 @@ +warning: unstable feature specified for `-Ctarget-feature`: `v68` + | + = note: this feature is not stably supported; its behavior can change in the future + +warning: 1 warning emitted + diff --git a/tests/ui/target-feature/feature-hierarchy.rs b/tests/ui/target-feature/feature-hierarchy.rs index a14af97d7234..65f7a1e6d3db 100644 --- a/tests/ui/target-feature/feature-hierarchy.rs +++ b/tests/ui/target-feature/feature-hierarchy.rs @@ -1,14 +1,22 @@ //@ revisions: aarch64-neon aarch64-sve2 +//@ revisions: hexagon-v60 hexagon-v68 hexagon-hvxv66 //@ [aarch64-neon] compile-flags: -Ctarget-feature=+neon --target=aarch64-unknown-linux-gnu //@ [aarch64-neon] needs-llvm-components: aarch64 //@ [aarch64-sve2] compile-flags: -Ctarget-feature=-neon,+sve2 --target=aarch64-unknown-linux-gnu //@ [aarch64-sve2] needs-llvm-components: aarch64 +//@ [hexagon-v60] compile-flags: -Ctarget-feature=+v60 --target=hexagon-unknown-linux-musl +//@ [hexagon-v60] needs-llvm-components: hexagon +//@ [hexagon-v68] compile-flags: -Ctarget-feature=+v68 --target=hexagon-unknown-linux-musl +//@ [hexagon-v68] needs-llvm-components: hexagon +//@ [hexagon-hvxv66] compile-flags: -Ctarget-feature=+hvxv66 --target=hexagon-unknown-linux-musl +//@ [hexagon-hvxv66] needs-llvm-components: hexagon //@ build-pass //@ add-minicore //@ ignore-backends: gcc #![no_core] #![crate_type = "rlib"] #![feature(intrinsics, rustc_attrs, no_core, staged_api)] +#![cfg_attr(any(hexagon_v60, hexagon_v68, hexagon_hvxv66), feature(hexagon_target_feature))] #![stable(feature = "test", since = "1.0.0")] // Tests vetting "feature hierarchies" in the cases where we impose them. @@ -54,3 +62,39 @@ fn check_sve2_includes_neon() { assert!(cfg!(target_feature = "neon")); assert!(cfg!(target_feature = "sve2")); } + +//[hexagon-v60]~? WARN unstable feature specified for `-Ctarget-feature`: `v60` +//[hexagon-v68]~? WARN unstable feature specified for `-Ctarget-feature`: `v68` +//[hexagon-hvxv66]~? WARN unstable feature specified for `-Ctarget-feature`: `hvxv66` + +#[cfg(hexagon_v60)] +fn check_v60_not_v68() { + // Enabling v60 should not jump up the scalar feature hierarchy. + assert!(cfg!(target_feature = "v60")); + assert!(cfg!(not(target_feature = "v62"))); + assert!(cfg!(not(target_feature = "v68"))); +} + +#[cfg(hexagon_v68)] +fn check_v68_implies_v60() { + // v68 implies all lower scalar arch versions. + assert!(cfg!(target_feature = "v60")); + assert!(cfg!(target_feature = "v62")); + assert!(cfg!(target_feature = "v65")); + assert!(cfg!(target_feature = "v66")); + assert!(cfg!(target_feature = "v67")); + assert!(cfg!(target_feature = "v68")); + assert!(cfg!(not(target_feature = "v69"))); +} + +#[cfg(hexagon_hvxv66)] +fn check_hvxv66_implies_hvx_and_zreg() { + // hvxv66 implies hvx, hvxv60..v65, and zreg. + assert!(cfg!(target_feature = "hvx")); + assert!(cfg!(target_feature = "hvxv60")); + assert!(cfg!(target_feature = "hvxv62")); + assert!(cfg!(target_feature = "hvxv65")); + assert!(cfg!(target_feature = "hvxv66")); + assert!(cfg!(target_feature = "zreg")); + assert!(cfg!(not(target_feature = "hvxv67"))); +} diff --git a/tests/ui/target-feature/invalid-attribute.stderr b/tests/ui/target-feature/invalid-attribute.stderr index 8b91381a32b3..64d4ceff5a87 100644 --- a/tests/ui/target-feature/invalid-attribute.stderr +++ b/tests/ui/target-feature/invalid-attribute.stderr @@ -27,27 +27,42 @@ error[E0539]: malformed `target_feature` attribute input | LL | #[target_feature = "+sse2"] | ^^^^^^^^^^^^^^^^^---------^ - | | | - | | expected this to be a list - | help: must be of the form: `#[target_feature(enable = "feat1, feat2")]` + | | + | expected this to be a list + | +help: must be of the form + | +LL - #[target_feature = "+sse2"] +LL + #[target_feature(enable = "feat1, feat2")] + | error[E0539]: malformed `target_feature` attribute input --> $DIR/invalid-attribute.rs:29:1 | LL | #[target_feature(bar)] | ^^^^^^^^^^^^^^^^^---^^ - | | | - | | expected this to be of the form `enable = "..."` - | help: must be of the form: `#[target_feature(enable = "feat1, feat2")]` + | | + | expected this to be of the form `enable = "..."` + | +help: must be of the form + | +LL - #[target_feature(bar)] +LL + #[target_feature(enable = "feat1, feat2")] + | error[E0539]: malformed `target_feature` attribute input --> $DIR/invalid-attribute.rs:32:1 | LL | #[target_feature(disable = "baz")] | ^^^^^^^^^^^^^^^^^-------^^^^^^^^^^ - | | | - | | expected this to be of the form `enable = "..."` - | help: must be of the form: `#[target_feature(enable = "feat1, feat2")]` + | | + | expected this to be of the form `enable = "..."` + | +help: must be of the form + | +LL - #[target_feature(disable = "baz")] +LL + #[target_feature(enable = "feat1, feat2")] + | error: `#[target_feature]` attribute cannot be used on modules --> $DIR/invalid-attribute.rs:37:1 @@ -161,7 +176,7 @@ error: the feature named `foo` is not valid for this target LL | #[target_feature(enable = "foo")] | ^^^^^^^^^^^^^^ `foo` is not valid for this target | - = help: valid names are: `fma`, `xop`, `adx`, `aes`, and `avx` and 74 more + = help: valid names are: `fma`, `xop`, `adx`, `aes`, and `avx` and 75 more error[E0046]: not all trait items implemented, missing: `foo` --> $DIR/invalid-attribute.rs:81:1 @@ -213,7 +228,7 @@ error: the feature named `sse5` is not valid for this target LL | #[target_feature(enable = "sse5")] | ^^^^^^^^^^^^^^^ `sse5` is not valid for this target | - = help: valid names are: `sse`, `sse2`, `sse3`, `sse4a`, and `ssse3` and 74 more + = help: valid names are: `sse`, `sse2`, `sse3`, `sse4a`, and `ssse3` and 75 more error: the feature named `avx512` is not valid for this target --> $DIR/invalid-attribute.rs:127:18 @@ -221,7 +236,7 @@ error: the feature named `avx512` is not valid for this target LL | #[target_feature(enable = "avx512")] | ^^^^^^^^^^^^^^^^^ `avx512` is not valid for this target | - = help: valid names are: `avx512f`, `avx2`, `avx512bw`, `avx512cd`, and `avx512dq` and 74 more + = help: valid names are: `avx512f`, `avx2`, `avx512bw`, `avx512cd`, and `avx512dq` and 75 more error: aborting due to 26 previous errors diff --git a/tests/ui/thir-print/c-variadic.stderr b/tests/ui/thir-print/c-variadic.stderr new file mode 100644 index 000000000000..a4050695944d --- /dev/null +++ b/tests/ui/thir-print/c-variadic.stderr @@ -0,0 +1,12 @@ +Future incompatibility report: Future breakage diagnostic: +warning: missing pattern for `...` argument + --> $DIR/c-variadic.rs:7:34 + | +LL | unsafe extern "C" fn foo(_: i32, ...) {} + | ^^^ + | +help: name the argument, or use `_` to continue ignoring it + | +LL | unsafe extern "C" fn foo(_: i32, _: ...) {} + | ++ + diff --git a/tests/ui/tool-attributes/invalid-tool.stderr b/tests/ui/tool-attributes/invalid-tool.stderr index 4f82e9ef5437..0e06af5a6ae1 100644 --- a/tests/ui/tool-attributes/invalid-tool.stderr +++ b/tests/ui/tool-attributes/invalid-tool.stderr @@ -3,9 +3,14 @@ error[E0539]: malformed `register_tool` attribute input | LL | #![register_tool(1)] | ^^^^^^^^^^^^^^^^^-^^ - | | | - | | expected a valid identifier here - | help: must be of the form: `#![register_tool(tool1, tool2, ...)]` + | | + | expected a valid identifier here + | +help: must be of the form + | +LL - #![register_tool(1)] +LL + #![register_tool(tool1, tool2, ...)] + | error: aborting due to 1 previous error diff --git a/tests/ui/tool-attributes/nested-disallowed.stderr b/tests/ui/tool-attributes/nested-disallowed.stderr index e59ebd979b4c..5e0369711a39 100644 --- a/tests/ui/tool-attributes/nested-disallowed.stderr +++ b/tests/ui/tool-attributes/nested-disallowed.stderr @@ -3,9 +3,14 @@ error[E0539]: malformed `register_tool` attribute input | LL | #![register_tool(foo::bar)] | ^^^^^^^^^^^^^^^^^--------^^ - | | | - | | expected a valid identifier here - | help: must be of the form: `#![register_tool(tool1, tool2, ...)]` + | | + | expected a valid identifier here + | +help: must be of the form + | +LL - #![register_tool(foo::bar)] +LL + #![register_tool(tool1, tool2, ...)] + | error: aborting due to 1 previous error diff --git a/tests/ui/tool-attributes/tool_lints.rs b/tests/ui/tool-attributes/tool_lints.rs index 0a9be75681ca..9e4aa7a939ac 100644 --- a/tests/ui/tool-attributes/tool_lints.rs +++ b/tests/ui/tool-attributes/tool_lints.rs @@ -1,3 +1,5 @@ #[warn(foo::bar)] //~^ ERROR unknown tool name `foo` found in scoped lint: `foo::bar` +//~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` +//~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` fn main() {} diff --git a/tests/ui/tool-attributes/tool_lints.stderr b/tests/ui/tool-attributes/tool_lints.stderr index a0c5316d95b0..eee0a9784ece 100644 --- a/tests/ui/tool-attributes/tool_lints.stderr +++ b/tests/ui/tool-attributes/tool_lints.stderr @@ -6,6 +6,24 @@ LL | #[warn(foo::bar)] | = help: add `#![register_tool(foo)]` to the crate root -error: aborting due to 1 previous error +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/tool_lints.rs:1:8 + | +LL | #[warn(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/tool_lints.rs:1:8 + | +LL | #[warn(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 3 previous errors For more information about this error, try `rustc --explain E0710`. diff --git a/tests/ui/tool-attributes/unknown-lint-tool-name.rs b/tests/ui/tool-attributes/unknown-lint-tool-name.rs index 844c29a46b7b..84ab7c1944ab 100644 --- a/tests/ui/tool-attributes/unknown-lint-tool-name.rs +++ b/tests/ui/tool-attributes/unknown-lint-tool-name.rs @@ -1,6 +1,8 @@ -#![deny(foo::bar)] -//~^ ERROR unknown tool name `foo` found in scoped lint: `foo::bar` +#![deny(foo::bar)] //~ ERROR unknown tool name `foo` found in scoped lint: `foo::bar` + //~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` + //~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` -#[allow(foo::bar)] -//~^ ERROR unknown tool name `foo` found in scoped lint: `foo::bar` +#[allow(foo::bar)] //~ ERROR unknown tool name `foo` found in scoped lint: `foo::bar` + //~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` + //~| ERROR unknown tool name `foo` found in scoped lint: `foo::bar` fn main() {} diff --git a/tests/ui/tool-attributes/unknown-lint-tool-name.stderr b/tests/ui/tool-attributes/unknown-lint-tool-name.stderr index ae8d081e9d9c..91baf8827375 100644 --- a/tests/ui/tool-attributes/unknown-lint-tool-name.stderr +++ b/tests/ui/tool-attributes/unknown-lint-tool-name.stderr @@ -7,13 +7,49 @@ LL | #![deny(foo::bar)] = help: add `#![register_tool(foo)]` to the crate root error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` - --> $DIR/unknown-lint-tool-name.rs:4:9 + --> $DIR/unknown-lint-tool-name.rs:5:9 | LL | #[allow(foo::bar)] | ^^^ | = help: add `#![register_tool(foo)]` to the crate root -error: aborting due to 2 previous errors +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/unknown-lint-tool-name.rs:1:9 + | +LL | #![deny(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/unknown-lint-tool-name.rs:5:9 + | +LL | #[allow(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/unknown-lint-tool-name.rs:1:9 + | +LL | #![deny(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error[E0710]: unknown tool name `foo` found in scoped lint: `foo::bar` + --> $DIR/unknown-lint-tool-name.rs:5:9 + | +LL | #[allow(foo::bar)] + | ^^^ + | + = help: add `#![register_tool(foo)]` to the crate root + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 6 previous errors For more information about this error, try `rustc --explain E0710`. diff --git a/tests/ui/traits/alias/default-trait-bounds.fail.stderr b/tests/ui/traits/alias/default-trait-bounds.fail.stderr new file mode 100644 index 000000000000..9216a1443b64 --- /dev/null +++ b/tests/ui/traits/alias/default-trait-bounds.fail.stderr @@ -0,0 +1,44 @@ +error[E0277]: the size for values of type `str` cannot be known at compilation time + --> $DIR/default-trait-bounds.rs:26:34 + | +LL | #[cfg(fail)] fn a1_fail() { a1::; } + | ^^^ doesn't have a size known at compile-time + | + = help: the trait `Sized` is not implemented for `str` + = note: required for `()` to implement `A1` +note: required by a bound in `a1` + --> $DIR/default-trait-bounds.rs:25:30 + | +LL | fn a1() where (): A1 { ensure_is_sized::; } + | ^^^^^ required by this bound in `a1` + +error[E0277]: the size for values of type `ExternTy` cannot be known + --> $DIR/default-trait-bounds.rs:49:34 + | +LL | #[cfg(fail)] fn b1_fail() { b1::; } + | ^^^^^^^^ doesn't have a known size + | + = help: the nightly-only, unstable trait `MetaSized` is not implemented for `ExternTy` + = note: required for `()` to implement `B1` +note: required by a bound in `b1` + --> $DIR/default-trait-bounds.rs:47:36 + | +LL | fn b1() where (): B1 { ensure_is_meta_sized::(); } + | ^^^^^ required by this bound in `b1` + +error[E0277]: the trait bound `ExternTy: C1` is not satisfied + --> $DIR/default-trait-bounds.rs:65:34 + | +LL | #[cfg(fail)] fn c1_fail() { c1::; } + | ^^^^^^^^ the nightly-only, unstable trait `MetaSized` is not implemented for `ExternTy` + | + = note: required for `ExternTy` to implement `C1` +note: required by a bound in `c1` + --> $DIR/default-trait-bounds.rs:63:35 + | +LL | fn c1() where T: C1 { ensure_is_meta_sized::; } + | ^^ required by this bound in `c1` + +error: aborting due to 3 previous errors + +For more information about this error, try `rustc --explain E0277`. diff --git a/tests/ui/traits/alias/default-trait-bounds.rs b/tests/ui/traits/alias/default-trait-bounds.rs new file mode 100644 index 000000000000..5b82dd8b1ba4 --- /dev/null +++ b/tests/ui/traits/alias/default-trait-bounds.rs @@ -0,0 +1,71 @@ +// Check that trait alias bounds also imply default trait bounds to ensure that +// default and user-written bounds behave the same wrt. trait solving. +// +// Previously, we would only imply default trait bounds on +// *`Self`* type params, not on regular type params however. +// issue: +// +//@ revisions: pass fail +//@[pass] check-pass + +#![feature(trait_alias)] +#![feature(sized_hierarchy, extern_types)] // only used for the `MetaSized` test cases + +//------------------------- `Sized` + +trait A0 =; // has a user-written `T: Sized` boun + +// `(): A0` requires+implies `T: Sized` +fn a0() where (): A0 { ensure_is_sized::; } + + +trait A1 =; // has a default `T: Sized` bound + +// `(): A1` requires+implies `T: Sized` +fn a1() where (): A1 { ensure_is_sized::; } +#[cfg(fail)] fn a1_fail() { a1::; } +//[fail]~^ ERROR the size for values of type `str` cannot be known at compilation time + + +fn ensure_is_sized() {} + +//------------------------- `MetaSized` + +use std::marker::{MetaSized, PointeeSized}; +unsafe extern "C" { type ExternTy; } + + +trait B0 =; // has a user-written `T: MetaSized` bounds + +// `(): B0` requires+implies `T: MetaSized` +fn b0() where (): B0 { ensure_is_meta_sized::(); } + + +trait B1 =; // has a default `T: MetaSized` bound + +// `(): B1` requires+implies `T: MetaSized` +fn b1() where (): B1 { ensure_is_meta_sized::(); } + +#[cfg(fail)] fn b1_fail() { b1::; } +//[fail]~^ ERROR the size for values of type `ExternTy` cannot be known + +// For completeness, let's also check default trait bounds on `Self`. + +trait C0 = MetaSized; // has a user-written `Self: MetaSized` bound + +// `T: C0` requires+implies `T: MetaSized` +fn c0() where T: C0 { ensure_is_meta_sized::; } + + +trait C1 =; // has a default `Self: MetaSized` bound + +// `T: C1` requires+implies `T: MetaSized` +fn c1() where T: C1 { ensure_is_meta_sized::; } + +#[cfg(fail)] fn c1_fail() { c1::; } +//[fail]~^ ERROR the trait bound `ExternTy: C1` is not satisfied + + +fn ensure_is_meta_sized() {} + +fn main() {} diff --git a/tests/ui/traits/alias/more-default-trait-bounds.fail.stderr b/tests/ui/traits/alias/more-default-trait-bounds.fail.stderr new file mode 100644 index 000000000000..35672b14c73b --- /dev/null +++ b/tests/ui/traits/alias/more-default-trait-bounds.fail.stderr @@ -0,0 +1,39 @@ +error[E0277]: the trait bound `Unmarked: Mark` is not satisfied + --> $DIR/more-default-trait-bounds.rs:27:34 + | +LL | #[cfg(fail)] fn a1_fail() { a1::; } + | ^^^^^^^^ unsatisfied trait bound + | +help: the trait `Mark` is not implemented for `Unmarked` + --> $DIR/more-default-trait-bounds.rs:47:1 + | +LL | enum Unmarked {} + | ^^^^^^^^^^^^^ + = note: required for `()` to implement `A1` +note: required by a bound in `a1` + --> $DIR/more-default-trait-bounds.rs:25:29 + | +LL | fn a1() where (): A1 { ensure_has_mark::; } + | ^^^^^ required by this bound in `a1` + +error[E0277]: the trait bound `Unmarked: B1` is not satisfied + --> $DIR/more-default-trait-bounds.rs:41:34 + | +LL | #[cfg(fail)] fn b1_fail() { b1::; } + | ^^^^^^^^ unsatisfied trait bound + | +help: the trait `Mark` is not implemented for `Unmarked` + --> $DIR/more-default-trait-bounds.rs:47:1 + | +LL | enum Unmarked {} + | ^^^^^^^^^^^^^ + = note: required for `Unmarked` to implement `B1` +note: required by a bound in `b1` + --> $DIR/more-default-trait-bounds.rs:39:28 + | +LL | fn b1() where T: B1 { ensure_has_mark::; } + | ^^ required by this bound in `b1` + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0277`. diff --git a/tests/ui/traits/alias/more-default-trait-bounds.rs b/tests/ui/traits/alias/more-default-trait-bounds.rs new file mode 100644 index 000000000000..dc1f171823a5 --- /dev/null +++ b/tests/ui/traits/alias/more-default-trait-bounds.rs @@ -0,0 +1,50 @@ +// Check that trait alias bounds also imply default trait bounds to ensure_has_mark that +// default and user-written bounds behave the same wrt. trait solving. +// +// Previously, we would only imply default trait bounds on +// *`Self`* type params, not on regular type params however. +// issue: +// +//@ revisions: pass fail +//@ compile-flags: -Zexperimental-default-bounds +//@[pass] check-pass + +#![feature(trait_alias, more_maybe_bounds, lang_items, auto_traits, negative_impls)] + +#[lang = "default_trait1"] +auto trait Mark {} + + +trait A0 = ?Mark; // has a user-written `T: Mark` bound + +fn a0() where (): A0 { ensure_has_mark::; } + + +trait A1 = ?Mark; // has a default `T: Mark` bound + +fn a1() where (): A1 { ensure_has_mark::; } + +#[cfg(fail)] fn a1_fail() { a1::; } +//[fail]~^ ERROR the trait bound `Unmarked: Mark` is not satisfied + +// For completeness, let's also check default trait bounds on `Self`. + +trait B0 = Mark; // has a user-written `Self: Mark` bound + +fn b0() where T: B0 { ensure_has_mark::; } + + +trait B1 =; // has a default `Self: Mark` bound + +fn b1() where T: B1 { ensure_has_mark::; } + +#[cfg(fail)] fn b1_fail() { b1::; } +//[fail]~^ ERROR the trait bound `Unmarked: B1` is not satisfied + + +fn ensure_has_mark() {} + +enum Unmarked {} +impl !Mark for Unmarked {} + +fn main() {} diff --git a/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.rs b/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.rs index ae5899f08446..e61ae2760aab 100644 --- a/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.rs +++ b/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.rs @@ -10,6 +10,6 @@ fn default() -> A { #[derive_const(Default)] pub struct S(A); -//~^ ERROR: `A: [const] Default` is not satisfied +//~^ ERROR: cannot call non-const associated function fn main() {} diff --git a/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.stderr b/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.stderr index ba6fb140f424..558957985328 100644 --- a/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.stderr +++ b/tests/ui/traits/const-traits/const_derives/derive-const-non-const-type.stderr @@ -1,4 +1,4 @@ -error[E0277]: the trait bound `A: [const] Default` is not satisfied +error[E0015]: cannot call non-const associated function `::default` in constant functions --> $DIR/derive-const-non-const-type.rs:12:14 | LL | #[derive_const(Default)] @@ -6,11 +6,8 @@ LL | #[derive_const(Default)] LL | pub struct S(A); | ^ | -help: make the `impl` of trait `Default` `const` - | -LL | impl const Default for A { - | +++++ + = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants error: aborting due to 1 previous error -For more information about this error, try `rustc --explain E0277`. +For more information about this error, try `rustc --explain E0015`. diff --git a/tests/ui/traits/const-traits/cross-crate.rs b/tests/ui/traits/const-traits/cross-crate.rs index a91201e3566b..b07aa8944c05 100644 --- a/tests/ui/traits/const-traits/cross-crate.rs +++ b/tests/ui/traits/const-traits/cross-crate.rs @@ -17,9 +17,10 @@ fn non_const_context() { const fn const_context() { #[cfg(any(stocknc, gatednc))] NonConst.func(); - //[stocknc,gatednc]~^ ERROR: the trait bound + //[stocknc]~^ ERROR: cannot call + //[gatednc]~^^ ERROR: the trait bound Const.func(); - //[stock]~^ ERROR: cannot call + //[stock,stocknc]~^ ERROR: cannot call } fn main() {} diff --git a/tests/ui/traits/const-traits/cross-crate.stock.stderr b/tests/ui/traits/const-traits/cross-crate.stock.stderr index 606793cd3149..44a60c99ae9e 100644 --- a/tests/ui/traits/const-traits/cross-crate.stock.stderr +++ b/tests/ui/traits/const-traits/cross-crate.stock.stderr @@ -1,5 +1,5 @@ error[E0658]: cannot call conditionally-const method `::func` in constant functions - --> $DIR/cross-crate.rs:21:11 + --> $DIR/cross-crate.rs:22:11 | LL | Const.func(); | ^^^^^^ diff --git a/tests/ui/traits/const-traits/cross-crate.stocknc.stderr b/tests/ui/traits/const-traits/cross-crate.stocknc.stderr index 45e06c78cfb2..766c20aa8211 100644 --- a/tests/ui/traits/const-traits/cross-crate.stocknc.stderr +++ b/tests/ui/traits/const-traits/cross-crate.stocknc.stderr @@ -1,15 +1,23 @@ -error[E0277]: the trait bound `cross_crate::NonConst: [const] cross_crate::MyTrait` is not satisfied +error[E0015]: cannot call non-const method `::func` in constant functions --> $DIR/cross-crate.rs:19:14 | LL | NonConst.func(); - | ^^^^ + | ^^^^^^ | -note: trait `MyTrait` is implemented but not `const` - --> $DIR/auxiliary/cross-crate.rs:11:1 + = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants + +error[E0658]: cannot call conditionally-const method `::func` in constant functions + --> $DIR/cross-crate.rs:22:11 | -LL | impl MyTrait for NonConst { - | ^^^^^^^^^^^^^^^^^^^^^^^^^ +LL | Const.func(); + | ^^^^^^ + | + = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants + = note: see issue #143874 for more information + = help: add `#![feature(const_trait_impl)]` to the crate attributes to enable + = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date -error: aborting due to 1 previous error +error: aborting due to 2 previous errors -For more information about this error, try `rustc --explain E0277`. +Some errors have detailed explanations: E0015, E0658. +For more information about an error, try `rustc --explain E0015`. diff --git a/tests/ui/traits/const-traits/ice-126148-failed-to-normalize.rs b/tests/ui/traits/const-traits/ice-126148-failed-to-normalize.rs index bfce9dc9c733..e02710eef628 100644 --- a/tests/ui/traits/const-traits/ice-126148-failed-to-normalize.rs +++ b/tests/ui/traits/const-traits/ice-126148-failed-to-normalize.rs @@ -1,6 +1,6 @@ #![allow(incomplete_features)] -#![feature(const_trait_impl, try_trait_v2, const_try)] -use std::ops::{FromResidual, Try}; +#![feature(const_trait_impl, try_trait_v2, try_trait_v2_residual, const_try, const_try_residual)] +use std::ops::{FromResidual, Residual, Try}; struct TryMe; struct Error; @@ -14,6 +14,10 @@ impl const Try for TryMe { type Residual = Error; } +impl const Residual<()> for Error { + type TryType = TryMe; +} + const fn t() -> TryMe { TryMe?; TryMe diff --git a/tests/ui/traits/const-traits/mismatched_generic_args.stderr b/tests/ui/traits/const-traits/mismatched_generic_args.stderr index 3094cb501330..7dfbe7509947 100644 --- a/tests/ui/traits/const-traits/mismatched_generic_args.stderr +++ b/tests/ui/traits/const-traits/mismatched_generic_args.stderr @@ -20,9 +20,9 @@ LL | pub struct Quantity(S); | ^^^^^^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | error[E0107]: trait takes at most 1 generic argument but 2 generic arguments were supplied @@ -38,9 +38,9 @@ LL | impl Add for Quantity(x: Quantity) -> Quantity { | ^^^^^^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | error: aborting due to 5 previous errors diff --git a/tests/ui/traits/const-traits/self-receiver-type-mismatch.rs b/tests/ui/traits/const-traits/self-receiver-type-mismatch.rs new file mode 100644 index 000000000000..61f0dbe3a975 --- /dev/null +++ b/tests/ui/traits/const-traits/self-receiver-type-mismatch.rs @@ -0,0 +1,24 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/112623. +//! The const evaluator used to ICE with an assertion failure on a size mismatch +//! when a trait impl changed the `self` receiver type from by-value to by-reference. + +#![feature(const_trait_impl)] + +const trait Func { + fn trigger(self) -> usize; +} + +struct Cls; + +impl const Func for Cls { + fn trigger(&self, a: usize) -> usize { + //~^ ERROR method `trigger` has 2 parameters but the declaration in trait `Func::trigger` has 1 + 0 + } +} + +enum Bug { + V(T), +} + +fn main() {} diff --git a/tests/ui/traits/const-traits/self-receiver-type-mismatch.stderr b/tests/ui/traits/const-traits/self-receiver-type-mismatch.stderr new file mode 100644 index 000000000000..4fd65d38a40d --- /dev/null +++ b/tests/ui/traits/const-traits/self-receiver-type-mismatch.stderr @@ -0,0 +1,12 @@ +error[E0050]: method `trigger` has 2 parameters but the declaration in trait `Func::trigger` has 1 + --> $DIR/self-receiver-type-mismatch.rs:14:16 + | +LL | fn trigger(self) -> usize; + | ---- trait requires 1 parameter +... +LL | fn trigger(&self, a: usize) -> usize { + | ^^^^^^^^^^^^^^^ expected 1 parameter, found 2 + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0050`. diff --git a/tests/ui/traits/const-traits/super-traits-fail-3.nyn.stderr b/tests/ui/traits/const-traits/super-traits-fail-3.nyn.stderr index 42b051cd8df8..1c56aa129794 100644 --- a/tests/ui/traits/const-traits/super-traits-fail-3.nyn.stderr +++ b/tests/ui/traits/const-traits/super-traits-fail-3.nyn.stderr @@ -83,13 +83,15 @@ help: enable `#![feature(const_trait_impl)]` in your crate and mark `Bar` as `co LL | #[cfg(any(yyn, ynn, nyn, nnn))] const trait Bar: [const] Foo {} | +++++ -error[E0277]: the trait bound `T: [const] Foo` is not satisfied +error[E0015]: cannot call non-const method `::a` in constant functions --> $DIR/super-traits-fail-3.rs:38:7 | LL | x.a(); - | ^ + | ^^^ + | + = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants error: aborting due to 9 previous errors -Some errors have detailed explanations: E0277, E0658. -For more information about an error, try `rustc --explain E0277`. +Some errors have detailed explanations: E0015, E0658. +For more information about an error, try `rustc --explain E0015`. diff --git a/tests/ui/traits/const-traits/super-traits-fail-3.rs b/tests/ui/traits/const-traits/super-traits-fail-3.rs index 55e8d3ca6e6a..7dd434c528d0 100644 --- a/tests/ui/traits/const-traits/super-traits-fail-3.rs +++ b/tests/ui/traits/const-traits/super-traits-fail-3.rs @@ -36,8 +36,8 @@ const fn foo(x: &T) { //[yyn,ynn,nyn,nnn]~| ERROR: `[const]` can only be applied to `const` traits //[nyy,nyn,nny,nnn]~^^^ ERROR: const trait impls are experimental x.a(); - //[yyn,nyn]~^ ERROR: the trait bound `T: [const] Foo` is not satisfied - //[ynn,yny,nny,nnn]~^^ ERROR: cannot call non-const method `::a` in constant functions + //[yyn]~^ ERROR: the trait bound `T: [const] Foo` is not satisfied + //[ynn,yny,nny,nnn,nyn]~^^ ERROR: cannot call non-const method `::a` in constant functions //[nyy]~^^^ ERROR: cannot call conditionally-const method `::a` in constant functions } diff --git a/tests/ui/traits/const-traits/trait-default-body-stability.rs b/tests/ui/traits/const-traits/trait-default-body-stability.rs index 1053f54aa6fc..4a2bcbe5dc1c 100644 --- a/tests/ui/traits/const-traits/trait-default-body-stability.rs +++ b/tests/ui/traits/const-traits/trait-default-body-stability.rs @@ -5,11 +5,12 @@ #![feature(const_trait_impl)] #![feature(const_t_try)] #![feature(const_try)] +#![feature(const_try_residual)] #![feature(try_trait_v2)] - +#![feature(try_trait_v2_residual)] #![stable(feature = "foo", since = "1.0")] -use std::ops::{ControlFlow, FromResidual, Try}; +use std::ops::{ControlFlow, FromResidual, Residual, Try}; #[stable(feature = "foo", since = "1.0")] pub struct T; @@ -29,6 +30,12 @@ fn branch(self) -> ControlFlow { } } +#[stable(feature = "foo", since = "1.0")] +#[rustc_const_unstable(feature = "const_t_try", issue = "none")] +impl const Residual for T { + type TryType = T; +} + #[stable(feature = "foo", since = "1.0")] #[rustc_const_unstable(feature = "const_t_try", issue = "none")] impl const FromResidual for T { diff --git a/tests/ui/traits/default-method/rustc_must_implement_one_of_misuse.stderr b/tests/ui/traits/default-method/rustc_must_implement_one_of_misuse.stderr index 0d854b4594fa..1059db683efb 100644 --- a/tests/ui/traits/default-method/rustc_must_implement_one_of_misuse.stderr +++ b/tests/ui/traits/default-method/rustc_must_implement_one_of_misuse.stderr @@ -3,18 +3,25 @@ error[E0539]: malformed `rustc_must_implement_one_of` attribute input | LL | #[rustc_must_implement_one_of(a)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^---^ - | | | - | | expected 2 or more items - | help: must be of the form: `#[rustc_must_implement_one_of(function1, function2, ...)]` + | | + | expected 2 or more items + | +help: must be of the form + | +LL - #[rustc_must_implement_one_of(a)] +LL + #[rustc_must_implement_one_of(function1, function2, ...)] + | error[E0539]: malformed `rustc_must_implement_one_of` attribute input --> $DIR/rustc_must_implement_one_of_misuse.rs:20:1 | LL | #[rustc_must_implement_one_of] - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - | | - | expected this to be a list - | help: must be of the form: `#[rustc_must_implement_one_of(function1, function2, ...)]` + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ expected this to be a list + | +help: must be of the form + | +LL | #[rustc_must_implement_one_of(function1, function2, ...)] + | +++++++++++++++++++++++++++ error: `#[rustc_must_implement_one_of]` attribute cannot be used on functions --> $DIR/rustc_must_implement_one_of_misuse.rs:38:1 diff --git a/tests/ui/traits/dyn-coerce-unsized-ice.rs b/tests/ui/traits/dyn-coerce-unsized-ice.rs new file mode 100644 index 000000000000..cfb6c57366bd --- /dev/null +++ b/tests/ui/traits/dyn-coerce-unsized-ice.rs @@ -0,0 +1,16 @@ +// Regression test for: +// https://github.com/rust-lang/rust/issues/149094#issuecomment-4191071539 +#![feature(coerce_unsized, unsized_fn_params)] +#![expect(internal_features)] + +use std::ops::CoerceUnsized; + +pub trait Trait {} + +pub fn foo(x: dyn CoerceUnsized<*const dyn Trait>) -> *const dyn Trait { +//~^ ERROR: the trait `CoerceUnsized` is not dyn compatible [E0038] + x +//~^ ERROR: the size for values of type `(dyn CoerceUnsized<*const (dyn Trait + 'static)> + 'static)` cannot be known at compilation time [E0277] +} + +fn main() {} diff --git a/tests/ui/traits/dyn-coerce-unsized-ice.stderr b/tests/ui/traits/dyn-coerce-unsized-ice.stderr new file mode 100644 index 000000000000..1bd3874f0e12 --- /dev/null +++ b/tests/ui/traits/dyn-coerce-unsized-ice.stderr @@ -0,0 +1,23 @@ +error[E0038]: the trait `CoerceUnsized` is not dyn compatible + --> $DIR/dyn-coerce-unsized-ice.rs:10:15 + | +LL | pub fn foo(x: dyn CoerceUnsized<*const dyn Trait>) -> *const dyn Trait { + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ `CoerceUnsized` is not dyn compatible + | + = note: the trait is not dyn compatible because it requires `Self: Sized` + = note: for a trait to be dyn compatible it needs to allow building a vtable + for more information, visit + +error[E0277]: the size for values of type `(dyn CoerceUnsized<*const (dyn Trait + 'static)> + 'static)` cannot be known at compilation time + --> $DIR/dyn-coerce-unsized-ice.rs:12:5 + | +LL | x + | ^ doesn't have a size known at compile-time + | + = help: the trait `Sized` is not implemented for `(dyn CoerceUnsized<*const (dyn Trait + 'static)> + 'static)` + = note: required for the cast from `(dyn CoerceUnsized<*const (dyn Trait + 'static)> + 'static)` to `*const (dyn Trait + 'static)` + +error: aborting due to 2 previous errors + +Some errors have detailed explanations: E0038, E0277. +For more information about an error, try `rustc --explain E0038`. diff --git a/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.rs b/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.rs new file mode 100644 index 000000000000..4185228a2586 --- /dev/null +++ b/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.rs @@ -0,0 +1,12 @@ +//! Regression test for https://github.com/rust-lang/rust/issues/151894 +//@ compile-flags: -Znext-solver=globally + +#![feature(const_trait_impl)] + +const fn with_positive [const] Fn(&'a ())>() {} + +const _: () = { + with_positive::<()>(); //~ ERROR expected a `Fn(&'a ())` closure, found `()` +}; + +fn main() {} diff --git a/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.stderr b/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.stderr new file mode 100644 index 000000000000..18f513cea6d4 --- /dev/null +++ b/tests/ui/traits/next-solver/diagnostics/const-host-effect-hrtb-no-ice.stderr @@ -0,0 +1,16 @@ +error[E0277]: expected a `Fn(&'a ())` closure, found `()` + --> $DIR/const-host-effect-hrtb-no-ice.rs:9:21 + | +LL | with_positive::<()>(); + | ^^ expected an `Fn(&'a ())` closure, found `()` + | + = help: the trait `for<'a> Fn(&'a ())` is not implemented for `()` +note: required by a bound in `with_positive` + --> $DIR/const-host-effect-hrtb-no-ice.rs:6:27 + | +LL | const fn with_positive [const] Fn(&'a ())>() {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `with_positive` + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0277`. diff --git a/tests/ui/transmute/raw-ptr-non-null.rs b/tests/ui/transmute/raw-ptr-non-null.rs new file mode 100644 index 000000000000..af518095b3fb --- /dev/null +++ b/tests/ui/transmute/raw-ptr-non-null.rs @@ -0,0 +1,11 @@ +//! After the use of pattern types inside `NonNull`, +//! transmuting between a niche optimized enum wrapping a +//! generic `NonNull` and raw pointers stopped working. +//@ check-pass + +use std::ptr::NonNull; +pub const fn is_null<'a, T: ?Sized>(ptr: *const T) -> bool { + unsafe { matches!(core::mem::transmute::<*const T, Option>>(ptr), None) } +} + +fn main() {} diff --git a/tests/ui/try-trait/try-operator-custom.rs b/tests/ui/try-trait/try-operator-custom.rs index ebeb0869f988..e52a07ef4bc3 100644 --- a/tests/ui/try-trait/try-operator-custom.rs +++ b/tests/ui/try-trait/try-operator-custom.rs @@ -1,12 +1,13 @@ //@ run-pass #![feature(try_trait_v2)] +#![feature(try_trait_v2_residual)] -use std::ops::{ControlFlow, FromResidual, Try}; +use std::ops::{ControlFlow, FromResidual, Residual, Try}; enum MyResult { Awesome(T), - Terrible(U) + Terrible(U), } enum Never {} @@ -27,7 +28,10 @@ fn branch(self) -> ControlFlow { } } -impl FromResidual> for MyResult where V: Into { +impl FromResidual> for MyResult +where + V: Into, +{ fn from_residual(x: MyResult) -> Self { match x { MyResult::Terrible(e) => MyResult::Terrible(e.into()), @@ -35,9 +39,16 @@ fn from_residual(x: MyResult) -> Self { } } +impl Residual for MyResult { + type TryType = MyResult; +} + type ResultResidual = Result; -impl FromResidual> for MyResult where V: Into { +impl FromResidual> for MyResult +where + V: Into, +{ fn from_residual(x: ResultResidual) -> Self { match x { Err(e) => MyResult::Terrible(e.into()), @@ -45,7 +56,10 @@ fn from_residual(x: ResultResidual) -> Self { } } -impl FromResidual> for Result where V: Into { +impl FromResidual> for Result +where + V: Into, +{ fn from_residual(x: MyResult) -> Self { match x { MyResult::Terrible(e) => Err(e.into()), diff --git a/tests/ui/type-alias-impl-trait/precise-capture-155151.current.stderr b/tests/ui/type-alias-impl-trait/precise-capture-155151.current.stderr new file mode 100644 index 000000000000..972bf142db67 --- /dev/null +++ b/tests/ui/type-alias-impl-trait/precise-capture-155151.current.stderr @@ -0,0 +1,12 @@ +error[E0381]: used binding `x` isn't initialized + --> $DIR/precise-capture-155151.rs:20:18 + | +LL | let Foo { x } = foo; + | - binding declared here but left uninitialized +... +LL | let _y = x; + | ^ `x` used here but it isn't initialized + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0381`. diff --git a/tests/ui/type-alias-impl-trait/precise-capture-155151.rs b/tests/ui/type-alias-impl-trait/precise-capture-155151.rs new file mode 100644 index 000000000000..b470c9373e93 --- /dev/null +++ b/tests/ui/type-alias-impl-trait/precise-capture-155151.rs @@ -0,0 +1,22 @@ +#![feature(type_alias_impl_trait)] +//@ revisions: current next +//@ edition: 2021 +//@[current] known-bug: #155151 +//@[current] check-fail +//@[next] compile-flags: -Znext-solver +//@[next] check-pass + +fn main() { + struct Foo { x: u32 } + + type T = impl Sized; + // `foo` has an opaque type, but this function knows that it's `Foo`. + let foo: T = Foo { x: 7 }; + + let _closure = move || { + let Foo { x } = foo; + // `x` should have been captured, but under old-solver the compiler + // thinks it's uninitialized here. + let _y = x; + }; +} diff --git a/tests/ui/type/pattern_types/non_null.rs b/tests/ui/type/pattern_types/non_null.rs index 7e86b8b684d1..e3c634da48b8 100644 --- a/tests/ui/type/pattern_types/non_null.rs +++ b/tests/ui/type/pattern_types/non_null.rs @@ -7,13 +7,13 @@ use std::pat::pattern_type; -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type NonNull = pattern_type!(*const T is !null); //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type Test = Option>; //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type Wide = pattern_type!(*const [u8] is !null); //~ ERROR layout_of const _: () = assert!(size_of::>() == size_of::>>()); diff --git a/tests/ui/type/pattern_types/or_patterns.rs b/tests/ui/type/pattern_types/or_patterns.rs index 25cb1867047a..881c3bd1b65d 100644 --- a/tests/ui/type/pattern_types/or_patterns.rs +++ b/tests/ui/type/pattern_types/or_patterns.rs @@ -13,11 +13,11 @@ use std::pat::pattern_type; -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type NonNullI8 = pattern_type!(i8 is ..0 | 1..); //~^ ERROR: layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type NonNegOneI8 = pattern_type!(i8 is ..-1 | 0..); //~^ ERROR: layout_of diff --git a/tests/ui/type/pattern_types/range_patterns.rs b/tests/ui/type/pattern_types/range_patterns.rs index 86b618a8d243..2f31c1d85296 100644 --- a/tests/ui/type/pattern_types/range_patterns.rs +++ b/tests/ui/type/pattern_types/range_patterns.rs @@ -7,34 +7,34 @@ use std::pat::pattern_type; -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type X = std::num::NonZeroU32; //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type Y = pattern_type!(u32 is 1..); //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type Z = Option; //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type A = Option; //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] struct NonZeroU32New(pattern_type!(u32 is 1..)); //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type EMPTY = pattern_type!(u32 is 1..1); //~ ERROR unknown layout -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type WRAP = pattern_type!(u32 is 1..0); //~ ERROR unknown layout //~^ ERROR: evaluation panicked: exclusive range end at minimum value of type -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type WRAP2 = pattern_type!(u32 is 5..2); //~ ERROR unknown layout -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type SIGN = pattern_type!(i8 is -10..=10); //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type MIN = pattern_type!(i8 is -128..=0); //~ ERROR layout_of -#[rustc_layout(debug)] +#[rustc_dump_layout(debug)] type SignedWrap = pattern_type!(i8 is 120..=-120); //~ ERROR unknown layout fn main() { diff --git a/tests/ui/typeck/for-in-const-eval.rs b/tests/ui/typeck/for-in-const-eval.rs index 8de969e3eee0..f187a9ef3077 100644 --- a/tests/ui/typeck/for-in-const-eval.rs +++ b/tests/ui/typeck/for-in-const-eval.rs @@ -2,6 +2,4 @@ fn main() { Vec::<[(); 1 + for x in 0..1 {}]>::new(); //~^ ERROR cannot add - //~| ERROR const Iterator` is not satisfied - //~| ERROR const Iterator` is not satisfied } diff --git a/tests/ui/typeck/for-in-const-eval.stderr b/tests/ui/typeck/for-in-const-eval.stderr index 343da0f25ecd..e7a255849581 100644 --- a/tests/ui/typeck/for-in-const-eval.stderr +++ b/tests/ui/typeck/for-in-const-eval.stderr @@ -1,22 +1,3 @@ -error[E0277]: the trait bound `std::ops::Range<{integer}>: const Iterator` is not satisfied - --> $DIR/for-in-const-eval.rs:3:29 - | -LL | Vec::<[(); 1 + for x in 0..1 {}]>::new(); - | ^^^^ required by a bound introduced by this call - | -note: trait `Iterator` is implemented but not `const` - --> $SRC_DIR/core/src/iter/range.rs:LL:COL - = note: required for `std::ops::Range<{integer}>` to implement `const IntoIterator` - -error[E0277]: the trait bound `std::ops::Range<{integer}>: const Iterator` is not satisfied - --> $DIR/for-in-const-eval.rs:3:29 - | -LL | Vec::<[(); 1 + for x in 0..1 {}]>::new(); - | ^^^^ - | -note: trait `Iterator` is implemented but not `const` - --> $SRC_DIR/core/src/iter/range.rs:LL:COL - error[E0277]: cannot add `()` to `{integer}` --> $DIR/for-in-const-eval.rs:3:18 | @@ -35,6 +16,6 @@ LL | Vec::<[(); 1 + for x in 0..1 {}]>::new(); `&f64` implements `Add` and 56 others -error: aborting due to 3 previous errors +error: aborting due to 1 previous error For more information about this error, try `rustc --explain E0277`. diff --git a/tests/ui/typeck/ice-unexpected-region-123863.stderr b/tests/ui/typeck/ice-unexpected-region-123863.stderr index e5050b4d3167..c529fe750890 100644 --- a/tests/ui/typeck/ice-unexpected-region-123863.stderr +++ b/tests/ui/typeck/ice-unexpected-region-123863.stderr @@ -5,9 +5,9 @@ LL | const fn concat_strs() -> &'static str { | ^^^^^^^^^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | help: add `#![feature(unsized_const_params)]` to the crate attributes to enable references to implement the `ConstParamTy` trait | @@ -21,9 +21,9 @@ LL | struct Inner; | ^^^^^^^^^^^^ | = note: the only supported types are integers, `bool`, and `char` -help: add `#![feature(adt_const_params)]` to the crate attributes to enable more complex and user defined types +help: add `#![feature(min_adt_const_params)]` to the crate attributes to enable more complex and user defined types | -LL + #![feature(adt_const_params)] +LL + #![feature(min_adt_const_params)] | help: add `#![feature(unsized_const_params)]` to the crate attributes to enable references to implement the `ConstParamTy` trait | diff --git a/tests/ui/typeck/main-termination-lifetime-issue-148421.rs b/tests/ui/typeck/main-termination-lifetime-issue-148421.rs new file mode 100644 index 000000000000..ce8a36cc2932 --- /dev/null +++ b/tests/ui/typeck/main-termination-lifetime-issue-148421.rs @@ -0,0 +1,17 @@ +// This test checks that the compiler correctly handles lifetime requirements +// on the `Termination` trait for the `main` function return type. +// See https://github.com/rust-lang/rust/issues/148421 + +use std::process::ExitCode; +use std::process::Termination; + +trait IsStatic {} +impl<'a: 'static> IsStatic for &'a () {} + +struct Thing; + +impl Termination for Thing where for<'a> &'a (): IsStatic { + fn report(self) -> ExitCode { panic!() } +} + +fn main() -> Thing { Thing } //~ ERROR implementation of `IsStatic` is not general enough diff --git a/tests/ui/typeck/main-termination-lifetime-issue-148421.stderr b/tests/ui/typeck/main-termination-lifetime-issue-148421.stderr new file mode 100644 index 000000000000..f0bb77cfe4c8 --- /dev/null +++ b/tests/ui/typeck/main-termination-lifetime-issue-148421.stderr @@ -0,0 +1,11 @@ +error: implementation of `IsStatic` is not general enough + --> $DIR/main-termination-lifetime-issue-148421.rs:17:14 + | +LL | fn main() -> Thing { Thing } + | ^^^^^ implementation of `IsStatic` is not general enough + | + = note: `IsStatic` would have to be implemented for the type `&'0 ()`, for any lifetime `'0`... + = note: ...but `IsStatic` is actually implemented for the type `&'1 ()`, for some specific lifetime `'1` + +error: aborting due to 1 previous error + diff --git a/tests/ui/typeck/typeck_type_placeholder_item.rs b/tests/ui/typeck/typeck_type_placeholder_item.rs index fa140b25cd1f..7616e391a35a 100644 --- a/tests/ui/typeck/typeck_type_placeholder_item.rs +++ b/tests/ui/typeck/typeck_type_placeholder_item.rs @@ -239,5 +239,5 @@ fn evens_squared(n: usize) -> _ { const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); //~^ ERROR the placeholder -//~| ERROR the trait bound `std::ops::Range<{integer}>: const Iterator` is not satisfied -//~| ERROR the trait bound `Filter +//~| ERROR cannot call +//~| ERROR cannot call diff --git a/tests/ui/typeck/typeck_type_placeholder_item.stderr b/tests/ui/typeck/typeck_type_placeholder_item.stderr index c144651c3c00..2772d55f953a 100644 --- a/tests/ui/typeck/typeck_type_placeholder_item.stderr +++ b/tests/ui/typeck/typeck_type_placeholder_item.stderr @@ -587,29 +587,17 @@ LL - fn evens_squared(n: usize) -> _ { LL + fn evens_squared(n: usize) -> impl Iterator { | -error[E0277]: the trait bound `std::ops::Range<{integer}>: const Iterator` is not satisfied - --> $DIR/typeck_type_placeholder_item.rs:240:15 - | -LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); - | ^^^^^ ------ required by a bound introduced by this call - | -note: trait `Iterator` is implemented but not `const` - --> $SRC_DIR/core/src/iter/range.rs:LL:COL - -error[E0277]: the trait bound `Filter, {closure@$DIR/typeck_type_placeholder_item.rs:240:29: 240:32}>: const Iterator` is not satisfied - --> $DIR/typeck_type_placeholder_item.rs:240:45 - | -LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); - | ^^^ - | -note: trait `Iterator` is implemented but not `const` - --> $SRC_DIR/core/src/iter/adapters/filter.rs:LL:COL - error[E0121]: the placeholder `_` is not allowed within types on item signatures for constants --> $DIR/typeck_type_placeholder_item.rs:240:10 | LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); | ^ not allowed in type signatures + | +note: however, the inferred type `Map, {closure@typeck_type_placeholder_item.rs:240:29}>, {closure@typeck_type_placeholder_item.rs:240:49}>` cannot be named + --> $DIR/typeck_type_placeholder_item.rs:240:14 + | +LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ error[E0121]: the placeholder `_` is not allowed within types on item signatures for return types --> $DIR/typeck_type_placeholder_item.rs:40:24 @@ -690,7 +678,23 @@ LL | fn map(_: fn() -> Option<&'static T>) -> Option { | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ = note: calls in constants are limited to constant functions, tuple structs and tuple variants +error[E0015]: cannot call non-const method ` as Iterator>::filter::<{closure@$DIR/typeck_type_placeholder_item.rs:240:29: 240:32}>` in constants + --> $DIR/typeck_type_placeholder_item.rs:240:22 + | +LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); + | ^^^^^^^^^^^^^^^^^^^^^^ + | + = note: calls in constants are limited to constant functions, tuple structs and tuple variants + +error[E0015]: cannot call non-const method `, {closure@$DIR/typeck_type_placeholder_item.rs:240:29: 240:32}> as Iterator>::map::` in constants + --> $DIR/typeck_type_placeholder_item.rs:240:45 + | +LL | const _: _ = (1..10).filter(|x| x % 2 == 0).map(|x| x * x); + | ^^^^^^^^^^^^^^ + | + = note: calls in constants are limited to constant functions, tuple structs and tuple variants + error: aborting due to 83 previous errors -Some errors have detailed explanations: E0015, E0046, E0121, E0277, E0282, E0403. +Some errors have detailed explanations: E0015, E0046, E0121, E0282, E0403. For more information about an error, try `rustc --explain E0015`. diff --git a/tests/ui/unpretty/exhaustive.hir.stdout b/tests/ui/unpretty/exhaustive.hir.stdout index 8265563787c8..78403e1704dc 100644 --- a/tests/ui/unpretty/exhaustive.hir.stdout +++ b/tests/ui/unpretty/exhaustive.hir.stdout @@ -1,14 +1,3 @@ -#![attr = Feature([auto_traits#0, box_patterns#0, builtin_syntax#0, -const_trait_impl#0, coroutines#0, decl_macro#0, deref_patterns#0, -explicit_tail_calls#0, gen_blocks#0, more_qualified_paths#0, never_patterns#0, -never_type#0, pattern_types#0, pattern_type_macro#0, prelude_import#0, -specialization#0, trace_macros#0, trait_alias#0, try_blocks#0, -try_blocks_heterogeneous#0, yeet_expr#0])] -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [incomplete_features]}])] -extern crate std; -#[attr = PreludeImport] -use std::prelude::rust_2024::*; //@ revisions: expanded hir //@[expanded]compile-flags: -Zunpretty=expanded //@[expanded]check-pass @@ -19,6 +8,16 @@ use std::prelude::rust_2024::*; // Note: the HIR revision includes a `.stderr` file because there are some // errors that only occur once we get past the AST. +#![allow(incomplete_features)] +#![attr = Feature([auto_traits#0, box_patterns#0, builtin_syntax#0, +const_trait_impl#0, coroutines#0, decl_macro#0, deref_patterns#0, +explicit_tail_calls#0, gen_blocks#0, more_qualified_paths#0, never_patterns#0, +never_type#0, pattern_types#0, pattern_type_macro#0, prelude_import#0, +specialization#0, trace_macros#0, trait_alias#0, try_blocks#0, +try_blocks_heterogeneous#0, yeet_expr#0])] +extern crate std; +#[attr = PreludeImport] +use std::prelude::rust_2024::*; mod prelude { use std::prelude::rust_2024::*; @@ -40,8 +39,7 @@ use self::prelude::*; * inner multi-line doc comment */ #[doc = "inner doc attribute"] -#[attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [dead_code, unused_variables]}])] +#[allow(dead_code, unused_variables)] #[attr = NoStd] mod attributes { @@ -51,9 +49,7 @@ mod attributes { */ #[doc = "outer doc attribute"] #[doc = "macro"] - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: []}])] + #[allow()] #[attr = Repr {reprs: [ReprC]}] struct Struct; } @@ -216,13 +212,9 @@ mod expressions { { } unsafe { } 'a: { } - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: []}])] + #[allow()] { } - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Inner, - lint_instances: []}])] + #[allow()] { } } @@ -252,15 +244,9 @@ mod expressions { type_ascribe!({ from_output(()) }, Option<_>); type_ascribe!({ from_output(match branch(None) { - Break { 0: residual } => - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: [unreachable_code]}])] + Break { 0: residual } => #[allow(unreachable_code)] break from_residual(residual), - Continue { 0: val } => - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: [unreachable_code]}])] + Continue { 0: val } => #[allow(unreachable_code)] val, }) }, Option) @@ -382,15 +368,9 @@ mod expressions { fn expr_try() { let expr; match branch(expr) { - Break { 0: residual } => - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: [unreachable_code]}])] + Break { 0: residual } => #[allow(unreachable_code)] return from_residual(residual), - Continue { 0: val } => - #[attr = LintAttributes([LintAttribute {kind: Allow, - attr_style: Outer, - lint_instances: [unreachable_code]}])] + Continue { 0: val } => #[allow(unreachable_code)] val, }; } diff --git a/tests/ui/unpretty/struct-exprs-tuple-call-pretty-printing.stdout b/tests/ui/unpretty/struct-exprs-tuple-call-pretty-printing.stdout index 298b9f8f9905..8c016f5083d2 100644 --- a/tests/ui/unpretty/struct-exprs-tuple-call-pretty-printing.stdout +++ b/tests/ui/unpretty/struct-exprs-tuple-call-pretty-printing.stdout @@ -1,13 +1,12 @@ -#![attr = Feature([min_generic_const_args#0, adt_const_params#0])] -#![attr = LintAttributes([LintAttribute {kind: Expect, attr_style: Inner, -lint_instances: [incomplete_features]}, LintAttribute {kind: Allow, -attr_style: Inner, lint_instances: [dead_code]}])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; //@ compile-flags: -Zunpretty=hir //@ check-pass +#![expect(incomplete_features)] +#![allow(dead_code)] +#![attr = Feature([min_generic_const_args#0, adt_const_params#0])] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; use std::marker::ConstParamTy; diff --git a/tests/ui/unpretty/unpretty-expr-fn-arg.stdout b/tests/ui/unpretty/unpretty-expr-fn-arg.stdout index 6fbdb77bfb36..19bfe92e3b27 100644 --- a/tests/ui/unpretty/unpretty-expr-fn-arg.stdout +++ b/tests/ui/unpretty/unpretty-expr-fn-arg.stdout @@ -1,8 +1,3 @@ -#![attr = LintAttributes([LintAttribute {kind: Allow, attr_style: Inner, -lint_instances: [dead_code]}])] -extern crate std; -#[attr = PreludeImport] -use ::std::prelude::rust_2015::*; // Regression test for the ICE described in #82328. The pretty-printer for // `-Zunpretty=hir,typed` would previously retrieve type-checking results // when entering a body, which means that type information was not available @@ -12,6 +7,10 @@ use ::std::prelude::rust_2015::*; //@ check-pass //@ compile-flags: -Zunpretty=hir,typed //@ edition: 2015 +#![allow(dead_code)] +extern crate std; +#[attr = PreludeImport] +use ::std::prelude::rust_2015::*; fn main() ({ } as ()) diff --git a/tests/ui/use/pub-use-self-super-crate.rs b/tests/ui/use/pub-use-self-super-crate.rs index 1a799acb50fb..2adb995cf2f3 100644 --- a/tests/ui/use/pub-use-self-super-crate.rs +++ b/tests/ui/use/pub-use-self-super-crate.rs @@ -8,7 +8,7 @@ pub mod bar { pub use self::super as parent2; //~^ ERROR `super` is only public within the crate, and cannot be re-exported outside pub use super::{self as parent3}; - //~^ ERROR `super` is only public within the crate, and cannot be re-exported outside + //~^ ERROR `self` is only public within the crate, and cannot be re-exported outside pub use self::{super as parent4}; //~^ ERROR `super` is only public within the crate, and cannot be re-exported outside diff --git a/tests/ui/use/pub-use-self-super-crate.stderr b/tests/ui/use/pub-use-self-super-crate.stderr index 3b336800a180..0f9c87b93a09 100644 --- a/tests/ui/use/pub-use-self-super-crate.stderr +++ b/tests/ui/use/pub-use-self-super-crate.stderr @@ -22,13 +22,13 @@ LL | pub use self::super as parent2; | = note: consider declaring type or module `super` with `pub` -error[E0365]: `super` is only public within the crate, and cannot be re-exported outside +error[E0365]: `self` is only public within the crate, and cannot be re-exported outside --> $DIR/pub-use-self-super-crate.rs:10:25 | LL | pub use super::{self as parent3}; - | ^^^^^^^^^^^^^^^ re-export of crate public `super` + | ^^^^^^^^^^^^^^^ re-export of crate public `self` | - = note: consider declaring type or module `super` with `pub` + = note: consider declaring type or module `self` with `pub` error[E0365]: `super` is only public within the crate, and cannot be re-exported outside --> $DIR/pub-use-self-super-crate.rs:12:24 diff --git a/tests/ui/use/use-mod/use-mod-4.stderr b/tests/ui/use/use-mod/use-mod-4.stderr index d4621296c0d1..03284298c16f 100644 --- a/tests/ui/use/use-mod/use-mod-4.stderr +++ b/tests/ui/use/use-mod/use-mod-4.stderr @@ -31,10 +31,15 @@ LL | use std::mem::{self}; | + + error[E0432]: unresolved import `crate::foo` - --> $DIR/use-mod-4.rs:1:5 + --> $DIR/use-mod-4.rs:1:12 | LL | use crate::foo::self; - | ^^^^^^^^^^^^^^^^ no `foo` in the root + | ^^^ use of unresolved module or unlinked crate `foo` + | +help: you might be missing a crate named `foo`, add it to your project and import it in your code + | +LL + extern crate foo; + | error: aborting due to 3 previous errors diff --git a/tests/ui/use/use-path-segment-kw.e2015.stderr b/tests/ui/use/use-path-segment-kw.e2015.stderr index 908e739ec520..dce3071f789b 100644 --- a/tests/ui/use/use-path-segment-kw.e2015.stderr +++ b/tests/ui/use/use-path-segment-kw.e2015.stderr @@ -935,39 +935,49 @@ help: try renaming it with a name LL | use $crate::{self as name}; | +++++++ -error[E0432]: unresolved import `foobar` +error[E0433]: cannot find module or crate `foobar` in the crate root --> $DIR/use-path-segment-kw.rs:187:17 | LL | pub use foobar::qux::self; - | ^^^^^^ + | ^^^^^^ use of unresolved module or unlinked crate `foobar` | -help: a similar path exists +help: you might be missing a crate named `foobar`, add it to your project and import it in your code + | +LL + extern crate foobar; + | + +error[E0433]: cannot find module or crate `foobar` in the crate root + --> $DIR/use-path-segment-kw.rs:191:17 + | +LL | pub use foobar::baz::{self}; + | ^^^^^^ use of unresolved module or unlinked crate `foobar` + | +help: you might be missing a crate named `foobar`, add it to your project and import it in your code + | +LL + extern crate foobar; | -LL | pub use self::foobar::qux::self; - | ++++++ error[E0432]: unresolved import `foobar` --> $DIR/use-path-segment-kw.rs:189:17 | LL | pub use foobar::self as _self3; - | ^^^^^^^^^^^^^^^^^^^^^^ no `foobar` in the root - -error[E0432]: unresolved import `foobar` - --> $DIR/use-path-segment-kw.rs:191:17 - | -LL | pub use foobar::baz::{self}; | ^^^^^^ | help: a similar path exists | -LL | pub use self::foobar::baz::{self}; +LL | pub use self::foobar::self as _self3; | ++++++ error[E0432]: unresolved import `foobar` - --> $DIR/use-path-segment-kw.rs:192:26 + --> $DIR/use-path-segment-kw.rs:192:17 | LL | pub use foobar::{self as _nested_self3}; - | ^^^^^^^^^^^^^^^^^^^^^ no `foobar` in the root + | ^^^^^^ + | +help: a similar path exists + | +LL | pub use self::foobar::{self as _nested_self3}; + | ++++++ error[E0433]: `self` in paths can only be used in start position --> $DIR/use-path-segment-kw.rs:215:36 diff --git a/tests/ui/use/use-path-segment-kw.rs b/tests/ui/use/use-path-segment-kw.rs index 164f645dc5c5..c9b404887e60 100644 --- a/tests/ui/use/use-path-segment-kw.rs +++ b/tests/ui/use/use-path-segment-kw.rs @@ -185,10 +185,10 @@ pub fn inner() {} type D3 = foobar::self; //~ ERROR `self` in paths can only be used in start position pub use foobar::qux::self; //~ ERROR `self` imports are only allowed within a { } list - //[e2015]~^ ERROR unresolved import `foobar` + //[e2015]~^ ERROR cannot find module or crate `foobar` in the crate root pub use foobar::self as _self3; //~ ERROR `self` imports are only allowed within a { } list //[e2015]~^ ERROR unresolved import `foobar` - pub use foobar::baz::{self}; //[e2015]~ ERROR unresolved import `foobar` + pub use foobar::baz::{self}; //[e2015]~ ERROR cannot find module or crate `foobar` in the crate root pub use foobar::{self as _nested_self3}; //[e2015]~ ERROR unresolved import `foobar` type D4 = crate::self; //~ ERROR `self` in paths can only be used in start position diff --git a/tests/ui/use/use-self-at-end.e2015.stderr b/tests/ui/use/use-self-at-end.e2015.stderr new file mode 100644 index 000000000000..a7e458831feb --- /dev/null +++ b/tests/ui/use/use-self-at-end.e2015.stderr @@ -0,0 +1,528 @@ +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:14:22 + | +LL | pub use crate::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::self; +LL + pub use crate; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:14:24 + | +LL | pub use crate::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:16:22 + | +LL | pub use crate::self as crate1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::self as crate1; +LL + pub use crate as crate1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::{self as crate1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:17:25 + | +LL | pub use crate::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use crate::{self as name}; + | +++++++ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:21:17 + | +LL | pub use self; + | ^^^^ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:23:18 + | +LL | pub use {self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use {self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:27:21 + | +LL | pub use self::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use self::self; +LL + pub use self; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use self::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:27:23 + | +LL | pub use self::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:29:21 + | +LL | pub use self::self as self3; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use self::self as self3; +LL + pub use self as self3; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use self::{self as self3}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:30:24 + | +LL | pub use self::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use self::{self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:34:22 + | +LL | pub use super::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::self; +LL + pub use super; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:34:24 + | +LL | pub use super::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:36:22 + | +LL | pub use super::self as super1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::self as super1; +LL + pub use super as super1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::{self as super1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:37:25 + | +LL | pub use super::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use super::{self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:41:25 + | +LL | pub use crate::x::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::x::self; +LL + pub use crate::x; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::x::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:42:25 + | +LL | pub use crate::x::self as x3; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::x::self as x3; +LL + pub use crate::x as x3; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::x::{self as x3}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:47:17 + | +LL | pub use ::self; + | ^^^^^^ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:47:19 + | +LL | pub use ::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:50:17 + | +LL | pub use ::self as crate4; + | ^^^^^^ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:52:20 + | +LL | pub use ::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use ::{self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:57:24 + | +LL | pub use z::self::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use z::self::self; +LL + pub use z::self; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use z::self::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:57:26 + | +LL | pub use z::self::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:59:24 + | +LL | pub use z::self::self as z1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use z::self::self as z1; +LL + pub use z::self as z1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use z::self::{self as z1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:61:28 + | +LL | pub use z::{self::{self}}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use z::{self::{self as name}}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:65:30 + | +LL | pub use super::Struct::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Struct::self; +LL + pub use super::Struct; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Struct::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:67:30 + | +LL | pub use super::Struct::self as Struct1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Struct::self as Struct1; +LL + pub use super::Struct as Struct1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Struct::{self as Struct1}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:73:28 + | +LL | pub use super::Enum::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Enum::self; +LL + pub use super::Enum; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Enum::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:74:28 + | +LL | pub use super::Enum::self as Enum1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Enum::self as Enum1; +LL + pub use super::Enum as Enum1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Enum::{self as Enum1}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:79:29 + | +LL | pub use super::Trait::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Trait::self; +LL + pub use super::Trait; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Trait::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:80:29 + | +LL | pub use super::Trait::self as Trait1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Trait::self as Trait1; +LL + pub use super::Trait as Trait1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Trait::{self as Trait1}; + | + + + +error[E0252]: the name `x` is defined multiple times + --> $DIR/use-self-at-end.rs:43:28 + | +LL | pub use crate::x::self; + | -------------- previous import of the module `x` here +LL | pub use crate::x::self as x3; +LL | pub use crate::x::{self}; + | -------------------^^^^-- + | | | + | | `x` reimported here + | help: remove unnecessary import + | + = note: `x` must be defined only once in the type namespace of this module + +error[E0252]: the name `Enum` is defined multiple times + --> $DIR/use-self-at-end.rs:75:31 + | +LL | pub use super::Enum::self; + | ----------------- previous import of the type `Enum` here +LL | pub use super::Enum::self as Enum1; +LL | pub use super::Enum::{self}; + | ----------------------^^^^-- + | | | + | | `Enum` reimported here + | help: remove unnecessary import + | + = note: `Enum` must be defined only once in the type namespace of this module + +error[E0252]: the name `Trait` is defined multiple times + --> $DIR/use-self-at-end.rs:81:32 + | +LL | pub use super::Trait::self; + | ------------------ previous import of the trait `Trait` here +LL | pub use super::Trait::self as Trait1; +LL | pub use super::Trait::{self}; + | -----------------------^^^^-- + | | | + | | `Trait` reimported here + | help: remove unnecessary import + | + = note: `Trait` must be defined only once in the type namespace of this module + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:59:20 + | +LL | pub use z::self::self as z1; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:62:21 + | +LL | pub use z::{self::{self as z2}}; + | ^^^^ can only be used in path start position + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:65:24 + | +LL | pub use super::Struct::self; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:67:24 + | +LL | pub use super::Struct::self as Struct1; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:69:24 + | +LL | pub use super::Struct::{self}; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:70:24 + | +LL | pub use super::Struct::{self as Struct2}; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:56:21 + | +LL | type G = z::self::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:72:31 + | +LL | type I = super::Enum::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:78:32 + | +LL | type J = super::Trait::self; + | ^^^^ can only be used in path start position + +error[E0573]: expected type, found module `self` + --> $DIR/use-self-at-end.rs:20:18 + | +LL | type B = self; + | ^^^^ not a type + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:40:28 + | +LL | type E = crate::x::self; + | ^^^^ can only be used in path start position + | +help: consider importing this module + | +LL + use x; + | +help: if you import `x`, refer to it directly + | +LL - type E = crate::x::self; +LL + type E = x::self; + | + +error[E0223]: ambiguous associated type + --> $DIR/use-self-at-end.rs:64:18 + | +LL | type H = super::Struct::self; + | ^^^^^^^^^^^^^^^^^^^ + | +help: if there were a trait named `Example` with associated type `self` implemented for `x::Struct`, you could use the fully-qualified path + | +LL - type H = super::Struct::self; +LL + type H = ::self; + | + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:13:25 + | +LL | type A = crate::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:26:24 + | +LL | type C = self::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:33:25 + | +LL | type D = super::self; + | ^^^^ can only be used in path start position + +error[E0433]: global paths cannot start with `self` + --> $DIR/use-self-at-end.rs:46:20 + | +LL | type F = ::self; + | ^^^^ cannot start with this + +error: aborting due to 49 previous errors + +Some errors have detailed explanations: E0223, E0252, E0429, E0432, E0433, E0573. +For more information about an error, try `rustc --explain E0223`. diff --git a/tests/ui/use/use-self-at-end.e2018.stderr b/tests/ui/use/use-self-at-end.e2018.stderr new file mode 100644 index 000000000000..5d56f4058069 --- /dev/null +++ b/tests/ui/use/use-self-at-end.e2018.stderr @@ -0,0 +1,523 @@ +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:14:22 + | +LL | pub use crate::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::self; +LL + pub use crate; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:14:24 + | +LL | pub use crate::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:16:22 + | +LL | pub use crate::self as crate1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::self as crate1; +LL + pub use crate as crate1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::{self as crate1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:17:25 + | +LL | pub use crate::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use crate::{self as name}; + | +++++++ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:21:17 + | +LL | pub use self; + | ^^^^ + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:23:18 + | +LL | pub use {self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use {self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:27:21 + | +LL | pub use self::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use self::self; +LL + pub use self; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use self::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:27:23 + | +LL | pub use self::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:29:21 + | +LL | pub use self::self as self3; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use self::self as self3; +LL + pub use self as self3; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use self::{self as self3}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:30:24 + | +LL | pub use self::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use self::{self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:34:22 + | +LL | pub use super::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::self; +LL + pub use super; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:34:24 + | +LL | pub use super::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:36:22 + | +LL | pub use super::self as super1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::self as super1; +LL + pub use super as super1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::{self as super1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:37:25 + | +LL | pub use super::{self}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use super::{self as name}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:41:25 + | +LL | pub use crate::x::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::x::self; +LL + pub use crate::x; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::x::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:42:25 + | +LL | pub use crate::x::self as x3; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use crate::x::self as x3; +LL + pub use crate::x as x3; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use crate::x::{self as x3}; + | + + + +error: extern prelude cannot be imported + --> $DIR/use-self-at-end.rs:47:17 + | +LL | pub use ::self; + | ^^^^^^ + +error: extern prelude cannot be imported + --> $DIR/use-self-at-end.rs:50:17 + | +LL | pub use ::self as crate4; + | ^^^^^^^^^^^^^^^^ + +error: extern prelude cannot be imported + --> $DIR/use-self-at-end.rs:52:20 + | +LL | pub use ::{self}; + | ^^^^ + +error: extern prelude cannot be imported + --> $DIR/use-self-at-end.rs:54:20 + | +LL | pub use ::{self as crate5}; + | ^^^^^^^^^^^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:57:24 + | +LL | pub use z::self::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use z::self::self; +LL + pub use z::self; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use z::self::{self}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:57:26 + | +LL | pub use z::self::self; + | ^^^^ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:59:24 + | +LL | pub use z::self::self as z1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use z::self::self as z1; +LL + pub use z::self as z1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use z::self::{self as z1}; + | + + + +error: imports need to be explicitly named + --> $DIR/use-self-at-end.rs:61:28 + | +LL | pub use z::{self::{self}}; + | ^^^^ + | +help: try renaming it with a name + | +LL | pub use z::{self::{self as name}}; + | +++++++ + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:65:30 + | +LL | pub use super::Struct::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Struct::self; +LL + pub use super::Struct; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Struct::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:67:30 + | +LL | pub use super::Struct::self as Struct1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Struct::self as Struct1; +LL + pub use super::Struct as Struct1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Struct::{self as Struct1}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:73:28 + | +LL | pub use super::Enum::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Enum::self; +LL + pub use super::Enum; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Enum::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:74:28 + | +LL | pub use super::Enum::self as Enum1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Enum::self as Enum1; +LL + pub use super::Enum as Enum1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Enum::{self as Enum1}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:79:29 + | +LL | pub use super::Trait::self; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Trait::self; +LL + pub use super::Trait; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Trait::{self}; + | + + + +error[E0429]: `self` imports are only allowed within a { } list + --> $DIR/use-self-at-end.rs:80:29 + | +LL | pub use super::Trait::self as Trait1; + | ^^^^^^ + | +help: consider importing the module directly + | +LL - pub use super::Trait::self as Trait1; +LL + pub use super::Trait as Trait1; + | +help: alternatively, use the multi-path `use` syntax to import `self` + | +LL | pub use super::Trait::{self as Trait1}; + | + + + +error[E0252]: the name `x` is defined multiple times + --> $DIR/use-self-at-end.rs:43:28 + | +LL | pub use crate::x::self; + | -------------- previous import of the module `x` here +LL | pub use crate::x::self as x3; +LL | pub use crate::x::{self}; + | -------------------^^^^-- + | | | + | | `x` reimported here + | help: remove unnecessary import + | + = note: `x` must be defined only once in the type namespace of this module + +error[E0252]: the name `Enum` is defined multiple times + --> $DIR/use-self-at-end.rs:75:31 + | +LL | pub use super::Enum::self; + | ----------------- previous import of the type `Enum` here +LL | pub use super::Enum::self as Enum1; +LL | pub use super::Enum::{self}; + | ----------------------^^^^-- + | | | + | | `Enum` reimported here + | help: remove unnecessary import + | + = note: `Enum` must be defined only once in the type namespace of this module + +error[E0252]: the name `Trait` is defined multiple times + --> $DIR/use-self-at-end.rs:81:32 + | +LL | pub use super::Trait::self; + | ------------------ previous import of the trait `Trait` here +LL | pub use super::Trait::self as Trait1; +LL | pub use super::Trait::{self}; + | -----------------------^^^^-- + | | | + | | `Trait` reimported here + | help: remove unnecessary import + | + = note: `Trait` must be defined only once in the type namespace of this module + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:59:20 + | +LL | pub use z::self::self as z1; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:62:21 + | +LL | pub use z::{self::{self as z2}}; + | ^^^^ can only be used in path start position + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:65:24 + | +LL | pub use super::Struct::self; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:67:24 + | +LL | pub use super::Struct::self as Struct1; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:69:24 + | +LL | pub use super::Struct::{self}; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0432]: unresolved import `super::Struct` + --> $DIR/use-self-at-end.rs:70:24 + | +LL | pub use super::Struct::{self as Struct2}; + | ^^^^^^ `Struct` is a struct, not a module + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:56:21 + | +LL | type G = z::self::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:72:31 + | +LL | type I = super::Enum::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:78:32 + | +LL | type J = super::Trait::self; + | ^^^^ can only be used in path start position + +error[E0573]: expected type, found module `self` + --> $DIR/use-self-at-end.rs:20:18 + | +LL | type B = self; + | ^^^^ not a type + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:40:28 + | +LL | type E = crate::x::self; + | ^^^^ can only be used in path start position + | +help: consider importing this module + | +LL + use crate::x; + | +help: if you import `x`, refer to it directly + | +LL - type E = crate::x::self; +LL + type E = x::self; + | + +error[E0223]: ambiguous associated type + --> $DIR/use-self-at-end.rs:64:18 + | +LL | type H = super::Struct::self; + | ^^^^^^^^^^^^^^^^^^^ + | +help: if there were a trait named `Example` with associated type `self` implemented for `x::Struct`, you could use the fully-qualified path + | +LL - type H = super::Struct::self; +LL + type H = ::self; + | + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:13:25 + | +LL | type A = crate::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:26:24 + | +LL | type C = self::self; + | ^^^^ can only be used in path start position + +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-self-at-end.rs:33:25 + | +LL | type D = super::self; + | ^^^^ can only be used in path start position + +error[E0433]: global paths cannot start with `self` + --> $DIR/use-self-at-end.rs:46:20 + | +LL | type F = ::self; + | ^^^^ cannot start with this + +error: aborting due to 49 previous errors + +Some errors have detailed explanations: E0223, E0252, E0429, E0432, E0433, E0573. +For more information about an error, try `rustc --explain E0223`. diff --git a/tests/ui/use/use-self-at-end.rs b/tests/ui/use/use-self-at-end.rs new file mode 100644 index 000000000000..84337dc9e503 --- /dev/null +++ b/tests/ui/use/use-self-at-end.rs @@ -0,0 +1,88 @@ +//@ revisions: e2015 e2018 +//@ [e2015] edition: 2015 +//@ [e2018] edition: 2018.. + +pub mod x { + pub struct Struct; + pub enum Enum {} + pub trait Trait {} + + pub mod y { + pub mod z {} + + type A = crate::self; //~ ERROR `self` in paths can only be used in start position + pub use crate::self; //~ ERROR `self` imports are only allowed within a { } list + //~^ ERROR imports need to be explicitly named + pub use crate::self as crate1; //~ ERROR `self` imports are only allowed within a { } list + pub use crate::{self}; //~ ERROR imports need to be explicitly named + pub use crate::{self as crate2}; + + type B = self; //~ ERROR expected type, found module `self` + pub use self; //~ ERROR imports need to be explicitly named + pub use self as self1; + pub use {self}; //~ ERROR imports need to be explicitly named + pub use {self as self2}; + + type C = self::self; //~ ERROR `self` in paths can only be used in start position + pub use self::self; //~ ERROR `self` imports are only allowed within a { } list + //~^ ERROR imports need to be explicitly named + pub use self::self as self3; //~ ERROR `self` imports are only allowed within a { } list + pub use self::{self}; //~ ERROR imports need to be explicitly named + pub use self::{self as self4}; + + type D = super::self; //~ ERROR `self` in paths can only be used in start position + pub use super::self; //~ ERROR `self` imports are only allowed within a { } list + //~^ ERROR imports need to be explicitly named + pub use super::self as super1; //~ ERROR `self` imports are only allowed within a { } list + pub use super::{self}; //~ ERROR imports need to be explicitly named + pub use super::{self as super2}; + + type E = crate::x::self; //~ ERROR `self` in paths can only be used in start position + pub use crate::x::self; //~ ERROR `self` imports are only allowed within a { } list + pub use crate::x::self as x3; //~ ERROR `self` imports are only allowed within a { } list + pub use crate::x::{self}; //~ ERROR the name `x` is defined multiple times + pub use crate::x::{self as x4}; + + type F = ::self; //~ ERROR global paths cannot start with `self` + pub use ::self; //[e2018]~ ERROR extern prelude cannot be imported + //[e2015]~^ ERROR imports need to be explicitly named + //[e2015]~^^ ERROR `self` imports are only allowed within a { } list + pub use ::self as crate4; //[e2018]~ ERROR extern prelude cannot be imported + //[e2015]~^ ERROR `self` imports are only allowed within a { } list + pub use ::{self}; //[e2018]~ ERROR extern prelude cannot be imported + //[e2015]~^ ERROR imports need to be explicitly named + pub use ::{self as crate5}; //[e2018]~ ERROR extern prelude cannot be imported + + type G = z::self::self; //~ ERROR `self` in paths can only be used in start position + pub use z::self::self; //~ ERROR imports need to be explicitly named + //~^ ERROR `self` imports are only allowed within a { } list + pub use z::self::self as z1; //~ ERROR `self` in paths can only be used in start position + //~^ ERROR `self` imports are only allowed within a { } list + pub use z::{self::{self}}; //~ ERROR imports need to be explicitly named + pub use z::{self::{self as z2}}; //~ ERROR `self` in paths can only be used in start position + + type H = super::Struct::self; //~ ERROR ambiguous associated type + pub use super::Struct::self; //~ ERROR unresolved import `super::Struct` + //~^ ERROR `self` imports are only allowed within a { } list + pub use super::Struct::self as Struct1; //~ ERROR unresolved import `super::Struct` + //~^ ERROR `self` imports are only allowed within a { } list + pub use super::Struct::{self}; //~ ERROR unresolved import `super::Struct` + pub use super::Struct::{self as Struct2}; //~ ERROR unresolved import `super::Struct` + + type I = super::Enum::self; //~ ERROR `self` in paths can only be used in start position + pub use super::Enum::self; //~ ERROR `self` imports are only allowed within a { } list + pub use super::Enum::self as Enum1; //~ ERROR `self` imports are only allowed within a { } list + pub use super::Enum::{self}; //~ ERROR the name `Enum` is defined multiple times + pub use super::Enum::{self as Enum2}; + + type J = super::Trait::self; //~ ERROR `self` in paths can only be used in start position + pub use super::Trait::self; //~ ERROR `self` imports are only allowed within a { } list + pub use super::Trait::self as Trait1; //~ ERROR `self` imports are only allowed within a { } list + pub use super::Trait::{self}; //~ ERROR the name `Trait` is defined multiple times + pub use super::Trait::{self as Trait2}; + } +} + +pub mod z {} + +fn main() {} diff --git a/tests/ui/use/use-super-in-middle.rs b/tests/ui/use/use-super-in-middle.rs index be9f3675c323..2e964b09f6b7 100644 --- a/tests/ui/use/use-super-in-middle.rs +++ b/tests/ui/use/use-super-in-middle.rs @@ -1,13 +1,13 @@ pub mod x { pub use crate::x::super::{self as crate1}; //~ ERROR `super` in paths can only be used in start position - pub use crate::x::self::super::{self as crate2}; //~ ERROR `super` in paths can only be used in start position + pub use crate::x::self::super::{self as crate2}; //~ ERROR `self` in paths can only be used in start position pub fn foo() {} } fn main() { - x::crate1::x::foo(); //~ ERROR cannot find `crate1` in `x` - x::crate2::x::foo(); //~ ERROR cannot find `crate2` in `x` + x::crate1::x::foo(); + x::crate2::x::foo(); crate::x::super::x::foo(); //~ ERROR `super` in paths can only be used in start position crate::x::self::super::x::foo(); //~ ERROR `self` in paths can only be used in start position diff --git a/tests/ui/use/use-super-in-middle.stderr b/tests/ui/use/use-super-in-middle.stderr index 276b1274f6a8..af28edd48b44 100644 --- a/tests/ui/use/use-super-in-middle.stderr +++ b/tests/ui/use/use-super-in-middle.stderr @@ -1,26 +1,14 @@ -error: `super` in paths can only be used in start position, after `self`, or after another `super` +error[E0433]: `super` in paths can only be used in start position --> $DIR/use-super-in-middle.rs:2:23 | LL | pub use crate::x::super::{self as crate1}; - | ^^^^^ + | ^^^^^ can only be used in path start position -error: `super` in paths can only be used in start position, after `self`, or after another `super` - --> $DIR/use-super-in-middle.rs:3:29 +error[E0433]: `self` in paths can only be used in start position + --> $DIR/use-super-in-middle.rs:3:23 | LL | pub use crate::x::self::super::{self as crate2}; - | ^^^^^ - -error[E0433]: cannot find `crate1` in `x` - --> $DIR/use-super-in-middle.rs:9:8 - | -LL | x::crate1::x::foo(); - | ^^^^^^ could not find `crate1` in `x` - -error[E0433]: cannot find `crate2` in `x` - --> $DIR/use-super-in-middle.rs:10:8 - | -LL | x::crate2::x::foo(); - | ^^^^^^ could not find `crate2` in `x` + | ^^^^ can only be used in path start position error[E0433]: `super` in paths can only be used in start position --> $DIR/use-super-in-middle.rs:12:15 @@ -34,6 +22,6 @@ error[E0433]: `self` in paths can only be used in start position LL | crate::x::self::super::x::foo(); | ^^^^ can only be used in path start position -error: aborting due to 6 previous errors +error: aborting due to 4 previous errors For more information about this error, try `rustc --explain E0433`. diff --git a/tests/ui/where-clauses/unsupported_attribute.rs b/tests/ui/where-clauses/unsupported_attribute.rs index 7e039de1a291..e86274f3ed5e 100644 --- a/tests/ui/where-clauses/unsupported_attribute.rs +++ b/tests/ui/where-clauses/unsupported_attribute.rs @@ -18,8 +18,8 @@ fn foo<'a, T>() #[should_panic] 'a: 'static, //~ ERROR attribute cannot be used on #[macro_use] T: Trait, //~ ERROR attribute cannot be used on #[macro_use] 'a: 'static, //~ ERROR attribute cannot be used on - #[allow(unused)] T: Trait, //~ ERROR attribute cannot be used on - #[allow(unused)] 'a: 'static, //~ ERROR attribute cannot be used on + #[allow(unused)] T: Trait, //~ ERROR most attributes are not supported in `where` clauses + #[allow(unused)] 'a: 'static, //~ ERROR most attributes are not supported in `where` clauses #[deprecated] T: Trait, //~ ERROR attribute cannot be used on #[deprecated] 'a: 'static, //~ ERROR attribute cannot be used on #[automatically_derived] T: Trait, //~ ERROR attribute cannot be used on diff --git a/tests/ui/where-clauses/unsupported_attribute.stderr b/tests/ui/where-clauses/unsupported_attribute.stderr index 4ff4b4761302..11f13ffa4d00 100644 --- a/tests/ui/where-clauses/unsupported_attribute.stderr +++ b/tests/ui/where-clauses/unsupported_attribute.stderr @@ -74,21 +74,21 @@ LL | #[macro_use] 'a: 'static, | = help: `#[macro_use]` can be applied to crates, extern crates, and modules -error: `#[allow]` attribute cannot be used on where predicates +error: most attributes are not supported in `where` clauses --> $DIR/unsupported_attribute.rs:21:5 | LL | #[allow(unused)] T: Trait, | ^^^^^^^^^^^^^^^^ | - = help: `#[allow]` can be applied to associated consts, associated types, const parameters, const parameters, constants, crates, data types, enum variants, extern crates, foreign modules, foreign statics, function params, functions, global asms, impl blocks, lifetime parameters, lifetime parameters, macro defs, match arms, modules, pattern fields, statics, struct fields, struct fields, trait aliases, traits, type aliases, type parameters, type parameters, and use statements + = help: only `#[cfg]` and `#[cfg_attr]` are supported -error: `#[allow]` attribute cannot be used on where predicates +error: most attributes are not supported in `where` clauses --> $DIR/unsupported_attribute.rs:22:5 | LL | #[allow(unused)] 'a: 'static, | ^^^^^^^^^^^^^^^^ | - = help: `#[allow]` can be applied to associated consts, associated types, const parameters, const parameters, constants, crates, data types, enum variants, extern crates, foreign modules, foreign statics, function params, functions, global asms, impl blocks, lifetime parameters, lifetime parameters, macro defs, match arms, modules, pattern fields, statics, struct fields, struct fields, trait aliases, traits, type aliases, type parameters, type parameters, and use statements + = help: only `#[cfg]` and `#[cfg_attr]` are supported error: `#[deprecated]` attribute cannot be used on where predicates --> $DIR/unsupported_attribute.rs:23:5 diff --git a/triagebot.toml b/triagebot.toml index 7708bdbceffc..953ef08a9cc8 100644 --- a/triagebot.toml +++ b/triagebot.toml @@ -1451,6 +1451,12 @@ code; adding it needs t-lang approval. """ cc = ["@rust-lang/wg-const-eval"] +[mentions."compiler/rustc_attr_parsing/src/attributes/diagnostic"] +message = "Some changes occurred to diagnostic attributes." +cc = ["@mejrs"] +[mentions."compiler/rustc_hir/src/attrs/diagnostic.rs"] +message = "Some changes occurred to diagnostic attributes." +cc = ["@mejrs"] # ------------------------------------------------------------------------------ # PR assignments @@ -1479,7 +1485,6 @@ libs = [ "@jhpratt", "@tgross35", "@thomcc", - "@ibraheemdev", "@joboet", ] infra-ci = [