diff --git a/compiler/rustc_codegen_llvm/src/va_arg.rs b/compiler/rustc_codegen_llvm/src/va_arg.rs
index be1733086c83..3cd4e490fd5b 100644
--- a/compiler/rustc_codegen_llvm/src/va_arg.rs
+++ b/compiler/rustc_codegen_llvm/src/va_arg.rs
@@ -1171,14 +1171,29 @@ pub(super) fn emit_va_arg<'ll, 'tcx>(
             AllowHigherAlign::Yes,
             ForceRightAdjust::No,
         ),
+        Arch::Mips | Arch::Mips32r6 | Arch::Mips64 | Arch::Mips64r6 => emit_ptr_va_arg(
+            bx,
+            addr,
+            target_ty,
+            PassMode::Direct,
+            match &target.llvm_abiname {
+                LlvmAbi::N32 | LlvmAbi::N64 => SlotSize::Bytes8,
+                LlvmAbi::O32 => SlotSize::Bytes4,
+                other => bug!("unexpected LLVM ABI {other}"),
+            },
+            AllowHigherAlign::Yes,
+            // In big-endian mode the actual value is stored in the right side of the slot, meaning
+            // that when the value is smaller than a slot, we need to adjust the pointer we read
+            // to somewhere in the middle of the slot.
+            match bx.tcx().sess.target.endian {
+                Endian::Big => ForceRightAdjust::Yes,
+                Endian::Little => ForceRightAdjust::No,
+            },
+        ),
 
         Arch::Bpf => bug!("bpf does not support c-variadic functions"),
         Arch::SpirV => bug!("spirv does not support c-variadic functions"),
 
-        Arch::Mips | Arch::Mips32r6 | Arch::Mips64 | Arch::Mips64r6 => {
-            // FIXME: port MipsTargetLowering::lowerVAARG.
-            bx.va_arg(addr.immediate(), bx.cx.layout_of(target_ty).llvm_type(bx.cx))
-        }
         Arch::Sparc | Arch::Avr | Arch::M68k | Arch::Msp430 => {
             // Clang uses the LLVM implementation for these architectures.
             bx.va_arg(addr.immediate(), bx.cx.layout_of(target_ty).llvm_type(bx.cx))
diff --git a/tests/assembly-llvm/c-variadic-mips.rs b/tests/assembly-llvm/c-variadic-mips.rs
index e619babeb091..9c74eeb8a6a1 100644
--- a/tests/assembly-llvm/c-variadic-mips.rs
+++ b/tests/assembly-llvm/c-variadic-mips.rs
@@ -3,9 +3,11 @@
 //
 //@ revisions: MIPS MIPS64 MIPS64EL
 //@ [MIPS] compile-flags: -Copt-level=3 --target mips-unknown-linux-gnu
+//@ [MIPS] needs-llvm-components: mips
 //@ [MIPS64] compile-flags: -Copt-level=3 --target mipsisa64r6-unknown-linux-gnuabi64
+//@ [MIPS64] needs-llvm-components: mips
 //@ [MIPS64EL] compile-flags: -Copt-level=3 --target mips64el-unknown-linux-gnuabi64
-//@ needs-llvm-components: mips
+//@ [MIPS64EL] needs-llvm-components: mips
 #![feature(c_variadic, no_core, lang_items, intrinsics, rustc_attrs, asm_experimental_arch)]
 #![no_core]
 #![crate_type = "lib"]
@@ -88,9 +90,9 @@ pub struct VaList<'a> {
     // MIPS64EL: ld  $1, 0($4)
     // MIPS64EL-NEXT: daddiu  $2, $1, 8
     // MIPS64EL-NEXT: sd  $2, 0($4)
-    // MIPS64EL-NEXT: lw  $1, 0($1)
+    // MIPS64EL-NEXT: lw  $2, 0($1)
     // MIPS64EL-NEXT: jr  $ra
-    // MIPS64EL-NEXT: sll $2, $1, 0
+    // MIPS64EL-NEXT: nop
     va_arg(ap)
 }
 
@@ -99,17 +101,15 @@ pub struct VaList<'a> {
     // CHECK-LABEL: read_i64
     //
     // MIPS: lw  $1, 0($4)
-    // MIPS-NEXT: addiu   $2, $zero, 4
-    // MIPS-NEXT: addiu   $1, $1, 7
-    // MIPS-NEXT: move    $3, $1
-    // MIPS-NEXT: ins $3, $2, 0, 3
     // MIPS-NEXT: addiu   $2, $zero, -8
+    // MIPS-NEXT: addiu   $1, $1, 7
+    // MIPS-NEXT: and $2, $1, $2
+    // MIPS-NEXT: addiu   $3, $2, 8
     // MIPS-NEXT: sw  $3, 0($4)
-    // MIPS-NEXT: and $1, $1, $2
-    // MIPS-NEXT: lw  $2, 0($1)
-    // MIPS-NEXT: addiu   $1, $3, 4
-    // MIPS-NEXT: sw  $1, 0($4)
-    // MIPS-NEXT: lw  $3, 0($3)
+    // MIPS-NEXT: addiu   $3, $zero, 4
+    // MIPS-NEXT: lw  $2, 0($2)
+    // MIPS-NEXT: ins $1, $3, 0, 3
+    // MIPS-NEXT: lw  $3, 0($1)
     // MIPS-NEXT: jr  $ra
     // MIPS-NEXT: nop
     //